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chisel-verilog-pairs

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Generate the Verilog code corresponding to this FIRRTL code module MSHR_51 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_51( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_22 : input clock : Clock input reset : Reset output auto : { } skip
module TLBuffer_22( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset // @[Buffer.scala:40:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_312 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_56 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_312( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_56 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ICache_1 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s2_vaddr : UInt<39>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s2_cacheable : UInt<1>, flip s2_prefetch : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<32>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, perf : { acquire : UInt<1>}, flip clock_enabled : UInt<1>, keep_clock_enabled : UInt<1>} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut regreset scratchpadOn : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) connect s1_slaveValid, UInt<1>(0h0) regreset s2_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_slaveValid, s1_slaveValid reg s3_slaveValid : UInt<1>, clock connect s3_slaveValid, UInt<1>(0h0) node s0_valid = and(io.req.ready, io.req.valid) regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg s1_vaddr : UInt<39>, clock when s0_valid : connect s1_vaddr, io.req.bits.addr wire s1_tag_hit : UInt<1>[8] node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1]) node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2]) node _s1_hit_T_2 = or(_s1_hit_T_1, s1_tag_hit[3]) node _s1_hit_T_3 = or(_s1_hit_T_2, s1_tag_hit[4]) node _s1_hit_T_4 = or(_s1_hit_T_3, s1_tag_hit[5]) node _s1_hit_T_5 = or(_s1_hit_T_4, s1_tag_hit[6]) node _s1_hit_T_6 = or(_s1_hit_T_5, s1_tag_hit[7]) node _s1_hit_T_7 = mux(s1_slaveValid, UInt<1>(0h1), UInt<1>(0h0)) node s1_hit = or(_s1_hit_T_6, _s1_hit_T_7) node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_hit : UInt<1>, clock connect s2_hit, s1_hit reg invalidated : UInt<1>, clock regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0) node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0)) node refill_fire = and(_refill_fire_T, _refill_fire_T_1) regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0) node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0)) node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) node _s1_can_request_refill_T = or(s2_miss, refill_valid) node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0)) reg s2_request_refill_REG : UInt<1>, clock connect s2_request_refill_REG, s1_can_request_refill node s2_request_refill = and(s2_miss, s2_request_refill_REG) node _refill_paddr_T = and(s1_valid, s1_can_request_refill) reg refill_paddr : UInt<32>, clock when _refill_paddr_T : connect refill_paddr, io.s1_paddr node _refill_vaddr_T = and(s1_valid, s1_can_request_refill) reg refill_vaddr : UInt<39>, clock when _refill_vaddr_T : connect refill_vaddr, s1_vaddr node refill_tag = shr(refill_paddr, 12) node refill_idx = bits(refill_paddr, 11, 6) node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) node _io_req_ready_T = or(refill_one_beat, UInt<1>(0h0)) node _io_req_ready_T_1 = or(_io_req_ready_T, s3_slaveValid) node _io_req_ready_T_2 = eq(_io_req_ready_T_1, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T_2 connect s1_valid, s0_valid node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node d_done = and(r_2, _T) node _r_count_T = not(r_counter1) node refill_cnt = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_done = and(refill_one_beat, d_done) node _masterNodeOut_d_ready_T = eq(s3_slaveValid, UInt<1>(0h0)) connect masterNodeOut.d.ready, _masterNodeOut_d_ready_T inst repl_way_v0_prng of MaxPeriodFibonacciLFSR_4 connect repl_way_v0_prng.clock, clock connect repl_way_v0_prng.reset, reset connect repl_way_v0_prng.io.seed.valid, UInt<1>(0h0) invalidate repl_way_v0_prng.io.seed.bits[0] invalidate repl_way_v0_prng.io.seed.bits[1] invalidate repl_way_v0_prng.io.seed.bits[2] invalidate repl_way_v0_prng.io.seed.bits[3] invalidate repl_way_v0_prng.io.seed.bits[4] invalidate repl_way_v0_prng.io.seed.bits[5] invalidate repl_way_v0_prng.io.seed.bits[6] invalidate repl_way_v0_prng.io.seed.bits[7] invalidate repl_way_v0_prng.io.seed.bits[8] invalidate repl_way_v0_prng.io.seed.bits[9] invalidate repl_way_v0_prng.io.seed.bits[10] invalidate repl_way_v0_prng.io.seed.bits[11] invalidate repl_way_v0_prng.io.seed.bits[12] invalidate repl_way_v0_prng.io.seed.bits[13] invalidate repl_way_v0_prng.io.seed.bits[14] invalidate repl_way_v0_prng.io.seed.bits[15] connect repl_way_v0_prng.io.increment, refill_fire node repl_way_v0_lo_lo_lo = cat(repl_way_v0_prng.io.out[1], repl_way_v0_prng.io.out[0]) node repl_way_v0_lo_lo_hi = cat(repl_way_v0_prng.io.out[3], repl_way_v0_prng.io.out[2]) node repl_way_v0_lo_lo = cat(repl_way_v0_lo_lo_hi, repl_way_v0_lo_lo_lo) node repl_way_v0_lo_hi_lo = cat(repl_way_v0_prng.io.out[5], repl_way_v0_prng.io.out[4]) node repl_way_v0_lo_hi_hi = cat(repl_way_v0_prng.io.out[7], repl_way_v0_prng.io.out[6]) node repl_way_v0_lo_hi = cat(repl_way_v0_lo_hi_hi, repl_way_v0_lo_hi_lo) node repl_way_v0_lo = cat(repl_way_v0_lo_hi, repl_way_v0_lo_lo) node repl_way_v0_hi_lo_lo = cat(repl_way_v0_prng.io.out[9], repl_way_v0_prng.io.out[8]) node repl_way_v0_hi_lo_hi = cat(repl_way_v0_prng.io.out[11], repl_way_v0_prng.io.out[10]) node repl_way_v0_hi_lo = cat(repl_way_v0_hi_lo_hi, repl_way_v0_hi_lo_lo) node repl_way_v0_hi_hi_lo = cat(repl_way_v0_prng.io.out[13], repl_way_v0_prng.io.out[12]) node repl_way_v0_hi_hi_hi = cat(repl_way_v0_prng.io.out[15], repl_way_v0_prng.io.out[14]) node repl_way_v0_hi_hi = cat(repl_way_v0_hi_hi_hi, repl_way_v0_hi_hi_lo) node repl_way_v0_hi = cat(repl_way_v0_hi_hi, repl_way_v0_hi_lo) node _repl_way_v0_T = cat(repl_way_v0_hi, repl_way_v0_lo) node repl_way_v0 = bits(_repl_way_v0_T, 2, 0) node _repl_way_T = or(repl_way_v0, UInt<1>(0h0)) node _repl_way_T_1 = cat(_repl_way_T, refill_idx) node _repl_way_T_2 = shl(UInt<1>(0h0), 2) node _repl_way_T_3 = or(repl_way_v0, _repl_way_T_2) node _repl_way_T_4 = or(repl_way_v0, UInt<3>(0h4)) node _repl_way_T_5 = cat(_repl_way_T_4, refill_idx) node _repl_way_T_6 = shl(UInt<1>(0h0), 1) node _repl_way_T_7 = or(_repl_way_T_3, _repl_way_T_6) node _repl_way_T_8 = or(repl_way_v0, UInt<3>(0h6)) node _repl_way_T_9 = cat(_repl_way_T_8, refill_idx) node _repl_way_T_10 = shl(UInt<1>(0h0), 0) node repl_way = or(_repl_way_T_7, _repl_way_T_10) node _repl_way_T_11 = cat(repl_way, refill_idx) node _repl_way_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _repl_way_T_13 = asUInt(reset) node _repl_way_T_14 = eq(_repl_way_T_13, UInt<1>(0h0)) when _repl_way_T_14 : node _repl_way_T_15 = eq(_repl_way_T_12, UInt<1>(0h0)) when _repl_way_T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:413 assert(!lineInScratchpad(Cat(v, refill_idx)))\n") : repl_way_printf assert(clock, _repl_way_T_12, UInt<1>(0h1), "") : repl_way_assert smem rockettile_icache_tag_array : UInt<21>[8] [64] node _tag_rdata_T = bits(io.req.bits.addr, 11, 6) node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) wire _tag_rdata_WIRE : UInt<6> invalidate _tag_rdata_WIRE when _tag_rdata_T_2 : connect _tag_rdata_WIRE, _tag_rdata_T read mport tag_rdata = rockettile_icache_tag_array[_tag_rdata_WIRE], clock reg accruedRefillError : UInt<1>, clock node _refillError_T = gt(refill_cnt, UInt<1>(0h0)) node _refillError_T_1 = and(_refillError_T, accruedRefillError) node refillError = or(masterNodeOut.d.bits.corrupt, _refillError_T_1) when refill_done : node enc_tag = cat(refillError, refill_tag) wire _WIRE : UInt<21>[8] connect _WIRE[0], enc_tag connect _WIRE[1], enc_tag connect _WIRE[2], enc_tag connect _WIRE[3], enc_tag connect _WIRE[4], enc_tag connect _WIRE[5], enc_tag connect _WIRE[6], enc_tag connect _WIRE[7], enc_tag node _T_1 = eq(repl_way, UInt<1>(0h0)) node _T_2 = eq(repl_way, UInt<1>(0h1)) node _T_3 = eq(repl_way, UInt<2>(0h2)) node _T_4 = eq(repl_way, UInt<2>(0h3)) node _T_5 = eq(repl_way, UInt<3>(0h4)) node _T_6 = eq(repl_way, UInt<3>(0h5)) node _T_7 = eq(repl_way, UInt<3>(0h6)) node _T_8 = eq(repl_way, UInt<3>(0h7)) write mport MPORT = rockettile_icache_tag_array[refill_idx], clock when _T_1 : connect MPORT[0], _WIRE[0] when _T_2 : connect MPORT[1], _WIRE[1] when _T_3 : connect MPORT[2], _WIRE[2] when _T_4 : connect MPORT[3], _WIRE[3] when _T_5 : connect MPORT[4], _WIRE[4] when _T_6 : connect MPORT[5], _WIRE[5] when _T_7 : connect MPORT[6], _WIRE[6] when _T_8 : connect MPORT[7], _WIRE[7] node _io_errors_bus_valid_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _io_errors_bus_valid_T_1 = or(masterNodeOut.d.bits.denied, masterNodeOut.d.bits.corrupt) node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1) connect io.errors.bus.valid, _io_errors_bus_valid_T_2 node _io_errors_bus_bits_T = shr(refill_paddr, 6) node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6) connect io.errors.bus.bits, _io_errors_bus_bits_T_1 regreset vb_array : UInt<512>, clock, reset, UInt<512>(0h0) when refill_one_beat : connect accruedRefillError, refillError node _vb_array_T = cat(repl_way, refill_idx) node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) node _vb_array_T_2 = and(refill_done, _vb_array_T_1) node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) node _vb_array_T_4 = or(vb_array, _vb_array_T_3) node _vb_array_T_5 = not(vb_array) node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) node _vb_array_T_7 = not(_vb_array_T_6) node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) connect vb_array, _vb_array_T_8 wire invalidate : UInt<1> connect invalidate, io.invalidate when invalidate : connect vb_array, UInt<1>(0h0) connect invalidated, UInt<1>(0h1) wire s1_tag_disparity : UInt<1>[8] wire s1_tl_error : UInt<1>[8] wire s1_dout : UInt<32>[8] invalidate s1_dout[0] invalidate s1_dout[1] invalidate s1_dout[2] invalidate s1_dout[3] invalidate s1_dout[4] invalidate s1_dout[5] invalidate s1_dout[6] invalidate s1_dout[7] reg s1s3_slaveAddr : UInt<15>, clock reg s1s3_slaveData : UInt<32>, clock node s1_idx = bits(io.s1_paddr, 11, 6) node s1_tag = shr(io.s1_paddr, 12) node _scratchpadHit_T = lt(UInt<1>(0h0), UInt<3>(0h7)) node _scratchpadHit_T_1 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_2 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_3 = eq(_scratchpadHit_T_2, UInt<1>(0h0)) node _scratchpadHit_T_4 = and(UInt<1>(0h0), _scratchpadHit_T_3) node _scratchpadHit_T_5 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_6 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_7 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_8 = eq(_scratchpadHit_T_7, UInt<1>(0h0)) node _scratchpadHit_T_9 = and(_scratchpadHit_T_6, _scratchpadHit_T_8) node _scratchpadHit_T_10 = mux(s1_slaveValid, _scratchpadHit_T_4, _scratchpadHit_T_9) node scratchpadHit = and(_scratchpadHit_T, _scratchpadHit_T_10) node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) node _s1_vb_T_1 = pad(_s1_vb_T, 9) node _s1_vb_T_2 = dshr(vb_array, _s1_vb_T_1) node _s1_vb_T_3 = bits(_s1_vb_T_2, 0, 0) node _s1_vb_T_4 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb = and(_s1_vb_T_3, _s1_vb_T_4) node tl_error = bits(tag_rdata[0], 20, 20) node tag = bits(tag_rdata[0], 19, 0) node _tagMatch_T = eq(tag, s1_tag) node tagMatch = and(s1_vb, _tagMatch_T) node _s1_tag_disparity_0_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_0_T_1 = and(s1_vb, _s1_tag_disparity_0_T) connect s1_tag_disparity[0], _s1_tag_disparity_0_T_1 node _s1_tl_error_0_T = bits(tl_error, 0, 0) node _s1_tl_error_0_T_1 = and(tagMatch, _s1_tl_error_0_T) connect s1_tl_error[0], _s1_tl_error_0_T_1 node _s1_tag_hit_0_T = or(tagMatch, scratchpadHit) connect s1_tag_hit[0], _s1_tag_hit_0_T node s1_idx_1 = bits(io.s1_paddr, 11, 6) node s1_tag_1 = shr(io.s1_paddr, 12) node _scratchpadHit_T_11 = lt(UInt<1>(0h1), UInt<3>(0h7)) node _scratchpadHit_T_12 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_13 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_14 = eq(_scratchpadHit_T_13, UInt<1>(0h1)) node _scratchpadHit_T_15 = and(UInt<1>(0h0), _scratchpadHit_T_14) node _scratchpadHit_T_16 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_17 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_18 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_19 = eq(_scratchpadHit_T_18, UInt<1>(0h1)) node _scratchpadHit_T_20 = and(_scratchpadHit_T_17, _scratchpadHit_T_19) node _scratchpadHit_T_21 = mux(s1_slaveValid, _scratchpadHit_T_15, _scratchpadHit_T_20) node scratchpadHit_1 = and(_scratchpadHit_T_11, _scratchpadHit_T_21) node _s1_vb_T_5 = cat(UInt<1>(0h1), s1_idx_1) node _s1_vb_T_6 = pad(_s1_vb_T_5, 9) node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6) node _s1_vb_T_8 = bits(_s1_vb_T_7, 0, 0) node _s1_vb_T_9 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_1 = and(_s1_vb_T_8, _s1_vb_T_9) node tl_error_1 = bits(tag_rdata[1], 20, 20) node tag_1 = bits(tag_rdata[1], 19, 0) node _tagMatch_T_1 = eq(tag_1, s1_tag_1) node tagMatch_1 = and(s1_vb_1, _tagMatch_T_1) node _s1_tag_disparity_1_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_1_T_1 = and(s1_vb_1, _s1_tag_disparity_1_T) connect s1_tag_disparity[1], _s1_tag_disparity_1_T_1 node _s1_tl_error_1_T = bits(tl_error_1, 0, 0) node _s1_tl_error_1_T_1 = and(tagMatch_1, _s1_tl_error_1_T) connect s1_tl_error[1], _s1_tl_error_1_T_1 node _s1_tag_hit_1_T = or(tagMatch_1, scratchpadHit_1) connect s1_tag_hit[1], _s1_tag_hit_1_T node s1_idx_2 = bits(io.s1_paddr, 11, 6) node s1_tag_2 = shr(io.s1_paddr, 12) node _scratchpadHit_T_22 = lt(UInt<2>(0h2), UInt<3>(0h7)) node _scratchpadHit_T_23 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_24 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_25 = eq(_scratchpadHit_T_24, UInt<2>(0h2)) node _scratchpadHit_T_26 = and(UInt<1>(0h0), _scratchpadHit_T_25) node _scratchpadHit_T_27 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_28 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_29 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_30 = eq(_scratchpadHit_T_29, UInt<2>(0h2)) node _scratchpadHit_T_31 = and(_scratchpadHit_T_28, _scratchpadHit_T_30) node _scratchpadHit_T_32 = mux(s1_slaveValid, _scratchpadHit_T_26, _scratchpadHit_T_31) node scratchpadHit_2 = and(_scratchpadHit_T_22, _scratchpadHit_T_32) node _s1_vb_T_10 = cat(UInt<2>(0h2), s1_idx_2) node _s1_vb_T_11 = pad(_s1_vb_T_10, 9) node _s1_vb_T_12 = dshr(vb_array, _s1_vb_T_11) node _s1_vb_T_13 = bits(_s1_vb_T_12, 0, 0) node _s1_vb_T_14 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_2 = and(_s1_vb_T_13, _s1_vb_T_14) node tl_error_2 = bits(tag_rdata[2], 20, 20) node tag_2 = bits(tag_rdata[2], 19, 0) node _tagMatch_T_2 = eq(tag_2, s1_tag_2) node tagMatch_2 = and(s1_vb_2, _tagMatch_T_2) node _s1_tag_disparity_2_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_2_T_1 = and(s1_vb_2, _s1_tag_disparity_2_T) connect s1_tag_disparity[2], _s1_tag_disparity_2_T_1 node _s1_tl_error_2_T = bits(tl_error_2, 0, 0) node _s1_tl_error_2_T_1 = and(tagMatch_2, _s1_tl_error_2_T) connect s1_tl_error[2], _s1_tl_error_2_T_1 node _s1_tag_hit_2_T = or(tagMatch_2, scratchpadHit_2) connect s1_tag_hit[2], _s1_tag_hit_2_T node s1_idx_3 = bits(io.s1_paddr, 11, 6) node s1_tag_3 = shr(io.s1_paddr, 12) node _scratchpadHit_T_33 = lt(UInt<2>(0h3), UInt<3>(0h7)) node _scratchpadHit_T_34 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_35 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_36 = eq(_scratchpadHit_T_35, UInt<2>(0h3)) node _scratchpadHit_T_37 = and(UInt<1>(0h0), _scratchpadHit_T_36) node _scratchpadHit_T_38 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_39 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_40 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_41 = eq(_scratchpadHit_T_40, UInt<2>(0h3)) node _scratchpadHit_T_42 = and(_scratchpadHit_T_39, _scratchpadHit_T_41) node _scratchpadHit_T_43 = mux(s1_slaveValid, _scratchpadHit_T_37, _scratchpadHit_T_42) node scratchpadHit_3 = and(_scratchpadHit_T_33, _scratchpadHit_T_43) node _s1_vb_T_15 = cat(UInt<2>(0h3), s1_idx_3) node _s1_vb_T_16 = pad(_s1_vb_T_15, 9) node _s1_vb_T_17 = dshr(vb_array, _s1_vb_T_16) node _s1_vb_T_18 = bits(_s1_vb_T_17, 0, 0) node _s1_vb_T_19 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_3 = and(_s1_vb_T_18, _s1_vb_T_19) node tl_error_3 = bits(tag_rdata[3], 20, 20) node tag_3 = bits(tag_rdata[3], 19, 0) node _tagMatch_T_3 = eq(tag_3, s1_tag_3) node tagMatch_3 = and(s1_vb_3, _tagMatch_T_3) node _s1_tag_disparity_3_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_3_T_1 = and(s1_vb_3, _s1_tag_disparity_3_T) connect s1_tag_disparity[3], _s1_tag_disparity_3_T_1 node _s1_tl_error_3_T = bits(tl_error_3, 0, 0) node _s1_tl_error_3_T_1 = and(tagMatch_3, _s1_tl_error_3_T) connect s1_tl_error[3], _s1_tl_error_3_T_1 node _s1_tag_hit_3_T = or(tagMatch_3, scratchpadHit_3) connect s1_tag_hit[3], _s1_tag_hit_3_T node s1_idx_4 = bits(io.s1_paddr, 11, 6) node s1_tag_4 = shr(io.s1_paddr, 12) node _scratchpadHit_T_44 = lt(UInt<3>(0h4), UInt<3>(0h7)) node _scratchpadHit_T_45 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_46 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_47 = eq(_scratchpadHit_T_46, UInt<3>(0h4)) node _scratchpadHit_T_48 = and(UInt<1>(0h0), _scratchpadHit_T_47) node _scratchpadHit_T_49 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_50 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_51 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_52 = eq(_scratchpadHit_T_51, UInt<3>(0h4)) node _scratchpadHit_T_53 = and(_scratchpadHit_T_50, _scratchpadHit_T_52) node _scratchpadHit_T_54 = mux(s1_slaveValid, _scratchpadHit_T_48, _scratchpadHit_T_53) node scratchpadHit_4 = and(_scratchpadHit_T_44, _scratchpadHit_T_54) node _s1_vb_T_20 = cat(UInt<3>(0h4), s1_idx_4) node _s1_vb_T_21 = dshr(vb_array, _s1_vb_T_20) node _s1_vb_T_22 = bits(_s1_vb_T_21, 0, 0) node _s1_vb_T_23 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_4 = and(_s1_vb_T_22, _s1_vb_T_23) node tl_error_4 = bits(tag_rdata[4], 20, 20) node tag_4 = bits(tag_rdata[4], 19, 0) node _tagMatch_T_4 = eq(tag_4, s1_tag_4) node tagMatch_4 = and(s1_vb_4, _tagMatch_T_4) node _s1_tag_disparity_4_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_4_T_1 = and(s1_vb_4, _s1_tag_disparity_4_T) connect s1_tag_disparity[4], _s1_tag_disparity_4_T_1 node _s1_tl_error_4_T = bits(tl_error_4, 0, 0) node _s1_tl_error_4_T_1 = and(tagMatch_4, _s1_tl_error_4_T) connect s1_tl_error[4], _s1_tl_error_4_T_1 node _s1_tag_hit_4_T = or(tagMatch_4, scratchpadHit_4) connect s1_tag_hit[4], _s1_tag_hit_4_T node s1_idx_5 = bits(io.s1_paddr, 11, 6) node s1_tag_5 = shr(io.s1_paddr, 12) node _scratchpadHit_T_55 = lt(UInt<3>(0h5), UInt<3>(0h7)) node _scratchpadHit_T_56 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_57 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_58 = eq(_scratchpadHit_T_57, UInt<3>(0h5)) node _scratchpadHit_T_59 = and(UInt<1>(0h0), _scratchpadHit_T_58) node _scratchpadHit_T_60 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_61 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_62 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_63 = eq(_scratchpadHit_T_62, UInt<3>(0h5)) node _scratchpadHit_T_64 = and(_scratchpadHit_T_61, _scratchpadHit_T_63) node _scratchpadHit_T_65 = mux(s1_slaveValid, _scratchpadHit_T_59, _scratchpadHit_T_64) node scratchpadHit_5 = and(_scratchpadHit_T_55, _scratchpadHit_T_65) node _s1_vb_T_24 = cat(UInt<3>(0h5), s1_idx_5) node _s1_vb_T_25 = dshr(vb_array, _s1_vb_T_24) node _s1_vb_T_26 = bits(_s1_vb_T_25, 0, 0) node _s1_vb_T_27 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_5 = and(_s1_vb_T_26, _s1_vb_T_27) node tl_error_5 = bits(tag_rdata[5], 20, 20) node tag_5 = bits(tag_rdata[5], 19, 0) node _tagMatch_T_5 = eq(tag_5, s1_tag_5) node tagMatch_5 = and(s1_vb_5, _tagMatch_T_5) node _s1_tag_disparity_5_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_5_T_1 = and(s1_vb_5, _s1_tag_disparity_5_T) connect s1_tag_disparity[5], _s1_tag_disparity_5_T_1 node _s1_tl_error_5_T = bits(tl_error_5, 0, 0) node _s1_tl_error_5_T_1 = and(tagMatch_5, _s1_tl_error_5_T) connect s1_tl_error[5], _s1_tl_error_5_T_1 node _s1_tag_hit_5_T = or(tagMatch_5, scratchpadHit_5) connect s1_tag_hit[5], _s1_tag_hit_5_T node s1_idx_6 = bits(io.s1_paddr, 11, 6) node s1_tag_6 = shr(io.s1_paddr, 12) node _scratchpadHit_T_66 = lt(UInt<3>(0h6), UInt<3>(0h7)) node _scratchpadHit_T_67 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_68 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_69 = eq(_scratchpadHit_T_68, UInt<3>(0h6)) node _scratchpadHit_T_70 = and(UInt<1>(0h0), _scratchpadHit_T_69) node _scratchpadHit_T_71 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_72 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_73 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_74 = eq(_scratchpadHit_T_73, UInt<3>(0h6)) node _scratchpadHit_T_75 = and(_scratchpadHit_T_72, _scratchpadHit_T_74) node _scratchpadHit_T_76 = mux(s1_slaveValid, _scratchpadHit_T_70, _scratchpadHit_T_75) node scratchpadHit_6 = and(_scratchpadHit_T_66, _scratchpadHit_T_76) node _s1_vb_T_28 = cat(UInt<3>(0h6), s1_idx_6) node _s1_vb_T_29 = dshr(vb_array, _s1_vb_T_28) node _s1_vb_T_30 = bits(_s1_vb_T_29, 0, 0) node _s1_vb_T_31 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_6 = and(_s1_vb_T_30, _s1_vb_T_31) node tl_error_6 = bits(tag_rdata[6], 20, 20) node tag_6 = bits(tag_rdata[6], 19, 0) node _tagMatch_T_6 = eq(tag_6, s1_tag_6) node tagMatch_6 = and(s1_vb_6, _tagMatch_T_6) node _s1_tag_disparity_6_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_6_T_1 = and(s1_vb_6, _s1_tag_disparity_6_T) connect s1_tag_disparity[6], _s1_tag_disparity_6_T_1 node _s1_tl_error_6_T = bits(tl_error_6, 0, 0) node _s1_tl_error_6_T_1 = and(tagMatch_6, _s1_tl_error_6_T) connect s1_tl_error[6], _s1_tl_error_6_T_1 node _s1_tag_hit_6_T = or(tagMatch_6, scratchpadHit_6) connect s1_tag_hit[6], _s1_tag_hit_6_T node s1_idx_7 = bits(io.s1_paddr, 11, 6) node s1_tag_7 = shr(io.s1_paddr, 12) node _scratchpadHit_T_77 = lt(UInt<3>(0h7), UInt<3>(0h7)) node _scratchpadHit_T_78 = bits(s1s3_slaveAddr, 14, 6) node _scratchpadHit_T_79 = bits(s1s3_slaveAddr, 14, 12) node _scratchpadHit_T_80 = eq(_scratchpadHit_T_79, UInt<3>(0h7)) node _scratchpadHit_T_81 = and(UInt<1>(0h0), _scratchpadHit_T_80) node _scratchpadHit_T_82 = bits(io.s1_paddr, 14, 6) node _scratchpadHit_T_83 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_84 = bits(io.s1_paddr, 14, 12) node _scratchpadHit_T_85 = eq(_scratchpadHit_T_84, UInt<3>(0h7)) node _scratchpadHit_T_86 = and(_scratchpadHit_T_83, _scratchpadHit_T_85) node _scratchpadHit_T_87 = mux(s1_slaveValid, _scratchpadHit_T_81, _scratchpadHit_T_86) node scratchpadHit_7 = and(_scratchpadHit_T_77, _scratchpadHit_T_87) node _s1_vb_T_32 = cat(UInt<3>(0h7), s1_idx_7) node _s1_vb_T_33 = dshr(vb_array, _s1_vb_T_32) node _s1_vb_T_34 = bits(_s1_vb_T_33, 0, 0) node _s1_vb_T_35 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb_7 = and(_s1_vb_T_34, _s1_vb_T_35) node tl_error_7 = bits(tag_rdata[7], 20, 20) node tag_7 = bits(tag_rdata[7], 19, 0) node _tagMatch_T_7 = eq(tag_7, s1_tag_7) node tagMatch_7 = and(s1_vb_7, _tagMatch_T_7) node _s1_tag_disparity_7_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_7_T_1 = and(s1_vb_7, _s1_tag_disparity_7_T) connect s1_tag_disparity[7], _s1_tag_disparity_7_T_1 node _s1_tl_error_7_T = bits(tl_error_7, 0, 0) node _s1_tl_error_7_T_1 = and(tagMatch_7, _s1_tl_error_7_T) connect s1_tl_error[7], _s1_tl_error_7_T_1 node _s1_tag_hit_7_T = or(tagMatch_7, scratchpadHit_7) connect s1_tag_hit[7], _s1_tag_hit_7_T node _T_9 = or(s1_valid, s1_slaveValid) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = eq(s1_tag_disparity[0], UInt<1>(0h0)) node _T_12 = and(s1_tag_hit[0], _T_11) node _T_13 = eq(s1_tag_disparity[1], UInt<1>(0h0)) node _T_14 = and(s1_tag_hit[1], _T_13) node _T_15 = eq(s1_tag_disparity[2], UInt<1>(0h0)) node _T_16 = and(s1_tag_hit[2], _T_15) node _T_17 = eq(s1_tag_disparity[3], UInt<1>(0h0)) node _T_18 = and(s1_tag_hit[3], _T_17) node _T_19 = eq(s1_tag_disparity[4], UInt<1>(0h0)) node _T_20 = and(s1_tag_hit[4], _T_19) node _T_21 = eq(s1_tag_disparity[5], UInt<1>(0h0)) node _T_22 = and(s1_tag_hit[5], _T_21) node _T_23 = eq(s1_tag_disparity[6], UInt<1>(0h0)) node _T_24 = and(s1_tag_hit[6], _T_23) node _T_25 = eq(s1_tag_disparity[7], UInt<1>(0h0)) node _T_26 = and(s1_tag_hit[7], _T_25) node _T_27 = add(_T_12, _T_14) node _T_28 = bits(_T_27, 1, 0) node _T_29 = add(_T_16, _T_18) node _T_30 = bits(_T_29, 1, 0) node _T_31 = add(_T_28, _T_30) node _T_32 = bits(_T_31, 2, 0) node _T_33 = add(_T_20, _T_22) node _T_34 = bits(_T_33, 1, 0) node _T_35 = add(_T_24, _T_26) node _T_36 = bits(_T_35, 1, 0) node _T_37 = add(_T_34, _T_36) node _T_38 = bits(_T_37, 2, 0) node _T_39 = add(_T_32, _T_38) node _T_40 = bits(_T_39, 3, 0) node _T_41 = leq(_T_40, UInt<1>(0h1)) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:521 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U)\n") : printf assert(clock, _T_42, UInt<1>(0h1), "") : assert smem rockettile_icache_data_arrays_0 : UInt<32>[8] [256] smem rockettile_icache_data_arrays_1 : UInt<32>[8] [256] smem rockettile_icache_data_arrays_2 : UInt<32>[8] [256] smem rockettile_icache_data_arrays_3 : UInt<32>[8] [256] node _s0_ren_T = bits(io.req.bits.addr, 3, 2) node _s0_ren_T_1 = eq(_s0_ren_T, UInt<1>(0h0)) node _s0_ren_T_2 = and(s0_valid, _s0_ren_T_1) node _s0_ren_T_3 = eq(UInt<2>(0h0), UInt<1>(0h0)) node _s0_ren_T_4 = and(UInt<1>(0h0), _s0_ren_T_3) node s0_ren = or(_s0_ren_T_2, _s0_ren_T_4) node _wen_T = eq(invalidated, UInt<1>(0h0)) node _wen_T_1 = and(refill_one_beat, _wen_T) node _wen_T_2 = bits(s1s3_slaveAddr, 3, 2) node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0)) node _wen_T_4 = and(s3_slaveValid, _wen_T_3) node wen = or(_wen_T_1, _wen_T_4) node _mem_idx_T = shl(refill_idx, 2) node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt) node _mem_idx_T_2 = bits(s1s3_slaveAddr, 11, 4) node _mem_idx_T_3 = bits(io.req.bits.addr, 11, 4) node _mem_idx_T_4 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_3) node _mem_idx_T_5 = mux(s3_slaveValid, _mem_idx_T_2, _mem_idx_T_4) node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_5) when wen : node _data_T = bits(masterNodeOut.d.bits.data, 31, 0) node data = mux(s3_slaveValid, s1s3_slaveData, _data_T) node _way_T = bits(s1s3_slaveAddr, 14, 12) node way = mux(s3_slaveValid, _way_T, repl_way) wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], data connect _WIRE_1[1], data connect _WIRE_1[2], data connect _WIRE_1[3], data connect _WIRE_1[4], data connect _WIRE_1[5], data connect _WIRE_1[6], data connect _WIRE_1[7], data node _T_46 = eq(way, UInt<1>(0h0)) node _T_47 = eq(way, UInt<1>(0h1)) node _T_48 = eq(way, UInt<2>(0h2)) node _T_49 = eq(way, UInt<2>(0h3)) node _T_50 = eq(way, UInt<3>(0h4)) node _T_51 = eq(way, UInt<3>(0h5)) node _T_52 = eq(way, UInt<3>(0h6)) node _T_53 = eq(way, UInt<3>(0h7)) write mport MPORT_1 = rockettile_icache_data_arrays_0[mem_idx], clock when _T_46 : connect MPORT_1[0], _WIRE_1[0] when _T_47 : connect MPORT_1[1], _WIRE_1[1] when _T_48 : connect MPORT_1[2], _WIRE_1[2] when _T_49 : connect MPORT_1[3], _WIRE_1[3] when _T_50 : connect MPORT_1[4], _WIRE_1[4] when _T_51 : connect MPORT_1[5], _WIRE_1[5] when _T_52 : connect MPORT_1[6], _WIRE_1[6] when _T_53 : connect MPORT_1[7], _WIRE_1[7] node _dout_T = eq(wen, UInt<1>(0h0)) node _dout_T_1 = and(_dout_T, s0_ren) wire _dout_WIRE : UInt<8> invalidate _dout_WIRE when _dout_T_1 : connect _dout_WIRE, mem_idx read mport dout = rockettile_icache_data_arrays_0[_dout_WIRE], clock node _T_54 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_55 = bits(_T_54, 3, 2) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : connect s1_dout, dout node _s0_ren_T_5 = bits(io.req.bits.addr, 3, 2) node _s0_ren_T_6 = eq(_s0_ren_T_5, UInt<1>(0h1)) node _s0_ren_T_7 = and(s0_valid, _s0_ren_T_6) node _s0_ren_T_8 = eq(UInt<2>(0h0), UInt<1>(0h1)) node _s0_ren_T_9 = and(UInt<1>(0h0), _s0_ren_T_8) node s0_ren_1 = or(_s0_ren_T_7, _s0_ren_T_9) node _wen_T_5 = eq(invalidated, UInt<1>(0h0)) node _wen_T_6 = and(refill_one_beat, _wen_T_5) node _wen_T_7 = bits(s1s3_slaveAddr, 3, 2) node _wen_T_8 = eq(_wen_T_7, UInt<1>(0h1)) node _wen_T_9 = and(s3_slaveValid, _wen_T_8) node wen_1 = or(_wen_T_6, _wen_T_9) node _mem_idx_T_6 = shl(refill_idx, 2) node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt) node _mem_idx_T_8 = bits(s1s3_slaveAddr, 11, 4) node _mem_idx_T_9 = bits(io.req.bits.addr, 11, 4) node _mem_idx_T_10 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_9) node _mem_idx_T_11 = mux(s3_slaveValid, _mem_idx_T_8, _mem_idx_T_10) node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_11) when wen_1 : node _data_T_1 = bits(masterNodeOut.d.bits.data, 63, 32) node data_1 = mux(s3_slaveValid, s1s3_slaveData, _data_T_1) node _way_T_1 = bits(s1s3_slaveAddr, 14, 12) node way_1 = mux(s3_slaveValid, _way_T_1, repl_way) wire _WIRE_2 : UInt<32>[8] connect _WIRE_2[0], data_1 connect _WIRE_2[1], data_1 connect _WIRE_2[2], data_1 connect _WIRE_2[3], data_1 connect _WIRE_2[4], data_1 connect _WIRE_2[5], data_1 connect _WIRE_2[6], data_1 connect _WIRE_2[7], data_1 node _T_57 = eq(way_1, UInt<1>(0h0)) node _T_58 = eq(way_1, UInt<1>(0h1)) node _T_59 = eq(way_1, UInt<2>(0h2)) node _T_60 = eq(way_1, UInt<2>(0h3)) node _T_61 = eq(way_1, UInt<3>(0h4)) node _T_62 = eq(way_1, UInt<3>(0h5)) node _T_63 = eq(way_1, UInt<3>(0h6)) node _T_64 = eq(way_1, UInt<3>(0h7)) write mport MPORT_2 = rockettile_icache_data_arrays_1[mem_idx_1], clock when _T_57 : connect MPORT_2[0], _WIRE_2[0] when _T_58 : connect MPORT_2[1], _WIRE_2[1] when _T_59 : connect MPORT_2[2], _WIRE_2[2] when _T_60 : connect MPORT_2[3], _WIRE_2[3] when _T_61 : connect MPORT_2[4], _WIRE_2[4] when _T_62 : connect MPORT_2[5], _WIRE_2[5] when _T_63 : connect MPORT_2[6], _WIRE_2[6] when _T_64 : connect MPORT_2[7], _WIRE_2[7] node _dout_T_2 = eq(wen_1, UInt<1>(0h0)) node _dout_T_3 = and(_dout_T_2, s0_ren_1) wire _dout_WIRE_1 : UInt<8> invalidate _dout_WIRE_1 when _dout_T_3 : connect _dout_WIRE_1, mem_idx_1 read mport dout_1 = rockettile_icache_data_arrays_1[_dout_WIRE_1], clock node _T_65 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_66 = bits(_T_65, 3, 2) node _T_67 = eq(_T_66, UInt<1>(0h1)) when _T_67 : connect s1_dout, dout_1 node _s0_ren_T_10 = bits(io.req.bits.addr, 3, 2) node _s0_ren_T_11 = eq(_s0_ren_T_10, UInt<2>(0h2)) node _s0_ren_T_12 = and(s0_valid, _s0_ren_T_11) node _s0_ren_T_13 = eq(UInt<2>(0h0), UInt<2>(0h2)) node _s0_ren_T_14 = and(UInt<1>(0h0), _s0_ren_T_13) node s0_ren_2 = or(_s0_ren_T_12, _s0_ren_T_14) node _wen_T_10 = eq(invalidated, UInt<1>(0h0)) node _wen_T_11 = and(refill_one_beat, _wen_T_10) node _wen_T_12 = bits(s1s3_slaveAddr, 3, 2) node _wen_T_13 = eq(_wen_T_12, UInt<2>(0h2)) node _wen_T_14 = and(s3_slaveValid, _wen_T_13) node wen_2 = or(_wen_T_11, _wen_T_14) node _mem_idx_T_12 = shl(refill_idx, 2) node _mem_idx_T_13 = or(_mem_idx_T_12, refill_cnt) node _mem_idx_T_14 = bits(s1s3_slaveAddr, 11, 4) node _mem_idx_T_15 = bits(io.req.bits.addr, 11, 4) node _mem_idx_T_16 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_15) node _mem_idx_T_17 = mux(s3_slaveValid, _mem_idx_T_14, _mem_idx_T_16) node mem_idx_2 = mux(refill_one_beat, _mem_idx_T_13, _mem_idx_T_17) when wen_2 : node _data_T_2 = bits(masterNodeOut.d.bits.data, 95, 64) node data_2 = mux(s3_slaveValid, s1s3_slaveData, _data_T_2) node _way_T_2 = bits(s1s3_slaveAddr, 14, 12) node way_2 = mux(s3_slaveValid, _way_T_2, repl_way) wire _WIRE_3 : UInt<32>[8] connect _WIRE_3[0], data_2 connect _WIRE_3[1], data_2 connect _WIRE_3[2], data_2 connect _WIRE_3[3], data_2 connect _WIRE_3[4], data_2 connect _WIRE_3[5], data_2 connect _WIRE_3[6], data_2 connect _WIRE_3[7], data_2 node _T_68 = eq(way_2, UInt<1>(0h0)) node _T_69 = eq(way_2, UInt<1>(0h1)) node _T_70 = eq(way_2, UInt<2>(0h2)) node _T_71 = eq(way_2, UInt<2>(0h3)) node _T_72 = eq(way_2, UInt<3>(0h4)) node _T_73 = eq(way_2, UInt<3>(0h5)) node _T_74 = eq(way_2, UInt<3>(0h6)) node _T_75 = eq(way_2, UInt<3>(0h7)) write mport MPORT_3 = rockettile_icache_data_arrays_2[mem_idx_2], clock when _T_68 : connect MPORT_3[0], _WIRE_3[0] when _T_69 : connect MPORT_3[1], _WIRE_3[1] when _T_70 : connect MPORT_3[2], _WIRE_3[2] when _T_71 : connect MPORT_3[3], _WIRE_3[3] when _T_72 : connect MPORT_3[4], _WIRE_3[4] when _T_73 : connect MPORT_3[5], _WIRE_3[5] when _T_74 : connect MPORT_3[6], _WIRE_3[6] when _T_75 : connect MPORT_3[7], _WIRE_3[7] node _dout_T_4 = eq(wen_2, UInt<1>(0h0)) node _dout_T_5 = and(_dout_T_4, s0_ren_2) wire _dout_WIRE_2 : UInt<8> invalidate _dout_WIRE_2 when _dout_T_5 : connect _dout_WIRE_2, mem_idx_2 read mport dout_2 = rockettile_icache_data_arrays_2[_dout_WIRE_2], clock node _T_76 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_77 = bits(_T_76, 3, 2) node _T_78 = eq(_T_77, UInt<2>(0h2)) when _T_78 : connect s1_dout, dout_2 node _s0_ren_T_15 = bits(io.req.bits.addr, 3, 2) node _s0_ren_T_16 = eq(_s0_ren_T_15, UInt<2>(0h3)) node _s0_ren_T_17 = and(s0_valid, _s0_ren_T_16) node _s0_ren_T_18 = eq(UInt<2>(0h0), UInt<2>(0h3)) node _s0_ren_T_19 = and(UInt<1>(0h0), _s0_ren_T_18) node s0_ren_3 = or(_s0_ren_T_17, _s0_ren_T_19) node _wen_T_15 = eq(invalidated, UInt<1>(0h0)) node _wen_T_16 = and(refill_one_beat, _wen_T_15) node _wen_T_17 = bits(s1s3_slaveAddr, 3, 2) node _wen_T_18 = eq(_wen_T_17, UInt<2>(0h3)) node _wen_T_19 = and(s3_slaveValid, _wen_T_18) node wen_3 = or(_wen_T_16, _wen_T_19) node _mem_idx_T_18 = shl(refill_idx, 2) node _mem_idx_T_19 = or(_mem_idx_T_18, refill_cnt) node _mem_idx_T_20 = bits(s1s3_slaveAddr, 11, 4) node _mem_idx_T_21 = bits(io.req.bits.addr, 11, 4) node _mem_idx_T_22 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_21) node _mem_idx_T_23 = mux(s3_slaveValid, _mem_idx_T_20, _mem_idx_T_22) node mem_idx_3 = mux(refill_one_beat, _mem_idx_T_19, _mem_idx_T_23) when wen_3 : node _data_T_3 = bits(masterNodeOut.d.bits.data, 127, 96) node data_3 = mux(s3_slaveValid, s1s3_slaveData, _data_T_3) node _way_T_3 = bits(s1s3_slaveAddr, 14, 12) node way_3 = mux(s3_slaveValid, _way_T_3, repl_way) wire _WIRE_4 : UInt<32>[8] connect _WIRE_4[0], data_3 connect _WIRE_4[1], data_3 connect _WIRE_4[2], data_3 connect _WIRE_4[3], data_3 connect _WIRE_4[4], data_3 connect _WIRE_4[5], data_3 connect _WIRE_4[6], data_3 connect _WIRE_4[7], data_3 node _T_79 = eq(way_3, UInt<1>(0h0)) node _T_80 = eq(way_3, UInt<1>(0h1)) node _T_81 = eq(way_3, UInt<2>(0h2)) node _T_82 = eq(way_3, UInt<2>(0h3)) node _T_83 = eq(way_3, UInt<3>(0h4)) node _T_84 = eq(way_3, UInt<3>(0h5)) node _T_85 = eq(way_3, UInt<3>(0h6)) node _T_86 = eq(way_3, UInt<3>(0h7)) write mport MPORT_4 = rockettile_icache_data_arrays_3[mem_idx_3], clock when _T_79 : connect MPORT_4[0], _WIRE_4[0] when _T_80 : connect MPORT_4[1], _WIRE_4[1] when _T_81 : connect MPORT_4[2], _WIRE_4[2] when _T_82 : connect MPORT_4[3], _WIRE_4[3] when _T_83 : connect MPORT_4[4], _WIRE_4[4] when _T_84 : connect MPORT_4[5], _WIRE_4[5] when _T_85 : connect MPORT_4[6], _WIRE_4[6] when _T_86 : connect MPORT_4[7], _WIRE_4[7] node _dout_T_6 = eq(wen_3, UInt<1>(0h0)) node _dout_T_7 = and(_dout_T_6, s0_ren_3) wire _dout_WIRE_3 : UInt<8> invalidate _dout_WIRE_3 when _dout_T_7 : connect _dout_WIRE_3, mem_idx_3 read mport dout_3 = rockettile_icache_data_arrays_3[_dout_WIRE_3], clock node _T_87 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_88 = bits(_T_87, 3, 2) node _T_89 = eq(_T_88, UInt<2>(0h3)) when _T_89 : connect s1_dout, dout_3 wire s1s2_full_word_write : UInt<1> connect s1s2_full_word_write, UInt<1>(0h0) node s1_dont_read = and(s1_slaveValid, s1s2_full_word_write) node s1_clk_en = or(s1_valid, s1_slaveValid) wire _s2_tag_hit_WIRE : UInt<1>[8] connect _s2_tag_hit_WIRE[0], UInt<1>(0h0) connect _s2_tag_hit_WIRE[1], UInt<1>(0h0) connect _s2_tag_hit_WIRE[2], UInt<1>(0h0) connect _s2_tag_hit_WIRE[3], UInt<1>(0h0) connect _s2_tag_hit_WIRE[4], UInt<1>(0h0) connect _s2_tag_hit_WIRE[5], UInt<1>(0h0) connect _s2_tag_hit_WIRE[6], UInt<1>(0h0) connect _s2_tag_hit_WIRE[7], UInt<1>(0h0) node _s2_tag_hit_T = mux(s1_dont_read, _s2_tag_hit_WIRE, s1_tag_hit) reg s2_tag_hit : UInt<1>[8], clock when s1_clk_en : connect s2_tag_hit, _s2_tag_hit_T node s2_hit_way_lo_lo = cat(s2_tag_hit[1], s2_tag_hit[0]) node s2_hit_way_lo_hi = cat(s2_tag_hit[3], s2_tag_hit[2]) node s2_hit_way_lo = cat(s2_hit_way_lo_hi, s2_hit_way_lo_lo) node s2_hit_way_hi_lo = cat(s2_tag_hit[5], s2_tag_hit[4]) node s2_hit_way_hi_hi = cat(s2_tag_hit[7], s2_tag_hit[6]) node s2_hit_way_hi = cat(s2_hit_way_hi_hi, s2_hit_way_hi_lo) node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo) node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 7, 4) node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 3, 0) node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1) node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1) node s2_hit_way_hi_2 = bits(_s2_hit_way_T_2, 3, 2) node s2_hit_way_lo_2 = bits(_s2_hit_way_T_2, 1, 0) node _s2_hit_way_T_3 = orr(s2_hit_way_hi_2) node _s2_hit_way_T_4 = or(s2_hit_way_hi_2, s2_hit_way_lo_2) node _s2_hit_way_T_5 = bits(_s2_hit_way_T_4, 1, 1) node _s2_hit_way_T_6 = cat(_s2_hit_way_T_3, _s2_hit_way_T_5) node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_6) node _s2_scratchpad_word_addr_T = mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr) node _s2_scratchpad_word_addr_T_1 = bits(_s2_scratchpad_word_addr_T, 11, 2) node s2_scratchpad_word_addr_hi = cat(s2_hit_way, _s2_scratchpad_word_addr_T_1) node s2_scratchpad_word_addr = cat(s2_scratchpad_word_addr_hi, UInt<2>(0h0)) reg s2_dout : UInt<32>[8], clock when s1_clk_en : connect s2_dout, s1_dout node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0)) node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0)) node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0)) node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0)) node _s2_way_mux_T_4 = mux(s2_tag_hit[4], s2_dout[4], UInt<1>(0h0)) node _s2_way_mux_T_5 = mux(s2_tag_hit[5], s2_dout[5], UInt<1>(0h0)) node _s2_way_mux_T_6 = mux(s2_tag_hit[6], s2_dout[6], UInt<1>(0h0)) node _s2_way_mux_T_7 = mux(s2_tag_hit[7], s2_dout[7], UInt<1>(0h0)) node _s2_way_mux_T_8 = or(_s2_way_mux_T, _s2_way_mux_T_1) node _s2_way_mux_T_9 = or(_s2_way_mux_T_8, _s2_way_mux_T_2) node _s2_way_mux_T_10 = or(_s2_way_mux_T_9, _s2_way_mux_T_3) node _s2_way_mux_T_11 = or(_s2_way_mux_T_10, _s2_way_mux_T_4) node _s2_way_mux_T_12 = or(_s2_way_mux_T_11, _s2_way_mux_T_5) node _s2_way_mux_T_13 = or(_s2_way_mux_T_12, _s2_way_mux_T_6) node _s2_way_mux_T_14 = or(_s2_way_mux_T_13, _s2_way_mux_T_7) wire s2_way_mux : UInt<32> connect s2_way_mux, _s2_way_mux_T_14 reg s2_tag_disparity_r : UInt<1>[8], clock when s1_clk_en : connect s2_tag_disparity_r, s1_tag_disparity node s2_tag_disparity_lo_lo = cat(s2_tag_disparity_r[1], s2_tag_disparity_r[0]) node s2_tag_disparity_lo_hi = cat(s2_tag_disparity_r[3], s2_tag_disparity_r[2]) node s2_tag_disparity_lo = cat(s2_tag_disparity_lo_hi, s2_tag_disparity_lo_lo) node s2_tag_disparity_hi_lo = cat(s2_tag_disparity_r[5], s2_tag_disparity_r[4]) node s2_tag_disparity_hi_hi = cat(s2_tag_disparity_r[7], s2_tag_disparity_r[6]) node s2_tag_disparity_hi = cat(s2_tag_disparity_hi_hi, s2_tag_disparity_hi_lo) node _s2_tag_disparity_T = cat(s2_tag_disparity_hi, s2_tag_disparity_lo) node s2_tag_disparity = orr(_s2_tag_disparity_T) node s2_tl_error_lo_lo = cat(s1_tl_error[1], s1_tl_error[0]) node s2_tl_error_lo_hi = cat(s1_tl_error[3], s1_tl_error[2]) node s2_tl_error_lo = cat(s2_tl_error_lo_hi, s2_tl_error_lo_lo) node s2_tl_error_hi_lo = cat(s1_tl_error[5], s1_tl_error[4]) node s2_tl_error_hi_hi = cat(s1_tl_error[7], s1_tl_error[6]) node s2_tl_error_hi = cat(s2_tl_error_hi_hi, s2_tl_error_hi_lo) node _s2_tl_error_T = cat(s2_tl_error_hi, s2_tl_error_lo) node _s2_tl_error_T_1 = orr(_s2_tl_error_T) reg s2_tl_error : UInt<1>, clock when s1_clk_en : connect s2_tl_error, _s2_tl_error_T_1 node _s2_disparity_T = or(UInt<1>(0h0), UInt<1>(0h0)) node s2_disparity = or(s2_tag_disparity, _s2_disparity_T) node _s1_scratchpad_hit_T = bits(s1s3_slaveAddr, 14, 6) node _s1_scratchpad_hit_T_1 = bits(io.s1_paddr, 14, 6) node _s1_scratchpad_hit_T_2 = and(UInt<1>(0h0), UInt<1>(0h0)) node s1_scratchpad_hit = mux(s1_slaveValid, UInt<1>(0h0), _s1_scratchpad_hit_T_2) reg s2_scratchpad_hit : UInt<1>, clock when s1_clk_en : connect s2_scratchpad_hit, s1_scratchpad_hit node _s2_report_uncorrectable_error_T = and(s2_scratchpad_hit, UInt<1>(0h0)) node _s2_report_uncorrectable_error_T_1 = eq(s1s2_full_word_write, UInt<1>(0h0)) node _s2_report_uncorrectable_error_T_2 = and(s2_slaveValid, _s2_report_uncorrectable_error_T_1) node _s2_report_uncorrectable_error_T_3 = or(s2_valid, _s2_report_uncorrectable_error_T_2) node s2_report_uncorrectable_error = and(_s2_report_uncorrectable_error_T, _s2_report_uncorrectable_error_T_3) node _T_90 = and(s2_valid, s2_disparity) when _T_90 : connect invalidate, UInt<1>(0h1) connect io.resp.bits.data, s2_way_mux connect io.resp.bits.ae, s2_tl_error connect io.resp.bits.replay, s2_disparity node _io_resp_valid_T = and(s2_valid, s2_hit) connect io.resp.valid, _io_resp_valid_T connect masterNodeOut.a.valid, s2_request_refill node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000)) node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h98013000))) node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000)) node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44) node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46) node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49) node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51) node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28) node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33) node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38) node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43) node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48) node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53) node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60) node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61) wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 3, 0) node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 3, 3) node masterNodeOut_a_bits_a_mask_sub_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 3, 3) node masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_sub_4_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_4 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_4_2) node masterNodeOut_a_bits_a_mask_sub_4_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_4) node masterNodeOut_a_bits_a_mask_sub_5_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_5 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_5_2) node masterNodeOut_a_bits_a_mask_sub_5_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_5) node masterNodeOut_a_bits_a_mask_sub_6_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_6 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_6_2) node masterNodeOut_a_bits_a_mask_sub_6_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_6) node masterNodeOut_a_bits_a_mask_sub_7_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_7 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_7_2) node masterNodeOut_a_bits_a_mask_sub_7_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_7) node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) node masterNodeOut_a_bits_a_mask_eq_8 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_8 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_8) node masterNodeOut_a_bits_a_mask_acc_8 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_8) node masterNodeOut_a_bits_a_mask_eq_9 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_9 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_9) node masterNodeOut_a_bits_a_mask_acc_9 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_9) node masterNodeOut_a_bits_a_mask_eq_10 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_10 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_10) node masterNodeOut_a_bits_a_mask_acc_10 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_10) node masterNodeOut_a_bits_a_mask_eq_11 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_11 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_11) node masterNodeOut_a_bits_a_mask_acc_11 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_11) node masterNodeOut_a_bits_a_mask_eq_12 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_12 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_12) node masterNodeOut_a_bits_a_mask_acc_12 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_12) node masterNodeOut_a_bits_a_mask_eq_13 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_13 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_13) node masterNodeOut_a_bits_a_mask_acc_13 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_13) node masterNodeOut_a_bits_a_mask_eq_14 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_14 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_14) node masterNodeOut_a_bits_a_mask_acc_14 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_14) node masterNodeOut_a_bits_a_mask_eq_15 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_15 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_15) node masterNodeOut_a_bits_a_mask_acc_15 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_15) node masterNodeOut_a_bits_a_mask_lo_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) node masterNodeOut_a_bits_a_mask_lo_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_lo_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo_lo) node masterNodeOut_a_bits_a_mask_lo_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) node masterNodeOut_a_bits_a_mask_lo_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_lo_hi_hi, masterNodeOut_a_bits_a_mask_lo_hi_lo) node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) node masterNodeOut_a_bits_a_mask_hi_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_9, masterNodeOut_a_bits_a_mask_acc_8) node masterNodeOut_a_bits_a_mask_hi_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_11, masterNodeOut_a_bits_a_mask_acc_10) node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_hi_lo_hi, masterNodeOut_a_bits_a_mask_hi_lo_lo) node masterNodeOut_a_bits_a_mask_hi_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_13, masterNodeOut_a_bits_a_mask_acc_12) node masterNodeOut_a_bits_a_mask_hi_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_15, masterNodeOut_a_bits_a_mask_acc_14) node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi_hi, masterNodeOut_a_bits_a_mask_hi_hi_lo) node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T invalidate masterNodeOut_a_bits_a.data connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect masterNodeOut.a.bits, masterNodeOut_a_bits_a wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits.corrupt, UInt<1>(0h0) connect _WIRE_5.bits.data, UInt<128>(0h0) connect _WIRE_5.bits.mask, UInt<16>(0h0) connect _WIRE_5.bits.address, UInt<32>(0h0) connect _WIRE_5.bits.source, UInt<1>(0h0) connect _WIRE_5.bits.size, UInt<4>(0h0) connect _WIRE_5.bits.param, UInt<2>(0h0) connect _WIRE_5.bits.opcode, UInt<3>(0h0) connect _WIRE_5.valid, UInt<1>(0h0) connect _WIRE_5.ready, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits, _WIRE_5.bits connect _WIRE_6.valid, _WIRE_5.valid connect _WIRE_6.ready, _WIRE_5.ready connect _WIRE_6.ready, UInt<1>(0h1) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits.corrupt, UInt<1>(0h0) connect _WIRE_7.bits.data, UInt<128>(0h0) connect _WIRE_7.bits.address, UInt<32>(0h0) connect _WIRE_7.bits.source, UInt<1>(0h0) connect _WIRE_7.bits.size, UInt<4>(0h0) connect _WIRE_7.bits.param, UInt<3>(0h0) connect _WIRE_7.bits.opcode, UInt<3>(0h0) connect _WIRE_7.valid, UInt<1>(0h0) connect _WIRE_7.ready, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits, _WIRE_7.bits connect _WIRE_8.valid, _WIRE_7.valid connect _WIRE_8.ready, _WIRE_7.ready connect _WIRE_8.valid, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_9.bits.sink, UInt<4>(0h0) connect _WIRE_9.valid, UInt<1>(0h0) connect _WIRE_9.ready, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits, _WIRE_9.bits connect _WIRE_10.valid, _WIRE_9.valid connect _WIRE_10.ready, _WIRE_9.ready connect _WIRE_10.valid, UInt<1>(0h0) node _T_91 = and(masterNodeOut.a.valid, UInt<1>(0h0)) node _T_92 = eq(_T_91, UInt<1>(0h0)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:826 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n") : printf_1 assert(clock, _T_92, UInt<1>(0h1), "") : assert_1 node _T_96 = eq(refill_valid, UInt<1>(0h0)) when _T_96 : connect invalidated, UInt<1>(0h0) when refill_fire : connect refill_valid, UInt<1>(0h1) when refill_done : connect refill_valid, UInt<1>(0h0) connect io.perf.acquire, refill_fire node _io_keep_clock_enabled_T = or(UInt<1>(0h0), s1_valid) node _io_keep_clock_enabled_T_1 = or(_io_keep_clock_enabled_T, s2_valid) node _io_keep_clock_enabled_T_2 = or(_io_keep_clock_enabled_T_1, refill_valid) node _io_keep_clock_enabled_T_3 = or(_io_keep_clock_enabled_T_2, send_hint) node _io_keep_clock_enabled_T_4 = or(_io_keep_clock_enabled_T_3, hint_outstanding) connect io.keep_clock_enabled, _io_keep_clock_enabled_T_4 node _T_97 = eq(send_hint, UInt<1>(0h0)) node _T_98 = eq(masterNodeOut.a.ready, UInt<1>(0h0)) node _T_99 = and(masterNodeOut.a.valid, _T_98) node _T_100 = and(_T_97, _T_99) node _T_101 = and(invalidate, refill_valid) node _T_102 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_103 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(s2_slaveValid, UInt<1>(0h0)) node _T_106 = eq(s2_tag_disparity, UInt<1>(0h0)) node _T_107 = eq(s2_scratchpad_hit, UInt<1>(0h0)) node _T_108 = and(_T_105, s2_scratchpad_hit) node _T_109 = and(_T_105, _T_107) node _T_110 = and(s2_slaveValid, s2_scratchpad_hit) node _T_111 = and(s2_slaveValid, _T_107) node _T_112 = and(_T_106, _T_108) node _T_113 = and(_T_106, _T_109) node _T_114 = and(_T_106, _T_110) node _T_115 = and(_T_106, _T_111) node _T_116 = and(_T_105, s2_scratchpad_hit) node _T_117 = and(_T_105, _T_107) node _T_118 = and(s2_slaveValid, s2_scratchpad_hit) node _T_119 = and(s2_slaveValid, _T_107) node _T_120 = and(s2_tag_disparity, _T_116) node _T_121 = and(s2_tag_disparity, _T_117) node _T_122 = and(s2_tag_disparity, _T_118) node _T_123 = and(s2_tag_disparity, _T_119) node _T_124 = and(_T_104, _T_112) node _T_125 = and(_T_104, _T_113) node _T_126 = and(_T_104, _T_114) node _T_127 = and(_T_104, _T_115) node _T_128 = and(_T_104, _T_120) node _T_129 = and(_T_104, _T_121) node _T_130 = and(_T_104, _T_122) node _T_131 = and(_T_104, _T_123) node _T_132 = and(_T_105, s2_scratchpad_hit) node _T_133 = and(_T_105, _T_107) node _T_134 = and(s2_slaveValid, s2_scratchpad_hit) node _T_135 = and(s2_slaveValid, _T_107) node _T_136 = and(_T_106, _T_132) node _T_137 = and(_T_106, _T_133) node _T_138 = and(_T_106, _T_134) node _T_139 = and(_T_106, _T_135) node _T_140 = and(_T_105, s2_scratchpad_hit) node _T_141 = and(_T_105, _T_107) node _T_142 = and(s2_slaveValid, s2_scratchpad_hit) node _T_143 = and(s2_slaveValid, _T_107) node _T_144 = and(s2_tag_disparity, _T_140) node _T_145 = and(s2_tag_disparity, _T_141) node _T_146 = and(s2_tag_disparity, _T_142) node _T_147 = and(s2_tag_disparity, _T_143) node _T_148 = and(UInt<1>(0h0), _T_136) node _T_149 = and(UInt<1>(0h0), _T_137) node _T_150 = and(UInt<1>(0h0), _T_138) node _T_151 = and(UInt<1>(0h0), _T_139) node _T_152 = and(UInt<1>(0h0), _T_144) node _T_153 = and(UInt<1>(0h0), _T_145) node _T_154 = and(UInt<1>(0h0), _T_146) node _T_155 = and(UInt<1>(0h0), _T_147) node _T_156 = and(_T_105, s2_scratchpad_hit) node _T_157 = and(_T_105, _T_107) node _T_158 = and(s2_slaveValid, s2_scratchpad_hit) node _T_159 = and(s2_slaveValid, _T_107) node _T_160 = and(_T_106, _T_156) node _T_161 = and(_T_106, _T_157) node _T_162 = and(_T_106, _T_158) node _T_163 = and(_T_106, _T_159) node _T_164 = and(_T_105, s2_scratchpad_hit) node _T_165 = and(_T_105, _T_107) node _T_166 = and(s2_slaveValid, s2_scratchpad_hit) node _T_167 = and(s2_slaveValid, _T_107) node _T_168 = and(s2_tag_disparity, _T_164) node _T_169 = and(s2_tag_disparity, _T_165) node _T_170 = and(s2_tag_disparity, _T_166) node _T_171 = and(s2_tag_disparity, _T_167) node _T_172 = and(UInt<1>(0h0), _T_160) node _T_173 = and(UInt<1>(0h0), _T_161) node _T_174 = and(UInt<1>(0h0), _T_162) node _T_175 = and(UInt<1>(0h0), _T_163) node _T_176 = and(UInt<1>(0h0), _T_168) node _T_177 = and(UInt<1>(0h0), _T_169) node _T_178 = and(UInt<1>(0h0), _T_170) node _T_179 = and(UInt<1>(0h0), _T_171) node _T_180 = and(s2_valid, _T_124) node _T_181 = and(s2_valid, _T_125) node _T_182 = and(s2_valid, _T_126) node _T_183 = and(s2_valid, _T_127) node _T_184 = and(s2_valid, _T_128) node _T_185 = and(s2_valid, _T_129) node _T_186 = and(s2_valid, _T_130) node _T_187 = and(s2_valid, _T_131) node _T_188 = and(s2_valid, _T_148) node _T_189 = and(s2_valid, _T_149) node _T_190 = and(s2_valid, _T_150) node _T_191 = and(s2_valid, _T_151) node _T_192 = and(s2_valid, _T_152) node _T_193 = and(s2_valid, _T_153) node _T_194 = and(s2_valid, _T_154) node _T_195 = and(s2_valid, _T_155) node _T_196 = and(s2_valid, _T_172) node _T_197 = and(s2_valid, _T_173) node _T_198 = and(s2_valid, _T_174) node _T_199 = and(s2_valid, _T_175) node _T_200 = and(s2_valid, _T_176) node _T_201 = and(s2_valid, _T_177) node _T_202 = and(s2_valid, _T_178) node _T_203 = and(s2_valid, _T_179)
module ICache_1( // @[ICache.scala:251:7] input clock, // @[ICache.scala:251:7] input reset, // @[ICache.scala:251:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_req_valid, // @[ICache.scala:256:14] input [38:0] io_req_bits_addr, // @[ICache.scala:256:14] input [31:0] io_s1_paddr, // @[ICache.scala:256:14] input [38:0] io_s2_vaddr, // @[ICache.scala:256:14] input io_s1_kill, // @[ICache.scala:256:14] input io_s2_kill, // @[ICache.scala:256:14] input io_s2_cacheable, // @[ICache.scala:256:14] input io_s2_prefetch, // @[ICache.scala:256:14] output io_resp_valid, // @[ICache.scala:256:14] output [31:0] io_resp_bits_data, // @[ICache.scala:256:14] output io_resp_bits_ae, // @[ICache.scala:256:14] input io_invalidate, // @[ICache.scala:256:14] output io_errors_bus_valid, // @[ICache.scala:256:14] output [31:0] io_errors_bus_bits, // @[ICache.scala:256:14] output io_perf_acquire // @[ICache.scala:256:14] ); wire rockettile_icache_data_arrays_3_MPORT_4_mask_7; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_6; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_5; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_4; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_3; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_2; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_1; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_3_MPORT_4_mask_0; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_7; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_6; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_5; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_4; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_3; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_2; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_1; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_2_MPORT_3_mask_0; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_7; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_6; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_5; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_4; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_3; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_2; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_1; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_1_MPORT_2_mask_0; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_7; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_6; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_5; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_4; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_3; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_2; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_1; // @[ICache.scala:586:102] wire rockettile_icache_data_arrays_0_MPORT_1_mask_0; // @[ICache.scala:586:102] wire rockettile_icache_tag_array_MPORT_mask_7; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_6; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_5; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_4; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_3; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_2; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_1; // @[ICache.scala:436:97] wire rockettile_icache_tag_array_MPORT_mask_0; // @[ICache.scala:436:97] wire s1_tag_hit_6; // @[ICache.scala:345:24] wire s1_tag_hit_5; // @[ICache.scala:345:24] wire s1_tag_hit_4; // @[ICache.scala:345:24] wire s1_tag_hit_3; // @[ICache.scala:345:24] wire s1_tag_hit_2; // @[ICache.scala:345:24] wire s1_tag_hit_1; // @[ICache.scala:345:24] wire s1_tag_hit_0; // @[ICache.scala:345:24] wire [255:0] _rockettile_icache_data_arrays_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [255:0] _rockettile_icache_data_arrays_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [255:0] _rockettile_icache_data_arrays_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [255:0] _rockettile_icache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [167:0] _rockettile_icache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _repl_way_v0_prng_io_out_0; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_1; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_2; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_3; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_4; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_5; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_6; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_7; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_8; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_9; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_10; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_11; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_12; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_13; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_14; // @[PRNG.scala:91:22] wire _repl_way_v0_prng_io_out_15; // @[PRNG.scala:91:22] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[ICache.scala:251:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[ICache.scala:251:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[ICache.scala:251:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[ICache.scala:251:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[ICache.scala:251:7] wire [3:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[ICache.scala:251:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[ICache.scala:251:7] wire [127:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[ICache.scala:251:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[ICache.scala:251:7] wire io_req_valid_0 = io_req_valid; // @[ICache.scala:251:7] wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[ICache.scala:251:7] wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[ICache.scala:251:7] wire [38:0] io_s2_vaddr_0 = io_s2_vaddr; // @[ICache.scala:251:7] wire io_s1_kill_0 = io_s1_kill; // @[ICache.scala:251:7] wire io_s2_kill_0 = io_s2_kill; // @[ICache.scala:251:7] wire io_s2_cacheable_0 = io_s2_cacheable; // @[ICache.scala:251:7] wire io_s2_prefetch_0 = io_s2_prefetch; // @[ICache.scala:251:7] wire io_invalidate_0 = io_invalidate; // @[ICache.scala:251:7] wire _repl_way_T_13 = reset; // @[ICache.scala:413:11] wire auto_master_out_d_ready = 1'h1; // @[ICache.scala:251:7] wire io_clock_enabled = 1'h1; // @[ICache.scala:251:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _refill_fire_T_1 = 1'h1; // @[ICache.scala:374:38] wire _masterNodeOut_d_ready_T = 1'h1; // @[ICache.scala:401:21] wire _repl_way_T_12 = 1'h1; // @[ICache.scala:413:12] wire _scratchpadHit_T = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_4 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_11 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_9 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_22 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_14 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_33 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_19 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_44 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_23 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_55 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_27 = 1'h1; // @[ICache.scala:508:74] wire _scratchpadHit_T_66 = 1'h1; // @[ICache.scala:316:43] wire _s1_vb_T_31 = 1'h1; // @[ICache.scala:508:74] wire _s1_vb_T_35 = 1'h1; // @[ICache.scala:508:74] wire _s0_ren_T_3 = 1'h1; // @[ICache.scala:564:111] wire _s2_report_uncorrectable_error_T_1 = 1'h1; // @[ICache.scala:632:124] wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire auto_master_out_a_bits_source = 1'h0; // @[ICache.scala:251:7] wire auto_master_out_a_bits_corrupt = 1'h0; // @[ICache.scala:251:7] wire auto_master_out_d_bits_source = 1'h0; // @[ICache.scala:251:7] wire io_resp_bits_replay = 1'h0; // @[ICache.scala:251:7] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _s1_hit_T_7 = 1'h0; // @[ICache.scala:361:46] wire _repl_way_T_10 = 1'h0; // @[ICache.scala:411:63] wire _repl_way_T_15 = 1'h0; // @[ICache.scala:413:11] wire s1_tag_disparity_0 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_1 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_2 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_3 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_4 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_5 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_6 = 1'h0; // @[ICache.scala:465:30] wire s1_tag_disparity_7 = 1'h0; // @[ICache.scala:465:30] wire _scratchpadHit_T_4 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_6 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_9 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_10 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_0_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_0_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_15 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_17 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_20 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_21 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_1 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_1_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_1_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_26 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_28 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_31 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_32 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_2 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_2_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_2_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_37 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_39 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_42 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_43 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_3 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_3_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_3_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_48 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_50 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_53 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_54 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_4 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_4_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_4_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_59 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_61 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_64 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_65 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_5 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_5_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_5_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_70 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_72 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_75 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_76 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_6 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_6_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_6_T_1 = 1'h0; // @[ICache.scala:516:34] wire _scratchpadHit_T_77 = 1'h0; // @[ICache.scala:316:43] wire _scratchpadHit_T_81 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_83 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_86 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_87 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit_7 = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_7_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_7_T_1 = 1'h0; // @[ICache.scala:516:34] wire _s0_ren_T_4 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_4 = 1'h0; // @[ICache.scala:570:67] wire _s0_ren_T_8 = 1'h0; // @[ICache.scala:564:111] wire _s0_ren_T_9 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_9 = 1'h0; // @[ICache.scala:570:67] wire _s0_ren_T_13 = 1'h0; // @[ICache.scala:564:111] wire _s0_ren_T_14 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_14 = 1'h0; // @[ICache.scala:570:67] wire _s0_ren_T_18 = 1'h0; // @[ICache.scala:564:111] wire _s0_ren_T_19 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_19 = 1'h0; // @[ICache.scala:570:67] wire s1s2_full_word_write = 1'h0; // @[ICache.scala:600:41] wire s1_dont_read = 1'h0; // @[ICache.scala:601:36] wire _s2_tag_hit_WIRE_0 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_1 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_2 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_3 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_4 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_5 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_6 = 1'h0; // @[ICache.scala:605:60] wire _s2_tag_hit_WIRE_7 = 1'h0; // @[ICache.scala:605:60] wire s2_tag_disparity = 1'h0; // @[ICache.scala:614:72] wire _s2_disparity_T = 1'h0; // @[ECC.scala:15:27] wire s2_disparity = 1'h0; // @[ICache.scala:619:39] wire _s1_scratchpad_hit_T_2 = 1'h0; // @[ICache.scala:302:66] wire s1_scratchpad_hit = 1'h0; // @[ICache.scala:621:30] wire _s2_report_uncorrectable_error_T = 1'h0; // @[ICache.scala:632:57] wire _s2_report_uncorrectable_error_T_2 = 1'h0; // @[ICache.scala:632:121] wire s2_report_uncorrectable_error = 1'h0; // @[ICache.scala:632:90] wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire [7:0] _mem_idx_T_2 = 8'h0; // @[ICache.scala:565:31] wire [7:0] _mem_idx_T_8 = 8'h0; // @[ICache.scala:565:31] wire [7:0] _mem_idx_T_14 = 8'h0; // @[ICache.scala:565:31] wire [7:0] _mem_idx_T_20 = 8'h0; // @[ICache.scala:565:31] wire [7:0] _s2_tag_disparity_T = 8'h0; // @[ICache.scala:614:65] wire [3:0] s2_tag_disparity_lo = 4'h0; // @[ICache.scala:614:65] wire [3:0] s2_tag_disparity_hi = 4'h0; // @[ICache.scala:614:65] wire [1:0] _repl_way_T_6 = 2'h0; // @[ICache.scala:411:63] wire [1:0] _wen_T_2 = 2'h0; // @[package.scala:163:13] wire [1:0] _wen_T_7 = 2'h0; // @[package.scala:163:13] wire [1:0] _wen_T_12 = 2'h0; // @[package.scala:163:13] wire [1:0] _wen_T_17 = 2'h0; // @[package.scala:163:13] wire [1:0] s2_tag_disparity_lo_lo = 2'h0; // @[ICache.scala:614:65] wire [1:0] s2_tag_disparity_lo_hi = 2'h0; // @[ICache.scala:614:65] wire [1:0] s2_tag_disparity_hi_lo = 2'h0; // @[ICache.scala:614:65] wire [1:0] s2_tag_disparity_hi_hi = 2'h0; // @[ICache.scala:614:65] wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _repl_way_T_2 = 3'h0; // @[ICache.scala:411:63] wire [2:0] _scratchpadHit_T_2 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_13 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_24 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_35 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_46 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_57 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_68 = 3'h0; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_79 = 3'h0; // @[package.scala:163:13] wire [2:0] _way_T = 3'h0; // @[package.scala:163:13] wire [2:0] _way_T_1 = 3'h0; // @[package.scala:163:13] wire [2:0] _way_T_2 = 3'h0; // @[package.scala:163:13] wire [2:0] _way_T_3 = 3'h0; // @[package.scala:163:13] wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17] wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[ICache.scala:251:7] wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [15:0] auto_master_out_a_bits_mask = 16'hFFFF; // @[ICache.scala:251:7] wire [15:0] masterNodeOut_a_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] masterNodeOut_a_bits_a_mask = 16'hFFFF; // @[Edges.scala:460:17] wire [15:0] _masterNodeOut_a_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] auto_master_out_a_bits_data = 128'h0; // @[ICache.scala:251:7] wire [127:0] masterNodeOut_a_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] masterNodeOut_a_bits_a_data = 128'h0; // @[Edges.scala:460:17] wire [7:0] masterNodeOut_a_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] masterNodeOut_a_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [8:0] _scratchpadHit_T_1 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_12 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_23 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_34 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_45 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_56 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_67 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _scratchpadHit_T_78 = 9'h0; // @[ICache.scala:327:40] wire [8:0] _s1_scratchpad_hit_T = 9'h0; // @[ICache.scala:327:40] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[ICache.scala:251:7] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[ICache.scala:251:7] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[ICache.scala:251:7] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[ICache.scala:251:7] wire [3:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[ICache.scala:251:7] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[ICache.scala:251:7] wire [127:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[ICache.scala:251:7] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[ICache.scala:251:7] wire _io_req_ready_T_2; // @[ICache.scala:394:19] wire [38:0] _s2_scratchpad_word_addr_T = io_s2_vaddr_0; // @[ICache.scala:251:7, :611:52] wire _io_resp_valid_T; // @[ICache.scala:659:33] wire [31:0] s2_way_mux; // @[Mux.scala:30:73] wire _io_errors_bus_valid_T_2; // @[ICache.scala:441:40] wire invalidate = io_invalidate_0; // @[ICache.scala:251:7, :456:31] wire [31:0] _io_errors_bus_bits_T_1; // @[ICache.scala:442:57] wire refill_fire; // @[ICache.scala:374:35] wire _io_keep_clock_enabled_T_4; // @[ICache.scala:837:55] wire [31:0] auto_master_out_a_bits_address_0; // @[ICache.scala:251:7] wire auto_master_out_a_valid_0; // @[ICache.scala:251:7] wire io_req_ready; // @[ICache.scala:251:7] wire [31:0] io_resp_bits_data_0; // @[ICache.scala:251:7] wire io_resp_bits_ae_0; // @[ICache.scala:251:7] wire io_resp_valid_0; // @[ICache.scala:251:7] wire io_errors_bus_valid_0; // @[ICache.scala:251:7] wire [31:0] io_errors_bus_bits_0; // @[ICache.scala:251:7] wire io_perf_acquire_0; // @[ICache.scala:251:7] wire io_keep_clock_enabled; // @[ICache.scala:251:7] wire s2_request_refill; // @[ICache.scala:385:35] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[ICache.scala:251:7] wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[ICache.scala:251:7] wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[ICache.scala:341:25] wire s1_clk_en = s1_valid; // @[ICache.scala:341:25, :604:28] wire _io_keep_clock_enabled_T = s1_valid; // @[ICache.scala:341:25, :836:117] reg [38:0] s1_vaddr; // @[ICache.scala:343:27] wire _s1_tag_hit_0_T; // @[ICache.scala:519:31] wire _s1_tag_hit_1_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_0 = s1_tag_hit_0; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_2_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_1 = s1_tag_hit_1; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_3_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_2 = s1_tag_hit_2; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_4_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_3 = s1_tag_hit_3; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_5_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_4 = s1_tag_hit_4; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_6_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_5 = s1_tag_hit_5; // @[ICache.scala:345:24, :605:33] wire _s1_tag_hit_7_T; // @[ICache.scala:519:31] wire _s2_tag_hit_T_6 = s1_tag_hit_6; // @[ICache.scala:345:24, :605:33] wire s1_tag_hit_7; // @[ICache.scala:345:24] wire _s2_tag_hit_T_7 = s1_tag_hit_7; // @[ICache.scala:345:24, :605:33] wire _s1_hit_T = s1_tag_hit_0 | s1_tag_hit_1; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_1 = _s1_hit_T | s1_tag_hit_2; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_2 = _s1_hit_T_1 | s1_tag_hit_3; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_3 = _s1_hit_T_2 | s1_tag_hit_4; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_4 = _s1_hit_T_3 | s1_tag_hit_5; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_5 = _s1_hit_T_4 | s1_tag_hit_6; // @[ICache.scala:345:24, :361:35] wire _s1_hit_T_6 = _s1_hit_T_5 | s1_tag_hit_7; // @[ICache.scala:345:24, :361:35] wire s1_hit = _s1_hit_T_6; // @[ICache.scala:361:{35,40}] wire _s2_valid_T = ~io_s1_kill_0; // @[ICache.scala:251:7, :363:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[ICache.scala:341:25, :363:{35,38}] reg s2_valid; // @[ICache.scala:363:25] wire _s2_report_uncorrectable_error_T_3 = s2_valid; // @[ICache.scala:363:25, :632:103] reg s2_hit; // @[ICache.scala:364:23] reg invalidated; // @[ICache.scala:367:24] reg refill_valid; // @[ICache.scala:368:29] wire _refill_fire_T = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35] assign refill_fire = _refill_fire_T; // @[Decoupled.scala:51:35] assign io_perf_acquire_0 = refill_fire; // @[ICache.scala:251:7, :374:35] wire _s2_miss_T = ~s2_hit; // @[ICache.scala:364:23, :378:29] wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[ICache.scala:363:25, :378:{26,29}] wire _s2_miss_T_2 = ~io_s2_kill_0; // @[ICache.scala:251:7, :378:40] wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[ICache.scala:378:{26,37,40}] wire _s1_can_request_refill_T = s2_miss | refill_valid; // @[ICache.scala:368:29, :378:37, :380:41] wire s1_can_request_refill = ~_s1_can_request_refill_T; // @[ICache.scala:380:{31,41}] reg s2_request_refill_REG; // @[ICache.scala:385:45] assign s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala:378:37, :385:{35,45}] assign masterNodeOut_a_valid = s2_request_refill; // @[ICache.scala:385:35] wire _GEN = s1_valid & s1_can_request_refill; // @[ICache.scala:341:25, :380:31, :386:54] wire _refill_paddr_T; // @[ICache.scala:386:54] assign _refill_paddr_T = _GEN; // @[ICache.scala:386:54] wire _refill_vaddr_T; // @[ICache.scala:387:51] assign _refill_vaddr_T = _GEN; // @[ICache.scala:386:54, :387:51] reg [31:0] refill_paddr; // @[ICache.scala:386:31] reg [38:0] refill_vaddr; // @[ICache.scala:387:31] wire [19:0] refill_tag = refill_paddr[31:12]; // @[ICache.scala:386:31, :388:33] wire [5:0] refill_idx = refill_paddr[11:6]; // @[ICache.scala:386:31, :859:21] wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35] wire _io_req_ready_T = refill_one_beat; // @[ICache.scala:391:39, :394:37] wire _io_req_ready_T_1 = _io_req_ready_T; // @[ICache.scala:394:{37,54}] assign _io_req_ready_T_2 = ~_io_req_ready_T_1; // @[ICache.scala:394:{19,54}] assign io_req_ready = _io_req_ready_T_2; // @[ICache.scala:251:7, :394:19] wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire refill_done = refill_one_beat & d_done; // @[Edges.scala:233:22] wire [1:0] repl_way_v0_lo_lo_lo = {_repl_way_v0_prng_io_out_1, _repl_way_v0_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_v0_lo_lo_hi = {_repl_way_v0_prng_io_out_3, _repl_way_v0_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_v0_lo_lo = {repl_way_v0_lo_lo_hi, repl_way_v0_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_v0_lo_hi_lo = {_repl_way_v0_prng_io_out_5, _repl_way_v0_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_v0_lo_hi_hi = {_repl_way_v0_prng_io_out_7, _repl_way_v0_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_v0_lo_hi = {repl_way_v0_lo_hi_hi, repl_way_v0_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_v0_lo = {repl_way_v0_lo_hi, repl_way_v0_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_v0_hi_lo_lo = {_repl_way_v0_prng_io_out_9, _repl_way_v0_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_v0_hi_lo_hi = {_repl_way_v0_prng_io_out_11, _repl_way_v0_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_v0_hi_lo = {repl_way_v0_hi_lo_hi, repl_way_v0_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] repl_way_v0_hi_hi_lo = {_repl_way_v0_prng_io_out_13, _repl_way_v0_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] repl_way_v0_hi_hi_hi = {_repl_way_v0_prng_io_out_15, _repl_way_v0_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] repl_way_v0_hi_hi = {repl_way_v0_hi_hi_hi, repl_way_v0_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] repl_way_v0_hi = {repl_way_v0_hi_hi, repl_way_v0_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _repl_way_v0_T = {repl_way_v0_hi, repl_way_v0_lo}; // @[PRNG.scala:95:17] wire [2:0] repl_way_v0 = _repl_way_v0_T[2:0]; // @[PRNG.scala:95:17] wire [2:0] _repl_way_T = repl_way_v0; // @[ICache.scala:407:35, :411:40] wire [2:0] _repl_way_T_3 = repl_way_v0; // @[ICache.scala:407:35, :411:13] wire [8:0] _repl_way_T_1 = {_repl_way_T, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21] wire [2:0] _repl_way_T_7 = _repl_way_T_3; // @[ICache.scala:411:13] wire [2:0] _repl_way_T_4 = repl_way_v0 | 3'h4; // @[ICache.scala:407:35, :411:40] wire [8:0] _repl_way_T_5 = {_repl_way_T_4, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21] wire [2:0] repl_way = _repl_way_T_7; // @[ICache.scala:411:13] wire [2:0] _repl_way_T_8 = repl_way_v0 | 3'h6; // @[ICache.scala:407:35, :411:40] wire [8:0] _repl_way_T_9 = {_repl_way_T_8, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21] wire [2:0] way = repl_way; // @[ICache.scala:411:13, :585:20] wire [2:0] way_1 = repl_way; // @[ICache.scala:411:13, :585:20] wire [2:0] way_2 = repl_way; // @[ICache.scala:411:13, :585:20] wire [2:0] way_3 = repl_way; // @[ICache.scala:411:13, :585:20] wire [8:0] _GEN_0 = {repl_way, refill_idx}; // @[ICache.scala:411:13, :413:33, :859:21] wire [8:0] _repl_way_T_11; // @[ICache.scala:413:33] assign _repl_way_T_11 = _GEN_0; // @[ICache.scala:413:33] wire [8:0] _vb_array_T; // @[ICache.scala:452:36] assign _vb_array_T = _GEN_0; // @[ICache.scala:413:33, :452:36] wire _repl_way_T_14 = ~_repl_way_T_13; // @[ICache.scala:413:11] wire [5:0] _tag_rdata_WIRE; // @[ICache.scala:426:33] wire _tag_rdata_T_2; // @[ICache.scala:426:83] wire [20:0] enc_tag; // @[ICache.scala:435:34] wire [5:0] _tag_rdata_T = io_req_bits_addr_0[11:6]; // @[ICache.scala:251:7, :426:42] assign _tag_rdata_WIRE = _tag_rdata_T; // @[ICache.scala:426:{33,42}] wire _tag_rdata_T_1 = ~refill_done; // @[ICache.scala:399:37, :426:70] assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35] reg accruedRefillError; // @[ICache.scala:428:31] wire _refillError_T = |refill_cnt; // @[Edges.scala:234:25] wire _refillError_T_1 = _refillError_T & accruedRefillError; // @[ICache.scala:428:31, :430:{58,64}] wire refillError = masterNodeOut_d_bits_corrupt | _refillError_T_1; // @[ICache.scala:430:{43,64}] assign enc_tag = {refillError, refill_tag}; // @[ICache.scala:388:33, :430:43, :435:34] assign rockettile_icache_tag_array_MPORT_mask_0 = repl_way == 3'h0; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_1 = repl_way == 3'h1; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_2 = repl_way == 3'h2; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_3 = repl_way == 3'h3; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_4 = repl_way == 3'h4; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_5 = repl_way == 3'h5; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_6 = repl_way == 3'h6; // @[ICache.scala:411:13, :436:97] assign rockettile_icache_tag_array_MPORT_mask_7 = &repl_way; // @[ICache.scala:411:13, :436:97] wire _io_errors_bus_valid_T_1 = masterNodeOut_d_bits_denied | masterNodeOut_d_bits_corrupt; // @[ICache.scala:441:65] assign _io_errors_bus_valid_T_2 = _io_errors_bus_valid_T & _io_errors_bus_valid_T_1; // @[Decoupled.scala:51:35] assign io_errors_bus_valid_0 = _io_errors_bus_valid_T_2; // @[ICache.scala:251:7, :441:40] wire [25:0] _io_errors_bus_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40] wire [25:0] _masterNodeOut_a_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40, :769:47] assign _io_errors_bus_bits_T_1 = {_io_errors_bus_bits_T, 6'h0}; // @[ICache.scala:442:{40,57}] assign io_errors_bus_bits_0 = _io_errors_bus_bits_T_1; // @[ICache.scala:251:7, :442:57] reg [511:0] vb_array; // @[ICache.scala:448:25] wire _vb_array_T_1 = ~invalidated; // @[ICache.scala:367:24, :452:75] wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[ICache.scala:399:37, :452:{72,75}] wire [511:0] _vb_array_T_3 = 512'h1 << _vb_array_T; // @[ICache.scala:452:{32,36}] wire [511:0] _vb_array_T_4 = vb_array | _vb_array_T_3; // @[ICache.scala:448:25, :452:32] wire [511:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala:448:25, :452:32] wire [511:0] _vb_array_T_6 = _vb_array_T_5 | _vb_array_T_3; // @[ICache.scala:452:32] wire [511:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala:452:32] wire [511:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[ICache.scala:452:{32,72}] wire _s1_tl_error_0_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_1_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_2_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_3_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_4_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_5_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_6_T_1; // @[ICache.scala:518:32] wire _s1_tl_error_7_T_1; // @[ICache.scala:518:32] wire s1_tl_error_0; // @[ICache.scala:469:25] wire s1_tl_error_1; // @[ICache.scala:469:25] wire s1_tl_error_2; // @[ICache.scala:469:25] wire s1_tl_error_3; // @[ICache.scala:469:25] wire s1_tl_error_4; // @[ICache.scala:469:25] wire s1_tl_error_5; // @[ICache.scala:469:25] wire s1_tl_error_6; // @[ICache.scala:469:25] wire s1_tl_error_7; // @[ICache.scala:469:25] wire [31:0] s1_dout_0; // @[ICache.scala:473:21] wire [31:0] s1_dout_1; // @[ICache.scala:473:21] wire [31:0] s1_dout_2; // @[ICache.scala:473:21] wire [31:0] s1_dout_3; // @[ICache.scala:473:21] wire [31:0] s1_dout_4; // @[ICache.scala:473:21] wire [31:0] s1_dout_5; // @[ICache.scala:473:21] wire [31:0] s1_dout_6; // @[ICache.scala:473:21] wire [31:0] s1_dout_7; // @[ICache.scala:473:21] wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_1 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_2 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_3 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_4 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_5 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_6 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] s1_idx_7 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_1 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_2 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_3 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_4 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_5 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_6 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [19:0] s1_tag_7 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire _scratchpadHit_T_3 = _scratchpadHit_T_2 == 3'h0; // @[package.scala:163:13] wire [8:0] _scratchpadHit_T_5 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_16 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_27 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_38 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_49 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_60 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_71 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _scratchpadHit_T_82 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [8:0] _s1_scratchpad_hit_T_1 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90] wire [2:0] _scratchpadHit_T_7 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_18 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_29 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_40 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_51 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_62 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_73 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire [2:0] _scratchpadHit_T_84 = io_s1_paddr_0[14:12]; // @[package.scala:163:13] wire _scratchpadHit_T_8 = _scratchpadHit_T_7 == 3'h0; // @[package.scala:163:13] wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[ICache.scala:508:29, :859:21] wire [8:0] _s1_vb_T_1 = {2'h0, _s1_vb_T}; // @[ICache.scala:508:{29,46}] wire [511:0] _s1_vb_T_2 = vb_array >> _s1_vb_T_1; // @[ICache.scala:448:25, :508:{25,46}] wire _s1_vb_T_3 = _s1_vb_T_2[0]; // @[ICache.scala:508:25] wire s1_vb = _s1_vb_T_3; // @[ICache.scala:508:{25,71}] wire tl_error = _rockettile_icache_tag_array_RW0_rdata[20]; // @[package.scala:163:13] wire _s1_tl_error_0_T = tl_error; // @[package.scala:163:13] wire [19:0] tag = _rockettile_icache_tag_array_RW0_rdata[19:0]; // @[package.scala:163:13] wire _tagMatch_T = tag == s1_tag; // @[package.scala:163:13] wire tagMatch = s1_vb & _tagMatch_T; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_0_T = tagMatch; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_0_T_1 = tagMatch & _s1_tl_error_0_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_0 = _s1_tl_error_0_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_0 = _s1_tag_hit_0_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_14 = _scratchpadHit_T_13 == 3'h1; // @[package.scala:163:13] wire _scratchpadHit_T_19 = _scratchpadHit_T_18 == 3'h1; // @[package.scala:163:13] wire [6:0] _s1_vb_T_5 = {1'h1, s1_idx_1}; // @[ICache.scala:508:29, :859:21] wire [8:0] _s1_vb_T_6 = {2'h0, _s1_vb_T_5}; // @[ICache.scala:508:{29,46}] wire [511:0] _s1_vb_T_7 = vb_array >> _s1_vb_T_6; // @[ICache.scala:448:25, :508:{25,46}] wire _s1_vb_T_8 = _s1_vb_T_7[0]; // @[ICache.scala:508:25] wire s1_vb_1 = _s1_vb_T_8; // @[ICache.scala:508:{25,71}] wire tl_error_1 = _rockettile_icache_tag_array_RW0_rdata[41]; // @[package.scala:163:13] wire _s1_tl_error_1_T = tl_error_1; // @[package.scala:163:13] wire [19:0] tag_1 = _rockettile_icache_tag_array_RW0_rdata[40:21]; // @[package.scala:163:13] wire _tagMatch_T_1 = tag_1 == s1_tag_1; // @[package.scala:163:13] wire tagMatch_1 = s1_vb_1 & _tagMatch_T_1; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_1_T = tagMatch_1; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_1_T_1 = tagMatch_1 & _s1_tl_error_1_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_1 = _s1_tl_error_1_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_1 = _s1_tag_hit_1_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_25 = _scratchpadHit_T_24 == 3'h2; // @[package.scala:163:13] wire _scratchpadHit_T_30 = _scratchpadHit_T_29 == 3'h2; // @[package.scala:163:13] wire [7:0] _s1_vb_T_10 = {2'h2, s1_idx_2}; // @[ICache.scala:508:29, :859:21] wire [8:0] _s1_vb_T_11 = {1'h0, _s1_vb_T_10}; // @[ICache.scala:508:{29,46}] wire [511:0] _s1_vb_T_12 = vb_array >> _s1_vb_T_11; // @[ICache.scala:448:25, :508:{25,46}] wire _s1_vb_T_13 = _s1_vb_T_12[0]; // @[ICache.scala:508:25] wire s1_vb_2 = _s1_vb_T_13; // @[ICache.scala:508:{25,71}] wire tl_error_2 = _rockettile_icache_tag_array_RW0_rdata[62]; // @[package.scala:163:13] wire _s1_tl_error_2_T = tl_error_2; // @[package.scala:163:13] wire [19:0] tag_2 = _rockettile_icache_tag_array_RW0_rdata[61:42]; // @[package.scala:163:13] wire _tagMatch_T_2 = tag_2 == s1_tag_2; // @[package.scala:163:13] wire tagMatch_2 = s1_vb_2 & _tagMatch_T_2; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_2_T = tagMatch_2; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_2_T_1 = tagMatch_2 & _s1_tl_error_2_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_2 = _s1_tl_error_2_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_2 = _s1_tag_hit_2_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_36 = _scratchpadHit_T_35 == 3'h3; // @[package.scala:163:13] wire _scratchpadHit_T_41 = _scratchpadHit_T_40 == 3'h3; // @[package.scala:163:13] wire [7:0] _s1_vb_T_15 = {2'h3, s1_idx_3}; // @[ICache.scala:508:29, :859:21] wire [8:0] _s1_vb_T_16 = {1'h0, _s1_vb_T_15}; // @[ICache.scala:508:{29,46}] wire [511:0] _s1_vb_T_17 = vb_array >> _s1_vb_T_16; // @[ICache.scala:448:25, :508:{25,46}] wire _s1_vb_T_18 = _s1_vb_T_17[0]; // @[ICache.scala:508:25] wire s1_vb_3 = _s1_vb_T_18; // @[ICache.scala:508:{25,71}] wire tl_error_3 = _rockettile_icache_tag_array_RW0_rdata[83]; // @[package.scala:163:13] wire _s1_tl_error_3_T = tl_error_3; // @[package.scala:163:13] wire [19:0] tag_3 = _rockettile_icache_tag_array_RW0_rdata[82:63]; // @[package.scala:163:13] wire _tagMatch_T_3 = tag_3 == s1_tag_3; // @[package.scala:163:13] wire tagMatch_3 = s1_vb_3 & _tagMatch_T_3; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_3_T = tagMatch_3; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_3_T_1 = tagMatch_3 & _s1_tl_error_3_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_3 = _s1_tl_error_3_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_3 = _s1_tag_hit_3_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_47 = _scratchpadHit_T_46 == 3'h4; // @[package.scala:163:13] wire _scratchpadHit_T_52 = _scratchpadHit_T_51 == 3'h4; // @[package.scala:163:13] wire [8:0] _s1_vb_T_20 = {3'h4, s1_idx_4}; // @[ICache.scala:508:29, :859:21] wire [511:0] _s1_vb_T_21 = vb_array >> _s1_vb_T_20; // @[ICache.scala:448:25, :508:{25,29}] wire _s1_vb_T_22 = _s1_vb_T_21[0]; // @[ICache.scala:508:25] wire s1_vb_4 = _s1_vb_T_22; // @[ICache.scala:508:{25,71}] wire tl_error_4 = _rockettile_icache_tag_array_RW0_rdata[104]; // @[package.scala:163:13] wire _s1_tl_error_4_T = tl_error_4; // @[package.scala:163:13] wire [19:0] tag_4 = _rockettile_icache_tag_array_RW0_rdata[103:84]; // @[package.scala:163:13] wire _tagMatch_T_4 = tag_4 == s1_tag_4; // @[package.scala:163:13] wire tagMatch_4 = s1_vb_4 & _tagMatch_T_4; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_4_T = tagMatch_4; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_4_T_1 = tagMatch_4 & _s1_tl_error_4_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_4 = _s1_tl_error_4_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_4 = _s1_tag_hit_4_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_58 = _scratchpadHit_T_57 == 3'h5; // @[package.scala:163:13] wire _scratchpadHit_T_63 = _scratchpadHit_T_62 == 3'h5; // @[package.scala:163:13] wire [8:0] _s1_vb_T_24 = {3'h5, s1_idx_5}; // @[ICache.scala:508:29, :859:21] wire [511:0] _s1_vb_T_25 = vb_array >> _s1_vb_T_24; // @[ICache.scala:448:25, :508:{25,29}] wire _s1_vb_T_26 = _s1_vb_T_25[0]; // @[ICache.scala:508:25] wire s1_vb_5 = _s1_vb_T_26; // @[ICache.scala:508:{25,71}] wire tl_error_5 = _rockettile_icache_tag_array_RW0_rdata[125]; // @[package.scala:163:13] wire _s1_tl_error_5_T = tl_error_5; // @[package.scala:163:13] wire [19:0] tag_5 = _rockettile_icache_tag_array_RW0_rdata[124:105]; // @[package.scala:163:13] wire _tagMatch_T_5 = tag_5 == s1_tag_5; // @[package.scala:163:13] wire tagMatch_5 = s1_vb_5 & _tagMatch_T_5; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_5_T = tagMatch_5; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_5_T_1 = tagMatch_5 & _s1_tl_error_5_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_5 = _s1_tl_error_5_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_5 = _s1_tag_hit_5_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_69 = _scratchpadHit_T_68 == 3'h6; // @[package.scala:163:13] wire _scratchpadHit_T_74 = _scratchpadHit_T_73 == 3'h6; // @[package.scala:163:13] wire [8:0] _s1_vb_T_28 = {3'h6, s1_idx_6}; // @[ICache.scala:508:29, :859:21] wire [511:0] _s1_vb_T_29 = vb_array >> _s1_vb_T_28; // @[ICache.scala:448:25, :508:{25,29}] wire _s1_vb_T_30 = _s1_vb_T_29[0]; // @[ICache.scala:508:25] wire s1_vb_6 = _s1_vb_T_30; // @[ICache.scala:508:{25,71}] wire tl_error_6 = _rockettile_icache_tag_array_RW0_rdata[146]; // @[package.scala:163:13] wire _s1_tl_error_6_T = tl_error_6; // @[package.scala:163:13] wire [19:0] tag_6 = _rockettile_icache_tag_array_RW0_rdata[145:126]; // @[package.scala:163:13] wire _tagMatch_T_6 = tag_6 == s1_tag_6; // @[package.scala:163:13] wire tagMatch_6 = s1_vb_6 & _tagMatch_T_6; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_6_T = tagMatch_6; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_6_T_1 = tagMatch_6 & _s1_tl_error_6_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_6 = _s1_tl_error_6_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_6 = _s1_tag_hit_6_T; // @[ICache.scala:345:24, :519:31] wire _scratchpadHit_T_80 = &_scratchpadHit_T_79; // @[package.scala:163:13] wire _scratchpadHit_T_85 = &_scratchpadHit_T_84; // @[package.scala:163:13] wire [8:0] _s1_vb_T_32 = {3'h7, s1_idx_7}; // @[ICache.scala:508:29, :859:21] wire [511:0] _s1_vb_T_33 = vb_array >> _s1_vb_T_32; // @[ICache.scala:448:25, :508:{25,29}] wire _s1_vb_T_34 = _s1_vb_T_33[0]; // @[ICache.scala:508:25] wire s1_vb_7 = _s1_vb_T_34; // @[ICache.scala:508:{25,71}] wire tl_error_7 = _rockettile_icache_tag_array_RW0_rdata[167]; // @[package.scala:163:13] wire _s1_tl_error_7_T = tl_error_7; // @[package.scala:163:13] wire [19:0] tag_7 = _rockettile_icache_tag_array_RW0_rdata[166:147]; // @[package.scala:163:13] wire _tagMatch_T_7 = tag_7 == s1_tag_7; // @[package.scala:163:13] wire tagMatch_7 = s1_vb_7 & _tagMatch_T_7; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_7_T = tagMatch_7; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_7_T_1 = tagMatch_7 & _s1_tl_error_7_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_7 = _s1_tl_error_7_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_7 = _s1_tag_hit_7_T; // @[ICache.scala:345:24, :519:31]
Generate the Verilog code corresponding to this FIRRTL code module IntToFPUnit_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>} connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.sfence.bits.hg invalidate io.resp.bits.sfence.bits.hv invalidate io.resp.bits.sfence.bits.asid invalidate io.resp.bits.sfence.bits.addr invalidate io.resp.bits.sfence.bits.rs2 invalidate io.resp.bits.sfence.bits.rs1 invalidate io.resp.bits.sfence.valid invalidate io.resp.bits.mxcpt.bits invalidate io.resp.bits.mxcpt.valid invalidate io.resp.bits.addr invalidate io.resp.bits.fflags.bits.flags invalidate io.resp.bits.fflags.bits.uop.debug_tsrc invalidate io.resp.bits.fflags.bits.uop.debug_fsrc invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.resp.bits.fflags.bits.uop.bp_debug_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.resp.bits.fflags.bits.uop.fp_single invalidate io.resp.bits.fflags.bits.uop.fp_val invalidate io.resp.bits.fflags.bits.uop.frs3_en invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate io.resp.bits.fflags.bits.uop.dst_rtype invalidate io.resp.bits.fflags.bits.uop.ldst_val invalidate io.resp.bits.fflags.bits.uop.lrs3 invalidate io.resp.bits.fflags.bits.uop.lrs2 invalidate io.resp.bits.fflags.bits.uop.lrs1 invalidate io.resp.bits.fflags.bits.uop.ldst invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.resp.bits.fflags.bits.uop.flush_on_commit invalidate io.resp.bits.fflags.bits.uop.is_unique invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.resp.bits.fflags.bits.uop.uses_stq invalidate io.resp.bits.fflags.bits.uop.uses_ldq invalidate io.resp.bits.fflags.bits.uop.is_amo invalidate io.resp.bits.fflags.bits.uop.is_fencei invalidate io.resp.bits.fflags.bits.uop.is_fence invalidate io.resp.bits.fflags.bits.uop.mem_signed invalidate io.resp.bits.fflags.bits.uop.mem_size invalidate io.resp.bits.fflags.bits.uop.mem_cmd invalidate io.resp.bits.fflags.bits.uop.bypassable invalidate io.resp.bits.fflags.bits.uop.exc_cause invalidate io.resp.bits.fflags.bits.uop.exception invalidate io.resp.bits.fflags.bits.uop.stale_pdst invalidate io.resp.bits.fflags.bits.uop.ppred_busy invalidate io.resp.bits.fflags.bits.uop.prs3_busy invalidate io.resp.bits.fflags.bits.uop.prs2_busy invalidate io.resp.bits.fflags.bits.uop.prs1_busy invalidate io.resp.bits.fflags.bits.uop.ppred invalidate io.resp.bits.fflags.bits.uop.prs3 invalidate io.resp.bits.fflags.bits.uop.prs2 invalidate io.resp.bits.fflags.bits.uop.prs1 invalidate io.resp.bits.fflags.bits.uop.pdst invalidate io.resp.bits.fflags.bits.uop.rxq_idx invalidate io.resp.bits.fflags.bits.uop.stq_idx invalidate io.resp.bits.fflags.bits.uop.ldq_idx invalidate io.resp.bits.fflags.bits.uop.rob_idx invalidate io.resp.bits.fflags.bits.uop.csr_addr invalidate io.resp.bits.fflags.bits.uop.imm_packed invalidate io.resp.bits.fflags.bits.uop.taken invalidate io.resp.bits.fflags.bits.uop.pc_lob invalidate io.resp.bits.fflags.bits.uop.edge_inst invalidate io.resp.bits.fflags.bits.uop.ftq_idx invalidate io.resp.bits.fflags.bits.uop.br_tag invalidate io.resp.bits.fflags.bits.uop.br_mask invalidate io.resp.bits.fflags.bits.uop.is_sfb invalidate io.resp.bits.fflags.bits.uop.is_jal invalidate io.resp.bits.fflags.bits.uop.is_jalr invalidate io.resp.bits.fflags.bits.uop.is_br invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.resp.bits.fflags.bits.uop.iw_state invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate io.resp.bits.fflags.bits.uop.fu_code invalidate io.resp.bits.fflags.bits.uop.iq_type invalidate io.resp.bits.fflags.bits.uop.debug_pc invalidate io.resp.bits.fflags.bits.uop.is_rvc invalidate io.resp.bits.fflags.bits.uop.debug_inst invalidate io.resp.bits.fflags.bits.uop.inst invalidate io.resp.bits.fflags.bits.uop.uopc invalidate io.resp.bits.fflags.valid invalidate io.resp.bits.data invalidate io.resp.bits.predicated invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.req.ready, UInt<1>(0h1) wire _r_valids_WIRE : UInt<1>[2] connect _r_valids_WIRE[0], UInt<1>(0h0) connect _r_valids_WIRE[1], UInt<1>(0h0) regreset r_valids : UInt<1>[2], clock, reset, _r_valids_WIRE reg r_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[2], clock node _r_valids_0_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _r_valids_0_T_1 = neq(_r_valids_0_T, UInt<1>(0h0)) node _r_valids_0_T_2 = eq(_r_valids_0_T_1, UInt<1>(0h0)) node _r_valids_0_T_3 = and(io.req.valid, _r_valids_0_T_2) node _r_valids_0_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_0_T_5 = and(_r_valids_0_T_3, _r_valids_0_T_4) connect r_valids[0], _r_valids_0_T_5 connect r_uops[0], io.req.bits.uop node _r_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_0_br_mask_T_1 = and(io.req.bits.uop.br_mask, _r_uops_0_br_mask_T) connect r_uops[0].br_mask, _r_uops_0_br_mask_T_1 node _r_valids_1_T = and(io.brupdate.b1.mispredict_mask, r_uops[0].br_mask) node _r_valids_1_T_1 = neq(_r_valids_1_T, UInt<1>(0h0)) node _r_valids_1_T_2 = eq(_r_valids_1_T_1, UInt<1>(0h0)) node _r_valids_1_T_3 = and(r_valids[0], _r_valids_1_T_2) node _r_valids_1_T_4 = eq(io.req.bits.kill, UInt<1>(0h0)) node _r_valids_1_T_5 = and(_r_valids_1_T_3, _r_valids_1_T_4) connect r_valids[1], _r_valids_1_T_5 connect r_uops[1], r_uops[0] node _r_uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _r_uops_1_br_mask_T_1 = and(r_uops[0].br_mask, _r_uops_1_br_mask_T) connect r_uops[1].br_mask, _r_uops_1_br_mask_T_1 node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_uops[1].br_mask) node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0)) node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0)) node _io_resp_valid_T_3 = and(r_valids[1], _io_resp_valid_T_2) connect io.resp.valid, _io_resp_valid_T_3 connect io.resp.bits.predicated, UInt<1>(0h0) connect io.resp.bits.uop, r_uops[1] node _io_resp_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_resp_bits_uop_br_mask_T_1 = and(r_uops[1].br_mask, _io_resp_bits_uop_br_mask_T) connect io.resp.bits.uop.br_mask, _io_resp_bits_uop_br_mask_T_1 inst fp_decoder of UOPCodeFPUDecoder_2 connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.uopc, io.req.bits.uop.uopc node _fp_rm_T = bits(io.req.bits.uop.imm_packed, 2, 0) node _fp_rm_T_1 = eq(_fp_rm_T, UInt<3>(0h7)) node _fp_rm_T_2 = bits(io.req.bits.uop.imm_packed, 2, 0) node fp_rm = mux(_fp_rm_T_1, io.fcsr_rm, _fp_rm_T_2) wire req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect req.vec, fp_decoder.io.sigs.vec connect req.wflags, fp_decoder.io.sigs.wflags connect req.sqrt, fp_decoder.io.sigs.sqrt connect req.div, fp_decoder.io.sigs.div connect req.fma, fp_decoder.io.sigs.fma connect req.fastpipe, fp_decoder.io.sigs.fastpipe connect req.toint, fp_decoder.io.sigs.toint connect req.fromint, fp_decoder.io.sigs.fromint connect req.typeTagOut, fp_decoder.io.sigs.typeTagOut connect req.typeTagIn, fp_decoder.io.sigs.typeTagIn connect req.swap23, fp_decoder.io.sigs.swap23 connect req.swap12, fp_decoder.io.sigs.swap12 connect req.ren3, fp_decoder.io.sigs.ren3 connect req.ren2, fp_decoder.io.sigs.ren2 connect req.ren1, fp_decoder.io.sigs.ren1 connect req.wen, fp_decoder.io.sigs.wen connect req.ldst, fp_decoder.io.sigs.ldst connect req.rm, fp_rm node _req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node req_in1_prev_unswizzled_hi = cat(_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1) node req_in1_prev_unswizzled = cat(req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2) node req_in1_prev_prev_sign = bits(req_in1_prev_unswizzled, 32, 32) node req_in1_prev_prev_fractIn = bits(req_in1_prev_unswizzled, 22, 0) node req_in1_prev_prev_expIn = bits(req_in1_prev_unswizzled, 31, 23) node _req_in1_prev_prev_fractOut_T = shl(req_in1_prev_prev_fractIn, 53) node req_in1_prev_prev_fractOut = shr(_req_in1_prev_prev_fractOut_T, 24) node req_in1_prev_prev_expOut_expCode = bits(req_in1_prev_prev_expIn, 8, 6) node _req_in1_prev_prev_expOut_commonCase_T = add(req_in1_prev_prev_expIn, UInt<12>(0h800)) node _req_in1_prev_prev_expOut_commonCase_T_1 = tail(_req_in1_prev_prev_expOut_commonCase_T, 1) node _req_in1_prev_prev_expOut_commonCase_T_2 = sub(_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in1_prev_prev_expOut_commonCase = tail(_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _req_in1_prev_prev_expOut_T = eq(req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in1_prev_prev_expOut_T_1 = geq(req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in1_prev_prev_expOut_T_2 = or(_req_in1_prev_prev_expOut_T, _req_in1_prev_prev_expOut_T_1) node _req_in1_prev_prev_expOut_T_3 = bits(req_in1_prev_prev_expOut_commonCase, 8, 0) node _req_in1_prev_prev_expOut_T_4 = cat(req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3) node _req_in1_prev_prev_expOut_T_5 = bits(req_in1_prev_prev_expOut_commonCase, 11, 0) node req_in1_prev_prev_expOut = mux(_req_in1_prev_prev_expOut_T_2, _req_in1_prev_prev_expOut_T_4, _req_in1_prev_prev_expOut_T_5) node req_in1_prev_prev_hi = cat(req_in1_prev_prev_sign, req_in1_prev_prev_expOut) node req_in1_floats_0 = cat(req_in1_prev_prev_hi, req_in1_prev_prev_fractOut) node _req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node req_in1_prev_isbox = andr(_req_in1_prev_isbox_T) node req_in1_oks_0 = and(req_in1_prev_isbox, UInt<1>(0h1)) node _req_in1_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx = bits(_req_in1_truncIdx_T, 0, 0) node _req_in1_T = eq(req_in1_truncIdx, UInt<1>(0h1)) node _req_in1_T_1 = mux(_req_in1_T, UInt<1>(0h1), req_in1_oks_0) node _req_in1_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in1_truncIdx_1 = bits(_req_in1_truncIdx_T_1, 0, 0) node _req_in1_T_2 = eq(req_in1_truncIdx_1, UInt<1>(0h1)) node _req_in1_T_3 = mux(_req_in1_T_2, io.req.bits.rs1_data, req_in1_floats_0) node _req_in1_T_4 = mux(_req_in1_T_1, _req_in1_T_3, UInt<65>(0he008000000000000)) connect req.in1, _req_in1_T_4 node _req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node req_in2_prev_unswizzled_hi = cat(_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1) node req_in2_prev_unswizzled = cat(req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2) node req_in2_prev_prev_sign = bits(req_in2_prev_unswizzled, 32, 32) node req_in2_prev_prev_fractIn = bits(req_in2_prev_unswizzled, 22, 0) node req_in2_prev_prev_expIn = bits(req_in2_prev_unswizzled, 31, 23) node _req_in2_prev_prev_fractOut_T = shl(req_in2_prev_prev_fractIn, 53) node req_in2_prev_prev_fractOut = shr(_req_in2_prev_prev_fractOut_T, 24) node req_in2_prev_prev_expOut_expCode = bits(req_in2_prev_prev_expIn, 8, 6) node _req_in2_prev_prev_expOut_commonCase_T = add(req_in2_prev_prev_expIn, UInt<12>(0h800)) node _req_in2_prev_prev_expOut_commonCase_T_1 = tail(_req_in2_prev_prev_expOut_commonCase_T, 1) node _req_in2_prev_prev_expOut_commonCase_T_2 = sub(_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node req_in2_prev_prev_expOut_commonCase = tail(_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _req_in2_prev_prev_expOut_T = eq(req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _req_in2_prev_prev_expOut_T_1 = geq(req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _req_in2_prev_prev_expOut_T_2 = or(_req_in2_prev_prev_expOut_T, _req_in2_prev_prev_expOut_T_1) node _req_in2_prev_prev_expOut_T_3 = bits(req_in2_prev_prev_expOut_commonCase, 8, 0) node _req_in2_prev_prev_expOut_T_4 = cat(req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3) node _req_in2_prev_prev_expOut_T_5 = bits(req_in2_prev_prev_expOut_commonCase, 11, 0) node req_in2_prev_prev_expOut = mux(_req_in2_prev_prev_expOut_T_2, _req_in2_prev_prev_expOut_T_4, _req_in2_prev_prev_expOut_T_5) node req_in2_prev_prev_hi = cat(req_in2_prev_prev_sign, req_in2_prev_prev_expOut) node req_in2_floats_0 = cat(req_in2_prev_prev_hi, req_in2_prev_prev_fractOut) node _req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node req_in2_prev_isbox = andr(_req_in2_prev_isbox_T) node req_in2_oks_0 = and(req_in2_prev_isbox, UInt<1>(0h1)) node _req_in2_truncIdx_T = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx = bits(_req_in2_truncIdx_T, 0, 0) node _req_in2_T = eq(req_in2_truncIdx, UInt<1>(0h1)) node _req_in2_T_1 = mux(_req_in2_T, UInt<1>(0h1), req_in2_oks_0) node _req_in2_truncIdx_T_1 = or(fp_decoder.io.sigs.typeTagIn, UInt<1>(0h0)) node req_in2_truncIdx_1 = bits(_req_in2_truncIdx_T_1, 0, 0) node _req_in2_T_2 = eq(req_in2_truncIdx_1, UInt<1>(0h1)) node _req_in2_T_3 = mux(_req_in2_T_2, io.req.bits.rs2_data, req_in2_floats_0) node _req_in2_T_4 = mux(_req_in2_T_1, _req_in2_T_3, UInt<65>(0he008000000000000)) connect req.in2, _req_in2_T_4 invalidate req.in3 node _req_typ_T = bits(io.req.bits.uop.imm_packed, 9, 8) connect req.typ, _req_typ_T invalidate req.fmt invalidate req.fmaCmd node _T = and(io.req.valid, fp_decoder.io.sigs.fromint) node _T_1 = bits(req.in1, 64, 64) node _T_2 = and(_T, _T_1) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] IntToFP integer input has 65th high-order bit set!\n at functional-unit.scala:618 assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(fp_decoder.io.sigs.fromint, UInt<1>(0h0)) node _T_8 = and(io.req.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: [func] Only support fromInt micro-ops.\n at functional-unit.scala:621 assert (!(io.req.valid && !fp_ctrl.fromint),\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 inst ifpu of IntToFP_3 connect ifpu.clock, clock connect ifpu.reset, reset connect ifpu.io.in.valid, io.req.valid connect ifpu.io.in.bits.in1, req.in1 connect ifpu.io.in.bits.typ, req.typ connect ifpu.io.in.bits.rm, req.rm connect ifpu.io.in.bits.vec, req.vec connect ifpu.io.in.bits.wflags, req.wflags connect ifpu.io.in.bits.sqrt, req.sqrt connect ifpu.io.in.bits.div, req.div connect ifpu.io.in.bits.fma, req.fma connect ifpu.io.in.bits.fastpipe, req.fastpipe connect ifpu.io.in.bits.toint, req.toint connect ifpu.io.in.bits.fromint, req.fromint connect ifpu.io.in.bits.typeTagOut, req.typeTagOut connect ifpu.io.in.bits.typeTagIn, req.typeTagIn connect ifpu.io.in.bits.swap23, req.swap23 connect ifpu.io.in.bits.swap12, req.swap12 connect ifpu.io.in.bits.ren3, req.ren3 connect ifpu.io.in.bits.ren2, req.ren2 connect ifpu.io.in.bits.ren1, req.ren1 connect ifpu.io.in.bits.wen, req.wen connect ifpu.io.in.bits.ldst, req.ldst connect ifpu.io.in.bits.in1, io.req.bits.rs1_data node _out_double_T = eq(fp_decoder.io.sigs.typeTagOut, UInt<1>(0h1)) regreset out_double_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_v, io.req.valid reg out_double_pipe_b : UInt<1>, clock when io.req.valid : connect out_double_pipe_b, _out_double_T regreset out_double_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect out_double_pipe_pipe_v, out_double_pipe_v reg out_double_pipe_pipe_b : UInt<1>, clock when out_double_pipe_v : connect out_double_pipe_pipe_b, out_double_pipe_b wire out_double_pipe_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect out_double_pipe_pipe_out.valid, out_double_pipe_pipe_v connect out_double_pipe_pipe_out.bits, out_double_pipe_pipe_b node _io_resp_bits_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_1 = bits(ifpu.io.out.bits.data, 31, 31) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_2 = bits(ifpu.io.out.bits.data, 32, 32) node _io_resp_bits_data_opts_bigger_swizzledNaN_T_3 = bits(ifpu.io.out.bits.data, 30, 0) node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_2) node io_resp_bits_data_opts_bigger_swizzledNaN_lo = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi, _io_resp_bits_data_opts_bigger_swizzledNaN_T_3) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_1) node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T) node io_resp_bits_data_opts_bigger_swizzledNaN_hi = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo) node io_resp_bits_data_opts_bigger_swizzledNaN = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi, io_resp_bits_data_opts_bigger_swizzledNaN_lo) node _io_resp_bits_data_opts_bigger_T = andr(UInt<3>(0h7)) node io_resp_bits_data_opts_bigger = mux(_io_resp_bits_data_opts_bigger_T, io_resp_bits_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) node io_resp_bits_data_opts_0 = or(io_resp_bits_data_opts_bigger, UInt<1>(0h0)) node _io_resp_bits_data_T = eq(out_double_pipe_pipe_out.bits, UInt<1>(0h1)) node _io_resp_bits_data_T_1 = mux(_io_resp_bits_data_T, ifpu.io.out.bits.data, io_resp_bits_data_opts_0) connect io.resp.bits.data, _io_resp_bits_data_T_1 connect io.resp.bits.fflags.valid, ifpu.io.out.valid connect io.resp.bits.fflags.bits.uop.debug_tsrc, io.resp.bits.uop.debug_tsrc connect io.resp.bits.fflags.bits.uop.debug_fsrc, io.resp.bits.uop.debug_fsrc connect io.resp.bits.fflags.bits.uop.bp_xcpt_if, io.resp.bits.uop.bp_xcpt_if connect io.resp.bits.fflags.bits.uop.bp_debug_if, io.resp.bits.uop.bp_debug_if connect io.resp.bits.fflags.bits.uop.xcpt_ma_if, io.resp.bits.uop.xcpt_ma_if connect io.resp.bits.fflags.bits.uop.xcpt_ae_if, io.resp.bits.uop.xcpt_ae_if connect io.resp.bits.fflags.bits.uop.xcpt_pf_if, io.resp.bits.uop.xcpt_pf_if connect io.resp.bits.fflags.bits.uop.fp_single, io.resp.bits.uop.fp_single connect io.resp.bits.fflags.bits.uop.fp_val, io.resp.bits.uop.fp_val connect io.resp.bits.fflags.bits.uop.frs3_en, io.resp.bits.uop.frs3_en connect io.resp.bits.fflags.bits.uop.lrs2_rtype, io.resp.bits.uop.lrs2_rtype connect io.resp.bits.fflags.bits.uop.lrs1_rtype, io.resp.bits.uop.lrs1_rtype connect io.resp.bits.fflags.bits.uop.dst_rtype, io.resp.bits.uop.dst_rtype connect io.resp.bits.fflags.bits.uop.ldst_val, io.resp.bits.uop.ldst_val connect io.resp.bits.fflags.bits.uop.lrs3, io.resp.bits.uop.lrs3 connect io.resp.bits.fflags.bits.uop.lrs2, io.resp.bits.uop.lrs2 connect io.resp.bits.fflags.bits.uop.lrs1, io.resp.bits.uop.lrs1 connect io.resp.bits.fflags.bits.uop.ldst, io.resp.bits.uop.ldst connect io.resp.bits.fflags.bits.uop.ldst_is_rs1, io.resp.bits.uop.ldst_is_rs1 connect io.resp.bits.fflags.bits.uop.flush_on_commit, io.resp.bits.uop.flush_on_commit connect io.resp.bits.fflags.bits.uop.is_unique, io.resp.bits.uop.is_unique connect io.resp.bits.fflags.bits.uop.is_sys_pc2epc, io.resp.bits.uop.is_sys_pc2epc connect io.resp.bits.fflags.bits.uop.uses_stq, io.resp.bits.uop.uses_stq connect io.resp.bits.fflags.bits.uop.uses_ldq, io.resp.bits.uop.uses_ldq connect io.resp.bits.fflags.bits.uop.is_amo, io.resp.bits.uop.is_amo connect io.resp.bits.fflags.bits.uop.is_fencei, io.resp.bits.uop.is_fencei connect io.resp.bits.fflags.bits.uop.is_fence, io.resp.bits.uop.is_fence connect io.resp.bits.fflags.bits.uop.mem_signed, io.resp.bits.uop.mem_signed connect io.resp.bits.fflags.bits.uop.mem_size, io.resp.bits.uop.mem_size connect io.resp.bits.fflags.bits.uop.mem_cmd, io.resp.bits.uop.mem_cmd connect io.resp.bits.fflags.bits.uop.bypassable, io.resp.bits.uop.bypassable connect io.resp.bits.fflags.bits.uop.exc_cause, io.resp.bits.uop.exc_cause connect io.resp.bits.fflags.bits.uop.exception, io.resp.bits.uop.exception connect io.resp.bits.fflags.bits.uop.stale_pdst, io.resp.bits.uop.stale_pdst connect io.resp.bits.fflags.bits.uop.ppred_busy, io.resp.bits.uop.ppred_busy connect io.resp.bits.fflags.bits.uop.prs3_busy, io.resp.bits.uop.prs3_busy connect io.resp.bits.fflags.bits.uop.prs2_busy, io.resp.bits.uop.prs2_busy connect io.resp.bits.fflags.bits.uop.prs1_busy, io.resp.bits.uop.prs1_busy connect io.resp.bits.fflags.bits.uop.ppred, io.resp.bits.uop.ppred connect io.resp.bits.fflags.bits.uop.prs3, io.resp.bits.uop.prs3 connect io.resp.bits.fflags.bits.uop.prs2, io.resp.bits.uop.prs2 connect io.resp.bits.fflags.bits.uop.prs1, io.resp.bits.uop.prs1 connect io.resp.bits.fflags.bits.uop.pdst, io.resp.bits.uop.pdst connect io.resp.bits.fflags.bits.uop.rxq_idx, io.resp.bits.uop.rxq_idx connect io.resp.bits.fflags.bits.uop.stq_idx, io.resp.bits.uop.stq_idx connect io.resp.bits.fflags.bits.uop.ldq_idx, io.resp.bits.uop.ldq_idx connect io.resp.bits.fflags.bits.uop.rob_idx, io.resp.bits.uop.rob_idx connect io.resp.bits.fflags.bits.uop.csr_addr, io.resp.bits.uop.csr_addr connect io.resp.bits.fflags.bits.uop.imm_packed, io.resp.bits.uop.imm_packed connect io.resp.bits.fflags.bits.uop.taken, io.resp.bits.uop.taken connect io.resp.bits.fflags.bits.uop.pc_lob, io.resp.bits.uop.pc_lob connect io.resp.bits.fflags.bits.uop.edge_inst, io.resp.bits.uop.edge_inst connect io.resp.bits.fflags.bits.uop.ftq_idx, io.resp.bits.uop.ftq_idx connect io.resp.bits.fflags.bits.uop.br_tag, io.resp.bits.uop.br_tag connect io.resp.bits.fflags.bits.uop.br_mask, io.resp.bits.uop.br_mask connect io.resp.bits.fflags.bits.uop.is_sfb, io.resp.bits.uop.is_sfb connect io.resp.bits.fflags.bits.uop.is_jal, io.resp.bits.uop.is_jal connect io.resp.bits.fflags.bits.uop.is_jalr, io.resp.bits.uop.is_jalr connect io.resp.bits.fflags.bits.uop.is_br, io.resp.bits.uop.is_br connect io.resp.bits.fflags.bits.uop.iw_p2_poisoned, io.resp.bits.uop.iw_p2_poisoned connect io.resp.bits.fflags.bits.uop.iw_p1_poisoned, io.resp.bits.uop.iw_p1_poisoned connect io.resp.bits.fflags.bits.uop.iw_state, io.resp.bits.uop.iw_state connect io.resp.bits.fflags.bits.uop.ctrl.is_std, io.resp.bits.uop.ctrl.is_std connect io.resp.bits.fflags.bits.uop.ctrl.is_sta, io.resp.bits.uop.ctrl.is_sta connect io.resp.bits.fflags.bits.uop.ctrl.is_load, io.resp.bits.uop.ctrl.is_load connect io.resp.bits.fflags.bits.uop.ctrl.csr_cmd, io.resp.bits.uop.ctrl.csr_cmd connect io.resp.bits.fflags.bits.uop.ctrl.fcn_dw, io.resp.bits.uop.ctrl.fcn_dw connect io.resp.bits.fflags.bits.uop.ctrl.op_fcn, io.resp.bits.uop.ctrl.op_fcn connect io.resp.bits.fflags.bits.uop.ctrl.imm_sel, io.resp.bits.uop.ctrl.imm_sel connect io.resp.bits.fflags.bits.uop.ctrl.op2_sel, io.resp.bits.uop.ctrl.op2_sel connect io.resp.bits.fflags.bits.uop.ctrl.op1_sel, io.resp.bits.uop.ctrl.op1_sel connect io.resp.bits.fflags.bits.uop.ctrl.br_type, io.resp.bits.uop.ctrl.br_type connect io.resp.bits.fflags.bits.uop.fu_code, io.resp.bits.uop.fu_code connect io.resp.bits.fflags.bits.uop.iq_type, io.resp.bits.uop.iq_type connect io.resp.bits.fflags.bits.uop.debug_pc, io.resp.bits.uop.debug_pc connect io.resp.bits.fflags.bits.uop.is_rvc, io.resp.bits.uop.is_rvc connect io.resp.bits.fflags.bits.uop.debug_inst, io.resp.bits.uop.debug_inst connect io.resp.bits.fflags.bits.uop.inst, io.resp.bits.uop.inst connect io.resp.bits.fflags.bits.uop.uopc, io.resp.bits.uop.uopc connect io.resp.bits.fflags.bits.flags, ifpu.io.out.bits.exc
module IntToFPUnit_1( // @[functional-unit.scala:591:7] input clock, // @[functional-unit.scala:591:7] input reset, // @[functional-unit.scala:591:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14] ); wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [64:0] _ifpu_io_out_bits_data; // @[functional-unit.scala:624:20] wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[functional-unit.scala:600:26] wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[functional-unit.scala:600:26] wire _fp_decoder_io_sigs_fromint; // @[functional-unit.scala:600:26] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:591:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:591:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:591:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:591:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:591:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:591:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:591:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:591:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:591:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:591:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:591:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:591:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:591:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:591:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:591:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:591:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:591:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:591:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:591:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:591:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:591:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:591:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:591:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:591:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:591:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:591:7] wire io_req_ready = 1'h1; // @[functional-unit.scala:591:7] wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[functional-unit.scala:591:7] wire [64:0] req_in3 = 65'h0; // @[functional-unit.scala:605:17] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:591:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:591:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire req_vec = 1'h0; // @[functional-unit.scala:605:17] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:591:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:591:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [1:0] req_fmaCmd = 2'h0; // @[functional-unit.scala:605:17] wire [1:0] req_fmt = 2'h0; // @[functional-unit.scala:605:17] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:591:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:591:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:591:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:591:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:591:7] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:591:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:591:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:591:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:591:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:591:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:591:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:591:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:591:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:591:7] wire [64:0] _io_resp_bits_data_T_1; // @[package.scala:39:76] wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:591:7] wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:591:7] wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:591:7] wire io_resp_valid_0; // @[functional-unit.scala:591:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] reg r_uops_0_taken; // @[functional-unit.scala:237:23] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] reg r_uops_0_exception; // @[functional-unit.scala:237:23] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :591:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :591:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :591:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :591:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :591:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :591:7] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :591:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :591:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :591:7] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :591:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :591:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :591:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :591:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :591:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :591:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :591:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :591:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :591:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_1 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :591:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_1_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [2:0] _fp_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire [2:0] _fp_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58] wire _fp_rm_T_1 = &_fp_rm_T; // @[util.scala:289:58] wire [2:0] fp_rm = _fp_rm_T_1 ? io_fcsr_rm_0 : _fp_rm_T_2; // @[util.scala:289:58] wire [2:0] req_rm = fp_rm; // @[functional-unit.scala:604:18, :605:17] wire [1:0] _req_typ_T; // @[util.scala:295:59] wire [64:0] _req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _req_in2_T_4; // @[FPU.scala:369:10] wire req_ldst; // @[functional-unit.scala:605:17] wire req_wen; // @[functional-unit.scala:605:17] wire req_ren1; // @[functional-unit.scala:605:17] wire req_ren2; // @[functional-unit.scala:605:17] wire req_ren3; // @[functional-unit.scala:605:17] wire req_swap12; // @[functional-unit.scala:605:17] wire req_swap23; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagIn; // @[functional-unit.scala:605:17] wire [1:0] req_typeTagOut; // @[functional-unit.scala:605:17] wire req_fromint; // @[functional-unit.scala:605:17] wire req_toint; // @[functional-unit.scala:605:17] wire req_fastpipe; // @[functional-unit.scala:605:17] wire req_fma; // @[functional-unit.scala:605:17] wire req_div; // @[functional-unit.scala:605:17] wire req_sqrt; // @[functional-unit.scala:605:17] wire req_wflags; // @[functional-unit.scala:605:17] wire [1:0] req_typ; // @[functional-unit.scala:605:17] wire [64:0] req_in1; // @[functional-unit.scala:605:17] wire [64:0] req_in2; // @[functional-unit.scala:605:17] wire _req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in1_prev_unswizzled_hi = {_req_in1_prev_unswizzled_T, _req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in1_prev_unswizzled = {req_in1_prev_unswizzled_hi, _req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in1_prev_prev_sign = req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in1_prev_prev_fractIn = req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in1_prev_prev_expIn = req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in1_prev_prev_fractOut_T = {req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in1_prev_prev_fractOut = _req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in1_prev_prev_expOut_expCode = req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T = {4'h0, req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in1_prev_prev_expOut_commonCase_T_1 = _req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in1_prev_prev_expOut_commonCase = _req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in1_prev_prev_expOut_T_5 = req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in1_prev_prev_expOut_T = req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in1_prev_prev_expOut_T_1 = req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in1_prev_prev_expOut_T_2 = _req_in1_prev_prev_expOut_T | _req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in1_prev_prev_expOut_T_3 = req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in1_prev_prev_expOut_T_4 = {req_in1_prev_prev_expOut_expCode, _req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in1_prev_prev_expOut = _req_in1_prev_prev_expOut_T_2 ? _req_in1_prev_prev_expOut_T_4 : _req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in1_prev_prev_hi = {req_in1_prev_prev_sign, req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in1_floats_0 = {req_in1_prev_prev_hi, req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire req_in1_prev_isbox = &_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in1_oks_0 = req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in1_truncIdx_T; // @[package.scala:38:21] wire req_in1_truncIdx = _req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in1_T = req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in1_T_1 = _req_in1_T | req_in1_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in1_truncIdx_T_1; // @[package.scala:38:21] wire req_in1_truncIdx_1 = _req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in1_T_2 = req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in1_T_3 = _req_in1_T_2 ? io_req_bits_rs1_data_0 : req_in1_floats_0; // @[package.scala:39:{76,86}] assign _req_in1_T_4 = _req_in1_T_1 ? _req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in1 = _req_in1_T_4; // @[FPU.scala:369:10] wire _req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] req_in2_prev_unswizzled_hi = {_req_in2_prev_unswizzled_T, _req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] req_in2_prev_unswizzled = {req_in2_prev_unswizzled_hi, _req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire req_in2_prev_prev_sign = req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] req_in2_prev_prev_fractIn = req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] req_in2_prev_prev_expIn = req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _req_in2_prev_prev_fractOut_T = {req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] req_in2_prev_prev_fractOut = _req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] req_in2_prev_prev_expOut_expCode = req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T = {4'h0, req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _req_in2_prev_prev_expOut_commonCase_T_1 = _req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] req_in2_prev_prev_expOut_commonCase = _req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _req_in2_prev_prev_expOut_T_5 = req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _req_in2_prev_prev_expOut_T = req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _req_in2_prev_prev_expOut_T_1 = req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _req_in2_prev_prev_expOut_T_2 = _req_in2_prev_prev_expOut_T | _req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _req_in2_prev_prev_expOut_T_3 = req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _req_in2_prev_prev_expOut_T_4 = {req_in2_prev_prev_expOut_expCode, _req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] req_in2_prev_prev_expOut = _req_in2_prev_prev_expOut_T_2 ? _req_in2_prev_prev_expOut_T_4 : _req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] req_in2_prev_prev_hi = {req_in2_prev_prev_sign, req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] req_in2_floats_0 = {req_in2_prev_prev_hi, req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire req_in2_prev_isbox = &_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire req_in2_oks_0 = req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [1:0] _req_in2_truncIdx_T; // @[package.scala:38:21] wire req_in2_truncIdx = _req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _req_in2_T = req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _req_in2_T_1 = _req_in2_T | req_in2_oks_0; // @[package.scala:39:{76,86}] wire [1:0] _req_in2_truncIdx_T_1; // @[package.scala:38:21] wire req_in2_truncIdx_1 = _req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _req_in2_T_2 = req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _req_in2_T_3 = _req_in2_T_2 ? io_req_bits_rs2_data_0 : req_in2_floats_0; // @[package.scala:39:{76,86}] assign _req_in2_T_4 = _req_in2_T_1 ? _req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign req_in2 = _req_in2_T_4; // @[FPU.scala:369:10] assign _req_typ_T = io_req_bits_uop_imm_packed_0[9:8]; // @[util.scala:295:59] assign req_typ = _req_typ_T; // @[util.scala:295:59]
Generate the Verilog code corresponding to this FIRRTL code module TLDFromNoC_1 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<21>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_denied_WIRE : UInt<1> connect _protocol_bits_denied_WIRE, const connect protocol.bits.denied, _protocol_bits_denied_WIRE node _T = shr(const, 1) wire _protocol_bits_sink_WIRE : UInt<5> connect _protocol_bits_sink_WIRE, _T connect protocol.bits.sink, _protocol_bits_sink_WIRE node _T_1 = shr(_T, 5) wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, _T_1 connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T_2 = shr(_T_1, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T_2 connect protocol.bits.user, _protocol_bits_user_WIRE node _T_3 = shr(_T_2, 0) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_3 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_4 = shr(_T_3, 6) wire _protocol_bits_size_WIRE : UInt<4> connect _protocol_bits_size_WIRE, _T_4 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_5 = shr(_T_4, 4) wire _protocol_bits_param_WIRE : UInt<2> connect _protocol_bits_param_WIRE, _T_5 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_6 = shr(_T_5, 2) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_6 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_7 = shr(_T_6, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_8 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_8 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_9 = shr(_T_8, 64) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol node _io_protocol_bits_source_T = bits(protocol.bits.source, 1, 0) connect io.protocol.bits.source, _io_protocol_bits_source_T
module TLDFromNoC_1( // @[TilelinkAdapters.scala:185:7] input clock, // @[TilelinkAdapters.scala:185:7] input reset, // @[TilelinkAdapters.scala:185:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [20:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [20:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[20:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7] if (reset) // @[TilelinkAdapters.scala:185:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7] else // @[TilelinkAdapters.scala:185:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[20:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_118 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_118( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper_3 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_41 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn
module ReRoCCManagerControlRemapper_3( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoccCommandRouter : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}[1], busy : UInt<1>} inst cmd_q of Queue2_RoCCCommand connect cmd_q.clock, clock connect cmd_q.reset, reset connect cmd_q.io.enq.valid, io.in.valid connect cmd_q.io.enq.bits.status.uie, io.in.bits.status.uie connect cmd_q.io.enq.bits.status.sie, io.in.bits.status.sie connect cmd_q.io.enq.bits.status.hie, io.in.bits.status.hie connect cmd_q.io.enq.bits.status.mie, io.in.bits.status.mie connect cmd_q.io.enq.bits.status.upie, io.in.bits.status.upie connect cmd_q.io.enq.bits.status.spie, io.in.bits.status.spie connect cmd_q.io.enq.bits.status.ube, io.in.bits.status.ube connect cmd_q.io.enq.bits.status.mpie, io.in.bits.status.mpie connect cmd_q.io.enq.bits.status.spp, io.in.bits.status.spp connect cmd_q.io.enq.bits.status.vs, io.in.bits.status.vs connect cmd_q.io.enq.bits.status.mpp, io.in.bits.status.mpp connect cmd_q.io.enq.bits.status.fs, io.in.bits.status.fs connect cmd_q.io.enq.bits.status.xs, io.in.bits.status.xs connect cmd_q.io.enq.bits.status.mprv, io.in.bits.status.mprv connect cmd_q.io.enq.bits.status.sum, io.in.bits.status.sum connect cmd_q.io.enq.bits.status.mxr, io.in.bits.status.mxr connect cmd_q.io.enq.bits.status.tvm, io.in.bits.status.tvm connect cmd_q.io.enq.bits.status.tw, io.in.bits.status.tw connect cmd_q.io.enq.bits.status.tsr, io.in.bits.status.tsr connect cmd_q.io.enq.bits.status.zero1, io.in.bits.status.zero1 connect cmd_q.io.enq.bits.status.sd_rv32, io.in.bits.status.sd_rv32 connect cmd_q.io.enq.bits.status.uxl, io.in.bits.status.uxl connect cmd_q.io.enq.bits.status.sxl, io.in.bits.status.sxl connect cmd_q.io.enq.bits.status.sbe, io.in.bits.status.sbe connect cmd_q.io.enq.bits.status.mbe, io.in.bits.status.mbe connect cmd_q.io.enq.bits.status.gva, io.in.bits.status.gva connect cmd_q.io.enq.bits.status.mpv, io.in.bits.status.mpv connect cmd_q.io.enq.bits.status.zero2, io.in.bits.status.zero2 connect cmd_q.io.enq.bits.status.sd, io.in.bits.status.sd connect cmd_q.io.enq.bits.status.v, io.in.bits.status.v connect cmd_q.io.enq.bits.status.prv, io.in.bits.status.prv connect cmd_q.io.enq.bits.status.dv, io.in.bits.status.dv connect cmd_q.io.enq.bits.status.dprv, io.in.bits.status.dprv connect cmd_q.io.enq.bits.status.isa, io.in.bits.status.isa connect cmd_q.io.enq.bits.status.wfi, io.in.bits.status.wfi connect cmd_q.io.enq.bits.status.cease, io.in.bits.status.cease connect cmd_q.io.enq.bits.status.debug, io.in.bits.status.debug connect cmd_q.io.enq.bits.rs2, io.in.bits.rs2 connect cmd_q.io.enq.bits.rs1, io.in.bits.rs1 connect cmd_q.io.enq.bits.inst.opcode, io.in.bits.inst.opcode connect cmd_q.io.enq.bits.inst.rd, io.in.bits.inst.rd connect cmd_q.io.enq.bits.inst.xs2, io.in.bits.inst.xs2 connect cmd_q.io.enq.bits.inst.xs1, io.in.bits.inst.xs1 connect cmd_q.io.enq.bits.inst.xd, io.in.bits.inst.xd connect cmd_q.io.enq.bits.inst.rs1, io.in.bits.inst.rs1 connect cmd_q.io.enq.bits.inst.rs2, io.in.bits.inst.rs2 connect cmd_q.io.enq.bits.inst.funct, io.in.bits.inst.funct connect io.in.ready, cmd_q.io.enq.ready node cmdReadys_me = eq(UInt<7>(0h7b), cmd_q.io.deq.bits.inst.opcode) node _cmdReadys_io_out_0_valid_T = and(cmd_q.io.deq.valid, cmdReadys_me) connect io.out[0].valid, _cmdReadys_io_out_0_valid_T connect io.out[0].bits, cmd_q.io.deq.bits node cmdReadys_0 = and(io.out[0].ready, cmdReadys_me) connect cmd_q.io.deq.ready, cmdReadys_0 connect io.busy, cmd_q.io.deq.valid node _T = leq(cmdReadys_0, UInt<1>(0h1)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Custom opcode matched for more than one accelerator\n at LazyRoCC.scala:418 assert(PopCount(cmdReadys) <= 1.U,\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert
module RoccCommandRouter( // @[LazyRoCC.scala:400:7] input clock, // @[LazyRoCC.scala:400:7] input reset, // @[LazyRoCC.scala:400:7] output io_in_ready, // @[LazyRoCC.scala:402:14] input io_in_valid, // @[LazyRoCC.scala:402:14] input [6:0] io_in_bits_inst_funct, // @[LazyRoCC.scala:402:14] input [4:0] io_in_bits_inst_rs2, // @[LazyRoCC.scala:402:14] input [4:0] io_in_bits_inst_rs1, // @[LazyRoCC.scala:402:14] input io_in_bits_inst_xd, // @[LazyRoCC.scala:402:14] input io_in_bits_inst_xs1, // @[LazyRoCC.scala:402:14] input io_in_bits_inst_xs2, // @[LazyRoCC.scala:402:14] input [4:0] io_in_bits_inst_rd, // @[LazyRoCC.scala:402:14] input [6:0] io_in_bits_inst_opcode, // @[LazyRoCC.scala:402:14] input [63:0] io_in_bits_rs1, // @[LazyRoCC.scala:402:14] input [63:0] io_in_bits_rs2, // @[LazyRoCC.scala:402:14] input io_in_bits_status_debug, // @[LazyRoCC.scala:402:14] input io_in_bits_status_cease, // @[LazyRoCC.scala:402:14] input io_in_bits_status_wfi, // @[LazyRoCC.scala:402:14] input [31:0] io_in_bits_status_isa, // @[LazyRoCC.scala:402:14] input [1:0] io_in_bits_status_dprv, // @[LazyRoCC.scala:402:14] input io_in_bits_status_dv, // @[LazyRoCC.scala:402:14] input [1:0] io_in_bits_status_prv, // @[LazyRoCC.scala:402:14] input io_in_bits_status_v, // @[LazyRoCC.scala:402:14] input io_in_bits_status_mpv, // @[LazyRoCC.scala:402:14] input io_in_bits_status_gva, // @[LazyRoCC.scala:402:14] input io_in_bits_status_tsr, // @[LazyRoCC.scala:402:14] input io_in_bits_status_tw, // @[LazyRoCC.scala:402:14] input io_in_bits_status_tvm, // @[LazyRoCC.scala:402:14] input io_in_bits_status_mxr, // @[LazyRoCC.scala:402:14] input io_in_bits_status_sum, // @[LazyRoCC.scala:402:14] input io_in_bits_status_mprv, // @[LazyRoCC.scala:402:14] input [1:0] io_in_bits_status_fs, // @[LazyRoCC.scala:402:14] input [1:0] io_in_bits_status_mpp, // @[LazyRoCC.scala:402:14] input io_in_bits_status_spp, // @[LazyRoCC.scala:402:14] input io_in_bits_status_mpie, // @[LazyRoCC.scala:402:14] input io_in_bits_status_spie, // @[LazyRoCC.scala:402:14] input io_in_bits_status_mie, // @[LazyRoCC.scala:402:14] input io_in_bits_status_sie, // @[LazyRoCC.scala:402:14] input io_out_0_ready, // @[LazyRoCC.scala:402:14] output io_out_0_valid, // @[LazyRoCC.scala:402:14] output [6:0] io_out_0_bits_inst_funct, // @[LazyRoCC.scala:402:14] output [4:0] io_out_0_bits_inst_rs2, // @[LazyRoCC.scala:402:14] output [4:0] io_out_0_bits_inst_rs1, // @[LazyRoCC.scala:402:14] output io_out_0_bits_inst_xd, // @[LazyRoCC.scala:402:14] output io_out_0_bits_inst_xs1, // @[LazyRoCC.scala:402:14] output io_out_0_bits_inst_xs2, // @[LazyRoCC.scala:402:14] output [4:0] io_out_0_bits_inst_rd, // @[LazyRoCC.scala:402:14] output [6:0] io_out_0_bits_inst_opcode, // @[LazyRoCC.scala:402:14] output [63:0] io_out_0_bits_rs1, // @[LazyRoCC.scala:402:14] output [63:0] io_out_0_bits_rs2, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_debug, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_cease, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_wfi, // @[LazyRoCC.scala:402:14] output [31:0] io_out_0_bits_status_isa, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_dprv, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_dv, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_prv, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_v, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_sd, // @[LazyRoCC.scala:402:14] output [22:0] io_out_0_bits_status_zero2, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mpv, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_gva, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mbe, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_sbe, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_sxl, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_uxl, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_sd_rv32, // @[LazyRoCC.scala:402:14] output [7:0] io_out_0_bits_status_zero1, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_tsr, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_tw, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_tvm, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mxr, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_sum, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mprv, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_xs, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_fs, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_mpp, // @[LazyRoCC.scala:402:14] output [1:0] io_out_0_bits_status_vs, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_spp, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mpie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_ube, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_spie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_upie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_mie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_hie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_sie, // @[LazyRoCC.scala:402:14] output io_out_0_bits_status_uie, // @[LazyRoCC.scala:402:14] output io_busy // @[LazyRoCC.scala:402:14] ); wire _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _cmd_q_io_deq_bits_inst_opcode; // @[Decoupled.scala:362:21] wire io_in_valid_0 = io_in_valid; // @[LazyRoCC.scala:400:7] wire [6:0] io_in_bits_inst_funct_0 = io_in_bits_inst_funct; // @[LazyRoCC.scala:400:7] wire [4:0] io_in_bits_inst_rs2_0 = io_in_bits_inst_rs2; // @[LazyRoCC.scala:400:7] wire [4:0] io_in_bits_inst_rs1_0 = io_in_bits_inst_rs1; // @[LazyRoCC.scala:400:7] wire io_in_bits_inst_xd_0 = io_in_bits_inst_xd; // @[LazyRoCC.scala:400:7] wire io_in_bits_inst_xs1_0 = io_in_bits_inst_xs1; // @[LazyRoCC.scala:400:7] wire io_in_bits_inst_xs2_0 = io_in_bits_inst_xs2; // @[LazyRoCC.scala:400:7] wire [4:0] io_in_bits_inst_rd_0 = io_in_bits_inst_rd; // @[LazyRoCC.scala:400:7] wire [6:0] io_in_bits_inst_opcode_0 = io_in_bits_inst_opcode; // @[LazyRoCC.scala:400:7] wire [63:0] io_in_bits_rs1_0 = io_in_bits_rs1; // @[LazyRoCC.scala:400:7] wire [63:0] io_in_bits_rs2_0 = io_in_bits_rs2; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_debug_0 = io_in_bits_status_debug; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_cease_0 = io_in_bits_status_cease; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_wfi_0 = io_in_bits_status_wfi; // @[LazyRoCC.scala:400:7] wire [31:0] io_in_bits_status_isa_0 = io_in_bits_status_isa; // @[LazyRoCC.scala:400:7] wire [1:0] io_in_bits_status_dprv_0 = io_in_bits_status_dprv; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_dv_0 = io_in_bits_status_dv; // @[LazyRoCC.scala:400:7] wire [1:0] io_in_bits_status_prv_0 = io_in_bits_status_prv; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_v_0 = io_in_bits_status_v; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_mpv_0 = io_in_bits_status_mpv; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_gva_0 = io_in_bits_status_gva; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_tsr_0 = io_in_bits_status_tsr; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_tw_0 = io_in_bits_status_tw; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_tvm_0 = io_in_bits_status_tvm; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_mxr_0 = io_in_bits_status_mxr; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_sum_0 = io_in_bits_status_sum; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_mprv_0 = io_in_bits_status_mprv; // @[LazyRoCC.scala:400:7] wire [1:0] io_in_bits_status_fs_0 = io_in_bits_status_fs; // @[LazyRoCC.scala:400:7] wire [1:0] io_in_bits_status_mpp_0 = io_in_bits_status_mpp; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_spp_0 = io_in_bits_status_spp; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_mpie_0 = io_in_bits_status_mpie; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_spie_0 = io_in_bits_status_spie; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_mie_0 = io_in_bits_status_mie; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_sie_0 = io_in_bits_status_sie; // @[LazyRoCC.scala:400:7] wire io_out_0_ready_0 = io_out_0_ready; // @[LazyRoCC.scala:400:7] wire [1:0] io_in_bits_status_sxl = 2'h2; // @[Decoupled.scala:362:21] wire [1:0] io_in_bits_status_uxl = 2'h2; // @[Decoupled.scala:362:21] wire [1:0] io_in_bits_status_vs = 2'h0; // @[Decoupled.scala:362:21] wire [1:0] io_in_bits_status_xs = 2'h3; // @[Decoupled.scala:362:21] wire [7:0] io_in_bits_status_zero1 = 8'h0; // @[Decoupled.scala:362:21] wire io_in_bits_status_mbe = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_sbe = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_sd_rv32 = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_ube = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_upie = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_hie = 1'h0; // @[LazyRoCC.scala:400:7] wire io_in_bits_status_uie = 1'h0; // @[LazyRoCC.scala:400:7] wire [22:0] io_in_bits_status_zero2 = 23'h0; // @[Decoupled.scala:362:21] wire io_in_bits_status_sd = 1'h1; // @[Decoupled.scala:362:21] wire _cmdReadys_io_out_0_valid_T; // @[LazyRoCC.scala:411:28] wire io_in_ready_0; // @[LazyRoCC.scala:400:7] wire [6:0] io_out_0_bits_inst_funct_0; // @[LazyRoCC.scala:400:7] wire [4:0] io_out_0_bits_inst_rs2_0; // @[LazyRoCC.scala:400:7] wire [4:0] io_out_0_bits_inst_rs1_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_inst_xd_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_inst_xs1_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_inst_xs2_0; // @[LazyRoCC.scala:400:7] wire [4:0] io_out_0_bits_inst_rd_0; // @[LazyRoCC.scala:400:7] wire [6:0] io_out_0_bits_inst_opcode_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_debug_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_cease_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_wfi_0; // @[LazyRoCC.scala:400:7] wire [31:0] io_out_0_bits_status_isa_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_dprv_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_dv_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_prv_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_v_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_sd_0; // @[LazyRoCC.scala:400:7] wire [22:0] io_out_0_bits_status_zero2_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mpv_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_gva_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mbe_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_sbe_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_sxl_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_uxl_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_sd_rv32_0; // @[LazyRoCC.scala:400:7] wire [7:0] io_out_0_bits_status_zero1_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_tsr_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_tw_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_tvm_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mxr_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_sum_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mprv_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_xs_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_fs_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_mpp_0; // @[LazyRoCC.scala:400:7] wire [1:0] io_out_0_bits_status_vs_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_spp_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mpie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_ube_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_spie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_upie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_mie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_hie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_sie_0; // @[LazyRoCC.scala:400:7] wire io_out_0_bits_status_uie_0; // @[LazyRoCC.scala:400:7] wire [63:0] io_out_0_bits_rs1_0; // @[LazyRoCC.scala:400:7] wire [63:0] io_out_0_bits_rs2_0; // @[LazyRoCC.scala:400:7] wire io_out_0_valid_0; // @[LazyRoCC.scala:400:7] wire io_busy_0; // @[LazyRoCC.scala:400:7] wire cmdReadys_me = _cmd_q_io_deq_bits_inst_opcode == 7'h7B; // @[Decoupled.scala:362:21] assign _cmdReadys_io_out_0_valid_T = _cmd_q_io_deq_valid & cmdReadys_me; // @[Decoupled.scala:362:21] assign io_out_0_valid_0 = _cmdReadys_io_out_0_valid_T; // @[LazyRoCC.scala:400:7, :411:28] wire cmdReadys_0 = io_out_0_ready_0 & cmdReadys_me; // @[LazyRoCC.scala:389:41, :400:7, :413:15] Queue2_RoCCCommand cmd_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (io_in_ready_0), .io_enq_valid (io_in_valid_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_funct (io_in_bits_inst_funct_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_rs2 (io_in_bits_inst_rs2_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_rs1 (io_in_bits_inst_rs1_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_xd (io_in_bits_inst_xd_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_xs1 (io_in_bits_inst_xs1_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_xs2 (io_in_bits_inst_xs2_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_rd (io_in_bits_inst_rd_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_inst_opcode (io_in_bits_inst_opcode_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_rs1 (io_in_bits_rs1_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_rs2 (io_in_bits_rs2_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_debug (io_in_bits_status_debug_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_cease (io_in_bits_status_cease_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_wfi (io_in_bits_status_wfi_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_isa (io_in_bits_status_isa_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_dprv (io_in_bits_status_dprv_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_dv (io_in_bits_status_dv_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_prv (io_in_bits_status_prv_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_v (io_in_bits_status_v_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mpv (io_in_bits_status_mpv_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_gva (io_in_bits_status_gva_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_tsr (io_in_bits_status_tsr_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_tw (io_in_bits_status_tw_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_tvm (io_in_bits_status_tvm_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mxr (io_in_bits_status_mxr_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_sum (io_in_bits_status_sum_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mprv (io_in_bits_status_mprv_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_fs (io_in_bits_status_fs_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mpp (io_in_bits_status_mpp_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_spp (io_in_bits_status_spp_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mpie (io_in_bits_status_mpie_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_spie (io_in_bits_status_spie_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_mie (io_in_bits_status_mie_0), // @[LazyRoCC.scala:400:7] .io_enq_bits_status_sie (io_in_bits_status_sie_0), // @[LazyRoCC.scala:400:7] .io_deq_ready (cmdReadys_0), // @[LazyRoCC.scala:413:15] .io_deq_valid (_cmd_q_io_deq_valid), .io_deq_bits_inst_funct (io_out_0_bits_inst_funct_0), .io_deq_bits_inst_rs2 (io_out_0_bits_inst_rs2_0), .io_deq_bits_inst_rs1 (io_out_0_bits_inst_rs1_0), .io_deq_bits_inst_xd (io_out_0_bits_inst_xd_0), .io_deq_bits_inst_xs1 (io_out_0_bits_inst_xs1_0), .io_deq_bits_inst_xs2 (io_out_0_bits_inst_xs2_0), .io_deq_bits_inst_rd (io_out_0_bits_inst_rd_0), .io_deq_bits_inst_opcode (_cmd_q_io_deq_bits_inst_opcode), .io_deq_bits_rs1 (io_out_0_bits_rs1_0), .io_deq_bits_rs2 (io_out_0_bits_rs2_0), .io_deq_bits_status_debug (io_out_0_bits_status_debug_0), .io_deq_bits_status_cease (io_out_0_bits_status_cease_0), .io_deq_bits_status_wfi (io_out_0_bits_status_wfi_0), .io_deq_bits_status_isa (io_out_0_bits_status_isa_0), .io_deq_bits_status_dprv (io_out_0_bits_status_dprv_0), .io_deq_bits_status_dv (io_out_0_bits_status_dv_0), .io_deq_bits_status_prv (io_out_0_bits_status_prv_0), .io_deq_bits_status_v (io_out_0_bits_status_v_0), .io_deq_bits_status_sd (io_out_0_bits_status_sd_0), .io_deq_bits_status_zero2 (io_out_0_bits_status_zero2_0), .io_deq_bits_status_mpv (io_out_0_bits_status_mpv_0), .io_deq_bits_status_gva (io_out_0_bits_status_gva_0), .io_deq_bits_status_mbe (io_out_0_bits_status_mbe_0), .io_deq_bits_status_sbe (io_out_0_bits_status_sbe_0), .io_deq_bits_status_sxl (io_out_0_bits_status_sxl_0), .io_deq_bits_status_uxl (io_out_0_bits_status_uxl_0), .io_deq_bits_status_sd_rv32 (io_out_0_bits_status_sd_rv32_0), .io_deq_bits_status_zero1 (io_out_0_bits_status_zero1_0), .io_deq_bits_status_tsr (io_out_0_bits_status_tsr_0), .io_deq_bits_status_tw (io_out_0_bits_status_tw_0), .io_deq_bits_status_tvm (io_out_0_bits_status_tvm_0), .io_deq_bits_status_mxr (io_out_0_bits_status_mxr_0), .io_deq_bits_status_sum (io_out_0_bits_status_sum_0), .io_deq_bits_status_mprv (io_out_0_bits_status_mprv_0), .io_deq_bits_status_xs (io_out_0_bits_status_xs_0), .io_deq_bits_status_fs (io_out_0_bits_status_fs_0), .io_deq_bits_status_mpp (io_out_0_bits_status_mpp_0), .io_deq_bits_status_vs (io_out_0_bits_status_vs_0), .io_deq_bits_status_spp (io_out_0_bits_status_spp_0), .io_deq_bits_status_mpie (io_out_0_bits_status_mpie_0), .io_deq_bits_status_ube (io_out_0_bits_status_ube_0), .io_deq_bits_status_spie (io_out_0_bits_status_spie_0), .io_deq_bits_status_upie (io_out_0_bits_status_upie_0), .io_deq_bits_status_mie (io_out_0_bits_status_mie_0), .io_deq_bits_status_hie (io_out_0_bits_status_hie_0), .io_deq_bits_status_sie (io_out_0_bits_status_sie_0), .io_deq_bits_status_uie (io_out_0_bits_status_uie_0) ); // @[Decoupled.scala:362:21] assign io_out_0_bits_inst_opcode_0 = _cmd_q_io_deq_bits_inst_opcode; // @[Decoupled.scala:362:21] assign io_busy_0 = _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] assign io_in_ready = io_in_ready_0; // @[LazyRoCC.scala:400:7] assign io_out_0_valid = io_out_0_valid_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_funct = io_out_0_bits_inst_funct_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_rs2 = io_out_0_bits_inst_rs2_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_rs1 = io_out_0_bits_inst_rs1_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_xd = io_out_0_bits_inst_xd_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_xs1 = io_out_0_bits_inst_xs1_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_xs2 = io_out_0_bits_inst_xs2_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_rd = io_out_0_bits_inst_rd_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_inst_opcode = io_out_0_bits_inst_opcode_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_rs1 = io_out_0_bits_rs1_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_rs2 = io_out_0_bits_rs2_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_debug = io_out_0_bits_status_debug_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_cease = io_out_0_bits_status_cease_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_wfi = io_out_0_bits_status_wfi_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_isa = io_out_0_bits_status_isa_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_dprv = io_out_0_bits_status_dprv_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_dv = io_out_0_bits_status_dv_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_prv = io_out_0_bits_status_prv_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_v = io_out_0_bits_status_v_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sd = io_out_0_bits_status_sd_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_zero2 = io_out_0_bits_status_zero2_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mpv = io_out_0_bits_status_mpv_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_gva = io_out_0_bits_status_gva_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mbe = io_out_0_bits_status_mbe_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sbe = io_out_0_bits_status_sbe_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sxl = io_out_0_bits_status_sxl_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_uxl = io_out_0_bits_status_uxl_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sd_rv32 = io_out_0_bits_status_sd_rv32_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_zero1 = io_out_0_bits_status_zero1_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_tsr = io_out_0_bits_status_tsr_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_tw = io_out_0_bits_status_tw_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_tvm = io_out_0_bits_status_tvm_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mxr = io_out_0_bits_status_mxr_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sum = io_out_0_bits_status_sum_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mprv = io_out_0_bits_status_mprv_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_xs = io_out_0_bits_status_xs_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_fs = io_out_0_bits_status_fs_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mpp = io_out_0_bits_status_mpp_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_vs = io_out_0_bits_status_vs_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_spp = io_out_0_bits_status_spp_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mpie = io_out_0_bits_status_mpie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_ube = io_out_0_bits_status_ube_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_spie = io_out_0_bits_status_spie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_upie = io_out_0_bits_status_upie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_mie = io_out_0_bits_status_mie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_hie = io_out_0_bits_status_hie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_sie = io_out_0_bits_status_sie_0; // @[LazyRoCC.scala:400:7] assign io_out_0_bits_status_uie = io_out_0_bits_status_uie_0; // @[LazyRoCC.scala:400:7] assign io_busy = io_busy_0; // @[LazyRoCC.scala:400:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_98 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_98( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 7, 0) node _source_ok_T = shr(io.in.a.bits.source, 8) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<8>(0h9f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits = bits(_uncommonBits_T, 7, 0) node _T_4 = shr(io.in.a.bits.source, 8) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<8>(0h9f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 7, 0) node _T_24 = shr(io.in.a.bits.source, 8) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<8>(0h9f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 7, 0) node _T_86 = shr(io.in.a.bits.source, 8) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<8>(0h9f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 7, 0) node _T_152 = shr(io.in.a.bits.source, 8) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<8>(0h9f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 7, 0) node _T_199 = shr(io.in.a.bits.source, 8) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<8>(0h9f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 7, 0) node _T_240 = shr(io.in.a.bits.source, 8) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<8>(0h9f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 7, 0) node _T_283 = shr(io.in.a.bits.source, 8) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<8>(0h9f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 7, 0) node _T_321 = shr(io.in.a.bits.source, 8) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<8>(0h9f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 7, 0) node _T_359 = shr(io.in.a.bits.source, 8) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<8>(0h9f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 7, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 8) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<8>(0h9f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes : UInt<640>, clock, reset, UInt<640>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<160> connect a_set, UInt<160>(0h0) wire a_set_wo_ready : UInt<160> connect a_set_wo_ready, UInt<160>(0h0) wire a_opcodes_set : UInt<640> connect a_opcodes_set, UInt<640>(0h0) wire a_sizes_set : UInt<640> connect a_sizes_set, UInt<640>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<160> connect d_clr, UInt<160>(0h0) wire d_clr_wo_ready : UInt<160> connect d_clr_wo_ready, UInt<160>(0h0) wire d_opcodes_clr : UInt<640> connect d_opcodes_clr, UInt<640>(0h0) wire d_sizes_clr : UInt<640> connect d_sizes_clr, UInt<640>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_117 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes_1 : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes_1 : UInt<640>, clock, reset, UInt<640>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<160> connect c_set, UInt<160>(0h0) wire c_set_wo_ready : UInt<160> connect c_set_wo_ready, UInt<160>(0h0) wire c_opcodes_set : UInt<640> connect c_opcodes_set, UInt<640>(0h0) wire c_sizes_set : UInt<640> connect c_sizes_set, UInt<640>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<160> connect d_clr_1, UInt<160>(0h0) wire d_clr_wo_ready_1 : UInt<160> connect d_clr_wo_ready_1, UInt<160>(0h0) wire d_opcodes_clr_1 : UInt<640> connect d_opcodes_clr_1, UInt<640>(0h0) wire d_sizes_clr_1 : UInt<640> connect d_sizes_clr_1, UInt<640>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_118 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_58( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2049:0] _c_sizes_set_T_1 = 2050'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [639:0] c_opcodes_set = 640'h0; // @[Monitor.scala:740:34] wire [639:0] c_sizes_set = 640'h0; // @[Monitor.scala:741:34] wire [159:0] c_set = 160'h0; // @[Monitor.scala:738:34] wire [159:0] c_set_wo_ready = 160'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [159:0] inflight; // @[Monitor.scala:614:27] reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [639:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [159:0] a_set; // @[Monitor.scala:626:34] wire [159:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [639:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [639:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [159:0] d_clr; // @[Monitor.scala:664:34] wire [159:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [639:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [639:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [159:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [159:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [159:0] inflight_1; // @[Monitor.scala:726:35] wire [159:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [639:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [159:0] d_clr_1; // @[Monitor.scala:774:34] wire [159:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [639:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [639:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [159:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0) node _source_ok_T = shr(io.in.a.bits.source, 13) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits = bits(_uncommonBits_T, 12, 0) node _T_4 = shr(io.in.a.bits.source, 13) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<13>(0h100f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0) node _T_24 = shr(io.in.a.bits.source, 13) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0) node _T_86 = shr(io.in.a.bits.source, 13) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0) node _T_152 = shr(io.in.a.bits.source, 13) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0) node _T_199 = shr(io.in.a.bits.source, 13) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0) node _T_240 = shr(io.in.a.bits.source, 13) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0) node _T_283 = shr(io.in.a.bits.source, 13) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0) node _T_321 = shr(io.in.a.bits.source, 13) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0) node _T_359 = shr(io.in.a.bits.source, 13) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 13) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<13>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<13>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4112> connect a_set, UInt<4112>(0h0) wire a_set_wo_ready : UInt<4112> connect a_set_wo_ready, UInt<4112>(0h0) wire a_opcodes_set : UInt<16448> connect a_opcodes_set, UInt<16448>(0h0) wire a_sizes_set : UInt<16448> connect a_sizes_set, UInt<16448>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4112> connect d_clr, UInt<4112>(0h0) wire d_clr_wo_ready : UInt<4112> connect d_clr_wo_ready, UInt<4112>(0h0) wire d_opcodes_clr : UInt<16448> connect d_opcodes_clr, UInt<16448>(0h0) wire d_sizes_clr : UInt<16448> connect d_sizes_clr, UInt<16448>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_134 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0) regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<13>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<13>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4112> connect c_set, UInt<4112>(0h0) wire c_set_wo_ready : UInt<4112> connect c_set_wo_ready, UInt<4112>(0h0) wire c_opcodes_set : UInt<16448> connect c_opcodes_set, UInt<16448>(0h0) wire c_sizes_set : UInt<16448> connect c_sizes_set, UInt<16448>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<13>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<13>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<13>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<13>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4112> connect d_clr_1, UInt<4112>(0h0) wire d_clr_wo_ready_1 : UInt<4112> connect d_clr_wo_ready_1, UInt<4112>(0h0) wire d_opcodes_clr_1 : UInt<16448> connect d_opcodes_clr_1, UInt<16448>(0h0) wire d_sizes_clr_1 : UInt<16448> connect d_sizes_clr_1, UInt<16448>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<13>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<13>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<13>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<13>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_135 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<13>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52] wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79] wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77] wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35] wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35] wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34] wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34] wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34] wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [12:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [12:0] source_1; // @[Monitor.scala:541:22] reg [4111:0] inflight; // @[Monitor.scala:614:27] reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [4111:0] a_set; // @[Monitor.scala:626:34] wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [8191:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4111:0] d_clr; // @[Monitor.scala:664:34] wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4111:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [16447:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [16447:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4111:0] inflight_1; // @[Monitor.scala:726:35] wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [4111:0] d_clr_1; // @[Monitor.scala:774:34] wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113] wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_31 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_31( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_138 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_152 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_138( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_152 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShuttleCore : input clock : Clock input reset : Reset output io : { flip hartid : UInt<1>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, imem : { redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt<40>, redirect_ras_head : UInt<3>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flush_icache : UInt<1>, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], flip peek : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>, mispredict : UInt<1>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<2>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { head : UInt<3>, addr : UInt<40>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_paddr : UInt<32>, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, s2_kill : UInt<1>, flip resp : { valid : UInt<1>, bits : { has_data : UInt<1>, tag : UInt<7>, data : UInt<64>, size : UInt<2>}}, flip s2_hit : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, clock_enabled : UInt<1>}, ptw_tlb : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, trace : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>}, fcsr_rm : UInt<3>} regreset debug_tsc_reg : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_reg_T = add(debug_tsc_reg, UInt<1>(0h1)) node _debug_tsc_reg_T_1 = tail(_debug_tsc_reg_T, 1) connect debug_tsc_reg, _debug_tsc_reg_T_1 regreset debug_irt_reg : UInt<64>, clock, reset, UInt<64>(0h0) wire _hits_WIRE : UInt<1>[1] connect _hits_WIRE[0], UInt<1>(0h0) wire hits : UInt<1>[1] connect hits, _hits_WIRE inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.customCSRs[0].sdata invalidate csr.io.customCSRs[0].set invalidate csr.io.customCSRs[0].stall invalidate csr.io.customCSRs[0].value invalidate csr.io.customCSRs[0].wdata invalidate csr.io.customCSRs[0].wen invalidate csr.io.customCSRs[0].ren invalidate csr.io.fiom invalidate csr.io.scontext invalidate csr.io.mcontext invalidate csr.io.trace[0].tval invalidate csr.io.trace[0].cause invalidate csr.io.trace[0].interrupt invalidate csr.io.trace[0].exception invalidate csr.io.trace[0].priv invalidate csr.io.trace[0].insn invalidate csr.io.trace[0].iaddr invalidate csr.io.trace[0].valid invalidate csr.io.trace[1].tval invalidate csr.io.trace[1].cause invalidate csr.io.trace[1].interrupt invalidate csr.io.trace[1].exception invalidate csr.io.trace[1].priv invalidate csr.io.trace[1].insn invalidate csr.io.trace[1].iaddr invalidate csr.io.trace[1].valid invalidate csr.io.inst[0] invalidate csr.io.inst[1] invalidate csr.io.inhibit_cycle invalidate csr.io.csrw_counter invalidate csr.io.interrupt_cause invalidate csr.io.interrupt invalidate csr.io.rocc_interrupt invalidate csr.io.set_fs_dirty invalidate csr.io.fcsr_flags.bits invalidate csr.io.fcsr_flags.valid invalidate csr.io.fcsr_rm invalidate csr.io.time invalidate csr.io.gva invalidate csr.io.mhtinst_read_pseudo invalidate csr.io.htval invalidate csr.io.tval invalidate csr.io.pc invalidate csr.io.cause invalidate csr.io.retire invalidate csr.io.exception invalidate csr.io.evec invalidate csr.io.vsatp.ppn invalidate csr.io.vsatp.asid invalidate csr.io.vsatp.mode invalidate csr.io.hgatp.ppn invalidate csr.io.hgatp.asid invalidate csr.io.hgatp.mode invalidate csr.io.ptbr.ppn invalidate csr.io.ptbr.asid invalidate csr.io.ptbr.mode invalidate csr.io.gstatus.uie invalidate csr.io.gstatus.sie invalidate csr.io.gstatus.hie invalidate csr.io.gstatus.mie invalidate csr.io.gstatus.upie invalidate csr.io.gstatus.spie invalidate csr.io.gstatus.ube invalidate csr.io.gstatus.mpie invalidate csr.io.gstatus.spp invalidate csr.io.gstatus.vs invalidate csr.io.gstatus.mpp invalidate csr.io.gstatus.fs invalidate csr.io.gstatus.xs invalidate csr.io.gstatus.mprv invalidate csr.io.gstatus.sum invalidate csr.io.gstatus.mxr invalidate csr.io.gstatus.tvm invalidate csr.io.gstatus.tw invalidate csr.io.gstatus.tsr invalidate csr.io.gstatus.zero1 invalidate csr.io.gstatus.sd_rv32 invalidate csr.io.gstatus.uxl invalidate csr.io.gstatus.sxl invalidate csr.io.gstatus.sbe invalidate csr.io.gstatus.mbe invalidate csr.io.gstatus.gva invalidate csr.io.gstatus.mpv invalidate csr.io.gstatus.zero2 invalidate csr.io.gstatus.sd invalidate csr.io.gstatus.v invalidate csr.io.gstatus.prv invalidate csr.io.gstatus.dv invalidate csr.io.gstatus.dprv invalidate csr.io.gstatus.isa invalidate csr.io.gstatus.wfi invalidate csr.io.gstatus.cease invalidate csr.io.gstatus.debug invalidate csr.io.hstatus.zero1 invalidate csr.io.hstatus.vsbe invalidate csr.io.hstatus.gva invalidate csr.io.hstatus.spv invalidate csr.io.hstatus.spvp invalidate csr.io.hstatus.hu invalidate csr.io.hstatus.zero2 invalidate csr.io.hstatus.vgein invalidate csr.io.hstatus.zero3 invalidate csr.io.hstatus.vtvm invalidate csr.io.hstatus.vtw invalidate csr.io.hstatus.vtsr invalidate csr.io.hstatus.zero5 invalidate csr.io.hstatus.vsxl invalidate csr.io.hstatus.zero6 invalidate csr.io.status.uie invalidate csr.io.status.sie invalidate csr.io.status.hie invalidate csr.io.status.mie invalidate csr.io.status.upie invalidate csr.io.status.spie invalidate csr.io.status.ube invalidate csr.io.status.mpie invalidate csr.io.status.spp invalidate csr.io.status.vs invalidate csr.io.status.mpp invalidate csr.io.status.fs invalidate csr.io.status.xs invalidate csr.io.status.mprv invalidate csr.io.status.sum invalidate csr.io.status.mxr invalidate csr.io.status.tvm invalidate csr.io.status.tw invalidate csr.io.status.tsr invalidate csr.io.status.zero1 invalidate csr.io.status.sd_rv32 invalidate csr.io.status.uxl invalidate csr.io.status.sxl invalidate csr.io.status.sbe invalidate csr.io.status.mbe invalidate csr.io.status.gva invalidate csr.io.status.mpv invalidate csr.io.status.zero2 invalidate csr.io.status.sd invalidate csr.io.status.v invalidate csr.io.status.prv invalidate csr.io.status.dv invalidate csr.io.status.dprv invalidate csr.io.status.isa invalidate csr.io.status.wfi invalidate csr.io.status.cease invalidate csr.io.status.debug invalidate csr.io.singleStep invalidate csr.io.eret invalidate csr.io.rw_stall invalidate csr.io.csr_stall invalidate csr.io.decode[0].virtual_system_illegal invalidate csr.io.decode[0].virtual_access_illegal invalidate csr.io.decode[0].system_illegal invalidate csr.io.decode[0].write_flush invalidate csr.io.decode[0].write_illegal invalidate csr.io.decode[0].read_illegal invalidate csr.io.decode[0].rocc_illegal invalidate csr.io.decode[0].vector_csr invalidate csr.io.decode[0].fp_csr invalidate csr.io.decode[0].vector_illegal invalidate csr.io.decode[0].fp_illegal invalidate csr.io.decode[0].inst invalidate csr.io.decode[1].virtual_system_illegal invalidate csr.io.decode[1].virtual_access_illegal invalidate csr.io.decode[1].system_illegal invalidate csr.io.decode[1].write_flush invalidate csr.io.decode[1].write_illegal invalidate csr.io.decode[1].read_illegal invalidate csr.io.decode[1].rocc_illegal invalidate csr.io.decode[1].vector_csr invalidate csr.io.decode[1].fp_csr invalidate csr.io.decode[1].vector_illegal invalidate csr.io.decode[1].fp_illegal invalidate csr.io.decode[1].inst invalidate csr.io.decode[2].virtual_system_illegal invalidate csr.io.decode[2].virtual_access_illegal invalidate csr.io.decode[2].system_illegal invalidate csr.io.decode[2].write_flush invalidate csr.io.decode[2].write_illegal invalidate csr.io.decode[2].read_illegal invalidate csr.io.decode[2].rocc_illegal invalidate csr.io.decode[2].vector_csr invalidate csr.io.decode[2].fp_csr invalidate csr.io.decode[2].vector_illegal invalidate csr.io.decode[2].fp_illegal invalidate csr.io.decode[2].inst invalidate csr.io.decode[3].virtual_system_illegal invalidate csr.io.decode[3].virtual_access_illegal invalidate csr.io.decode[3].system_illegal invalidate csr.io.decode[3].write_flush invalidate csr.io.decode[3].write_illegal invalidate csr.io.decode[3].read_illegal invalidate csr.io.decode[3].rocc_illegal invalidate csr.io.decode[3].vector_csr invalidate csr.io.decode[3].fp_csr invalidate csr.io.decode[3].vector_illegal invalidate csr.io.decode[3].fp_illegal invalidate csr.io.decode[3].inst invalidate csr.io.rw.wdata invalidate csr.io.rw.rdata invalidate csr.io.rw.cmd invalidate csr.io.rw.addr invalidate csr.io.hartid invalidate csr.io.interrupts.seip invalidate csr.io.interrupts.meip invalidate csr.io.interrupts.msip invalidate csr.io.interrupts.mtip invalidate csr.io.interrupts.debug invalidate csr.io.ungated_clock connect csr.io.customCSRs[0].set, UInt<1>(0h0) invalidate csr.io.customCSRs[0].sdata connect csr.io.ungated_clock, clock wire rrd_uops : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2] reg ex_uops_reg : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], clock reg mem_uops_reg : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], clock reg com_uops_reg : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], clock wire com_uops : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2] connect com_uops, com_uops_reg reg wb_uops_reg : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2], clock wire wb_uops : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}}[2] connect wb_uops, wb_uops_reg wire ex_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire ex_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire mem_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire mem_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire com_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire com_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire wb_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire wb_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire ll_bypass_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire fp_mem_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire fp_mem_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire fp_com_bypasses_0 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} wire fp_com_bypasses_1 : { valid : UInt<1>, dst : UInt<5>, data : UInt<64>, can_bypass : UInt<1>} node _T = and(fp_com_bypasses_0.valid, fp_com_bypasses_0.can_bypass) node _T_1 = and(fp_com_bypasses_1.valid, fp_com_bypasses_1.can_bypass) node _T_2 = and(fp_mem_bypasses_0.valid, fp_mem_bypasses_0.can_bypass) node _T_3 = and(fp_mem_bypasses_1.valid, fp_mem_bypasses_1.can_bypass) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:104 assert(!fp_bypasses.map(b => b.valid && b.can_bypass).reduce(_||_))\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert wire rrd_stall : UInt<1>[2] wire ex_stall : UInt<1> connect ex_stall, UInt<1>(0h0) connect rrd_stall[0], UInt<1>(0h0) connect rrd_stall[1], UInt<1>(0h0) wire flush_rrd_ex : UInt<1> connect flush_rrd_ex, UInt<1>(0h0) wire kill_mem : UInt<1> connect kill_mem, UInt<1>(0h0) wire _kill_com_WIRE : UInt<1>[2] connect _kill_com_WIRE[0], UInt<1>(0h0) connect _kill_com_WIRE[1], UInt<1>(0h0) wire kill_com : UInt<1>[2] connect kill_com, _kill_com_WIRE node ex_bsy = or(ex_uops_reg[0].valid, ex_uops_reg[1].valid) node mem_bsy = or(mem_uops_reg[0].valid, mem_uops_reg[1].valid) node com_bsy = or(com_uops_reg[0].valid, com_uops_reg[1].valid) wire com_retire : UInt<1>[2] node _T_11 = eq(ex_stall, UInt<1>(0h0)) when _T_11 : connect ex_uops_reg[0].bits, rrd_uops[0].bits node _ex_uops_reg_0_valid_T = eq(rrd_stall[0], UInt<1>(0h0)) node _ex_uops_reg_0_valid_T_1 = and(rrd_uops[0].valid, _ex_uops_reg_0_valid_T) connect ex_uops_reg[0].valid, _ex_uops_reg_0_valid_T_1 when flush_rrd_ex : connect ex_uops_reg[0].valid, UInt<1>(0h0) node _T_12 = or(ex_uops_reg[0].valid, ex_uops_reg[1].valid) when _T_12 : connect mem_uops_reg[0].bits, ex_uops_reg[0].bits node _mem_uops_reg_0_valid_T = eq(flush_rrd_ex, UInt<1>(0h0)) node _mem_uops_reg_0_valid_T_1 = and(ex_uops_reg[0].valid, _mem_uops_reg_0_valid_T) node _mem_uops_reg_0_valid_T_2 = eq(ex_stall, UInt<1>(0h0)) node _mem_uops_reg_0_valid_T_3 = and(_mem_uops_reg_0_valid_T_1, _mem_uops_reg_0_valid_T_2) connect mem_uops_reg[0].valid, _mem_uops_reg_0_valid_T_3 node _T_13 = or(mem_uops_reg[0].valid, mem_uops_reg[1].valid) when _T_13 : connect com_uops_reg[0].bits, mem_uops_reg[0].bits node _com_uops_reg_0_valid_T = eq(kill_mem, UInt<1>(0h0)) node _com_uops_reg_0_valid_T_1 = and(mem_uops_reg[0].valid, _com_uops_reg_0_valid_T) connect com_uops_reg[0].valid, _com_uops_reg_0_valid_T_1 node _T_14 = or(com_uops_reg[0].valid, com_uops_reg[1].valid) when _T_14 : connect wb_uops_reg[0].bits, com_uops[0].bits connect wb_uops_reg[0].valid, com_retire[0] node _T_15 = eq(ex_stall, UInt<1>(0h0)) when _T_15 : connect ex_uops_reg[1].bits, rrd_uops[1].bits node _ex_uops_reg_1_valid_T = eq(rrd_stall[1], UInt<1>(0h0)) node _ex_uops_reg_1_valid_T_1 = and(rrd_uops[1].valid, _ex_uops_reg_1_valid_T) connect ex_uops_reg[1].valid, _ex_uops_reg_1_valid_T_1 when flush_rrd_ex : connect ex_uops_reg[1].valid, UInt<1>(0h0) node _T_16 = or(ex_uops_reg[0].valid, ex_uops_reg[1].valid) when _T_16 : connect mem_uops_reg[1].bits, ex_uops_reg[1].bits node _mem_uops_reg_1_valid_T = eq(flush_rrd_ex, UInt<1>(0h0)) node _mem_uops_reg_1_valid_T_1 = and(ex_uops_reg[1].valid, _mem_uops_reg_1_valid_T) node _mem_uops_reg_1_valid_T_2 = eq(ex_stall, UInt<1>(0h0)) node _mem_uops_reg_1_valid_T_3 = and(_mem_uops_reg_1_valid_T_1, _mem_uops_reg_1_valid_T_2) connect mem_uops_reg[1].valid, _mem_uops_reg_1_valid_T_3 node _T_17 = or(mem_uops_reg[0].valid, mem_uops_reg[1].valid) when _T_17 : connect com_uops_reg[1].bits, mem_uops_reg[1].bits node _com_uops_reg_1_valid_T = eq(kill_mem, UInt<1>(0h0)) node _com_uops_reg_1_valid_T_1 = and(mem_uops_reg[1].valid, _com_uops_reg_1_valid_T) connect com_uops_reg[1].valid, _com_uops_reg_1_valid_T_1 node _T_18 = or(com_uops_reg[0].valid, com_uops_reg[1].valid) when _T_18 : connect wb_uops_reg[1].bits, com_uops[1].bits connect wb_uops_reg[1].valid, com_retire[1] connect io.imem.redirect_val, UInt<1>(0h0) connect io.imem.redirect_flush, UInt<1>(0h0) connect io.imem.flush_icache, UInt<1>(0h0) connect rrd_uops[0].bits, io.imem.resp[0].bits connect rrd_uops[0].valid, io.imem.resp[0].valid connect rrd_uops[1].bits, io.imem.resp[1].bits connect rrd_uops[1].valid, io.imem.resp[1].valid wire decoder_decoded_plaInput : UInt<32> node decoder_decoded_invInputs = not(decoder_decoded_plaInput) wire decoder_decoded : UInt<42> node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5) node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6) node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3) node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1) node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo) node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo) node decoder_decoded_andMatrixOutputs_98_2 = andr(_decoder_decoded_andMatrixOutputs_T) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7) node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo) node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_1) node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1) node decoder_decoded_andMatrixOutputs_101_2 = andr(_decoder_decoded_andMatrixOutputs_T_1) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_2) node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2) node decoder_decoded_andMatrixOutputs_9_2 = andr(_decoder_decoded_andMatrixOutputs_T_2) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_3) node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3) node decoder_decoded_andMatrixOutputs_29_2 = andr(_decoder_decoded_andMatrixOutputs_T_3) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_4) node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4) node decoder_decoded_andMatrixOutputs_139_2 = andr(_decoder_decoded_andMatrixOutputs_T_4) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8) node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_5) node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5) node decoder_decoded_andMatrixOutputs_117_2 = andr(_decoder_decoded_andMatrixOutputs_T_5) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_6) node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6) node decoder_decoded_andMatrixOutputs_95_2 = andr(_decoder_decoded_andMatrixOutputs_T_6) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoder_decoded_andMatrixOutputs_lo_7 = cat(decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoder_decoded_andMatrixOutputs_hi_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _decoder_decoded_andMatrixOutputs_T_7 = cat(decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7) node decoder_decoded_andMatrixOutputs_35_2 = andr(_decoder_decoded_andMatrixOutputs_T_7) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoder_decoded_andMatrixOutputs_lo_8 = cat(decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) node decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoder_decoded_andMatrixOutputs_hi_8 = cat(decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7) node _decoder_decoded_andMatrixOutputs_T_8 = cat(decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8) node decoder_decoded_andMatrixOutputs_182_2 = andr(_decoder_decoded_andMatrixOutputs_T_8) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoder_decoded_andMatrixOutputs_lo_9 = cat(decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9) node decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoder_decoded_andMatrixOutputs_hi_9 = cat(decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8) node _decoder_decoded_andMatrixOutputs_T_9 = cat(decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9) node decoder_decoded_andMatrixOutputs_128_2 = andr(_decoder_decoded_andMatrixOutputs_T_9) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoder_decoded_andMatrixOutputs_lo_10 = cat(decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) node decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoder_decoded_andMatrixOutputs_hi_10 = cat(decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9) node _decoder_decoded_andMatrixOutputs_T_10 = cat(decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10) node decoder_decoded_andMatrixOutputs_66_2 = andr(_decoder_decoded_andMatrixOutputs_T_10) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13) node decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10, decoder_decoded_andMatrixOutputs_andMatrixInput_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, decoder_decoded_andMatrixOutputs_andMatrixInput_9) node decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_lo_hi_lo) node decoder_decoded_andMatrixOutputs_lo_11 = cat(decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) node decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_hi_lo_lo) node decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, decoder_decoded_andMatrixOutputs_andMatrixInput_3_11) node decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_hi_lo) node decoder_decoded_andMatrixOutputs_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10) node _decoder_decoded_andMatrixOutputs_T_11 = cat(decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11) node decoder_decoded_andMatrixOutputs_77_2 = andr(_decoder_decoded_andMatrixOutputs_T_11) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) node decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, decoder_decoded_andMatrixOutputs_andMatrixInput_9_1) node decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_lo_1) node decoder_decoded_andMatrixOutputs_lo_12 = cat(decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_8) node decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) node decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_hi_lo_1) node decoder_decoded_andMatrixOutputs_hi_12 = cat(decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11) node _decoder_decoded_andMatrixOutputs_T_12 = cat(decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12) node decoder_decoded_andMatrixOutputs_190_2 = andr(_decoder_decoded_andMatrixOutputs_T_12) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) node decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_9_2) node decoder_decoded_andMatrixOutputs_lo_13 = cat(decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_9) node decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, decoder_decoded_andMatrixOutputs_andMatrixInput_3_13) node decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_hi_lo_2) node decoder_decoded_andMatrixOutputs_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12) node _decoder_decoded_andMatrixOutputs_T_13 = cat(decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13) node decoder_decoded_andMatrixOutputs_7_2 = andr(_decoder_decoded_andMatrixOutputs_T_13) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) node decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) node decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, decoder_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_lo_hi_lo_2) node decoder_decoded_andMatrixOutputs_lo_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_10) node decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) node decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_hi_lo_3) node decoder_decoded_andMatrixOutputs_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13) node _decoder_decoded_andMatrixOutputs_T_14 = cat(decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14) node decoder_decoded_andMatrixOutputs_97_2 = andr(_decoder_decoded_andMatrixOutputs_T_14) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) node decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, decoder_decoded_andMatrixOutputs_andMatrixInput_9_4) node decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_lo_3) node decoder_decoded_andMatrixOutputs_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_11) node decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, decoder_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) node decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_lo_4) node decoder_decoded_andMatrixOutputs_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14) node _decoder_decoded_andMatrixOutputs_T_15 = cat(decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15) node decoder_decoded_andMatrixOutputs_32_2 = andr(_decoder_decoded_andMatrixOutputs_T_15) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, decoder_decoded_andMatrixOutputs_andMatrixInput_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) node decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_lo) node decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, decoder_decoded_andMatrixOutputs_andMatrixInput_9_5) node decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_hi_lo_4) node decoder_decoded_andMatrixOutputs_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_12) node decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, decoder_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, decoder_decoded_andMatrixOutputs_andMatrixInput_3_16) node decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_hi_lo_5) node decoder_decoded_andMatrixOutputs_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15) node _decoder_decoded_andMatrixOutputs_T_16 = cat(decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16) node decoder_decoded_andMatrixOutputs_70_2 = andr(_decoder_decoded_andMatrixOutputs_T_16) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoder_decoded_andMatrixOutputs_hi_17 = cat(decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) node _decoder_decoded_andMatrixOutputs_T_17 = cat(decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17) node decoder_decoded_andMatrixOutputs_181_2 = andr(_decoder_decoded_andMatrixOutputs_T_17) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoder_decoded_andMatrixOutputs_lo_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoder_decoded_andMatrixOutputs_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _decoder_decoded_andMatrixOutputs_T_18 = cat(decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18) node decoder_decoded_andMatrixOutputs_145_2 = andr(_decoder_decoded_andMatrixOutputs_T_18) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoder_decoded_andMatrixOutputs_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoder_decoded_andMatrixOutputs_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _decoder_decoded_andMatrixOutputs_T_19 = cat(decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19) node decoder_decoded_andMatrixOutputs_143_2 = andr(_decoder_decoded_andMatrixOutputs_T_19) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoder_decoded_andMatrixOutputs_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_13) node decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoder_decoded_andMatrixOutputs_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_16) node _decoder_decoded_andMatrixOutputs_T_20 = cat(decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20) node decoder_decoded_andMatrixOutputs_20_2 = andr(_decoder_decoded_andMatrixOutputs_T_20) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoder_decoded_andMatrixOutputs_lo_21 = cat(decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_14) node decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoder_decoded_andMatrixOutputs_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_17) node _decoder_decoded_andMatrixOutputs_T_21 = cat(decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21) node decoder_decoded_andMatrixOutputs_22_2 = andr(_decoder_decoded_andMatrixOutputs_T_21) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoder_decoded_andMatrixOutputs_lo_22 = cat(decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_15) node decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22) node decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoder_decoded_andMatrixOutputs_hi_22 = cat(decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_18) node _decoder_decoded_andMatrixOutputs_T_22 = cat(decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22) node decoder_decoded_andMatrixOutputs_96_2 = andr(_decoder_decoded_andMatrixOutputs_T_22) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19) node decoder_decoded_andMatrixOutputs_lo_23 = cat(decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_16) node decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoder_decoded_andMatrixOutputs_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_19) node _decoder_decoded_andMatrixOutputs_T_23 = cat(decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23) node decoder_decoded_andMatrixOutputs_39_2 = andr(_decoder_decoded_andMatrixOutputs_T_23) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoder_decoded_andMatrixOutputs_lo_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_17) node decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoder_decoded_andMatrixOutputs_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_20) node _decoder_decoded_andMatrixOutputs_T_24 = cat(decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24) node decoder_decoded_andMatrixOutputs_131_2 = andr(_decoder_decoded_andMatrixOutputs_T_24) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8) node decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21) node decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoder_decoded_andMatrixOutputs_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_18) node decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoder_decoded_andMatrixOutputs_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_21) node _decoder_decoded_andMatrixOutputs_T_25 = cat(decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25) node decoder_decoded_andMatrixOutputs_191_2 = andr(_decoder_decoded_andMatrixOutputs_T_25) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoder_decoded_andMatrixOutputs_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22) node decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26) node decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoder_decoded_andMatrixOutputs_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_22) node _decoder_decoded_andMatrixOutputs_T_26 = cat(decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26) node decoder_decoded_andMatrixOutputs_165_2 = andr(_decoder_decoded_andMatrixOutputs_T_26) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25, decoder_decoded_andMatrixOutputs_andMatrixInput_26) node decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_27) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23, decoder_decoded_andMatrixOutputs_andMatrixInput_24) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21, decoder_decoded_andMatrixOutputs_andMatrixInput_22) node decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo) node decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_lo_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18, decoder_decoded_andMatrixOutputs_andMatrixInput_19) node decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_20) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16, decoder_decoded_andMatrixOutputs_andMatrixInput_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo) node decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_lo_hi_lo_5) node decoder_decoded_andMatrixOutputs_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_19) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12_6) node decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo) node decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo) node decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_hi_lo_6) node decoder_decoded_andMatrixOutputs_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_23) node _decoder_decoded_andMatrixOutputs_T_27 = cat(decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27) node decoder_decoded_andMatrixOutputs_54_2 = andr(_decoder_decoded_andMatrixOutputs_T_27) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28, decoder_decoded_andMatrixOutputs_andMatrixInput_29) node decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, decoder_decoded_andMatrixOutputs_andMatrixInput_27_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, decoder_decoded_andMatrixOutputs_andMatrixInput_25_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1) node decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_lo_2) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, decoder_decoded_andMatrixOutputs_andMatrixInput_23_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, decoder_decoded_andMatrixOutputs_andMatrixInput_19_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1) node decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_lo_hi_lo_6) node decoder_decoded_andMatrixOutputs_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_20) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, decoder_decoded_andMatrixOutputs_andMatrixInput_15_2) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) node decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10) node decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1) node decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_20) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1) node decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo_7) node decoder_decoded_andMatrixOutputs_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_24) node _decoder_decoded_andMatrixOutputs_T_28 = cat(decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28) node decoder_decoded_andMatrixOutputs_89_2 = andr(_decoder_decoded_andMatrixOutputs_T_28) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoder_decoded_andMatrixOutputs_lo_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_6_25) node decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoder_decoded_andMatrixOutputs_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_25) node _decoder_decoded_andMatrixOutputs_T_29 = cat(decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29) node decoder_decoded_andMatrixOutputs_30_2 = andr(_decoder_decoded_andMatrixOutputs_T_29) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, decoder_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoder_decoded_andMatrixOutputs_lo_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_21) node decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) node decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoder_decoded_andMatrixOutputs_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_26) node _decoder_decoded_andMatrixOutputs_T_30 = cat(decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30) node decoder_decoded_andMatrixOutputs_26_2 = andr(_decoder_decoded_andMatrixOutputs_T_30) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoder_decoded_andMatrixOutputs_lo_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_22) node decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31) node decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoder_decoded_andMatrixOutputs_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_27) node _decoder_decoded_andMatrixOutputs_T_31 = cat(decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31) node decoder_decoded_andMatrixOutputs_176_2 = andr(_decoder_decoded_andMatrixOutputs_T_31) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, decoder_decoded_andMatrixOutputs_andMatrixInput_6_28) node decoder_decoded_andMatrixOutputs_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_23) node decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoder_decoded_andMatrixOutputs_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_28) node _decoder_decoded_andMatrixOutputs_T_32 = cat(decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32) node decoder_decoded_andMatrixOutputs_76_2 = andr(_decoder_decoded_andMatrixOutputs_T_32) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, decoder_decoded_andMatrixOutputs_andMatrixInput_6_29) node decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoder_decoded_andMatrixOutputs_lo_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_24) node decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoder_decoded_andMatrixOutputs_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_29) node _decoder_decoded_andMatrixOutputs_T_33 = cat(decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33) node decoder_decoded_andMatrixOutputs_21_2 = andr(_decoder_decoded_andMatrixOutputs_T_33) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8) node decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo_7) node decoder_decoded_andMatrixOutputs_lo_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_25) node decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_30) node decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_8) node decoder_decoded_andMatrixOutputs_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_30) node _decoder_decoded_andMatrixOutputs_T_34 = cat(decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34) node decoder_decoded_andMatrixOutputs_121_2 = andr(_decoder_decoded_andMatrixOutputs_T_34) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) node decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, decoder_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, decoder_decoded_andMatrixOutputs_andMatrixInput_9_13) node decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_8) node decoder_decoded_andMatrixOutputs_lo_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_26) node decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_9) node decoder_decoded_andMatrixOutputs_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_31) node _decoder_decoded_andMatrixOutputs_T_35 = cat(decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35) node decoder_decoded_andMatrixOutputs_60_2 = andr(_decoder_decoded_andMatrixOutputs_T_35) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9) node decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8) node decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, decoder_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, decoder_decoded_andMatrixOutputs_andMatrixInput_9_14) node decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_9) node decoder_decoded_andMatrixOutputs_lo_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_27) node decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_lo_8) node decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_10) node decoder_decoded_andMatrixOutputs_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_32) node _decoder_decoded_andMatrixOutputs_T_36 = cat(decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36) node decoder_decoded_andMatrixOutputs_103_2 = andr(_decoder_decoded_andMatrixOutputs_T_36) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, decoder_decoded_andMatrixOutputs_andMatrixInput_15_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) node decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_lo_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, decoder_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_15) node decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_10) node decoder_decoded_andMatrixOutputs_lo_37 = cat(decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_28) node decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_lo_9) node decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) node decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_11) node decoder_decoded_andMatrixOutputs_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_33) node _decoder_decoded_andMatrixOutputs_T_37 = cat(decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37) node decoder_decoded_andMatrixOutputs_24_2 = andr(_decoder_decoded_andMatrixOutputs_T_37) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoder_decoded_andMatrixOutputs_lo_38 = cat(decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_29) node decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoder_decoded_andMatrixOutputs_hi_38 = cat(decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_34) node _decoder_decoded_andMatrixOutputs_T_38 = cat(decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38) node decoder_decoded_andMatrixOutputs_166_2 = andr(_decoder_decoded_andMatrixOutputs_T_38) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, decoder_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_35) node decoder_decoded_andMatrixOutputs_lo_39 = cat(decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_30) node decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoder_decoded_andMatrixOutputs_hi_39 = cat(decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_35) node _decoder_decoded_andMatrixOutputs_T_39 = cat(decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39) node decoder_decoded_andMatrixOutputs_160_2 = andr(_decoder_decoded_andMatrixOutputs_T_39) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoder_decoded_andMatrixOutputs_lo_40 = cat(decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_31) node decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoder_decoded_andMatrixOutputs_hi_40 = cat(decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_36) node _decoder_decoded_andMatrixOutputs_T_40 = cat(decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40) node decoder_decoded_andMatrixOutputs_94_2 = andr(_decoder_decoded_andMatrixOutputs_T_40) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37) node decoder_decoded_andMatrixOutputs_lo_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_32) node decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoder_decoded_andMatrixOutputs_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_37) node _decoder_decoded_andMatrixOutputs_T_41 = cat(decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41) node decoder_decoded_andMatrixOutputs_55_2 = andr(_decoder_decoded_andMatrixOutputs_T_41) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38) node decoder_decoded_andMatrixOutputs_lo_42 = cat(decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_33) node decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoder_decoded_andMatrixOutputs_hi_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_38) node _decoder_decoded_andMatrixOutputs_T_42 = cat(decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42) node decoder_decoded_andMatrixOutputs_16_2 = andr(_decoder_decoded_andMatrixOutputs_T_42) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, decoder_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, decoder_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoder_decoded_andMatrixOutputs_lo_43 = cat(decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_34) node decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoder_decoded_andMatrixOutputs_hi_43 = cat(decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_39) node _decoder_decoded_andMatrixOutputs_T_43 = cat(decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43) node decoder_decoded_andMatrixOutputs_185_2 = andr(_decoder_decoded_andMatrixOutputs_T_43) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, decoder_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoder_decoded_andMatrixOutputs_lo_44 = cat(decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40) node decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, decoder_decoded_andMatrixOutputs_andMatrixInput_3_44) node decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoder_decoded_andMatrixOutputs_hi_44 = cat(decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_40) node _decoder_decoded_andMatrixOutputs_T_44 = cat(decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44) node decoder_decoded_andMatrixOutputs_140_2 = andr(_decoder_decoded_andMatrixOutputs_T_44) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, decoder_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, decoder_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoder_decoded_andMatrixOutputs_lo_45 = cat(decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_35) node decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoder_decoded_andMatrixOutputs_hi_45 = cat(decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_41) node _decoder_decoded_andMatrixOutputs_T_45 = cat(decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45) node decoder_decoded_andMatrixOutputs_52_2 = andr(_decoder_decoded_andMatrixOutputs_T_45) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, decoder_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoder_decoded_andMatrixOutputs_lo_46 = cat(decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_36) node decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoder_decoded_andMatrixOutputs_hi_46 = cat(decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_42) node _decoder_decoded_andMatrixOutputs_T_46 = cat(decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46) node decoder_decoded_andMatrixOutputs_193_2 = andr(_decoder_decoded_andMatrixOutputs_T_46) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43) node decoder_decoded_andMatrixOutputs_lo_47 = cat(decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_37) node decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoder_decoded_andMatrixOutputs_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_43) node _decoder_decoded_andMatrixOutputs_T_47 = cat(decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47) node decoder_decoded_andMatrixOutputs_91_2 = andr(_decoder_decoded_andMatrixOutputs_T_47) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, decoder_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, decoder_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoder_decoded_andMatrixOutputs_lo_48 = cat(decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_38) node decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, decoder_decoded_andMatrixOutputs_andMatrixInput_3_48) node decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoder_decoded_andMatrixOutputs_hi_48 = cat(decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_44) node _decoder_decoded_andMatrixOutputs_T_48 = cat(decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48) node decoder_decoded_andMatrixOutputs_17_2 = andr(_decoder_decoded_andMatrixOutputs_T_48) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, decoder_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45) node decoder_decoded_andMatrixOutputs_lo_49 = cat(decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_39) node decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoder_decoded_andMatrixOutputs_hi_49 = cat(decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_45) node _decoder_decoded_andMatrixOutputs_T_49 = cat(decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49) node decoder_decoded_andMatrixOutputs_129_2 = andr(_decoder_decoded_andMatrixOutputs_T_49) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, decoder_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, decoder_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoder_decoded_andMatrixOutputs_lo_50 = cat(decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_40) node decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, decoder_decoded_andMatrixOutputs_andMatrixInput_3_50) node decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoder_decoded_andMatrixOutputs_hi_50 = cat(decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_46) node _decoder_decoded_andMatrixOutputs_T_50 = cat(decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50) node decoder_decoded_andMatrixOutputs_177_2 = andr(_decoder_decoded_andMatrixOutputs_T_50) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47) node decoder_decoded_andMatrixOutputs_lo_51 = cat(decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_41) node decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoder_decoded_andMatrixOutputs_hi_51 = cat(decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_47) node _decoder_decoded_andMatrixOutputs_T_51 = cat(decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51) node decoder_decoded_andMatrixOutputs_123_2 = andr(_decoder_decoded_andMatrixOutputs_T_51) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, decoder_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoder_decoded_andMatrixOutputs_lo_52 = cat(decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_42) node decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoder_decoded_andMatrixOutputs_hi_52 = cat(decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_48) node _decoder_decoded_andMatrixOutputs_T_52 = cat(decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52) node decoder_decoded_andMatrixOutputs_14_2 = andr(_decoder_decoded_andMatrixOutputs_T_52) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11) node decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10) node decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) node decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_11) node decoder_decoded_andMatrixOutputs_lo_53 = cat(decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_43) node decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, decoder_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_10) node decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) node decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_12) node decoder_decoded_andMatrixOutputs_hi_53 = cat(decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_49) node _decoder_decoded_andMatrixOutputs_T_53 = cat(decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53) node decoder_decoded_andMatrixOutputs_132_2 = andr(_decoder_decoded_andMatrixOutputs_T_53) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) node decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_lo_4) node decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_18) node decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_12) node decoder_decoded_andMatrixOutputs_lo_54 = cat(decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_44) node decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, decoder_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_lo_11) node decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54) node decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_13) node decoder_decoded_andMatrixOutputs_hi_54 = cat(decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_50) node _decoder_decoded_andMatrixOutputs_T_54 = cat(decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54) node decoder_decoded_andMatrixOutputs_48_2 = andr(_decoder_decoded_andMatrixOutputs_T_54) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoder_decoded_andMatrixOutputs_lo_55 = cat(decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_45) node decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) node decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoder_decoded_andMatrixOutputs_hi_55 = cat(decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_51) node _decoder_decoded_andMatrixOutputs_T_55 = cat(decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55) node decoder_decoded_andMatrixOutputs_155_2 = andr(_decoder_decoded_andMatrixOutputs_T_55) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, decoder_decoded_andMatrixOutputs_andMatrixInput_6_52) node decoder_decoded_andMatrixOutputs_lo_56 = cat(decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_46) node decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, decoder_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoder_decoded_andMatrixOutputs_hi_56 = cat(decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_52) node _decoder_decoded_andMatrixOutputs_T_56 = cat(decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56) node decoder_decoded_andMatrixOutputs_184_2 = andr(_decoder_decoded_andMatrixOutputs_T_56) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, decoder_decoded_andMatrixOutputs_andMatrixInput_6_53) node decoder_decoded_andMatrixOutputs_lo_57 = cat(decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_47) node decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, decoder_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoder_decoded_andMatrixOutputs_hi_57 = cat(decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_53) node _decoder_decoded_andMatrixOutputs_T_57 = cat(decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57) node decoder_decoded_andMatrixOutputs_148_2 = andr(_decoder_decoded_andMatrixOutputs_T_57) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, decoder_decoded_andMatrixOutputs_andMatrixInput_6_54) node decoder_decoded_andMatrixOutputs_lo_58 = cat(decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_48) node decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, decoder_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoder_decoded_andMatrixOutputs_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_54) node _decoder_decoded_andMatrixOutputs_T_58 = cat(decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58) node decoder_decoded_andMatrixOutputs_115_2 = andr(_decoder_decoded_andMatrixOutputs_T_58) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13) node decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12) node decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, decoder_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, decoder_decoded_andMatrixOutputs_andMatrixInput_9_19) node decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_13) node decoder_decoded_andMatrixOutputs_lo_59 = cat(decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_49) node decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_lo_12) node decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_14) node decoder_decoded_andMatrixOutputs_hi_59 = cat(decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_55) node _decoder_decoded_andMatrixOutputs_T_59 = cat(decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59) node decoder_decoded_andMatrixOutputs_163_2 = andr(_decoder_decoded_andMatrixOutputs_T_59) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, decoder_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, decoder_decoded_andMatrixOutputs_andMatrixInput_6_56) node decoder_decoded_andMatrixOutputs_lo_60 = cat(decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_50) node decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, decoder_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoder_decoded_andMatrixOutputs_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_56) node _decoder_decoded_andMatrixOutputs_T_60 = cat(decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60) node decoder_decoded_andMatrixOutputs_45_2 = andr(_decoder_decoded_andMatrixOutputs_T_60) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_15) node decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, decoder_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_14) node decoder_decoded_andMatrixOutputs_lo_61 = cat(decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_51) node decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_6_57) node decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_15) node decoder_decoded_andMatrixOutputs_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_57) node _decoder_decoded_andMatrixOutputs_T_61 = cat(decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61) node decoder_decoded_andMatrixOutputs_126_2 = andr(_decoder_decoded_andMatrixOutputs_T_61) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, decoder_decoded_andMatrixOutputs_andMatrixInput_12_16) node decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) node decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, decoder_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_15) node decoder_decoded_andMatrixOutputs_lo_62 = cat(decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_52) node decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_6_58) node decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) node decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_16) node decoder_decoded_andMatrixOutputs_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_58) node _decoder_decoded_andMatrixOutputs_T_62 = cat(decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62) node decoder_decoded_andMatrixOutputs_150_2 = andr(_decoder_decoded_andMatrixOutputs_T_62) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoder_decoded_andMatrixOutputs_lo_63 = cat(decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_53) node decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoder_decoded_andMatrixOutputs_hi_63 = cat(decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_59) node _decoder_decoded_andMatrixOutputs_T_63 = cat(decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63) node decoder_decoded_andMatrixOutputs_162_2 = andr(_decoder_decoded_andMatrixOutputs_T_63) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_16) node decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) node decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_16) node decoder_decoded_andMatrixOutputs_lo_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_54) node decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_13) node decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64) node decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_17) node decoder_decoded_andMatrixOutputs_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_60) node _decoder_decoded_andMatrixOutputs_T_64 = cat(decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64) node decoder_decoded_andMatrixOutputs_133_2 = andr(_decoder_decoded_andMatrixOutputs_T_64) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) node decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23) node decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_17) node decoder_decoded_andMatrixOutputs_lo_65 = cat(decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_55) node decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, decoder_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_14) node decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, decoder_decoded_andMatrixOutputs_andMatrixInput_3_65) node decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_18) node decoder_decoded_andMatrixOutputs_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_61) node _decoder_decoded_andMatrixOutputs_T_65 = cat(decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65) node decoder_decoded_andMatrixOutputs_179_2 = andr(_decoder_decoded_andMatrixOutputs_T_65) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, decoder_decoded_andMatrixOutputs_andMatrixInput_15_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_18) node decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_lo_5) node decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) node decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_18) node decoder_decoded_andMatrixOutputs_lo_66 = cat(decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_56) node decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, decoder_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_15) node decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, decoder_decoded_andMatrixOutputs_andMatrixInput_3_66) node decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_19) node decoder_decoded_andMatrixOutputs_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_62) node _decoder_decoded_andMatrixOutputs_T_66 = cat(decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66) node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_66) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_19) node decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16) node decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25) node decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_19) node decoder_decoded_andMatrixOutputs_lo_67 = cat(decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_57) node decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, decoder_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_16) node decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, decoder_decoded_andMatrixOutputs_andMatrixInput_3_67) node decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_20) node decoder_decoded_andMatrixOutputs_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_63) node _decoder_decoded_andMatrixOutputs_T_67 = cat(decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67) node decoder_decoded_andMatrixOutputs_87_2 = andr(_decoder_decoded_andMatrixOutputs_T_67) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20) node decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_17) node decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26) node decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_20) node decoder_decoded_andMatrixOutputs_lo_68 = cat(decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_58) node decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_17) node decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, decoder_decoded_andMatrixOutputs_andMatrixInput_3_68) node decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_21) node decoder_decoded_andMatrixOutputs_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_64) node _decoder_decoded_andMatrixOutputs_T_68 = cat(decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68) node decoder_decoded_andMatrixOutputs_93_2 = andr(_decoder_decoded_andMatrixOutputs_T_68) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, decoder_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoder_decoded_andMatrixOutputs_lo_69 = cat(decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_59) node decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, decoder_decoded_andMatrixOutputs_andMatrixInput_3_69) node decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoder_decoded_andMatrixOutputs_hi_69 = cat(decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_65) node _decoder_decoded_andMatrixOutputs_T_69 = cat(decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69) node decoder_decoded_andMatrixOutputs_65_2 = andr(_decoder_decoded_andMatrixOutputs_T_69) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66) node decoder_decoded_andMatrixOutputs_lo_70 = cat(decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_60) node decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoder_decoded_andMatrixOutputs_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_66) node _decoder_decoded_andMatrixOutputs_T_70 = cat(decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70) node decoder_decoded_andMatrixOutputs_125_2 = andr(_decoder_decoded_andMatrixOutputs_T_70) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, decoder_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, decoder_decoded_andMatrixOutputs_andMatrixInput_6_67) node decoder_decoded_andMatrixOutputs_lo_71 = cat(decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_61) node decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoder_decoded_andMatrixOutputs_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_67) node _decoder_decoded_andMatrixOutputs_T_71 = cat(decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71) node decoder_decoded_andMatrixOutputs_90_2 = andr(_decoder_decoded_andMatrixOutputs_T_71) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68) node decoder_decoded_andMatrixOutputs_lo_72 = cat(decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_62) node decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoder_decoded_andMatrixOutputs_hi_72 = cat(decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_68) node _decoder_decoded_andMatrixOutputs_T_72 = cat(decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72) node decoder_decoded_andMatrixOutputs_111_2 = andr(_decoder_decoded_andMatrixOutputs_T_72) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_21) node decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18) node decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) node decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_21) node decoder_decoded_andMatrixOutputs_lo_73 = cat(decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_63) node decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_18) node decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, decoder_decoded_andMatrixOutputs_andMatrixInput_3_73) node decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_22) node decoder_decoded_andMatrixOutputs_hi_73 = cat(decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_69) node _decoder_decoded_andMatrixOutputs_T_73 = cat(decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73) node decoder_decoded_andMatrixOutputs_172_2 = andr(_decoder_decoded_andMatrixOutputs_T_73) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoder_decoded_andMatrixOutputs_lo_74 = cat(decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_64) node decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, decoder_decoded_andMatrixOutputs_andMatrixInput_3_74) node decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoder_decoded_andMatrixOutputs_hi_74 = cat(decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_70) node _decoder_decoded_andMatrixOutputs_T_74 = cat(decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74) node decoder_decoded_andMatrixOutputs_146_2 = andr(_decoder_decoded_andMatrixOutputs_T_74) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, decoder_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, decoder_decoded_andMatrixOutputs_andMatrixInput_6_71) node decoder_decoded_andMatrixOutputs_lo_75 = cat(decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_65) node decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoder_decoded_andMatrixOutputs_hi_75 = cat(decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_71) node _decoder_decoded_andMatrixOutputs_T_75 = cat(decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75) node decoder_decoded_andMatrixOutputs_170_2 = andr(_decoder_decoded_andMatrixOutputs_T_75) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, decoder_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, decoder_decoded_andMatrixOutputs_andMatrixInput_6_72) node decoder_decoded_andMatrixOutputs_lo_76 = cat(decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_66) node decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoder_decoded_andMatrixOutputs_hi_76 = cat(decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_72) node _decoder_decoded_andMatrixOutputs_T_76 = cat(decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76) node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_76) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_28) node decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, decoder_decoded_andMatrixOutputs_andMatrixInput_6_73) node decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoder_decoded_andMatrixOutputs_lo_77 = cat(decoder_decoded_andMatrixOutputs_lo_hi_76, decoder_decoded_andMatrixOutputs_lo_lo_67) node decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, decoder_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, decoder_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoder_decoded_andMatrixOutputs_hi_77 = cat(decoder_decoded_andMatrixOutputs_hi_hi_77, decoder_decoded_andMatrixOutputs_hi_lo_73) node _decoder_decoded_andMatrixOutputs_T_77 = cat(decoder_decoded_andMatrixOutputs_hi_77, decoder_decoded_andMatrixOutputs_lo_77) node decoder_decoded_andMatrixOutputs_15_2 = andr(_decoder_decoded_andMatrixOutputs_T_77) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, decoder_decoded_andMatrixOutputs_andMatrixInput_13_22) node decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19) node decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_29) node decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_22) node decoder_decoded_andMatrixOutputs_lo_78 = cat(decoder_decoded_andMatrixOutputs_lo_hi_77, decoder_decoded_andMatrixOutputs_lo_lo_68) node decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, decoder_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_19) node decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, decoder_decoded_andMatrixOutputs_andMatrixInput_3_78) node decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, decoder_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_23) node decoder_decoded_andMatrixOutputs_hi_78 = cat(decoder_decoded_andMatrixOutputs_hi_hi_78, decoder_decoded_andMatrixOutputs_hi_lo_74) node _decoder_decoded_andMatrixOutputs_T_78 = cat(decoder_decoded_andMatrixOutputs_hi_78, decoder_decoded_andMatrixOutputs_lo_78) node decoder_decoded_andMatrixOutputs_167_2 = andr(_decoder_decoded_andMatrixOutputs_T_78) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) node decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo_6) node decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, decoder_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30) node decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_23) node decoder_decoded_andMatrixOutputs_lo_79 = cat(decoder_decoded_andMatrixOutputs_lo_hi_78, decoder_decoded_andMatrixOutputs_lo_lo_69) node decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, decoder_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_20) node decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, decoder_decoded_andMatrixOutputs_andMatrixInput_3_79) node decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, decoder_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_24) node decoder_decoded_andMatrixOutputs_hi_79 = cat(decoder_decoded_andMatrixOutputs_hi_hi_79, decoder_decoded_andMatrixOutputs_hi_lo_75) node _decoder_decoded_andMatrixOutputs_T_79 = cat(decoder_decoded_andMatrixOutputs_hi_79, decoder_decoded_andMatrixOutputs_lo_79) node decoder_decoded_andMatrixOutputs_108_2 = andr(_decoder_decoded_andMatrixOutputs_T_79) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, decoder_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoder_decoded_andMatrixOutputs_lo_80 = cat(decoder_decoded_andMatrixOutputs_lo_hi_79, decoder_decoded_andMatrixOutputs_andMatrixInput_6_76) node decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, decoder_decoded_andMatrixOutputs_andMatrixInput_3_80) node decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, decoder_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoder_decoded_andMatrixOutputs_hi_80 = cat(decoder_decoded_andMatrixOutputs_hi_hi_80, decoder_decoded_andMatrixOutputs_hi_lo_76) node _decoder_decoded_andMatrixOutputs_T_80 = cat(decoder_decoded_andMatrixOutputs_hi_80, decoder_decoded_andMatrixOutputs_lo_80) node decoder_decoded_andMatrixOutputs_75_2 = andr(_decoder_decoded_andMatrixOutputs_T_80) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoder_decoded_andMatrixOutputs_lo_81 = cat(decoder_decoded_andMatrixOutputs_lo_hi_80, decoder_decoded_andMatrixOutputs_lo_lo_70) node decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, decoder_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, decoder_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoder_decoded_andMatrixOutputs_hi_81 = cat(decoder_decoded_andMatrixOutputs_hi_hi_81, decoder_decoded_andMatrixOutputs_hi_lo_77) node _decoder_decoded_andMatrixOutputs_T_81 = cat(decoder_decoded_andMatrixOutputs_hi_81, decoder_decoded_andMatrixOutputs_lo_81) node decoder_decoded_andMatrixOutputs_86_2 = andr(_decoder_decoded_andMatrixOutputs_T_81) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_24) node decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21) node decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_32) node decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_24) node decoder_decoded_andMatrixOutputs_lo_82 = cat(decoder_decoded_andMatrixOutputs_lo_hi_81, decoder_decoded_andMatrixOutputs_lo_lo_71) node decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, decoder_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_21) node decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, decoder_decoded_andMatrixOutputs_andMatrixInput_3_82) node decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, decoder_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_25) node decoder_decoded_andMatrixOutputs_hi_82 = cat(decoder_decoded_andMatrixOutputs_hi_hi_82, decoder_decoded_andMatrixOutputs_hi_lo_78) node _decoder_decoded_andMatrixOutputs_T_82 = cat(decoder_decoded_andMatrixOutputs_hi_82, decoder_decoded_andMatrixOutputs_lo_82) node decoder_decoded_andMatrixOutputs_144_2 = andr(_decoder_decoded_andMatrixOutputs_T_82) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, decoder_decoded_andMatrixOutputs_andMatrixInput_13_25) node decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_22) node decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, decoder_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33) node decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_25) node decoder_decoded_andMatrixOutputs_lo_83 = cat(decoder_decoded_andMatrixOutputs_lo_hi_82, decoder_decoded_andMatrixOutputs_lo_lo_72) node decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, decoder_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_22) node decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, decoder_decoded_andMatrixOutputs_andMatrixInput_3_83) node decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, decoder_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_26) node decoder_decoded_andMatrixOutputs_hi_83 = cat(decoder_decoded_andMatrixOutputs_hi_hi_83, decoder_decoded_andMatrixOutputs_hi_lo_79) node _decoder_decoded_andMatrixOutputs_T_83 = cat(decoder_decoded_andMatrixOutputs_hi_83, decoder_decoded_andMatrixOutputs_lo_83) node decoder_decoded_andMatrixOutputs_36_2 = andr(_decoder_decoded_andMatrixOutputs_T_83) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27) node decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26) node decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, decoder_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_26) node decoder_decoded_andMatrixOutputs_lo_84 = cat(decoder_decoded_andMatrixOutputs_lo_hi_83, decoder_decoded_andMatrixOutputs_lo_lo_73) node decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, decoder_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_6_80) node decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, decoder_decoded_andMatrixOutputs_andMatrixInput_3_84) node decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, decoder_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_27) node decoder_decoded_andMatrixOutputs_hi_84 = cat(decoder_decoded_andMatrixOutputs_hi_hi_84, decoder_decoded_andMatrixOutputs_hi_lo_80) node _decoder_decoded_andMatrixOutputs_T_84 = cat(decoder_decoded_andMatrixOutputs_hi_84, decoder_decoded_andMatrixOutputs_lo_84) node decoder_decoded_andMatrixOutputs_41_2 = andr(_decoder_decoded_andMatrixOutputs_T_84) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, decoder_decoded_andMatrixOutputs_andMatrixInput_12_28) node decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_13_27) node decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, decoder_decoded_andMatrixOutputs_andMatrixInput_8_55) node decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_27) node decoder_decoded_andMatrixOutputs_lo_85 = cat(decoder_decoded_andMatrixOutputs_lo_hi_84, decoder_decoded_andMatrixOutputs_lo_lo_74) node decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, decoder_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_6_81) node decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, decoder_decoded_andMatrixOutputs_andMatrixInput_3_85) node decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, decoder_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_28) node decoder_decoded_andMatrixOutputs_hi_85 = cat(decoder_decoded_andMatrixOutputs_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_lo_81) node _decoder_decoded_andMatrixOutputs_T_85 = cat(decoder_decoded_andMatrixOutputs_hi_85, decoder_decoded_andMatrixOutputs_lo_85) node decoder_decoded_andMatrixOutputs_8_2 = andr(_decoder_decoded_andMatrixOutputs_T_85) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28) node decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_23) node decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, decoder_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36) node decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_28) node decoder_decoded_andMatrixOutputs_lo_86 = cat(decoder_decoded_andMatrixOutputs_lo_hi_85, decoder_decoded_andMatrixOutputs_lo_lo_75) node decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, decoder_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, decoder_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_23) node decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, decoder_decoded_andMatrixOutputs_andMatrixInput_3_86) node decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, decoder_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_29) node decoder_decoded_andMatrixOutputs_hi_86 = cat(decoder_decoded_andMatrixOutputs_hi_hi_86, decoder_decoded_andMatrixOutputs_hi_lo_82) node _decoder_decoded_andMatrixOutputs_T_86 = cat(decoder_decoded_andMatrixOutputs_hi_86, decoder_decoded_andMatrixOutputs_lo_86) node decoder_decoded_andMatrixOutputs_102_2 = andr(_decoder_decoded_andMatrixOutputs_T_86) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29) node decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24) node decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_37) node decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_29) node decoder_decoded_andMatrixOutputs_lo_87 = cat(decoder_decoded_andMatrixOutputs_lo_hi_86, decoder_decoded_andMatrixOutputs_lo_lo_76) node decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, decoder_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, decoder_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_24) node decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, decoder_decoded_andMatrixOutputs_andMatrixInput_3_87) node decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, decoder_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_30) node decoder_decoded_andMatrixOutputs_hi_87 = cat(decoder_decoded_andMatrixOutputs_hi_hi_87, decoder_decoded_andMatrixOutputs_hi_lo_83) node _decoder_decoded_andMatrixOutputs_T_87 = cat(decoder_decoded_andMatrixOutputs_hi_87, decoder_decoded_andMatrixOutputs_lo_87) node decoder_decoded_andMatrixOutputs_72_2 = andr(_decoder_decoded_andMatrixOutputs_T_87) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_7, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25) node decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, decoder_decoded_andMatrixOutputs_andMatrixInput_12_31) node decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_30) node decoder_decoded_andMatrixOutputs_lo_88 = cat(decoder_decoded_andMatrixOutputs_lo_hi_87, decoder_decoded_andMatrixOutputs_lo_lo_77) node decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, decoder_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, decoder_decoded_andMatrixOutputs_andMatrixInput_6_84) node decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_25) node decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, decoder_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, decoder_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_31) node decoder_decoded_andMatrixOutputs_hi_88 = cat(decoder_decoded_andMatrixOutputs_hi_hi_88, decoder_decoded_andMatrixOutputs_hi_lo_84) node _decoder_decoded_andMatrixOutputs_T_88 = cat(decoder_decoded_andMatrixOutputs_hi_88, decoder_decoded_andMatrixOutputs_lo_88) node decoder_decoded_andMatrixOutputs_189_2 = andr(_decoder_decoded_andMatrixOutputs_T_88) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, decoder_decoded_andMatrixOutputs_andMatrixInput_15_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, decoder_decoded_andMatrixOutputs_andMatrixInput_13_31) node decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_8) node decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, decoder_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39) node decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_31) node decoder_decoded_andMatrixOutputs_lo_89 = cat(decoder_decoded_andMatrixOutputs_lo_hi_88, decoder_decoded_andMatrixOutputs_lo_lo_78) node decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, decoder_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, decoder_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_26) node decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, decoder_decoded_andMatrixOutputs_andMatrixInput_3_89) node decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, decoder_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_32) node decoder_decoded_andMatrixOutputs_hi_89 = cat(decoder_decoded_andMatrixOutputs_hi_hi_89, decoder_decoded_andMatrixOutputs_hi_lo_85) node _decoder_decoded_andMatrixOutputs_T_89 = cat(decoder_decoded_andMatrixOutputs_hi_89, decoder_decoded_andMatrixOutputs_lo_89) node decoder_decoded_andMatrixOutputs_28_2 = andr(_decoder_decoded_andMatrixOutputs_T_89) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33) node decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_40) node decoder_decoded_andMatrixOutputs_lo_90 = cat(decoder_decoded_andMatrixOutputs_lo_hi_89, decoder_decoded_andMatrixOutputs_lo_lo_79) node decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, decoder_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_86) node decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, decoder_decoded_andMatrixOutputs_andMatrixInput_3_90) node decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, decoder_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_33) node decoder_decoded_andMatrixOutputs_hi_90 = cat(decoder_decoded_andMatrixOutputs_hi_hi_90, decoder_decoded_andMatrixOutputs_hi_lo_86) node _decoder_decoded_andMatrixOutputs_T_90 = cat(decoder_decoded_andMatrixOutputs_hi_90, decoder_decoded_andMatrixOutputs_lo_90) node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_90) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2) node decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_9) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, decoder_decoded_andMatrixOutputs_andMatrixInput_15_9) node decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, decoder_decoded_andMatrixOutputs_andMatrixInput_12_34) node decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32) node decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_32) node decoder_decoded_andMatrixOutputs_lo_91 = cat(decoder_decoded_andMatrixOutputs_lo_hi_90, decoder_decoded_andMatrixOutputs_lo_lo_80) node decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, decoder_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_27) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, decoder_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, decoder_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_34) node decoder_decoded_andMatrixOutputs_hi_91 = cat(decoder_decoded_andMatrixOutputs_hi_hi_91, decoder_decoded_andMatrixOutputs_hi_lo_87) node _decoder_decoded_andMatrixOutputs_T_91 = cat(decoder_decoded_andMatrixOutputs_hi_91, decoder_decoded_andMatrixOutputs_lo_91) node decoder_decoded_andMatrixOutputs_59_2 = andr(_decoder_decoded_andMatrixOutputs_T_91) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33) node decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42) node decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_33) node decoder_decoded_andMatrixOutputs_lo_92 = cat(decoder_decoded_andMatrixOutputs_lo_hi_91, decoder_decoded_andMatrixOutputs_lo_lo_81) node decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, decoder_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, decoder_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_28) node decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, decoder_decoded_andMatrixOutputs_andMatrixInput_3_92) node decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, decoder_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_35) node decoder_decoded_andMatrixOutputs_hi_92 = cat(decoder_decoded_andMatrixOutputs_hi_hi_92, decoder_decoded_andMatrixOutputs_hi_lo_88) node _decoder_decoded_andMatrixOutputs_T_92 = cat(decoder_decoded_andMatrixOutputs_hi_92, decoder_decoded_andMatrixOutputs_lo_92) node decoder_decoded_andMatrixOutputs_43_2 = andr(_decoder_decoded_andMatrixOutputs_T_92) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34) node decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_10) node decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43) node decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_34) node decoder_decoded_andMatrixOutputs_lo_93 = cat(decoder_decoded_andMatrixOutputs_lo_hi_92, decoder_decoded_andMatrixOutputs_lo_lo_82) node decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, decoder_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, decoder_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_29) node decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, decoder_decoded_andMatrixOutputs_andMatrixInput_3_93) node decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, decoder_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_36) node decoder_decoded_andMatrixOutputs_hi_93 = cat(decoder_decoded_andMatrixOutputs_hi_hi_93, decoder_decoded_andMatrixOutputs_hi_lo_89) node _decoder_decoded_andMatrixOutputs_T_93 = cat(decoder_decoded_andMatrixOutputs_hi_93, decoder_decoded_andMatrixOutputs_lo_93) node decoder_decoded_andMatrixOutputs_169_2 = andr(_decoder_decoded_andMatrixOutputs_T_93) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, decoder_decoded_andMatrixOutputs_andMatrixInput_15_11) node decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35) node decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_11) node decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44) node decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_35) node decoder_decoded_andMatrixOutputs_lo_94 = cat(decoder_decoded_andMatrixOutputs_lo_hi_93, decoder_decoded_andMatrixOutputs_lo_lo_83) node decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, decoder_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, decoder_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_30) node decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, decoder_decoded_andMatrixOutputs_andMatrixInput_3_94) node decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, decoder_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_37) node decoder_decoded_andMatrixOutputs_hi_94 = cat(decoder_decoded_andMatrixOutputs_hi_hi_94, decoder_decoded_andMatrixOutputs_hi_lo_90) node _decoder_decoded_andMatrixOutputs_T_94 = cat(decoder_decoded_andMatrixOutputs_hi_94, decoder_decoded_andMatrixOutputs_lo_94) node decoder_decoded_andMatrixOutputs_164_2 = andr(_decoder_decoded_andMatrixOutputs_T_94) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, decoder_decoded_andMatrixOutputs_andMatrixInput_16_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31) node decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_12) node decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, decoder_decoded_andMatrixOutputs_andMatrixInput_12_38) node decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, decoder_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_36) node decoder_decoded_andMatrixOutputs_lo_95 = cat(decoder_decoded_andMatrixOutputs_lo_hi_94, decoder_decoded_andMatrixOutputs_lo_lo_84) node decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, decoder_decoded_andMatrixOutputs_andMatrixInput_6_91) node decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_31) node decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, decoder_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, decoder_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_38) node decoder_decoded_andMatrixOutputs_hi_95 = cat(decoder_decoded_andMatrixOutputs_hi_hi_95, decoder_decoded_andMatrixOutputs_hi_lo_91) node _decoder_decoded_andMatrixOutputs_T_95 = cat(decoder_decoded_andMatrixOutputs_hi_95, decoder_decoded_andMatrixOutputs_lo_95) node decoder_decoded_andMatrixOutputs_137_2 = andr(_decoder_decoded_andMatrixOutputs_T_95) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5) node decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_lo_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, decoder_decoded_andMatrixOutputs_andMatrixInput_14_32) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_39) node decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_37) node decoder_decoded_andMatrixOutputs_lo_96 = cat(decoder_decoded_andMatrixOutputs_lo_hi_95, decoder_decoded_andMatrixOutputs_lo_lo_85) node decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, decoder_decoded_andMatrixOutputs_andMatrixInput_6_92) node decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_32) node decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, decoder_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, decoder_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_39) node decoder_decoded_andMatrixOutputs_hi_96 = cat(decoder_decoded_andMatrixOutputs_hi_hi_96, decoder_decoded_andMatrixOutputs_hi_lo_92) node _decoder_decoded_andMatrixOutputs_T_96 = cat(decoder_decoded_andMatrixOutputs_hi_96, decoder_decoded_andMatrixOutputs_lo_96) node decoder_decoded_andMatrixOutputs_73_2 = andr(_decoder_decoded_andMatrixOutputs_T_96) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, decoder_decoded_andMatrixOutputs_andMatrixInput_26_2) node decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_27_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, decoder_decoded_andMatrixOutputs_andMatrixInput_24_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, decoder_decoded_andMatrixOutputs_andMatrixInput_22_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2) node decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_lo_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_14) node decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2) node decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_38) node decoder_decoded_andMatrixOutputs_lo_97 = cat(decoder_decoded_andMatrixOutputs_lo_hi_96, decoder_decoded_andMatrixOutputs_lo_lo_86) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, decoder_decoded_andMatrixOutputs_andMatrixInput_12_40) node decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, decoder_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2) node decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_33) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, decoder_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_93) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, decoder_decoded_andMatrixOutputs_andMatrixInput_3_97) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, decoder_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2) node decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_40) node decoder_decoded_andMatrixOutputs_hi_97 = cat(decoder_decoded_andMatrixOutputs_hi_hi_97, decoder_decoded_andMatrixOutputs_hi_lo_93) node _decoder_decoded_andMatrixOutputs_T_97 = cat(decoder_decoded_andMatrixOutputs_hi_97, decoder_decoded_andMatrixOutputs_lo_97) node decoder_decoded_andMatrixOutputs_58_2 = andr(_decoder_decoded_andMatrixOutputs_T_97) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, decoder_decoded_andMatrixOutputs_andMatrixInput_29_1) node decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_30_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, decoder_decoded_andMatrixOutputs_andMatrixInput_27_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, decoder_decoded_andMatrixOutputs_andMatrixInput_25_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3) node decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_lo_15) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, decoder_decoded_andMatrixOutputs_andMatrixInput_23_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, decoder_decoded_andMatrixOutputs_andMatrixInput_21_4) node decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_5) node decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3) node decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_39) node decoder_decoded_andMatrixOutputs_lo_98 = cat(decoder_decoded_andMatrixOutputs_lo_hi_97, decoder_decoded_andMatrixOutputs_lo_lo_87) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_15) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39) node decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48) node decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3) node decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_34) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, decoder_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, decoder_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, decoder_decoded_andMatrixOutputs_andMatrixInput_3_98) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, decoder_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3) node decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_41) node decoder_decoded_andMatrixOutputs_hi_98 = cat(decoder_decoded_andMatrixOutputs_hi_hi_98, decoder_decoded_andMatrixOutputs_hi_lo_94) node _decoder_decoded_andMatrixOutputs_T_98 = cat(decoder_decoded_andMatrixOutputs_hi_98, decoder_decoded_andMatrixOutputs_lo_98) node decoder_decoded_andMatrixOutputs_152_2 = andr(_decoder_decoded_andMatrixOutputs_T_98) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(decoder_decoded_plaInput, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, decoder_decoded_andMatrixOutputs_andMatrixInput_26_4) node decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_27_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, decoder_decoded_andMatrixOutputs_andMatrixInput_24_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, decoder_decoded_andMatrixOutputs_andMatrixInput_22_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4) node decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_lo_16) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19_5) node decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16) node decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4) node decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_40) node decoder_decoded_andMatrixOutputs_lo_99 = cat(decoder_decoded_andMatrixOutputs_lo_hi_98, decoder_decoded_andMatrixOutputs_lo_lo_88) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, decoder_decoded_andMatrixOutputs_andMatrixInput_12_42) node decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, decoder_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4) node decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_35) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, decoder_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_95) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, decoder_decoded_andMatrixOutputs_andMatrixInput_3_99) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, decoder_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4) node decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_42) node decoder_decoded_andMatrixOutputs_hi_99 = cat(decoder_decoded_andMatrixOutputs_hi_hi_99, decoder_decoded_andMatrixOutputs_hi_lo_95) node _decoder_decoded_andMatrixOutputs_T_99 = cat(decoder_decoded_andMatrixOutputs_hi_99, decoder_decoded_andMatrixOutputs_lo_99) node decoder_decoded_andMatrixOutputs_161_2 = andr(_decoder_decoded_andMatrixOutputs_T_99) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(decoder_decoded_plaInput, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, decoder_decoded_andMatrixOutputs_andMatrixInput_31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, decoder_decoded_andMatrixOutputs_andMatrixInput_29_2) node decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, decoder_decoded_andMatrixOutputs_andMatrixInput_27_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, decoder_decoded_andMatrixOutputs_andMatrixInput_25_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5) node decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_lo_17) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, decoder_decoded_andMatrixOutputs_andMatrixInput_23_5) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, decoder_decoded_andMatrixOutputs_andMatrixInput_21_6) node decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, decoder_decoded_andMatrixOutputs_andMatrixInput_19_6) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, decoder_decoded_andMatrixOutputs_andMatrixInput_17_7) node decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5) node decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_41) node decoder_decoded_andMatrixOutputs_lo_100 = cat(decoder_decoded_andMatrixOutputs_lo_hi_99, decoder_decoded_andMatrixOutputs_lo_lo_89) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41) node decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50) node decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5) node decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_36) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, decoder_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, decoder_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, decoder_decoded_andMatrixOutputs_andMatrixInput_3_100) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, decoder_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5) node decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_43) node decoder_decoded_andMatrixOutputs_hi_100 = cat(decoder_decoded_andMatrixOutputs_hi_hi_100, decoder_decoded_andMatrixOutputs_hi_lo_96) node _decoder_decoded_andMatrixOutputs_T_100 = cat(decoder_decoded_andMatrixOutputs_hi_100, decoder_decoded_andMatrixOutputs_lo_100) node decoder_decoded_andMatrixOutputs_112_2 = andr(_decoder_decoded_andMatrixOutputs_T_100) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, decoder_decoded_andMatrixOutputs_andMatrixInput_16_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_37) node decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_lo_18) node decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, decoder_decoded_andMatrixOutputs_andMatrixInput_12_44) node decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, decoder_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_42) node decoder_decoded_andMatrixOutputs_lo_101 = cat(decoder_decoded_andMatrixOutputs_lo_hi_100, decoder_decoded_andMatrixOutputs_lo_lo_90) node decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, decoder_decoded_andMatrixOutputs_andMatrixInput_6_97) node decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_37) node decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, decoder_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, decoder_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_44) node decoder_decoded_andMatrixOutputs_hi_101 = cat(decoder_decoded_andMatrixOutputs_hi_hi_101, decoder_decoded_andMatrixOutputs_hi_lo_97) node _decoder_decoded_andMatrixOutputs_T_101 = cat(decoder_decoded_andMatrixOutputs_hi_101, decoder_decoded_andMatrixOutputs_lo_101) node decoder_decoded_andMatrixOutputs_82_2 = andr(_decoder_decoded_andMatrixOutputs_T_101) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19) node decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_19) node decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, decoder_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_43) node decoder_decoded_andMatrixOutputs_lo_102 = cat(decoder_decoded_andMatrixOutputs_lo_hi_101, decoder_decoded_andMatrixOutputs_lo_lo_91) node decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, decoder_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, decoder_decoded_andMatrixOutputs_andMatrixInput_6_98) node decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_38) node decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, decoder_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, decoder_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_hi_lo_45) node decoder_decoded_andMatrixOutputs_hi_102 = cat(decoder_decoded_andMatrixOutputs_hi_hi_102, decoder_decoded_andMatrixOutputs_hi_lo_98) node _decoder_decoded_andMatrixOutputs_T_102 = cat(decoder_decoded_andMatrixOutputs_hi_102, decoder_decoded_andMatrixOutputs_lo_102) node decoder_decoded_andMatrixOutputs_31_2 = andr(_decoder_decoded_andMatrixOutputs_T_102) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_7) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_20, decoder_decoded_andMatrixOutputs_andMatrixInput_16_12) node decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) node decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_20) node decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46) node decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_44) node decoder_decoded_andMatrixOutputs_lo_103 = cat(decoder_decoded_andMatrixOutputs_lo_hi_102, decoder_decoded_andMatrixOutputs_lo_lo_92) node decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, decoder_decoded_andMatrixOutputs_andMatrixInput_6_99) node decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_39) node decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, decoder_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, decoder_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_hi_lo_46) node decoder_decoded_andMatrixOutputs_hi_103 = cat(decoder_decoded_andMatrixOutputs_hi_hi_103, decoder_decoded_andMatrixOutputs_hi_lo_99) node _decoder_decoded_andMatrixOutputs_T_103 = cat(decoder_decoded_andMatrixOutputs_hi_103, decoder_decoded_andMatrixOutputs_lo_103) node decoder_decoded_andMatrixOutputs_13_2 = andr(_decoder_decoded_andMatrixOutputs_T_103) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_7) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_8) node decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_21) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_40, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21) node decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_16_13) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47) node decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_45) node decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_45) node decoder_decoded_andMatrixOutputs_lo_104 = cat(decoder_decoded_andMatrixOutputs_lo_hi_103, decoder_decoded_andMatrixOutputs_lo_lo_93) node decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, decoder_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, decoder_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_40) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, decoder_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, decoder_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_hi_lo_47) node decoder_decoded_andMatrixOutputs_hi_104 = cat(decoder_decoded_andMatrixOutputs_hi_hi_104, decoder_decoded_andMatrixOutputs_hi_lo_100) node _decoder_decoded_andMatrixOutputs_T_104 = cat(decoder_decoded_andMatrixOutputs_hi_104, decoder_decoded_andMatrixOutputs_lo_104) node decoder_decoded_andMatrixOutputs_110_2 = andr(_decoder_decoded_andMatrixOutputs_T_104) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48) node decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_13_46) node decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, decoder_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, decoder_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_46) node decoder_decoded_andMatrixOutputs_lo_105 = cat(decoder_decoded_andMatrixOutputs_lo_hi_104, decoder_decoded_andMatrixOutputs_lo_lo_94) node decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, decoder_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_6_101) node decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, decoder_decoded_andMatrixOutputs_andMatrixInput_3_105) node decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, decoder_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_hi_lo_48) node decoder_decoded_andMatrixOutputs_hi_105 = cat(decoder_decoded_andMatrixOutputs_hi_hi_105, decoder_decoded_andMatrixOutputs_hi_lo_101) node _decoder_decoded_andMatrixOutputs_T_105 = cat(decoder_decoded_andMatrixOutputs_hi_105, decoder_decoded_andMatrixOutputs_lo_105) node decoder_decoded_andMatrixOutputs_64_2 = andr(_decoder_decoded_andMatrixOutputs_T_105) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49) node decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47) node decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, decoder_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_47) node decoder_decoded_andMatrixOutputs_lo_106 = cat(decoder_decoded_andMatrixOutputs_lo_hi_105, decoder_decoded_andMatrixOutputs_lo_lo_95) node decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, decoder_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_6_102) node decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, decoder_decoded_andMatrixOutputs_andMatrixInput_3_106) node decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, decoder_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_hi_lo_49) node decoder_decoded_andMatrixOutputs_hi_106 = cat(decoder_decoded_andMatrixOutputs_hi_hi_106, decoder_decoded_andMatrixOutputs_hi_lo_102) node _decoder_decoded_andMatrixOutputs_T_106 = cat(decoder_decoded_andMatrixOutputs_hi_106, decoder_decoded_andMatrixOutputs_lo_106) node decoder_decoded_andMatrixOutputs_124_2 = andr(_decoder_decoded_andMatrixOutputs_T_106) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50) node decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_13_48) node decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, decoder_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_48) node decoder_decoded_andMatrixOutputs_lo_107 = cat(decoder_decoded_andMatrixOutputs_lo_hi_106, decoder_decoded_andMatrixOutputs_lo_lo_96) node decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, decoder_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_6_103) node decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, decoder_decoded_andMatrixOutputs_andMatrixInput_3_107) node decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, decoder_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_77, decoder_decoded_andMatrixOutputs_hi_hi_lo_50) node decoder_decoded_andMatrixOutputs_hi_107 = cat(decoder_decoded_andMatrixOutputs_hi_hi_107, decoder_decoded_andMatrixOutputs_hi_lo_103) node _decoder_decoded_andMatrixOutputs_T_107 = cat(decoder_decoded_andMatrixOutputs_hi_107, decoder_decoded_andMatrixOutputs_lo_107) node decoder_decoded_andMatrixOutputs_49_2 = andr(_decoder_decoded_andMatrixOutputs_T_107) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51) node decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49) node decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, decoder_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_49) node decoder_decoded_andMatrixOutputs_lo_108 = cat(decoder_decoded_andMatrixOutputs_lo_hi_107, decoder_decoded_andMatrixOutputs_lo_lo_97) node decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, decoder_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_6_104) node decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, decoder_decoded_andMatrixOutputs_andMatrixInput_3_108) node decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, decoder_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_78, decoder_decoded_andMatrixOutputs_hi_hi_lo_51) node decoder_decoded_andMatrixOutputs_hi_108 = cat(decoder_decoded_andMatrixOutputs_hi_hi_108, decoder_decoded_andMatrixOutputs_hi_lo_104) node _decoder_decoded_andMatrixOutputs_T_108 = cat(decoder_decoded_andMatrixOutputs_hi_108, decoder_decoded_andMatrixOutputs_lo_108) node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T_108) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52) node decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50) node decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, decoder_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_50) node decoder_decoded_andMatrixOutputs_lo_109 = cat(decoder_decoded_andMatrixOutputs_lo_hi_108, decoder_decoded_andMatrixOutputs_lo_lo_98) node decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, decoder_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_6_105) node decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, decoder_decoded_andMatrixOutputs_andMatrixInput_3_109) node decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, decoder_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_79, decoder_decoded_andMatrixOutputs_hi_hi_lo_52) node decoder_decoded_andMatrixOutputs_hi_109 = cat(decoder_decoded_andMatrixOutputs_hi_hi_109, decoder_decoded_andMatrixOutputs_hi_lo_105) node _decoder_decoded_andMatrixOutputs_T_109 = cat(decoder_decoded_andMatrixOutputs_hi_109, decoder_decoded_andMatrixOutputs_lo_109) node decoder_decoded_andMatrixOutputs_134_2 = andr(_decoder_decoded_andMatrixOutputs_T_109) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53) node decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51) node decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, decoder_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_51) node decoder_decoded_andMatrixOutputs_lo_110 = cat(decoder_decoded_andMatrixOutputs_lo_hi_109, decoder_decoded_andMatrixOutputs_lo_lo_99) node decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, decoder_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_6_106) node decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, decoder_decoded_andMatrixOutputs_andMatrixInput_3_110) node decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, decoder_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_80, decoder_decoded_andMatrixOutputs_hi_hi_lo_53) node decoder_decoded_andMatrixOutputs_hi_110 = cat(decoder_decoded_andMatrixOutputs_hi_hi_110, decoder_decoded_andMatrixOutputs_hi_lo_106) node _decoder_decoded_andMatrixOutputs_T_110 = cat(decoder_decoded_andMatrixOutputs_hi_110, decoder_decoded_andMatrixOutputs_lo_110) node decoder_decoded_andMatrixOutputs_153_2 = andr(_decoder_decoded_andMatrixOutputs_T_110) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54) node decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52) node decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, decoder_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_52) node decoder_decoded_andMatrixOutputs_lo_111 = cat(decoder_decoded_andMatrixOutputs_lo_hi_110, decoder_decoded_andMatrixOutputs_lo_lo_100) node decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, decoder_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_6_107) node decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, decoder_decoded_andMatrixOutputs_andMatrixInput_3_111) node decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, decoder_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_81, decoder_decoded_andMatrixOutputs_hi_hi_lo_54) node decoder_decoded_andMatrixOutputs_hi_111 = cat(decoder_decoded_andMatrixOutputs_hi_hi_111, decoder_decoded_andMatrixOutputs_hi_lo_107) node _decoder_decoded_andMatrixOutputs_T_111 = cat(decoder_decoded_andMatrixOutputs_hi_111, decoder_decoded_andMatrixOutputs_lo_111) node decoder_decoded_andMatrixOutputs_107_2 = andr(_decoder_decoded_andMatrixOutputs_T_111) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53) node decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_14_41) node decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, decoder_decoded_andMatrixOutputs_andMatrixInput_9_62) node decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_53) node decoder_decoded_andMatrixOutputs_lo_112 = cat(decoder_decoded_andMatrixOutputs_lo_hi_111, decoder_decoded_andMatrixOutputs_lo_lo_101) node decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, decoder_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, decoder_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_41) node decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, decoder_decoded_andMatrixOutputs_andMatrixInput_3_112) node decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, decoder_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_82, decoder_decoded_andMatrixOutputs_hi_hi_lo_55) node decoder_decoded_andMatrixOutputs_hi_112 = cat(decoder_decoded_andMatrixOutputs_hi_hi_112, decoder_decoded_andMatrixOutputs_hi_lo_108) node _decoder_decoded_andMatrixOutputs_T_112 = cat(decoder_decoded_andMatrixOutputs_hi_112, decoder_decoded_andMatrixOutputs_lo_112) node decoder_decoded_andMatrixOutputs_187_2 = andr(_decoder_decoded_andMatrixOutputs_T_112) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54) node decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42) node decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, decoder_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, decoder_decoded_andMatrixOutputs_andMatrixInput_9_63) node decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_54) node decoder_decoded_andMatrixOutputs_lo_113 = cat(decoder_decoded_andMatrixOutputs_lo_hi_112, decoder_decoded_andMatrixOutputs_lo_lo_102) node decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, decoder_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, decoder_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_42) node decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, decoder_decoded_andMatrixOutputs_andMatrixInput_3_113) node decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, decoder_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_83, decoder_decoded_andMatrixOutputs_hi_hi_lo_56) node decoder_decoded_andMatrixOutputs_hi_113 = cat(decoder_decoded_andMatrixOutputs_hi_hi_113, decoder_decoded_andMatrixOutputs_hi_lo_109) node _decoder_decoded_andMatrixOutputs_T_113 = cat(decoder_decoded_andMatrixOutputs_hi_113, decoder_decoded_andMatrixOutputs_lo_113) node decoder_decoded_andMatrixOutputs_46_2 = andr(_decoder_decoded_andMatrixOutputs_T_113) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, decoder_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoder_decoded_andMatrixOutputs_lo_114 = cat(decoder_decoded_andMatrixOutputs_lo_hi_113, decoder_decoded_andMatrixOutputs_lo_lo_103) node decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, decoder_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, decoder_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_84, decoder_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoder_decoded_andMatrixOutputs_hi_114 = cat(decoder_decoded_andMatrixOutputs_hi_hi_114, decoder_decoded_andMatrixOutputs_hi_lo_110) node _decoder_decoded_andMatrixOutputs_T_114 = cat(decoder_decoded_andMatrixOutputs_hi_114, decoder_decoded_andMatrixOutputs_lo_114) node decoder_decoded_andMatrixOutputs_78_2 = andr(_decoder_decoded_andMatrixOutputs_T_114) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55) node decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_andMatrixInput_14_43) node decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, decoder_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, decoder_decoded_andMatrixOutputs_andMatrixInput_9_65) node decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_55) node decoder_decoded_andMatrixOutputs_lo_115 = cat(decoder_decoded_andMatrixOutputs_lo_hi_114, decoder_decoded_andMatrixOutputs_lo_lo_104) node decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, decoder_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, decoder_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_43) node decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, decoder_decoded_andMatrixOutputs_andMatrixInput_3_115) node decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, decoder_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_hi_lo_57) node decoder_decoded_andMatrixOutputs_hi_115 = cat(decoder_decoded_andMatrixOutputs_hi_hi_115, decoder_decoded_andMatrixOutputs_hi_lo_111) node _decoder_decoded_andMatrixOutputs_T_115 = cat(decoder_decoded_andMatrixOutputs_hi_115, decoder_decoded_andMatrixOutputs_lo_115) node decoder_decoded_andMatrixOutputs_159_2 = andr(_decoder_decoded_andMatrixOutputs_T_115) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, decoder_decoded_andMatrixOutputs_andMatrixInput_13_56) node decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_14_44) node decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, decoder_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, decoder_decoded_andMatrixOutputs_andMatrixInput_9_66) node decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_56) node decoder_decoded_andMatrixOutputs_lo_116 = cat(decoder_decoded_andMatrixOutputs_lo_hi_115, decoder_decoded_andMatrixOutputs_lo_lo_105) node decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, decoder_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, decoder_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_44) node decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, decoder_decoded_andMatrixOutputs_andMatrixInput_3_116) node decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, decoder_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_86, decoder_decoded_andMatrixOutputs_hi_hi_lo_58) node decoder_decoded_andMatrixOutputs_hi_116 = cat(decoder_decoded_andMatrixOutputs_hi_hi_116, decoder_decoded_andMatrixOutputs_hi_lo_112) node _decoder_decoded_andMatrixOutputs_T_116 = cat(decoder_decoded_andMatrixOutputs_hi_116, decoder_decoded_andMatrixOutputs_lo_116) node decoder_decoded_andMatrixOutputs_34_2 = andr(_decoder_decoded_andMatrixOutputs_T_116) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, decoder_decoded_andMatrixOutputs_andMatrixInput_13_57) node decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_14_45) node decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, decoder_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, decoder_decoded_andMatrixOutputs_andMatrixInput_9_67) node decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_57) node decoder_decoded_andMatrixOutputs_lo_117 = cat(decoder_decoded_andMatrixOutputs_lo_hi_116, decoder_decoded_andMatrixOutputs_lo_lo_106) node decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, decoder_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, decoder_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_45) node decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, decoder_decoded_andMatrixOutputs_andMatrixInput_3_117) node decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, decoder_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_87, decoder_decoded_andMatrixOutputs_hi_hi_lo_59) node decoder_decoded_andMatrixOutputs_hi_117 = cat(decoder_decoded_andMatrixOutputs_hi_hi_117, decoder_decoded_andMatrixOutputs_hi_lo_113) node _decoder_decoded_andMatrixOutputs_T_117 = cat(decoder_decoded_andMatrixOutputs_hi_117, decoder_decoded_andMatrixOutputs_lo_117) node decoder_decoded_andMatrixOutputs_85_2 = andr(_decoder_decoded_andMatrixOutputs_T_117) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, decoder_decoded_andMatrixOutputs_andMatrixInput_13_58) node decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_14_46) node decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, decoder_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, decoder_decoded_andMatrixOutputs_andMatrixInput_9_68) node decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_68, decoder_decoded_andMatrixOutputs_lo_hi_lo_58) node decoder_decoded_andMatrixOutputs_lo_118 = cat(decoder_decoded_andMatrixOutputs_lo_hi_117, decoder_decoded_andMatrixOutputs_lo_lo_107) node decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, decoder_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, decoder_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_46) node decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, decoder_decoded_andMatrixOutputs_andMatrixInput_3_118) node decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, decoder_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_88, decoder_decoded_andMatrixOutputs_hi_hi_lo_60) node decoder_decoded_andMatrixOutputs_hi_118 = cat(decoder_decoded_andMatrixOutputs_hi_hi_118, decoder_decoded_andMatrixOutputs_hi_lo_114) node _decoder_decoded_andMatrixOutputs_T_118 = cat(decoder_decoded_andMatrixOutputs_hi_118, decoder_decoded_andMatrixOutputs_lo_118) node decoder_decoded_andMatrixOutputs_10_2 = andr(_decoder_decoded_andMatrixOutputs_T_118) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, decoder_decoded_andMatrixOutputs_andMatrixInput_13_59) node decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_14_47) node decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, decoder_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, decoder_decoded_andMatrixOutputs_andMatrixInput_9_69) node decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_69, decoder_decoded_andMatrixOutputs_lo_hi_lo_59) node decoder_decoded_andMatrixOutputs_lo_119 = cat(decoder_decoded_andMatrixOutputs_lo_hi_118, decoder_decoded_andMatrixOutputs_lo_lo_108) node decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, decoder_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, decoder_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_lo_47) node decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, decoder_decoded_andMatrixOutputs_andMatrixInput_3_119) node decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, decoder_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_89, decoder_decoded_andMatrixOutputs_hi_hi_lo_61) node decoder_decoded_andMatrixOutputs_hi_119 = cat(decoder_decoded_andMatrixOutputs_hi_hi_119, decoder_decoded_andMatrixOutputs_hi_lo_115) node _decoder_decoded_andMatrixOutputs_T_119 = cat(decoder_decoded_andMatrixOutputs_hi_119, decoder_decoded_andMatrixOutputs_lo_119) node decoder_decoded_andMatrixOutputs_92_2 = andr(_decoder_decoded_andMatrixOutputs_T_119) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, decoder_decoded_andMatrixOutputs_andMatrixInput_13_60) node decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_14_48) node decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, decoder_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, decoder_decoded_andMatrixOutputs_andMatrixInput_9_70) node decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_70, decoder_decoded_andMatrixOutputs_lo_hi_lo_60) node decoder_decoded_andMatrixOutputs_lo_120 = cat(decoder_decoded_andMatrixOutputs_lo_hi_119, decoder_decoded_andMatrixOutputs_lo_lo_109) node decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, decoder_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, decoder_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_lo_48) node decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, decoder_decoded_andMatrixOutputs_andMatrixInput_3_120) node decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, decoder_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_90, decoder_decoded_andMatrixOutputs_hi_hi_lo_62) node decoder_decoded_andMatrixOutputs_hi_120 = cat(decoder_decoded_andMatrixOutputs_hi_hi_120, decoder_decoded_andMatrixOutputs_hi_lo_116) node _decoder_decoded_andMatrixOutputs_T_120 = cat(decoder_decoded_andMatrixOutputs_hi_120, decoder_decoded_andMatrixOutputs_lo_120) node decoder_decoded_andMatrixOutputs_180_2 = andr(_decoder_decoded_andMatrixOutputs_T_120) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_22) node decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, decoder_decoded_andMatrixOutputs_andMatrixInput_13_61) node decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_lo_22) node decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, decoder_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, decoder_decoded_andMatrixOutputs_andMatrixInput_9_71) node decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_71, decoder_decoded_andMatrixOutputs_lo_hi_lo_61) node decoder_decoded_andMatrixOutputs_lo_121 = cat(decoder_decoded_andMatrixOutputs_lo_hi_120, decoder_decoded_andMatrixOutputs_lo_lo_110) node decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, decoder_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, decoder_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_lo_49) node decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, decoder_decoded_andMatrixOutputs_andMatrixInput_3_121) node decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, decoder_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_91, decoder_decoded_andMatrixOutputs_hi_hi_lo_63) node decoder_decoded_andMatrixOutputs_hi_121 = cat(decoder_decoded_andMatrixOutputs_hi_hi_121, decoder_decoded_andMatrixOutputs_hi_lo_117) node _decoder_decoded_andMatrixOutputs_T_121 = cat(decoder_decoded_andMatrixOutputs_hi_121, decoder_decoded_andMatrixOutputs_lo_121) node decoder_decoded_andMatrixOutputs_44_2 = andr(_decoder_decoded_andMatrixOutputs_T_121) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_50, decoder_decoded_andMatrixOutputs_andMatrixInput_15_23) node decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, decoder_decoded_andMatrixOutputs_andMatrixInput_13_62) node decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_lo_23) node decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, decoder_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, decoder_decoded_andMatrixOutputs_andMatrixInput_9_72) node decoder_decoded_andMatrixOutputs_lo_hi_121 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_72, decoder_decoded_andMatrixOutputs_lo_hi_lo_62) node decoder_decoded_andMatrixOutputs_lo_122 = cat(decoder_decoded_andMatrixOutputs_lo_hi_121, decoder_decoded_andMatrixOutputs_lo_lo_111) node decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, decoder_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, decoder_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_lo_50) node decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, decoder_decoded_andMatrixOutputs_andMatrixInput_3_122) node decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, decoder_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoder_decoded_andMatrixOutputs_hi_hi_122 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_92, decoder_decoded_andMatrixOutputs_hi_hi_lo_64) node decoder_decoded_andMatrixOutputs_hi_122 = cat(decoder_decoded_andMatrixOutputs_hi_hi_122, decoder_decoded_andMatrixOutputs_hi_lo_118) node _decoder_decoded_andMatrixOutputs_T_122 = cat(decoder_decoded_andMatrixOutputs_hi_122, decoder_decoded_andMatrixOutputs_lo_122) node decoder_decoded_andMatrixOutputs_135_2 = andr(_decoder_decoded_andMatrixOutputs_T_122) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, decoder_decoded_andMatrixOutputs_andMatrixInput_14_51) node decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_lo_24) node decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, decoder_decoded_andMatrixOutputs_andMatrixInput_12_65) node decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, decoder_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoder_decoded_andMatrixOutputs_lo_hi_122 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_73, decoder_decoded_andMatrixOutputs_lo_hi_lo_63) node decoder_decoded_andMatrixOutputs_lo_123 = cat(decoder_decoded_andMatrixOutputs_lo_hi_122, decoder_decoded_andMatrixOutputs_lo_lo_112) node decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, decoder_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, decoder_decoded_andMatrixOutputs_andMatrixInput_6_119) node decoder_decoded_andMatrixOutputs_hi_lo_119 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_lo_51) node decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, decoder_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, decoder_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoder_decoded_andMatrixOutputs_hi_hi_123 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_93, decoder_decoded_andMatrixOutputs_hi_hi_lo_65) node decoder_decoded_andMatrixOutputs_hi_123 = cat(decoder_decoded_andMatrixOutputs_hi_hi_123, decoder_decoded_andMatrixOutputs_hi_lo_119) node _decoder_decoded_andMatrixOutputs_T_123 = cat(decoder_decoded_andMatrixOutputs_hi_123, decoder_decoded_andMatrixOutputs_lo_123) node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_123) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(decoder_decoded_plaInput, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, decoder_decoded_andMatrixOutputs_andMatrixInput_21_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9) node decoder_decoded_andMatrixOutputs_lo_lo_113 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_lo_25) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25) node decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, decoder_decoded_andMatrixOutputs_andMatrixInput_12_66) node decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_64) node decoder_decoded_andMatrixOutputs_lo_hi_123 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_74, decoder_decoded_andMatrixOutputs_lo_hi_lo_64) node decoder_decoded_andMatrixOutputs_lo_124 = cat(decoder_decoded_andMatrixOutputs_lo_hi_123, decoder_decoded_andMatrixOutputs_lo_lo_113) node decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, decoder_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, decoder_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoder_decoded_andMatrixOutputs_hi_lo_120 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_lo_52) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, decoder_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, decoder_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoder_decoded_andMatrixOutputs_hi_hi_124 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_94, decoder_decoded_andMatrixOutputs_hi_hi_lo_66) node decoder_decoded_andMatrixOutputs_hi_124 = cat(decoder_decoded_andMatrixOutputs_hi_hi_124, decoder_decoded_andMatrixOutputs_hi_lo_120) node _decoder_decoded_andMatrixOutputs_T_124 = cat(decoder_decoded_andMatrixOutputs_hi_124, decoder_decoded_andMatrixOutputs_lo_124) node decoder_decoded_andMatrixOutputs_188_2 = andr(_decoder_decoded_andMatrixOutputs_T_124) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, decoder_decoded_andMatrixOutputs_andMatrixInput_15_26) node decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, decoder_decoded_andMatrixOutputs_andMatrixInput_13_65) node decoder_decoded_andMatrixOutputs_lo_lo_114 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_lo_26) node decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, decoder_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, decoder_decoded_andMatrixOutputs_andMatrixInput_9_75) node decoder_decoded_andMatrixOutputs_lo_hi_124 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_75, decoder_decoded_andMatrixOutputs_lo_hi_lo_65) node decoder_decoded_andMatrixOutputs_lo_125 = cat(decoder_decoded_andMatrixOutputs_lo_hi_124, decoder_decoded_andMatrixOutputs_lo_lo_114) node decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, decoder_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, decoder_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoder_decoded_andMatrixOutputs_hi_lo_121 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_lo_53) node decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, decoder_decoded_andMatrixOutputs_andMatrixInput_3_125) node decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, decoder_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoder_decoded_andMatrixOutputs_hi_hi_125 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_95, decoder_decoded_andMatrixOutputs_hi_hi_lo_67) node decoder_decoded_andMatrixOutputs_hi_125 = cat(decoder_decoded_andMatrixOutputs_hi_hi_125, decoder_decoded_andMatrixOutputs_hi_lo_121) node _decoder_decoded_andMatrixOutputs_T_125 = cat(decoder_decoded_andMatrixOutputs_hi_125, decoder_decoded_andMatrixOutputs_lo_125) node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_125) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27) node decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, decoder_decoded_andMatrixOutputs_andMatrixInput_13_66) node decoder_decoded_andMatrixOutputs_lo_lo_115 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_lo_27) node decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, decoder_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, decoder_decoded_andMatrixOutputs_andMatrixInput_9_76) node decoder_decoded_andMatrixOutputs_lo_hi_125 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_76, decoder_decoded_andMatrixOutputs_lo_hi_lo_66) node decoder_decoded_andMatrixOutputs_lo_126 = cat(decoder_decoded_andMatrixOutputs_lo_hi_125, decoder_decoded_andMatrixOutputs_lo_lo_115) node decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, decoder_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, decoder_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoder_decoded_andMatrixOutputs_hi_lo_122 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_lo_54) node decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, decoder_decoded_andMatrixOutputs_andMatrixInput_3_126) node decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, decoder_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoder_decoded_andMatrixOutputs_hi_hi_126 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_96, decoder_decoded_andMatrixOutputs_hi_hi_lo_68) node decoder_decoded_andMatrixOutputs_hi_126 = cat(decoder_decoded_andMatrixOutputs_hi_hi_126, decoder_decoded_andMatrixOutputs_hi_lo_122) node _decoder_decoded_andMatrixOutputs_T_126 = cat(decoder_decoded_andMatrixOutputs_hi_126, decoder_decoded_andMatrixOutputs_lo_126) node decoder_decoded_andMatrixOutputs_25_2 = andr(_decoder_decoded_andMatrixOutputs_T_126) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, decoder_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoder_decoded_andMatrixOutputs_lo_lo_116 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_71, decoder_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, decoder_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoder_decoded_andMatrixOutputs_lo_hi_126 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoder_decoded_andMatrixOutputs_lo_127 = cat(decoder_decoded_andMatrixOutputs_lo_hi_126, decoder_decoded_andMatrixOutputs_lo_lo_116) node decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, decoder_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoder_decoded_andMatrixOutputs_hi_lo_123 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, decoder_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoder_decoded_andMatrixOutputs_hi_hi_127 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_97, decoder_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoder_decoded_andMatrixOutputs_hi_127 = cat(decoder_decoded_andMatrixOutputs_hi_hi_127, decoder_decoded_andMatrixOutputs_hi_lo_123) node _decoder_decoded_andMatrixOutputs_T_127 = cat(decoder_decoded_andMatrixOutputs_hi_127, decoder_decoded_andMatrixOutputs_lo_127) node decoder_decoded_andMatrixOutputs_57_2 = andr(_decoder_decoded_andMatrixOutputs_T_127) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, decoder_decoded_andMatrixOutputs_andMatrixInput_13_67) node decoder_decoded_andMatrixOutputs_lo_lo_117 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_72, decoder_decoded_andMatrixOutputs_andMatrixInput_14_55) node decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, decoder_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, decoder_decoded_andMatrixOutputs_andMatrixInput_9_78) node decoder_decoded_andMatrixOutputs_lo_hi_127 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_78, decoder_decoded_andMatrixOutputs_lo_hi_lo_67) node decoder_decoded_andMatrixOutputs_lo_128 = cat(decoder_decoded_andMatrixOutputs_lo_hi_127, decoder_decoded_andMatrixOutputs_lo_lo_117) node decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, decoder_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, decoder_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoder_decoded_andMatrixOutputs_hi_lo_124 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_lo_55) node decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, decoder_decoded_andMatrixOutputs_andMatrixInput_3_128) node decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, decoder_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoder_decoded_andMatrixOutputs_hi_hi_128 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_98, decoder_decoded_andMatrixOutputs_hi_hi_lo_69) node decoder_decoded_andMatrixOutputs_hi_128 = cat(decoder_decoded_andMatrixOutputs_hi_hi_128, decoder_decoded_andMatrixOutputs_hi_lo_124) node _decoder_decoded_andMatrixOutputs_T_128 = cat(decoder_decoded_andMatrixOutputs_hi_128, decoder_decoded_andMatrixOutputs_lo_128) node decoder_decoded_andMatrixOutputs_147_2 = andr(_decoder_decoded_andMatrixOutputs_T_128) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28) node decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, decoder_decoded_andMatrixOutputs_andMatrixInput_13_68) node decoder_decoded_andMatrixOutputs_lo_lo_118 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_lo_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, decoder_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, decoder_decoded_andMatrixOutputs_andMatrixInput_9_79) node decoder_decoded_andMatrixOutputs_lo_hi_128 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_79, decoder_decoded_andMatrixOutputs_lo_hi_lo_68) node decoder_decoded_andMatrixOutputs_lo_129 = cat(decoder_decoded_andMatrixOutputs_lo_hi_128, decoder_decoded_andMatrixOutputs_lo_lo_118) node decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, decoder_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, decoder_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoder_decoded_andMatrixOutputs_hi_lo_125 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_lo_56) node decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, decoder_decoded_andMatrixOutputs_andMatrixInput_3_129) node decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, decoder_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoder_decoded_andMatrixOutputs_hi_hi_129 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_99, decoder_decoded_andMatrixOutputs_hi_hi_lo_70) node decoder_decoded_andMatrixOutputs_hi_129 = cat(decoder_decoded_andMatrixOutputs_hi_hi_129, decoder_decoded_andMatrixOutputs_hi_lo_125) node _decoder_decoded_andMatrixOutputs_T_129 = cat(decoder_decoded_andMatrixOutputs_hi_129, decoder_decoded_andMatrixOutputs_lo_129) node decoder_decoded_andMatrixOutputs_27_2 = andr(_decoder_decoded_andMatrixOutputs_T_129) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, decoder_decoded_andMatrixOutputs_andMatrixInput_13_69) node decoder_decoded_andMatrixOutputs_lo_lo_119 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_14_57) node decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, decoder_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, decoder_decoded_andMatrixOutputs_andMatrixInput_9_80) node decoder_decoded_andMatrixOutputs_lo_hi_129 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_80, decoder_decoded_andMatrixOutputs_lo_hi_lo_69) node decoder_decoded_andMatrixOutputs_lo_130 = cat(decoder_decoded_andMatrixOutputs_lo_hi_129, decoder_decoded_andMatrixOutputs_lo_lo_119) node decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, decoder_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, decoder_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoder_decoded_andMatrixOutputs_hi_lo_126 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_77, decoder_decoded_andMatrixOutputs_hi_lo_lo_57) node decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, decoder_decoded_andMatrixOutputs_andMatrixInput_3_130) node decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, decoder_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoder_decoded_andMatrixOutputs_hi_hi_130 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_100, decoder_decoded_andMatrixOutputs_hi_hi_lo_71) node decoder_decoded_andMatrixOutputs_hi_130 = cat(decoder_decoded_andMatrixOutputs_hi_hi_130, decoder_decoded_andMatrixOutputs_hi_lo_126) node _decoder_decoded_andMatrixOutputs_T_130 = cat(decoder_decoded_andMatrixOutputs_hi_130, decoder_decoded_andMatrixOutputs_lo_130) node decoder_decoded_andMatrixOutputs_51_2 = andr(_decoder_decoded_andMatrixOutputs_T_130) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, decoder_decoded_andMatrixOutputs_andMatrixInput_13_70) node decoder_decoded_andMatrixOutputs_lo_lo_120 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_75, decoder_decoded_andMatrixOutputs_andMatrixInput_14_58) node decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, decoder_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, decoder_decoded_andMatrixOutputs_andMatrixInput_9_81) node decoder_decoded_andMatrixOutputs_lo_hi_130 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_81, decoder_decoded_andMatrixOutputs_lo_hi_lo_70) node decoder_decoded_andMatrixOutputs_lo_131 = cat(decoder_decoded_andMatrixOutputs_lo_hi_130, decoder_decoded_andMatrixOutputs_lo_lo_120) node decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, decoder_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, decoder_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoder_decoded_andMatrixOutputs_hi_lo_127 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_78, decoder_decoded_andMatrixOutputs_hi_lo_lo_58) node decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, decoder_decoded_andMatrixOutputs_andMatrixInput_3_131) node decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, decoder_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoder_decoded_andMatrixOutputs_hi_hi_131 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_101, decoder_decoded_andMatrixOutputs_hi_hi_lo_72) node decoder_decoded_andMatrixOutputs_hi_131 = cat(decoder_decoded_andMatrixOutputs_hi_hi_131, decoder_decoded_andMatrixOutputs_hi_lo_127) node _decoder_decoded_andMatrixOutputs_T_131 = cat(decoder_decoded_andMatrixOutputs_hi_131, decoder_decoded_andMatrixOutputs_lo_131) node decoder_decoded_andMatrixOutputs_138_2 = andr(_decoder_decoded_andMatrixOutputs_T_131) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_59, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29) node decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, decoder_decoded_andMatrixOutputs_andMatrixInput_13_71) node decoder_decoded_andMatrixOutputs_lo_lo_121 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_76, decoder_decoded_andMatrixOutputs_lo_lo_lo_29) node decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, decoder_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, decoder_decoded_andMatrixOutputs_andMatrixInput_9_82) node decoder_decoded_andMatrixOutputs_lo_hi_131 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_82, decoder_decoded_andMatrixOutputs_lo_hi_lo_71) node decoder_decoded_andMatrixOutputs_lo_132 = cat(decoder_decoded_andMatrixOutputs_lo_hi_131, decoder_decoded_andMatrixOutputs_lo_lo_121) node decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, decoder_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, decoder_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoder_decoded_andMatrixOutputs_hi_lo_128 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_79, decoder_decoded_andMatrixOutputs_hi_lo_lo_59) node decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, decoder_decoded_andMatrixOutputs_andMatrixInput_3_132) node decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, decoder_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoder_decoded_andMatrixOutputs_hi_hi_132 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_102, decoder_decoded_andMatrixOutputs_hi_hi_lo_73) node decoder_decoded_andMatrixOutputs_hi_132 = cat(decoder_decoded_andMatrixOutputs_hi_hi_132, decoder_decoded_andMatrixOutputs_hi_lo_128) node _decoder_decoded_andMatrixOutputs_T_132 = cat(decoder_decoded_andMatrixOutputs_hi_132, decoder_decoded_andMatrixOutputs_lo_132) node decoder_decoded_andMatrixOutputs_178_2 = andr(_decoder_decoded_andMatrixOutputs_T_132) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, decoder_decoded_andMatrixOutputs_andMatrixInput_13_72) node decoder_decoded_andMatrixOutputs_lo_lo_122 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_14_60) node decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, decoder_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, decoder_decoded_andMatrixOutputs_andMatrixInput_9_83) node decoder_decoded_andMatrixOutputs_lo_hi_132 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_83, decoder_decoded_andMatrixOutputs_lo_hi_lo_72) node decoder_decoded_andMatrixOutputs_lo_133 = cat(decoder_decoded_andMatrixOutputs_lo_hi_132, decoder_decoded_andMatrixOutputs_lo_lo_122) node decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, decoder_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, decoder_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoder_decoded_andMatrixOutputs_hi_lo_129 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_80, decoder_decoded_andMatrixOutputs_hi_lo_lo_60) node decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, decoder_decoded_andMatrixOutputs_andMatrixInput_3_133) node decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, decoder_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoder_decoded_andMatrixOutputs_hi_hi_133 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_103, decoder_decoded_andMatrixOutputs_hi_hi_lo_74) node decoder_decoded_andMatrixOutputs_hi_133 = cat(decoder_decoded_andMatrixOutputs_hi_hi_133, decoder_decoded_andMatrixOutputs_hi_lo_129) node _decoder_decoded_andMatrixOutputs_T_133 = cat(decoder_decoded_andMatrixOutputs_hi_133, decoder_decoded_andMatrixOutputs_lo_133) node decoder_decoded_andMatrixOutputs_174_2 = andr(_decoder_decoded_andMatrixOutputs_T_133) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, decoder_decoded_andMatrixOutputs_andMatrixInput_13_73) node decoder_decoded_andMatrixOutputs_lo_lo_123 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_78, decoder_decoded_andMatrixOutputs_lo_lo_lo_30) node decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, decoder_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, decoder_decoded_andMatrixOutputs_andMatrixInput_9_84) node decoder_decoded_andMatrixOutputs_lo_hi_133 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_84, decoder_decoded_andMatrixOutputs_lo_hi_lo_73) node decoder_decoded_andMatrixOutputs_lo_134 = cat(decoder_decoded_andMatrixOutputs_lo_hi_133, decoder_decoded_andMatrixOutputs_lo_lo_123) node decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, decoder_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, decoder_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoder_decoded_andMatrixOutputs_hi_lo_130 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_81, decoder_decoded_andMatrixOutputs_hi_lo_lo_61) node decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, decoder_decoded_andMatrixOutputs_andMatrixInput_3_134) node decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, decoder_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoder_decoded_andMatrixOutputs_hi_hi_134 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_104, decoder_decoded_andMatrixOutputs_hi_hi_lo_75) node decoder_decoded_andMatrixOutputs_hi_134 = cat(decoder_decoded_andMatrixOutputs_hi_hi_134, decoder_decoded_andMatrixOutputs_hi_lo_130) node _decoder_decoded_andMatrixOutputs_T_134 = cat(decoder_decoded_andMatrixOutputs_hi_134, decoder_decoded_andMatrixOutputs_lo_134) node decoder_decoded_andMatrixOutputs_120_2 = andr(_decoder_decoded_andMatrixOutputs_T_134) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, decoder_decoded_andMatrixOutputs_andMatrixInput_13_74) node decoder_decoded_andMatrixOutputs_lo_lo_124 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_79, decoder_decoded_andMatrixOutputs_lo_lo_lo_31) node decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, decoder_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, decoder_decoded_andMatrixOutputs_andMatrixInput_9_85) node decoder_decoded_andMatrixOutputs_lo_hi_134 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_85, decoder_decoded_andMatrixOutputs_lo_hi_lo_74) node decoder_decoded_andMatrixOutputs_lo_135 = cat(decoder_decoded_andMatrixOutputs_lo_hi_134, decoder_decoded_andMatrixOutputs_lo_lo_124) node decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, decoder_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, decoder_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoder_decoded_andMatrixOutputs_hi_lo_131 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_82, decoder_decoded_andMatrixOutputs_hi_lo_lo_62) node decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, decoder_decoded_andMatrixOutputs_andMatrixInput_3_135) node decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, decoder_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoder_decoded_andMatrixOutputs_hi_hi_135 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_105, decoder_decoded_andMatrixOutputs_hi_hi_lo_76) node decoder_decoded_andMatrixOutputs_hi_135 = cat(decoder_decoded_andMatrixOutputs_hi_hi_135, decoder_decoded_andMatrixOutputs_hi_lo_131) node _decoder_decoded_andMatrixOutputs_T_135 = cat(decoder_decoded_andMatrixOutputs_hi_135, decoder_decoded_andMatrixOutputs_lo_135) node decoder_decoded_andMatrixOutputs_19_2 = andr(_decoder_decoded_andMatrixOutputs_T_135) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, decoder_decoded_andMatrixOutputs_andMatrixInput_13_75) node decoder_decoded_andMatrixOutputs_lo_lo_125 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_80, decoder_decoded_andMatrixOutputs_andMatrixInput_14_63) node decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, decoder_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, decoder_decoded_andMatrixOutputs_andMatrixInput_9_86) node decoder_decoded_andMatrixOutputs_lo_hi_135 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_86, decoder_decoded_andMatrixOutputs_lo_hi_lo_75) node decoder_decoded_andMatrixOutputs_lo_136 = cat(decoder_decoded_andMatrixOutputs_lo_hi_135, decoder_decoded_andMatrixOutputs_lo_lo_125) node decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, decoder_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, decoder_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoder_decoded_andMatrixOutputs_hi_lo_132 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_83, decoder_decoded_andMatrixOutputs_hi_lo_lo_63) node decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, decoder_decoded_andMatrixOutputs_andMatrixInput_3_136) node decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, decoder_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoder_decoded_andMatrixOutputs_hi_hi_136 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_106, decoder_decoded_andMatrixOutputs_hi_hi_lo_77) node decoder_decoded_andMatrixOutputs_hi_136 = cat(decoder_decoded_andMatrixOutputs_hi_hi_136, decoder_decoded_andMatrixOutputs_hi_lo_132) node _decoder_decoded_andMatrixOutputs_T_136 = cat(decoder_decoded_andMatrixOutputs_hi_136, decoder_decoded_andMatrixOutputs_lo_136) node decoder_decoded_andMatrixOutputs_63_2 = andr(_decoder_decoded_andMatrixOutputs_T_136) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32) node decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, decoder_decoded_andMatrixOutputs_andMatrixInput_13_76) node decoder_decoded_andMatrixOutputs_lo_lo_126 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_81, decoder_decoded_andMatrixOutputs_lo_lo_lo_32) node decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, decoder_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, decoder_decoded_andMatrixOutputs_andMatrixInput_9_87) node decoder_decoded_andMatrixOutputs_lo_hi_136 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_87, decoder_decoded_andMatrixOutputs_lo_hi_lo_76) node decoder_decoded_andMatrixOutputs_lo_137 = cat(decoder_decoded_andMatrixOutputs_lo_hi_136, decoder_decoded_andMatrixOutputs_lo_lo_126) node decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, decoder_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, decoder_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoder_decoded_andMatrixOutputs_hi_lo_133 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_84, decoder_decoded_andMatrixOutputs_hi_lo_lo_64) node decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, decoder_decoded_andMatrixOutputs_andMatrixInput_3_137) node decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, decoder_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoder_decoded_andMatrixOutputs_hi_hi_137 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_107, decoder_decoded_andMatrixOutputs_hi_hi_lo_78) node decoder_decoded_andMatrixOutputs_hi_137 = cat(decoder_decoded_andMatrixOutputs_hi_hi_137, decoder_decoded_andMatrixOutputs_hi_lo_133) node _decoder_decoded_andMatrixOutputs_T_137 = cat(decoder_decoded_andMatrixOutputs_hi_137, decoder_decoded_andMatrixOutputs_lo_137) node decoder_decoded_andMatrixOutputs_142_2 = andr(_decoder_decoded_andMatrixOutputs_T_137) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_65, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33) node decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, decoder_decoded_andMatrixOutputs_andMatrixInput_13_77) node decoder_decoded_andMatrixOutputs_lo_lo_127 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_82, decoder_decoded_andMatrixOutputs_lo_lo_lo_33) node decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, decoder_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, decoder_decoded_andMatrixOutputs_andMatrixInput_9_88) node decoder_decoded_andMatrixOutputs_lo_hi_137 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_88, decoder_decoded_andMatrixOutputs_lo_hi_lo_77) node decoder_decoded_andMatrixOutputs_lo_138 = cat(decoder_decoded_andMatrixOutputs_lo_hi_137, decoder_decoded_andMatrixOutputs_lo_lo_127) node decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, decoder_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, decoder_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoder_decoded_andMatrixOutputs_hi_lo_134 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_85, decoder_decoded_andMatrixOutputs_hi_lo_lo_65) node decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, decoder_decoded_andMatrixOutputs_andMatrixInput_3_138) node decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, decoder_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoder_decoded_andMatrixOutputs_hi_hi_138 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_108, decoder_decoded_andMatrixOutputs_hi_hi_lo_79) node decoder_decoded_andMatrixOutputs_hi_138 = cat(decoder_decoded_andMatrixOutputs_hi_hi_138, decoder_decoded_andMatrixOutputs_hi_lo_134) node _decoder_decoded_andMatrixOutputs_T_138 = cat(decoder_decoded_andMatrixOutputs_hi_138, decoder_decoded_andMatrixOutputs_lo_138) node decoder_decoded_andMatrixOutputs_11_2 = andr(_decoder_decoded_andMatrixOutputs_T_138) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, decoder_decoded_andMatrixOutputs_andMatrixInput_14_66) node decoder_decoded_andMatrixOutputs_lo_lo_128 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_83, decoder_decoded_andMatrixOutputs_lo_lo_lo_34) node decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, decoder_decoded_andMatrixOutputs_andMatrixInput_12_80) node decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, decoder_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoder_decoded_andMatrixOutputs_lo_hi_138 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_89, decoder_decoded_andMatrixOutputs_lo_hi_lo_78) node decoder_decoded_andMatrixOutputs_lo_139 = cat(decoder_decoded_andMatrixOutputs_lo_hi_138, decoder_decoded_andMatrixOutputs_lo_lo_128) node decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, decoder_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, decoder_decoded_andMatrixOutputs_andMatrixInput_6_135) node decoder_decoded_andMatrixOutputs_hi_lo_135 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_86, decoder_decoded_andMatrixOutputs_hi_lo_lo_66) node decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, decoder_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, decoder_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoder_decoded_andMatrixOutputs_hi_hi_139 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_109, decoder_decoded_andMatrixOutputs_hi_hi_lo_80) node decoder_decoded_andMatrixOutputs_hi_139 = cat(decoder_decoded_andMatrixOutputs_hi_hi_139, decoder_decoded_andMatrixOutputs_hi_lo_135) node _decoder_decoded_andMatrixOutputs_T_139 = cat(decoder_decoded_andMatrixOutputs_hi_139, decoder_decoded_andMatrixOutputs_lo_139) node decoder_decoded_andMatrixOutputs_47_2 = andr(_decoder_decoded_andMatrixOutputs_T_139) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, decoder_decoded_andMatrixOutputs_andMatrixInput_14_67) node decoder_decoded_andMatrixOutputs_lo_lo_129 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_84, decoder_decoded_andMatrixOutputs_lo_lo_lo_35) node decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, decoder_decoded_andMatrixOutputs_andMatrixInput_12_81) node decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, decoder_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoder_decoded_andMatrixOutputs_lo_hi_139 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_90, decoder_decoded_andMatrixOutputs_lo_hi_lo_79) node decoder_decoded_andMatrixOutputs_lo_140 = cat(decoder_decoded_andMatrixOutputs_lo_hi_139, decoder_decoded_andMatrixOutputs_lo_lo_129) node decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, decoder_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, decoder_decoded_andMatrixOutputs_andMatrixInput_6_136) node decoder_decoded_andMatrixOutputs_hi_lo_136 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_87, decoder_decoded_andMatrixOutputs_hi_lo_lo_67) node decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, decoder_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, decoder_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoder_decoded_andMatrixOutputs_hi_hi_140 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_110, decoder_decoded_andMatrixOutputs_hi_hi_lo_81) node decoder_decoded_andMatrixOutputs_hi_140 = cat(decoder_decoded_andMatrixOutputs_hi_hi_140, decoder_decoded_andMatrixOutputs_hi_lo_136) node _decoder_decoded_andMatrixOutputs_T_140 = cat(decoder_decoded_andMatrixOutputs_hi_140, decoder_decoded_andMatrixOutputs_lo_140) node decoder_decoded_andMatrixOutputs_141_2 = andr(_decoder_decoded_andMatrixOutputs_T_140) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12) node decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, decoder_decoded_andMatrixOutputs_andMatrixInput_15_36) node decoder_decoded_andMatrixOutputs_lo_lo_130 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_85, decoder_decoded_andMatrixOutputs_lo_lo_lo_36) node decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, decoder_decoded_andMatrixOutputs_andMatrixInput_13_80) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, decoder_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoder_decoded_andMatrixOutputs_lo_hi_140 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_91, decoder_decoded_andMatrixOutputs_lo_hi_lo_80) node decoder_decoded_andMatrixOutputs_lo_141 = cat(decoder_decoded_andMatrixOutputs_lo_hi_140, decoder_decoded_andMatrixOutputs_lo_lo_130) node decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, decoder_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, decoder_decoded_andMatrixOutputs_andMatrixInput_6_137) node decoder_decoded_andMatrixOutputs_hi_lo_137 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_88, decoder_decoded_andMatrixOutputs_hi_lo_lo_68) node decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, decoder_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, decoder_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoder_decoded_andMatrixOutputs_hi_hi_141 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_111, decoder_decoded_andMatrixOutputs_hi_hi_lo_82) node decoder_decoded_andMatrixOutputs_hi_141 = cat(decoder_decoded_andMatrixOutputs_hi_hi_141, decoder_decoded_andMatrixOutputs_hi_lo_137) node _decoder_decoded_andMatrixOutputs_T_141 = cat(decoder_decoded_andMatrixOutputs_hi_141, decoder_decoded_andMatrixOutputs_lo_141) node decoder_decoded_andMatrixOutputs_114_2 = andr(_decoder_decoded_andMatrixOutputs_T_141) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, decoder_decoded_andMatrixOutputs_andMatrixInput_16_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, decoder_decoded_andMatrixOutputs_andMatrixInput_14_69) node decoder_decoded_andMatrixOutputs_lo_lo_131 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_86, decoder_decoded_andMatrixOutputs_lo_lo_lo_37) node decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, decoder_decoded_andMatrixOutputs_andMatrixInput_12_83) node decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, decoder_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoder_decoded_andMatrixOutputs_lo_hi_141 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_92, decoder_decoded_andMatrixOutputs_lo_hi_lo_81) node decoder_decoded_andMatrixOutputs_lo_142 = cat(decoder_decoded_andMatrixOutputs_lo_hi_141, decoder_decoded_andMatrixOutputs_lo_lo_131) node decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, decoder_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, decoder_decoded_andMatrixOutputs_andMatrixInput_6_138) node decoder_decoded_andMatrixOutputs_hi_lo_138 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_89, decoder_decoded_andMatrixOutputs_hi_lo_lo_69) node decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, decoder_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, decoder_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoder_decoded_andMatrixOutputs_hi_hi_142 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_112, decoder_decoded_andMatrixOutputs_hi_hi_lo_83) node decoder_decoded_andMatrixOutputs_hi_142 = cat(decoder_decoded_andMatrixOutputs_hi_hi_142, decoder_decoded_andMatrixOutputs_hi_lo_138) node _decoder_decoded_andMatrixOutputs_T_142 = cat(decoder_decoded_andMatrixOutputs_hi_142, decoder_decoded_andMatrixOutputs_lo_142) node decoder_decoded_andMatrixOutputs_69_2 = andr(_decoder_decoded_andMatrixOutputs_T_142) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_70, decoder_decoded_andMatrixOutputs_andMatrixInput_15_38) node decoder_decoded_andMatrixOutputs_lo_lo_132 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_87, decoder_decoded_andMatrixOutputs_lo_lo_lo_38) node decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, decoder_decoded_andMatrixOutputs_andMatrixInput_13_82) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, decoder_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoder_decoded_andMatrixOutputs_lo_hi_142 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_93, decoder_decoded_andMatrixOutputs_lo_hi_lo_82) node decoder_decoded_andMatrixOutputs_lo_143 = cat(decoder_decoded_andMatrixOutputs_lo_hi_142, decoder_decoded_andMatrixOutputs_lo_lo_132) node decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, decoder_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, decoder_decoded_andMatrixOutputs_andMatrixInput_6_139) node decoder_decoded_andMatrixOutputs_hi_lo_139 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_90, decoder_decoded_andMatrixOutputs_hi_lo_lo_70) node decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, decoder_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, decoder_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoder_decoded_andMatrixOutputs_hi_hi_143 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_113, decoder_decoded_andMatrixOutputs_hi_hi_lo_84) node decoder_decoded_andMatrixOutputs_hi_143 = cat(decoder_decoded_andMatrixOutputs_hi_hi_143, decoder_decoded_andMatrixOutputs_hi_lo_139) node _decoder_decoded_andMatrixOutputs_T_143 = cat(decoder_decoded_andMatrixOutputs_hi_143, decoder_decoded_andMatrixOutputs_lo_143) node decoder_decoded_andMatrixOutputs_71_2 = andr(_decoder_decoded_andMatrixOutputs_T_143) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, decoder_decoded_andMatrixOutputs_andMatrixInput_16_21) node decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, decoder_decoded_andMatrixOutputs_andMatrixInput_14_71) node decoder_decoded_andMatrixOutputs_lo_lo_133 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_88, decoder_decoded_andMatrixOutputs_lo_lo_lo_39) node decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, decoder_decoded_andMatrixOutputs_andMatrixInput_12_85) node decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, decoder_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoder_decoded_andMatrixOutputs_lo_hi_143 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_94, decoder_decoded_andMatrixOutputs_lo_hi_lo_83) node decoder_decoded_andMatrixOutputs_lo_144 = cat(decoder_decoded_andMatrixOutputs_lo_hi_143, decoder_decoded_andMatrixOutputs_lo_lo_133) node decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, decoder_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, decoder_decoded_andMatrixOutputs_andMatrixInput_6_140) node decoder_decoded_andMatrixOutputs_hi_lo_140 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_91, decoder_decoded_andMatrixOutputs_hi_lo_lo_71) node decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, decoder_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, decoder_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoder_decoded_andMatrixOutputs_hi_hi_144 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_114, decoder_decoded_andMatrixOutputs_hi_hi_lo_85) node decoder_decoded_andMatrixOutputs_hi_144 = cat(decoder_decoded_andMatrixOutputs_hi_hi_144, decoder_decoded_andMatrixOutputs_hi_lo_140) node _decoder_decoded_andMatrixOutputs_T_144 = cat(decoder_decoded_andMatrixOutputs_hi_144, decoder_decoded_andMatrixOutputs_lo_144) node decoder_decoded_andMatrixOutputs_175_2 = andr(_decoder_decoded_andMatrixOutputs_T_144) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_72, decoder_decoded_andMatrixOutputs_andMatrixInput_15_40) node decoder_decoded_andMatrixOutputs_lo_lo_134 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_89, decoder_decoded_andMatrixOutputs_lo_lo_lo_40) node decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, decoder_decoded_andMatrixOutputs_andMatrixInput_13_84) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, decoder_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoder_decoded_andMatrixOutputs_lo_hi_144 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_95, decoder_decoded_andMatrixOutputs_lo_hi_lo_84) node decoder_decoded_andMatrixOutputs_lo_145 = cat(decoder_decoded_andMatrixOutputs_lo_hi_144, decoder_decoded_andMatrixOutputs_lo_lo_134) node decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, decoder_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, decoder_decoded_andMatrixOutputs_andMatrixInput_6_141) node decoder_decoded_andMatrixOutputs_hi_lo_141 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_92, decoder_decoded_andMatrixOutputs_hi_lo_lo_72) node decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, decoder_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, decoder_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoder_decoded_andMatrixOutputs_hi_hi_145 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_115, decoder_decoded_andMatrixOutputs_hi_hi_lo_86) node decoder_decoded_andMatrixOutputs_hi_145 = cat(decoder_decoded_andMatrixOutputs_hi_hi_145, decoder_decoded_andMatrixOutputs_hi_lo_141) node _decoder_decoded_andMatrixOutputs_T_145 = cat(decoder_decoded_andMatrixOutputs_hi_145, decoder_decoded_andMatrixOutputs_lo_145) node decoder_decoded_andMatrixOutputs_80_2 = andr(_decoder_decoded_andMatrixOutputs_T_145) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(decoder_decoded_plaInput, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, decoder_decoded_andMatrixOutputs_andMatrixInput_16_23) node decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, decoder_decoded_andMatrixOutputs_andMatrixInput_14_73) node decoder_decoded_andMatrixOutputs_lo_lo_135 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_90, decoder_decoded_andMatrixOutputs_lo_lo_lo_41) node decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, decoder_decoded_andMatrixOutputs_andMatrixInput_12_87) node decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, decoder_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoder_decoded_andMatrixOutputs_lo_hi_145 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_96, decoder_decoded_andMatrixOutputs_lo_hi_lo_85) node decoder_decoded_andMatrixOutputs_lo_146 = cat(decoder_decoded_andMatrixOutputs_lo_hi_145, decoder_decoded_andMatrixOutputs_lo_lo_135) node decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, decoder_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, decoder_decoded_andMatrixOutputs_andMatrixInput_6_142) node decoder_decoded_andMatrixOutputs_hi_lo_142 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_93, decoder_decoded_andMatrixOutputs_hi_lo_lo_73) node decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, decoder_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, decoder_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoder_decoded_andMatrixOutputs_hi_hi_146 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_116, decoder_decoded_andMatrixOutputs_hi_hi_lo_87) node decoder_decoded_andMatrixOutputs_hi_146 = cat(decoder_decoded_andMatrixOutputs_hi_hi_146, decoder_decoded_andMatrixOutputs_hi_lo_142) node _decoder_decoded_andMatrixOutputs_T_146 = cat(decoder_decoded_andMatrixOutputs_hi_146, decoder_decoded_andMatrixOutputs_lo_146) node decoder_decoded_andMatrixOutputs_130_2 = andr(_decoder_decoded_andMatrixOutputs_T_146) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(decoder_decoded_plaInput, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, decoder_decoded_andMatrixOutputs_andMatrixInput_15_42) node decoder_decoded_andMatrixOutputs_lo_lo_136 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_91, decoder_decoded_andMatrixOutputs_lo_lo_lo_42) node decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, decoder_decoded_andMatrixOutputs_andMatrixInput_13_86) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, decoder_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoder_decoded_andMatrixOutputs_lo_hi_146 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_97, decoder_decoded_andMatrixOutputs_lo_hi_lo_86) node decoder_decoded_andMatrixOutputs_lo_147 = cat(decoder_decoded_andMatrixOutputs_lo_hi_146, decoder_decoded_andMatrixOutputs_lo_lo_136) node decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, decoder_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, decoder_decoded_andMatrixOutputs_andMatrixInput_6_143) node decoder_decoded_andMatrixOutputs_hi_lo_143 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_94, decoder_decoded_andMatrixOutputs_hi_lo_lo_74) node decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, decoder_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, decoder_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoder_decoded_andMatrixOutputs_hi_hi_147 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_117, decoder_decoded_andMatrixOutputs_hi_hi_lo_88) node decoder_decoded_andMatrixOutputs_hi_147 = cat(decoder_decoded_andMatrixOutputs_hi_hi_147, decoder_decoded_andMatrixOutputs_hi_lo_143) node _decoder_decoded_andMatrixOutputs_T_147 = cat(decoder_decoded_andMatrixOutputs_hi_147, decoder_decoded_andMatrixOutputs_lo_147) node decoder_decoded_andMatrixOutputs_157_2 = andr(_decoder_decoded_andMatrixOutputs_T_147) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, decoder_decoded_andMatrixOutputs_andMatrixInput_13_87) node decoder_decoded_andMatrixOutputs_lo_lo_137 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_92, decoder_decoded_andMatrixOutputs_andMatrixInput_14_75) node decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, decoder_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, decoder_decoded_andMatrixOutputs_andMatrixInput_9_98) node decoder_decoded_andMatrixOutputs_lo_hi_147 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_98, decoder_decoded_andMatrixOutputs_lo_hi_lo_87) node decoder_decoded_andMatrixOutputs_lo_148 = cat(decoder_decoded_andMatrixOutputs_lo_hi_147, decoder_decoded_andMatrixOutputs_lo_lo_137) node decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, decoder_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, decoder_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoder_decoded_andMatrixOutputs_hi_lo_144 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_95, decoder_decoded_andMatrixOutputs_hi_lo_lo_75) node decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, decoder_decoded_andMatrixOutputs_andMatrixInput_3_148) node decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, decoder_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoder_decoded_andMatrixOutputs_hi_hi_148 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_118, decoder_decoded_andMatrixOutputs_hi_hi_lo_89) node decoder_decoded_andMatrixOutputs_hi_148 = cat(decoder_decoded_andMatrixOutputs_hi_hi_148, decoder_decoded_andMatrixOutputs_hi_lo_144) node _decoder_decoded_andMatrixOutputs_T_148 = cat(decoder_decoded_andMatrixOutputs_hi_148, decoder_decoded_andMatrixOutputs_lo_148) node decoder_decoded_andMatrixOutputs_67_2 = andr(_decoder_decoded_andMatrixOutputs_T_148) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, decoder_decoded_andMatrixOutputs_andMatrixInput_13_88) node decoder_decoded_andMatrixOutputs_lo_lo_138 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_93, decoder_decoded_andMatrixOutputs_andMatrixInput_14_76) node decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, decoder_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, decoder_decoded_andMatrixOutputs_andMatrixInput_9_99) node decoder_decoded_andMatrixOutputs_lo_hi_148 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_99, decoder_decoded_andMatrixOutputs_lo_hi_lo_88) node decoder_decoded_andMatrixOutputs_lo_149 = cat(decoder_decoded_andMatrixOutputs_lo_hi_148, decoder_decoded_andMatrixOutputs_lo_lo_138) node decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, decoder_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, decoder_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoder_decoded_andMatrixOutputs_hi_lo_145 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_96, decoder_decoded_andMatrixOutputs_hi_lo_lo_76) node decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, decoder_decoded_andMatrixOutputs_andMatrixInput_3_149) node decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, decoder_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoder_decoded_andMatrixOutputs_hi_hi_149 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_119, decoder_decoded_andMatrixOutputs_hi_hi_lo_90) node decoder_decoded_andMatrixOutputs_hi_149 = cat(decoder_decoded_andMatrixOutputs_hi_hi_149, decoder_decoded_andMatrixOutputs_hi_lo_145) node _decoder_decoded_andMatrixOutputs_T_149 = cat(decoder_decoded_andMatrixOutputs_hi_149, decoder_decoded_andMatrixOutputs_lo_149) node decoder_decoded_andMatrixOutputs_42_2 = andr(_decoder_decoded_andMatrixOutputs_T_149) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, decoder_decoded_andMatrixOutputs_andMatrixInput_15_43) node decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, decoder_decoded_andMatrixOutputs_andMatrixInput_13_89) node decoder_decoded_andMatrixOutputs_lo_lo_139 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_94, decoder_decoded_andMatrixOutputs_lo_lo_lo_43) node decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, decoder_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, decoder_decoded_andMatrixOutputs_andMatrixInput_9_100) node decoder_decoded_andMatrixOutputs_lo_hi_149 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_100, decoder_decoded_andMatrixOutputs_lo_hi_lo_89) node decoder_decoded_andMatrixOutputs_lo_150 = cat(decoder_decoded_andMatrixOutputs_lo_hi_149, decoder_decoded_andMatrixOutputs_lo_lo_139) node decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, decoder_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, decoder_decoded_andMatrixOutputs_andMatrixInput_5_149) node decoder_decoded_andMatrixOutputs_hi_lo_146 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_97, decoder_decoded_andMatrixOutputs_hi_lo_lo_77) node decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, decoder_decoded_andMatrixOutputs_andMatrixInput_3_150) node decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, decoder_decoded_andMatrixOutputs_andMatrixInput_1_150) node decoder_decoded_andMatrixOutputs_hi_hi_150 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_120, decoder_decoded_andMatrixOutputs_hi_hi_lo_91) node decoder_decoded_andMatrixOutputs_hi_150 = cat(decoder_decoded_andMatrixOutputs_hi_hi_150, decoder_decoded_andMatrixOutputs_hi_lo_146) node _decoder_decoded_andMatrixOutputs_T_150 = cat(decoder_decoded_andMatrixOutputs_hi_150, decoder_decoded_andMatrixOutputs_lo_150) node decoder_decoded_andMatrixOutputs_53_2 = andr(_decoder_decoded_andMatrixOutputs_T_150) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, decoder_decoded_andMatrixOutputs_andMatrixInput_15_44) node decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, decoder_decoded_andMatrixOutputs_andMatrixInput_13_90) node decoder_decoded_andMatrixOutputs_lo_lo_140 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_95, decoder_decoded_andMatrixOutputs_lo_lo_lo_44) node decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, decoder_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, decoder_decoded_andMatrixOutputs_andMatrixInput_9_101) node decoder_decoded_andMatrixOutputs_lo_hi_150 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_101, decoder_decoded_andMatrixOutputs_lo_hi_lo_90) node decoder_decoded_andMatrixOutputs_lo_151 = cat(decoder_decoded_andMatrixOutputs_lo_hi_150, decoder_decoded_andMatrixOutputs_lo_lo_140) node decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, decoder_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, decoder_decoded_andMatrixOutputs_andMatrixInput_5_150) node decoder_decoded_andMatrixOutputs_hi_lo_147 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_98, decoder_decoded_andMatrixOutputs_hi_lo_lo_78) node decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, decoder_decoded_andMatrixOutputs_andMatrixInput_3_151) node decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, decoder_decoded_andMatrixOutputs_andMatrixInput_1_151) node decoder_decoded_andMatrixOutputs_hi_hi_151 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_121, decoder_decoded_andMatrixOutputs_hi_hi_lo_92) node decoder_decoded_andMatrixOutputs_hi_151 = cat(decoder_decoded_andMatrixOutputs_hi_hi_151, decoder_decoded_andMatrixOutputs_hi_lo_147) node _decoder_decoded_andMatrixOutputs_T_151 = cat(decoder_decoded_andMatrixOutputs_hi_151, decoder_decoded_andMatrixOutputs_lo_151) node decoder_decoded_andMatrixOutputs_62_2 = andr(_decoder_decoded_andMatrixOutputs_T_151) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_79, decoder_decoded_andMatrixOutputs_andMatrixInput_15_45) node decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, decoder_decoded_andMatrixOutputs_andMatrixInput_13_91) node decoder_decoded_andMatrixOutputs_lo_lo_141 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_96, decoder_decoded_andMatrixOutputs_lo_lo_lo_45) node decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, decoder_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, decoder_decoded_andMatrixOutputs_andMatrixInput_9_102) node decoder_decoded_andMatrixOutputs_lo_hi_151 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_102, decoder_decoded_andMatrixOutputs_lo_hi_lo_91) node decoder_decoded_andMatrixOutputs_lo_152 = cat(decoder_decoded_andMatrixOutputs_lo_hi_151, decoder_decoded_andMatrixOutputs_lo_lo_141) node decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, decoder_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, decoder_decoded_andMatrixOutputs_andMatrixInput_5_151) node decoder_decoded_andMatrixOutputs_hi_lo_148 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_99, decoder_decoded_andMatrixOutputs_hi_lo_lo_79) node decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, decoder_decoded_andMatrixOutputs_andMatrixInput_3_152) node decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, decoder_decoded_andMatrixOutputs_andMatrixInput_1_152) node decoder_decoded_andMatrixOutputs_hi_hi_152 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_122, decoder_decoded_andMatrixOutputs_hi_hi_lo_93) node decoder_decoded_andMatrixOutputs_hi_152 = cat(decoder_decoded_andMatrixOutputs_hi_hi_152, decoder_decoded_andMatrixOutputs_hi_lo_148) node _decoder_decoded_andMatrixOutputs_T_152 = cat(decoder_decoded_andMatrixOutputs_hi_152, decoder_decoded_andMatrixOutputs_lo_152) node decoder_decoded_andMatrixOutputs_68_2 = andr(_decoder_decoded_andMatrixOutputs_T_152) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, decoder_decoded_andMatrixOutputs_andMatrixInput_16_25) node decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, decoder_decoded_andMatrixOutputs_andMatrixInput_14_80) node decoder_decoded_andMatrixOutputs_lo_lo_142 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_97, decoder_decoded_andMatrixOutputs_lo_lo_lo_46) node decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, decoder_decoded_andMatrixOutputs_andMatrixInput_12_94) node decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, decoder_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoder_decoded_andMatrixOutputs_lo_hi_152 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_103, decoder_decoded_andMatrixOutputs_lo_hi_lo_92) node decoder_decoded_andMatrixOutputs_lo_153 = cat(decoder_decoded_andMatrixOutputs_lo_hi_152, decoder_decoded_andMatrixOutputs_lo_lo_142) node decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, decoder_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, decoder_decoded_andMatrixOutputs_andMatrixInput_6_149) node decoder_decoded_andMatrixOutputs_hi_lo_149 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_100, decoder_decoded_andMatrixOutputs_hi_lo_lo_80) node decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, decoder_decoded_andMatrixOutputs_andMatrixInput_4_153) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, decoder_decoded_andMatrixOutputs_andMatrixInput_1_153) node decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_153) node decoder_decoded_andMatrixOutputs_hi_hi_153 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_123, decoder_decoded_andMatrixOutputs_hi_hi_lo_94) node decoder_decoded_andMatrixOutputs_hi_153 = cat(decoder_decoded_andMatrixOutputs_hi_hi_153, decoder_decoded_andMatrixOutputs_hi_lo_149) node _decoder_decoded_andMatrixOutputs_T_153 = cat(decoder_decoded_andMatrixOutputs_hi_153, decoder_decoded_andMatrixOutputs_lo_153) node decoder_decoded_andMatrixOutputs_183_2 = andr(_decoder_decoded_andMatrixOutputs_T_153) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, decoder_decoded_andMatrixOutputs_andMatrixInput_15_47) node decoder_decoded_andMatrixOutputs_lo_lo_143 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_98, decoder_decoded_andMatrixOutputs_lo_lo_lo_47) node decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, decoder_decoded_andMatrixOutputs_andMatrixInput_13_93) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, decoder_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoder_decoded_andMatrixOutputs_lo_hi_153 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_104, decoder_decoded_andMatrixOutputs_lo_hi_lo_93) node decoder_decoded_andMatrixOutputs_lo_154 = cat(decoder_decoded_andMatrixOutputs_lo_hi_153, decoder_decoded_andMatrixOutputs_lo_lo_143) node decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, decoder_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, decoder_decoded_andMatrixOutputs_andMatrixInput_6_150) node decoder_decoded_andMatrixOutputs_hi_lo_150 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_101, decoder_decoded_andMatrixOutputs_hi_lo_lo_81) node decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, decoder_decoded_andMatrixOutputs_andMatrixInput_4_154) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, decoder_decoded_andMatrixOutputs_andMatrixInput_1_154) node decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_154) node decoder_decoded_andMatrixOutputs_hi_hi_154 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_124, decoder_decoded_andMatrixOutputs_hi_hi_lo_95) node decoder_decoded_andMatrixOutputs_hi_154 = cat(decoder_decoded_andMatrixOutputs_hi_hi_154, decoder_decoded_andMatrixOutputs_hi_lo_150) node _decoder_decoded_andMatrixOutputs_T_154 = cat(decoder_decoded_andMatrixOutputs_hi_154, decoder_decoded_andMatrixOutputs_lo_154) node decoder_decoded_andMatrixOutputs_50_2 = andr(_decoder_decoded_andMatrixOutputs_T_154) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, decoder_decoded_andMatrixOutputs_andMatrixInput_15_48) node decoder_decoded_andMatrixOutputs_lo_lo_144 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_99, decoder_decoded_andMatrixOutputs_lo_lo_lo_48) node decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, decoder_decoded_andMatrixOutputs_andMatrixInput_13_94) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, decoder_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoder_decoded_andMatrixOutputs_lo_hi_154 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_105, decoder_decoded_andMatrixOutputs_lo_hi_lo_94) node decoder_decoded_andMatrixOutputs_lo_155 = cat(decoder_decoded_andMatrixOutputs_lo_hi_154, decoder_decoded_andMatrixOutputs_lo_lo_144) node decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, decoder_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, decoder_decoded_andMatrixOutputs_andMatrixInput_6_151) node decoder_decoded_andMatrixOutputs_hi_lo_151 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_102, decoder_decoded_andMatrixOutputs_hi_lo_lo_82) node decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, decoder_decoded_andMatrixOutputs_andMatrixInput_4_155) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, decoder_decoded_andMatrixOutputs_andMatrixInput_1_155) node decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_155) node decoder_decoded_andMatrixOutputs_hi_hi_155 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_125, decoder_decoded_andMatrixOutputs_hi_hi_lo_96) node decoder_decoded_andMatrixOutputs_hi_155 = cat(decoder_decoded_andMatrixOutputs_hi_hi_155, decoder_decoded_andMatrixOutputs_hi_lo_151) node _decoder_decoded_andMatrixOutputs_T_155 = cat(decoder_decoded_andMatrixOutputs_hi_155, decoder_decoded_andMatrixOutputs_lo_155) node decoder_decoded_andMatrixOutputs_136_2 = andr(_decoder_decoded_andMatrixOutputs_T_155) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11) node decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, decoder_decoded_andMatrixOutputs_andMatrixInput_16_28) node decoder_decoded_andMatrixOutputs_lo_lo_145 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_100, decoder_decoded_andMatrixOutputs_lo_lo_lo_49) node decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, decoder_decoded_andMatrixOutputs_andMatrixInput_14_83) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, decoder_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_12_97) node decoder_decoded_andMatrixOutputs_lo_hi_155 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_106, decoder_decoded_andMatrixOutputs_lo_hi_lo_95) node decoder_decoded_andMatrixOutputs_lo_156 = cat(decoder_decoded_andMatrixOutputs_lo_hi_155, decoder_decoded_andMatrixOutputs_lo_lo_145) node decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, decoder_decoded_andMatrixOutputs_andMatrixInput_9_106) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, decoder_decoded_andMatrixOutputs_andMatrixInput_6_152) node decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoder_decoded_andMatrixOutputs_hi_lo_152 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_103, decoder_decoded_andMatrixOutputs_hi_lo_lo_83) node decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, decoder_decoded_andMatrixOutputs_andMatrixInput_4_156) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, decoder_decoded_andMatrixOutputs_andMatrixInput_1_156) node decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_2_156) node decoder_decoded_andMatrixOutputs_hi_hi_156 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_126, decoder_decoded_andMatrixOutputs_hi_hi_lo_97) node decoder_decoded_andMatrixOutputs_hi_156 = cat(decoder_decoded_andMatrixOutputs_hi_hi_156, decoder_decoded_andMatrixOutputs_hi_lo_152) node _decoder_decoded_andMatrixOutputs_T_156 = cat(decoder_decoded_andMatrixOutputs_hi_156, decoder_decoded_andMatrixOutputs_lo_156) node decoder_decoded_andMatrixOutputs_127_2 = andr(_decoder_decoded_andMatrixOutputs_T_156) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, decoder_decoded_andMatrixOutputs_andMatrixInput_16_29) node decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, decoder_decoded_andMatrixOutputs_andMatrixInput_14_84) node decoder_decoded_andMatrixOutputs_lo_lo_146 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_101, decoder_decoded_andMatrixOutputs_lo_lo_lo_50) node decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, decoder_decoded_andMatrixOutputs_andMatrixInput_12_98) node decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, decoder_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoder_decoded_andMatrixOutputs_lo_hi_156 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_107, decoder_decoded_andMatrixOutputs_lo_hi_lo_96) node decoder_decoded_andMatrixOutputs_lo_157 = cat(decoder_decoded_andMatrixOutputs_lo_hi_156, decoder_decoded_andMatrixOutputs_lo_lo_146) node decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, decoder_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, decoder_decoded_andMatrixOutputs_andMatrixInput_6_153) node decoder_decoded_andMatrixOutputs_hi_lo_153 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_104, decoder_decoded_andMatrixOutputs_hi_lo_lo_84) node decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, decoder_decoded_andMatrixOutputs_andMatrixInput_4_157) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, decoder_decoded_andMatrixOutputs_andMatrixInput_1_157) node decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_2_157) node decoder_decoded_andMatrixOutputs_hi_hi_157 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_127, decoder_decoded_andMatrixOutputs_hi_hi_lo_98) node decoder_decoded_andMatrixOutputs_hi_157 = cat(decoder_decoded_andMatrixOutputs_hi_hi_157, decoder_decoded_andMatrixOutputs_hi_lo_153) node _decoder_decoded_andMatrixOutputs_T_157 = cat(decoder_decoded_andMatrixOutputs_hi_157, decoder_decoded_andMatrixOutputs_lo_157) node decoder_decoded_andMatrixOutputs_151_2 = andr(_decoder_decoded_andMatrixOutputs_T_157) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, decoder_decoded_andMatrixOutputs_andMatrixInput_16_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, decoder_decoded_andMatrixOutputs_andMatrixInput_14_85) node decoder_decoded_andMatrixOutputs_lo_lo_147 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_102, decoder_decoded_andMatrixOutputs_lo_lo_lo_51) node decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, decoder_decoded_andMatrixOutputs_andMatrixInput_12_99) node decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, decoder_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoder_decoded_andMatrixOutputs_lo_hi_157 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_108, decoder_decoded_andMatrixOutputs_lo_hi_lo_97) node decoder_decoded_andMatrixOutputs_lo_158 = cat(decoder_decoded_andMatrixOutputs_lo_hi_157, decoder_decoded_andMatrixOutputs_lo_lo_147) node decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, decoder_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, decoder_decoded_andMatrixOutputs_andMatrixInput_6_154) node decoder_decoded_andMatrixOutputs_hi_lo_154 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_105, decoder_decoded_andMatrixOutputs_hi_lo_lo_85) node decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, decoder_decoded_andMatrixOutputs_andMatrixInput_4_158) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, decoder_decoded_andMatrixOutputs_andMatrixInput_1_158) node decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_2_158) node decoder_decoded_andMatrixOutputs_hi_hi_158 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_128, decoder_decoded_andMatrixOutputs_hi_hi_lo_99) node decoder_decoded_andMatrixOutputs_hi_158 = cat(decoder_decoded_andMatrixOutputs_hi_hi_158, decoder_decoded_andMatrixOutputs_hi_lo_154) node _decoder_decoded_andMatrixOutputs_T_158 = cat(decoder_decoded_andMatrixOutputs_hi_158, decoder_decoded_andMatrixOutputs_lo_158) node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_158) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, decoder_decoded_andMatrixOutputs_andMatrixInput_16_31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, decoder_decoded_andMatrixOutputs_andMatrixInput_14_86) node decoder_decoded_andMatrixOutputs_lo_lo_148 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_103, decoder_decoded_andMatrixOutputs_lo_lo_lo_52) node decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, decoder_decoded_andMatrixOutputs_andMatrixInput_12_100) node decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, decoder_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoder_decoded_andMatrixOutputs_lo_hi_158 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_109, decoder_decoded_andMatrixOutputs_lo_hi_lo_98) node decoder_decoded_andMatrixOutputs_lo_159 = cat(decoder_decoded_andMatrixOutputs_lo_hi_158, decoder_decoded_andMatrixOutputs_lo_lo_148) node decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, decoder_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, decoder_decoded_andMatrixOutputs_andMatrixInput_6_155) node decoder_decoded_andMatrixOutputs_hi_lo_155 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_106, decoder_decoded_andMatrixOutputs_hi_lo_lo_86) node decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, decoder_decoded_andMatrixOutputs_andMatrixInput_4_159) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, decoder_decoded_andMatrixOutputs_andMatrixInput_1_159) node decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_2_159) node decoder_decoded_andMatrixOutputs_hi_hi_159 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_129, decoder_decoded_andMatrixOutputs_hi_hi_lo_100) node decoder_decoded_andMatrixOutputs_hi_159 = cat(decoder_decoded_andMatrixOutputs_hi_hi_159, decoder_decoded_andMatrixOutputs_hi_lo_155) node _decoder_decoded_andMatrixOutputs_T_159 = cat(decoder_decoded_andMatrixOutputs_hi_159, decoder_decoded_andMatrixOutputs_lo_159) node decoder_decoded_andMatrixOutputs_99_2 = andr(_decoder_decoded_andMatrixOutputs_T_159) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, decoder_decoded_andMatrixOutputs_andMatrixInput_19_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, decoder_decoded_andMatrixOutputs_andMatrixInput_16_32) node decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19) node decoder_decoded_andMatrixOutputs_lo_lo_149 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_104, decoder_decoded_andMatrixOutputs_lo_lo_lo_53) node decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, decoder_decoded_andMatrixOutputs_andMatrixInput_14_87) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, decoder_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_12_101) node decoder_decoded_andMatrixOutputs_lo_hi_159 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_110, decoder_decoded_andMatrixOutputs_lo_hi_lo_99) node decoder_decoded_andMatrixOutputs_lo_160 = cat(decoder_decoded_andMatrixOutputs_lo_hi_159, decoder_decoded_andMatrixOutputs_lo_lo_149) node decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, decoder_decoded_andMatrixOutputs_andMatrixInput_9_110) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, decoder_decoded_andMatrixOutputs_andMatrixInput_6_156) node decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_7_149) node decoder_decoded_andMatrixOutputs_hi_lo_156 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_107, decoder_decoded_andMatrixOutputs_hi_lo_lo_87) node decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, decoder_decoded_andMatrixOutputs_andMatrixInput_4_160) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, decoder_decoded_andMatrixOutputs_andMatrixInput_1_160) node decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_2_160) node decoder_decoded_andMatrixOutputs_hi_hi_160 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_130, decoder_decoded_andMatrixOutputs_hi_hi_lo_101) node decoder_decoded_andMatrixOutputs_hi_160 = cat(decoder_decoded_andMatrixOutputs_hi_hi_160, decoder_decoded_andMatrixOutputs_hi_lo_156) node _decoder_decoded_andMatrixOutputs_T_160 = cat(decoder_decoded_andMatrixOutputs_hi_160, decoder_decoded_andMatrixOutputs_lo_160) node decoder_decoded_andMatrixOutputs_104_2 = andr(_decoder_decoded_andMatrixOutputs_T_160) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, decoder_decoded_andMatrixOutputs_andMatrixInput_19_11) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_54, decoder_decoded_andMatrixOutputs_andMatrixInput_16_33) node decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20) node decoder_decoded_andMatrixOutputs_lo_lo_150 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_105, decoder_decoded_andMatrixOutputs_lo_lo_lo_54) node decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, decoder_decoded_andMatrixOutputs_andMatrixInput_14_88) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, decoder_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_12_102) node decoder_decoded_andMatrixOutputs_lo_hi_160 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_111, decoder_decoded_andMatrixOutputs_lo_hi_lo_100) node decoder_decoded_andMatrixOutputs_lo_161 = cat(decoder_decoded_andMatrixOutputs_lo_hi_160, decoder_decoded_andMatrixOutputs_lo_lo_150) node decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, decoder_decoded_andMatrixOutputs_andMatrixInput_9_111) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, decoder_decoded_andMatrixOutputs_andMatrixInput_6_157) node decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_7_150) node decoder_decoded_andMatrixOutputs_hi_lo_157 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_108, decoder_decoded_andMatrixOutputs_hi_lo_lo_88) node decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, decoder_decoded_andMatrixOutputs_andMatrixInput_4_161) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, decoder_decoded_andMatrixOutputs_andMatrixInput_1_161) node decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_2_161) node decoder_decoded_andMatrixOutputs_hi_hi_161 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_131, decoder_decoded_andMatrixOutputs_hi_hi_lo_102) node decoder_decoded_andMatrixOutputs_hi_161 = cat(decoder_decoded_andMatrixOutputs_hi_hi_161, decoder_decoded_andMatrixOutputs_hi_lo_157) node _decoder_decoded_andMatrixOutputs_T_161 = cat(decoder_decoded_andMatrixOutputs_hi_161, decoder_decoded_andMatrixOutputs_lo_161) node decoder_decoded_andMatrixOutputs_186_2 = andr(_decoder_decoded_andMatrixOutputs_T_161) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, decoder_decoded_andMatrixOutputs_andMatrixInput_20_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, decoder_decoded_andMatrixOutputs_andMatrixInput_17_21) node decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14) node decoder_decoded_andMatrixOutputs_lo_lo_151 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_106, decoder_decoded_andMatrixOutputs_lo_lo_lo_55) node decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, decoder_decoded_andMatrixOutputs_andMatrixInput_15_55) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, decoder_decoded_andMatrixOutputs_andMatrixInput_12_103) node decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_101) node decoder_decoded_andMatrixOutputs_lo_hi_161 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_112, decoder_decoded_andMatrixOutputs_lo_hi_lo_101) node decoder_decoded_andMatrixOutputs_lo_162 = cat(decoder_decoded_andMatrixOutputs_lo_hi_161, decoder_decoded_andMatrixOutputs_lo_lo_151) node decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, decoder_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, decoder_decoded_andMatrixOutputs_andMatrixInput_7_151) node decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoder_decoded_andMatrixOutputs_hi_lo_158 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_109, decoder_decoded_andMatrixOutputs_hi_lo_lo_89) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, decoder_decoded_andMatrixOutputs_andMatrixInput_4_162) node decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_161) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, decoder_decoded_andMatrixOutputs_andMatrixInput_1_162) node decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_2_162) node decoder_decoded_andMatrixOutputs_hi_hi_162 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_132, decoder_decoded_andMatrixOutputs_hi_hi_lo_103) node decoder_decoded_andMatrixOutputs_hi_162 = cat(decoder_decoded_andMatrixOutputs_hi_hi_162, decoder_decoded_andMatrixOutputs_hi_lo_158) node _decoder_decoded_andMatrixOutputs_T_162 = cat(decoder_decoded_andMatrixOutputs_hi_162, decoder_decoded_andMatrixOutputs_lo_162) node decoder_decoded_andMatrixOutputs_18_2 = andr(_decoder_decoded_andMatrixOutputs_T_162) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, decoder_decoded_andMatrixOutputs_andMatrixInput_19_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_56, decoder_decoded_andMatrixOutputs_andMatrixInput_16_35) node decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_22) node decoder_decoded_andMatrixOutputs_lo_lo_152 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_107, decoder_decoded_andMatrixOutputs_lo_lo_lo_56) node decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, decoder_decoded_andMatrixOutputs_andMatrixInput_14_90) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, decoder_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_12_104) node decoder_decoded_andMatrixOutputs_lo_hi_162 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_113, decoder_decoded_andMatrixOutputs_lo_hi_lo_102) node decoder_decoded_andMatrixOutputs_lo_163 = cat(decoder_decoded_andMatrixOutputs_lo_hi_162, decoder_decoded_andMatrixOutputs_lo_lo_152) node decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, decoder_decoded_andMatrixOutputs_andMatrixInput_9_113) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, decoder_decoded_andMatrixOutputs_andMatrixInput_6_159) node decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_7_152) node decoder_decoded_andMatrixOutputs_hi_lo_159 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_110, decoder_decoded_andMatrixOutputs_hi_lo_lo_90) node decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, decoder_decoded_andMatrixOutputs_andMatrixInput_4_163) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, decoder_decoded_andMatrixOutputs_andMatrixInput_1_163) node decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_2_163) node decoder_decoded_andMatrixOutputs_hi_hi_163 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_133, decoder_decoded_andMatrixOutputs_hi_hi_lo_104) node decoder_decoded_andMatrixOutputs_hi_163 = cat(decoder_decoded_andMatrixOutputs_hi_hi_163, decoder_decoded_andMatrixOutputs_hi_lo_159) node _decoder_decoded_andMatrixOutputs_T_163 = cat(decoder_decoded_andMatrixOutputs_hi_163, decoder_decoded_andMatrixOutputs_lo_163) node decoder_decoded_andMatrixOutputs_106_2 = andr(_decoder_decoded_andMatrixOutputs_T_163) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, decoder_decoded_andMatrixOutputs_andMatrixInput_13_103) node decoder_decoded_andMatrixOutputs_lo_lo_153 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_108, decoder_decoded_andMatrixOutputs_andMatrixInput_14_91) node decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, decoder_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, decoder_decoded_andMatrixOutputs_andMatrixInput_9_114) node decoder_decoded_andMatrixOutputs_lo_hi_163 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_114, decoder_decoded_andMatrixOutputs_lo_hi_lo_103) node decoder_decoded_andMatrixOutputs_lo_164 = cat(decoder_decoded_andMatrixOutputs_lo_hi_163, decoder_decoded_andMatrixOutputs_lo_lo_153) node decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, decoder_decoded_andMatrixOutputs_andMatrixInput_7_153) node decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, decoder_decoded_andMatrixOutputs_andMatrixInput_5_163) node decoder_decoded_andMatrixOutputs_hi_lo_160 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_111, decoder_decoded_andMatrixOutputs_hi_lo_lo_91) node decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, decoder_decoded_andMatrixOutputs_andMatrixInput_3_164) node decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, decoder_decoded_andMatrixOutputs_andMatrixInput_1_164) node decoder_decoded_andMatrixOutputs_hi_hi_164 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_134, decoder_decoded_andMatrixOutputs_hi_hi_lo_105) node decoder_decoded_andMatrixOutputs_hi_164 = cat(decoder_decoded_andMatrixOutputs_hi_hi_164, decoder_decoded_andMatrixOutputs_hi_lo_160) node _decoder_decoded_andMatrixOutputs_T_164 = cat(decoder_decoded_andMatrixOutputs_hi_164, decoder_decoded_andMatrixOutputs_lo_164) node decoder_decoded_andMatrixOutputs_88_2 = andr(_decoder_decoded_andMatrixOutputs_T_164) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, decoder_decoded_andMatrixOutputs_andMatrixInput_15_57) node decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, decoder_decoded_andMatrixOutputs_andMatrixInput_13_104) node decoder_decoded_andMatrixOutputs_lo_lo_154 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_109, decoder_decoded_andMatrixOutputs_lo_lo_lo_57) node decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, decoder_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, decoder_decoded_andMatrixOutputs_andMatrixInput_9_115) node decoder_decoded_andMatrixOutputs_lo_hi_164 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_115, decoder_decoded_andMatrixOutputs_lo_hi_lo_104) node decoder_decoded_andMatrixOutputs_lo_165 = cat(decoder_decoded_andMatrixOutputs_lo_hi_164, decoder_decoded_andMatrixOutputs_lo_lo_154) node decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, decoder_decoded_andMatrixOutputs_andMatrixInput_7_154) node decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, decoder_decoded_andMatrixOutputs_andMatrixInput_5_164) node decoder_decoded_andMatrixOutputs_hi_lo_161 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_112, decoder_decoded_andMatrixOutputs_hi_lo_lo_92) node decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, decoder_decoded_andMatrixOutputs_andMatrixInput_3_165) node decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, decoder_decoded_andMatrixOutputs_andMatrixInput_1_165) node decoder_decoded_andMatrixOutputs_hi_hi_165 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_135, decoder_decoded_andMatrixOutputs_hi_hi_lo_106) node decoder_decoded_andMatrixOutputs_hi_165 = cat(decoder_decoded_andMatrixOutputs_hi_hi_165, decoder_decoded_andMatrixOutputs_hi_lo_161) node _decoder_decoded_andMatrixOutputs_T_165 = cat(decoder_decoded_andMatrixOutputs_hi_165, decoder_decoded_andMatrixOutputs_lo_165) node decoder_decoded_andMatrixOutputs_61_2 = andr(_decoder_decoded_andMatrixOutputs_T_165) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, decoder_decoded_andMatrixOutputs_andMatrixInput_15_58) node decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, decoder_decoded_andMatrixOutputs_andMatrixInput_13_105) node decoder_decoded_andMatrixOutputs_lo_lo_155 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_110, decoder_decoded_andMatrixOutputs_lo_lo_lo_58) node decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, decoder_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, decoder_decoded_andMatrixOutputs_andMatrixInput_9_116) node decoder_decoded_andMatrixOutputs_lo_hi_165 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_116, decoder_decoded_andMatrixOutputs_lo_hi_lo_105) node decoder_decoded_andMatrixOutputs_lo_166 = cat(decoder_decoded_andMatrixOutputs_lo_hi_165, decoder_decoded_andMatrixOutputs_lo_lo_155) node decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, decoder_decoded_andMatrixOutputs_andMatrixInput_7_155) node decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, decoder_decoded_andMatrixOutputs_andMatrixInput_5_165) node decoder_decoded_andMatrixOutputs_hi_lo_162 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_113, decoder_decoded_andMatrixOutputs_hi_lo_lo_93) node decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, decoder_decoded_andMatrixOutputs_andMatrixInput_3_166) node decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, decoder_decoded_andMatrixOutputs_andMatrixInput_1_166) node decoder_decoded_andMatrixOutputs_hi_hi_166 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_136, decoder_decoded_andMatrixOutputs_hi_hi_lo_107) node decoder_decoded_andMatrixOutputs_hi_166 = cat(decoder_decoded_andMatrixOutputs_hi_hi_166, decoder_decoded_andMatrixOutputs_hi_lo_162) node _decoder_decoded_andMatrixOutputs_T_166 = cat(decoder_decoded_andMatrixOutputs_hi_166, decoder_decoded_andMatrixOutputs_lo_166) node decoder_decoded_andMatrixOutputs_149_2 = andr(_decoder_decoded_andMatrixOutputs_T_166) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, decoder_decoded_andMatrixOutputs_andMatrixInput_15_59) node decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, decoder_decoded_andMatrixOutputs_andMatrixInput_13_106) node decoder_decoded_andMatrixOutputs_lo_lo_156 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_111, decoder_decoded_andMatrixOutputs_lo_lo_lo_59) node decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, decoder_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, decoder_decoded_andMatrixOutputs_andMatrixInput_9_117) node decoder_decoded_andMatrixOutputs_lo_hi_166 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_117, decoder_decoded_andMatrixOutputs_lo_hi_lo_106) node decoder_decoded_andMatrixOutputs_lo_167 = cat(decoder_decoded_andMatrixOutputs_lo_hi_166, decoder_decoded_andMatrixOutputs_lo_lo_156) node decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, decoder_decoded_andMatrixOutputs_andMatrixInput_7_156) node decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, decoder_decoded_andMatrixOutputs_andMatrixInput_5_166) node decoder_decoded_andMatrixOutputs_hi_lo_163 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_114, decoder_decoded_andMatrixOutputs_hi_lo_lo_94) node decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, decoder_decoded_andMatrixOutputs_andMatrixInput_3_167) node decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, decoder_decoded_andMatrixOutputs_andMatrixInput_1_167) node decoder_decoded_andMatrixOutputs_hi_hi_167 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_137, decoder_decoded_andMatrixOutputs_hi_hi_lo_108) node decoder_decoded_andMatrixOutputs_hi_167 = cat(decoder_decoded_andMatrixOutputs_hi_hi_167, decoder_decoded_andMatrixOutputs_hi_lo_163) node _decoder_decoded_andMatrixOutputs_T_167 = cat(decoder_decoded_andMatrixOutputs_hi_167, decoder_decoded_andMatrixOutputs_lo_167) node decoder_decoded_andMatrixOutputs_173_2 = andr(_decoder_decoded_andMatrixOutputs_T_167) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, decoder_decoded_andMatrixOutputs_andMatrixInput_15_60) node decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, decoder_decoded_andMatrixOutputs_andMatrixInput_13_107) node decoder_decoded_andMatrixOutputs_lo_lo_157 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_112, decoder_decoded_andMatrixOutputs_lo_lo_lo_60) node decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, decoder_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, decoder_decoded_andMatrixOutputs_andMatrixInput_9_118) node decoder_decoded_andMatrixOutputs_lo_hi_167 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_118, decoder_decoded_andMatrixOutputs_lo_hi_lo_107) node decoder_decoded_andMatrixOutputs_lo_168 = cat(decoder_decoded_andMatrixOutputs_lo_hi_167, decoder_decoded_andMatrixOutputs_lo_lo_157) node decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, decoder_decoded_andMatrixOutputs_andMatrixInput_7_157) node decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, decoder_decoded_andMatrixOutputs_andMatrixInput_5_167) node decoder_decoded_andMatrixOutputs_hi_lo_164 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_115, decoder_decoded_andMatrixOutputs_hi_lo_lo_95) node decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, decoder_decoded_andMatrixOutputs_andMatrixInput_3_168) node decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, decoder_decoded_andMatrixOutputs_andMatrixInput_1_168) node decoder_decoded_andMatrixOutputs_hi_hi_168 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_138, decoder_decoded_andMatrixOutputs_hi_hi_lo_109) node decoder_decoded_andMatrixOutputs_hi_168 = cat(decoder_decoded_andMatrixOutputs_hi_hi_168, decoder_decoded_andMatrixOutputs_hi_lo_164) node _decoder_decoded_andMatrixOutputs_T_168 = cat(decoder_decoded_andMatrixOutputs_hi_168, decoder_decoded_andMatrixOutputs_lo_168) node decoder_decoded_andMatrixOutputs_37_2 = andr(_decoder_decoded_andMatrixOutputs_T_168) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoder_decoded_plaInput, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = bits(decoder_decoded_plaInput, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = bits(decoder_decoded_plaInput, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, decoder_decoded_andMatrixOutputs_andMatrixInput_21_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, decoder_decoded_andMatrixOutputs_andMatrixInput_18_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_19_14) node decoder_decoded_andMatrixOutputs_lo_lo_158 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_113, decoder_decoded_andMatrixOutputs_lo_lo_lo_61) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, decoder_decoded_andMatrixOutputs_andMatrixInput_15_61) node decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_36) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, decoder_decoded_andMatrixOutputs_andMatrixInput_12_110) node decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_13_108) node decoder_decoded_andMatrixOutputs_lo_hi_168 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_119, decoder_decoded_andMatrixOutputs_lo_hi_lo_108) node decoder_decoded_andMatrixOutputs_lo_169 = cat(decoder_decoded_andMatrixOutputs_lo_hi_168, decoder_decoded_andMatrixOutputs_lo_lo_158) node decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, decoder_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, decoder_decoded_andMatrixOutputs_andMatrixInput_7_158) node decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoder_decoded_andMatrixOutputs_hi_lo_165 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_116, decoder_decoded_andMatrixOutputs_hi_lo_lo_96) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, decoder_decoded_andMatrixOutputs_andMatrixInput_4_169) node decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_5_168) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, decoder_decoded_andMatrixOutputs_andMatrixInput_1_169) node decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_2_169) node decoder_decoded_andMatrixOutputs_hi_hi_169 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_139, decoder_decoded_andMatrixOutputs_hi_hi_lo_110) node decoder_decoded_andMatrixOutputs_hi_169 = cat(decoder_decoded_andMatrixOutputs_hi_hi_169, decoder_decoded_andMatrixOutputs_hi_lo_165) node _decoder_decoded_andMatrixOutputs_T_169 = cat(decoder_decoded_andMatrixOutputs_hi_169, decoder_decoded_andMatrixOutputs_lo_169) node decoder_decoded_andMatrixOutputs_122_2 = andr(_decoder_decoded_andMatrixOutputs_T_169) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = bits(decoder_decoded_plaInput, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, decoder_decoded_andMatrixOutputs_andMatrixInput_26_6) node decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_27_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, decoder_decoded_andMatrixOutputs_andMatrixInput_24_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, decoder_decoded_andMatrixOutputs_andMatrixInput_22_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6) node decoder_decoded_andMatrixOutputs_lo_lo_159 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_114, decoder_decoded_andMatrixOutputs_lo_lo_lo_62) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, decoder_decoded_andMatrixOutputs_andMatrixInput_19_15) node decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_20_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, decoder_decoded_andMatrixOutputs_andMatrixInput_17_24) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, decoder_decoded_andMatrixOutputs_andMatrixInput_15_62) node decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6) node decoder_decoded_andMatrixOutputs_lo_hi_169 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_120, decoder_decoded_andMatrixOutputs_lo_hi_lo_109) node decoder_decoded_andMatrixOutputs_lo_170 = cat(decoder_decoded_andMatrixOutputs_lo_hi_169, decoder_decoded_andMatrixOutputs_lo_lo_159) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, decoder_decoded_andMatrixOutputs_andMatrixInput_12_111) node decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_109) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, decoder_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, decoder_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6) node decoder_decoded_andMatrixOutputs_hi_lo_166 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_117, decoder_decoded_andMatrixOutputs_hi_lo_lo_97) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, decoder_decoded_andMatrixOutputs_andMatrixInput_5_169) node decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_166) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, decoder_decoded_andMatrixOutputs_andMatrixInput_3_170) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, decoder_decoded_andMatrixOutputs_andMatrixInput_1_170) node decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6) node decoder_decoded_andMatrixOutputs_hi_hi_170 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_140, decoder_decoded_andMatrixOutputs_hi_hi_lo_111) node decoder_decoded_andMatrixOutputs_hi_170 = cat(decoder_decoded_andMatrixOutputs_hi_hi_170, decoder_decoded_andMatrixOutputs_hi_lo_166) node _decoder_decoded_andMatrixOutputs_T_170 = cat(decoder_decoded_andMatrixOutputs_hi_170, decoder_decoded_andMatrixOutputs_lo_170) node decoder_decoded_andMatrixOutputs_81_2 = andr(_decoder_decoded_andMatrixOutputs_T_170) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(decoder_decoded_invInputs, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoder_decoded_invInputs, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoder_decoded_invInputs, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoder_decoded_invInputs, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoder_decoded_invInputs, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = bits(decoder_decoded_invInputs, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = bits(decoder_decoded_invInputs, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = bits(decoder_decoded_invInputs, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = bits(decoder_decoded_invInputs, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = bits(decoder_decoded_invInputs, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(decoder_decoded_plaInput, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, decoder_decoded_andMatrixOutputs_andMatrixInput_31_1) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, decoder_decoded_andMatrixOutputs_andMatrixInput_29_3) node decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, decoder_decoded_andMatrixOutputs_andMatrixInput_27_7) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, decoder_decoded_andMatrixOutputs_andMatrixInput_25_7) node decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7) node decoder_decoded_andMatrixOutputs_lo_lo_160 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_115, decoder_decoded_andMatrixOutputs_lo_lo_lo_63) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, decoder_decoded_andMatrixOutputs_andMatrixInput_23_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, decoder_decoded_andMatrixOutputs_andMatrixInput_21_11) node decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, decoder_decoded_andMatrixOutputs_andMatrixInput_19_16) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, decoder_decoded_andMatrixOutputs_andMatrixInput_17_25) node decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7) node decoder_decoded_andMatrixOutputs_lo_hi_170 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_121, decoder_decoded_andMatrixOutputs_lo_hi_lo_110) node decoder_decoded_andMatrixOutputs_lo_171 = cat(decoder_decoded_andMatrixOutputs_lo_hi_170, decoder_decoded_andMatrixOutputs_lo_lo_160) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_98, decoder_decoded_andMatrixOutputs_andMatrixInput_15_63) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, decoder_decoded_andMatrixOutputs_andMatrixInput_13_110) node decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, decoder_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, decoder_decoded_andMatrixOutputs_andMatrixInput_9_121) node decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7) node decoder_decoded_andMatrixOutputs_hi_lo_167 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_118, decoder_decoded_andMatrixOutputs_hi_lo_lo_98) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, decoder_decoded_andMatrixOutputs_andMatrixInput_7_160) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, decoder_decoded_andMatrixOutputs_andMatrixInput_5_170) node decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, decoder_decoded_andMatrixOutputs_andMatrixInput_3_171) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, decoder_decoded_andMatrixOutputs_andMatrixInput_1_171) node decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7) node decoder_decoded_andMatrixOutputs_hi_hi_171 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_141, decoder_decoded_andMatrixOutputs_hi_hi_lo_112) node decoder_decoded_andMatrixOutputs_hi_171 = cat(decoder_decoded_andMatrixOutputs_hi_hi_171, decoder_decoded_andMatrixOutputs_hi_lo_167) node _decoder_decoded_andMatrixOutputs_T_171 = cat(decoder_decoded_andMatrixOutputs_hi_171, decoder_decoded_andMatrixOutputs_lo_171) node decoder_decoded_andMatrixOutputs_119_2 = andr(_decoder_decoded_andMatrixOutputs_T_171) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(decoder_decoded_plaInput, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, decoder_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoder_decoded_andMatrixOutputs_lo_lo_161 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_116, decoder_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, decoder_decoded_andMatrixOutputs_andMatrixInput_7_161) node decoder_decoded_andMatrixOutputs_lo_hi_171 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_122, decoder_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoder_decoded_andMatrixOutputs_lo_172 = cat(decoder_decoded_andMatrixOutputs_lo_hi_171, decoder_decoded_andMatrixOutputs_lo_lo_161) node decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, decoder_decoded_andMatrixOutputs_andMatrixInput_4_172) node decoder_decoded_andMatrixOutputs_hi_lo_168 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_119, decoder_decoded_andMatrixOutputs_andMatrixInput_5_171) node decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, decoder_decoded_andMatrixOutputs_andMatrixInput_1_172) node decoder_decoded_andMatrixOutputs_hi_hi_172 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_142, decoder_decoded_andMatrixOutputs_andMatrixInput_2_172) node decoder_decoded_andMatrixOutputs_hi_172 = cat(decoder_decoded_andMatrixOutputs_hi_hi_172, decoder_decoded_andMatrixOutputs_hi_lo_168) node _decoder_decoded_andMatrixOutputs_T_172 = cat(decoder_decoded_andMatrixOutputs_hi_172, decoder_decoded_andMatrixOutputs_lo_172) node decoder_decoded_andMatrixOutputs_171_2 = andr(_decoder_decoded_andMatrixOutputs_T_172) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, decoder_decoded_andMatrixOutputs_andMatrixInput_13_111) node decoder_decoded_andMatrixOutputs_lo_lo_162 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_117, decoder_decoded_andMatrixOutputs_andMatrixInput_14_99) node decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, decoder_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, decoder_decoded_andMatrixOutputs_andMatrixInput_9_123) node decoder_decoded_andMatrixOutputs_lo_hi_172 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_123, decoder_decoded_andMatrixOutputs_lo_hi_lo_111) node decoder_decoded_andMatrixOutputs_lo_173 = cat(decoder_decoded_andMatrixOutputs_lo_hi_172, decoder_decoded_andMatrixOutputs_lo_lo_162) node decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, decoder_decoded_andMatrixOutputs_andMatrixInput_7_162) node decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, decoder_decoded_andMatrixOutputs_andMatrixInput_5_172) node decoder_decoded_andMatrixOutputs_hi_lo_169 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_120, decoder_decoded_andMatrixOutputs_hi_lo_lo_99) node decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, decoder_decoded_andMatrixOutputs_andMatrixInput_3_173) node decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, decoder_decoded_andMatrixOutputs_andMatrixInput_1_173) node decoder_decoded_andMatrixOutputs_hi_hi_173 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_143, decoder_decoded_andMatrixOutputs_hi_hi_lo_113) node decoder_decoded_andMatrixOutputs_hi_173 = cat(decoder_decoded_andMatrixOutputs_hi_hi_173, decoder_decoded_andMatrixOutputs_hi_lo_169) node _decoder_decoded_andMatrixOutputs_T_173 = cat(decoder_decoded_andMatrixOutputs_hi_173, decoder_decoded_andMatrixOutputs_lo_173) node decoder_decoded_andMatrixOutputs_56_2 = andr(_decoder_decoded_andMatrixOutputs_T_173) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, decoder_decoded_andMatrixOutputs_andMatrixInput_13_112) node decoder_decoded_andMatrixOutputs_lo_lo_163 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_118, decoder_decoded_andMatrixOutputs_andMatrixInput_14_100) node decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, decoder_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, decoder_decoded_andMatrixOutputs_andMatrixInput_9_124) node decoder_decoded_andMatrixOutputs_lo_hi_173 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_124, decoder_decoded_andMatrixOutputs_lo_hi_lo_112) node decoder_decoded_andMatrixOutputs_lo_174 = cat(decoder_decoded_andMatrixOutputs_lo_hi_173, decoder_decoded_andMatrixOutputs_lo_lo_163) node decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, decoder_decoded_andMatrixOutputs_andMatrixInput_7_163) node decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, decoder_decoded_andMatrixOutputs_andMatrixInput_5_173) node decoder_decoded_andMatrixOutputs_hi_lo_170 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_121, decoder_decoded_andMatrixOutputs_hi_lo_lo_100) node decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, decoder_decoded_andMatrixOutputs_andMatrixInput_3_174) node decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, decoder_decoded_andMatrixOutputs_andMatrixInput_1_174) node decoder_decoded_andMatrixOutputs_hi_hi_174 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_144, decoder_decoded_andMatrixOutputs_hi_hi_lo_114) node decoder_decoded_andMatrixOutputs_hi_174 = cat(decoder_decoded_andMatrixOutputs_hi_hi_174, decoder_decoded_andMatrixOutputs_hi_lo_170) node _decoder_decoded_andMatrixOutputs_T_174 = cat(decoder_decoded_andMatrixOutputs_hi_174, decoder_decoded_andMatrixOutputs_lo_174) node decoder_decoded_andMatrixOutputs_79_2 = andr(_decoder_decoded_andMatrixOutputs_T_174) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, decoder_decoded_andMatrixOutputs_andMatrixInput_13_113) node decoder_decoded_andMatrixOutputs_lo_lo_164 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_119, decoder_decoded_andMatrixOutputs_andMatrixInput_14_101) node decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, decoder_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, decoder_decoded_andMatrixOutputs_andMatrixInput_9_125) node decoder_decoded_andMatrixOutputs_lo_hi_174 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_125, decoder_decoded_andMatrixOutputs_lo_hi_lo_113) node decoder_decoded_andMatrixOutputs_lo_175 = cat(decoder_decoded_andMatrixOutputs_lo_hi_174, decoder_decoded_andMatrixOutputs_lo_lo_164) node decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, decoder_decoded_andMatrixOutputs_andMatrixInput_7_164) node decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, decoder_decoded_andMatrixOutputs_andMatrixInput_5_174) node decoder_decoded_andMatrixOutputs_hi_lo_171 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_122, decoder_decoded_andMatrixOutputs_hi_lo_lo_101) node decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, decoder_decoded_andMatrixOutputs_andMatrixInput_3_175) node decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, decoder_decoded_andMatrixOutputs_andMatrixInput_1_175) node decoder_decoded_andMatrixOutputs_hi_hi_175 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_145, decoder_decoded_andMatrixOutputs_hi_hi_lo_115) node decoder_decoded_andMatrixOutputs_hi_175 = cat(decoder_decoded_andMatrixOutputs_hi_hi_175, decoder_decoded_andMatrixOutputs_hi_lo_171) node _decoder_decoded_andMatrixOutputs_T_175 = cat(decoder_decoded_andMatrixOutputs_hi_175, decoder_decoded_andMatrixOutputs_lo_175) node decoder_decoded_andMatrixOutputs_168_2 = andr(_decoder_decoded_andMatrixOutputs_T_175) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, decoder_decoded_andMatrixOutputs_andMatrixInput_13_114) node decoder_decoded_andMatrixOutputs_lo_lo_165 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_120, decoder_decoded_andMatrixOutputs_andMatrixInput_14_102) node decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, decoder_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, decoder_decoded_andMatrixOutputs_andMatrixInput_9_126) node decoder_decoded_andMatrixOutputs_lo_hi_175 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_126, decoder_decoded_andMatrixOutputs_lo_hi_lo_114) node decoder_decoded_andMatrixOutputs_lo_176 = cat(decoder_decoded_andMatrixOutputs_lo_hi_175, decoder_decoded_andMatrixOutputs_lo_lo_165) node decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, decoder_decoded_andMatrixOutputs_andMatrixInput_7_165) node decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, decoder_decoded_andMatrixOutputs_andMatrixInput_5_175) node decoder_decoded_andMatrixOutputs_hi_lo_172 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_123, decoder_decoded_andMatrixOutputs_hi_lo_lo_102) node decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, decoder_decoded_andMatrixOutputs_andMatrixInput_3_176) node decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, decoder_decoded_andMatrixOutputs_andMatrixInput_1_176) node decoder_decoded_andMatrixOutputs_hi_hi_176 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_146, decoder_decoded_andMatrixOutputs_hi_hi_lo_116) node decoder_decoded_andMatrixOutputs_hi_176 = cat(decoder_decoded_andMatrixOutputs_hi_hi_176, decoder_decoded_andMatrixOutputs_hi_lo_172) node _decoder_decoded_andMatrixOutputs_T_176 = cat(decoder_decoded_andMatrixOutputs_hi_176, decoder_decoded_andMatrixOutputs_lo_176) node decoder_decoded_andMatrixOutputs_154_2 = andr(_decoder_decoded_andMatrixOutputs_T_176) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, decoder_decoded_andMatrixOutputs_andMatrixInput_15_64) node decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, decoder_decoded_andMatrixOutputs_andMatrixInput_13_115) node decoder_decoded_andMatrixOutputs_lo_lo_166 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_121, decoder_decoded_andMatrixOutputs_lo_lo_lo_64) node decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, decoder_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, decoder_decoded_andMatrixOutputs_andMatrixInput_9_127) node decoder_decoded_andMatrixOutputs_lo_hi_176 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_127, decoder_decoded_andMatrixOutputs_lo_hi_lo_115) node decoder_decoded_andMatrixOutputs_lo_177 = cat(decoder_decoded_andMatrixOutputs_lo_hi_176, decoder_decoded_andMatrixOutputs_lo_lo_166) node decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, decoder_decoded_andMatrixOutputs_andMatrixInput_7_166) node decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, decoder_decoded_andMatrixOutputs_andMatrixInput_5_176) node decoder_decoded_andMatrixOutputs_hi_lo_173 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_124, decoder_decoded_andMatrixOutputs_hi_lo_lo_103) node decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, decoder_decoded_andMatrixOutputs_andMatrixInput_3_177) node decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, decoder_decoded_andMatrixOutputs_andMatrixInput_1_177) node decoder_decoded_andMatrixOutputs_hi_hi_177 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_147, decoder_decoded_andMatrixOutputs_hi_hi_lo_117) node decoder_decoded_andMatrixOutputs_hi_177 = cat(decoder_decoded_andMatrixOutputs_hi_hi_177, decoder_decoded_andMatrixOutputs_hi_lo_173) node _decoder_decoded_andMatrixOutputs_T_177 = cat(decoder_decoded_andMatrixOutputs_hi_177, decoder_decoded_andMatrixOutputs_lo_177) node decoder_decoded_andMatrixOutputs_192_2 = andr(_decoder_decoded_andMatrixOutputs_T_177) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, decoder_decoded_andMatrixOutputs_andMatrixInput_15_65) node decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, decoder_decoded_andMatrixOutputs_andMatrixInput_13_116) node decoder_decoded_andMatrixOutputs_lo_lo_167 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_122, decoder_decoded_andMatrixOutputs_lo_lo_lo_65) node decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, decoder_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, decoder_decoded_andMatrixOutputs_andMatrixInput_9_128) node decoder_decoded_andMatrixOutputs_lo_hi_177 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_128, decoder_decoded_andMatrixOutputs_lo_hi_lo_116) node decoder_decoded_andMatrixOutputs_lo_178 = cat(decoder_decoded_andMatrixOutputs_lo_hi_177, decoder_decoded_andMatrixOutputs_lo_lo_167) node decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, decoder_decoded_andMatrixOutputs_andMatrixInput_7_167) node decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, decoder_decoded_andMatrixOutputs_andMatrixInput_5_177) node decoder_decoded_andMatrixOutputs_hi_lo_174 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_125, decoder_decoded_andMatrixOutputs_hi_lo_lo_104) node decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, decoder_decoded_andMatrixOutputs_andMatrixInput_3_178) node decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, decoder_decoded_andMatrixOutputs_andMatrixInput_1_178) node decoder_decoded_andMatrixOutputs_hi_hi_178 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_148, decoder_decoded_andMatrixOutputs_hi_hi_lo_118) node decoder_decoded_andMatrixOutputs_hi_178 = cat(decoder_decoded_andMatrixOutputs_hi_hi_178, decoder_decoded_andMatrixOutputs_hi_lo_174) node _decoder_decoded_andMatrixOutputs_T_178 = cat(decoder_decoded_andMatrixOutputs_hi_178, decoder_decoded_andMatrixOutputs_lo_178) node decoder_decoded_andMatrixOutputs_38_2 = andr(_decoder_decoded_andMatrixOutputs_T_178) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, decoder_decoded_andMatrixOutputs_andMatrixInput_13_117) node decoder_decoded_andMatrixOutputs_lo_lo_168 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_123, decoder_decoded_andMatrixOutputs_andMatrixInput_14_105) node decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, decoder_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, decoder_decoded_andMatrixOutputs_andMatrixInput_9_129) node decoder_decoded_andMatrixOutputs_lo_hi_178 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_129, decoder_decoded_andMatrixOutputs_lo_hi_lo_117) node decoder_decoded_andMatrixOutputs_lo_179 = cat(decoder_decoded_andMatrixOutputs_lo_hi_178, decoder_decoded_andMatrixOutputs_lo_lo_168) node decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, decoder_decoded_andMatrixOutputs_andMatrixInput_7_168) node decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, decoder_decoded_andMatrixOutputs_andMatrixInput_5_178) node decoder_decoded_andMatrixOutputs_hi_lo_175 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_126, decoder_decoded_andMatrixOutputs_hi_lo_lo_105) node decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, decoder_decoded_andMatrixOutputs_andMatrixInput_3_179) node decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, decoder_decoded_andMatrixOutputs_andMatrixInput_1_179) node decoder_decoded_andMatrixOutputs_hi_hi_179 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_149, decoder_decoded_andMatrixOutputs_hi_hi_lo_119) node decoder_decoded_andMatrixOutputs_hi_179 = cat(decoder_decoded_andMatrixOutputs_hi_hi_179, decoder_decoded_andMatrixOutputs_hi_lo_175) node _decoder_decoded_andMatrixOutputs_T_179 = cat(decoder_decoded_andMatrixOutputs_hi_179, decoder_decoded_andMatrixOutputs_lo_179) node decoder_decoded_andMatrixOutputs_158_2 = andr(_decoder_decoded_andMatrixOutputs_T_179) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, decoder_decoded_andMatrixOutputs_andMatrixInput_13_118) node decoder_decoded_andMatrixOutputs_lo_lo_169 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_124, decoder_decoded_andMatrixOutputs_andMatrixInput_14_106) node decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, decoder_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, decoder_decoded_andMatrixOutputs_andMatrixInput_9_130) node decoder_decoded_andMatrixOutputs_lo_hi_179 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_130, decoder_decoded_andMatrixOutputs_lo_hi_lo_118) node decoder_decoded_andMatrixOutputs_lo_180 = cat(decoder_decoded_andMatrixOutputs_lo_hi_179, decoder_decoded_andMatrixOutputs_lo_lo_169) node decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, decoder_decoded_andMatrixOutputs_andMatrixInput_7_169) node decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, decoder_decoded_andMatrixOutputs_andMatrixInput_5_179) node decoder_decoded_andMatrixOutputs_hi_lo_176 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_127, decoder_decoded_andMatrixOutputs_hi_lo_lo_106) node decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, decoder_decoded_andMatrixOutputs_andMatrixInput_3_180) node decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, decoder_decoded_andMatrixOutputs_andMatrixInput_1_180) node decoder_decoded_andMatrixOutputs_hi_hi_180 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_150, decoder_decoded_andMatrixOutputs_hi_hi_lo_120) node decoder_decoded_andMatrixOutputs_hi_180 = cat(decoder_decoded_andMatrixOutputs_hi_hi_180, decoder_decoded_andMatrixOutputs_hi_lo_176) node _decoder_decoded_andMatrixOutputs_T_180 = cat(decoder_decoded_andMatrixOutputs_hi_180, decoder_decoded_andMatrixOutputs_lo_180) node decoder_decoded_andMatrixOutputs_109_2 = andr(_decoder_decoded_andMatrixOutputs_T_180) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, decoder_decoded_andMatrixOutputs_andMatrixInput_15_66) node decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, decoder_decoded_andMatrixOutputs_andMatrixInput_13_119) node decoder_decoded_andMatrixOutputs_lo_lo_170 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_125, decoder_decoded_andMatrixOutputs_lo_lo_lo_66) node decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, decoder_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, decoder_decoded_andMatrixOutputs_andMatrixInput_9_131) node decoder_decoded_andMatrixOutputs_lo_hi_180 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_131, decoder_decoded_andMatrixOutputs_lo_hi_lo_119) node decoder_decoded_andMatrixOutputs_lo_181 = cat(decoder_decoded_andMatrixOutputs_lo_hi_180, decoder_decoded_andMatrixOutputs_lo_lo_170) node decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, decoder_decoded_andMatrixOutputs_andMatrixInput_7_170) node decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, decoder_decoded_andMatrixOutputs_andMatrixInput_5_180) node decoder_decoded_andMatrixOutputs_hi_lo_177 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_128, decoder_decoded_andMatrixOutputs_hi_lo_lo_107) node decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, decoder_decoded_andMatrixOutputs_andMatrixInput_3_181) node decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, decoder_decoded_andMatrixOutputs_andMatrixInput_1_181) node decoder_decoded_andMatrixOutputs_hi_hi_181 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_151, decoder_decoded_andMatrixOutputs_hi_hi_lo_121) node decoder_decoded_andMatrixOutputs_hi_181 = cat(decoder_decoded_andMatrixOutputs_hi_hi_181, decoder_decoded_andMatrixOutputs_hi_lo_177) node _decoder_decoded_andMatrixOutputs_T_181 = cat(decoder_decoded_andMatrixOutputs_hi_181, decoder_decoded_andMatrixOutputs_lo_181) node decoder_decoded_andMatrixOutputs_23_2 = andr(_decoder_decoded_andMatrixOutputs_T_181) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, decoder_decoded_andMatrixOutputs_andMatrixInput_15_67) node decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, decoder_decoded_andMatrixOutputs_andMatrixInput_13_120) node decoder_decoded_andMatrixOutputs_lo_lo_171 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_126, decoder_decoded_andMatrixOutputs_lo_lo_lo_67) node decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, decoder_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, decoder_decoded_andMatrixOutputs_andMatrixInput_9_132) node decoder_decoded_andMatrixOutputs_lo_hi_181 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_132, decoder_decoded_andMatrixOutputs_lo_hi_lo_120) node decoder_decoded_andMatrixOutputs_lo_182 = cat(decoder_decoded_andMatrixOutputs_lo_hi_181, decoder_decoded_andMatrixOutputs_lo_lo_171) node decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, decoder_decoded_andMatrixOutputs_andMatrixInput_7_171) node decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, decoder_decoded_andMatrixOutputs_andMatrixInput_5_181) node decoder_decoded_andMatrixOutputs_hi_lo_178 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_129, decoder_decoded_andMatrixOutputs_hi_lo_lo_108) node decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, decoder_decoded_andMatrixOutputs_andMatrixInput_3_182) node decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, decoder_decoded_andMatrixOutputs_andMatrixInput_1_182) node decoder_decoded_andMatrixOutputs_hi_hi_182 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_152, decoder_decoded_andMatrixOutputs_hi_hi_lo_122) node decoder_decoded_andMatrixOutputs_hi_182 = cat(decoder_decoded_andMatrixOutputs_hi_hi_182, decoder_decoded_andMatrixOutputs_hi_lo_178) node _decoder_decoded_andMatrixOutputs_T_182 = cat(decoder_decoded_andMatrixOutputs_hi_182, decoder_decoded_andMatrixOutputs_lo_182) node decoder_decoded_andMatrixOutputs_100_2 = andr(_decoder_decoded_andMatrixOutputs_T_182) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, decoder_decoded_andMatrixOutputs_andMatrixInput_15_68) node decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, decoder_decoded_andMatrixOutputs_andMatrixInput_13_121) node decoder_decoded_andMatrixOutputs_lo_lo_172 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_127, decoder_decoded_andMatrixOutputs_lo_lo_lo_68) node decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, decoder_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, decoder_decoded_andMatrixOutputs_andMatrixInput_9_133) node decoder_decoded_andMatrixOutputs_lo_hi_182 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_133, decoder_decoded_andMatrixOutputs_lo_hi_lo_121) node decoder_decoded_andMatrixOutputs_lo_183 = cat(decoder_decoded_andMatrixOutputs_lo_hi_182, decoder_decoded_andMatrixOutputs_lo_lo_172) node decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, decoder_decoded_andMatrixOutputs_andMatrixInput_7_172) node decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, decoder_decoded_andMatrixOutputs_andMatrixInput_5_182) node decoder_decoded_andMatrixOutputs_hi_lo_179 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_130, decoder_decoded_andMatrixOutputs_hi_lo_lo_109) node decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, decoder_decoded_andMatrixOutputs_andMatrixInput_3_183) node decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, decoder_decoded_andMatrixOutputs_andMatrixInput_1_183) node decoder_decoded_andMatrixOutputs_hi_hi_183 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_153, decoder_decoded_andMatrixOutputs_hi_hi_lo_123) node decoder_decoded_andMatrixOutputs_hi_183 = cat(decoder_decoded_andMatrixOutputs_hi_hi_183, decoder_decoded_andMatrixOutputs_hi_lo_179) node _decoder_decoded_andMatrixOutputs_T_183 = cat(decoder_decoded_andMatrixOutputs_hi_183, decoder_decoded_andMatrixOutputs_lo_183) node decoder_decoded_andMatrixOutputs_118_2 = andr(_decoder_decoded_andMatrixOutputs_T_183) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, decoder_decoded_andMatrixOutputs_andMatrixInput_15_69) node decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, decoder_decoded_andMatrixOutputs_andMatrixInput_13_122) node decoder_decoded_andMatrixOutputs_lo_lo_173 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_128, decoder_decoded_andMatrixOutputs_lo_lo_lo_69) node decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, decoder_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, decoder_decoded_andMatrixOutputs_andMatrixInput_9_134) node decoder_decoded_andMatrixOutputs_lo_hi_183 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_134, decoder_decoded_andMatrixOutputs_lo_hi_lo_122) node decoder_decoded_andMatrixOutputs_lo_184 = cat(decoder_decoded_andMatrixOutputs_lo_hi_183, decoder_decoded_andMatrixOutputs_lo_lo_173) node decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, decoder_decoded_andMatrixOutputs_andMatrixInput_7_173) node decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, decoder_decoded_andMatrixOutputs_andMatrixInput_5_183) node decoder_decoded_andMatrixOutputs_hi_lo_180 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_131, decoder_decoded_andMatrixOutputs_hi_lo_lo_110) node decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, decoder_decoded_andMatrixOutputs_andMatrixInput_3_184) node decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, decoder_decoded_andMatrixOutputs_andMatrixInput_1_184) node decoder_decoded_andMatrixOutputs_hi_hi_184 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_154, decoder_decoded_andMatrixOutputs_hi_hi_lo_124) node decoder_decoded_andMatrixOutputs_hi_184 = cat(decoder_decoded_andMatrixOutputs_hi_hi_184, decoder_decoded_andMatrixOutputs_hi_lo_180) node _decoder_decoded_andMatrixOutputs_T_184 = cat(decoder_decoded_andMatrixOutputs_hi_184, decoder_decoded_andMatrixOutputs_lo_184) node decoder_decoded_andMatrixOutputs_116_2 = andr(_decoder_decoded_andMatrixOutputs_T_184) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_111, decoder_decoded_andMatrixOutputs_andMatrixInput_15_70) node decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, decoder_decoded_andMatrixOutputs_andMatrixInput_13_123) node decoder_decoded_andMatrixOutputs_lo_lo_174 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_129, decoder_decoded_andMatrixOutputs_lo_lo_lo_70) node decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, decoder_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, decoder_decoded_andMatrixOutputs_andMatrixInput_9_135) node decoder_decoded_andMatrixOutputs_lo_hi_184 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_135, decoder_decoded_andMatrixOutputs_lo_hi_lo_123) node decoder_decoded_andMatrixOutputs_lo_185 = cat(decoder_decoded_andMatrixOutputs_lo_hi_184, decoder_decoded_andMatrixOutputs_lo_lo_174) node decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, decoder_decoded_andMatrixOutputs_andMatrixInput_7_174) node decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, decoder_decoded_andMatrixOutputs_andMatrixInput_5_184) node decoder_decoded_andMatrixOutputs_hi_lo_181 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_132, decoder_decoded_andMatrixOutputs_hi_lo_lo_111) node decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, decoder_decoded_andMatrixOutputs_andMatrixInput_3_185) node decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, decoder_decoded_andMatrixOutputs_andMatrixInput_1_185) node decoder_decoded_andMatrixOutputs_hi_hi_185 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_155, decoder_decoded_andMatrixOutputs_hi_hi_lo_125) node decoder_decoded_andMatrixOutputs_hi_185 = cat(decoder_decoded_andMatrixOutputs_hi_hi_185, decoder_decoded_andMatrixOutputs_hi_lo_181) node _decoder_decoded_andMatrixOutputs_T_185 = cat(decoder_decoded_andMatrixOutputs_hi_185, decoder_decoded_andMatrixOutputs_lo_185) node decoder_decoded_andMatrixOutputs_156_2 = andr(_decoder_decoded_andMatrixOutputs_T_185) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, decoder_decoded_andMatrixOutputs_andMatrixInput_19_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, decoder_decoded_andMatrixOutputs_andMatrixInput_16_39) node decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_17_26) node decoder_decoded_andMatrixOutputs_lo_lo_175 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_130, decoder_decoded_andMatrixOutputs_lo_lo_lo_71) node decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, decoder_decoded_andMatrixOutputs_andMatrixInput_14_112) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, decoder_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_12_126) node decoder_decoded_andMatrixOutputs_lo_hi_185 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_136, decoder_decoded_andMatrixOutputs_lo_hi_lo_124) node decoder_decoded_andMatrixOutputs_lo_186 = cat(decoder_decoded_andMatrixOutputs_lo_hi_185, decoder_decoded_andMatrixOutputs_lo_lo_175) node decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, decoder_decoded_andMatrixOutputs_andMatrixInput_9_136) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, decoder_decoded_andMatrixOutputs_andMatrixInput_6_182) node decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_7_175) node decoder_decoded_andMatrixOutputs_hi_lo_182 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_133, decoder_decoded_andMatrixOutputs_hi_lo_lo_112) node decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, decoder_decoded_andMatrixOutputs_andMatrixInput_4_186) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, decoder_decoded_andMatrixOutputs_andMatrixInput_1_186) node decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_2_186) node decoder_decoded_andMatrixOutputs_hi_hi_186 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_156, decoder_decoded_andMatrixOutputs_hi_hi_lo_126) node decoder_decoded_andMatrixOutputs_hi_186 = cat(decoder_decoded_andMatrixOutputs_hi_hi_186, decoder_decoded_andMatrixOutputs_hi_lo_182) node _decoder_decoded_andMatrixOutputs_T_186 = cat(decoder_decoded_andMatrixOutputs_hi_186, decoder_decoded_andMatrixOutputs_lo_186) node decoder_decoded_andMatrixOutputs_113_2 = andr(_decoder_decoded_andMatrixOutputs_T_186) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, decoder_decoded_andMatrixOutputs_andMatrixInput_19_18) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, decoder_decoded_andMatrixOutputs_andMatrixInput_16_40) node decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_17_27) node decoder_decoded_andMatrixOutputs_lo_lo_176 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_131, decoder_decoded_andMatrixOutputs_lo_lo_lo_72) node decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, decoder_decoded_andMatrixOutputs_andMatrixInput_14_113) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, decoder_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_127) node decoder_decoded_andMatrixOutputs_lo_hi_186 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_137, decoder_decoded_andMatrixOutputs_lo_hi_lo_125) node decoder_decoded_andMatrixOutputs_lo_187 = cat(decoder_decoded_andMatrixOutputs_lo_hi_186, decoder_decoded_andMatrixOutputs_lo_lo_176) node decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, decoder_decoded_andMatrixOutputs_andMatrixInput_9_137) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, decoder_decoded_andMatrixOutputs_andMatrixInput_6_183) node decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_7_176) node decoder_decoded_andMatrixOutputs_hi_lo_183 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_134, decoder_decoded_andMatrixOutputs_hi_lo_lo_113) node decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, decoder_decoded_andMatrixOutputs_andMatrixInput_4_187) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, decoder_decoded_andMatrixOutputs_andMatrixInput_1_187) node decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_2_187) node decoder_decoded_andMatrixOutputs_hi_hi_187 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_157, decoder_decoded_andMatrixOutputs_hi_hi_lo_127) node decoder_decoded_andMatrixOutputs_hi_187 = cat(decoder_decoded_andMatrixOutputs_hi_hi_187, decoder_decoded_andMatrixOutputs_hi_lo_183) node _decoder_decoded_andMatrixOutputs_T_187 = cat(decoder_decoded_andMatrixOutputs_hi_187, decoder_decoded_andMatrixOutputs_lo_187) node decoder_decoded_andMatrixOutputs_105_2 = andr(_decoder_decoded_andMatrixOutputs_T_187) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, decoder_decoded_andMatrixOutputs_andMatrixInput_19_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, decoder_decoded_andMatrixOutputs_andMatrixInput_16_41) node decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_28) node decoder_decoded_andMatrixOutputs_lo_lo_177 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_132, decoder_decoded_andMatrixOutputs_lo_lo_lo_73) node decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, decoder_decoded_andMatrixOutputs_andMatrixInput_14_114) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, decoder_decoded_andMatrixOutputs_andMatrixInput_11_132) node decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_12_128) node decoder_decoded_andMatrixOutputs_lo_hi_187 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_138, decoder_decoded_andMatrixOutputs_lo_hi_lo_126) node decoder_decoded_andMatrixOutputs_lo_188 = cat(decoder_decoded_andMatrixOutputs_lo_hi_187, decoder_decoded_andMatrixOutputs_lo_lo_177) node decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, decoder_decoded_andMatrixOutputs_andMatrixInput_9_138) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, decoder_decoded_andMatrixOutputs_andMatrixInput_6_184) node decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_7_177) node decoder_decoded_andMatrixOutputs_hi_lo_184 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_135, decoder_decoded_andMatrixOutputs_hi_lo_lo_114) node decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, decoder_decoded_andMatrixOutputs_andMatrixInput_4_188) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, decoder_decoded_andMatrixOutputs_andMatrixInput_1_188) node decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_2_188) node decoder_decoded_andMatrixOutputs_hi_hi_188 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_158, decoder_decoded_andMatrixOutputs_hi_hi_lo_128) node decoder_decoded_andMatrixOutputs_hi_188 = cat(decoder_decoded_andMatrixOutputs_hi_hi_188, decoder_decoded_andMatrixOutputs_hi_lo_184) node _decoder_decoded_andMatrixOutputs_T_188 = cat(decoder_decoded_andMatrixOutputs_hi_188, decoder_decoded_andMatrixOutputs_lo_188) node decoder_decoded_andMatrixOutputs_83_2 = andr(_decoder_decoded_andMatrixOutputs_T_188) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, decoder_decoded_andMatrixOutputs_andMatrixInput_19_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_74, decoder_decoded_andMatrixOutputs_andMatrixInput_16_42) node decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_17_29) node decoder_decoded_andMatrixOutputs_lo_lo_178 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_133, decoder_decoded_andMatrixOutputs_lo_lo_lo_74) node decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, decoder_decoded_andMatrixOutputs_andMatrixInput_14_115) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, decoder_decoded_andMatrixOutputs_andMatrixInput_11_133) node decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_12_129) node decoder_decoded_andMatrixOutputs_lo_hi_188 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_139, decoder_decoded_andMatrixOutputs_lo_hi_lo_127) node decoder_decoded_andMatrixOutputs_lo_189 = cat(decoder_decoded_andMatrixOutputs_lo_hi_188, decoder_decoded_andMatrixOutputs_lo_lo_178) node decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, decoder_decoded_andMatrixOutputs_andMatrixInput_9_139) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, decoder_decoded_andMatrixOutputs_andMatrixInput_6_185) node decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_7_178) node decoder_decoded_andMatrixOutputs_hi_lo_185 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_136, decoder_decoded_andMatrixOutputs_hi_lo_lo_115) node decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, decoder_decoded_andMatrixOutputs_andMatrixInput_4_189) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, decoder_decoded_andMatrixOutputs_andMatrixInput_1_189) node decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_2_189) node decoder_decoded_andMatrixOutputs_hi_hi_189 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_159, decoder_decoded_andMatrixOutputs_hi_hi_lo_129) node decoder_decoded_andMatrixOutputs_hi_189 = cat(decoder_decoded_andMatrixOutputs_hi_hi_189, decoder_decoded_andMatrixOutputs_hi_lo_185) node _decoder_decoded_andMatrixOutputs_T_189 = cat(decoder_decoded_andMatrixOutputs_hi_189, decoder_decoded_andMatrixOutputs_lo_189) node decoder_decoded_andMatrixOutputs_33_2 = andr(_decoder_decoded_andMatrixOutputs_T_189) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, decoder_decoded_andMatrixOutputs_andMatrixInput_20_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, decoder_decoded_andMatrixOutputs_andMatrixInput_17_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_23) node decoder_decoded_andMatrixOutputs_lo_lo_179 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_134, decoder_decoded_andMatrixOutputs_lo_lo_lo_75) node decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, decoder_decoded_andMatrixOutputs_andMatrixInput_15_75) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, decoder_decoded_andMatrixOutputs_andMatrixInput_12_130) node decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_128) node decoder_decoded_andMatrixOutputs_lo_hi_189 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_140, decoder_decoded_andMatrixOutputs_lo_hi_lo_128) node decoder_decoded_andMatrixOutputs_lo_190 = cat(decoder_decoded_andMatrixOutputs_lo_hi_189, decoder_decoded_andMatrixOutputs_lo_lo_179) node decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, decoder_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, decoder_decoded_andMatrixOutputs_andMatrixInput_7_179) node decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_8_160) node decoder_decoded_andMatrixOutputs_hi_lo_186 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_137, decoder_decoded_andMatrixOutputs_hi_lo_lo_116) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, decoder_decoded_andMatrixOutputs_andMatrixInput_4_190) node decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_5_189) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, decoder_decoded_andMatrixOutputs_andMatrixInput_1_190) node decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_2_190) node decoder_decoded_andMatrixOutputs_hi_hi_190 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_160, decoder_decoded_andMatrixOutputs_hi_hi_lo_130) node decoder_decoded_andMatrixOutputs_hi_190 = cat(decoder_decoded_andMatrixOutputs_hi_hi_190, decoder_decoded_andMatrixOutputs_hi_lo_186) node _decoder_decoded_andMatrixOutputs_T_190 = cat(decoder_decoded_andMatrixOutputs_hi_190, decoder_decoded_andMatrixOutputs_lo_190) node decoder_decoded_andMatrixOutputs_84_2 = andr(_decoder_decoded_andMatrixOutputs_T_190) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, decoder_decoded_andMatrixOutputs_andMatrixInput_20_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, decoder_decoded_andMatrixOutputs_andMatrixInput_17_31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_18_24) node decoder_decoded_andMatrixOutputs_lo_lo_180 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_135, decoder_decoded_andMatrixOutputs_lo_lo_lo_76) node decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, decoder_decoded_andMatrixOutputs_andMatrixInput_15_76) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, decoder_decoded_andMatrixOutputs_andMatrixInput_12_131) node decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_129) node decoder_decoded_andMatrixOutputs_lo_hi_190 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_141, decoder_decoded_andMatrixOutputs_lo_hi_lo_129) node decoder_decoded_andMatrixOutputs_lo_191 = cat(decoder_decoded_andMatrixOutputs_lo_hi_190, decoder_decoded_andMatrixOutputs_lo_lo_180) node decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, decoder_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, decoder_decoded_andMatrixOutputs_andMatrixInput_7_180) node decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_161) node decoder_decoded_andMatrixOutputs_hi_lo_187 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_138, decoder_decoded_andMatrixOutputs_hi_lo_lo_117) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, decoder_decoded_andMatrixOutputs_andMatrixInput_4_191) node decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_190) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, decoder_decoded_andMatrixOutputs_andMatrixInput_1_191) node decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_2_191) node decoder_decoded_andMatrixOutputs_hi_hi_191 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_161, decoder_decoded_andMatrixOutputs_hi_hi_lo_131) node decoder_decoded_andMatrixOutputs_hi_191 = cat(decoder_decoded_andMatrixOutputs_hi_hi_191, decoder_decoded_andMatrixOutputs_hi_lo_187) node _decoder_decoded_andMatrixOutputs_T_191 = cat(decoder_decoded_andMatrixOutputs_hi_191, decoder_decoded_andMatrixOutputs_lo_191) node decoder_decoded_andMatrixOutputs_40_2 = andr(_decoder_decoded_andMatrixOutputs_T_191) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, decoder_decoded_andMatrixOutputs_andMatrixInput_20_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, decoder_decoded_andMatrixOutputs_andMatrixInput_17_32) node decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_18_25) node decoder_decoded_andMatrixOutputs_lo_lo_181 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_136, decoder_decoded_andMatrixOutputs_lo_lo_lo_77) node decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, decoder_decoded_andMatrixOutputs_andMatrixInput_15_77) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, decoder_decoded_andMatrixOutputs_andMatrixInput_12_132) node decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_13_130) node decoder_decoded_andMatrixOutputs_lo_hi_191 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_142, decoder_decoded_andMatrixOutputs_lo_hi_lo_130) node decoder_decoded_andMatrixOutputs_lo_192 = cat(decoder_decoded_andMatrixOutputs_lo_hi_191, decoder_decoded_andMatrixOutputs_lo_lo_181) node decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, decoder_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, decoder_decoded_andMatrixOutputs_andMatrixInput_7_181) node decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_162) node decoder_decoded_andMatrixOutputs_hi_lo_188 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_139, decoder_decoded_andMatrixOutputs_hi_lo_lo_118) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, decoder_decoded_andMatrixOutputs_andMatrixInput_4_192) node decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_191) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, decoder_decoded_andMatrixOutputs_andMatrixInput_1_192) node decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_2_192) node decoder_decoded_andMatrixOutputs_hi_hi_192 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_162, decoder_decoded_andMatrixOutputs_hi_hi_lo_132) node decoder_decoded_andMatrixOutputs_hi_192 = cat(decoder_decoded_andMatrixOutputs_hi_hi_192, decoder_decoded_andMatrixOutputs_hi_lo_188) node _decoder_decoded_andMatrixOutputs_T_192 = cat(decoder_decoded_andMatrixOutputs_hi_192, decoder_decoded_andMatrixOutputs_lo_192) node decoder_decoded_andMatrixOutputs_12_2 = andr(_decoder_decoded_andMatrixOutputs_T_192) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_119 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_78 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, decoder_decoded_andMatrixOutputs_andMatrixInput_20_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, decoder_decoded_andMatrixOutputs_andMatrixInput_17_33) node decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_18_26) node decoder_decoded_andMatrixOutputs_lo_lo_182 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_137, decoder_decoded_andMatrixOutputs_lo_lo_lo_78) node decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_119, decoder_decoded_andMatrixOutputs_andMatrixInput_15_78) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, decoder_decoded_andMatrixOutputs_andMatrixInput_12_133) node decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_13_131) node decoder_decoded_andMatrixOutputs_lo_hi_192 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_143, decoder_decoded_andMatrixOutputs_lo_hi_lo_131) node decoder_decoded_andMatrixOutputs_lo_193 = cat(decoder_decoded_andMatrixOutputs_lo_hi_192, decoder_decoded_andMatrixOutputs_lo_lo_182) node decoder_decoded_andMatrixOutputs_hi_lo_lo_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, decoder_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, decoder_decoded_andMatrixOutputs_andMatrixInput_7_182) node decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_8_163) node decoder_decoded_andMatrixOutputs_hi_lo_189 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_140, decoder_decoded_andMatrixOutputs_hi_lo_lo_119) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, decoder_decoded_andMatrixOutputs_andMatrixInput_4_193) node decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_192) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, decoder_decoded_andMatrixOutputs_andMatrixInput_1_193) node decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_2_193) node decoder_decoded_andMatrixOutputs_hi_hi_193 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_163, decoder_decoded_andMatrixOutputs_hi_hi_lo_133) node decoder_decoded_andMatrixOutputs_hi_193 = cat(decoder_decoded_andMatrixOutputs_hi_hi_193, decoder_decoded_andMatrixOutputs_hi_lo_189) node _decoder_decoded_andMatrixOutputs_T_193 = cat(decoder_decoded_andMatrixOutputs_hi_193, decoder_decoded_andMatrixOutputs_lo_193) node decoder_decoded_andMatrixOutputs_74_2 = andr(_decoder_decoded_andMatrixOutputs_T_193) node decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_118_2, decoder_decoded_andMatrixOutputs_84_2) node decoder_decoded_orMatrixOutputs_lo_lo = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_40_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_114_2, decoder_decoded_andMatrixOutputs_175_2) node decoder_decoded_orMatrixOutputs_lo_hi = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_127_2) node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo) node decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_85_2, decoder_decoded_andMatrixOutputs_10_2) node decoder_decoded_orMatrixOutputs_hi_lo = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_92_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_148_2, decoder_decoded_andMatrixOutputs_75_2) node decoder_decoded_orMatrixOutputs_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_86_2) node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo) node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo) node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T) node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_0_2) node _decoder_decoded_orMatrixOutputs_T_2 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_137_2) node _decoder_decoded_orMatrixOutputs_T_3 = orr(_decoder_decoded_orMatrixOutputs_T_2) node _decoder_decoded_orMatrixOutputs_T_4 = orr(decoder_decoded_andMatrixOutputs_117_2) node _decoder_decoded_orMatrixOutputs_T_5 = orr(decoder_decoded_andMatrixOutputs_21_2) node _decoder_decoded_orMatrixOutputs_T_6 = orr(decoder_decoded_andMatrixOutputs_185_2) node _decoder_decoded_orMatrixOutputs_T_7 = orr(decoder_decoded_andMatrixOutputs_155_2) node decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_161_2, decoder_decoded_andMatrixOutputs_82_2) node decoder_decoded_orMatrixOutputs_lo_1 = cat(decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_81_2) node decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_155_2, decoder_decoded_andMatrixOutputs_58_2) node decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_54_2, decoder_decoded_andMatrixOutputs_185_2) node decoder_decoded_orMatrixOutputs_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_1) node _decoder_decoded_orMatrixOutputs_T_8 = cat(decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_1) node _decoder_decoded_orMatrixOutputs_T_9 = orr(_decoder_decoded_orMatrixOutputs_T_8) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_83_2, decoder_decoded_andMatrixOutputs_33_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_154_2, decoder_decoded_andMatrixOutputs_23_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_100_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_56_2, decoder_decoded_andMatrixOutputs_79_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_168_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_99_2, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_1_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_51_2, decoder_decoded_andMatrixOutputs_174_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_42_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_188_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_137_2, decoder_decoded_andMatrixOutputs_159_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo) node decoder_decoded_orMatrixOutputs_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_8_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_155_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_126_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_103_2, decoder_decoded_andMatrixOutputs_185_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_17_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_191_2, decoder_decoded_andMatrixOutputs_165_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_121_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_97_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_70_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_35_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_190_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_139_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo) node decoder_decoded_orMatrixOutputs_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_2) node _decoder_decoded_orMatrixOutputs_T_10 = cat(decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_2) node _decoder_decoded_orMatrixOutputs_T_11 = orr(_decoder_decoded_orMatrixOutputs_T_10) node _decoder_decoded_orMatrixOutputs_T_12 = orr(decoder_decoded_andMatrixOutputs_8_2) node _decoder_decoded_orMatrixOutputs_T_13 = cat(decoder_decoded_andMatrixOutputs_167_2, decoder_decoded_andMatrixOutputs_108_2) node _decoder_decoded_orMatrixOutputs_T_14 = orr(_decoder_decoded_orMatrixOutputs_T_13) node decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_74_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_116_2, decoder_decoded_andMatrixOutputs_156_2) node decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_136_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_80_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_157_2) node decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_114_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_153_2, decoder_decoded_andMatrixOutputs_107_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_187_2) node decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_76_2, decoder_decoded_andMatrixOutputs_91_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_181_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_3) node _decoder_decoded_orMatrixOutputs_T_15 = cat(decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_3) node _decoder_decoded_orMatrixOutputs_T_16 = orr(_decoder_decoded_orMatrixOutputs_T_15) node _decoder_decoded_orMatrixOutputs_T_17 = orr(decoder_decoded_andMatrixOutputs_181_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_107_2, decoder_decoded_andMatrixOutputs_50_2) node decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_136_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_134_2) node decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_153_2) node decoder_decoded_orMatrixOutputs_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_123_2, decoder_decoded_andMatrixOutputs_124_2) node decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_49_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_22_2, decoder_decoded_andMatrixOutputs_160_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_181_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node decoder_decoded_orMatrixOutputs_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_4) node _decoder_decoded_orMatrixOutputs_T_18 = cat(decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_4) node _decoder_decoded_orMatrixOutputs_T_19 = orr(_decoder_decoded_orMatrixOutputs_T_18) node decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_83_2, decoder_decoded_andMatrixOutputs_33_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_100_2) node decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_136_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_175_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_130_2) node decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node decoder_decoded_orMatrixOutputs_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_4) node decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_107_2, decoder_decoded_andMatrixOutputs_141_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_134_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_153_2) node decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_124_2, decoder_decoded_andMatrixOutputs_49_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_181_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node decoder_decoded_orMatrixOutputs_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_5) node _decoder_decoded_orMatrixOutputs_T_20 = cat(decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_5) node _decoder_decoded_orMatrixOutputs_T_21 = orr(_decoder_decoded_orMatrixOutputs_T_20) node decoder_decoded_orMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_64_2, decoder_decoded_andMatrixOutputs_78_2) node decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_128_2, decoder_decoded_andMatrixOutputs_166_2) node decoder_decoded_orMatrixOutputs_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_177_2) node _decoder_decoded_orMatrixOutputs_T_22 = cat(decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_6) node _decoder_decoded_orMatrixOutputs_T_23 = orr(_decoder_decoded_orMatrixOutputs_T_22) node decoder_decoded_orMatrixOutputs_hi_8 = cat(decoder_decoded_andMatrixOutputs_137_2, decoder_decoded_andMatrixOutputs_64_2) node _decoder_decoded_orMatrixOutputs_T_24 = cat(decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_57_2) node _decoder_decoded_orMatrixOutputs_T_25 = orr(_decoder_decoded_orMatrixOutputs_T_24) node decoder_decoded_orMatrixOutputs_lo_7 = cat(decoder_decoded_andMatrixOutputs_82_2, decoder_decoded_andMatrixOutputs_171_2) node decoder_decoded_orMatrixOutputs_hi_9 = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_137_2) node _decoder_decoded_orMatrixOutputs_T_26 = cat(decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_7) node _decoder_decoded_orMatrixOutputs_T_27 = orr(_decoder_decoded_orMatrixOutputs_T_26) node _decoder_decoded_orMatrixOutputs_T_28 = orr(decoder_decoded_andMatrixOutputs_14_2) node _decoder_decoded_orMatrixOutputs_T_29 = orr(decoder_decoded_andMatrixOutputs_82_2) node decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_110_2) node decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_0_2) node decoder_decoded_orMatrixOutputs_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_5) node decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_140_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_101_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6) node _decoder_decoded_orMatrixOutputs_T_30 = cat(decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_8) node _decoder_decoded_orMatrixOutputs_T_31 = orr(_decoder_decoded_orMatrixOutputs_T_30) node decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_142_2, decoder_decoded_andMatrixOutputs_47_2) node decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_149_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_169_2, decoder_decoded_andMatrixOutputs_138_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_102_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_lo_3) node decoder_decoded_orMatrixOutputs_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_6) node decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_144_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_93_2, decoder_decoded_andMatrixOutputs_125_2) node decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_55_2, decoder_decoded_andMatrixOutputs_179_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_103_2) node decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_lo_4) node decoder_decoded_orMatrixOutputs_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7) node _decoder_decoded_orMatrixOutputs_T_32 = cat(decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_9) node _decoder_decoded_orMatrixOutputs_T_33 = orr(_decoder_decoded_orMatrixOutputs_T_32) node decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_63_2, decoder_decoded_andMatrixOutputs_142_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_138_2, decoder_decoded_andMatrixOutputs_174_2) node decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_lo_3) node decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_25_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_3_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_4_2) node decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_lo_4) node decoder_decoded_orMatrixOutputs_lo_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_7) node decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_164_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_170_2, decoder_decoded_andMatrixOutputs_36_2) node decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_4) node decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_111_2, decoder_decoded_andMatrixOutputs_172_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_39_2, decoder_decoded_andMatrixOutputs_115_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_163_2) node decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_5) node decoder_decoded_orMatrixOutputs_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8) node _decoder_decoded_orMatrixOutputs_T_34 = cat(decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_10) node _decoder_decoded_orMatrixOutputs_T_35 = orr(_decoder_decoded_orMatrixOutputs_T_34) node decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_41_2) node decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_8_2) node decoder_decoded_orMatrixOutputs_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_8) node decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_150_2, decoder_decoded_andMatrixOutputs_162_2) node decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_133_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_132_2) node decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_45_2) node decoder_decoded_orMatrixOutputs_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9) node _decoder_decoded_orMatrixOutputs_T_36 = cat(decoder_decoded_orMatrixOutputs_hi_13, decoder_decoded_orMatrixOutputs_lo_11) node _decoder_decoded_orMatrixOutputs_T_37 = orr(_decoder_decoded_orMatrixOutputs_T_36) node decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_53_2, decoder_decoded_andMatrixOutputs_183_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_147_2, decoder_decoded_andMatrixOutputs_178_2) node decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_19_2) node decoder_decoded_orMatrixOutputs_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_9) node decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_43_2, decoder_decoded_andMatrixOutputs_25_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_129_2, decoder_decoded_andMatrixOutputs_48_2) node decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_162_2) node decoder_decoded_orMatrixOutputs_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10) node _decoder_decoded_orMatrixOutputs_T_38 = cat(decoder_decoded_orMatrixOutputs_hi_14, decoder_decoded_orMatrixOutputs_lo_12) node _decoder_decoded_orMatrixOutputs_T_39 = orr(_decoder_decoded_orMatrixOutputs_T_38) node decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_173_2, decoder_decoded_andMatrixOutputs_37_2) node decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_106_2, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_104_2, decoder_decoded_andMatrixOutputs_186_2) node decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_5) node decoder_decoded_orMatrixOutputs_lo_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_10) node decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_42_2) node decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_27_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_43_2) node decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_hi_lo_6) node decoder_decoded_orMatrixOutputs_hi_15 = cat(decoder_decoded_orMatrixOutputs_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_11) node _decoder_decoded_orMatrixOutputs_T_40 = cat(decoder_decoded_orMatrixOutputs_hi_15, decoder_decoded_orMatrixOutputs_lo_13) node _decoder_decoded_orMatrixOutputs_T_41 = orr(_decoder_decoded_orMatrixOutputs_T_40) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_151_2, decoder_decoded_andMatrixOutputs_18_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_135_2, decoder_decoded_andMatrixOutputs_188_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_4) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_180_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_82_2, decoder_decoded_andMatrixOutputs_159_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_137_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_189_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_0_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_hi_lo_6) node decoder_decoded_orMatrixOutputs_lo_14 = cat(decoder_decoded_orMatrixOutputs_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_11) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_162_2, decoder_decoded_andMatrixOutputs_41_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_155_2, decoder_decoded_andMatrixOutputs_126_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_14_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_94_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_140_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_lo_5) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_165_2, decoder_decoded_andMatrixOutputs_30_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_131_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_77_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_hi_lo_7) node decoder_decoded_orMatrixOutputs_hi_16 = cat(decoder_decoded_orMatrixOutputs_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_12) node _decoder_decoded_orMatrixOutputs_T_42 = cat(decoder_decoded_orMatrixOutputs_hi_16, decoder_decoded_orMatrixOutputs_lo_14) node _decoder_decoded_orMatrixOutputs_T_43 = orr(_decoder_decoded_orMatrixOutputs_T_42) node decoder_decoded_orMatrixOutputs_lo_15 = cat(decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_146_2) node decoder_decoded_orMatrixOutputs_hi_17 = cat(decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_165_2) node _decoder_decoded_orMatrixOutputs_T_44 = cat(decoder_decoded_orMatrixOutputs_hi_17, decoder_decoded_orMatrixOutputs_lo_15) node _decoder_decoded_orMatrixOutputs_T_45 = orr(_decoder_decoded_orMatrixOutputs_T_44) node _decoder_decoded_orMatrixOutputs_T_46 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_165_2) node _decoder_decoded_orMatrixOutputs_T_47 = orr(_decoder_decoded_orMatrixOutputs_T_46) node decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_99_2, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_1_2) node decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_lo_5) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_120_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_180_2) node decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_lo_hi_lo_7) node decoder_decoded_orMatrixOutputs_lo_16 = cat(decoder_decoded_orMatrixOutputs_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_12) node decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_90_2, decoder_decoded_andMatrixOutputs_2_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_52_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_17_2) node decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_lo_6) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_191_2, decoder_decoded_andMatrixOutputs_26_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_60_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_95_2) node decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_lo_8) node decoder_decoded_orMatrixOutputs_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_13) node _decoder_decoded_orMatrixOutputs_T_48 = cat(decoder_decoded_orMatrixOutputs_hi_18, decoder_decoded_orMatrixOutputs_lo_16) node _decoder_decoded_orMatrixOutputs_T_49 = orr(_decoder_decoded_orMatrixOutputs_T_48) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_74_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_122_2, decoder_decoded_andMatrixOutputs_116_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_156_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_99_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2) node decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_lo_6) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_51_2, decoder_decoded_andMatrixOutputs_174_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_188_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_159_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_137_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2) node decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_lo_8) node decoder_decoded_orMatrixOutputs_lo_17 = cat(decoder_decoded_orMatrixOutputs_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_13) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_8_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_162_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_41_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_14_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_184_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_103_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_140_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2) node decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_lo_7) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_121_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_97_2, decoder_decoded_andMatrixOutputs_70_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_131_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_190_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_7_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2) node decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_hi_lo_9) node decoder_decoded_orMatrixOutputs_hi_19 = cat(decoder_decoded_orMatrixOutputs_hi_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_14) node _decoder_decoded_orMatrixOutputs_T_50 = cat(decoder_decoded_orMatrixOutputs_hi_19, decoder_decoded_orMatrixOutputs_lo_17) node _decoder_decoded_orMatrixOutputs_T_51 = orr(_decoder_decoded_orMatrixOutputs_T_50) node decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_159_2) node decoder_decoded_orMatrixOutputs_lo_18 = cat(decoder_decoded_orMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_182_2, decoder_decoded_andMatrixOutputs_165_2) node decoder_decoded_orMatrixOutputs_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_189_2) node _decoder_decoded_orMatrixOutputs_T_52 = cat(decoder_decoded_orMatrixOutputs_hi_20, decoder_decoded_orMatrixOutputs_lo_18) node _decoder_decoded_orMatrixOutputs_T_53 = orr(_decoder_decoded_orMatrixOutputs_T_52) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_99_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_120_2, decoder_decoded_andMatrixOutputs_42_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_lo_7) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_188_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_lo_9) node decoder_decoded_orMatrixOutputs_lo_19 = cat(decoder_decoded_orMatrixOutputs_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_14) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_140_2, decoder_decoded_andMatrixOutputs_17_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_90_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_60_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_24_2) node decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_lo_8) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_191_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_165_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_95_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3) node decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_lo_10) node decoder_decoded_orMatrixOutputs_hi_21 = cat(decoder_decoded_orMatrixOutputs_hi_hi_17, decoder_decoded_orMatrixOutputs_hi_lo_15) node _decoder_decoded_orMatrixOutputs_T_54 = cat(decoder_decoded_orMatrixOutputs_hi_21, decoder_decoded_orMatrixOutputs_lo_19) node _decoder_decoded_orMatrixOutputs_T_55 = orr(_decoder_decoded_orMatrixOutputs_T_54) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_88_2, decoder_decoded_andMatrixOutputs_122_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_99_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_142_2, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_138_2, decoder_decoded_andMatrixOutputs_174_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3) node decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_lo_8) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_159_2, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_146_2, decoder_decoded_andMatrixOutputs_41_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_8_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3) node decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_hi_lo_10) node decoder_decoded_orMatrixOutputs_lo_20 = cat(decoder_decoded_orMatrixOutputs_lo_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_15) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_65_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_140_2, decoder_decoded_andMatrixOutputs_17_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_103_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_131_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_30_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3) node decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_lo_9) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_97_2, decoder_decoded_andMatrixOutputs_70_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_190_2, decoder_decoded_andMatrixOutputs_7_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_35_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4) node decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_15, decoder_decoded_orMatrixOutputs_hi_hi_lo_11) node decoder_decoded_orMatrixOutputs_hi_22 = cat(decoder_decoded_orMatrixOutputs_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_16) node _decoder_decoded_orMatrixOutputs_T_56 = cat(decoder_decoded_orMatrixOutputs_hi_22, decoder_decoded_orMatrixOutputs_lo_20) node _decoder_decoded_orMatrixOutputs_T_57 = orr(_decoder_decoded_orMatrixOutputs_T_56) node decoder_decoded_orMatrixOutputs_lo_21 = cat(decoder_decoded_andMatrixOutputs_67_2, decoder_decoded_andMatrixOutputs_62_2) node decoder_decoded_orMatrixOutputs_hi_23 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node _decoder_decoded_orMatrixOutputs_T_58 = cat(decoder_decoded_orMatrixOutputs_hi_23, decoder_decoded_orMatrixOutputs_lo_21) node _decoder_decoded_orMatrixOutputs_T_59 = orr(_decoder_decoded_orMatrixOutputs_T_58) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_74_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_122_2, decoder_decoded_andMatrixOutputs_116_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_156_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_99_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_151_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4) node decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_lo_9) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_51_2, decoder_decoded_andMatrixOutputs_174_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_188_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_159_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_137_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4) node decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_15, decoder_decoded_orMatrixOutputs_lo_hi_lo_11) node decoder_decoded_orMatrixOutputs_lo_22 = cat(decoder_decoded_orMatrixOutputs_lo_hi_18, decoder_decoded_orMatrixOutputs_lo_lo_16) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_8_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_162_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_41_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_14_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_184_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_103_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_140_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4) node decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_lo_10) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_121_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_97_2, decoder_decoded_andMatrixOutputs_70_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_131_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_190_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_7_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5) node decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_16, decoder_decoded_orMatrixOutputs_hi_hi_lo_12) node decoder_decoded_orMatrixOutputs_hi_24 = cat(decoder_decoded_orMatrixOutputs_hi_hi_19, decoder_decoded_orMatrixOutputs_hi_lo_17) node _decoder_decoded_orMatrixOutputs_T_60 = cat(decoder_decoded_orMatrixOutputs_hi_24, decoder_decoded_orMatrixOutputs_lo_22) node _decoder_decoded_orMatrixOutputs_T_61 = orr(_decoder_decoded_orMatrixOutputs_T_60) node decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_159_2, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_lo_17 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_lo_10) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_137_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_13_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_8_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_lo_hi_lo_12) node decoder_decoded_orMatrixOutputs_lo_23 = cat(decoder_decoded_orMatrixOutputs_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_lo_17) node decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_162_2, decoder_decoded_andMatrixOutputs_87_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_14_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_126_2) node decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_lo_11) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_97_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_32_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_128_2, decoder_decoded_andMatrixOutputs_66_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_190_2) node decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_17, decoder_decoded_orMatrixOutputs_hi_hi_lo_13) node decoder_decoded_orMatrixOutputs_hi_25 = cat(decoder_decoded_orMatrixOutputs_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_18) node _decoder_decoded_orMatrixOutputs_T_62 = cat(decoder_decoded_orMatrixOutputs_hi_25, decoder_decoded_orMatrixOutputs_lo_23) node _decoder_decoded_orMatrixOutputs_T_63 = orr(_decoder_decoded_orMatrixOutputs_T_62) node _decoder_decoded_orMatrixOutputs_T_64 = orr(decoder_decoded_andMatrixOutputs_191_2) node _decoder_decoded_orMatrixOutputs_T_65 = orr(decoder_decoded_andMatrixOutputs_165_2) node _decoder_decoded_orMatrixOutputs_T_66 = cat(decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_162_2) node _decoder_decoded_orMatrixOutputs_T_67 = orr(_decoder_decoded_orMatrixOutputs_T_66) node decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_158_2, decoder_decoded_andMatrixOutputs_109_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_136_2, decoder_decoded_andMatrixOutputs_192_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_38_2) node decoder_decoded_orMatrixOutputs_lo_lo_18 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_lo_lo_11) node decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_130_2, decoder_decoded_andMatrixOutputs_50_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_141_2, decoder_decoded_andMatrixOutputs_69_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_175_2) node decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_17, decoder_decoded_orMatrixOutputs_lo_hi_lo_13) node decoder_decoded_orMatrixOutputs_lo_24 = cat(decoder_decoded_orMatrixOutputs_lo_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_18) node decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_153_2, decoder_decoded_andMatrixOutputs_107_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_6_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_134_2) node decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_hi_lo_lo_12) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_176_2, decoder_decoded_andMatrixOutputs_193_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_124_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_181_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_hi_hi_21 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_hi_lo_14) node decoder_decoded_orMatrixOutputs_hi_26 = cat(decoder_decoded_orMatrixOutputs_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_19) node _decoder_decoded_orMatrixOutputs_T_68 = cat(decoder_decoded_orMatrixOutputs_hi_26, decoder_decoded_orMatrixOutputs_lo_24) node _decoder_decoded_orMatrixOutputs_T_69 = orr(_decoder_decoded_orMatrixOutputs_T_68) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_83_2, decoder_decoded_andMatrixOutputs_33_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_113_2, decoder_decoded_andMatrixOutputs_105_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_158_2, decoder_decoded_andMatrixOutputs_109_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_122_2, decoder_decoded_andMatrixOutputs_119_2) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_106_2, decoder_decoded_andMatrixOutputs_88_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_104_2, decoder_decoded_andMatrixOutputs_186_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_136_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_130_2, decoder_decoded_andMatrixOutputs_42_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5) node decoder_decoded_orMatrixOutputs_lo_lo_19 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_lo_12) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_175_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_174_2, decoder_decoded_andMatrixOutputs_141_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_159_2, decoder_decoded_andMatrixOutputs_34_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_153_2, decoder_decoded_andMatrixOutputs_107_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_134_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_110_2, decoder_decoded_andMatrixOutputs_124_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_49_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5) node decoder_decoded_orMatrixOutputs_lo_hi_21 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_lo_14) node decoder_decoded_orMatrixOutputs_lo_25 = cat(decoder_decoded_orMatrixOutputs_lo_hi_21, decoder_decoded_orMatrixOutputs_lo_lo_19) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_152_2, decoder_decoded_andMatrixOutputs_112_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_73_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_0_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_8_2) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_162_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_155_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_140_2, decoder_decoded_andMatrixOutputs_17_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_103_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_94_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5) node decoder_decoded_orMatrixOutputs_hi_lo_20 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_17, decoder_decoded_orMatrixOutputs_hi_lo_lo_13) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_89_2, decoder_decoded_andMatrixOutputs_30_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_131_2, decoder_decoded_andMatrixOutputs_165_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_20_2, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_145_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_143_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_97_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_190_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_117_2, decoder_decoded_andMatrixOutputs_95_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6) node decoder_decoded_orMatrixOutputs_hi_hi_22 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_19, decoder_decoded_orMatrixOutputs_hi_hi_lo_15) node decoder_decoded_orMatrixOutputs_hi_27 = cat(decoder_decoded_orMatrixOutputs_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_lo_20) node _decoder_decoded_orMatrixOutputs_T_70 = cat(decoder_decoded_orMatrixOutputs_hi_27, decoder_decoded_orMatrixOutputs_lo_25) node _decoder_decoded_orMatrixOutputs_T_71 = orr(_decoder_decoded_orMatrixOutputs_T_70) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_6, _decoder_decoded_orMatrixOutputs_T_5) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_4) node decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = cat(_decoder_decoded_orMatrixOutputs_T_14, _decoder_decoded_orMatrixOutputs_T_12) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _decoder_decoded_orMatrixOutputs_T_11) node decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6) node decoder_decoded_orMatrixOutputs_lo_lo_20 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_lo_13) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_17, _decoder_decoded_orMatrixOutputs_T_16) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_23, _decoder_decoded_orMatrixOutputs_T_21) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_19) node decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_27) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _decoder_decoded_orMatrixOutputs_T_25) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = cat(_decoder_decoded_orMatrixOutputs_T_33, _decoder_decoded_orMatrixOutputs_T_31) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _decoder_decoded_orMatrixOutputs_T_29) node decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6) node decoder_decoded_orMatrixOutputs_lo_hi_22 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_19, decoder_decoded_orMatrixOutputs_lo_hi_lo_15) node decoder_decoded_orMatrixOutputs_lo_26 = cat(decoder_decoded_orMatrixOutputs_lo_hi_22, decoder_decoded_orMatrixOutputs_lo_lo_20) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_37, _decoder_decoded_orMatrixOutputs_T_35) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_43, _decoder_decoded_orMatrixOutputs_T_41) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_39) node decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_47, _decoder_decoded_orMatrixOutputs_T_45) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = cat(_decoder_decoded_orMatrixOutputs_T_53, _decoder_decoded_orMatrixOutputs_T_51) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _decoder_decoded_orMatrixOutputs_T_49) node decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6) node decoder_decoded_orMatrixOutputs_hi_lo_21 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_lo_14) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = cat(_decoder_decoded_orMatrixOutputs_T_57, _decoder_decoded_orMatrixOutputs_T_55) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_63, _decoder_decoded_orMatrixOutputs_T_61) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_59) node decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = cat(_decoder_decoded_orMatrixOutputs_T_67, _decoder_decoded_orMatrixOutputs_T_65) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _decoder_decoded_orMatrixOutputs_T_64) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = cat(_decoder_decoded_orMatrixOutputs_T_71, _decoder_decoded_orMatrixOutputs_T_69) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, UInt<1>(0h0)) node decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7) node decoder_decoded_orMatrixOutputs_hi_hi_23 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_lo_16) node decoder_decoded_orMatrixOutputs_hi_28 = cat(decoder_decoded_orMatrixOutputs_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_lo_21) node decoder_decoded_orMatrixOutputs = cat(decoder_decoded_orMatrixOutputs_hi_28, decoder_decoded_orMatrixOutputs_lo_26) node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0) node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1) node _decoder_decoded_invMatrixOutputs_T_2 = bits(decoder_decoded_orMatrixOutputs, 2, 2) node _decoder_decoded_invMatrixOutputs_T_3 = bits(decoder_decoded_orMatrixOutputs, 3, 3) node _decoder_decoded_invMatrixOutputs_T_4 = bits(decoder_decoded_orMatrixOutputs, 4, 4) node _decoder_decoded_invMatrixOutputs_T_5 = bits(decoder_decoded_orMatrixOutputs, 5, 5) node _decoder_decoded_invMatrixOutputs_T_6 = bits(decoder_decoded_orMatrixOutputs, 6, 6) node _decoder_decoded_invMatrixOutputs_T_7 = bits(decoder_decoded_orMatrixOutputs, 7, 7) node _decoder_decoded_invMatrixOutputs_T_8 = bits(decoder_decoded_orMatrixOutputs, 8, 8) node _decoder_decoded_invMatrixOutputs_T_9 = bits(decoder_decoded_orMatrixOutputs, 9, 9) node _decoder_decoded_invMatrixOutputs_T_10 = bits(decoder_decoded_orMatrixOutputs, 10, 10) node _decoder_decoded_invMatrixOutputs_T_11 = bits(decoder_decoded_orMatrixOutputs, 11, 11) node _decoder_decoded_invMatrixOutputs_T_12 = bits(decoder_decoded_orMatrixOutputs, 12, 12) node _decoder_decoded_invMatrixOutputs_T_13 = bits(decoder_decoded_orMatrixOutputs, 13, 13) node _decoder_decoded_invMatrixOutputs_T_14 = bits(decoder_decoded_orMatrixOutputs, 14, 14) node _decoder_decoded_invMatrixOutputs_T_15 = bits(decoder_decoded_orMatrixOutputs, 15, 15) node _decoder_decoded_invMatrixOutputs_T_16 = bits(decoder_decoded_orMatrixOutputs, 16, 16) node _decoder_decoded_invMatrixOutputs_T_17 = bits(decoder_decoded_orMatrixOutputs, 17, 17) node _decoder_decoded_invMatrixOutputs_T_18 = bits(decoder_decoded_orMatrixOutputs, 18, 18) node _decoder_decoded_invMatrixOutputs_T_19 = bits(decoder_decoded_orMatrixOutputs, 19, 19) node _decoder_decoded_invMatrixOutputs_T_20 = bits(decoder_decoded_orMatrixOutputs, 20, 20) node _decoder_decoded_invMatrixOutputs_T_21 = bits(decoder_decoded_orMatrixOutputs, 21, 21) node _decoder_decoded_invMatrixOutputs_T_22 = bits(decoder_decoded_orMatrixOutputs, 22, 22) node _decoder_decoded_invMatrixOutputs_T_23 = bits(decoder_decoded_orMatrixOutputs, 23, 23) node _decoder_decoded_invMatrixOutputs_T_24 = bits(decoder_decoded_orMatrixOutputs, 24, 24) node _decoder_decoded_invMatrixOutputs_T_25 = bits(decoder_decoded_orMatrixOutputs, 25, 25) node _decoder_decoded_invMatrixOutputs_T_26 = bits(decoder_decoded_orMatrixOutputs, 26, 26) node _decoder_decoded_invMatrixOutputs_T_27 = bits(decoder_decoded_orMatrixOutputs, 27, 27) node _decoder_decoded_invMatrixOutputs_T_28 = bits(decoder_decoded_orMatrixOutputs, 28, 28) node _decoder_decoded_invMatrixOutputs_T_29 = bits(decoder_decoded_orMatrixOutputs, 29, 29) node _decoder_decoded_invMatrixOutputs_T_30 = bits(decoder_decoded_orMatrixOutputs, 30, 30) node _decoder_decoded_invMatrixOutputs_T_31 = bits(decoder_decoded_orMatrixOutputs, 31, 31) node _decoder_decoded_invMatrixOutputs_T_32 = bits(decoder_decoded_orMatrixOutputs, 32, 32) node _decoder_decoded_invMatrixOutputs_T_33 = bits(decoder_decoded_orMatrixOutputs, 33, 33) node _decoder_decoded_invMatrixOutputs_T_34 = bits(decoder_decoded_orMatrixOutputs, 34, 34) node _decoder_decoded_invMatrixOutputs_T_35 = bits(decoder_decoded_orMatrixOutputs, 35, 35) node _decoder_decoded_invMatrixOutputs_T_36 = bits(decoder_decoded_orMatrixOutputs, 36, 36) node _decoder_decoded_invMatrixOutputs_T_37 = bits(decoder_decoded_orMatrixOutputs, 37, 37) node _decoder_decoded_invMatrixOutputs_T_38 = bits(decoder_decoded_orMatrixOutputs, 38, 38) node _decoder_decoded_invMatrixOutputs_T_39 = bits(decoder_decoded_orMatrixOutputs, 39, 39) node _decoder_decoded_invMatrixOutputs_T_40 = bits(decoder_decoded_orMatrixOutputs, 40, 40) node _decoder_decoded_invMatrixOutputs_T_41 = bits(decoder_decoded_orMatrixOutputs, 41, 41) node decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T) node decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_4, _decoder_decoded_invMatrixOutputs_T_3) node decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_2) node decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_6, _decoder_decoded_invMatrixOutputs_T_5) node decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_9, _decoder_decoded_invMatrixOutputs_T_8) node decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_7) node decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoder_decoded_invMatrixOutputs_lo_lo = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo) node decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_11, _decoder_decoded_invMatrixOutputs_T_10) node decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_14, _decoder_decoded_invMatrixOutputs_T_13) node decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_12) node decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_decoder_decoded_invMatrixOutputs_T_17, _decoder_decoded_invMatrixOutputs_T_16) node decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _decoder_decoded_invMatrixOutputs_T_15) node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_20, _decoder_decoded_invMatrixOutputs_T_19) node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_18) node decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoder_decoded_invMatrixOutputs_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo) node decoder_decoded_invMatrixOutputs_lo = cat(decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo) node decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_22, _decoder_decoded_invMatrixOutputs_T_21) node decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_25, _decoder_decoded_invMatrixOutputs_T_24) node decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_23) node decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_27, _decoder_decoded_invMatrixOutputs_T_26) node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_30, _decoder_decoded_invMatrixOutputs_T_29) node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_28) node decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoder_decoded_invMatrixOutputs_hi_lo = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo) node decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_32, _decoder_decoded_invMatrixOutputs_T_31) node decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_35, _decoder_decoded_invMatrixOutputs_T_34) node decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_33) node decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_decoder_decoded_invMatrixOutputs_T_38, _decoder_decoded_invMatrixOutputs_T_37) node decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _decoder_decoded_invMatrixOutputs_T_36) node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_41, _decoder_decoded_invMatrixOutputs_T_40) node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_39) node decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoder_decoded_invMatrixOutputs_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo) node decoder_decoded_invMatrixOutputs_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo) node decoder_decoded_invMatrixOutputs = cat(decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo) connect decoder_decoded, decoder_decoded_invMatrixOutputs connect decoder_decoded_plaInput, io.imem.resp[0].bits.inst node decoder_0 = bits(decoder_decoded, 41, 41) node decoder_1 = bits(decoder_decoded, 40, 40) node decoder_2 = bits(decoder_decoded, 39, 39) node decoder_3 = bits(decoder_decoded, 38, 38) node decoder_4 = bits(decoder_decoded, 37, 37) node decoder_5 = bits(decoder_decoded, 36, 36) node decoder_6 = bits(decoder_decoded, 35, 35) node decoder_7 = bits(decoder_decoded, 34, 34) node decoder_8 = bits(decoder_decoded, 33, 31) node decoder_9 = bits(decoder_decoded, 30, 29) node decoder_10 = bits(decoder_decoded, 28, 26) node decoder_11 = bits(decoder_decoded, 25, 25) node decoder_12 = bits(decoder_decoded, 24, 20) node decoder_13 = bits(decoder_decoded, 19, 19) node decoder_14 = bits(decoder_decoded, 18, 14) node decoder_15 = bits(decoder_decoded, 13, 13) node decoder_16 = bits(decoder_decoded, 12, 12) node decoder_17 = bits(decoder_decoded, 11, 11) node decoder_18 = bits(decoder_decoded, 10, 10) node decoder_19 = bits(decoder_decoded, 9, 9) node decoder_20 = bits(decoder_decoded, 8, 8) node decoder_21 = bits(decoder_decoded, 7, 7) node decoder_22 = bits(decoder_decoded, 6, 4) node decoder_23 = bits(decoder_decoded, 3, 3) node decoder_24 = bits(decoder_decoded, 2, 2) node decoder_25 = bits(decoder_decoded, 1, 1) node decoder_26 = bits(decoder_decoded, 0, 0) connect rrd_uops[0].bits.ctrl.legal, decoder_0 connect rrd_uops[0].bits.ctrl.fp, decoder_1 connect rrd_uops[0].bits.ctrl.rocc, decoder_2 connect rrd_uops[0].bits.ctrl.branch, decoder_3 connect rrd_uops[0].bits.ctrl.jal, decoder_4 connect rrd_uops[0].bits.ctrl.jalr, decoder_5 connect rrd_uops[0].bits.ctrl.rxs2, decoder_6 connect rrd_uops[0].bits.ctrl.rxs1, decoder_7 connect rrd_uops[0].bits.ctrl.sel_alu2, decoder_8 connect rrd_uops[0].bits.ctrl.sel_alu1, decoder_9 connect rrd_uops[0].bits.ctrl.sel_imm, decoder_10 connect rrd_uops[0].bits.ctrl.alu_dw, decoder_11 connect rrd_uops[0].bits.ctrl.alu_fn, decoder_12 connect rrd_uops[0].bits.ctrl.mem, decoder_13 connect rrd_uops[0].bits.ctrl.mem_cmd, decoder_14 connect rrd_uops[0].bits.ctrl.rfs1, decoder_15 connect rrd_uops[0].bits.ctrl.rfs2, decoder_16 connect rrd_uops[0].bits.ctrl.rfs3, decoder_17 connect rrd_uops[0].bits.ctrl.wfd, decoder_18 connect rrd_uops[0].bits.ctrl.mul, decoder_19 connect rrd_uops[0].bits.ctrl.div, decoder_20 connect rrd_uops[0].bits.ctrl.wxd, decoder_21 connect rrd_uops[0].bits.ctrl.csr, decoder_22 connect rrd_uops[0].bits.ctrl.fence_i, decoder_23 connect rrd_uops[0].bits.ctrl.fence, decoder_24 connect rrd_uops[0].bits.ctrl.amo, decoder_25 connect rrd_uops[0].bits.ctrl.dp, decoder_26 inst rrd_uops_0_bits_fp_ctrl_fp_decoder of FPUDecoder connect rrd_uops_0_bits_fp_ctrl_fp_decoder.clock, clock connect rrd_uops_0_bits_fp_ctrl_fp_decoder.reset, reset connect rrd_uops_0_bits_fp_ctrl_fp_decoder.io.inst, io.imem.resp[0].bits.inst connect rrd_uops[0].bits.fp_ctrl, rrd_uops_0_bits_fp_ctrl_fp_decoder.io.sigs node _rrd_uops_0_bits_sets_vcfg_T = and(io.imem.resp[0].bits.inst, UInt<32>(0h8000707f)) node _rrd_uops_0_bits_sets_vcfg_T_1 = eq(UInt<15>(0h7057), _rrd_uops_0_bits_sets_vcfg_T) node _rrd_uops_0_bits_sets_vcfg_T_2 = and(io.imem.resp[0].bits.inst, UInt<32>(0hc000707f)) node _rrd_uops_0_bits_sets_vcfg_T_3 = eq(UInt<32>(0hc0007057), _rrd_uops_0_bits_sets_vcfg_T_2) node _rrd_uops_0_bits_sets_vcfg_T_4 = and(io.imem.resp[0].bits.inst, UInt<32>(0hfe00707f)) node _rrd_uops_0_bits_sets_vcfg_T_5 = eq(UInt<32>(0h80007057), _rrd_uops_0_bits_sets_vcfg_T_4) node _rrd_uops_0_bits_sets_vcfg_T_6 = or(_rrd_uops_0_bits_sets_vcfg_T_1, _rrd_uops_0_bits_sets_vcfg_T_3) node _rrd_uops_0_bits_sets_vcfg_T_7 = or(_rrd_uops_0_bits_sets_vcfg_T_6, _rrd_uops_0_bits_sets_vcfg_T_5) node _rrd_uops_0_bits_sets_vcfg_T_8 = and(_rrd_uops_0_bits_sets_vcfg_T_7, UInt<1>(0h0)) connect rrd_uops[0].bits.sets_vcfg, _rrd_uops_0_bits_sets_vcfg_T_8 wire decoder_decoded_plaInput_1 : UInt<32> node decoder_decoded_invInputs_1 = not(decoder_decoded_plaInput_1) wire decoder_decoded_1 : UInt<42> node decoder_decoded_andMatrixOutputs_andMatrixInput_0_194 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_194 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_194 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_194 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_194 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_193 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_190 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_lo_hi_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_194, decoder_decoded_andMatrixOutputs_andMatrixInput_5_193) node decoder_decoded_andMatrixOutputs_lo_194 = cat(decoder_decoded_andMatrixOutputs_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_6_190) node decoder_decoded_andMatrixOutputs_hi_lo_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_194, decoder_decoded_andMatrixOutputs_andMatrixInput_3_194) node decoder_decoded_andMatrixOutputs_hi_hi_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_194, decoder_decoded_andMatrixOutputs_andMatrixInput_1_194) node decoder_decoded_andMatrixOutputs_hi_194 = cat(decoder_decoded_andMatrixOutputs_hi_hi_194, decoder_decoded_andMatrixOutputs_hi_lo_190) node _decoder_decoded_andMatrixOutputs_T_194 = cat(decoder_decoded_andMatrixOutputs_hi_194, decoder_decoded_andMatrixOutputs_lo_194) node decoder_decoded_andMatrixOutputs_98_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_194) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_195 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_195 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_195 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_195 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_195 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_194 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_191 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_183 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_lo_lo_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_191, decoder_decoded_andMatrixOutputs_andMatrixInput_7_183) node decoder_decoded_andMatrixOutputs_lo_hi_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_195, decoder_decoded_andMatrixOutputs_andMatrixInput_5_194) node decoder_decoded_andMatrixOutputs_lo_195 = cat(decoder_decoded_andMatrixOutputs_lo_hi_194, decoder_decoded_andMatrixOutputs_lo_lo_183) node decoder_decoded_andMatrixOutputs_hi_lo_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_195, decoder_decoded_andMatrixOutputs_andMatrixInput_3_195) node decoder_decoded_andMatrixOutputs_hi_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_195, decoder_decoded_andMatrixOutputs_andMatrixInput_1_195) node decoder_decoded_andMatrixOutputs_hi_195 = cat(decoder_decoded_andMatrixOutputs_hi_hi_195, decoder_decoded_andMatrixOutputs_hi_lo_191) node _decoder_decoded_andMatrixOutputs_T_195 = cat(decoder_decoded_andMatrixOutputs_hi_195, decoder_decoded_andMatrixOutputs_lo_195) node decoder_decoded_andMatrixOutputs_101_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_195) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_196 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_196 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_196 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_196 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_196 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_195 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_192 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_184 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_192, decoder_decoded_andMatrixOutputs_andMatrixInput_7_184) node decoder_decoded_andMatrixOutputs_lo_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_196, decoder_decoded_andMatrixOutputs_andMatrixInput_5_195) node decoder_decoded_andMatrixOutputs_lo_196 = cat(decoder_decoded_andMatrixOutputs_lo_hi_195, decoder_decoded_andMatrixOutputs_lo_lo_184) node decoder_decoded_andMatrixOutputs_hi_lo_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_196, decoder_decoded_andMatrixOutputs_andMatrixInput_3_196) node decoder_decoded_andMatrixOutputs_hi_hi_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_196, decoder_decoded_andMatrixOutputs_andMatrixInput_1_196) node decoder_decoded_andMatrixOutputs_hi_196 = cat(decoder_decoded_andMatrixOutputs_hi_hi_196, decoder_decoded_andMatrixOutputs_hi_lo_192) node _decoder_decoded_andMatrixOutputs_T_196 = cat(decoder_decoded_andMatrixOutputs_hi_196, decoder_decoded_andMatrixOutputs_lo_196) node decoder_decoded_andMatrixOutputs_9_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_196) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_197 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_197 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_197 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_197 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_197 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_196 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_193 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_197, decoder_decoded_andMatrixOutputs_andMatrixInput_5_196) node decoder_decoded_andMatrixOutputs_lo_197 = cat(decoder_decoded_andMatrixOutputs_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_6_193) node decoder_decoded_andMatrixOutputs_hi_lo_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_197, decoder_decoded_andMatrixOutputs_andMatrixInput_3_197) node decoder_decoded_andMatrixOutputs_hi_hi_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_197, decoder_decoded_andMatrixOutputs_andMatrixInput_1_197) node decoder_decoded_andMatrixOutputs_hi_197 = cat(decoder_decoded_andMatrixOutputs_hi_hi_197, decoder_decoded_andMatrixOutputs_hi_lo_193) node _decoder_decoded_andMatrixOutputs_T_197 = cat(decoder_decoded_andMatrixOutputs_hi_197, decoder_decoded_andMatrixOutputs_lo_197) node decoder_decoded_andMatrixOutputs_29_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_197) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_198 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_198 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_198 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_198 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_198 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_197 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_194 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_185 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_185 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_194, decoder_decoded_andMatrixOutputs_andMatrixInput_7_185) node decoder_decoded_andMatrixOutputs_lo_hi_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_198, decoder_decoded_andMatrixOutputs_andMatrixInput_5_197) node decoder_decoded_andMatrixOutputs_lo_198 = cat(decoder_decoded_andMatrixOutputs_lo_hi_197, decoder_decoded_andMatrixOutputs_lo_lo_185) node decoder_decoded_andMatrixOutputs_hi_lo_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_198, decoder_decoded_andMatrixOutputs_andMatrixInput_3_198) node decoder_decoded_andMatrixOutputs_hi_hi_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_198, decoder_decoded_andMatrixOutputs_andMatrixInput_1_198) node decoder_decoded_andMatrixOutputs_hi_198 = cat(decoder_decoded_andMatrixOutputs_hi_hi_198, decoder_decoded_andMatrixOutputs_hi_lo_194) node _decoder_decoded_andMatrixOutputs_T_198 = cat(decoder_decoded_andMatrixOutputs_hi_198, decoder_decoded_andMatrixOutputs_lo_198) node decoder_decoded_andMatrixOutputs_139_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_198) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_199 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_199 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_199 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_199 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_199 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_198 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_195 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_186 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_164 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_186, decoder_decoded_andMatrixOutputs_andMatrixInput_8_164) node decoder_decoded_andMatrixOutputs_lo_hi_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_198, decoder_decoded_andMatrixOutputs_andMatrixInput_6_195) node decoder_decoded_andMatrixOutputs_lo_199 = cat(decoder_decoded_andMatrixOutputs_lo_hi_198, decoder_decoded_andMatrixOutputs_lo_lo_186) node decoder_decoded_andMatrixOutputs_hi_lo_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_199, decoder_decoded_andMatrixOutputs_andMatrixInput_4_199) node decoder_decoded_andMatrixOutputs_hi_hi_hi_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_199, decoder_decoded_andMatrixOutputs_andMatrixInput_1_199) node decoder_decoded_andMatrixOutputs_hi_hi_199 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_164, decoder_decoded_andMatrixOutputs_andMatrixInput_2_199) node decoder_decoded_andMatrixOutputs_hi_199 = cat(decoder_decoded_andMatrixOutputs_hi_hi_199, decoder_decoded_andMatrixOutputs_hi_lo_195) node _decoder_decoded_andMatrixOutputs_T_199 = cat(decoder_decoded_andMatrixOutputs_hi_199, decoder_decoded_andMatrixOutputs_lo_199) node decoder_decoded_andMatrixOutputs_117_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_199) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_200 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_200 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_200 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_200 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_200 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_199 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_196 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_187 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_165 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_187, decoder_decoded_andMatrixOutputs_andMatrixInput_8_165) node decoder_decoded_andMatrixOutputs_lo_hi_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_199, decoder_decoded_andMatrixOutputs_andMatrixInput_6_196) node decoder_decoded_andMatrixOutputs_lo_200 = cat(decoder_decoded_andMatrixOutputs_lo_hi_199, decoder_decoded_andMatrixOutputs_lo_lo_187) node decoder_decoded_andMatrixOutputs_hi_lo_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_200, decoder_decoded_andMatrixOutputs_andMatrixInput_4_200) node decoder_decoded_andMatrixOutputs_hi_hi_hi_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_200, decoder_decoded_andMatrixOutputs_andMatrixInput_1_200) node decoder_decoded_andMatrixOutputs_hi_hi_200 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_165, decoder_decoded_andMatrixOutputs_andMatrixInput_2_200) node decoder_decoded_andMatrixOutputs_hi_200 = cat(decoder_decoded_andMatrixOutputs_hi_hi_200, decoder_decoded_andMatrixOutputs_hi_lo_196) node _decoder_decoded_andMatrixOutputs_T_200 = cat(decoder_decoded_andMatrixOutputs_hi_200, decoder_decoded_andMatrixOutputs_lo_200) node decoder_decoded_andMatrixOutputs_95_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_200) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_201 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_201 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_201 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_201 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_201 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_200 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_201, decoder_decoded_andMatrixOutputs_andMatrixInput_4_201) node decoder_decoded_andMatrixOutputs_lo_201 = cat(decoder_decoded_andMatrixOutputs_lo_hi_200, decoder_decoded_andMatrixOutputs_andMatrixInput_5_200) node decoder_decoded_andMatrixOutputs_hi_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_201, decoder_decoded_andMatrixOutputs_andMatrixInput_1_201) node decoder_decoded_andMatrixOutputs_hi_201 = cat(decoder_decoded_andMatrixOutputs_hi_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_2_201) node _decoder_decoded_andMatrixOutputs_T_201 = cat(decoder_decoded_andMatrixOutputs_hi_201, decoder_decoded_andMatrixOutputs_lo_201) node decoder_decoded_andMatrixOutputs_35_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_201) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_202 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_202 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_202 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_202 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_202 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_201 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_197 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_202, decoder_decoded_andMatrixOutputs_andMatrixInput_5_201) node decoder_decoded_andMatrixOutputs_lo_202 = cat(decoder_decoded_andMatrixOutputs_lo_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_6_197) node decoder_decoded_andMatrixOutputs_hi_lo_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_202, decoder_decoded_andMatrixOutputs_andMatrixInput_3_202) node decoder_decoded_andMatrixOutputs_hi_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_202, decoder_decoded_andMatrixOutputs_andMatrixInput_1_202) node decoder_decoded_andMatrixOutputs_hi_202 = cat(decoder_decoded_andMatrixOutputs_hi_hi_202, decoder_decoded_andMatrixOutputs_hi_lo_197) node _decoder_decoded_andMatrixOutputs_T_202 = cat(decoder_decoded_andMatrixOutputs_hi_202, decoder_decoded_andMatrixOutputs_lo_202) node decoder_decoded_andMatrixOutputs_182_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_202) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_203 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_203 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_203 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_203 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_203 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_202 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_198 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_188 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_198, decoder_decoded_andMatrixOutputs_andMatrixInput_7_188) node decoder_decoded_andMatrixOutputs_lo_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_203, decoder_decoded_andMatrixOutputs_andMatrixInput_5_202) node decoder_decoded_andMatrixOutputs_lo_203 = cat(decoder_decoded_andMatrixOutputs_lo_hi_202, decoder_decoded_andMatrixOutputs_lo_lo_188) node decoder_decoded_andMatrixOutputs_hi_lo_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_203, decoder_decoded_andMatrixOutputs_andMatrixInput_3_203) node decoder_decoded_andMatrixOutputs_hi_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_203, decoder_decoded_andMatrixOutputs_andMatrixInput_1_203) node decoder_decoded_andMatrixOutputs_hi_203 = cat(decoder_decoded_andMatrixOutputs_hi_hi_203, decoder_decoded_andMatrixOutputs_hi_lo_198) node _decoder_decoded_andMatrixOutputs_T_203 = cat(decoder_decoded_andMatrixOutputs_hi_203, decoder_decoded_andMatrixOutputs_lo_203) node decoder_decoded_andMatrixOutputs_128_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_203) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_204 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_204 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_204 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_204 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_204 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_203 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_199 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_189 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_199, decoder_decoded_andMatrixOutputs_andMatrixInput_7_189) node decoder_decoded_andMatrixOutputs_lo_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_204, decoder_decoded_andMatrixOutputs_andMatrixInput_5_203) node decoder_decoded_andMatrixOutputs_lo_204 = cat(decoder_decoded_andMatrixOutputs_lo_hi_203, decoder_decoded_andMatrixOutputs_lo_lo_189) node decoder_decoded_andMatrixOutputs_hi_lo_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_204, decoder_decoded_andMatrixOutputs_andMatrixInput_3_204) node decoder_decoded_andMatrixOutputs_hi_hi_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_204, decoder_decoded_andMatrixOutputs_andMatrixInput_1_204) node decoder_decoded_andMatrixOutputs_hi_204 = cat(decoder_decoded_andMatrixOutputs_hi_hi_204, decoder_decoded_andMatrixOutputs_hi_lo_199) node _decoder_decoded_andMatrixOutputs_T_204 = cat(decoder_decoded_andMatrixOutputs_hi_204, decoder_decoded_andMatrixOutputs_lo_204) node decoder_decoded_andMatrixOutputs_66_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_204) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_205 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_205 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_205 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_205 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_205 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_204 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_200 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_190 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_166 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_138 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_134 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_132 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_120 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_138 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_134, decoder_decoded_andMatrixOutputs_andMatrixInput_13_132) node decoder_decoded_andMatrixOutputs_lo_lo_190 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_138, decoder_decoded_andMatrixOutputs_andMatrixInput_14_120) node decoder_decoded_andMatrixOutputs_lo_hi_lo_132 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_141, decoder_decoded_andMatrixOutputs_andMatrixInput_11_138) node decoder_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_166, decoder_decoded_andMatrixOutputs_andMatrixInput_9_144) node decoder_decoded_andMatrixOutputs_lo_hi_204 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_144, decoder_decoded_andMatrixOutputs_lo_hi_lo_132) node decoder_decoded_andMatrixOutputs_lo_205 = cat(decoder_decoded_andMatrixOutputs_lo_hi_204, decoder_decoded_andMatrixOutputs_lo_lo_190) node decoder_decoded_andMatrixOutputs_hi_lo_lo_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_200, decoder_decoded_andMatrixOutputs_andMatrixInput_7_190) node decoder_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_205, decoder_decoded_andMatrixOutputs_andMatrixInput_5_204) node decoder_decoded_andMatrixOutputs_hi_lo_200 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_141, decoder_decoded_andMatrixOutputs_hi_lo_lo_120) node decoder_decoded_andMatrixOutputs_hi_hi_lo_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_205, decoder_decoded_andMatrixOutputs_andMatrixInput_3_205) node decoder_decoded_andMatrixOutputs_hi_hi_hi_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_205, decoder_decoded_andMatrixOutputs_andMatrixInput_1_205) node decoder_decoded_andMatrixOutputs_hi_hi_205 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_166, decoder_decoded_andMatrixOutputs_hi_hi_lo_134) node decoder_decoded_andMatrixOutputs_hi_205 = cat(decoder_decoded_andMatrixOutputs_hi_hi_205, decoder_decoded_andMatrixOutputs_hi_lo_200) node _decoder_decoded_andMatrixOutputs_T_205 = cat(decoder_decoded_andMatrixOutputs_hi_205, decoder_decoded_andMatrixOutputs_lo_205) node decoder_decoded_andMatrixOutputs_77_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_205) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_206 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_206 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_206 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_206 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_206 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_205 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_201 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_191 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_167 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_139 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_135 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_133 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_121 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_139 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_135, decoder_decoded_andMatrixOutputs_andMatrixInput_13_133) node decoder_decoded_andMatrixOutputs_lo_lo_191 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_139, decoder_decoded_andMatrixOutputs_andMatrixInput_14_121) node decoder_decoded_andMatrixOutputs_lo_hi_lo_133 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_142, decoder_decoded_andMatrixOutputs_andMatrixInput_11_139) node decoder_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_167, decoder_decoded_andMatrixOutputs_andMatrixInput_9_145) node decoder_decoded_andMatrixOutputs_lo_hi_205 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_145, decoder_decoded_andMatrixOutputs_lo_hi_lo_133) node decoder_decoded_andMatrixOutputs_lo_206 = cat(decoder_decoded_andMatrixOutputs_lo_hi_205, decoder_decoded_andMatrixOutputs_lo_lo_191) node decoder_decoded_andMatrixOutputs_hi_lo_lo_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_201, decoder_decoded_andMatrixOutputs_andMatrixInput_7_191) node decoder_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_206, decoder_decoded_andMatrixOutputs_andMatrixInput_5_205) node decoder_decoded_andMatrixOutputs_hi_lo_201 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_142, decoder_decoded_andMatrixOutputs_hi_lo_lo_121) node decoder_decoded_andMatrixOutputs_hi_hi_lo_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_206, decoder_decoded_andMatrixOutputs_andMatrixInput_3_206) node decoder_decoded_andMatrixOutputs_hi_hi_hi_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_206, decoder_decoded_andMatrixOutputs_andMatrixInput_1_206) node decoder_decoded_andMatrixOutputs_hi_hi_206 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_167, decoder_decoded_andMatrixOutputs_hi_hi_lo_135) node decoder_decoded_andMatrixOutputs_hi_206 = cat(decoder_decoded_andMatrixOutputs_hi_hi_206, decoder_decoded_andMatrixOutputs_hi_lo_201) node _decoder_decoded_andMatrixOutputs_T_206 = cat(decoder_decoded_andMatrixOutputs_hi_206, decoder_decoded_andMatrixOutputs_lo_206) node decoder_decoded_andMatrixOutputs_190_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_206) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_207 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_207 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_207 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_207 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_207 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_206 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_202 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_192 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_168 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_146 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_143 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_140 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_136 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_140 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_143, decoder_decoded_andMatrixOutputs_andMatrixInput_11_140) node decoder_decoded_andMatrixOutputs_lo_lo_192 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_140, decoder_decoded_andMatrixOutputs_andMatrixInput_12_136) node decoder_decoded_andMatrixOutputs_lo_hi_hi_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_192, decoder_decoded_andMatrixOutputs_andMatrixInput_8_168) node decoder_decoded_andMatrixOutputs_lo_hi_206 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_146, decoder_decoded_andMatrixOutputs_andMatrixInput_9_146) node decoder_decoded_andMatrixOutputs_lo_207 = cat(decoder_decoded_andMatrixOutputs_lo_hi_206, decoder_decoded_andMatrixOutputs_lo_lo_192) node decoder_decoded_andMatrixOutputs_hi_lo_hi_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_207, decoder_decoded_andMatrixOutputs_andMatrixInput_5_206) node decoder_decoded_andMatrixOutputs_hi_lo_202 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_143, decoder_decoded_andMatrixOutputs_andMatrixInput_6_202) node decoder_decoded_andMatrixOutputs_hi_hi_lo_136 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_207, decoder_decoded_andMatrixOutputs_andMatrixInput_3_207) node decoder_decoded_andMatrixOutputs_hi_hi_hi_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_207, decoder_decoded_andMatrixOutputs_andMatrixInput_1_207) node decoder_decoded_andMatrixOutputs_hi_hi_207 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_168, decoder_decoded_andMatrixOutputs_hi_hi_lo_136) node decoder_decoded_andMatrixOutputs_hi_207 = cat(decoder_decoded_andMatrixOutputs_hi_hi_207, decoder_decoded_andMatrixOutputs_hi_lo_202) node _decoder_decoded_andMatrixOutputs_T_207 = cat(decoder_decoded_andMatrixOutputs_hi_207, decoder_decoded_andMatrixOutputs_lo_207) node decoder_decoded_andMatrixOutputs_7_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_207) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_208 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_208 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_208 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_208 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_208 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_207 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_203 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_193 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_169 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_147 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_144 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_141 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_137 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_134 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_122 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_141 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_137, decoder_decoded_andMatrixOutputs_andMatrixInput_13_134) node decoder_decoded_andMatrixOutputs_lo_lo_193 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_141, decoder_decoded_andMatrixOutputs_andMatrixInput_14_122) node decoder_decoded_andMatrixOutputs_lo_hi_lo_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_144, decoder_decoded_andMatrixOutputs_andMatrixInput_11_141) node decoder_decoded_andMatrixOutputs_lo_hi_hi_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_169, decoder_decoded_andMatrixOutputs_andMatrixInput_9_147) node decoder_decoded_andMatrixOutputs_lo_hi_207 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_147, decoder_decoded_andMatrixOutputs_lo_hi_lo_134) node decoder_decoded_andMatrixOutputs_lo_208 = cat(decoder_decoded_andMatrixOutputs_lo_hi_207, decoder_decoded_andMatrixOutputs_lo_lo_193) node decoder_decoded_andMatrixOutputs_hi_lo_lo_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_203, decoder_decoded_andMatrixOutputs_andMatrixInput_7_193) node decoder_decoded_andMatrixOutputs_hi_lo_hi_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_208, decoder_decoded_andMatrixOutputs_andMatrixInput_5_207) node decoder_decoded_andMatrixOutputs_hi_lo_203 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_144, decoder_decoded_andMatrixOutputs_hi_lo_lo_122) node decoder_decoded_andMatrixOutputs_hi_hi_lo_137 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_208, decoder_decoded_andMatrixOutputs_andMatrixInput_3_208) node decoder_decoded_andMatrixOutputs_hi_hi_hi_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_208, decoder_decoded_andMatrixOutputs_andMatrixInput_1_208) node decoder_decoded_andMatrixOutputs_hi_hi_208 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_169, decoder_decoded_andMatrixOutputs_hi_hi_lo_137) node decoder_decoded_andMatrixOutputs_hi_208 = cat(decoder_decoded_andMatrixOutputs_hi_hi_208, decoder_decoded_andMatrixOutputs_hi_lo_203) node _decoder_decoded_andMatrixOutputs_T_208 = cat(decoder_decoded_andMatrixOutputs_hi_208, decoder_decoded_andMatrixOutputs_lo_208) node decoder_decoded_andMatrixOutputs_97_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_208) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_209 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_209 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_209 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_209 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_209 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_208 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_204 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_194 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_170 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_148 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_145 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_142 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_138 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_135 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_123 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_138, decoder_decoded_andMatrixOutputs_andMatrixInput_13_135) node decoder_decoded_andMatrixOutputs_lo_lo_194 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_142, decoder_decoded_andMatrixOutputs_andMatrixInput_14_123) node decoder_decoded_andMatrixOutputs_lo_hi_lo_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_145, decoder_decoded_andMatrixOutputs_andMatrixInput_11_142) node decoder_decoded_andMatrixOutputs_lo_hi_hi_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_170, decoder_decoded_andMatrixOutputs_andMatrixInput_9_148) node decoder_decoded_andMatrixOutputs_lo_hi_208 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_148, decoder_decoded_andMatrixOutputs_lo_hi_lo_135) node decoder_decoded_andMatrixOutputs_lo_209 = cat(decoder_decoded_andMatrixOutputs_lo_hi_208, decoder_decoded_andMatrixOutputs_lo_lo_194) node decoder_decoded_andMatrixOutputs_hi_lo_lo_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_204, decoder_decoded_andMatrixOutputs_andMatrixInput_7_194) node decoder_decoded_andMatrixOutputs_hi_lo_hi_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_209, decoder_decoded_andMatrixOutputs_andMatrixInput_5_208) node decoder_decoded_andMatrixOutputs_hi_lo_204 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_145, decoder_decoded_andMatrixOutputs_hi_lo_lo_123) node decoder_decoded_andMatrixOutputs_hi_hi_lo_138 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_209, decoder_decoded_andMatrixOutputs_andMatrixInput_3_209) node decoder_decoded_andMatrixOutputs_hi_hi_hi_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_209, decoder_decoded_andMatrixOutputs_andMatrixInput_1_209) node decoder_decoded_andMatrixOutputs_hi_hi_209 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_170, decoder_decoded_andMatrixOutputs_hi_hi_lo_138) node decoder_decoded_andMatrixOutputs_hi_209 = cat(decoder_decoded_andMatrixOutputs_hi_hi_209, decoder_decoded_andMatrixOutputs_hi_lo_204) node _decoder_decoded_andMatrixOutputs_T_209 = cat(decoder_decoded_andMatrixOutputs_hi_209, decoder_decoded_andMatrixOutputs_lo_209) node decoder_decoded_andMatrixOutputs_32_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_209) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_210 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_210 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_210 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_210 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_210 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_209 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_205 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_195 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_171 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_149 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_146 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_143 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_139 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_136 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_124 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_79 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_124, decoder_decoded_andMatrixOutputs_andMatrixInput_15_79) node decoder_decoded_andMatrixOutputs_lo_lo_hi_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_139, decoder_decoded_andMatrixOutputs_andMatrixInput_13_136) node decoder_decoded_andMatrixOutputs_lo_lo_195 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_143, decoder_decoded_andMatrixOutputs_lo_lo_lo_79) node decoder_decoded_andMatrixOutputs_lo_hi_lo_136 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_146, decoder_decoded_andMatrixOutputs_andMatrixInput_11_143) node decoder_decoded_andMatrixOutputs_lo_hi_hi_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_171, decoder_decoded_andMatrixOutputs_andMatrixInput_9_149) node decoder_decoded_andMatrixOutputs_lo_hi_209 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_149, decoder_decoded_andMatrixOutputs_lo_hi_lo_136) node decoder_decoded_andMatrixOutputs_lo_210 = cat(decoder_decoded_andMatrixOutputs_lo_hi_209, decoder_decoded_andMatrixOutputs_lo_lo_195) node decoder_decoded_andMatrixOutputs_hi_lo_lo_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_205, decoder_decoded_andMatrixOutputs_andMatrixInput_7_195) node decoder_decoded_andMatrixOutputs_hi_lo_hi_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_210, decoder_decoded_andMatrixOutputs_andMatrixInput_5_209) node decoder_decoded_andMatrixOutputs_hi_lo_205 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_146, decoder_decoded_andMatrixOutputs_hi_lo_lo_124) node decoder_decoded_andMatrixOutputs_hi_hi_lo_139 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_210, decoder_decoded_andMatrixOutputs_andMatrixInput_3_210) node decoder_decoded_andMatrixOutputs_hi_hi_hi_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_210, decoder_decoded_andMatrixOutputs_andMatrixInput_1_210) node decoder_decoded_andMatrixOutputs_hi_hi_210 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_171, decoder_decoded_andMatrixOutputs_hi_hi_lo_139) node decoder_decoded_andMatrixOutputs_hi_210 = cat(decoder_decoded_andMatrixOutputs_hi_hi_210, decoder_decoded_andMatrixOutputs_hi_lo_205) node _decoder_decoded_andMatrixOutputs_T_210 = cat(decoder_decoded_andMatrixOutputs_hi_210, decoder_decoded_andMatrixOutputs_lo_210) node decoder_decoded_andMatrixOutputs_70_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_210) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_211 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_211 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_211 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_211 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_211 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_lo_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_211, decoder_decoded_andMatrixOutputs_andMatrixInput_4_211) node decoder_decoded_andMatrixOutputs_hi_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_211, decoder_decoded_andMatrixOutputs_andMatrixInput_1_211) node decoder_decoded_andMatrixOutputs_hi_211 = cat(decoder_decoded_andMatrixOutputs_hi_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_2_211) node _decoder_decoded_andMatrixOutputs_T_211 = cat(decoder_decoded_andMatrixOutputs_hi_211, decoder_decoded_andMatrixOutputs_lo_211) node decoder_decoded_andMatrixOutputs_181_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_211) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_212 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_212 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_212 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_212 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_212 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_210 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_lo_hi_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_212, decoder_decoded_andMatrixOutputs_andMatrixInput_4_212) node decoder_decoded_andMatrixOutputs_lo_212 = cat(decoder_decoded_andMatrixOutputs_lo_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_5_210) node decoder_decoded_andMatrixOutputs_hi_hi_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_212, decoder_decoded_andMatrixOutputs_andMatrixInput_1_212) node decoder_decoded_andMatrixOutputs_hi_212 = cat(decoder_decoded_andMatrixOutputs_hi_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_2_212) node _decoder_decoded_andMatrixOutputs_T_212 = cat(decoder_decoded_andMatrixOutputs_hi_212, decoder_decoded_andMatrixOutputs_lo_212) node decoder_decoded_andMatrixOutputs_145_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_212) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_213 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_213 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_213 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_213 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_213 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_211 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_213, decoder_decoded_andMatrixOutputs_andMatrixInput_4_213) node decoder_decoded_andMatrixOutputs_lo_213 = cat(decoder_decoded_andMatrixOutputs_lo_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_5_211) node decoder_decoded_andMatrixOutputs_hi_hi_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_213, decoder_decoded_andMatrixOutputs_andMatrixInput_1_213) node decoder_decoded_andMatrixOutputs_hi_213 = cat(decoder_decoded_andMatrixOutputs_hi_hi_213, decoder_decoded_andMatrixOutputs_andMatrixInput_2_213) node _decoder_decoded_andMatrixOutputs_T_213 = cat(decoder_decoded_andMatrixOutputs_hi_213, decoder_decoded_andMatrixOutputs_lo_213) node decoder_decoded_andMatrixOutputs_143_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_213) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_214 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_214 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_214 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_214 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_214 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_212 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_206 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_196 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_172 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_150 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_147 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_150, decoder_decoded_andMatrixOutputs_andMatrixInput_10_147) node decoder_decoded_andMatrixOutputs_lo_hi_hi_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_206, decoder_decoded_andMatrixOutputs_andMatrixInput_7_196) node decoder_decoded_andMatrixOutputs_lo_hi_212 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_150, decoder_decoded_andMatrixOutputs_andMatrixInput_8_172) node decoder_decoded_andMatrixOutputs_lo_214 = cat(decoder_decoded_andMatrixOutputs_lo_hi_212, decoder_decoded_andMatrixOutputs_lo_lo_196) node decoder_decoded_andMatrixOutputs_hi_lo_hi_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_214, decoder_decoded_andMatrixOutputs_andMatrixInput_4_214) node decoder_decoded_andMatrixOutputs_hi_lo_206 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_147, decoder_decoded_andMatrixOutputs_andMatrixInput_5_212) node decoder_decoded_andMatrixOutputs_hi_hi_hi_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_214, decoder_decoded_andMatrixOutputs_andMatrixInput_1_214) node decoder_decoded_andMatrixOutputs_hi_hi_214 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_2_214) node decoder_decoded_andMatrixOutputs_hi_214 = cat(decoder_decoded_andMatrixOutputs_hi_hi_214, decoder_decoded_andMatrixOutputs_hi_lo_206) node _decoder_decoded_andMatrixOutputs_T_214 = cat(decoder_decoded_andMatrixOutputs_hi_214, decoder_decoded_andMatrixOutputs_lo_214) node decoder_decoded_andMatrixOutputs_20_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_214) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_215 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_215 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_215 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_215 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_215 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_213 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_207 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_197 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_173 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_151 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_148 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_151, decoder_decoded_andMatrixOutputs_andMatrixInput_10_148) node decoder_decoded_andMatrixOutputs_lo_hi_hi_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_207, decoder_decoded_andMatrixOutputs_andMatrixInput_7_197) node decoder_decoded_andMatrixOutputs_lo_hi_213 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_151, decoder_decoded_andMatrixOutputs_andMatrixInput_8_173) node decoder_decoded_andMatrixOutputs_lo_215 = cat(decoder_decoded_andMatrixOutputs_lo_hi_213, decoder_decoded_andMatrixOutputs_lo_lo_197) node decoder_decoded_andMatrixOutputs_hi_lo_hi_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_215, decoder_decoded_andMatrixOutputs_andMatrixInput_4_215) node decoder_decoded_andMatrixOutputs_hi_lo_207 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_148, decoder_decoded_andMatrixOutputs_andMatrixInput_5_213) node decoder_decoded_andMatrixOutputs_hi_hi_hi_173 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_215, decoder_decoded_andMatrixOutputs_andMatrixInput_1_215) node decoder_decoded_andMatrixOutputs_hi_hi_215 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_173, decoder_decoded_andMatrixOutputs_andMatrixInput_2_215) node decoder_decoded_andMatrixOutputs_hi_215 = cat(decoder_decoded_andMatrixOutputs_hi_hi_215, decoder_decoded_andMatrixOutputs_hi_lo_207) node _decoder_decoded_andMatrixOutputs_T_215 = cat(decoder_decoded_andMatrixOutputs_hi_215, decoder_decoded_andMatrixOutputs_lo_215) node decoder_decoded_andMatrixOutputs_22_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_215) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_216 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_216 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_216 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_216 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_216 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_214 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_208 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_198 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_208, decoder_decoded_andMatrixOutputs_andMatrixInput_7_198) node decoder_decoded_andMatrixOutputs_lo_hi_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_216, decoder_decoded_andMatrixOutputs_andMatrixInput_5_214) node decoder_decoded_andMatrixOutputs_lo_216 = cat(decoder_decoded_andMatrixOutputs_lo_hi_214, decoder_decoded_andMatrixOutputs_lo_lo_198) node decoder_decoded_andMatrixOutputs_hi_lo_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_216, decoder_decoded_andMatrixOutputs_andMatrixInput_3_216) node decoder_decoded_andMatrixOutputs_hi_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_216, decoder_decoded_andMatrixOutputs_andMatrixInput_1_216) node decoder_decoded_andMatrixOutputs_hi_216 = cat(decoder_decoded_andMatrixOutputs_hi_hi_216, decoder_decoded_andMatrixOutputs_hi_lo_208) node _decoder_decoded_andMatrixOutputs_T_216 = cat(decoder_decoded_andMatrixOutputs_hi_216, decoder_decoded_andMatrixOutputs_lo_216) node decoder_decoded_andMatrixOutputs_96_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_216) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_217 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_217 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_217 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_217 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_217 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_215 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_209 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_199 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_174 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_199, decoder_decoded_andMatrixOutputs_andMatrixInput_8_174) node decoder_decoded_andMatrixOutputs_lo_hi_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_215, decoder_decoded_andMatrixOutputs_andMatrixInput_6_209) node decoder_decoded_andMatrixOutputs_lo_217 = cat(decoder_decoded_andMatrixOutputs_lo_hi_215, decoder_decoded_andMatrixOutputs_lo_lo_199) node decoder_decoded_andMatrixOutputs_hi_lo_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_217, decoder_decoded_andMatrixOutputs_andMatrixInput_4_217) node decoder_decoded_andMatrixOutputs_hi_hi_hi_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_217, decoder_decoded_andMatrixOutputs_andMatrixInput_1_217) node decoder_decoded_andMatrixOutputs_hi_hi_217 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_174, decoder_decoded_andMatrixOutputs_andMatrixInput_2_217) node decoder_decoded_andMatrixOutputs_hi_217 = cat(decoder_decoded_andMatrixOutputs_hi_hi_217, decoder_decoded_andMatrixOutputs_hi_lo_209) node _decoder_decoded_andMatrixOutputs_T_217 = cat(decoder_decoded_andMatrixOutputs_hi_217, decoder_decoded_andMatrixOutputs_lo_217) node decoder_decoded_andMatrixOutputs_39_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_217) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_218 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_218 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_218 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_218 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_218 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_216 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_210 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_200 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_175 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_200, decoder_decoded_andMatrixOutputs_andMatrixInput_8_175) node decoder_decoded_andMatrixOutputs_lo_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_216, decoder_decoded_andMatrixOutputs_andMatrixInput_6_210) node decoder_decoded_andMatrixOutputs_lo_218 = cat(decoder_decoded_andMatrixOutputs_lo_hi_216, decoder_decoded_andMatrixOutputs_lo_lo_200) node decoder_decoded_andMatrixOutputs_hi_lo_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_218, decoder_decoded_andMatrixOutputs_andMatrixInput_4_218) node decoder_decoded_andMatrixOutputs_hi_hi_hi_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_218, decoder_decoded_andMatrixOutputs_andMatrixInput_1_218) node decoder_decoded_andMatrixOutputs_hi_hi_218 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_175, decoder_decoded_andMatrixOutputs_andMatrixInput_2_218) node decoder_decoded_andMatrixOutputs_hi_218 = cat(decoder_decoded_andMatrixOutputs_hi_hi_218, decoder_decoded_andMatrixOutputs_hi_lo_210) node _decoder_decoded_andMatrixOutputs_T_218 = cat(decoder_decoded_andMatrixOutputs_hi_218, decoder_decoded_andMatrixOutputs_lo_218) node decoder_decoded_andMatrixOutputs_131_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_218) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_219 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_219 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_219 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_219 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_219 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_217 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_211 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_201 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_176 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_152 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_176, decoder_decoded_andMatrixOutputs_andMatrixInput_9_152) node decoder_decoded_andMatrixOutputs_lo_hi_hi_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_217, decoder_decoded_andMatrixOutputs_andMatrixInput_6_211) node decoder_decoded_andMatrixOutputs_lo_hi_217 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_152, decoder_decoded_andMatrixOutputs_andMatrixInput_7_201) node decoder_decoded_andMatrixOutputs_lo_219 = cat(decoder_decoded_andMatrixOutputs_lo_hi_217, decoder_decoded_andMatrixOutputs_lo_lo_201) node decoder_decoded_andMatrixOutputs_hi_lo_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_219, decoder_decoded_andMatrixOutputs_andMatrixInput_4_219) node decoder_decoded_andMatrixOutputs_hi_hi_hi_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_219, decoder_decoded_andMatrixOutputs_andMatrixInput_1_219) node decoder_decoded_andMatrixOutputs_hi_hi_219 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_176, decoder_decoded_andMatrixOutputs_andMatrixInput_2_219) node decoder_decoded_andMatrixOutputs_hi_219 = cat(decoder_decoded_andMatrixOutputs_hi_hi_219, decoder_decoded_andMatrixOutputs_hi_lo_211) node _decoder_decoded_andMatrixOutputs_T_219 = cat(decoder_decoded_andMatrixOutputs_hi_219, decoder_decoded_andMatrixOutputs_lo_219) node decoder_decoded_andMatrixOutputs_191_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_219) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_220 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_220 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_220 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_220 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_220 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_218 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_212 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_lo_hi_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_220, decoder_decoded_andMatrixOutputs_andMatrixInput_5_218) node decoder_decoded_andMatrixOutputs_lo_220 = cat(decoder_decoded_andMatrixOutputs_lo_hi_218, decoder_decoded_andMatrixOutputs_andMatrixInput_6_212) node decoder_decoded_andMatrixOutputs_hi_lo_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_220, decoder_decoded_andMatrixOutputs_andMatrixInput_3_220) node decoder_decoded_andMatrixOutputs_hi_hi_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_220, decoder_decoded_andMatrixOutputs_andMatrixInput_1_220) node decoder_decoded_andMatrixOutputs_hi_220 = cat(decoder_decoded_andMatrixOutputs_hi_hi_220, decoder_decoded_andMatrixOutputs_hi_lo_212) node _decoder_decoded_andMatrixOutputs_T_220 = cat(decoder_decoded_andMatrixOutputs_hi_220, decoder_decoded_andMatrixOutputs_lo_220) node decoder_decoded_andMatrixOutputs_165_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_220) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_221 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_221 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_221 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_221 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_221 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_219 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_213 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_202 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_177 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_153 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_149 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_144 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_140 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_137 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_125 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_80 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_47 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_34 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_8 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_8 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_8, decoder_decoded_andMatrixOutputs_andMatrixInput_26_8) node decoder_decoded_andMatrixOutputs_lo_lo_lo_80 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_27_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_8, decoder_decoded_andMatrixOutputs_andMatrixInput_24_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_12, decoder_decoded_andMatrixOutputs_andMatrixInput_22_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_144 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_8) node decoder_decoded_andMatrixOutputs_lo_lo_202 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_144, decoder_decoded_andMatrixOutputs_lo_lo_lo_80) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_27, decoder_decoded_andMatrixOutputs_andMatrixInput_19_25) node decoder_decoded_andMatrixOutputs_lo_hi_lo_137 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_20_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_47, decoder_decoded_andMatrixOutputs_andMatrixInput_17_34) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_125, decoder_decoded_andMatrixOutputs_andMatrixInput_15_80) node decoder_decoded_andMatrixOutputs_lo_hi_hi_153 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8) node decoder_decoded_andMatrixOutputs_lo_hi_219 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_153, decoder_decoded_andMatrixOutputs_lo_hi_lo_137) node decoder_decoded_andMatrixOutputs_lo_221 = cat(decoder_decoded_andMatrixOutputs_lo_hi_219, decoder_decoded_andMatrixOutputs_lo_lo_202) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_144, decoder_decoded_andMatrixOutputs_andMatrixInput_12_140) node decoder_decoded_andMatrixOutputs_hi_lo_lo_125 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_137) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_153, decoder_decoded_andMatrixOutputs_andMatrixInput_10_149) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_202, decoder_decoded_andMatrixOutputs_andMatrixInput_8_177) node decoder_decoded_andMatrixOutputs_hi_lo_hi_149 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_8) node decoder_decoded_andMatrixOutputs_hi_lo_213 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_149, decoder_decoded_andMatrixOutputs_hi_lo_lo_125) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_221, decoder_decoded_andMatrixOutputs_andMatrixInput_5_219) node decoder_decoded_andMatrixOutputs_hi_hi_lo_140 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_213) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_221, decoder_decoded_andMatrixOutputs_andMatrixInput_3_221) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_221, decoder_decoded_andMatrixOutputs_andMatrixInput_1_221) node decoder_decoded_andMatrixOutputs_hi_hi_hi_177 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8) node decoder_decoded_andMatrixOutputs_hi_hi_221 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_177, decoder_decoded_andMatrixOutputs_hi_hi_lo_140) node decoder_decoded_andMatrixOutputs_hi_221 = cat(decoder_decoded_andMatrixOutputs_hi_hi_221, decoder_decoded_andMatrixOutputs_hi_lo_213) node _decoder_decoded_andMatrixOutputs_T_221 = cat(decoder_decoded_andMatrixOutputs_hi_221, decoder_decoded_andMatrixOutputs_lo_221) node decoder_decoded_andMatrixOutputs_54_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_221) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_222 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_222 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_222 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_222 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_222 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_220 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_214 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_203 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_178 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_154 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_150 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_145 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_141 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_138 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_126 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_81 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_48 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_35 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_9 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_9 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_4 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_4 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_4 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_4, decoder_decoded_andMatrixOutputs_andMatrixInput_29_4) node decoder_decoded_andMatrixOutputs_lo_lo_lo_81 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_30_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_9, decoder_decoded_andMatrixOutputs_andMatrixInput_27_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_9, decoder_decoded_andMatrixOutputs_andMatrixInput_25_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_145 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_9) node decoder_decoded_andMatrixOutputs_lo_lo_203 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_145, decoder_decoded_andMatrixOutputs_lo_lo_lo_81) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_9, decoder_decoded_andMatrixOutputs_andMatrixInput_23_9) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_18, decoder_decoded_andMatrixOutputs_andMatrixInput_21_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo_138 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_4) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_28, decoder_decoded_andMatrixOutputs_andMatrixInput_19_26) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_48, decoder_decoded_andMatrixOutputs_andMatrixInput_17_35) node decoder_decoded_andMatrixOutputs_lo_hi_hi_154 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9) node decoder_decoded_andMatrixOutputs_lo_hi_220 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_154, decoder_decoded_andMatrixOutputs_lo_hi_lo_138) node decoder_decoded_andMatrixOutputs_lo_222 = cat(decoder_decoded_andMatrixOutputs_lo_hi_220, decoder_decoded_andMatrixOutputs_lo_lo_203) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_126, decoder_decoded_andMatrixOutputs_andMatrixInput_15_81) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_141, decoder_decoded_andMatrixOutputs_andMatrixInput_13_138) node decoder_decoded_andMatrixOutputs_hi_lo_lo_126 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_150, decoder_decoded_andMatrixOutputs_andMatrixInput_11_145) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_178, decoder_decoded_andMatrixOutputs_andMatrixInput_9_154) node decoder_decoded_andMatrixOutputs_hi_lo_hi_150 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_9) node decoder_decoded_andMatrixOutputs_hi_lo_214 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_150, decoder_decoded_andMatrixOutputs_hi_lo_lo_126) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_214, decoder_decoded_andMatrixOutputs_andMatrixInput_7_203) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_222, decoder_decoded_andMatrixOutputs_andMatrixInput_5_220) node decoder_decoded_andMatrixOutputs_hi_hi_lo_141 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_222, decoder_decoded_andMatrixOutputs_andMatrixInput_3_222) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_222, decoder_decoded_andMatrixOutputs_andMatrixInput_1_222) node decoder_decoded_andMatrixOutputs_hi_hi_hi_178 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9) node decoder_decoded_andMatrixOutputs_hi_hi_222 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_178, decoder_decoded_andMatrixOutputs_hi_hi_lo_141) node decoder_decoded_andMatrixOutputs_hi_222 = cat(decoder_decoded_andMatrixOutputs_hi_hi_222, decoder_decoded_andMatrixOutputs_hi_lo_214) node _decoder_decoded_andMatrixOutputs_T_222 = cat(decoder_decoded_andMatrixOutputs_hi_222, decoder_decoded_andMatrixOutputs_lo_222) node decoder_decoded_andMatrixOutputs_89_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_222) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_223 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_223 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_223 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_223 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_223 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_221 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_215 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_223, decoder_decoded_andMatrixOutputs_andMatrixInput_5_221) node decoder_decoded_andMatrixOutputs_lo_223 = cat(decoder_decoded_andMatrixOutputs_lo_hi_221, decoder_decoded_andMatrixOutputs_andMatrixInput_6_215) node decoder_decoded_andMatrixOutputs_hi_lo_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_223, decoder_decoded_andMatrixOutputs_andMatrixInput_3_223) node decoder_decoded_andMatrixOutputs_hi_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_223, decoder_decoded_andMatrixOutputs_andMatrixInput_1_223) node decoder_decoded_andMatrixOutputs_hi_223 = cat(decoder_decoded_andMatrixOutputs_hi_hi_223, decoder_decoded_andMatrixOutputs_hi_lo_215) node _decoder_decoded_andMatrixOutputs_T_223 = cat(decoder_decoded_andMatrixOutputs_hi_223, decoder_decoded_andMatrixOutputs_lo_223) node decoder_decoded_andMatrixOutputs_30_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_223) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_224 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_224 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_224 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_224 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_224 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_222 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_216 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_204 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_216, decoder_decoded_andMatrixOutputs_andMatrixInput_7_204) node decoder_decoded_andMatrixOutputs_lo_hi_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_224, decoder_decoded_andMatrixOutputs_andMatrixInput_5_222) node decoder_decoded_andMatrixOutputs_lo_224 = cat(decoder_decoded_andMatrixOutputs_lo_hi_222, decoder_decoded_andMatrixOutputs_lo_lo_204) node decoder_decoded_andMatrixOutputs_hi_lo_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_224, decoder_decoded_andMatrixOutputs_andMatrixInput_3_224) node decoder_decoded_andMatrixOutputs_hi_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_224, decoder_decoded_andMatrixOutputs_andMatrixInput_1_224) node decoder_decoded_andMatrixOutputs_hi_224 = cat(decoder_decoded_andMatrixOutputs_hi_hi_224, decoder_decoded_andMatrixOutputs_hi_lo_216) node _decoder_decoded_andMatrixOutputs_T_224 = cat(decoder_decoded_andMatrixOutputs_hi_224, decoder_decoded_andMatrixOutputs_lo_224) node decoder_decoded_andMatrixOutputs_26_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_224) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_225 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_225 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_225 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_225 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_225 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_223 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_217 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_205 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_217, decoder_decoded_andMatrixOutputs_andMatrixInput_7_205) node decoder_decoded_andMatrixOutputs_lo_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_225, decoder_decoded_andMatrixOutputs_andMatrixInput_5_223) node decoder_decoded_andMatrixOutputs_lo_225 = cat(decoder_decoded_andMatrixOutputs_lo_hi_223, decoder_decoded_andMatrixOutputs_lo_lo_205) node decoder_decoded_andMatrixOutputs_hi_lo_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_225, decoder_decoded_andMatrixOutputs_andMatrixInput_3_225) node decoder_decoded_andMatrixOutputs_hi_hi_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_225, decoder_decoded_andMatrixOutputs_andMatrixInput_1_225) node decoder_decoded_andMatrixOutputs_hi_225 = cat(decoder_decoded_andMatrixOutputs_hi_hi_225, decoder_decoded_andMatrixOutputs_hi_lo_217) node _decoder_decoded_andMatrixOutputs_T_225 = cat(decoder_decoded_andMatrixOutputs_hi_225, decoder_decoded_andMatrixOutputs_lo_225) node decoder_decoded_andMatrixOutputs_176_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_225) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_226 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_226 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_226 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_226 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_226 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_224 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_218 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_206 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_179 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_206, decoder_decoded_andMatrixOutputs_andMatrixInput_8_179) node decoder_decoded_andMatrixOutputs_lo_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_224, decoder_decoded_andMatrixOutputs_andMatrixInput_6_218) node decoder_decoded_andMatrixOutputs_lo_226 = cat(decoder_decoded_andMatrixOutputs_lo_hi_224, decoder_decoded_andMatrixOutputs_lo_lo_206) node decoder_decoded_andMatrixOutputs_hi_lo_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_226, decoder_decoded_andMatrixOutputs_andMatrixInput_4_226) node decoder_decoded_andMatrixOutputs_hi_hi_hi_179 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_226, decoder_decoded_andMatrixOutputs_andMatrixInput_1_226) node decoder_decoded_andMatrixOutputs_hi_hi_226 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_179, decoder_decoded_andMatrixOutputs_andMatrixInput_2_226) node decoder_decoded_andMatrixOutputs_hi_226 = cat(decoder_decoded_andMatrixOutputs_hi_hi_226, decoder_decoded_andMatrixOutputs_hi_lo_218) node _decoder_decoded_andMatrixOutputs_T_226 = cat(decoder_decoded_andMatrixOutputs_hi_226, decoder_decoded_andMatrixOutputs_lo_226) node decoder_decoded_andMatrixOutputs_76_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_226) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_227 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_227 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_227 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_227 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_227 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_225 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_219 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_207 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_180 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_155 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_180, decoder_decoded_andMatrixOutputs_andMatrixInput_9_155) node decoder_decoded_andMatrixOutputs_lo_hi_hi_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_225, decoder_decoded_andMatrixOutputs_andMatrixInput_6_219) node decoder_decoded_andMatrixOutputs_lo_hi_225 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_7_207) node decoder_decoded_andMatrixOutputs_lo_227 = cat(decoder_decoded_andMatrixOutputs_lo_hi_225, decoder_decoded_andMatrixOutputs_lo_lo_207) node decoder_decoded_andMatrixOutputs_hi_lo_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_227, decoder_decoded_andMatrixOutputs_andMatrixInput_4_227) node decoder_decoded_andMatrixOutputs_hi_hi_hi_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_227, decoder_decoded_andMatrixOutputs_andMatrixInput_1_227) node decoder_decoded_andMatrixOutputs_hi_hi_227 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_180, decoder_decoded_andMatrixOutputs_andMatrixInput_2_227) node decoder_decoded_andMatrixOutputs_hi_227 = cat(decoder_decoded_andMatrixOutputs_hi_hi_227, decoder_decoded_andMatrixOutputs_hi_lo_219) node _decoder_decoded_andMatrixOutputs_T_227 = cat(decoder_decoded_andMatrixOutputs_hi_227, decoder_decoded_andMatrixOutputs_lo_227) node decoder_decoded_andMatrixOutputs_21_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_227) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_228 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_228 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_228 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_228 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_228 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_226 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_220 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_208 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_181 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_156 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_151 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_146 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_142 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_139 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_146, decoder_decoded_andMatrixOutputs_andMatrixInput_12_142) node decoder_decoded_andMatrixOutputs_lo_lo_208 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_146, decoder_decoded_andMatrixOutputs_andMatrixInput_13_139) node decoder_decoded_andMatrixOutputs_lo_hi_lo_139 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_156, decoder_decoded_andMatrixOutputs_andMatrixInput_10_151) node decoder_decoded_andMatrixOutputs_lo_hi_hi_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_208, decoder_decoded_andMatrixOutputs_andMatrixInput_8_181) node decoder_decoded_andMatrixOutputs_lo_hi_226 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_156, decoder_decoded_andMatrixOutputs_lo_hi_lo_139) node decoder_decoded_andMatrixOutputs_lo_228 = cat(decoder_decoded_andMatrixOutputs_lo_hi_226, decoder_decoded_andMatrixOutputs_lo_lo_208) node decoder_decoded_andMatrixOutputs_hi_lo_hi_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_228, decoder_decoded_andMatrixOutputs_andMatrixInput_5_226) node decoder_decoded_andMatrixOutputs_hi_lo_220 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_151, decoder_decoded_andMatrixOutputs_andMatrixInput_6_220) node decoder_decoded_andMatrixOutputs_hi_hi_lo_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_228, decoder_decoded_andMatrixOutputs_andMatrixInput_3_228) node decoder_decoded_andMatrixOutputs_hi_hi_hi_181 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_228, decoder_decoded_andMatrixOutputs_andMatrixInput_1_228) node decoder_decoded_andMatrixOutputs_hi_hi_228 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_181, decoder_decoded_andMatrixOutputs_hi_hi_lo_142) node decoder_decoded_andMatrixOutputs_hi_228 = cat(decoder_decoded_andMatrixOutputs_hi_hi_228, decoder_decoded_andMatrixOutputs_hi_lo_220) node _decoder_decoded_andMatrixOutputs_T_228 = cat(decoder_decoded_andMatrixOutputs_hi_228, decoder_decoded_andMatrixOutputs_lo_228) node decoder_decoded_andMatrixOutputs_121_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_228) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_229 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_229 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_229 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_229 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_229 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_227 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_221 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_209 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_182 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_157 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_152 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_147 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_143 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_140 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_127 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_143, decoder_decoded_andMatrixOutputs_andMatrixInput_13_140) node decoder_decoded_andMatrixOutputs_lo_lo_209 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_147, decoder_decoded_andMatrixOutputs_andMatrixInput_14_127) node decoder_decoded_andMatrixOutputs_lo_hi_lo_140 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_152, decoder_decoded_andMatrixOutputs_andMatrixInput_11_147) node decoder_decoded_andMatrixOutputs_lo_hi_hi_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_182, decoder_decoded_andMatrixOutputs_andMatrixInput_9_157) node decoder_decoded_andMatrixOutputs_lo_hi_227 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_157, decoder_decoded_andMatrixOutputs_lo_hi_lo_140) node decoder_decoded_andMatrixOutputs_lo_229 = cat(decoder_decoded_andMatrixOutputs_lo_hi_227, decoder_decoded_andMatrixOutputs_lo_lo_209) node decoder_decoded_andMatrixOutputs_hi_lo_lo_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_221, decoder_decoded_andMatrixOutputs_andMatrixInput_7_209) node decoder_decoded_andMatrixOutputs_hi_lo_hi_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_229, decoder_decoded_andMatrixOutputs_andMatrixInput_5_227) node decoder_decoded_andMatrixOutputs_hi_lo_221 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_152, decoder_decoded_andMatrixOutputs_hi_lo_lo_127) node decoder_decoded_andMatrixOutputs_hi_hi_lo_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_229, decoder_decoded_andMatrixOutputs_andMatrixInput_3_229) node decoder_decoded_andMatrixOutputs_hi_hi_hi_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_229, decoder_decoded_andMatrixOutputs_andMatrixInput_1_229) node decoder_decoded_andMatrixOutputs_hi_hi_229 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_182, decoder_decoded_andMatrixOutputs_hi_hi_lo_143) node decoder_decoded_andMatrixOutputs_hi_229 = cat(decoder_decoded_andMatrixOutputs_hi_hi_229, decoder_decoded_andMatrixOutputs_hi_lo_221) node _decoder_decoded_andMatrixOutputs_T_229 = cat(decoder_decoded_andMatrixOutputs_hi_229, decoder_decoded_andMatrixOutputs_lo_229) node decoder_decoded_andMatrixOutputs_60_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_229) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_230 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_230 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_230 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_230 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_230 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_228 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_222 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_210 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_183 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_158 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_153 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_148 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_144 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_141 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_128 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_144, decoder_decoded_andMatrixOutputs_andMatrixInput_13_141) node decoder_decoded_andMatrixOutputs_lo_lo_210 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_148, decoder_decoded_andMatrixOutputs_andMatrixInput_14_128) node decoder_decoded_andMatrixOutputs_lo_hi_lo_141 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_153, decoder_decoded_andMatrixOutputs_andMatrixInput_11_148) node decoder_decoded_andMatrixOutputs_lo_hi_hi_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_183, decoder_decoded_andMatrixOutputs_andMatrixInput_9_158) node decoder_decoded_andMatrixOutputs_lo_hi_228 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_158, decoder_decoded_andMatrixOutputs_lo_hi_lo_141) node decoder_decoded_andMatrixOutputs_lo_230 = cat(decoder_decoded_andMatrixOutputs_lo_hi_228, decoder_decoded_andMatrixOutputs_lo_lo_210) node decoder_decoded_andMatrixOutputs_hi_lo_lo_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_222, decoder_decoded_andMatrixOutputs_andMatrixInput_7_210) node decoder_decoded_andMatrixOutputs_hi_lo_hi_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_230, decoder_decoded_andMatrixOutputs_andMatrixInput_5_228) node decoder_decoded_andMatrixOutputs_hi_lo_222 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_153, decoder_decoded_andMatrixOutputs_hi_lo_lo_128) node decoder_decoded_andMatrixOutputs_hi_hi_lo_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_230, decoder_decoded_andMatrixOutputs_andMatrixInput_3_230) node decoder_decoded_andMatrixOutputs_hi_hi_hi_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_230, decoder_decoded_andMatrixOutputs_andMatrixInput_1_230) node decoder_decoded_andMatrixOutputs_hi_hi_230 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_183, decoder_decoded_andMatrixOutputs_hi_hi_lo_144) node decoder_decoded_andMatrixOutputs_hi_230 = cat(decoder_decoded_andMatrixOutputs_hi_hi_230, decoder_decoded_andMatrixOutputs_hi_lo_222) node _decoder_decoded_andMatrixOutputs_T_230 = cat(decoder_decoded_andMatrixOutputs_hi_230, decoder_decoded_andMatrixOutputs_lo_230) node decoder_decoded_andMatrixOutputs_103_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_230) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_231 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_231 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_231 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_231 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_231 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_229 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_223 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_211 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_184 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_159 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_154 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_149 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_145 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_142 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_129 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_82 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_129, decoder_decoded_andMatrixOutputs_andMatrixInput_15_82) node decoder_decoded_andMatrixOutputs_lo_lo_hi_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_145, decoder_decoded_andMatrixOutputs_andMatrixInput_13_142) node decoder_decoded_andMatrixOutputs_lo_lo_211 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_149, decoder_decoded_andMatrixOutputs_lo_lo_lo_82) node decoder_decoded_andMatrixOutputs_lo_hi_lo_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_154, decoder_decoded_andMatrixOutputs_andMatrixInput_11_149) node decoder_decoded_andMatrixOutputs_lo_hi_hi_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_184, decoder_decoded_andMatrixOutputs_andMatrixInput_9_159) node decoder_decoded_andMatrixOutputs_lo_hi_229 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_159, decoder_decoded_andMatrixOutputs_lo_hi_lo_142) node decoder_decoded_andMatrixOutputs_lo_231 = cat(decoder_decoded_andMatrixOutputs_lo_hi_229, decoder_decoded_andMatrixOutputs_lo_lo_211) node decoder_decoded_andMatrixOutputs_hi_lo_lo_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_223, decoder_decoded_andMatrixOutputs_andMatrixInput_7_211) node decoder_decoded_andMatrixOutputs_hi_lo_hi_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_231, decoder_decoded_andMatrixOutputs_andMatrixInput_5_229) node decoder_decoded_andMatrixOutputs_hi_lo_223 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_154, decoder_decoded_andMatrixOutputs_hi_lo_lo_129) node decoder_decoded_andMatrixOutputs_hi_hi_lo_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_231, decoder_decoded_andMatrixOutputs_andMatrixInput_3_231) node decoder_decoded_andMatrixOutputs_hi_hi_hi_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_231, decoder_decoded_andMatrixOutputs_andMatrixInput_1_231) node decoder_decoded_andMatrixOutputs_hi_hi_231 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_184, decoder_decoded_andMatrixOutputs_hi_hi_lo_145) node decoder_decoded_andMatrixOutputs_hi_231 = cat(decoder_decoded_andMatrixOutputs_hi_hi_231, decoder_decoded_andMatrixOutputs_hi_lo_223) node _decoder_decoded_andMatrixOutputs_T_231 = cat(decoder_decoded_andMatrixOutputs_hi_231, decoder_decoded_andMatrixOutputs_lo_231) node decoder_decoded_andMatrixOutputs_24_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_231) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_232 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_232 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_232 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_232 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_232 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_230 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_224 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_212 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_224, decoder_decoded_andMatrixOutputs_andMatrixInput_7_212) node decoder_decoded_andMatrixOutputs_lo_hi_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_232, decoder_decoded_andMatrixOutputs_andMatrixInput_5_230) node decoder_decoded_andMatrixOutputs_lo_232 = cat(decoder_decoded_andMatrixOutputs_lo_hi_230, decoder_decoded_andMatrixOutputs_lo_lo_212) node decoder_decoded_andMatrixOutputs_hi_lo_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_232, decoder_decoded_andMatrixOutputs_andMatrixInput_3_232) node decoder_decoded_andMatrixOutputs_hi_hi_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_232, decoder_decoded_andMatrixOutputs_andMatrixInput_1_232) node decoder_decoded_andMatrixOutputs_hi_232 = cat(decoder_decoded_andMatrixOutputs_hi_hi_232, decoder_decoded_andMatrixOutputs_hi_lo_224) node _decoder_decoded_andMatrixOutputs_T_232 = cat(decoder_decoded_andMatrixOutputs_hi_232, decoder_decoded_andMatrixOutputs_lo_232) node decoder_decoded_andMatrixOutputs_166_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_232) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_233 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_233 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_233 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_233 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_233 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_231 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_225 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_213 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_185 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_213, decoder_decoded_andMatrixOutputs_andMatrixInput_8_185) node decoder_decoded_andMatrixOutputs_lo_hi_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_231, decoder_decoded_andMatrixOutputs_andMatrixInput_6_225) node decoder_decoded_andMatrixOutputs_lo_233 = cat(decoder_decoded_andMatrixOutputs_lo_hi_231, decoder_decoded_andMatrixOutputs_lo_lo_213) node decoder_decoded_andMatrixOutputs_hi_lo_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_233, decoder_decoded_andMatrixOutputs_andMatrixInput_4_233) node decoder_decoded_andMatrixOutputs_hi_hi_hi_185 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_233, decoder_decoded_andMatrixOutputs_andMatrixInput_1_233) node decoder_decoded_andMatrixOutputs_hi_hi_233 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_185, decoder_decoded_andMatrixOutputs_andMatrixInput_2_233) node decoder_decoded_andMatrixOutputs_hi_233 = cat(decoder_decoded_andMatrixOutputs_hi_hi_233, decoder_decoded_andMatrixOutputs_hi_lo_225) node _decoder_decoded_andMatrixOutputs_T_233 = cat(decoder_decoded_andMatrixOutputs_hi_233, decoder_decoded_andMatrixOutputs_lo_233) node decoder_decoded_andMatrixOutputs_160_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_233) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_234 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_234 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_234 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_234 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_234 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_232 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_226 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_214 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_226, decoder_decoded_andMatrixOutputs_andMatrixInput_7_214) node decoder_decoded_andMatrixOutputs_lo_hi_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_234, decoder_decoded_andMatrixOutputs_andMatrixInput_5_232) node decoder_decoded_andMatrixOutputs_lo_234 = cat(decoder_decoded_andMatrixOutputs_lo_hi_232, decoder_decoded_andMatrixOutputs_lo_lo_214) node decoder_decoded_andMatrixOutputs_hi_lo_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_234, decoder_decoded_andMatrixOutputs_andMatrixInput_3_234) node decoder_decoded_andMatrixOutputs_hi_hi_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_234, decoder_decoded_andMatrixOutputs_andMatrixInput_1_234) node decoder_decoded_andMatrixOutputs_hi_234 = cat(decoder_decoded_andMatrixOutputs_hi_hi_234, decoder_decoded_andMatrixOutputs_hi_lo_226) node _decoder_decoded_andMatrixOutputs_T_234 = cat(decoder_decoded_andMatrixOutputs_hi_234, decoder_decoded_andMatrixOutputs_lo_234) node decoder_decoded_andMatrixOutputs_94_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_234) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_235 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_235 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_235 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_235 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_235 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_233 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_227 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_215 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_186 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_215, decoder_decoded_andMatrixOutputs_andMatrixInput_8_186) node decoder_decoded_andMatrixOutputs_lo_hi_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_233, decoder_decoded_andMatrixOutputs_andMatrixInput_6_227) node decoder_decoded_andMatrixOutputs_lo_235 = cat(decoder_decoded_andMatrixOutputs_lo_hi_233, decoder_decoded_andMatrixOutputs_lo_lo_215) node decoder_decoded_andMatrixOutputs_hi_lo_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_235, decoder_decoded_andMatrixOutputs_andMatrixInput_4_235) node decoder_decoded_andMatrixOutputs_hi_hi_hi_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_235, decoder_decoded_andMatrixOutputs_andMatrixInput_1_235) node decoder_decoded_andMatrixOutputs_hi_hi_235 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_186, decoder_decoded_andMatrixOutputs_andMatrixInput_2_235) node decoder_decoded_andMatrixOutputs_hi_235 = cat(decoder_decoded_andMatrixOutputs_hi_hi_235, decoder_decoded_andMatrixOutputs_hi_lo_227) node _decoder_decoded_andMatrixOutputs_T_235 = cat(decoder_decoded_andMatrixOutputs_hi_235, decoder_decoded_andMatrixOutputs_lo_235) node decoder_decoded_andMatrixOutputs_55_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_235) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_236 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_236 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_236 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_236 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_236 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_234 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_228 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_216 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_187 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_216, decoder_decoded_andMatrixOutputs_andMatrixInput_8_187) node decoder_decoded_andMatrixOutputs_lo_hi_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_234, decoder_decoded_andMatrixOutputs_andMatrixInput_6_228) node decoder_decoded_andMatrixOutputs_lo_236 = cat(decoder_decoded_andMatrixOutputs_lo_hi_234, decoder_decoded_andMatrixOutputs_lo_lo_216) node decoder_decoded_andMatrixOutputs_hi_lo_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_236, decoder_decoded_andMatrixOutputs_andMatrixInput_4_236) node decoder_decoded_andMatrixOutputs_hi_hi_hi_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_236, decoder_decoded_andMatrixOutputs_andMatrixInput_1_236) node decoder_decoded_andMatrixOutputs_hi_hi_236 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_187, decoder_decoded_andMatrixOutputs_andMatrixInput_2_236) node decoder_decoded_andMatrixOutputs_hi_236 = cat(decoder_decoded_andMatrixOutputs_hi_hi_236, decoder_decoded_andMatrixOutputs_hi_lo_228) node _decoder_decoded_andMatrixOutputs_T_236 = cat(decoder_decoded_andMatrixOutputs_hi_236, decoder_decoded_andMatrixOutputs_lo_236) node decoder_decoded_andMatrixOutputs_16_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_236) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_237 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_237 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_237 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_237 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_237 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_235 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_229 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_217 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_lo_lo_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_229, decoder_decoded_andMatrixOutputs_andMatrixInput_7_217) node decoder_decoded_andMatrixOutputs_lo_hi_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_237, decoder_decoded_andMatrixOutputs_andMatrixInput_5_235) node decoder_decoded_andMatrixOutputs_lo_237 = cat(decoder_decoded_andMatrixOutputs_lo_hi_235, decoder_decoded_andMatrixOutputs_lo_lo_217) node decoder_decoded_andMatrixOutputs_hi_lo_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_237, decoder_decoded_andMatrixOutputs_andMatrixInput_3_237) node decoder_decoded_andMatrixOutputs_hi_hi_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_237, decoder_decoded_andMatrixOutputs_andMatrixInput_1_237) node decoder_decoded_andMatrixOutputs_hi_237 = cat(decoder_decoded_andMatrixOutputs_hi_hi_237, decoder_decoded_andMatrixOutputs_hi_lo_229) node _decoder_decoded_andMatrixOutputs_T_237 = cat(decoder_decoded_andMatrixOutputs_hi_237, decoder_decoded_andMatrixOutputs_lo_237) node decoder_decoded_andMatrixOutputs_185_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_237) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_238 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_238 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_238 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_238 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_238 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_236 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_230 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_hi_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_238, decoder_decoded_andMatrixOutputs_andMatrixInput_5_236) node decoder_decoded_andMatrixOutputs_lo_238 = cat(decoder_decoded_andMatrixOutputs_lo_hi_236, decoder_decoded_andMatrixOutputs_andMatrixInput_6_230) node decoder_decoded_andMatrixOutputs_hi_lo_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_238, decoder_decoded_andMatrixOutputs_andMatrixInput_3_238) node decoder_decoded_andMatrixOutputs_hi_hi_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_238, decoder_decoded_andMatrixOutputs_andMatrixInput_1_238) node decoder_decoded_andMatrixOutputs_hi_238 = cat(decoder_decoded_andMatrixOutputs_hi_hi_238, decoder_decoded_andMatrixOutputs_hi_lo_230) node _decoder_decoded_andMatrixOutputs_T_238 = cat(decoder_decoded_andMatrixOutputs_hi_238, decoder_decoded_andMatrixOutputs_lo_238) node decoder_decoded_andMatrixOutputs_140_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_238) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_239 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_239 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_239 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_239 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_239 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_237 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_231 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_218 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_231, decoder_decoded_andMatrixOutputs_andMatrixInput_7_218) node decoder_decoded_andMatrixOutputs_lo_hi_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_239, decoder_decoded_andMatrixOutputs_andMatrixInput_5_237) node decoder_decoded_andMatrixOutputs_lo_239 = cat(decoder_decoded_andMatrixOutputs_lo_hi_237, decoder_decoded_andMatrixOutputs_lo_lo_218) node decoder_decoded_andMatrixOutputs_hi_lo_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_239, decoder_decoded_andMatrixOutputs_andMatrixInput_3_239) node decoder_decoded_andMatrixOutputs_hi_hi_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_239, decoder_decoded_andMatrixOutputs_andMatrixInput_1_239) node decoder_decoded_andMatrixOutputs_hi_239 = cat(decoder_decoded_andMatrixOutputs_hi_hi_239, decoder_decoded_andMatrixOutputs_hi_lo_231) node _decoder_decoded_andMatrixOutputs_T_239 = cat(decoder_decoded_andMatrixOutputs_hi_239, decoder_decoded_andMatrixOutputs_lo_239) node decoder_decoded_andMatrixOutputs_52_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_239) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_240 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_240 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_240 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_240 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_240 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_238 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_232 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_219 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_232, decoder_decoded_andMatrixOutputs_andMatrixInput_7_219) node decoder_decoded_andMatrixOutputs_lo_hi_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_240, decoder_decoded_andMatrixOutputs_andMatrixInput_5_238) node decoder_decoded_andMatrixOutputs_lo_240 = cat(decoder_decoded_andMatrixOutputs_lo_hi_238, decoder_decoded_andMatrixOutputs_lo_lo_219) node decoder_decoded_andMatrixOutputs_hi_lo_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_240, decoder_decoded_andMatrixOutputs_andMatrixInput_3_240) node decoder_decoded_andMatrixOutputs_hi_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_240, decoder_decoded_andMatrixOutputs_andMatrixInput_1_240) node decoder_decoded_andMatrixOutputs_hi_240 = cat(decoder_decoded_andMatrixOutputs_hi_hi_240, decoder_decoded_andMatrixOutputs_hi_lo_232) node _decoder_decoded_andMatrixOutputs_T_240 = cat(decoder_decoded_andMatrixOutputs_hi_240, decoder_decoded_andMatrixOutputs_lo_240) node decoder_decoded_andMatrixOutputs_193_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_240) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_241 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_241 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_241 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_241 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_241 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_239 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_233 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_220 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_188 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_220, decoder_decoded_andMatrixOutputs_andMatrixInput_8_188) node decoder_decoded_andMatrixOutputs_lo_hi_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_239, decoder_decoded_andMatrixOutputs_andMatrixInput_6_233) node decoder_decoded_andMatrixOutputs_lo_241 = cat(decoder_decoded_andMatrixOutputs_lo_hi_239, decoder_decoded_andMatrixOutputs_lo_lo_220) node decoder_decoded_andMatrixOutputs_hi_lo_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_241, decoder_decoded_andMatrixOutputs_andMatrixInput_4_241) node decoder_decoded_andMatrixOutputs_hi_hi_hi_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_241, decoder_decoded_andMatrixOutputs_andMatrixInput_1_241) node decoder_decoded_andMatrixOutputs_hi_hi_241 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_188, decoder_decoded_andMatrixOutputs_andMatrixInput_2_241) node decoder_decoded_andMatrixOutputs_hi_241 = cat(decoder_decoded_andMatrixOutputs_hi_hi_241, decoder_decoded_andMatrixOutputs_hi_lo_233) node _decoder_decoded_andMatrixOutputs_T_241 = cat(decoder_decoded_andMatrixOutputs_hi_241, decoder_decoded_andMatrixOutputs_lo_241) node decoder_decoded_andMatrixOutputs_91_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_241) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_242 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_242 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_242 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_242 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_242 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_240 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_234 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_221 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_234, decoder_decoded_andMatrixOutputs_andMatrixInput_7_221) node decoder_decoded_andMatrixOutputs_lo_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_242, decoder_decoded_andMatrixOutputs_andMatrixInput_5_240) node decoder_decoded_andMatrixOutputs_lo_242 = cat(decoder_decoded_andMatrixOutputs_lo_hi_240, decoder_decoded_andMatrixOutputs_lo_lo_221) node decoder_decoded_andMatrixOutputs_hi_lo_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_242, decoder_decoded_andMatrixOutputs_andMatrixInput_3_242) node decoder_decoded_andMatrixOutputs_hi_hi_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_242, decoder_decoded_andMatrixOutputs_andMatrixInput_1_242) node decoder_decoded_andMatrixOutputs_hi_242 = cat(decoder_decoded_andMatrixOutputs_hi_hi_242, decoder_decoded_andMatrixOutputs_hi_lo_234) node _decoder_decoded_andMatrixOutputs_T_242 = cat(decoder_decoded_andMatrixOutputs_hi_242, decoder_decoded_andMatrixOutputs_lo_242) node decoder_decoded_andMatrixOutputs_17_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_242) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_243 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_243 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_243 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_243 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_243 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_241 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_235 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_222 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_189 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_222, decoder_decoded_andMatrixOutputs_andMatrixInput_8_189) node decoder_decoded_andMatrixOutputs_lo_hi_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_241, decoder_decoded_andMatrixOutputs_andMatrixInput_6_235) node decoder_decoded_andMatrixOutputs_lo_243 = cat(decoder_decoded_andMatrixOutputs_lo_hi_241, decoder_decoded_andMatrixOutputs_lo_lo_222) node decoder_decoded_andMatrixOutputs_hi_lo_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_243, decoder_decoded_andMatrixOutputs_andMatrixInput_4_243) node decoder_decoded_andMatrixOutputs_hi_hi_hi_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_243, decoder_decoded_andMatrixOutputs_andMatrixInput_1_243) node decoder_decoded_andMatrixOutputs_hi_hi_243 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_189, decoder_decoded_andMatrixOutputs_andMatrixInput_2_243) node decoder_decoded_andMatrixOutputs_hi_243 = cat(decoder_decoded_andMatrixOutputs_hi_hi_243, decoder_decoded_andMatrixOutputs_hi_lo_235) node _decoder_decoded_andMatrixOutputs_T_243 = cat(decoder_decoded_andMatrixOutputs_hi_243, decoder_decoded_andMatrixOutputs_lo_243) node decoder_decoded_andMatrixOutputs_129_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_243) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_244 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_244 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_244 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_244 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_244 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_242 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_236 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_223 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_236, decoder_decoded_andMatrixOutputs_andMatrixInput_7_223) node decoder_decoded_andMatrixOutputs_lo_hi_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_244, decoder_decoded_andMatrixOutputs_andMatrixInput_5_242) node decoder_decoded_andMatrixOutputs_lo_244 = cat(decoder_decoded_andMatrixOutputs_lo_hi_242, decoder_decoded_andMatrixOutputs_lo_lo_223) node decoder_decoded_andMatrixOutputs_hi_lo_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_244, decoder_decoded_andMatrixOutputs_andMatrixInput_3_244) node decoder_decoded_andMatrixOutputs_hi_hi_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_244, decoder_decoded_andMatrixOutputs_andMatrixInput_1_244) node decoder_decoded_andMatrixOutputs_hi_244 = cat(decoder_decoded_andMatrixOutputs_hi_hi_244, decoder_decoded_andMatrixOutputs_hi_lo_236) node _decoder_decoded_andMatrixOutputs_T_244 = cat(decoder_decoded_andMatrixOutputs_hi_244, decoder_decoded_andMatrixOutputs_lo_244) node decoder_decoded_andMatrixOutputs_177_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_244) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_245 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_245 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_245 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_245 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_245 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_243 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_237 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_224 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_190 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_224, decoder_decoded_andMatrixOutputs_andMatrixInput_8_190) node decoder_decoded_andMatrixOutputs_lo_hi_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_243, decoder_decoded_andMatrixOutputs_andMatrixInput_6_237) node decoder_decoded_andMatrixOutputs_lo_245 = cat(decoder_decoded_andMatrixOutputs_lo_hi_243, decoder_decoded_andMatrixOutputs_lo_lo_224) node decoder_decoded_andMatrixOutputs_hi_lo_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_245, decoder_decoded_andMatrixOutputs_andMatrixInput_4_245) node decoder_decoded_andMatrixOutputs_hi_hi_hi_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_245, decoder_decoded_andMatrixOutputs_andMatrixInput_1_245) node decoder_decoded_andMatrixOutputs_hi_hi_245 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_190, decoder_decoded_andMatrixOutputs_andMatrixInput_2_245) node decoder_decoded_andMatrixOutputs_hi_245 = cat(decoder_decoded_andMatrixOutputs_hi_hi_245, decoder_decoded_andMatrixOutputs_hi_lo_237) node _decoder_decoded_andMatrixOutputs_T_245 = cat(decoder_decoded_andMatrixOutputs_hi_245, decoder_decoded_andMatrixOutputs_lo_245) node decoder_decoded_andMatrixOutputs_123_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_245) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_246 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_246 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_246 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_246 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_246 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_244 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_238 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_225 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_191 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_160 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_155 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_lo_lo_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_160, decoder_decoded_andMatrixOutputs_andMatrixInput_10_155) node decoder_decoded_andMatrixOutputs_lo_hi_hi_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_238, decoder_decoded_andMatrixOutputs_andMatrixInput_7_225) node decoder_decoded_andMatrixOutputs_lo_hi_244 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_8_191) node decoder_decoded_andMatrixOutputs_lo_246 = cat(decoder_decoded_andMatrixOutputs_lo_hi_244, decoder_decoded_andMatrixOutputs_lo_lo_225) node decoder_decoded_andMatrixOutputs_hi_lo_hi_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_246, decoder_decoded_andMatrixOutputs_andMatrixInput_4_246) node decoder_decoded_andMatrixOutputs_hi_lo_238 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_5_244) node decoder_decoded_andMatrixOutputs_hi_hi_hi_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_246, decoder_decoded_andMatrixOutputs_andMatrixInput_1_246) node decoder_decoded_andMatrixOutputs_hi_hi_246 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_191, decoder_decoded_andMatrixOutputs_andMatrixInput_2_246) node decoder_decoded_andMatrixOutputs_hi_246 = cat(decoder_decoded_andMatrixOutputs_hi_hi_246, decoder_decoded_andMatrixOutputs_hi_lo_238) node _decoder_decoded_andMatrixOutputs_T_246 = cat(decoder_decoded_andMatrixOutputs_hi_246, decoder_decoded_andMatrixOutputs_lo_246) node decoder_decoded_andMatrixOutputs_14_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_246) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_247 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_247 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_247 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_247 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_247 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_245 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_239 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_226 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_192 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_161 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_156 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_150 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_146 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_143 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_130 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_146, decoder_decoded_andMatrixOutputs_andMatrixInput_13_143) node decoder_decoded_andMatrixOutputs_lo_lo_226 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_150, decoder_decoded_andMatrixOutputs_andMatrixInput_14_130) node decoder_decoded_andMatrixOutputs_lo_hi_lo_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_156, decoder_decoded_andMatrixOutputs_andMatrixInput_11_150) node decoder_decoded_andMatrixOutputs_lo_hi_hi_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_192, decoder_decoded_andMatrixOutputs_andMatrixInput_9_161) node decoder_decoded_andMatrixOutputs_lo_hi_245 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_161, decoder_decoded_andMatrixOutputs_lo_hi_lo_143) node decoder_decoded_andMatrixOutputs_lo_247 = cat(decoder_decoded_andMatrixOutputs_lo_hi_245, decoder_decoded_andMatrixOutputs_lo_lo_226) node decoder_decoded_andMatrixOutputs_hi_lo_lo_130 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_239, decoder_decoded_andMatrixOutputs_andMatrixInput_7_226) node decoder_decoded_andMatrixOutputs_hi_lo_hi_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_247, decoder_decoded_andMatrixOutputs_andMatrixInput_5_245) node decoder_decoded_andMatrixOutputs_hi_lo_239 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_156, decoder_decoded_andMatrixOutputs_hi_lo_lo_130) node decoder_decoded_andMatrixOutputs_hi_hi_lo_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_247, decoder_decoded_andMatrixOutputs_andMatrixInput_3_247) node decoder_decoded_andMatrixOutputs_hi_hi_hi_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_247, decoder_decoded_andMatrixOutputs_andMatrixInput_1_247) node decoder_decoded_andMatrixOutputs_hi_hi_247 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_192, decoder_decoded_andMatrixOutputs_hi_hi_lo_146) node decoder_decoded_andMatrixOutputs_hi_247 = cat(decoder_decoded_andMatrixOutputs_hi_hi_247, decoder_decoded_andMatrixOutputs_hi_lo_239) node _decoder_decoded_andMatrixOutputs_T_247 = cat(decoder_decoded_andMatrixOutputs_hi_247, decoder_decoded_andMatrixOutputs_lo_247) node decoder_decoded_andMatrixOutputs_132_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_247) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_248 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_248 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_248 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_248 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_248 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_246 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_240 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_227 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_193 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_162 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_157 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_151 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_147 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_144 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_131 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_83 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_131, decoder_decoded_andMatrixOutputs_andMatrixInput_15_83) node decoder_decoded_andMatrixOutputs_lo_lo_hi_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_147, decoder_decoded_andMatrixOutputs_andMatrixInput_13_144) node decoder_decoded_andMatrixOutputs_lo_lo_227 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_151, decoder_decoded_andMatrixOutputs_lo_lo_lo_83) node decoder_decoded_andMatrixOutputs_lo_hi_lo_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_157, decoder_decoded_andMatrixOutputs_andMatrixInput_11_151) node decoder_decoded_andMatrixOutputs_lo_hi_hi_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_193, decoder_decoded_andMatrixOutputs_andMatrixInput_9_162) node decoder_decoded_andMatrixOutputs_lo_hi_246 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_162, decoder_decoded_andMatrixOutputs_lo_hi_lo_144) node decoder_decoded_andMatrixOutputs_lo_248 = cat(decoder_decoded_andMatrixOutputs_lo_hi_246, decoder_decoded_andMatrixOutputs_lo_lo_227) node decoder_decoded_andMatrixOutputs_hi_lo_lo_131 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_240, decoder_decoded_andMatrixOutputs_andMatrixInput_7_227) node decoder_decoded_andMatrixOutputs_hi_lo_hi_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_248, decoder_decoded_andMatrixOutputs_andMatrixInput_5_246) node decoder_decoded_andMatrixOutputs_hi_lo_240 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_157, decoder_decoded_andMatrixOutputs_hi_lo_lo_131) node decoder_decoded_andMatrixOutputs_hi_hi_lo_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_248, decoder_decoded_andMatrixOutputs_andMatrixInput_3_248) node decoder_decoded_andMatrixOutputs_hi_hi_hi_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_248, decoder_decoded_andMatrixOutputs_andMatrixInput_1_248) node decoder_decoded_andMatrixOutputs_hi_hi_248 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_193, decoder_decoded_andMatrixOutputs_hi_hi_lo_147) node decoder_decoded_andMatrixOutputs_hi_248 = cat(decoder_decoded_andMatrixOutputs_hi_hi_248, decoder_decoded_andMatrixOutputs_hi_lo_240) node _decoder_decoded_andMatrixOutputs_T_248 = cat(decoder_decoded_andMatrixOutputs_hi_248, decoder_decoded_andMatrixOutputs_lo_248) node decoder_decoded_andMatrixOutputs_48_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_248) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_249 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_249 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_249 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_249 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_249 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_247 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_241 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_228 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_241, decoder_decoded_andMatrixOutputs_andMatrixInput_7_228) node decoder_decoded_andMatrixOutputs_lo_hi_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_249, decoder_decoded_andMatrixOutputs_andMatrixInput_5_247) node decoder_decoded_andMatrixOutputs_lo_249 = cat(decoder_decoded_andMatrixOutputs_lo_hi_247, decoder_decoded_andMatrixOutputs_lo_lo_228) node decoder_decoded_andMatrixOutputs_hi_lo_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_249, decoder_decoded_andMatrixOutputs_andMatrixInput_3_249) node decoder_decoded_andMatrixOutputs_hi_hi_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_249, decoder_decoded_andMatrixOutputs_andMatrixInput_1_249) node decoder_decoded_andMatrixOutputs_hi_249 = cat(decoder_decoded_andMatrixOutputs_hi_hi_249, decoder_decoded_andMatrixOutputs_hi_lo_241) node _decoder_decoded_andMatrixOutputs_T_249 = cat(decoder_decoded_andMatrixOutputs_hi_249, decoder_decoded_andMatrixOutputs_lo_249) node decoder_decoded_andMatrixOutputs_155_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_249) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_250 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_250 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_250 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_250 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_250 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_248 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_242 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_229 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_194 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_229, decoder_decoded_andMatrixOutputs_andMatrixInput_8_194) node decoder_decoded_andMatrixOutputs_lo_hi_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_248, decoder_decoded_andMatrixOutputs_andMatrixInput_6_242) node decoder_decoded_andMatrixOutputs_lo_250 = cat(decoder_decoded_andMatrixOutputs_lo_hi_248, decoder_decoded_andMatrixOutputs_lo_lo_229) node decoder_decoded_andMatrixOutputs_hi_lo_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_250, decoder_decoded_andMatrixOutputs_andMatrixInput_4_250) node decoder_decoded_andMatrixOutputs_hi_hi_hi_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_250, decoder_decoded_andMatrixOutputs_andMatrixInput_1_250) node decoder_decoded_andMatrixOutputs_hi_hi_250 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_2_250) node decoder_decoded_andMatrixOutputs_hi_250 = cat(decoder_decoded_andMatrixOutputs_hi_hi_250, decoder_decoded_andMatrixOutputs_hi_lo_242) node _decoder_decoded_andMatrixOutputs_T_250 = cat(decoder_decoded_andMatrixOutputs_hi_250, decoder_decoded_andMatrixOutputs_lo_250) node decoder_decoded_andMatrixOutputs_184_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_250) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_251 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_251 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_251 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_251 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_251 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_249 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_243 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_230 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_195 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_230, decoder_decoded_andMatrixOutputs_andMatrixInput_8_195) node decoder_decoded_andMatrixOutputs_lo_hi_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_249, decoder_decoded_andMatrixOutputs_andMatrixInput_6_243) node decoder_decoded_andMatrixOutputs_lo_251 = cat(decoder_decoded_andMatrixOutputs_lo_hi_249, decoder_decoded_andMatrixOutputs_lo_lo_230) node decoder_decoded_andMatrixOutputs_hi_lo_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_251, decoder_decoded_andMatrixOutputs_andMatrixInput_4_251) node decoder_decoded_andMatrixOutputs_hi_hi_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_251, decoder_decoded_andMatrixOutputs_andMatrixInput_1_251) node decoder_decoded_andMatrixOutputs_hi_hi_251 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_2_251) node decoder_decoded_andMatrixOutputs_hi_251 = cat(decoder_decoded_andMatrixOutputs_hi_hi_251, decoder_decoded_andMatrixOutputs_hi_lo_243) node _decoder_decoded_andMatrixOutputs_T_251 = cat(decoder_decoded_andMatrixOutputs_hi_251, decoder_decoded_andMatrixOutputs_lo_251) node decoder_decoded_andMatrixOutputs_148_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_251) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_252 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_252 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_252 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_252 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_252 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_250 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_244 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_231 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_196 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_lo_lo_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_231, decoder_decoded_andMatrixOutputs_andMatrixInput_8_196) node decoder_decoded_andMatrixOutputs_lo_hi_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_250, decoder_decoded_andMatrixOutputs_andMatrixInput_6_244) node decoder_decoded_andMatrixOutputs_lo_252 = cat(decoder_decoded_andMatrixOutputs_lo_hi_250, decoder_decoded_andMatrixOutputs_lo_lo_231) node decoder_decoded_andMatrixOutputs_hi_lo_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_252, decoder_decoded_andMatrixOutputs_andMatrixInput_4_252) node decoder_decoded_andMatrixOutputs_hi_hi_hi_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_252, decoder_decoded_andMatrixOutputs_andMatrixInput_1_252) node decoder_decoded_andMatrixOutputs_hi_hi_252 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_2_252) node decoder_decoded_andMatrixOutputs_hi_252 = cat(decoder_decoded_andMatrixOutputs_hi_hi_252, decoder_decoded_andMatrixOutputs_hi_lo_244) node _decoder_decoded_andMatrixOutputs_T_252 = cat(decoder_decoded_andMatrixOutputs_hi_252, decoder_decoded_andMatrixOutputs_lo_252) node decoder_decoded_andMatrixOutputs_115_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_252) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_253 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_253 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_253 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_253 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_253 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_251 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_245 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_232 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_197 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_163 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_158 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_152 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_148 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_145 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_132 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_148, decoder_decoded_andMatrixOutputs_andMatrixInput_13_145) node decoder_decoded_andMatrixOutputs_lo_lo_232 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_152, decoder_decoded_andMatrixOutputs_andMatrixInput_14_132) node decoder_decoded_andMatrixOutputs_lo_hi_lo_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_158, decoder_decoded_andMatrixOutputs_andMatrixInput_11_152) node decoder_decoded_andMatrixOutputs_lo_hi_hi_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_197, decoder_decoded_andMatrixOutputs_andMatrixInput_9_163) node decoder_decoded_andMatrixOutputs_lo_hi_251 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_163, decoder_decoded_andMatrixOutputs_lo_hi_lo_145) node decoder_decoded_andMatrixOutputs_lo_253 = cat(decoder_decoded_andMatrixOutputs_lo_hi_251, decoder_decoded_andMatrixOutputs_lo_lo_232) node decoder_decoded_andMatrixOutputs_hi_lo_lo_132 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_245, decoder_decoded_andMatrixOutputs_andMatrixInput_7_232) node decoder_decoded_andMatrixOutputs_hi_lo_hi_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_253, decoder_decoded_andMatrixOutputs_andMatrixInput_5_251) node decoder_decoded_andMatrixOutputs_hi_lo_245 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_158, decoder_decoded_andMatrixOutputs_hi_lo_lo_132) node decoder_decoded_andMatrixOutputs_hi_hi_lo_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_253, decoder_decoded_andMatrixOutputs_andMatrixInput_3_253) node decoder_decoded_andMatrixOutputs_hi_hi_hi_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_253, decoder_decoded_andMatrixOutputs_andMatrixInput_1_253) node decoder_decoded_andMatrixOutputs_hi_hi_253 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_197, decoder_decoded_andMatrixOutputs_hi_hi_lo_148) node decoder_decoded_andMatrixOutputs_hi_253 = cat(decoder_decoded_andMatrixOutputs_hi_hi_253, decoder_decoded_andMatrixOutputs_hi_lo_245) node _decoder_decoded_andMatrixOutputs_T_253 = cat(decoder_decoded_andMatrixOutputs_hi_253, decoder_decoded_andMatrixOutputs_lo_253) node decoder_decoded_andMatrixOutputs_163_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_253) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_254 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_254 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_254 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_254 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_254 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_252 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_246 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_233 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_198 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_233, decoder_decoded_andMatrixOutputs_andMatrixInput_8_198) node decoder_decoded_andMatrixOutputs_lo_hi_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_252, decoder_decoded_andMatrixOutputs_andMatrixInput_6_246) node decoder_decoded_andMatrixOutputs_lo_254 = cat(decoder_decoded_andMatrixOutputs_lo_hi_252, decoder_decoded_andMatrixOutputs_lo_lo_233) node decoder_decoded_andMatrixOutputs_hi_lo_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_254, decoder_decoded_andMatrixOutputs_andMatrixInput_4_254) node decoder_decoded_andMatrixOutputs_hi_hi_hi_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_254, decoder_decoded_andMatrixOutputs_andMatrixInput_1_254) node decoder_decoded_andMatrixOutputs_hi_hi_254 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_2_254) node decoder_decoded_andMatrixOutputs_hi_254 = cat(decoder_decoded_andMatrixOutputs_hi_hi_254, decoder_decoded_andMatrixOutputs_hi_lo_246) node _decoder_decoded_andMatrixOutputs_T_254 = cat(decoder_decoded_andMatrixOutputs_hi_254, decoder_decoded_andMatrixOutputs_lo_254) node decoder_decoded_andMatrixOutputs_45_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_254) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_255 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_255 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_255 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_255 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_255 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_253 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_247 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_234 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_199 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_164 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_159 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_153 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_149 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_146 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_153, decoder_decoded_andMatrixOutputs_andMatrixInput_12_149) node decoder_decoded_andMatrixOutputs_lo_lo_234 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_153, decoder_decoded_andMatrixOutputs_andMatrixInput_13_146) node decoder_decoded_andMatrixOutputs_lo_hi_lo_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_164, decoder_decoded_andMatrixOutputs_andMatrixInput_10_159) node decoder_decoded_andMatrixOutputs_lo_hi_hi_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_234, decoder_decoded_andMatrixOutputs_andMatrixInput_8_199) node decoder_decoded_andMatrixOutputs_lo_hi_253 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_164, decoder_decoded_andMatrixOutputs_lo_hi_lo_146) node decoder_decoded_andMatrixOutputs_lo_255 = cat(decoder_decoded_andMatrixOutputs_lo_hi_253, decoder_decoded_andMatrixOutputs_lo_lo_234) node decoder_decoded_andMatrixOutputs_hi_lo_hi_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_255, decoder_decoded_andMatrixOutputs_andMatrixInput_5_253) node decoder_decoded_andMatrixOutputs_hi_lo_247 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_159, decoder_decoded_andMatrixOutputs_andMatrixInput_6_247) node decoder_decoded_andMatrixOutputs_hi_hi_lo_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_255, decoder_decoded_andMatrixOutputs_andMatrixInput_3_255) node decoder_decoded_andMatrixOutputs_hi_hi_hi_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_255, decoder_decoded_andMatrixOutputs_andMatrixInput_1_255) node decoder_decoded_andMatrixOutputs_hi_hi_255 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_199, decoder_decoded_andMatrixOutputs_hi_hi_lo_149) node decoder_decoded_andMatrixOutputs_hi_255 = cat(decoder_decoded_andMatrixOutputs_hi_hi_255, decoder_decoded_andMatrixOutputs_hi_lo_247) node _decoder_decoded_andMatrixOutputs_T_255 = cat(decoder_decoded_andMatrixOutputs_hi_255, decoder_decoded_andMatrixOutputs_lo_255) node decoder_decoded_andMatrixOutputs_126_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_255) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_256 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_256 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_256 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_256 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_256 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_254 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_248 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_235 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_200 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_165 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_160 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_154 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_150 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_147 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_154, decoder_decoded_andMatrixOutputs_andMatrixInput_12_150) node decoder_decoded_andMatrixOutputs_lo_lo_235 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_154, decoder_decoded_andMatrixOutputs_andMatrixInput_13_147) node decoder_decoded_andMatrixOutputs_lo_hi_lo_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_165, decoder_decoded_andMatrixOutputs_andMatrixInput_10_160) node decoder_decoded_andMatrixOutputs_lo_hi_hi_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_235, decoder_decoded_andMatrixOutputs_andMatrixInput_8_200) node decoder_decoded_andMatrixOutputs_lo_hi_254 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_165, decoder_decoded_andMatrixOutputs_lo_hi_lo_147) node decoder_decoded_andMatrixOutputs_lo_256 = cat(decoder_decoded_andMatrixOutputs_lo_hi_254, decoder_decoded_andMatrixOutputs_lo_lo_235) node decoder_decoded_andMatrixOutputs_hi_lo_hi_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_256, decoder_decoded_andMatrixOutputs_andMatrixInput_5_254) node decoder_decoded_andMatrixOutputs_hi_lo_248 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_6_248) node decoder_decoded_andMatrixOutputs_hi_hi_lo_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_256, decoder_decoded_andMatrixOutputs_andMatrixInput_3_256) node decoder_decoded_andMatrixOutputs_hi_hi_hi_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_256, decoder_decoded_andMatrixOutputs_andMatrixInput_1_256) node decoder_decoded_andMatrixOutputs_hi_hi_256 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_200, decoder_decoded_andMatrixOutputs_hi_hi_lo_150) node decoder_decoded_andMatrixOutputs_hi_256 = cat(decoder_decoded_andMatrixOutputs_hi_hi_256, decoder_decoded_andMatrixOutputs_hi_lo_248) node _decoder_decoded_andMatrixOutputs_T_256 = cat(decoder_decoded_andMatrixOutputs_hi_256, decoder_decoded_andMatrixOutputs_lo_256) node decoder_decoded_andMatrixOutputs_150_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_256) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_257 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_257 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_257 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_257 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_257 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_255 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_249 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_236 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_249, decoder_decoded_andMatrixOutputs_andMatrixInput_7_236) node decoder_decoded_andMatrixOutputs_lo_hi_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_257, decoder_decoded_andMatrixOutputs_andMatrixInput_5_255) node decoder_decoded_andMatrixOutputs_lo_257 = cat(decoder_decoded_andMatrixOutputs_lo_hi_255, decoder_decoded_andMatrixOutputs_lo_lo_236) node decoder_decoded_andMatrixOutputs_hi_lo_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_257, decoder_decoded_andMatrixOutputs_andMatrixInput_3_257) node decoder_decoded_andMatrixOutputs_hi_hi_257 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_257, decoder_decoded_andMatrixOutputs_andMatrixInput_1_257) node decoder_decoded_andMatrixOutputs_hi_257 = cat(decoder_decoded_andMatrixOutputs_hi_hi_257, decoder_decoded_andMatrixOutputs_hi_lo_249) node _decoder_decoded_andMatrixOutputs_T_257 = cat(decoder_decoded_andMatrixOutputs_hi_257, decoder_decoded_andMatrixOutputs_lo_257) node decoder_decoded_andMatrixOutputs_162_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_257) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_258 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_258 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_258 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_258 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_258 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_256 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_250 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_237 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_201 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_166 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_161 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_155 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_151 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_148 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_133 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_151, decoder_decoded_andMatrixOutputs_andMatrixInput_13_148) node decoder_decoded_andMatrixOutputs_lo_lo_237 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_14_133) node decoder_decoded_andMatrixOutputs_lo_hi_lo_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_161, decoder_decoded_andMatrixOutputs_andMatrixInput_11_155) node decoder_decoded_andMatrixOutputs_lo_hi_hi_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_201, decoder_decoded_andMatrixOutputs_andMatrixInput_9_166) node decoder_decoded_andMatrixOutputs_lo_hi_256 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_166, decoder_decoded_andMatrixOutputs_lo_hi_lo_148) node decoder_decoded_andMatrixOutputs_lo_258 = cat(decoder_decoded_andMatrixOutputs_lo_hi_256, decoder_decoded_andMatrixOutputs_lo_lo_237) node decoder_decoded_andMatrixOutputs_hi_lo_lo_133 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_250, decoder_decoded_andMatrixOutputs_andMatrixInput_7_237) node decoder_decoded_andMatrixOutputs_hi_lo_hi_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_258, decoder_decoded_andMatrixOutputs_andMatrixInput_5_256) node decoder_decoded_andMatrixOutputs_hi_lo_250 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_161, decoder_decoded_andMatrixOutputs_hi_lo_lo_133) node decoder_decoded_andMatrixOutputs_hi_hi_lo_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_258, decoder_decoded_andMatrixOutputs_andMatrixInput_3_258) node decoder_decoded_andMatrixOutputs_hi_hi_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_258, decoder_decoded_andMatrixOutputs_andMatrixInput_1_258) node decoder_decoded_andMatrixOutputs_hi_hi_258 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_201, decoder_decoded_andMatrixOutputs_hi_hi_lo_151) node decoder_decoded_andMatrixOutputs_hi_258 = cat(decoder_decoded_andMatrixOutputs_hi_hi_258, decoder_decoded_andMatrixOutputs_hi_lo_250) node _decoder_decoded_andMatrixOutputs_T_258 = cat(decoder_decoded_andMatrixOutputs_hi_258, decoder_decoded_andMatrixOutputs_lo_258) node decoder_decoded_andMatrixOutputs_133_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_258) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_259 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_259 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_259 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_259 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_259 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_257 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_251 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_238 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_202 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_167 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_162 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_156 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_152 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_149 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_134 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_152, decoder_decoded_andMatrixOutputs_andMatrixInput_13_149) node decoder_decoded_andMatrixOutputs_lo_lo_238 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_156, decoder_decoded_andMatrixOutputs_andMatrixInput_14_134) node decoder_decoded_andMatrixOutputs_lo_hi_lo_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_162, decoder_decoded_andMatrixOutputs_andMatrixInput_11_156) node decoder_decoded_andMatrixOutputs_lo_hi_hi_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_202, decoder_decoded_andMatrixOutputs_andMatrixInput_9_167) node decoder_decoded_andMatrixOutputs_lo_hi_257 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_167, decoder_decoded_andMatrixOutputs_lo_hi_lo_149) node decoder_decoded_andMatrixOutputs_lo_259 = cat(decoder_decoded_andMatrixOutputs_lo_hi_257, decoder_decoded_andMatrixOutputs_lo_lo_238) node decoder_decoded_andMatrixOutputs_hi_lo_lo_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_251, decoder_decoded_andMatrixOutputs_andMatrixInput_7_238) node decoder_decoded_andMatrixOutputs_hi_lo_hi_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_259, decoder_decoded_andMatrixOutputs_andMatrixInput_5_257) node decoder_decoded_andMatrixOutputs_hi_lo_251 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_162, decoder_decoded_andMatrixOutputs_hi_lo_lo_134) node decoder_decoded_andMatrixOutputs_hi_hi_lo_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_259, decoder_decoded_andMatrixOutputs_andMatrixInput_3_259) node decoder_decoded_andMatrixOutputs_hi_hi_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_259, decoder_decoded_andMatrixOutputs_andMatrixInput_1_259) node decoder_decoded_andMatrixOutputs_hi_hi_259 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_202, decoder_decoded_andMatrixOutputs_hi_hi_lo_152) node decoder_decoded_andMatrixOutputs_hi_259 = cat(decoder_decoded_andMatrixOutputs_hi_hi_259, decoder_decoded_andMatrixOutputs_hi_lo_251) node _decoder_decoded_andMatrixOutputs_T_259 = cat(decoder_decoded_andMatrixOutputs_hi_259, decoder_decoded_andMatrixOutputs_lo_259) node decoder_decoded_andMatrixOutputs_179_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_259) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_260 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_260 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_260 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_260 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_260 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_258 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_252 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_239 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_203 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_168 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_163 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_157 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_153 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_150 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_135 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_84 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_135, decoder_decoded_andMatrixOutputs_andMatrixInput_15_84) node decoder_decoded_andMatrixOutputs_lo_lo_hi_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_153, decoder_decoded_andMatrixOutputs_andMatrixInput_13_150) node decoder_decoded_andMatrixOutputs_lo_lo_239 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_157, decoder_decoded_andMatrixOutputs_lo_lo_lo_84) node decoder_decoded_andMatrixOutputs_lo_hi_lo_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_163, decoder_decoded_andMatrixOutputs_andMatrixInput_11_157) node decoder_decoded_andMatrixOutputs_lo_hi_hi_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_203, decoder_decoded_andMatrixOutputs_andMatrixInput_9_168) node decoder_decoded_andMatrixOutputs_lo_hi_258 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_168, decoder_decoded_andMatrixOutputs_lo_hi_lo_150) node decoder_decoded_andMatrixOutputs_lo_260 = cat(decoder_decoded_andMatrixOutputs_lo_hi_258, decoder_decoded_andMatrixOutputs_lo_lo_239) node decoder_decoded_andMatrixOutputs_hi_lo_lo_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_252, decoder_decoded_andMatrixOutputs_andMatrixInput_7_239) node decoder_decoded_andMatrixOutputs_hi_lo_hi_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_260, decoder_decoded_andMatrixOutputs_andMatrixInput_5_258) node decoder_decoded_andMatrixOutputs_hi_lo_252 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_163, decoder_decoded_andMatrixOutputs_hi_lo_lo_135) node decoder_decoded_andMatrixOutputs_hi_hi_lo_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_260, decoder_decoded_andMatrixOutputs_andMatrixInput_3_260) node decoder_decoded_andMatrixOutputs_hi_hi_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_260, decoder_decoded_andMatrixOutputs_andMatrixInput_1_260) node decoder_decoded_andMatrixOutputs_hi_hi_260 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_203, decoder_decoded_andMatrixOutputs_hi_hi_lo_153) node decoder_decoded_andMatrixOutputs_hi_260 = cat(decoder_decoded_andMatrixOutputs_hi_hi_260, decoder_decoded_andMatrixOutputs_hi_lo_252) node _decoder_decoded_andMatrixOutputs_T_260 = cat(decoder_decoded_andMatrixOutputs_hi_260, decoder_decoded_andMatrixOutputs_lo_260) node decoder_decoded_andMatrixOutputs_5_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_260) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_261 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_261 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_261 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_261 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_261 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_259 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_253 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_240 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_204 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_169 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_164 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_158 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_154 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_151 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_136 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_154, decoder_decoded_andMatrixOutputs_andMatrixInput_13_151) node decoder_decoded_andMatrixOutputs_lo_lo_240 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_158, decoder_decoded_andMatrixOutputs_andMatrixInput_14_136) node decoder_decoded_andMatrixOutputs_lo_hi_lo_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_164, decoder_decoded_andMatrixOutputs_andMatrixInput_11_158) node decoder_decoded_andMatrixOutputs_lo_hi_hi_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_204, decoder_decoded_andMatrixOutputs_andMatrixInput_9_169) node decoder_decoded_andMatrixOutputs_lo_hi_259 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_169, decoder_decoded_andMatrixOutputs_lo_hi_lo_151) node decoder_decoded_andMatrixOutputs_lo_261 = cat(decoder_decoded_andMatrixOutputs_lo_hi_259, decoder_decoded_andMatrixOutputs_lo_lo_240) node decoder_decoded_andMatrixOutputs_hi_lo_lo_136 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_253, decoder_decoded_andMatrixOutputs_andMatrixInput_7_240) node decoder_decoded_andMatrixOutputs_hi_lo_hi_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_261, decoder_decoded_andMatrixOutputs_andMatrixInput_5_259) node decoder_decoded_andMatrixOutputs_hi_lo_253 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_164, decoder_decoded_andMatrixOutputs_hi_lo_lo_136) node decoder_decoded_andMatrixOutputs_hi_hi_lo_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_261, decoder_decoded_andMatrixOutputs_andMatrixInput_3_261) node decoder_decoded_andMatrixOutputs_hi_hi_hi_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_261, decoder_decoded_andMatrixOutputs_andMatrixInput_1_261) node decoder_decoded_andMatrixOutputs_hi_hi_261 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_204, decoder_decoded_andMatrixOutputs_hi_hi_lo_154) node decoder_decoded_andMatrixOutputs_hi_261 = cat(decoder_decoded_andMatrixOutputs_hi_hi_261, decoder_decoded_andMatrixOutputs_hi_lo_253) node _decoder_decoded_andMatrixOutputs_T_261 = cat(decoder_decoded_andMatrixOutputs_hi_261, decoder_decoded_andMatrixOutputs_lo_261) node decoder_decoded_andMatrixOutputs_87_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_261) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_262 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_262 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_262 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_262 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_262 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_260 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_254 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_241 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_205 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_170 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_165 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_159 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_155 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_152 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_137 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_155, decoder_decoded_andMatrixOutputs_andMatrixInput_13_152) node decoder_decoded_andMatrixOutputs_lo_lo_241 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_159, decoder_decoded_andMatrixOutputs_andMatrixInput_14_137) node decoder_decoded_andMatrixOutputs_lo_hi_lo_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_165, decoder_decoded_andMatrixOutputs_andMatrixInput_11_159) node decoder_decoded_andMatrixOutputs_lo_hi_hi_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_205, decoder_decoded_andMatrixOutputs_andMatrixInput_9_170) node decoder_decoded_andMatrixOutputs_lo_hi_260 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_170, decoder_decoded_andMatrixOutputs_lo_hi_lo_152) node decoder_decoded_andMatrixOutputs_lo_262 = cat(decoder_decoded_andMatrixOutputs_lo_hi_260, decoder_decoded_andMatrixOutputs_lo_lo_241) node decoder_decoded_andMatrixOutputs_hi_lo_lo_137 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_254, decoder_decoded_andMatrixOutputs_andMatrixInput_7_241) node decoder_decoded_andMatrixOutputs_hi_lo_hi_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_262, decoder_decoded_andMatrixOutputs_andMatrixInput_5_260) node decoder_decoded_andMatrixOutputs_hi_lo_254 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_165, decoder_decoded_andMatrixOutputs_hi_lo_lo_137) node decoder_decoded_andMatrixOutputs_hi_hi_lo_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_262, decoder_decoded_andMatrixOutputs_andMatrixInput_3_262) node decoder_decoded_andMatrixOutputs_hi_hi_hi_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_262, decoder_decoded_andMatrixOutputs_andMatrixInput_1_262) node decoder_decoded_andMatrixOutputs_hi_hi_262 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_205, decoder_decoded_andMatrixOutputs_hi_hi_lo_155) node decoder_decoded_andMatrixOutputs_hi_262 = cat(decoder_decoded_andMatrixOutputs_hi_hi_262, decoder_decoded_andMatrixOutputs_hi_lo_254) node _decoder_decoded_andMatrixOutputs_T_262 = cat(decoder_decoded_andMatrixOutputs_hi_262, decoder_decoded_andMatrixOutputs_lo_262) node decoder_decoded_andMatrixOutputs_93_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_262) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_263 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_263 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_263 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_263 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_263 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_261 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_255 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_242 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_255, decoder_decoded_andMatrixOutputs_andMatrixInput_7_242) node decoder_decoded_andMatrixOutputs_lo_hi_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_263, decoder_decoded_andMatrixOutputs_andMatrixInput_5_261) node decoder_decoded_andMatrixOutputs_lo_263 = cat(decoder_decoded_andMatrixOutputs_lo_hi_261, decoder_decoded_andMatrixOutputs_lo_lo_242) node decoder_decoded_andMatrixOutputs_hi_lo_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_263, decoder_decoded_andMatrixOutputs_andMatrixInput_3_263) node decoder_decoded_andMatrixOutputs_hi_hi_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_263, decoder_decoded_andMatrixOutputs_andMatrixInput_1_263) node decoder_decoded_andMatrixOutputs_hi_263 = cat(decoder_decoded_andMatrixOutputs_hi_hi_263, decoder_decoded_andMatrixOutputs_hi_lo_255) node _decoder_decoded_andMatrixOutputs_T_263 = cat(decoder_decoded_andMatrixOutputs_hi_263, decoder_decoded_andMatrixOutputs_lo_263) node decoder_decoded_andMatrixOutputs_65_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_263) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_264 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_264 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_264 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_264 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_264 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_262 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_256 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_243 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_206 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_243, decoder_decoded_andMatrixOutputs_andMatrixInput_8_206) node decoder_decoded_andMatrixOutputs_lo_hi_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_262, decoder_decoded_andMatrixOutputs_andMatrixInput_6_256) node decoder_decoded_andMatrixOutputs_lo_264 = cat(decoder_decoded_andMatrixOutputs_lo_hi_262, decoder_decoded_andMatrixOutputs_lo_lo_243) node decoder_decoded_andMatrixOutputs_hi_lo_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_264, decoder_decoded_andMatrixOutputs_andMatrixInput_4_264) node decoder_decoded_andMatrixOutputs_hi_hi_hi_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_264, decoder_decoded_andMatrixOutputs_andMatrixInput_1_264) node decoder_decoded_andMatrixOutputs_hi_hi_264 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_206, decoder_decoded_andMatrixOutputs_andMatrixInput_2_264) node decoder_decoded_andMatrixOutputs_hi_264 = cat(decoder_decoded_andMatrixOutputs_hi_hi_264, decoder_decoded_andMatrixOutputs_hi_lo_256) node _decoder_decoded_andMatrixOutputs_T_264 = cat(decoder_decoded_andMatrixOutputs_hi_264, decoder_decoded_andMatrixOutputs_lo_264) node decoder_decoded_andMatrixOutputs_125_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_264) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_265 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_265 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_265 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_265 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_265 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_263 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_257 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_244 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_207 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_244, decoder_decoded_andMatrixOutputs_andMatrixInput_8_207) node decoder_decoded_andMatrixOutputs_lo_hi_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_263, decoder_decoded_andMatrixOutputs_andMatrixInput_6_257) node decoder_decoded_andMatrixOutputs_lo_265 = cat(decoder_decoded_andMatrixOutputs_lo_hi_263, decoder_decoded_andMatrixOutputs_lo_lo_244) node decoder_decoded_andMatrixOutputs_hi_lo_257 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_265, decoder_decoded_andMatrixOutputs_andMatrixInput_4_265) node decoder_decoded_andMatrixOutputs_hi_hi_hi_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_265, decoder_decoded_andMatrixOutputs_andMatrixInput_1_265) node decoder_decoded_andMatrixOutputs_hi_hi_265 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_207, decoder_decoded_andMatrixOutputs_andMatrixInput_2_265) node decoder_decoded_andMatrixOutputs_hi_265 = cat(decoder_decoded_andMatrixOutputs_hi_hi_265, decoder_decoded_andMatrixOutputs_hi_lo_257) node _decoder_decoded_andMatrixOutputs_T_265 = cat(decoder_decoded_andMatrixOutputs_hi_265, decoder_decoded_andMatrixOutputs_lo_265) node decoder_decoded_andMatrixOutputs_90_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_265) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_266 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_266 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_266 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_266 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_266 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_264 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_258 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_245 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_208 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_245 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_245, decoder_decoded_andMatrixOutputs_andMatrixInput_8_208) node decoder_decoded_andMatrixOutputs_lo_hi_264 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_264, decoder_decoded_andMatrixOutputs_andMatrixInput_6_258) node decoder_decoded_andMatrixOutputs_lo_266 = cat(decoder_decoded_andMatrixOutputs_lo_hi_264, decoder_decoded_andMatrixOutputs_lo_lo_245) node decoder_decoded_andMatrixOutputs_hi_lo_258 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_266, decoder_decoded_andMatrixOutputs_andMatrixInput_4_266) node decoder_decoded_andMatrixOutputs_hi_hi_hi_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_266, decoder_decoded_andMatrixOutputs_andMatrixInput_1_266) node decoder_decoded_andMatrixOutputs_hi_hi_266 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_208, decoder_decoded_andMatrixOutputs_andMatrixInput_2_266) node decoder_decoded_andMatrixOutputs_hi_266 = cat(decoder_decoded_andMatrixOutputs_hi_hi_266, decoder_decoded_andMatrixOutputs_hi_lo_258) node _decoder_decoded_andMatrixOutputs_T_266 = cat(decoder_decoded_andMatrixOutputs_hi_266, decoder_decoded_andMatrixOutputs_lo_266) node decoder_decoded_andMatrixOutputs_111_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_266) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_267 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_267 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_267 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_267 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_267 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_265 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_259 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_246 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_209 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_171 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_166 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_160 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_156 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_153 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_138 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_156, decoder_decoded_andMatrixOutputs_andMatrixInput_13_153) node decoder_decoded_andMatrixOutputs_lo_lo_246 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_14_138) node decoder_decoded_andMatrixOutputs_lo_hi_lo_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_166, decoder_decoded_andMatrixOutputs_andMatrixInput_11_160) node decoder_decoded_andMatrixOutputs_lo_hi_hi_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_209, decoder_decoded_andMatrixOutputs_andMatrixInput_9_171) node decoder_decoded_andMatrixOutputs_lo_hi_265 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_171, decoder_decoded_andMatrixOutputs_lo_hi_lo_153) node decoder_decoded_andMatrixOutputs_lo_267 = cat(decoder_decoded_andMatrixOutputs_lo_hi_265, decoder_decoded_andMatrixOutputs_lo_lo_246) node decoder_decoded_andMatrixOutputs_hi_lo_lo_138 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_259, decoder_decoded_andMatrixOutputs_andMatrixInput_7_246) node decoder_decoded_andMatrixOutputs_hi_lo_hi_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_267, decoder_decoded_andMatrixOutputs_andMatrixInput_5_265) node decoder_decoded_andMatrixOutputs_hi_lo_259 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_166, decoder_decoded_andMatrixOutputs_hi_lo_lo_138) node decoder_decoded_andMatrixOutputs_hi_hi_lo_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_267, decoder_decoded_andMatrixOutputs_andMatrixInput_3_267) node decoder_decoded_andMatrixOutputs_hi_hi_hi_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_267, decoder_decoded_andMatrixOutputs_andMatrixInput_1_267) node decoder_decoded_andMatrixOutputs_hi_hi_267 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_209, decoder_decoded_andMatrixOutputs_hi_hi_lo_156) node decoder_decoded_andMatrixOutputs_hi_267 = cat(decoder_decoded_andMatrixOutputs_hi_hi_267, decoder_decoded_andMatrixOutputs_hi_lo_259) node _decoder_decoded_andMatrixOutputs_T_267 = cat(decoder_decoded_andMatrixOutputs_hi_267, decoder_decoded_andMatrixOutputs_lo_267) node decoder_decoded_andMatrixOutputs_172_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_267) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_268 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_268 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_268 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_268 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_268 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_266 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_260 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_247 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_260, decoder_decoded_andMatrixOutputs_andMatrixInput_7_247) node decoder_decoded_andMatrixOutputs_lo_hi_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_268, decoder_decoded_andMatrixOutputs_andMatrixInput_5_266) node decoder_decoded_andMatrixOutputs_lo_268 = cat(decoder_decoded_andMatrixOutputs_lo_hi_266, decoder_decoded_andMatrixOutputs_lo_lo_247) node decoder_decoded_andMatrixOutputs_hi_lo_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_268, decoder_decoded_andMatrixOutputs_andMatrixInput_3_268) node decoder_decoded_andMatrixOutputs_hi_hi_268 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_268, decoder_decoded_andMatrixOutputs_andMatrixInput_1_268) node decoder_decoded_andMatrixOutputs_hi_268 = cat(decoder_decoded_andMatrixOutputs_hi_hi_268, decoder_decoded_andMatrixOutputs_hi_lo_260) node _decoder_decoded_andMatrixOutputs_T_268 = cat(decoder_decoded_andMatrixOutputs_hi_268, decoder_decoded_andMatrixOutputs_lo_268) node decoder_decoded_andMatrixOutputs_146_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_268) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_269 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_269 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_269 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_269 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_269 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_267 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_261 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_248 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_210 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_248, decoder_decoded_andMatrixOutputs_andMatrixInput_8_210) node decoder_decoded_andMatrixOutputs_lo_hi_267 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_267, decoder_decoded_andMatrixOutputs_andMatrixInput_6_261) node decoder_decoded_andMatrixOutputs_lo_269 = cat(decoder_decoded_andMatrixOutputs_lo_hi_267, decoder_decoded_andMatrixOutputs_lo_lo_248) node decoder_decoded_andMatrixOutputs_hi_lo_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_269, decoder_decoded_andMatrixOutputs_andMatrixInput_4_269) node decoder_decoded_andMatrixOutputs_hi_hi_hi_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_269, decoder_decoded_andMatrixOutputs_andMatrixInput_1_269) node decoder_decoded_andMatrixOutputs_hi_hi_269 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_2_269) node decoder_decoded_andMatrixOutputs_hi_269 = cat(decoder_decoded_andMatrixOutputs_hi_hi_269, decoder_decoded_andMatrixOutputs_hi_lo_261) node _decoder_decoded_andMatrixOutputs_T_269 = cat(decoder_decoded_andMatrixOutputs_hi_269, decoder_decoded_andMatrixOutputs_lo_269) node decoder_decoded_andMatrixOutputs_170_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_269) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_270 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_270 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_270 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_270 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_270 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_268 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_262 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_249 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_211 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_249, decoder_decoded_andMatrixOutputs_andMatrixInput_8_211) node decoder_decoded_andMatrixOutputs_lo_hi_268 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_268, decoder_decoded_andMatrixOutputs_andMatrixInput_6_262) node decoder_decoded_andMatrixOutputs_lo_270 = cat(decoder_decoded_andMatrixOutputs_lo_hi_268, decoder_decoded_andMatrixOutputs_lo_lo_249) node decoder_decoded_andMatrixOutputs_hi_lo_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_270, decoder_decoded_andMatrixOutputs_andMatrixInput_4_270) node decoder_decoded_andMatrixOutputs_hi_hi_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_270, decoder_decoded_andMatrixOutputs_andMatrixInput_1_270) node decoder_decoded_andMatrixOutputs_hi_hi_270 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_2_270) node decoder_decoded_andMatrixOutputs_hi_270 = cat(decoder_decoded_andMatrixOutputs_hi_hi_270, decoder_decoded_andMatrixOutputs_hi_lo_262) node _decoder_decoded_andMatrixOutputs_T_270 = cat(decoder_decoded_andMatrixOutputs_hi_270, decoder_decoded_andMatrixOutputs_lo_270) node decoder_decoded_andMatrixOutputs_2_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_270) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_271 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_271 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_271 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_271 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_271 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_269 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_263 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_250 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_212 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_172 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_212, decoder_decoded_andMatrixOutputs_andMatrixInput_9_172) node decoder_decoded_andMatrixOutputs_lo_hi_hi_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_269, decoder_decoded_andMatrixOutputs_andMatrixInput_6_263) node decoder_decoded_andMatrixOutputs_lo_hi_269 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_7_250) node decoder_decoded_andMatrixOutputs_lo_271 = cat(decoder_decoded_andMatrixOutputs_lo_hi_269, decoder_decoded_andMatrixOutputs_lo_lo_250) node decoder_decoded_andMatrixOutputs_hi_lo_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_271, decoder_decoded_andMatrixOutputs_andMatrixInput_4_271) node decoder_decoded_andMatrixOutputs_hi_hi_hi_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_271, decoder_decoded_andMatrixOutputs_andMatrixInput_1_271) node decoder_decoded_andMatrixOutputs_hi_hi_271 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_2_271) node decoder_decoded_andMatrixOutputs_hi_271 = cat(decoder_decoded_andMatrixOutputs_hi_hi_271, decoder_decoded_andMatrixOutputs_hi_lo_263) node _decoder_decoded_andMatrixOutputs_T_271 = cat(decoder_decoded_andMatrixOutputs_hi_271, decoder_decoded_andMatrixOutputs_lo_271) node decoder_decoded_andMatrixOutputs_15_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_271) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_272 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_272 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_272 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_272 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_272 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_270 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_264 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_251 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_213 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_173 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_167 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_161 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_157 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_154 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_139 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_157, decoder_decoded_andMatrixOutputs_andMatrixInput_13_154) node decoder_decoded_andMatrixOutputs_lo_lo_251 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_161, decoder_decoded_andMatrixOutputs_andMatrixInput_14_139) node decoder_decoded_andMatrixOutputs_lo_hi_lo_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_167, decoder_decoded_andMatrixOutputs_andMatrixInput_11_161) node decoder_decoded_andMatrixOutputs_lo_hi_hi_173 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_213, decoder_decoded_andMatrixOutputs_andMatrixInput_9_173) node decoder_decoded_andMatrixOutputs_lo_hi_270 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_173, decoder_decoded_andMatrixOutputs_lo_hi_lo_154) node decoder_decoded_andMatrixOutputs_lo_272 = cat(decoder_decoded_andMatrixOutputs_lo_hi_270, decoder_decoded_andMatrixOutputs_lo_lo_251) node decoder_decoded_andMatrixOutputs_hi_lo_lo_139 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_264, decoder_decoded_andMatrixOutputs_andMatrixInput_7_251) node decoder_decoded_andMatrixOutputs_hi_lo_hi_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_272, decoder_decoded_andMatrixOutputs_andMatrixInput_5_270) node decoder_decoded_andMatrixOutputs_hi_lo_264 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_167, decoder_decoded_andMatrixOutputs_hi_lo_lo_139) node decoder_decoded_andMatrixOutputs_hi_hi_lo_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_272, decoder_decoded_andMatrixOutputs_andMatrixInput_3_272) node decoder_decoded_andMatrixOutputs_hi_hi_hi_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_272, decoder_decoded_andMatrixOutputs_andMatrixInput_1_272) node decoder_decoded_andMatrixOutputs_hi_hi_272 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_213, decoder_decoded_andMatrixOutputs_hi_hi_lo_157) node decoder_decoded_andMatrixOutputs_hi_272 = cat(decoder_decoded_andMatrixOutputs_hi_hi_272, decoder_decoded_andMatrixOutputs_hi_lo_264) node _decoder_decoded_andMatrixOutputs_T_272 = cat(decoder_decoded_andMatrixOutputs_hi_272, decoder_decoded_andMatrixOutputs_lo_272) node decoder_decoded_andMatrixOutputs_167_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_272) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_273 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_273 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_273 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_273 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_273 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_271 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_265 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_252 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_214 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_174 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_168 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_162 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_158 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_155 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_140 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_85 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_140, decoder_decoded_andMatrixOutputs_andMatrixInput_15_85) node decoder_decoded_andMatrixOutputs_lo_lo_hi_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_158, decoder_decoded_andMatrixOutputs_andMatrixInput_13_155) node decoder_decoded_andMatrixOutputs_lo_lo_252 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_162, decoder_decoded_andMatrixOutputs_lo_lo_lo_85) node decoder_decoded_andMatrixOutputs_lo_hi_lo_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_168, decoder_decoded_andMatrixOutputs_andMatrixInput_11_162) node decoder_decoded_andMatrixOutputs_lo_hi_hi_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_214, decoder_decoded_andMatrixOutputs_andMatrixInput_9_174) node decoder_decoded_andMatrixOutputs_lo_hi_271 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_174, decoder_decoded_andMatrixOutputs_lo_hi_lo_155) node decoder_decoded_andMatrixOutputs_lo_273 = cat(decoder_decoded_andMatrixOutputs_lo_hi_271, decoder_decoded_andMatrixOutputs_lo_lo_252) node decoder_decoded_andMatrixOutputs_hi_lo_lo_140 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_265, decoder_decoded_andMatrixOutputs_andMatrixInput_7_252) node decoder_decoded_andMatrixOutputs_hi_lo_hi_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_273, decoder_decoded_andMatrixOutputs_andMatrixInput_5_271) node decoder_decoded_andMatrixOutputs_hi_lo_265 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_168, decoder_decoded_andMatrixOutputs_hi_lo_lo_140) node decoder_decoded_andMatrixOutputs_hi_hi_lo_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_273, decoder_decoded_andMatrixOutputs_andMatrixInput_3_273) node decoder_decoded_andMatrixOutputs_hi_hi_hi_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_273, decoder_decoded_andMatrixOutputs_andMatrixInput_1_273) node decoder_decoded_andMatrixOutputs_hi_hi_273 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_214, decoder_decoded_andMatrixOutputs_hi_hi_lo_158) node decoder_decoded_andMatrixOutputs_hi_273 = cat(decoder_decoded_andMatrixOutputs_hi_hi_273, decoder_decoded_andMatrixOutputs_hi_lo_265) node _decoder_decoded_andMatrixOutputs_T_273 = cat(decoder_decoded_andMatrixOutputs_hi_273, decoder_decoded_andMatrixOutputs_lo_273) node decoder_decoded_andMatrixOutputs_108_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_273) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_274 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_274 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_274 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_274 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_274 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_272 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_266 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi_272 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_274, decoder_decoded_andMatrixOutputs_andMatrixInput_5_272) node decoder_decoded_andMatrixOutputs_lo_274 = cat(decoder_decoded_andMatrixOutputs_lo_hi_272, decoder_decoded_andMatrixOutputs_andMatrixInput_6_266) node decoder_decoded_andMatrixOutputs_hi_lo_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_274, decoder_decoded_andMatrixOutputs_andMatrixInput_3_274) node decoder_decoded_andMatrixOutputs_hi_hi_274 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_274, decoder_decoded_andMatrixOutputs_andMatrixInput_1_274) node decoder_decoded_andMatrixOutputs_hi_274 = cat(decoder_decoded_andMatrixOutputs_hi_hi_274, decoder_decoded_andMatrixOutputs_hi_lo_266) node _decoder_decoded_andMatrixOutputs_T_274 = cat(decoder_decoded_andMatrixOutputs_hi_274, decoder_decoded_andMatrixOutputs_lo_274) node decoder_decoded_andMatrixOutputs_75_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_274) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_275 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_275 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_275 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_275 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_275 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_273 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_267 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_253 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_215 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_175 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_169 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_163 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_175, decoder_decoded_andMatrixOutputs_andMatrixInput_10_169) node decoder_decoded_andMatrixOutputs_lo_lo_253 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_163, decoder_decoded_andMatrixOutputs_andMatrixInput_11_163) node decoder_decoded_andMatrixOutputs_lo_hi_hi_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_267, decoder_decoded_andMatrixOutputs_andMatrixInput_7_253) node decoder_decoded_andMatrixOutputs_lo_hi_273 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_175, decoder_decoded_andMatrixOutputs_andMatrixInput_8_215) node decoder_decoded_andMatrixOutputs_lo_275 = cat(decoder_decoded_andMatrixOutputs_lo_hi_273, decoder_decoded_andMatrixOutputs_lo_lo_253) node decoder_decoded_andMatrixOutputs_hi_lo_hi_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_275, decoder_decoded_andMatrixOutputs_andMatrixInput_4_275) node decoder_decoded_andMatrixOutputs_hi_lo_267 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_169, decoder_decoded_andMatrixOutputs_andMatrixInput_5_273) node decoder_decoded_andMatrixOutputs_hi_hi_hi_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_275, decoder_decoded_andMatrixOutputs_andMatrixInput_1_275) node decoder_decoded_andMatrixOutputs_hi_hi_275 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_2_275) node decoder_decoded_andMatrixOutputs_hi_275 = cat(decoder_decoded_andMatrixOutputs_hi_hi_275, decoder_decoded_andMatrixOutputs_hi_lo_267) node _decoder_decoded_andMatrixOutputs_T_275 = cat(decoder_decoded_andMatrixOutputs_hi_275, decoder_decoded_andMatrixOutputs_lo_275) node decoder_decoded_andMatrixOutputs_86_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_275) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_276 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_276 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_276 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_276 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_276 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_274 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_268 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_254 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_216 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_176 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_170 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_164 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_159 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_156 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_141 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_159, decoder_decoded_andMatrixOutputs_andMatrixInput_13_156) node decoder_decoded_andMatrixOutputs_lo_lo_254 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_164, decoder_decoded_andMatrixOutputs_andMatrixInput_14_141) node decoder_decoded_andMatrixOutputs_lo_hi_lo_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_170, decoder_decoded_andMatrixOutputs_andMatrixInput_11_164) node decoder_decoded_andMatrixOutputs_lo_hi_hi_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_216, decoder_decoded_andMatrixOutputs_andMatrixInput_9_176) node decoder_decoded_andMatrixOutputs_lo_hi_274 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_176, decoder_decoded_andMatrixOutputs_lo_hi_lo_156) node decoder_decoded_andMatrixOutputs_lo_276 = cat(decoder_decoded_andMatrixOutputs_lo_hi_274, decoder_decoded_andMatrixOutputs_lo_lo_254) node decoder_decoded_andMatrixOutputs_hi_lo_lo_141 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_268, decoder_decoded_andMatrixOutputs_andMatrixInput_7_254) node decoder_decoded_andMatrixOutputs_hi_lo_hi_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_276, decoder_decoded_andMatrixOutputs_andMatrixInput_5_274) node decoder_decoded_andMatrixOutputs_hi_lo_268 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_170, decoder_decoded_andMatrixOutputs_hi_lo_lo_141) node decoder_decoded_andMatrixOutputs_hi_hi_lo_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_276, decoder_decoded_andMatrixOutputs_andMatrixInput_3_276) node decoder_decoded_andMatrixOutputs_hi_hi_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_276, decoder_decoded_andMatrixOutputs_andMatrixInput_1_276) node decoder_decoded_andMatrixOutputs_hi_hi_276 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_216, decoder_decoded_andMatrixOutputs_hi_hi_lo_159) node decoder_decoded_andMatrixOutputs_hi_276 = cat(decoder_decoded_andMatrixOutputs_hi_hi_276, decoder_decoded_andMatrixOutputs_hi_lo_268) node _decoder_decoded_andMatrixOutputs_T_276 = cat(decoder_decoded_andMatrixOutputs_hi_276, decoder_decoded_andMatrixOutputs_lo_276) node decoder_decoded_andMatrixOutputs_144_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_276) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_277 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_277 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_277 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_277 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_277 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_275 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_269 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_255 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_217 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_177 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_171 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_165 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_160 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_157 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_142 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_160, decoder_decoded_andMatrixOutputs_andMatrixInput_13_157) node decoder_decoded_andMatrixOutputs_lo_lo_255 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_165, decoder_decoded_andMatrixOutputs_andMatrixInput_14_142) node decoder_decoded_andMatrixOutputs_lo_hi_lo_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_171, decoder_decoded_andMatrixOutputs_andMatrixInput_11_165) node decoder_decoded_andMatrixOutputs_lo_hi_hi_177 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_217, decoder_decoded_andMatrixOutputs_andMatrixInput_9_177) node decoder_decoded_andMatrixOutputs_lo_hi_275 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_177, decoder_decoded_andMatrixOutputs_lo_hi_lo_157) node decoder_decoded_andMatrixOutputs_lo_277 = cat(decoder_decoded_andMatrixOutputs_lo_hi_275, decoder_decoded_andMatrixOutputs_lo_lo_255) node decoder_decoded_andMatrixOutputs_hi_lo_lo_142 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_269, decoder_decoded_andMatrixOutputs_andMatrixInput_7_255) node decoder_decoded_andMatrixOutputs_hi_lo_hi_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_277, decoder_decoded_andMatrixOutputs_andMatrixInput_5_275) node decoder_decoded_andMatrixOutputs_hi_lo_269 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_171, decoder_decoded_andMatrixOutputs_hi_lo_lo_142) node decoder_decoded_andMatrixOutputs_hi_hi_lo_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_277, decoder_decoded_andMatrixOutputs_andMatrixInput_3_277) node decoder_decoded_andMatrixOutputs_hi_hi_hi_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_277, decoder_decoded_andMatrixOutputs_andMatrixInput_1_277) node decoder_decoded_andMatrixOutputs_hi_hi_277 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_217, decoder_decoded_andMatrixOutputs_hi_hi_lo_160) node decoder_decoded_andMatrixOutputs_hi_277 = cat(decoder_decoded_andMatrixOutputs_hi_hi_277, decoder_decoded_andMatrixOutputs_hi_lo_269) node _decoder_decoded_andMatrixOutputs_T_277 = cat(decoder_decoded_andMatrixOutputs_hi_277, decoder_decoded_andMatrixOutputs_lo_277) node decoder_decoded_andMatrixOutputs_36_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_277) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_278 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_278 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_278 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_278 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_278 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_276 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_270 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_256 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_218 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_178 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_172 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_166 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_161 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_158 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_166, decoder_decoded_andMatrixOutputs_andMatrixInput_12_161) node decoder_decoded_andMatrixOutputs_lo_lo_256 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_166, decoder_decoded_andMatrixOutputs_andMatrixInput_13_158) node decoder_decoded_andMatrixOutputs_lo_hi_lo_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_178, decoder_decoded_andMatrixOutputs_andMatrixInput_10_172) node decoder_decoded_andMatrixOutputs_lo_hi_hi_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_256, decoder_decoded_andMatrixOutputs_andMatrixInput_8_218) node decoder_decoded_andMatrixOutputs_lo_hi_276 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_178, decoder_decoded_andMatrixOutputs_lo_hi_lo_158) node decoder_decoded_andMatrixOutputs_lo_278 = cat(decoder_decoded_andMatrixOutputs_lo_hi_276, decoder_decoded_andMatrixOutputs_lo_lo_256) node decoder_decoded_andMatrixOutputs_hi_lo_hi_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_278, decoder_decoded_andMatrixOutputs_andMatrixInput_5_276) node decoder_decoded_andMatrixOutputs_hi_lo_270 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_6_270) node decoder_decoded_andMatrixOutputs_hi_hi_lo_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_278, decoder_decoded_andMatrixOutputs_andMatrixInput_3_278) node decoder_decoded_andMatrixOutputs_hi_hi_hi_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_278, decoder_decoded_andMatrixOutputs_andMatrixInput_1_278) node decoder_decoded_andMatrixOutputs_hi_hi_278 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_218, decoder_decoded_andMatrixOutputs_hi_hi_lo_161) node decoder_decoded_andMatrixOutputs_hi_278 = cat(decoder_decoded_andMatrixOutputs_hi_hi_278, decoder_decoded_andMatrixOutputs_hi_lo_270) node _decoder_decoded_andMatrixOutputs_T_278 = cat(decoder_decoded_andMatrixOutputs_hi_278, decoder_decoded_andMatrixOutputs_lo_278) node decoder_decoded_andMatrixOutputs_41_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_278) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_279 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_279 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_279 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_279 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_279 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_277 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_271 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_257 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_219 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_179 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_173 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_167 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_162 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_159 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_167, decoder_decoded_andMatrixOutputs_andMatrixInput_12_162) node decoder_decoded_andMatrixOutputs_lo_lo_257 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_167, decoder_decoded_andMatrixOutputs_andMatrixInput_13_159) node decoder_decoded_andMatrixOutputs_lo_hi_lo_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_179, decoder_decoded_andMatrixOutputs_andMatrixInput_10_173) node decoder_decoded_andMatrixOutputs_lo_hi_hi_179 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_257, decoder_decoded_andMatrixOutputs_andMatrixInput_8_219) node decoder_decoded_andMatrixOutputs_lo_hi_277 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_179, decoder_decoded_andMatrixOutputs_lo_hi_lo_159) node decoder_decoded_andMatrixOutputs_lo_279 = cat(decoder_decoded_andMatrixOutputs_lo_hi_277, decoder_decoded_andMatrixOutputs_lo_lo_257) node decoder_decoded_andMatrixOutputs_hi_lo_hi_173 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_279, decoder_decoded_andMatrixOutputs_andMatrixInput_5_277) node decoder_decoded_andMatrixOutputs_hi_lo_271 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_173, decoder_decoded_andMatrixOutputs_andMatrixInput_6_271) node decoder_decoded_andMatrixOutputs_hi_hi_lo_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_279, decoder_decoded_andMatrixOutputs_andMatrixInput_3_279) node decoder_decoded_andMatrixOutputs_hi_hi_hi_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_279, decoder_decoded_andMatrixOutputs_andMatrixInput_1_279) node decoder_decoded_andMatrixOutputs_hi_hi_279 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_219, decoder_decoded_andMatrixOutputs_hi_hi_lo_162) node decoder_decoded_andMatrixOutputs_hi_279 = cat(decoder_decoded_andMatrixOutputs_hi_hi_279, decoder_decoded_andMatrixOutputs_hi_lo_271) node _decoder_decoded_andMatrixOutputs_T_279 = cat(decoder_decoded_andMatrixOutputs_hi_279, decoder_decoded_andMatrixOutputs_lo_279) node decoder_decoded_andMatrixOutputs_8_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_279) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_280 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_280 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_280 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_280 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_280 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_278 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_272 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_258 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_220 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_180 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_174 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_168 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_163 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_160 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_143 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_163, decoder_decoded_andMatrixOutputs_andMatrixInput_13_160) node decoder_decoded_andMatrixOutputs_lo_lo_258 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_168, decoder_decoded_andMatrixOutputs_andMatrixInput_14_143) node decoder_decoded_andMatrixOutputs_lo_hi_lo_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_174, decoder_decoded_andMatrixOutputs_andMatrixInput_11_168) node decoder_decoded_andMatrixOutputs_lo_hi_hi_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_220, decoder_decoded_andMatrixOutputs_andMatrixInput_9_180) node decoder_decoded_andMatrixOutputs_lo_hi_278 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_180, decoder_decoded_andMatrixOutputs_lo_hi_lo_160) node decoder_decoded_andMatrixOutputs_lo_280 = cat(decoder_decoded_andMatrixOutputs_lo_hi_278, decoder_decoded_andMatrixOutputs_lo_lo_258) node decoder_decoded_andMatrixOutputs_hi_lo_lo_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_272, decoder_decoded_andMatrixOutputs_andMatrixInput_7_258) node decoder_decoded_andMatrixOutputs_hi_lo_hi_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_280, decoder_decoded_andMatrixOutputs_andMatrixInput_5_278) node decoder_decoded_andMatrixOutputs_hi_lo_272 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_174, decoder_decoded_andMatrixOutputs_hi_lo_lo_143) node decoder_decoded_andMatrixOutputs_hi_hi_lo_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_280, decoder_decoded_andMatrixOutputs_andMatrixInput_3_280) node decoder_decoded_andMatrixOutputs_hi_hi_hi_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_280, decoder_decoded_andMatrixOutputs_andMatrixInput_1_280) node decoder_decoded_andMatrixOutputs_hi_hi_280 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_220, decoder_decoded_andMatrixOutputs_hi_hi_lo_163) node decoder_decoded_andMatrixOutputs_hi_280 = cat(decoder_decoded_andMatrixOutputs_hi_hi_280, decoder_decoded_andMatrixOutputs_hi_lo_272) node _decoder_decoded_andMatrixOutputs_T_280 = cat(decoder_decoded_andMatrixOutputs_hi_280, decoder_decoded_andMatrixOutputs_lo_280) node decoder_decoded_andMatrixOutputs_102_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_280) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_281 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_281 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_281 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_281 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_281 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_279 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_273 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_259 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_221 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_181 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_175 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_169 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_164 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_161 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_144 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_164, decoder_decoded_andMatrixOutputs_andMatrixInput_13_161) node decoder_decoded_andMatrixOutputs_lo_lo_259 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_169, decoder_decoded_andMatrixOutputs_andMatrixInput_14_144) node decoder_decoded_andMatrixOutputs_lo_hi_lo_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_175, decoder_decoded_andMatrixOutputs_andMatrixInput_11_169) node decoder_decoded_andMatrixOutputs_lo_hi_hi_181 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_221, decoder_decoded_andMatrixOutputs_andMatrixInput_9_181) node decoder_decoded_andMatrixOutputs_lo_hi_279 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_181, decoder_decoded_andMatrixOutputs_lo_hi_lo_161) node decoder_decoded_andMatrixOutputs_lo_281 = cat(decoder_decoded_andMatrixOutputs_lo_hi_279, decoder_decoded_andMatrixOutputs_lo_lo_259) node decoder_decoded_andMatrixOutputs_hi_lo_lo_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_273, decoder_decoded_andMatrixOutputs_andMatrixInput_7_259) node decoder_decoded_andMatrixOutputs_hi_lo_hi_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_281, decoder_decoded_andMatrixOutputs_andMatrixInput_5_279) node decoder_decoded_andMatrixOutputs_hi_lo_273 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_175, decoder_decoded_andMatrixOutputs_hi_lo_lo_144) node decoder_decoded_andMatrixOutputs_hi_hi_lo_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_281, decoder_decoded_andMatrixOutputs_andMatrixInput_3_281) node decoder_decoded_andMatrixOutputs_hi_hi_hi_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_281, decoder_decoded_andMatrixOutputs_andMatrixInput_1_281) node decoder_decoded_andMatrixOutputs_hi_hi_281 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_221, decoder_decoded_andMatrixOutputs_hi_hi_lo_164) node decoder_decoded_andMatrixOutputs_hi_281 = cat(decoder_decoded_andMatrixOutputs_hi_hi_281, decoder_decoded_andMatrixOutputs_hi_lo_273) node _decoder_decoded_andMatrixOutputs_T_281 = cat(decoder_decoded_andMatrixOutputs_hi_281, decoder_decoded_andMatrixOutputs_lo_281) node decoder_decoded_andMatrixOutputs_72_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_281) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_282 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_282 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_282 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_282 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_282 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_280 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_274 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_260 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_222 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_182 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_176 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_170 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_165 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_162 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_145 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_86 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_49 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_86, decoder_decoded_andMatrixOutputs_andMatrixInput_16_49) node decoder_decoded_andMatrixOutputs_lo_lo_hi_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_162, decoder_decoded_andMatrixOutputs_andMatrixInput_14_145) node decoder_decoded_andMatrixOutputs_lo_lo_260 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_170, decoder_decoded_andMatrixOutputs_lo_lo_lo_86) node decoder_decoded_andMatrixOutputs_lo_hi_lo_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_170, decoder_decoded_andMatrixOutputs_andMatrixInput_12_165) node decoder_decoded_andMatrixOutputs_lo_hi_hi_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_182, decoder_decoded_andMatrixOutputs_andMatrixInput_10_176) node decoder_decoded_andMatrixOutputs_lo_hi_280 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_182, decoder_decoded_andMatrixOutputs_lo_hi_lo_162) node decoder_decoded_andMatrixOutputs_lo_282 = cat(decoder_decoded_andMatrixOutputs_lo_hi_280, decoder_decoded_andMatrixOutputs_lo_lo_260) node decoder_decoded_andMatrixOutputs_hi_lo_lo_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_260, decoder_decoded_andMatrixOutputs_andMatrixInput_8_222) node decoder_decoded_andMatrixOutputs_hi_lo_hi_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_280, decoder_decoded_andMatrixOutputs_andMatrixInput_6_274) node decoder_decoded_andMatrixOutputs_hi_lo_274 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_176, decoder_decoded_andMatrixOutputs_hi_lo_lo_145) node decoder_decoded_andMatrixOutputs_hi_hi_lo_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_282, decoder_decoded_andMatrixOutputs_andMatrixInput_4_282) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_282, decoder_decoded_andMatrixOutputs_andMatrixInput_1_282) node decoder_decoded_andMatrixOutputs_hi_hi_hi_222 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_2_282) node decoder_decoded_andMatrixOutputs_hi_hi_282 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_222, decoder_decoded_andMatrixOutputs_hi_hi_lo_165) node decoder_decoded_andMatrixOutputs_hi_282 = cat(decoder_decoded_andMatrixOutputs_hi_hi_282, decoder_decoded_andMatrixOutputs_hi_lo_274) node _decoder_decoded_andMatrixOutputs_T_282 = cat(decoder_decoded_andMatrixOutputs_hi_282, decoder_decoded_andMatrixOutputs_lo_282) node decoder_decoded_andMatrixOutputs_189_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_282) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_283 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_283 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_283 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_283 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_283 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_281 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_275 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_261 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_223 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_183 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_177 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_171 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_166 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_163 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_146 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_87 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_146, decoder_decoded_andMatrixOutputs_andMatrixInput_15_87) node decoder_decoded_andMatrixOutputs_lo_lo_hi_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_166, decoder_decoded_andMatrixOutputs_andMatrixInput_13_163) node decoder_decoded_andMatrixOutputs_lo_lo_261 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_171, decoder_decoded_andMatrixOutputs_lo_lo_lo_87) node decoder_decoded_andMatrixOutputs_lo_hi_lo_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_177, decoder_decoded_andMatrixOutputs_andMatrixInput_11_171) node decoder_decoded_andMatrixOutputs_lo_hi_hi_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_223, decoder_decoded_andMatrixOutputs_andMatrixInput_9_183) node decoder_decoded_andMatrixOutputs_lo_hi_281 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_183, decoder_decoded_andMatrixOutputs_lo_hi_lo_163) node decoder_decoded_andMatrixOutputs_lo_283 = cat(decoder_decoded_andMatrixOutputs_lo_hi_281, decoder_decoded_andMatrixOutputs_lo_lo_261) node decoder_decoded_andMatrixOutputs_hi_lo_lo_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_275, decoder_decoded_andMatrixOutputs_andMatrixInput_7_261) node decoder_decoded_andMatrixOutputs_hi_lo_hi_177 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_283, decoder_decoded_andMatrixOutputs_andMatrixInput_5_281) node decoder_decoded_andMatrixOutputs_hi_lo_275 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_177, decoder_decoded_andMatrixOutputs_hi_lo_lo_146) node decoder_decoded_andMatrixOutputs_hi_hi_lo_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_283, decoder_decoded_andMatrixOutputs_andMatrixInput_3_283) node decoder_decoded_andMatrixOutputs_hi_hi_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_283, decoder_decoded_andMatrixOutputs_andMatrixInput_1_283) node decoder_decoded_andMatrixOutputs_hi_hi_283 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_223, decoder_decoded_andMatrixOutputs_hi_hi_lo_166) node decoder_decoded_andMatrixOutputs_hi_283 = cat(decoder_decoded_andMatrixOutputs_hi_hi_283, decoder_decoded_andMatrixOutputs_hi_lo_275) node _decoder_decoded_andMatrixOutputs_T_283 = cat(decoder_decoded_andMatrixOutputs_hi_283, decoder_decoded_andMatrixOutputs_lo_283) node decoder_decoded_andMatrixOutputs_28_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_283) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_284 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_284 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_284 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_284 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_284 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_282 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_276 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_262 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_224 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_184 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_178 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_172 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_167 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_178, decoder_decoded_andMatrixOutputs_andMatrixInput_11_172) node decoder_decoded_andMatrixOutputs_lo_lo_262 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_12_167) node decoder_decoded_andMatrixOutputs_lo_hi_hi_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_262, decoder_decoded_andMatrixOutputs_andMatrixInput_8_224) node decoder_decoded_andMatrixOutputs_lo_hi_282 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_184, decoder_decoded_andMatrixOutputs_andMatrixInput_9_184) node decoder_decoded_andMatrixOutputs_lo_284 = cat(decoder_decoded_andMatrixOutputs_lo_hi_282, decoder_decoded_andMatrixOutputs_lo_lo_262) node decoder_decoded_andMatrixOutputs_hi_lo_hi_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_284, decoder_decoded_andMatrixOutputs_andMatrixInput_5_282) node decoder_decoded_andMatrixOutputs_hi_lo_276 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_178, decoder_decoded_andMatrixOutputs_andMatrixInput_6_276) node decoder_decoded_andMatrixOutputs_hi_hi_lo_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_284, decoder_decoded_andMatrixOutputs_andMatrixInput_3_284) node decoder_decoded_andMatrixOutputs_hi_hi_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_284, decoder_decoded_andMatrixOutputs_andMatrixInput_1_284) node decoder_decoded_andMatrixOutputs_hi_hi_284 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_224, decoder_decoded_andMatrixOutputs_hi_hi_lo_167) node decoder_decoded_andMatrixOutputs_hi_284 = cat(decoder_decoded_andMatrixOutputs_hi_hi_284, decoder_decoded_andMatrixOutputs_hi_lo_276) node _decoder_decoded_andMatrixOutputs_T_284 = cat(decoder_decoded_andMatrixOutputs_hi_284, decoder_decoded_andMatrixOutputs_lo_284) node decoder_decoded_andMatrixOutputs_0_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_284) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_285 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_285 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_285 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_285 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_285 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_283 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_277 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_263 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_225 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_185 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_179 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_173 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_168 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_164 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_147 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_88 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_50 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_36 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_27 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_19, decoder_decoded_andMatrixOutputs_andMatrixInput_21_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_36, decoder_decoded_andMatrixOutputs_andMatrixInput_18_29) node decoder_decoded_andMatrixOutputs_lo_lo_hi_173 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_19_27) node decoder_decoded_andMatrixOutputs_lo_lo_263 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_173, decoder_decoded_andMatrixOutputs_lo_lo_lo_88) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_147, decoder_decoded_andMatrixOutputs_andMatrixInput_15_88) node decoder_decoded_andMatrixOutputs_lo_hi_lo_164 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_50) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_173, decoder_decoded_andMatrixOutputs_andMatrixInput_12_168) node decoder_decoded_andMatrixOutputs_lo_hi_hi_185 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_164) node decoder_decoded_andMatrixOutputs_lo_hi_283 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_185, decoder_decoded_andMatrixOutputs_lo_hi_lo_164) node decoder_decoded_andMatrixOutputs_lo_285 = cat(decoder_decoded_andMatrixOutputs_lo_hi_283, decoder_decoded_andMatrixOutputs_lo_lo_263) node decoder_decoded_andMatrixOutputs_hi_lo_lo_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_185, decoder_decoded_andMatrixOutputs_andMatrixInput_10_179) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_277, decoder_decoded_andMatrixOutputs_andMatrixInput_7_263) node decoder_decoded_andMatrixOutputs_hi_lo_hi_179 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_8_225) node decoder_decoded_andMatrixOutputs_hi_lo_277 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_179, decoder_decoded_andMatrixOutputs_hi_lo_lo_147) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_285, decoder_decoded_andMatrixOutputs_andMatrixInput_4_285) node decoder_decoded_andMatrixOutputs_hi_hi_lo_168 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_283) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_285, decoder_decoded_andMatrixOutputs_andMatrixInput_1_285) node decoder_decoded_andMatrixOutputs_hi_hi_hi_225 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_2_285) node decoder_decoded_andMatrixOutputs_hi_hi_285 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_225, decoder_decoded_andMatrixOutputs_hi_hi_lo_168) node decoder_decoded_andMatrixOutputs_hi_285 = cat(decoder_decoded_andMatrixOutputs_hi_hi_285, decoder_decoded_andMatrixOutputs_hi_lo_277) node _decoder_decoded_andMatrixOutputs_T_285 = cat(decoder_decoded_andMatrixOutputs_hi_285, decoder_decoded_andMatrixOutputs_lo_285) node decoder_decoded_andMatrixOutputs_59_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_285) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_286 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_286 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_286 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_286 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_286 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_284 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_278 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_264 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_226 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_186 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_180 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_174 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_169 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_165 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_148 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_169, decoder_decoded_andMatrixOutputs_andMatrixInput_13_165) node decoder_decoded_andMatrixOutputs_lo_lo_264 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_174, decoder_decoded_andMatrixOutputs_andMatrixInput_14_148) node decoder_decoded_andMatrixOutputs_lo_hi_lo_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_180, decoder_decoded_andMatrixOutputs_andMatrixInput_11_174) node decoder_decoded_andMatrixOutputs_lo_hi_hi_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_226, decoder_decoded_andMatrixOutputs_andMatrixInput_9_186) node decoder_decoded_andMatrixOutputs_lo_hi_284 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_186, decoder_decoded_andMatrixOutputs_lo_hi_lo_165) node decoder_decoded_andMatrixOutputs_lo_286 = cat(decoder_decoded_andMatrixOutputs_lo_hi_284, decoder_decoded_andMatrixOutputs_lo_lo_264) node decoder_decoded_andMatrixOutputs_hi_lo_lo_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_278, decoder_decoded_andMatrixOutputs_andMatrixInput_7_264) node decoder_decoded_andMatrixOutputs_hi_lo_hi_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_286, decoder_decoded_andMatrixOutputs_andMatrixInput_5_284) node decoder_decoded_andMatrixOutputs_hi_lo_278 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_180, decoder_decoded_andMatrixOutputs_hi_lo_lo_148) node decoder_decoded_andMatrixOutputs_hi_hi_lo_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_286, decoder_decoded_andMatrixOutputs_andMatrixInput_3_286) node decoder_decoded_andMatrixOutputs_hi_hi_hi_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_286, decoder_decoded_andMatrixOutputs_andMatrixInput_1_286) node decoder_decoded_andMatrixOutputs_hi_hi_286 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_226, decoder_decoded_andMatrixOutputs_hi_hi_lo_169) node decoder_decoded_andMatrixOutputs_hi_286 = cat(decoder_decoded_andMatrixOutputs_hi_hi_286, decoder_decoded_andMatrixOutputs_hi_lo_278) node _decoder_decoded_andMatrixOutputs_T_286 = cat(decoder_decoded_andMatrixOutputs_hi_286, decoder_decoded_andMatrixOutputs_lo_286) node decoder_decoded_andMatrixOutputs_43_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_286) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_287 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_287 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_287 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_287 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_287 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_285 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_279 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_265 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_227 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_187 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_181 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_175 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_170 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_166 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_149 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_89 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_149, decoder_decoded_andMatrixOutputs_andMatrixInput_15_89) node decoder_decoded_andMatrixOutputs_lo_lo_hi_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_170, decoder_decoded_andMatrixOutputs_andMatrixInput_13_166) node decoder_decoded_andMatrixOutputs_lo_lo_265 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_175, decoder_decoded_andMatrixOutputs_lo_lo_lo_89) node decoder_decoded_andMatrixOutputs_lo_hi_lo_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_181, decoder_decoded_andMatrixOutputs_andMatrixInput_11_175) node decoder_decoded_andMatrixOutputs_lo_hi_hi_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_227, decoder_decoded_andMatrixOutputs_andMatrixInput_9_187) node decoder_decoded_andMatrixOutputs_lo_hi_285 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_187, decoder_decoded_andMatrixOutputs_lo_hi_lo_166) node decoder_decoded_andMatrixOutputs_lo_287 = cat(decoder_decoded_andMatrixOutputs_lo_hi_285, decoder_decoded_andMatrixOutputs_lo_lo_265) node decoder_decoded_andMatrixOutputs_hi_lo_lo_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_279, decoder_decoded_andMatrixOutputs_andMatrixInput_7_265) node decoder_decoded_andMatrixOutputs_hi_lo_hi_181 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_287, decoder_decoded_andMatrixOutputs_andMatrixInput_5_285) node decoder_decoded_andMatrixOutputs_hi_lo_279 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_181, decoder_decoded_andMatrixOutputs_hi_lo_lo_149) node decoder_decoded_andMatrixOutputs_hi_hi_lo_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_287, decoder_decoded_andMatrixOutputs_andMatrixInput_3_287) node decoder_decoded_andMatrixOutputs_hi_hi_hi_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_287, decoder_decoded_andMatrixOutputs_andMatrixInput_1_287) node decoder_decoded_andMatrixOutputs_hi_hi_287 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_227, decoder_decoded_andMatrixOutputs_hi_hi_lo_170) node decoder_decoded_andMatrixOutputs_hi_287 = cat(decoder_decoded_andMatrixOutputs_hi_hi_287, decoder_decoded_andMatrixOutputs_hi_lo_279) node _decoder_decoded_andMatrixOutputs_T_287 = cat(decoder_decoded_andMatrixOutputs_hi_287, decoder_decoded_andMatrixOutputs_lo_287) node decoder_decoded_andMatrixOutputs_169_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_287) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_288 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_288 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_288 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_288 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_288 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_286 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_280 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_266 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_228 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_188 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_182 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_176 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_171 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_167 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_150 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_90 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_150, decoder_decoded_andMatrixOutputs_andMatrixInput_15_90) node decoder_decoded_andMatrixOutputs_lo_lo_hi_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_171, decoder_decoded_andMatrixOutputs_andMatrixInput_13_167) node decoder_decoded_andMatrixOutputs_lo_lo_266 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_176, decoder_decoded_andMatrixOutputs_lo_lo_lo_90) node decoder_decoded_andMatrixOutputs_lo_hi_lo_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_182, decoder_decoded_andMatrixOutputs_andMatrixInput_11_176) node decoder_decoded_andMatrixOutputs_lo_hi_hi_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_228, decoder_decoded_andMatrixOutputs_andMatrixInput_9_188) node decoder_decoded_andMatrixOutputs_lo_hi_286 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_188, decoder_decoded_andMatrixOutputs_lo_hi_lo_167) node decoder_decoded_andMatrixOutputs_lo_288 = cat(decoder_decoded_andMatrixOutputs_lo_hi_286, decoder_decoded_andMatrixOutputs_lo_lo_266) node decoder_decoded_andMatrixOutputs_hi_lo_lo_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_280, decoder_decoded_andMatrixOutputs_andMatrixInput_7_266) node decoder_decoded_andMatrixOutputs_hi_lo_hi_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_288, decoder_decoded_andMatrixOutputs_andMatrixInput_5_286) node decoder_decoded_andMatrixOutputs_hi_lo_280 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_182, decoder_decoded_andMatrixOutputs_hi_lo_lo_150) node decoder_decoded_andMatrixOutputs_hi_hi_lo_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_288, decoder_decoded_andMatrixOutputs_andMatrixInput_3_288) node decoder_decoded_andMatrixOutputs_hi_hi_hi_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_288, decoder_decoded_andMatrixOutputs_andMatrixInput_1_288) node decoder_decoded_andMatrixOutputs_hi_hi_288 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_228, decoder_decoded_andMatrixOutputs_hi_hi_lo_171) node decoder_decoded_andMatrixOutputs_hi_288 = cat(decoder_decoded_andMatrixOutputs_hi_hi_288, decoder_decoded_andMatrixOutputs_hi_lo_280) node _decoder_decoded_andMatrixOutputs_T_288 = cat(decoder_decoded_andMatrixOutputs_hi_288, decoder_decoded_andMatrixOutputs_lo_288) node decoder_decoded_andMatrixOutputs_164_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_288) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_289 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_289 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_289 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_289 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_289 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_287 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_281 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_267 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_229 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_189 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_183 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_177 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_172 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_168 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_151 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_91 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_51 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_91, decoder_decoded_andMatrixOutputs_andMatrixInput_16_51) node decoder_decoded_andMatrixOutputs_lo_lo_hi_177 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_168, decoder_decoded_andMatrixOutputs_andMatrixInput_14_151) node decoder_decoded_andMatrixOutputs_lo_lo_267 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_177, decoder_decoded_andMatrixOutputs_lo_lo_lo_91) node decoder_decoded_andMatrixOutputs_lo_hi_lo_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_177, decoder_decoded_andMatrixOutputs_andMatrixInput_12_172) node decoder_decoded_andMatrixOutputs_lo_hi_hi_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_189, decoder_decoded_andMatrixOutputs_andMatrixInput_10_183) node decoder_decoded_andMatrixOutputs_lo_hi_287 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_189, decoder_decoded_andMatrixOutputs_lo_hi_lo_168) node decoder_decoded_andMatrixOutputs_lo_289 = cat(decoder_decoded_andMatrixOutputs_lo_hi_287, decoder_decoded_andMatrixOutputs_lo_lo_267) node decoder_decoded_andMatrixOutputs_hi_lo_lo_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_267, decoder_decoded_andMatrixOutputs_andMatrixInput_8_229) node decoder_decoded_andMatrixOutputs_hi_lo_hi_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_287, decoder_decoded_andMatrixOutputs_andMatrixInput_6_281) node decoder_decoded_andMatrixOutputs_hi_lo_281 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_183, decoder_decoded_andMatrixOutputs_hi_lo_lo_151) node decoder_decoded_andMatrixOutputs_hi_hi_lo_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_289, decoder_decoded_andMatrixOutputs_andMatrixInput_4_289) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_289, decoder_decoded_andMatrixOutputs_andMatrixInput_1_289) node decoder_decoded_andMatrixOutputs_hi_hi_hi_229 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_2_289) node decoder_decoded_andMatrixOutputs_hi_hi_289 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_229, decoder_decoded_andMatrixOutputs_hi_hi_lo_172) node decoder_decoded_andMatrixOutputs_hi_289 = cat(decoder_decoded_andMatrixOutputs_hi_hi_289, decoder_decoded_andMatrixOutputs_hi_lo_281) node _decoder_decoded_andMatrixOutputs_T_289 = cat(decoder_decoded_andMatrixOutputs_hi_289, decoder_decoded_andMatrixOutputs_lo_289) node decoder_decoded_andMatrixOutputs_137_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_289) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_290 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_290 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_290 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_290 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_290 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_288 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_282 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_268 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_230 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_190 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_184 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_178 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_173 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_169 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_152 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_92 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_52 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_37 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_37, decoder_decoded_andMatrixOutputs_andMatrixInput_18_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_92, decoder_decoded_andMatrixOutputs_andMatrixInput_16_52) node decoder_decoded_andMatrixOutputs_lo_lo_268 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_178, decoder_decoded_andMatrixOutputs_lo_lo_lo_92) node decoder_decoded_andMatrixOutputs_lo_hi_lo_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_169, decoder_decoded_andMatrixOutputs_andMatrixInput_14_152) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_184, decoder_decoded_andMatrixOutputs_andMatrixInput_11_178) node decoder_decoded_andMatrixOutputs_lo_hi_hi_190 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_12_173) node decoder_decoded_andMatrixOutputs_lo_hi_288 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_190, decoder_decoded_andMatrixOutputs_lo_hi_lo_169) node decoder_decoded_andMatrixOutputs_lo_290 = cat(decoder_decoded_andMatrixOutputs_lo_hi_288, decoder_decoded_andMatrixOutputs_lo_lo_268) node decoder_decoded_andMatrixOutputs_hi_lo_lo_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_230, decoder_decoded_andMatrixOutputs_andMatrixInput_9_190) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_288, decoder_decoded_andMatrixOutputs_andMatrixInput_6_282) node decoder_decoded_andMatrixOutputs_hi_lo_hi_184 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_268) node decoder_decoded_andMatrixOutputs_hi_lo_282 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_184, decoder_decoded_andMatrixOutputs_hi_lo_lo_152) node decoder_decoded_andMatrixOutputs_hi_hi_lo_173 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_290, decoder_decoded_andMatrixOutputs_andMatrixInput_4_290) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_290, decoder_decoded_andMatrixOutputs_andMatrixInput_1_290) node decoder_decoded_andMatrixOutputs_hi_hi_hi_230 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_2_290) node decoder_decoded_andMatrixOutputs_hi_hi_290 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_230, decoder_decoded_andMatrixOutputs_hi_hi_lo_173) node decoder_decoded_andMatrixOutputs_hi_290 = cat(decoder_decoded_andMatrixOutputs_hi_hi_290, decoder_decoded_andMatrixOutputs_hi_lo_282) node _decoder_decoded_andMatrixOutputs_T_290 = cat(decoder_decoded_andMatrixOutputs_hi_290, decoder_decoded_andMatrixOutputs_lo_290) node decoder_decoded_andMatrixOutputs_73_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_290) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_291 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_291 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_291 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_291 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_291 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_289 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_283 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_269 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_231 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_191 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_185 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_179 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_174 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_170 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_153 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_93 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_53 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_38 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_31 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_28 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_10 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_10 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, decoder_decoded_andMatrixOutputs_andMatrixInput_26_10) node decoder_decoded_andMatrixOutputs_lo_lo_lo_93 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_27_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, decoder_decoded_andMatrixOutputs_andMatrixInput_24_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_15, decoder_decoded_andMatrixOutputs_andMatrixInput_22_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_179 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_10) node decoder_decoded_andMatrixOutputs_lo_lo_269 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_179, decoder_decoded_andMatrixOutputs_lo_lo_lo_93) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_31, decoder_decoded_andMatrixOutputs_andMatrixInput_19_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_170 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_20_20) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_53, decoder_decoded_andMatrixOutputs_andMatrixInput_17_38) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_153, decoder_decoded_andMatrixOutputs_andMatrixInput_15_93) node decoder_decoded_andMatrixOutputs_lo_hi_hi_191 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10) node decoder_decoded_andMatrixOutputs_lo_hi_289 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_191, decoder_decoded_andMatrixOutputs_lo_hi_lo_170) node decoder_decoded_andMatrixOutputs_lo_291 = cat(decoder_decoded_andMatrixOutputs_lo_hi_289, decoder_decoded_andMatrixOutputs_lo_lo_269) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_179, decoder_decoded_andMatrixOutputs_andMatrixInput_12_174) node decoder_decoded_andMatrixOutputs_hi_lo_lo_153 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_170) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_191, decoder_decoded_andMatrixOutputs_andMatrixInput_10_185) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_269, decoder_decoded_andMatrixOutputs_andMatrixInput_8_231) node decoder_decoded_andMatrixOutputs_hi_lo_hi_185 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_10) node decoder_decoded_andMatrixOutputs_hi_lo_283 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_185, decoder_decoded_andMatrixOutputs_hi_lo_lo_153) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_291, decoder_decoded_andMatrixOutputs_andMatrixInput_5_289) node decoder_decoded_andMatrixOutputs_hi_hi_lo_174 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_6_283) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_291, decoder_decoded_andMatrixOutputs_andMatrixInput_3_291) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_291, decoder_decoded_andMatrixOutputs_andMatrixInput_1_291) node decoder_decoded_andMatrixOutputs_hi_hi_hi_231 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10) node decoder_decoded_andMatrixOutputs_hi_hi_291 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_231, decoder_decoded_andMatrixOutputs_hi_hi_lo_174) node decoder_decoded_andMatrixOutputs_hi_291 = cat(decoder_decoded_andMatrixOutputs_hi_hi_291, decoder_decoded_andMatrixOutputs_hi_lo_283) node _decoder_decoded_andMatrixOutputs_T_291 = cat(decoder_decoded_andMatrixOutputs_hi_291, decoder_decoded_andMatrixOutputs_lo_291) node decoder_decoded_andMatrixOutputs_58_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_291) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_292 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_292 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_292 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_292 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_292 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_290 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_284 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_270 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_232 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_192 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_186 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_180 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_175 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_171 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_154 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_94 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_54 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_39 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_32 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_29 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_21 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_16 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_11 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_11 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_5 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_5 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_5 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_5, decoder_decoded_andMatrixOutputs_andMatrixInput_29_5) node decoder_decoded_andMatrixOutputs_lo_lo_lo_94 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_30_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_11, decoder_decoded_andMatrixOutputs_andMatrixInput_27_11) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, decoder_decoded_andMatrixOutputs_andMatrixInput_25_11) node decoder_decoded_andMatrixOutputs_lo_lo_hi_180 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_11) node decoder_decoded_andMatrixOutputs_lo_lo_270 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_180, decoder_decoded_andMatrixOutputs_lo_lo_lo_94) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, decoder_decoded_andMatrixOutputs_andMatrixInput_23_11) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_21, decoder_decoded_andMatrixOutputs_andMatrixInput_21_16) node decoder_decoded_andMatrixOutputs_lo_hi_lo_171 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_5) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_32, decoder_decoded_andMatrixOutputs_andMatrixInput_19_29) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_54, decoder_decoded_andMatrixOutputs_andMatrixInput_17_39) node decoder_decoded_andMatrixOutputs_lo_hi_hi_192 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11) node decoder_decoded_andMatrixOutputs_lo_hi_290 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_192, decoder_decoded_andMatrixOutputs_lo_hi_lo_171) node decoder_decoded_andMatrixOutputs_lo_292 = cat(decoder_decoded_andMatrixOutputs_lo_hi_290, decoder_decoded_andMatrixOutputs_lo_lo_270) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_154, decoder_decoded_andMatrixOutputs_andMatrixInput_15_94) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_175, decoder_decoded_andMatrixOutputs_andMatrixInput_13_171) node decoder_decoded_andMatrixOutputs_hi_lo_lo_154 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_186, decoder_decoded_andMatrixOutputs_andMatrixInput_11_180) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_232, decoder_decoded_andMatrixOutputs_andMatrixInput_9_192) node decoder_decoded_andMatrixOutputs_hi_lo_hi_186 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_11) node decoder_decoded_andMatrixOutputs_hi_lo_284 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_186, decoder_decoded_andMatrixOutputs_hi_lo_lo_154) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_284, decoder_decoded_andMatrixOutputs_andMatrixInput_7_270) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_292, decoder_decoded_andMatrixOutputs_andMatrixInput_5_290) node decoder_decoded_andMatrixOutputs_hi_hi_lo_175 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_292, decoder_decoded_andMatrixOutputs_andMatrixInput_3_292) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_292, decoder_decoded_andMatrixOutputs_andMatrixInput_1_292) node decoder_decoded_andMatrixOutputs_hi_hi_hi_232 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11) node decoder_decoded_andMatrixOutputs_hi_hi_292 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_232, decoder_decoded_andMatrixOutputs_hi_hi_lo_175) node decoder_decoded_andMatrixOutputs_hi_292 = cat(decoder_decoded_andMatrixOutputs_hi_hi_292, decoder_decoded_andMatrixOutputs_hi_lo_284) node _decoder_decoded_andMatrixOutputs_T_292 = cat(decoder_decoded_andMatrixOutputs_hi_292, decoder_decoded_andMatrixOutputs_lo_292) node decoder_decoded_andMatrixOutputs_152_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_292) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_293 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_293 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_293 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_293 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_293 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_291 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_285 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_271 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_233 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_193 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_187 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_181 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_176 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_172 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_155 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_95 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_55 = bits(decoder_decoded_plaInput_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_40 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_33 = bits(decoder_decoded_plaInput_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_30 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_22 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_17 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_12 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_12 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_12 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_12 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_12 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_12 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_12, decoder_decoded_andMatrixOutputs_andMatrixInput_26_12) node decoder_decoded_andMatrixOutputs_lo_lo_lo_95 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_27_12) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_12, decoder_decoded_andMatrixOutputs_andMatrixInput_24_12) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_17, decoder_decoded_andMatrixOutputs_andMatrixInput_22_12) node decoder_decoded_andMatrixOutputs_lo_lo_hi_181 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_12) node decoder_decoded_andMatrixOutputs_lo_lo_271 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_181, decoder_decoded_andMatrixOutputs_lo_lo_lo_95) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_33, decoder_decoded_andMatrixOutputs_andMatrixInput_19_30) node decoder_decoded_andMatrixOutputs_lo_hi_lo_172 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_20_22) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_55, decoder_decoded_andMatrixOutputs_andMatrixInput_17_40) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_155, decoder_decoded_andMatrixOutputs_andMatrixInput_15_95) node decoder_decoded_andMatrixOutputs_lo_hi_hi_193 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_12) node decoder_decoded_andMatrixOutputs_lo_hi_291 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_193, decoder_decoded_andMatrixOutputs_lo_hi_lo_172) node decoder_decoded_andMatrixOutputs_lo_293 = cat(decoder_decoded_andMatrixOutputs_lo_hi_291, decoder_decoded_andMatrixOutputs_lo_lo_271) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_181, decoder_decoded_andMatrixOutputs_andMatrixInput_12_176) node decoder_decoded_andMatrixOutputs_hi_lo_lo_155 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_172) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_193, decoder_decoded_andMatrixOutputs_andMatrixInput_10_187) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_271, decoder_decoded_andMatrixOutputs_andMatrixInput_8_233) node decoder_decoded_andMatrixOutputs_hi_lo_hi_187 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_12) node decoder_decoded_andMatrixOutputs_hi_lo_285 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_187, decoder_decoded_andMatrixOutputs_hi_lo_lo_155) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_293, decoder_decoded_andMatrixOutputs_andMatrixInput_5_291) node decoder_decoded_andMatrixOutputs_hi_hi_lo_176 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_6_285) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_293, decoder_decoded_andMatrixOutputs_andMatrixInput_3_293) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_293, decoder_decoded_andMatrixOutputs_andMatrixInput_1_293) node decoder_decoded_andMatrixOutputs_hi_hi_hi_233 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_12) node decoder_decoded_andMatrixOutputs_hi_hi_293 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_233, decoder_decoded_andMatrixOutputs_hi_hi_lo_176) node decoder_decoded_andMatrixOutputs_hi_293 = cat(decoder_decoded_andMatrixOutputs_hi_hi_293, decoder_decoded_andMatrixOutputs_hi_lo_285) node _decoder_decoded_andMatrixOutputs_T_293 = cat(decoder_decoded_andMatrixOutputs_hi_293, decoder_decoded_andMatrixOutputs_lo_293) node decoder_decoded_andMatrixOutputs_161_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_293) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_294 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_294 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_294 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_294 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_294 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_292 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_286 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_272 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_234 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_194 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_188 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_182 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_177 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_173 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_156 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_96 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_56 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_41 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_34 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_31 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_23 = bits(decoder_decoded_plaInput_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_18 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_13 = bits(decoder_decoded_plaInput_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_13 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_13 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_13 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_13 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_13 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_6 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_6 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_6 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_31_2 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_30_6, decoder_decoded_andMatrixOutputs_andMatrixInput_31_2) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_6, decoder_decoded_andMatrixOutputs_andMatrixInput_29_6) node decoder_decoded_andMatrixOutputs_lo_lo_lo_96 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_13, decoder_decoded_andMatrixOutputs_andMatrixInput_27_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_13, decoder_decoded_andMatrixOutputs_andMatrixInput_25_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_182 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_13) node decoder_decoded_andMatrixOutputs_lo_lo_272 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_182, decoder_decoded_andMatrixOutputs_lo_lo_lo_96) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_13, decoder_decoded_andMatrixOutputs_andMatrixInput_23_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_23, decoder_decoded_andMatrixOutputs_andMatrixInput_21_18) node decoder_decoded_andMatrixOutputs_lo_hi_lo_173 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_6) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_34, decoder_decoded_andMatrixOutputs_andMatrixInput_19_31) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_56, decoder_decoded_andMatrixOutputs_andMatrixInput_17_41) node decoder_decoded_andMatrixOutputs_lo_hi_hi_194 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_13) node decoder_decoded_andMatrixOutputs_lo_hi_292 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_194, decoder_decoded_andMatrixOutputs_lo_hi_lo_173) node decoder_decoded_andMatrixOutputs_lo_294 = cat(decoder_decoded_andMatrixOutputs_lo_hi_292, decoder_decoded_andMatrixOutputs_lo_lo_272) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_156, decoder_decoded_andMatrixOutputs_andMatrixInput_15_96) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_177, decoder_decoded_andMatrixOutputs_andMatrixInput_13_173) node decoder_decoded_andMatrixOutputs_hi_lo_lo_156 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_188, decoder_decoded_andMatrixOutputs_andMatrixInput_11_182) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_234, decoder_decoded_andMatrixOutputs_andMatrixInput_9_194) node decoder_decoded_andMatrixOutputs_hi_lo_hi_188 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_13) node decoder_decoded_andMatrixOutputs_hi_lo_286 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_188, decoder_decoded_andMatrixOutputs_hi_lo_lo_156) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_286, decoder_decoded_andMatrixOutputs_andMatrixInput_7_272) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_294, decoder_decoded_andMatrixOutputs_andMatrixInput_5_292) node decoder_decoded_andMatrixOutputs_hi_hi_lo_177 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_294, decoder_decoded_andMatrixOutputs_andMatrixInput_3_294) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_294, decoder_decoded_andMatrixOutputs_andMatrixInput_1_294) node decoder_decoded_andMatrixOutputs_hi_hi_hi_234 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_13) node decoder_decoded_andMatrixOutputs_hi_hi_294 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_234, decoder_decoded_andMatrixOutputs_hi_hi_lo_177) node decoder_decoded_andMatrixOutputs_hi_294 = cat(decoder_decoded_andMatrixOutputs_hi_hi_294, decoder_decoded_andMatrixOutputs_hi_lo_286) node _decoder_decoded_andMatrixOutputs_T_294 = cat(decoder_decoded_andMatrixOutputs_hi_294, decoder_decoded_andMatrixOutputs_lo_294) node decoder_decoded_andMatrixOutputs_112_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_294) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_295 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_295 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_295 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_295 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_295 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_293 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_287 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_273 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_235 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_195 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_189 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_183 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_178 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_174 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_157 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_97 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_57 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_97 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_97, decoder_decoded_andMatrixOutputs_andMatrixInput_16_57) node decoder_decoded_andMatrixOutputs_lo_lo_hi_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_174, decoder_decoded_andMatrixOutputs_andMatrixInput_14_157) node decoder_decoded_andMatrixOutputs_lo_lo_273 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_183, decoder_decoded_andMatrixOutputs_lo_lo_lo_97) node decoder_decoded_andMatrixOutputs_lo_hi_lo_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_183, decoder_decoded_andMatrixOutputs_andMatrixInput_12_178) node decoder_decoded_andMatrixOutputs_lo_hi_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_195, decoder_decoded_andMatrixOutputs_andMatrixInput_10_189) node decoder_decoded_andMatrixOutputs_lo_hi_293 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_195, decoder_decoded_andMatrixOutputs_lo_hi_lo_174) node decoder_decoded_andMatrixOutputs_lo_295 = cat(decoder_decoded_andMatrixOutputs_lo_hi_293, decoder_decoded_andMatrixOutputs_lo_lo_273) node decoder_decoded_andMatrixOutputs_hi_lo_lo_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_273, decoder_decoded_andMatrixOutputs_andMatrixInput_8_235) node decoder_decoded_andMatrixOutputs_hi_lo_hi_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_293, decoder_decoded_andMatrixOutputs_andMatrixInput_6_287) node decoder_decoded_andMatrixOutputs_hi_lo_287 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_189, decoder_decoded_andMatrixOutputs_hi_lo_lo_157) node decoder_decoded_andMatrixOutputs_hi_hi_lo_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_295, decoder_decoded_andMatrixOutputs_andMatrixInput_4_295) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_295, decoder_decoded_andMatrixOutputs_andMatrixInput_1_295) node decoder_decoded_andMatrixOutputs_hi_hi_hi_235 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_2_295) node decoder_decoded_andMatrixOutputs_hi_hi_295 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_235, decoder_decoded_andMatrixOutputs_hi_hi_lo_178) node decoder_decoded_andMatrixOutputs_hi_295 = cat(decoder_decoded_andMatrixOutputs_hi_hi_295, decoder_decoded_andMatrixOutputs_hi_lo_287) node _decoder_decoded_andMatrixOutputs_T_295 = cat(decoder_decoded_andMatrixOutputs_hi_295, decoder_decoded_andMatrixOutputs_lo_295) node decoder_decoded_andMatrixOutputs_82_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_295) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_296 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_296 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_296 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_296 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_296 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_294 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_288 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_274 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_236 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_196 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_190 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_184 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_179 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_175 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_158 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_98 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_58 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_42 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_98 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_58, decoder_decoded_andMatrixOutputs_andMatrixInput_17_42) node decoder_decoded_andMatrixOutputs_lo_lo_hi_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_158, decoder_decoded_andMatrixOutputs_andMatrixInput_15_98) node decoder_decoded_andMatrixOutputs_lo_lo_274 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_184, decoder_decoded_andMatrixOutputs_lo_lo_lo_98) node decoder_decoded_andMatrixOutputs_lo_hi_lo_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_179, decoder_decoded_andMatrixOutputs_andMatrixInput_13_175) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_196, decoder_decoded_andMatrixOutputs_andMatrixInput_10_190) node decoder_decoded_andMatrixOutputs_lo_hi_hi_196 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_184) node decoder_decoded_andMatrixOutputs_lo_hi_294 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_196, decoder_decoded_andMatrixOutputs_lo_hi_lo_175) node decoder_decoded_andMatrixOutputs_lo_296 = cat(decoder_decoded_andMatrixOutputs_lo_hi_294, decoder_decoded_andMatrixOutputs_lo_lo_274) node decoder_decoded_andMatrixOutputs_hi_lo_lo_158 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_274, decoder_decoded_andMatrixOutputs_andMatrixInput_8_236) node decoder_decoded_andMatrixOutputs_hi_lo_hi_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_294, decoder_decoded_andMatrixOutputs_andMatrixInput_6_288) node decoder_decoded_andMatrixOutputs_hi_lo_288 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_190, decoder_decoded_andMatrixOutputs_hi_lo_lo_158) node decoder_decoded_andMatrixOutputs_hi_hi_lo_179 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_296, decoder_decoded_andMatrixOutputs_andMatrixInput_4_296) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_296, decoder_decoded_andMatrixOutputs_andMatrixInput_1_296) node decoder_decoded_andMatrixOutputs_hi_hi_hi_236 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_2_296) node decoder_decoded_andMatrixOutputs_hi_hi_296 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_236, decoder_decoded_andMatrixOutputs_hi_hi_lo_179) node decoder_decoded_andMatrixOutputs_hi_296 = cat(decoder_decoded_andMatrixOutputs_hi_hi_296, decoder_decoded_andMatrixOutputs_hi_lo_288) node _decoder_decoded_andMatrixOutputs_T_296 = cat(decoder_decoded_andMatrixOutputs_hi_296, decoder_decoded_andMatrixOutputs_lo_296) node decoder_decoded_andMatrixOutputs_31_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_296) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_297 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_297 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_297 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_297 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_297 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_295 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_289 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_275 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_237 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_197 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_191 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_185 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_180 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_176 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_159 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_99 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_59 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_43 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_35 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_32 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_99 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_35, decoder_decoded_andMatrixOutputs_andMatrixInput_19_32) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_99, decoder_decoded_andMatrixOutputs_andMatrixInput_16_59) node decoder_decoded_andMatrixOutputs_lo_lo_hi_185 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_17_43) node decoder_decoded_andMatrixOutputs_lo_lo_275 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_185, decoder_decoded_andMatrixOutputs_lo_lo_lo_99) node decoder_decoded_andMatrixOutputs_lo_hi_lo_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_176, decoder_decoded_andMatrixOutputs_andMatrixInput_14_159) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_191, decoder_decoded_andMatrixOutputs_andMatrixInput_11_185) node decoder_decoded_andMatrixOutputs_lo_hi_hi_197 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_12_180) node decoder_decoded_andMatrixOutputs_lo_hi_295 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_197, decoder_decoded_andMatrixOutputs_lo_hi_lo_176) node decoder_decoded_andMatrixOutputs_lo_297 = cat(decoder_decoded_andMatrixOutputs_lo_hi_295, decoder_decoded_andMatrixOutputs_lo_lo_275) node decoder_decoded_andMatrixOutputs_hi_lo_lo_159 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_237, decoder_decoded_andMatrixOutputs_andMatrixInput_9_197) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_295, decoder_decoded_andMatrixOutputs_andMatrixInput_6_289) node decoder_decoded_andMatrixOutputs_hi_lo_hi_191 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_275) node decoder_decoded_andMatrixOutputs_hi_lo_289 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_191, decoder_decoded_andMatrixOutputs_hi_lo_lo_159) node decoder_decoded_andMatrixOutputs_hi_hi_lo_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_297, decoder_decoded_andMatrixOutputs_andMatrixInput_4_297) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_297, decoder_decoded_andMatrixOutputs_andMatrixInput_1_297) node decoder_decoded_andMatrixOutputs_hi_hi_hi_237 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_andMatrixInput_2_297) node decoder_decoded_andMatrixOutputs_hi_hi_297 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_237, decoder_decoded_andMatrixOutputs_hi_hi_lo_180) node decoder_decoded_andMatrixOutputs_hi_297 = cat(decoder_decoded_andMatrixOutputs_hi_hi_297, decoder_decoded_andMatrixOutputs_hi_lo_289) node _decoder_decoded_andMatrixOutputs_T_297 = cat(decoder_decoded_andMatrixOutputs_hi_297, decoder_decoded_andMatrixOutputs_lo_297) node decoder_decoded_andMatrixOutputs_13_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_297) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_298 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_298 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_298 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_298 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_298 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_296 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_290 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_276 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_238 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_198 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_192 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_186 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_181 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_177 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_160 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_100 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_60 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_44 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_36 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_33 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_24 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_19 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_100 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_24, decoder_decoded_andMatrixOutputs_andMatrixInput_21_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_44, decoder_decoded_andMatrixOutputs_andMatrixInput_18_36) node decoder_decoded_andMatrixOutputs_lo_lo_hi_186 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_19_33) node decoder_decoded_andMatrixOutputs_lo_lo_276 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_186, decoder_decoded_andMatrixOutputs_lo_lo_lo_100) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_160, decoder_decoded_andMatrixOutputs_andMatrixInput_15_100) node decoder_decoded_andMatrixOutputs_lo_hi_lo_177 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_16_60) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_186, decoder_decoded_andMatrixOutputs_andMatrixInput_12_181) node decoder_decoded_andMatrixOutputs_lo_hi_hi_198 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_177) node decoder_decoded_andMatrixOutputs_lo_hi_296 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_198, decoder_decoded_andMatrixOutputs_lo_hi_lo_177) node decoder_decoded_andMatrixOutputs_lo_298 = cat(decoder_decoded_andMatrixOutputs_lo_hi_296, decoder_decoded_andMatrixOutputs_lo_lo_276) node decoder_decoded_andMatrixOutputs_hi_lo_lo_160 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_198, decoder_decoded_andMatrixOutputs_andMatrixInput_10_192) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_290, decoder_decoded_andMatrixOutputs_andMatrixInput_7_276) node decoder_decoded_andMatrixOutputs_hi_lo_hi_192 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_8_238) node decoder_decoded_andMatrixOutputs_hi_lo_290 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_192, decoder_decoded_andMatrixOutputs_hi_lo_lo_160) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_298, decoder_decoded_andMatrixOutputs_andMatrixInput_4_298) node decoder_decoded_andMatrixOutputs_hi_hi_lo_181 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_296) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_298, decoder_decoded_andMatrixOutputs_andMatrixInput_1_298) node decoder_decoded_andMatrixOutputs_hi_hi_hi_238 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_2_298) node decoder_decoded_andMatrixOutputs_hi_hi_298 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_238, decoder_decoded_andMatrixOutputs_hi_hi_lo_181) node decoder_decoded_andMatrixOutputs_hi_298 = cat(decoder_decoded_andMatrixOutputs_hi_hi_298, decoder_decoded_andMatrixOutputs_hi_lo_290) node _decoder_decoded_andMatrixOutputs_T_298 = cat(decoder_decoded_andMatrixOutputs_hi_298, decoder_decoded_andMatrixOutputs_lo_298) node decoder_decoded_andMatrixOutputs_110_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_298) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_299 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_299 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_299 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_299 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_299 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_297 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_291 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_277 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_239 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_199 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_193 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_187 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_182 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_178 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_187, decoder_decoded_andMatrixOutputs_andMatrixInput_12_182) node decoder_decoded_andMatrixOutputs_lo_lo_277 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_187, decoder_decoded_andMatrixOutputs_andMatrixInput_13_178) node decoder_decoded_andMatrixOutputs_lo_hi_lo_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_199, decoder_decoded_andMatrixOutputs_andMatrixInput_10_193) node decoder_decoded_andMatrixOutputs_lo_hi_hi_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_277, decoder_decoded_andMatrixOutputs_andMatrixInput_8_239) node decoder_decoded_andMatrixOutputs_lo_hi_297 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_199, decoder_decoded_andMatrixOutputs_lo_hi_lo_178) node decoder_decoded_andMatrixOutputs_lo_299 = cat(decoder_decoded_andMatrixOutputs_lo_hi_297, decoder_decoded_andMatrixOutputs_lo_lo_277) node decoder_decoded_andMatrixOutputs_hi_lo_hi_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_299, decoder_decoded_andMatrixOutputs_andMatrixInput_5_297) node decoder_decoded_andMatrixOutputs_hi_lo_291 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_6_291) node decoder_decoded_andMatrixOutputs_hi_hi_lo_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_299, decoder_decoded_andMatrixOutputs_andMatrixInput_3_299) node decoder_decoded_andMatrixOutputs_hi_hi_hi_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_299, decoder_decoded_andMatrixOutputs_andMatrixInput_1_299) node decoder_decoded_andMatrixOutputs_hi_hi_299 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_239, decoder_decoded_andMatrixOutputs_hi_hi_lo_182) node decoder_decoded_andMatrixOutputs_hi_299 = cat(decoder_decoded_andMatrixOutputs_hi_hi_299, decoder_decoded_andMatrixOutputs_hi_lo_291) node _decoder_decoded_andMatrixOutputs_T_299 = cat(decoder_decoded_andMatrixOutputs_hi_299, decoder_decoded_andMatrixOutputs_lo_299) node decoder_decoded_andMatrixOutputs_64_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_299) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_300 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_300 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_300 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_300 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_300 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_298 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_292 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_278 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_240 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_200 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_194 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_188 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_183 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_179 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_188, decoder_decoded_andMatrixOutputs_andMatrixInput_12_183) node decoder_decoded_andMatrixOutputs_lo_lo_278 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_188, decoder_decoded_andMatrixOutputs_andMatrixInput_13_179) node decoder_decoded_andMatrixOutputs_lo_hi_lo_179 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_200, decoder_decoded_andMatrixOutputs_andMatrixInput_10_194) node decoder_decoded_andMatrixOutputs_lo_hi_hi_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_278, decoder_decoded_andMatrixOutputs_andMatrixInput_8_240) node decoder_decoded_andMatrixOutputs_lo_hi_298 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_200, decoder_decoded_andMatrixOutputs_lo_hi_lo_179) node decoder_decoded_andMatrixOutputs_lo_300 = cat(decoder_decoded_andMatrixOutputs_lo_hi_298, decoder_decoded_andMatrixOutputs_lo_lo_278) node decoder_decoded_andMatrixOutputs_hi_lo_hi_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_300, decoder_decoded_andMatrixOutputs_andMatrixInput_5_298) node decoder_decoded_andMatrixOutputs_hi_lo_292 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_6_292) node decoder_decoded_andMatrixOutputs_hi_hi_lo_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_300, decoder_decoded_andMatrixOutputs_andMatrixInput_3_300) node decoder_decoded_andMatrixOutputs_hi_hi_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_300, decoder_decoded_andMatrixOutputs_andMatrixInput_1_300) node decoder_decoded_andMatrixOutputs_hi_hi_300 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_240, decoder_decoded_andMatrixOutputs_hi_hi_lo_183) node decoder_decoded_andMatrixOutputs_hi_300 = cat(decoder_decoded_andMatrixOutputs_hi_hi_300, decoder_decoded_andMatrixOutputs_hi_lo_292) node _decoder_decoded_andMatrixOutputs_T_300 = cat(decoder_decoded_andMatrixOutputs_hi_300, decoder_decoded_andMatrixOutputs_lo_300) node decoder_decoded_andMatrixOutputs_124_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_300) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_301 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_301 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_301 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_301 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_301 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_299 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_293 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_279 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_241 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_201 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_195 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_189 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_184 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_180 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_189, decoder_decoded_andMatrixOutputs_andMatrixInput_12_184) node decoder_decoded_andMatrixOutputs_lo_lo_279 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_189, decoder_decoded_andMatrixOutputs_andMatrixInput_13_180) node decoder_decoded_andMatrixOutputs_lo_hi_lo_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_201, decoder_decoded_andMatrixOutputs_andMatrixInput_10_195) node decoder_decoded_andMatrixOutputs_lo_hi_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_279, decoder_decoded_andMatrixOutputs_andMatrixInput_8_241) node decoder_decoded_andMatrixOutputs_lo_hi_299 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_201, decoder_decoded_andMatrixOutputs_lo_hi_lo_180) node decoder_decoded_andMatrixOutputs_lo_301 = cat(decoder_decoded_andMatrixOutputs_lo_hi_299, decoder_decoded_andMatrixOutputs_lo_lo_279) node decoder_decoded_andMatrixOutputs_hi_lo_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_301, decoder_decoded_andMatrixOutputs_andMatrixInput_5_299) node decoder_decoded_andMatrixOutputs_hi_lo_293 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_6_293) node decoder_decoded_andMatrixOutputs_hi_hi_lo_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_301, decoder_decoded_andMatrixOutputs_andMatrixInput_3_301) node decoder_decoded_andMatrixOutputs_hi_hi_hi_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_301, decoder_decoded_andMatrixOutputs_andMatrixInput_1_301) node decoder_decoded_andMatrixOutputs_hi_hi_301 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_241, decoder_decoded_andMatrixOutputs_hi_hi_lo_184) node decoder_decoded_andMatrixOutputs_hi_301 = cat(decoder_decoded_andMatrixOutputs_hi_hi_301, decoder_decoded_andMatrixOutputs_hi_lo_293) node _decoder_decoded_andMatrixOutputs_T_301 = cat(decoder_decoded_andMatrixOutputs_hi_301, decoder_decoded_andMatrixOutputs_lo_301) node decoder_decoded_andMatrixOutputs_49_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_301) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_302 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_302 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_302 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_302 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_302 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_300 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_294 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_280 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_242 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_202 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_196 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_190 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_185 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_181 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_190, decoder_decoded_andMatrixOutputs_andMatrixInput_12_185) node decoder_decoded_andMatrixOutputs_lo_lo_280 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_190, decoder_decoded_andMatrixOutputs_andMatrixInput_13_181) node decoder_decoded_andMatrixOutputs_lo_hi_lo_181 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_202, decoder_decoded_andMatrixOutputs_andMatrixInput_10_196) node decoder_decoded_andMatrixOutputs_lo_hi_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_280, decoder_decoded_andMatrixOutputs_andMatrixInput_8_242) node decoder_decoded_andMatrixOutputs_lo_hi_300 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_202, decoder_decoded_andMatrixOutputs_lo_hi_lo_181) node decoder_decoded_andMatrixOutputs_lo_302 = cat(decoder_decoded_andMatrixOutputs_lo_hi_300, decoder_decoded_andMatrixOutputs_lo_lo_280) node decoder_decoded_andMatrixOutputs_hi_lo_hi_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_302, decoder_decoded_andMatrixOutputs_andMatrixInput_5_300) node decoder_decoded_andMatrixOutputs_hi_lo_294 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_6_294) node decoder_decoded_andMatrixOutputs_hi_hi_lo_185 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_302, decoder_decoded_andMatrixOutputs_andMatrixInput_3_302) node decoder_decoded_andMatrixOutputs_hi_hi_hi_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_302, decoder_decoded_andMatrixOutputs_andMatrixInput_1_302) node decoder_decoded_andMatrixOutputs_hi_hi_302 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_242, decoder_decoded_andMatrixOutputs_hi_hi_lo_185) node decoder_decoded_andMatrixOutputs_hi_302 = cat(decoder_decoded_andMatrixOutputs_hi_hi_302, decoder_decoded_andMatrixOutputs_hi_lo_294) node _decoder_decoded_andMatrixOutputs_T_302 = cat(decoder_decoded_andMatrixOutputs_hi_302, decoder_decoded_andMatrixOutputs_lo_302) node decoder_decoded_andMatrixOutputs_6_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_302) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_303 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_303 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_303 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_303 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_303 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_301 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_295 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_281 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_243 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_203 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_197 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_191 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_186 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_182 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_191, decoder_decoded_andMatrixOutputs_andMatrixInput_12_186) node decoder_decoded_andMatrixOutputs_lo_lo_281 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_191, decoder_decoded_andMatrixOutputs_andMatrixInput_13_182) node decoder_decoded_andMatrixOutputs_lo_hi_lo_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_203, decoder_decoded_andMatrixOutputs_andMatrixInput_10_197) node decoder_decoded_andMatrixOutputs_lo_hi_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_281, decoder_decoded_andMatrixOutputs_andMatrixInput_8_243) node decoder_decoded_andMatrixOutputs_lo_hi_301 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_203, decoder_decoded_andMatrixOutputs_lo_hi_lo_182) node decoder_decoded_andMatrixOutputs_lo_303 = cat(decoder_decoded_andMatrixOutputs_lo_hi_301, decoder_decoded_andMatrixOutputs_lo_lo_281) node decoder_decoded_andMatrixOutputs_hi_lo_hi_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_303, decoder_decoded_andMatrixOutputs_andMatrixInput_5_301) node decoder_decoded_andMatrixOutputs_hi_lo_295 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_197, decoder_decoded_andMatrixOutputs_andMatrixInput_6_295) node decoder_decoded_andMatrixOutputs_hi_hi_lo_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_303, decoder_decoded_andMatrixOutputs_andMatrixInput_3_303) node decoder_decoded_andMatrixOutputs_hi_hi_hi_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_303, decoder_decoded_andMatrixOutputs_andMatrixInput_1_303) node decoder_decoded_andMatrixOutputs_hi_hi_303 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_243, decoder_decoded_andMatrixOutputs_hi_hi_lo_186) node decoder_decoded_andMatrixOutputs_hi_303 = cat(decoder_decoded_andMatrixOutputs_hi_hi_303, decoder_decoded_andMatrixOutputs_hi_lo_295) node _decoder_decoded_andMatrixOutputs_T_303 = cat(decoder_decoded_andMatrixOutputs_hi_303, decoder_decoded_andMatrixOutputs_lo_303) node decoder_decoded_andMatrixOutputs_134_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_303) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_304 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_304 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_304 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_304 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_304 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_302 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_296 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_282 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_244 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_204 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_198 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_192 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_187 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_183 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_192, decoder_decoded_andMatrixOutputs_andMatrixInput_12_187) node decoder_decoded_andMatrixOutputs_lo_lo_282 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_192, decoder_decoded_andMatrixOutputs_andMatrixInput_13_183) node decoder_decoded_andMatrixOutputs_lo_hi_lo_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_204, decoder_decoded_andMatrixOutputs_andMatrixInput_10_198) node decoder_decoded_andMatrixOutputs_lo_hi_hi_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_282, decoder_decoded_andMatrixOutputs_andMatrixInput_8_244) node decoder_decoded_andMatrixOutputs_lo_hi_302 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_204, decoder_decoded_andMatrixOutputs_lo_hi_lo_183) node decoder_decoded_andMatrixOutputs_lo_304 = cat(decoder_decoded_andMatrixOutputs_lo_hi_302, decoder_decoded_andMatrixOutputs_lo_lo_282) node decoder_decoded_andMatrixOutputs_hi_lo_hi_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_304, decoder_decoded_andMatrixOutputs_andMatrixInput_5_302) node decoder_decoded_andMatrixOutputs_hi_lo_296 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_6_296) node decoder_decoded_andMatrixOutputs_hi_hi_lo_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_304, decoder_decoded_andMatrixOutputs_andMatrixInput_3_304) node decoder_decoded_andMatrixOutputs_hi_hi_hi_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_304, decoder_decoded_andMatrixOutputs_andMatrixInput_1_304) node decoder_decoded_andMatrixOutputs_hi_hi_304 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_244, decoder_decoded_andMatrixOutputs_hi_hi_lo_187) node decoder_decoded_andMatrixOutputs_hi_304 = cat(decoder_decoded_andMatrixOutputs_hi_hi_304, decoder_decoded_andMatrixOutputs_hi_lo_296) node _decoder_decoded_andMatrixOutputs_T_304 = cat(decoder_decoded_andMatrixOutputs_hi_304, decoder_decoded_andMatrixOutputs_lo_304) node decoder_decoded_andMatrixOutputs_153_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_304) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_305 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_305 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_305 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_305 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_305 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_303 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_297 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_283 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_245 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_205 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_199 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_193 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_188 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_184 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_193, decoder_decoded_andMatrixOutputs_andMatrixInput_12_188) node decoder_decoded_andMatrixOutputs_lo_lo_283 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_13_184) node decoder_decoded_andMatrixOutputs_lo_hi_lo_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_205, decoder_decoded_andMatrixOutputs_andMatrixInput_10_199) node decoder_decoded_andMatrixOutputs_lo_hi_hi_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_283, decoder_decoded_andMatrixOutputs_andMatrixInput_8_245) node decoder_decoded_andMatrixOutputs_lo_hi_303 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_205, decoder_decoded_andMatrixOutputs_lo_hi_lo_184) node decoder_decoded_andMatrixOutputs_lo_305 = cat(decoder_decoded_andMatrixOutputs_lo_hi_303, decoder_decoded_andMatrixOutputs_lo_lo_283) node decoder_decoded_andMatrixOutputs_hi_lo_hi_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_305, decoder_decoded_andMatrixOutputs_andMatrixInput_5_303) node decoder_decoded_andMatrixOutputs_hi_lo_297 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_199, decoder_decoded_andMatrixOutputs_andMatrixInput_6_297) node decoder_decoded_andMatrixOutputs_hi_hi_lo_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_305, decoder_decoded_andMatrixOutputs_andMatrixInput_3_305) node decoder_decoded_andMatrixOutputs_hi_hi_hi_245 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_305, decoder_decoded_andMatrixOutputs_andMatrixInput_1_305) node decoder_decoded_andMatrixOutputs_hi_hi_305 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_245, decoder_decoded_andMatrixOutputs_hi_hi_lo_188) node decoder_decoded_andMatrixOutputs_hi_305 = cat(decoder_decoded_andMatrixOutputs_hi_hi_305, decoder_decoded_andMatrixOutputs_hi_lo_297) node _decoder_decoded_andMatrixOutputs_T_305 = cat(decoder_decoded_andMatrixOutputs_hi_305, decoder_decoded_andMatrixOutputs_lo_305) node decoder_decoded_andMatrixOutputs_107_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_305) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_306 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_306 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_306 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_306 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_306 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_304 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_298 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_284 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_246 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_206 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_200 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_194 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_189 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_185 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_161 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_189, decoder_decoded_andMatrixOutputs_andMatrixInput_13_185) node decoder_decoded_andMatrixOutputs_lo_lo_284 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_14_161) node decoder_decoded_andMatrixOutputs_lo_hi_lo_185 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_200, decoder_decoded_andMatrixOutputs_andMatrixInput_11_194) node decoder_decoded_andMatrixOutputs_lo_hi_hi_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_246, decoder_decoded_andMatrixOutputs_andMatrixInput_9_206) node decoder_decoded_andMatrixOutputs_lo_hi_304 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_206, decoder_decoded_andMatrixOutputs_lo_hi_lo_185) node decoder_decoded_andMatrixOutputs_lo_306 = cat(decoder_decoded_andMatrixOutputs_lo_hi_304, decoder_decoded_andMatrixOutputs_lo_lo_284) node decoder_decoded_andMatrixOutputs_hi_lo_lo_161 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_298, decoder_decoded_andMatrixOutputs_andMatrixInput_7_284) node decoder_decoded_andMatrixOutputs_hi_lo_hi_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_306, decoder_decoded_andMatrixOutputs_andMatrixInput_5_304) node decoder_decoded_andMatrixOutputs_hi_lo_298 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_200, decoder_decoded_andMatrixOutputs_hi_lo_lo_161) node decoder_decoded_andMatrixOutputs_hi_hi_lo_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_306, decoder_decoded_andMatrixOutputs_andMatrixInput_3_306) node decoder_decoded_andMatrixOutputs_hi_hi_hi_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_306, decoder_decoded_andMatrixOutputs_andMatrixInput_1_306) node decoder_decoded_andMatrixOutputs_hi_hi_306 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_246, decoder_decoded_andMatrixOutputs_hi_hi_lo_189) node decoder_decoded_andMatrixOutputs_hi_306 = cat(decoder_decoded_andMatrixOutputs_hi_hi_306, decoder_decoded_andMatrixOutputs_hi_lo_298) node _decoder_decoded_andMatrixOutputs_T_306 = cat(decoder_decoded_andMatrixOutputs_hi_306, decoder_decoded_andMatrixOutputs_lo_306) node decoder_decoded_andMatrixOutputs_187_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_306) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_307 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_307 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_307 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_307 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_307 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_305 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_299 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_285 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_247 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_207 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_201 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_195 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_190 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_186 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_162 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_190, decoder_decoded_andMatrixOutputs_andMatrixInput_13_186) node decoder_decoded_andMatrixOutputs_lo_lo_285 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_14_162) node decoder_decoded_andMatrixOutputs_lo_hi_lo_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_201, decoder_decoded_andMatrixOutputs_andMatrixInput_11_195) node decoder_decoded_andMatrixOutputs_lo_hi_hi_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_247, decoder_decoded_andMatrixOutputs_andMatrixInput_9_207) node decoder_decoded_andMatrixOutputs_lo_hi_305 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_207, decoder_decoded_andMatrixOutputs_lo_hi_lo_186) node decoder_decoded_andMatrixOutputs_lo_307 = cat(decoder_decoded_andMatrixOutputs_lo_hi_305, decoder_decoded_andMatrixOutputs_lo_lo_285) node decoder_decoded_andMatrixOutputs_hi_lo_lo_162 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_299, decoder_decoded_andMatrixOutputs_andMatrixInput_7_285) node decoder_decoded_andMatrixOutputs_hi_lo_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_307, decoder_decoded_andMatrixOutputs_andMatrixInput_5_305) node decoder_decoded_andMatrixOutputs_hi_lo_299 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_201, decoder_decoded_andMatrixOutputs_hi_lo_lo_162) node decoder_decoded_andMatrixOutputs_hi_hi_lo_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_307, decoder_decoded_andMatrixOutputs_andMatrixInput_3_307) node decoder_decoded_andMatrixOutputs_hi_hi_hi_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_307, decoder_decoded_andMatrixOutputs_andMatrixInput_1_307) node decoder_decoded_andMatrixOutputs_hi_hi_307 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_247, decoder_decoded_andMatrixOutputs_hi_hi_lo_190) node decoder_decoded_andMatrixOutputs_hi_307 = cat(decoder_decoded_andMatrixOutputs_hi_hi_307, decoder_decoded_andMatrixOutputs_hi_lo_299) node _decoder_decoded_andMatrixOutputs_T_307 = cat(decoder_decoded_andMatrixOutputs_hi_307, decoder_decoded_andMatrixOutputs_lo_307) node decoder_decoded_andMatrixOutputs_46_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_307) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_308 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_308 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_308 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_308 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_308 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_306 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_300 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_286 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_248 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_208 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_202 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_196 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_lo_lo_hi_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_208, decoder_decoded_andMatrixOutputs_andMatrixInput_10_202) node decoder_decoded_andMatrixOutputs_lo_lo_286 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_11_196) node decoder_decoded_andMatrixOutputs_lo_hi_hi_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_300, decoder_decoded_andMatrixOutputs_andMatrixInput_7_286) node decoder_decoded_andMatrixOutputs_lo_hi_306 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_208, decoder_decoded_andMatrixOutputs_andMatrixInput_8_248) node decoder_decoded_andMatrixOutputs_lo_308 = cat(decoder_decoded_andMatrixOutputs_lo_hi_306, decoder_decoded_andMatrixOutputs_lo_lo_286) node decoder_decoded_andMatrixOutputs_hi_lo_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_308, decoder_decoded_andMatrixOutputs_andMatrixInput_4_308) node decoder_decoded_andMatrixOutputs_hi_lo_300 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_202, decoder_decoded_andMatrixOutputs_andMatrixInput_5_306) node decoder_decoded_andMatrixOutputs_hi_hi_hi_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_308, decoder_decoded_andMatrixOutputs_andMatrixInput_1_308) node decoder_decoded_andMatrixOutputs_hi_hi_308 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_248, decoder_decoded_andMatrixOutputs_andMatrixInput_2_308) node decoder_decoded_andMatrixOutputs_hi_308 = cat(decoder_decoded_andMatrixOutputs_hi_hi_308, decoder_decoded_andMatrixOutputs_hi_lo_300) node _decoder_decoded_andMatrixOutputs_T_308 = cat(decoder_decoded_andMatrixOutputs_hi_308, decoder_decoded_andMatrixOutputs_lo_308) node decoder_decoded_andMatrixOutputs_78_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_308) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_309 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_309 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_309 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_309 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_309 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_307 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_301 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_287 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_249 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_209 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_203 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_197 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_191 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_187 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_163 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_191, decoder_decoded_andMatrixOutputs_andMatrixInput_13_187) node decoder_decoded_andMatrixOutputs_lo_lo_287 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_197, decoder_decoded_andMatrixOutputs_andMatrixInput_14_163) node decoder_decoded_andMatrixOutputs_lo_hi_lo_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_203, decoder_decoded_andMatrixOutputs_andMatrixInput_11_197) node decoder_decoded_andMatrixOutputs_lo_hi_hi_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_249, decoder_decoded_andMatrixOutputs_andMatrixInput_9_209) node decoder_decoded_andMatrixOutputs_lo_hi_307 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_209, decoder_decoded_andMatrixOutputs_lo_hi_lo_187) node decoder_decoded_andMatrixOutputs_lo_309 = cat(decoder_decoded_andMatrixOutputs_lo_hi_307, decoder_decoded_andMatrixOutputs_lo_lo_287) node decoder_decoded_andMatrixOutputs_hi_lo_lo_163 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_301, decoder_decoded_andMatrixOutputs_andMatrixInput_7_287) node decoder_decoded_andMatrixOutputs_hi_lo_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_309, decoder_decoded_andMatrixOutputs_andMatrixInput_5_307) node decoder_decoded_andMatrixOutputs_hi_lo_301 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_203, decoder_decoded_andMatrixOutputs_hi_lo_lo_163) node decoder_decoded_andMatrixOutputs_hi_hi_lo_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_309, decoder_decoded_andMatrixOutputs_andMatrixInput_3_309) node decoder_decoded_andMatrixOutputs_hi_hi_hi_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_309, decoder_decoded_andMatrixOutputs_andMatrixInput_1_309) node decoder_decoded_andMatrixOutputs_hi_hi_309 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_249, decoder_decoded_andMatrixOutputs_hi_hi_lo_191) node decoder_decoded_andMatrixOutputs_hi_309 = cat(decoder_decoded_andMatrixOutputs_hi_hi_309, decoder_decoded_andMatrixOutputs_hi_lo_301) node _decoder_decoded_andMatrixOutputs_T_309 = cat(decoder_decoded_andMatrixOutputs_hi_309, decoder_decoded_andMatrixOutputs_lo_309) node decoder_decoded_andMatrixOutputs_159_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_309) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_310 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_310 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_310 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_310 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_310 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_308 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_302 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_288 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_250 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_210 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_204 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_198 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_192 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_188 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_164 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_192, decoder_decoded_andMatrixOutputs_andMatrixInput_13_188) node decoder_decoded_andMatrixOutputs_lo_lo_288 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_14_164) node decoder_decoded_andMatrixOutputs_lo_hi_lo_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_204, decoder_decoded_andMatrixOutputs_andMatrixInput_11_198) node decoder_decoded_andMatrixOutputs_lo_hi_hi_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_250, decoder_decoded_andMatrixOutputs_andMatrixInput_9_210) node decoder_decoded_andMatrixOutputs_lo_hi_308 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_210, decoder_decoded_andMatrixOutputs_lo_hi_lo_188) node decoder_decoded_andMatrixOutputs_lo_310 = cat(decoder_decoded_andMatrixOutputs_lo_hi_308, decoder_decoded_andMatrixOutputs_lo_lo_288) node decoder_decoded_andMatrixOutputs_hi_lo_lo_164 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_302, decoder_decoded_andMatrixOutputs_andMatrixInput_7_288) node decoder_decoded_andMatrixOutputs_hi_lo_hi_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_310, decoder_decoded_andMatrixOutputs_andMatrixInput_5_308) node decoder_decoded_andMatrixOutputs_hi_lo_302 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_204, decoder_decoded_andMatrixOutputs_hi_lo_lo_164) node decoder_decoded_andMatrixOutputs_hi_hi_lo_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_310, decoder_decoded_andMatrixOutputs_andMatrixInput_3_310) node decoder_decoded_andMatrixOutputs_hi_hi_hi_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_310, decoder_decoded_andMatrixOutputs_andMatrixInput_1_310) node decoder_decoded_andMatrixOutputs_hi_hi_310 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_250, decoder_decoded_andMatrixOutputs_hi_hi_lo_192) node decoder_decoded_andMatrixOutputs_hi_310 = cat(decoder_decoded_andMatrixOutputs_hi_hi_310, decoder_decoded_andMatrixOutputs_hi_lo_302) node _decoder_decoded_andMatrixOutputs_T_310 = cat(decoder_decoded_andMatrixOutputs_hi_310, decoder_decoded_andMatrixOutputs_lo_310) node decoder_decoded_andMatrixOutputs_34_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_310) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_311 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_311 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_311 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_311 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_311 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_309 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_303 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_289 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_251 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_211 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_205 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_199 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_193 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_189 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_165 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_193, decoder_decoded_andMatrixOutputs_andMatrixInput_13_189) node decoder_decoded_andMatrixOutputs_lo_lo_289 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_199, decoder_decoded_andMatrixOutputs_andMatrixInput_14_165) node decoder_decoded_andMatrixOutputs_lo_hi_lo_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_205, decoder_decoded_andMatrixOutputs_andMatrixInput_11_199) node decoder_decoded_andMatrixOutputs_lo_hi_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_251, decoder_decoded_andMatrixOutputs_andMatrixInput_9_211) node decoder_decoded_andMatrixOutputs_lo_hi_309 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_211, decoder_decoded_andMatrixOutputs_lo_hi_lo_189) node decoder_decoded_andMatrixOutputs_lo_311 = cat(decoder_decoded_andMatrixOutputs_lo_hi_309, decoder_decoded_andMatrixOutputs_lo_lo_289) node decoder_decoded_andMatrixOutputs_hi_lo_lo_165 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_303, decoder_decoded_andMatrixOutputs_andMatrixInput_7_289) node decoder_decoded_andMatrixOutputs_hi_lo_hi_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_311, decoder_decoded_andMatrixOutputs_andMatrixInput_5_309) node decoder_decoded_andMatrixOutputs_hi_lo_303 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_205, decoder_decoded_andMatrixOutputs_hi_lo_lo_165) node decoder_decoded_andMatrixOutputs_hi_hi_lo_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_311, decoder_decoded_andMatrixOutputs_andMatrixInput_3_311) node decoder_decoded_andMatrixOutputs_hi_hi_hi_251 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_311, decoder_decoded_andMatrixOutputs_andMatrixInput_1_311) node decoder_decoded_andMatrixOutputs_hi_hi_311 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_251, decoder_decoded_andMatrixOutputs_hi_hi_lo_193) node decoder_decoded_andMatrixOutputs_hi_311 = cat(decoder_decoded_andMatrixOutputs_hi_hi_311, decoder_decoded_andMatrixOutputs_hi_lo_303) node _decoder_decoded_andMatrixOutputs_T_311 = cat(decoder_decoded_andMatrixOutputs_hi_311, decoder_decoded_andMatrixOutputs_lo_311) node decoder_decoded_andMatrixOutputs_85_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_311) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_312 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_312 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_312 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_312 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_312 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_310 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_304 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_290 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_252 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_212 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_206 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_200 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_194 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_190 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_166 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_194, decoder_decoded_andMatrixOutputs_andMatrixInput_13_190) node decoder_decoded_andMatrixOutputs_lo_lo_290 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_200, decoder_decoded_andMatrixOutputs_andMatrixInput_14_166) node decoder_decoded_andMatrixOutputs_lo_hi_lo_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_206, decoder_decoded_andMatrixOutputs_andMatrixInput_11_200) node decoder_decoded_andMatrixOutputs_lo_hi_hi_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_252, decoder_decoded_andMatrixOutputs_andMatrixInput_9_212) node decoder_decoded_andMatrixOutputs_lo_hi_310 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_212, decoder_decoded_andMatrixOutputs_lo_hi_lo_190) node decoder_decoded_andMatrixOutputs_lo_312 = cat(decoder_decoded_andMatrixOutputs_lo_hi_310, decoder_decoded_andMatrixOutputs_lo_lo_290) node decoder_decoded_andMatrixOutputs_hi_lo_lo_166 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_304, decoder_decoded_andMatrixOutputs_andMatrixInput_7_290) node decoder_decoded_andMatrixOutputs_hi_lo_hi_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_312, decoder_decoded_andMatrixOutputs_andMatrixInput_5_310) node decoder_decoded_andMatrixOutputs_hi_lo_304 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_206, decoder_decoded_andMatrixOutputs_hi_lo_lo_166) node decoder_decoded_andMatrixOutputs_hi_hi_lo_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_312, decoder_decoded_andMatrixOutputs_andMatrixInput_3_312) node decoder_decoded_andMatrixOutputs_hi_hi_hi_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_312, decoder_decoded_andMatrixOutputs_andMatrixInput_1_312) node decoder_decoded_andMatrixOutputs_hi_hi_312 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_252, decoder_decoded_andMatrixOutputs_hi_hi_lo_194) node decoder_decoded_andMatrixOutputs_hi_312 = cat(decoder_decoded_andMatrixOutputs_hi_hi_312, decoder_decoded_andMatrixOutputs_hi_lo_304) node _decoder_decoded_andMatrixOutputs_T_312 = cat(decoder_decoded_andMatrixOutputs_hi_312, decoder_decoded_andMatrixOutputs_lo_312) node decoder_decoded_andMatrixOutputs_10_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_312) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_313 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_313 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_313 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_313 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_313 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_311 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_305 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_291 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_253 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_213 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_207 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_201 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_195 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_191 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_167 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_195, decoder_decoded_andMatrixOutputs_andMatrixInput_13_191) node decoder_decoded_andMatrixOutputs_lo_lo_291 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_14_167) node decoder_decoded_andMatrixOutputs_lo_hi_lo_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_207, decoder_decoded_andMatrixOutputs_andMatrixInput_11_201) node decoder_decoded_andMatrixOutputs_lo_hi_hi_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_253, decoder_decoded_andMatrixOutputs_andMatrixInput_9_213) node decoder_decoded_andMatrixOutputs_lo_hi_311 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_213, decoder_decoded_andMatrixOutputs_lo_hi_lo_191) node decoder_decoded_andMatrixOutputs_lo_313 = cat(decoder_decoded_andMatrixOutputs_lo_hi_311, decoder_decoded_andMatrixOutputs_lo_lo_291) node decoder_decoded_andMatrixOutputs_hi_lo_lo_167 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_305, decoder_decoded_andMatrixOutputs_andMatrixInput_7_291) node decoder_decoded_andMatrixOutputs_hi_lo_hi_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_313, decoder_decoded_andMatrixOutputs_andMatrixInput_5_311) node decoder_decoded_andMatrixOutputs_hi_lo_305 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_207, decoder_decoded_andMatrixOutputs_hi_lo_lo_167) node decoder_decoded_andMatrixOutputs_hi_hi_lo_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_313, decoder_decoded_andMatrixOutputs_andMatrixInput_3_313) node decoder_decoded_andMatrixOutputs_hi_hi_hi_253 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_313, decoder_decoded_andMatrixOutputs_andMatrixInput_1_313) node decoder_decoded_andMatrixOutputs_hi_hi_313 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_253, decoder_decoded_andMatrixOutputs_hi_hi_lo_195) node decoder_decoded_andMatrixOutputs_hi_313 = cat(decoder_decoded_andMatrixOutputs_hi_hi_313, decoder_decoded_andMatrixOutputs_hi_lo_305) node _decoder_decoded_andMatrixOutputs_T_313 = cat(decoder_decoded_andMatrixOutputs_hi_313, decoder_decoded_andMatrixOutputs_lo_313) node decoder_decoded_andMatrixOutputs_92_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_313) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_314 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_314 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_314 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_314 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_314 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_312 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_306 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_292 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_254 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_214 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_208 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_202 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_196 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_192 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_168 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_196, decoder_decoded_andMatrixOutputs_andMatrixInput_13_192) node decoder_decoded_andMatrixOutputs_lo_lo_292 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_202, decoder_decoded_andMatrixOutputs_andMatrixInput_14_168) node decoder_decoded_andMatrixOutputs_lo_hi_lo_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_208, decoder_decoded_andMatrixOutputs_andMatrixInput_11_202) node decoder_decoded_andMatrixOutputs_lo_hi_hi_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_254, decoder_decoded_andMatrixOutputs_andMatrixInput_9_214) node decoder_decoded_andMatrixOutputs_lo_hi_312 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_214, decoder_decoded_andMatrixOutputs_lo_hi_lo_192) node decoder_decoded_andMatrixOutputs_lo_314 = cat(decoder_decoded_andMatrixOutputs_lo_hi_312, decoder_decoded_andMatrixOutputs_lo_lo_292) node decoder_decoded_andMatrixOutputs_hi_lo_lo_168 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_306, decoder_decoded_andMatrixOutputs_andMatrixInput_7_292) node decoder_decoded_andMatrixOutputs_hi_lo_hi_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_314, decoder_decoded_andMatrixOutputs_andMatrixInput_5_312) node decoder_decoded_andMatrixOutputs_hi_lo_306 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_208, decoder_decoded_andMatrixOutputs_hi_lo_lo_168) node decoder_decoded_andMatrixOutputs_hi_hi_lo_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_314, decoder_decoded_andMatrixOutputs_andMatrixInput_3_314) node decoder_decoded_andMatrixOutputs_hi_hi_hi_254 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_314, decoder_decoded_andMatrixOutputs_andMatrixInput_1_314) node decoder_decoded_andMatrixOutputs_hi_hi_314 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_254, decoder_decoded_andMatrixOutputs_hi_hi_lo_196) node decoder_decoded_andMatrixOutputs_hi_314 = cat(decoder_decoded_andMatrixOutputs_hi_hi_314, decoder_decoded_andMatrixOutputs_hi_lo_306) node _decoder_decoded_andMatrixOutputs_T_314 = cat(decoder_decoded_andMatrixOutputs_hi_314, decoder_decoded_andMatrixOutputs_lo_314) node decoder_decoded_andMatrixOutputs_180_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_314) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_315 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_315 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_315 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_315 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_315 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_313 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_307 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_293 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_255 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_215 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_209 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_203 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_197 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_193 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_169 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_101 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_101 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_169, decoder_decoded_andMatrixOutputs_andMatrixInput_15_101) node decoder_decoded_andMatrixOutputs_lo_lo_hi_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_197, decoder_decoded_andMatrixOutputs_andMatrixInput_13_193) node decoder_decoded_andMatrixOutputs_lo_lo_293 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_203, decoder_decoded_andMatrixOutputs_lo_lo_lo_101) node decoder_decoded_andMatrixOutputs_lo_hi_lo_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_209, decoder_decoded_andMatrixOutputs_andMatrixInput_11_203) node decoder_decoded_andMatrixOutputs_lo_hi_hi_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_255, decoder_decoded_andMatrixOutputs_andMatrixInput_9_215) node decoder_decoded_andMatrixOutputs_lo_hi_313 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_215, decoder_decoded_andMatrixOutputs_lo_hi_lo_193) node decoder_decoded_andMatrixOutputs_lo_315 = cat(decoder_decoded_andMatrixOutputs_lo_hi_313, decoder_decoded_andMatrixOutputs_lo_lo_293) node decoder_decoded_andMatrixOutputs_hi_lo_lo_169 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_307, decoder_decoded_andMatrixOutputs_andMatrixInput_7_293) node decoder_decoded_andMatrixOutputs_hi_lo_hi_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_315, decoder_decoded_andMatrixOutputs_andMatrixInput_5_313) node decoder_decoded_andMatrixOutputs_hi_lo_307 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_209, decoder_decoded_andMatrixOutputs_hi_lo_lo_169) node decoder_decoded_andMatrixOutputs_hi_hi_lo_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_315, decoder_decoded_andMatrixOutputs_andMatrixInput_3_315) node decoder_decoded_andMatrixOutputs_hi_hi_hi_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_315, decoder_decoded_andMatrixOutputs_andMatrixInput_1_315) node decoder_decoded_andMatrixOutputs_hi_hi_315 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_255, decoder_decoded_andMatrixOutputs_hi_hi_lo_197) node decoder_decoded_andMatrixOutputs_hi_315 = cat(decoder_decoded_andMatrixOutputs_hi_hi_315, decoder_decoded_andMatrixOutputs_hi_lo_307) node _decoder_decoded_andMatrixOutputs_T_315 = cat(decoder_decoded_andMatrixOutputs_hi_315, decoder_decoded_andMatrixOutputs_lo_315) node decoder_decoded_andMatrixOutputs_44_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_315) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_316 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_316 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_316 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_316 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_316 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_314 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_308 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_294 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_256 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_216 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_210 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_204 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_198 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_194 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_170 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_102 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_102 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_170, decoder_decoded_andMatrixOutputs_andMatrixInput_15_102) node decoder_decoded_andMatrixOutputs_lo_lo_hi_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_198, decoder_decoded_andMatrixOutputs_andMatrixInput_13_194) node decoder_decoded_andMatrixOutputs_lo_lo_294 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_204, decoder_decoded_andMatrixOutputs_lo_lo_lo_102) node decoder_decoded_andMatrixOutputs_lo_hi_lo_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_210, decoder_decoded_andMatrixOutputs_andMatrixInput_11_204) node decoder_decoded_andMatrixOutputs_lo_hi_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_256, decoder_decoded_andMatrixOutputs_andMatrixInput_9_216) node decoder_decoded_andMatrixOutputs_lo_hi_314 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_216, decoder_decoded_andMatrixOutputs_lo_hi_lo_194) node decoder_decoded_andMatrixOutputs_lo_316 = cat(decoder_decoded_andMatrixOutputs_lo_hi_314, decoder_decoded_andMatrixOutputs_lo_lo_294) node decoder_decoded_andMatrixOutputs_hi_lo_lo_170 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_308, decoder_decoded_andMatrixOutputs_andMatrixInput_7_294) node decoder_decoded_andMatrixOutputs_hi_lo_hi_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_316, decoder_decoded_andMatrixOutputs_andMatrixInput_5_314) node decoder_decoded_andMatrixOutputs_hi_lo_308 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_210, decoder_decoded_andMatrixOutputs_hi_lo_lo_170) node decoder_decoded_andMatrixOutputs_hi_hi_lo_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_316, decoder_decoded_andMatrixOutputs_andMatrixInput_3_316) node decoder_decoded_andMatrixOutputs_hi_hi_hi_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_316, decoder_decoded_andMatrixOutputs_andMatrixInput_1_316) node decoder_decoded_andMatrixOutputs_hi_hi_316 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_256, decoder_decoded_andMatrixOutputs_hi_hi_lo_198) node decoder_decoded_andMatrixOutputs_hi_316 = cat(decoder_decoded_andMatrixOutputs_hi_hi_316, decoder_decoded_andMatrixOutputs_hi_lo_308) node _decoder_decoded_andMatrixOutputs_T_316 = cat(decoder_decoded_andMatrixOutputs_hi_316, decoder_decoded_andMatrixOutputs_lo_316) node decoder_decoded_andMatrixOutputs_135_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_316) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_317 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_317 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_317 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_317 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_317 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_315 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_309 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_295 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_257 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_217 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_211 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_205 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_199 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_195 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_171 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_103 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_61 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_103 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_103, decoder_decoded_andMatrixOutputs_andMatrixInput_16_61) node decoder_decoded_andMatrixOutputs_lo_lo_hi_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_195, decoder_decoded_andMatrixOutputs_andMatrixInput_14_171) node decoder_decoded_andMatrixOutputs_lo_lo_295 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_205, decoder_decoded_andMatrixOutputs_lo_lo_lo_103) node decoder_decoded_andMatrixOutputs_lo_hi_lo_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_205, decoder_decoded_andMatrixOutputs_andMatrixInput_12_199) node decoder_decoded_andMatrixOutputs_lo_hi_hi_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_217, decoder_decoded_andMatrixOutputs_andMatrixInput_10_211) node decoder_decoded_andMatrixOutputs_lo_hi_315 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_217, decoder_decoded_andMatrixOutputs_lo_hi_lo_195) node decoder_decoded_andMatrixOutputs_lo_317 = cat(decoder_decoded_andMatrixOutputs_lo_hi_315, decoder_decoded_andMatrixOutputs_lo_lo_295) node decoder_decoded_andMatrixOutputs_hi_lo_lo_171 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_295, decoder_decoded_andMatrixOutputs_andMatrixInput_8_257) node decoder_decoded_andMatrixOutputs_hi_lo_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_315, decoder_decoded_andMatrixOutputs_andMatrixInput_6_309) node decoder_decoded_andMatrixOutputs_hi_lo_309 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_211, decoder_decoded_andMatrixOutputs_hi_lo_lo_171) node decoder_decoded_andMatrixOutputs_hi_hi_lo_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_317, decoder_decoded_andMatrixOutputs_andMatrixInput_4_317) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_317, decoder_decoded_andMatrixOutputs_andMatrixInput_1_317) node decoder_decoded_andMatrixOutputs_hi_hi_hi_257 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_2_317) node decoder_decoded_andMatrixOutputs_hi_hi_317 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_257, decoder_decoded_andMatrixOutputs_hi_hi_lo_199) node decoder_decoded_andMatrixOutputs_hi_317 = cat(decoder_decoded_andMatrixOutputs_hi_hi_317, decoder_decoded_andMatrixOutputs_hi_lo_309) node _decoder_decoded_andMatrixOutputs_T_317 = cat(decoder_decoded_andMatrixOutputs_hi_317, decoder_decoded_andMatrixOutputs_lo_317) node decoder_decoded_andMatrixOutputs_3_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_317) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_318 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_318 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_318 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_318 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_318 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_316 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_310 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_296 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_258 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_218 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_212 = bits(decoder_decoded_plaInput_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_206 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_200 = bits(decoder_decoded_plaInput_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_196 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_172 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_104 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_62 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_45 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_37 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_34 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_25 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_20 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_104 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_25, decoder_decoded_andMatrixOutputs_andMatrixInput_21_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_45, decoder_decoded_andMatrixOutputs_andMatrixInput_18_37) node decoder_decoded_andMatrixOutputs_lo_lo_hi_206 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_19_34) node decoder_decoded_andMatrixOutputs_lo_lo_296 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_206, decoder_decoded_andMatrixOutputs_lo_lo_lo_104) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_172, decoder_decoded_andMatrixOutputs_andMatrixInput_15_104) node decoder_decoded_andMatrixOutputs_lo_hi_lo_196 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_16_62) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_206, decoder_decoded_andMatrixOutputs_andMatrixInput_12_200) node decoder_decoded_andMatrixOutputs_lo_hi_hi_218 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_196) node decoder_decoded_andMatrixOutputs_lo_hi_316 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_218, decoder_decoded_andMatrixOutputs_lo_hi_lo_196) node decoder_decoded_andMatrixOutputs_lo_318 = cat(decoder_decoded_andMatrixOutputs_lo_hi_316, decoder_decoded_andMatrixOutputs_lo_lo_296) node decoder_decoded_andMatrixOutputs_hi_lo_lo_172 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_218, decoder_decoded_andMatrixOutputs_andMatrixInput_10_212) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_310, decoder_decoded_andMatrixOutputs_andMatrixInput_7_296) node decoder_decoded_andMatrixOutputs_hi_lo_hi_212 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_258) node decoder_decoded_andMatrixOutputs_hi_lo_310 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_212, decoder_decoded_andMatrixOutputs_hi_lo_lo_172) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_318, decoder_decoded_andMatrixOutputs_andMatrixInput_4_318) node decoder_decoded_andMatrixOutputs_hi_hi_lo_200 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_316) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_318, decoder_decoded_andMatrixOutputs_andMatrixInput_1_318) node decoder_decoded_andMatrixOutputs_hi_hi_hi_258 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_2_318) node decoder_decoded_andMatrixOutputs_hi_hi_318 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_258, decoder_decoded_andMatrixOutputs_hi_hi_lo_200) node decoder_decoded_andMatrixOutputs_hi_318 = cat(decoder_decoded_andMatrixOutputs_hi_hi_318, decoder_decoded_andMatrixOutputs_hi_lo_310) node _decoder_decoded_andMatrixOutputs_T_318 = cat(decoder_decoded_andMatrixOutputs_hi_318, decoder_decoded_andMatrixOutputs_lo_318) node decoder_decoded_andMatrixOutputs_188_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_318) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_319 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_319 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_319 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_319 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_319 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_317 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_311 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_297 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_259 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_219 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_213 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_207 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_201 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_197 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_173 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_105 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_105 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_173, decoder_decoded_andMatrixOutputs_andMatrixInput_15_105) node decoder_decoded_andMatrixOutputs_lo_lo_hi_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_201, decoder_decoded_andMatrixOutputs_andMatrixInput_13_197) node decoder_decoded_andMatrixOutputs_lo_lo_297 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_207, decoder_decoded_andMatrixOutputs_lo_lo_lo_105) node decoder_decoded_andMatrixOutputs_lo_hi_lo_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_213, decoder_decoded_andMatrixOutputs_andMatrixInput_11_207) node decoder_decoded_andMatrixOutputs_lo_hi_hi_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_259, decoder_decoded_andMatrixOutputs_andMatrixInput_9_219) node decoder_decoded_andMatrixOutputs_lo_hi_317 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_219, decoder_decoded_andMatrixOutputs_lo_hi_lo_197) node decoder_decoded_andMatrixOutputs_lo_319 = cat(decoder_decoded_andMatrixOutputs_lo_hi_317, decoder_decoded_andMatrixOutputs_lo_lo_297) node decoder_decoded_andMatrixOutputs_hi_lo_lo_173 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_311, decoder_decoded_andMatrixOutputs_andMatrixInput_7_297) node decoder_decoded_andMatrixOutputs_hi_lo_hi_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_319, decoder_decoded_andMatrixOutputs_andMatrixInput_5_317) node decoder_decoded_andMatrixOutputs_hi_lo_311 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_213, decoder_decoded_andMatrixOutputs_hi_lo_lo_173) node decoder_decoded_andMatrixOutputs_hi_hi_lo_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_319, decoder_decoded_andMatrixOutputs_andMatrixInput_3_319) node decoder_decoded_andMatrixOutputs_hi_hi_hi_259 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_319, decoder_decoded_andMatrixOutputs_andMatrixInput_1_319) node decoder_decoded_andMatrixOutputs_hi_hi_319 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_259, decoder_decoded_andMatrixOutputs_hi_hi_lo_201) node decoder_decoded_andMatrixOutputs_hi_319 = cat(decoder_decoded_andMatrixOutputs_hi_hi_319, decoder_decoded_andMatrixOutputs_hi_lo_311) node _decoder_decoded_andMatrixOutputs_T_319 = cat(decoder_decoded_andMatrixOutputs_hi_319, decoder_decoded_andMatrixOutputs_lo_319) node decoder_decoded_andMatrixOutputs_4_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_319) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_320 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_320 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_320 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_320 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_320 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_318 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_312 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_298 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_260 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_220 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_214 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_208 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_202 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_198 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_174 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_106 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_106 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_174, decoder_decoded_andMatrixOutputs_andMatrixInput_15_106) node decoder_decoded_andMatrixOutputs_lo_lo_hi_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_202, decoder_decoded_andMatrixOutputs_andMatrixInput_13_198) node decoder_decoded_andMatrixOutputs_lo_lo_298 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_208, decoder_decoded_andMatrixOutputs_lo_lo_lo_106) node decoder_decoded_andMatrixOutputs_lo_hi_lo_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_214, decoder_decoded_andMatrixOutputs_andMatrixInput_11_208) node decoder_decoded_andMatrixOutputs_lo_hi_hi_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_260, decoder_decoded_andMatrixOutputs_andMatrixInput_9_220) node decoder_decoded_andMatrixOutputs_lo_hi_318 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_220, decoder_decoded_andMatrixOutputs_lo_hi_lo_198) node decoder_decoded_andMatrixOutputs_lo_320 = cat(decoder_decoded_andMatrixOutputs_lo_hi_318, decoder_decoded_andMatrixOutputs_lo_lo_298) node decoder_decoded_andMatrixOutputs_hi_lo_lo_174 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_312, decoder_decoded_andMatrixOutputs_andMatrixInput_7_298) node decoder_decoded_andMatrixOutputs_hi_lo_hi_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_320, decoder_decoded_andMatrixOutputs_andMatrixInput_5_318) node decoder_decoded_andMatrixOutputs_hi_lo_312 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_214, decoder_decoded_andMatrixOutputs_hi_lo_lo_174) node decoder_decoded_andMatrixOutputs_hi_hi_lo_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_320, decoder_decoded_andMatrixOutputs_andMatrixInput_3_320) node decoder_decoded_andMatrixOutputs_hi_hi_hi_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_320, decoder_decoded_andMatrixOutputs_andMatrixInput_1_320) node decoder_decoded_andMatrixOutputs_hi_hi_320 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_260, decoder_decoded_andMatrixOutputs_hi_hi_lo_202) node decoder_decoded_andMatrixOutputs_hi_320 = cat(decoder_decoded_andMatrixOutputs_hi_hi_320, decoder_decoded_andMatrixOutputs_hi_lo_312) node _decoder_decoded_andMatrixOutputs_T_320 = cat(decoder_decoded_andMatrixOutputs_hi_320, decoder_decoded_andMatrixOutputs_lo_320) node decoder_decoded_andMatrixOutputs_25_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_320) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_321 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_321 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_321 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_321 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_321 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_319 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_313 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_299 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_261 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_221 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_215 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_209 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_221, decoder_decoded_andMatrixOutputs_andMatrixInput_10_215) node decoder_decoded_andMatrixOutputs_lo_lo_299 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_209, decoder_decoded_andMatrixOutputs_andMatrixInput_11_209) node decoder_decoded_andMatrixOutputs_lo_hi_hi_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_313, decoder_decoded_andMatrixOutputs_andMatrixInput_7_299) node decoder_decoded_andMatrixOutputs_lo_hi_319 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_221, decoder_decoded_andMatrixOutputs_andMatrixInput_8_261) node decoder_decoded_andMatrixOutputs_lo_321 = cat(decoder_decoded_andMatrixOutputs_lo_hi_319, decoder_decoded_andMatrixOutputs_lo_lo_299) node decoder_decoded_andMatrixOutputs_hi_lo_hi_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_321, decoder_decoded_andMatrixOutputs_andMatrixInput_4_321) node decoder_decoded_andMatrixOutputs_hi_lo_313 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_5_319) node decoder_decoded_andMatrixOutputs_hi_hi_hi_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_321, decoder_decoded_andMatrixOutputs_andMatrixInput_1_321) node decoder_decoded_andMatrixOutputs_hi_hi_321 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_261, decoder_decoded_andMatrixOutputs_andMatrixInput_2_321) node decoder_decoded_andMatrixOutputs_hi_321 = cat(decoder_decoded_andMatrixOutputs_hi_hi_321, decoder_decoded_andMatrixOutputs_hi_lo_313) node _decoder_decoded_andMatrixOutputs_T_321 = cat(decoder_decoded_andMatrixOutputs_hi_321, decoder_decoded_andMatrixOutputs_lo_321) node decoder_decoded_andMatrixOutputs_57_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_321) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_322 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_322 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_322 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_322 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_322 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_320 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_314 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_300 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_262 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_222 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_216 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_210 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_203 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_199 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_175 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_203, decoder_decoded_andMatrixOutputs_andMatrixInput_13_199) node decoder_decoded_andMatrixOutputs_lo_lo_300 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_14_175) node decoder_decoded_andMatrixOutputs_lo_hi_lo_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_216, decoder_decoded_andMatrixOutputs_andMatrixInput_11_210) node decoder_decoded_andMatrixOutputs_lo_hi_hi_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_262, decoder_decoded_andMatrixOutputs_andMatrixInput_9_222) node decoder_decoded_andMatrixOutputs_lo_hi_320 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_222, decoder_decoded_andMatrixOutputs_lo_hi_lo_199) node decoder_decoded_andMatrixOutputs_lo_322 = cat(decoder_decoded_andMatrixOutputs_lo_hi_320, decoder_decoded_andMatrixOutputs_lo_lo_300) node decoder_decoded_andMatrixOutputs_hi_lo_lo_175 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_314, decoder_decoded_andMatrixOutputs_andMatrixInput_7_300) node decoder_decoded_andMatrixOutputs_hi_lo_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_322, decoder_decoded_andMatrixOutputs_andMatrixInput_5_320) node decoder_decoded_andMatrixOutputs_hi_lo_314 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_216, decoder_decoded_andMatrixOutputs_hi_lo_lo_175) node decoder_decoded_andMatrixOutputs_hi_hi_lo_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_322, decoder_decoded_andMatrixOutputs_andMatrixInput_3_322) node decoder_decoded_andMatrixOutputs_hi_hi_hi_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_322, decoder_decoded_andMatrixOutputs_andMatrixInput_1_322) node decoder_decoded_andMatrixOutputs_hi_hi_322 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_262, decoder_decoded_andMatrixOutputs_hi_hi_lo_203) node decoder_decoded_andMatrixOutputs_hi_322 = cat(decoder_decoded_andMatrixOutputs_hi_hi_322, decoder_decoded_andMatrixOutputs_hi_lo_314) node _decoder_decoded_andMatrixOutputs_T_322 = cat(decoder_decoded_andMatrixOutputs_hi_322, decoder_decoded_andMatrixOutputs_lo_322) node decoder_decoded_andMatrixOutputs_147_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_322) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_323 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_323 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_323 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_323 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_323 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_321 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_315 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_301 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_263 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_223 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_217 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_211 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_204 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_200 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_176 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_107 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_107 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_176, decoder_decoded_andMatrixOutputs_andMatrixInput_15_107) node decoder_decoded_andMatrixOutputs_lo_lo_hi_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_204, decoder_decoded_andMatrixOutputs_andMatrixInput_13_200) node decoder_decoded_andMatrixOutputs_lo_lo_301 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_211, decoder_decoded_andMatrixOutputs_lo_lo_lo_107) node decoder_decoded_andMatrixOutputs_lo_hi_lo_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_217, decoder_decoded_andMatrixOutputs_andMatrixInput_11_211) node decoder_decoded_andMatrixOutputs_lo_hi_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_263, decoder_decoded_andMatrixOutputs_andMatrixInput_9_223) node decoder_decoded_andMatrixOutputs_lo_hi_321 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_223, decoder_decoded_andMatrixOutputs_lo_hi_lo_200) node decoder_decoded_andMatrixOutputs_lo_323 = cat(decoder_decoded_andMatrixOutputs_lo_hi_321, decoder_decoded_andMatrixOutputs_lo_lo_301) node decoder_decoded_andMatrixOutputs_hi_lo_lo_176 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_315, decoder_decoded_andMatrixOutputs_andMatrixInput_7_301) node decoder_decoded_andMatrixOutputs_hi_lo_hi_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_323, decoder_decoded_andMatrixOutputs_andMatrixInput_5_321) node decoder_decoded_andMatrixOutputs_hi_lo_315 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_217, decoder_decoded_andMatrixOutputs_hi_lo_lo_176) node decoder_decoded_andMatrixOutputs_hi_hi_lo_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_323, decoder_decoded_andMatrixOutputs_andMatrixInput_3_323) node decoder_decoded_andMatrixOutputs_hi_hi_hi_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_323, decoder_decoded_andMatrixOutputs_andMatrixInput_1_323) node decoder_decoded_andMatrixOutputs_hi_hi_323 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_263, decoder_decoded_andMatrixOutputs_hi_hi_lo_204) node decoder_decoded_andMatrixOutputs_hi_323 = cat(decoder_decoded_andMatrixOutputs_hi_hi_323, decoder_decoded_andMatrixOutputs_hi_lo_315) node _decoder_decoded_andMatrixOutputs_T_323 = cat(decoder_decoded_andMatrixOutputs_hi_323, decoder_decoded_andMatrixOutputs_lo_323) node decoder_decoded_andMatrixOutputs_27_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_323) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_324 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_324 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_324 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_324 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_324 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_322 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_316 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_302 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_264 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_224 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_218 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_212 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_205 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_201 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_177 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_205, decoder_decoded_andMatrixOutputs_andMatrixInput_13_201) node decoder_decoded_andMatrixOutputs_lo_lo_302 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_14_177) node decoder_decoded_andMatrixOutputs_lo_hi_lo_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_218, decoder_decoded_andMatrixOutputs_andMatrixInput_11_212) node decoder_decoded_andMatrixOutputs_lo_hi_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_264, decoder_decoded_andMatrixOutputs_andMatrixInput_9_224) node decoder_decoded_andMatrixOutputs_lo_hi_322 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_224, decoder_decoded_andMatrixOutputs_lo_hi_lo_201) node decoder_decoded_andMatrixOutputs_lo_324 = cat(decoder_decoded_andMatrixOutputs_lo_hi_322, decoder_decoded_andMatrixOutputs_lo_lo_302) node decoder_decoded_andMatrixOutputs_hi_lo_lo_177 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_316, decoder_decoded_andMatrixOutputs_andMatrixInput_7_302) node decoder_decoded_andMatrixOutputs_hi_lo_hi_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_324, decoder_decoded_andMatrixOutputs_andMatrixInput_5_322) node decoder_decoded_andMatrixOutputs_hi_lo_316 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_218, decoder_decoded_andMatrixOutputs_hi_lo_lo_177) node decoder_decoded_andMatrixOutputs_hi_hi_lo_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_324, decoder_decoded_andMatrixOutputs_andMatrixInput_3_324) node decoder_decoded_andMatrixOutputs_hi_hi_hi_264 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_324, decoder_decoded_andMatrixOutputs_andMatrixInput_1_324) node decoder_decoded_andMatrixOutputs_hi_hi_324 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_264, decoder_decoded_andMatrixOutputs_hi_hi_lo_205) node decoder_decoded_andMatrixOutputs_hi_324 = cat(decoder_decoded_andMatrixOutputs_hi_hi_324, decoder_decoded_andMatrixOutputs_hi_lo_316) node _decoder_decoded_andMatrixOutputs_T_324 = cat(decoder_decoded_andMatrixOutputs_hi_324, decoder_decoded_andMatrixOutputs_lo_324) node decoder_decoded_andMatrixOutputs_51_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_324) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_325 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_325 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_325 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_325 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_325 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_323 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_317 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_303 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_265 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_225 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_219 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_213 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_206 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_202 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_178 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_206, decoder_decoded_andMatrixOutputs_andMatrixInput_13_202) node decoder_decoded_andMatrixOutputs_lo_lo_303 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_213, decoder_decoded_andMatrixOutputs_andMatrixInput_14_178) node decoder_decoded_andMatrixOutputs_lo_hi_lo_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_219, decoder_decoded_andMatrixOutputs_andMatrixInput_11_213) node decoder_decoded_andMatrixOutputs_lo_hi_hi_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_265, decoder_decoded_andMatrixOutputs_andMatrixInput_9_225) node decoder_decoded_andMatrixOutputs_lo_hi_323 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_225, decoder_decoded_andMatrixOutputs_lo_hi_lo_202) node decoder_decoded_andMatrixOutputs_lo_325 = cat(decoder_decoded_andMatrixOutputs_lo_hi_323, decoder_decoded_andMatrixOutputs_lo_lo_303) node decoder_decoded_andMatrixOutputs_hi_lo_lo_178 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_317, decoder_decoded_andMatrixOutputs_andMatrixInput_7_303) node decoder_decoded_andMatrixOutputs_hi_lo_hi_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_325, decoder_decoded_andMatrixOutputs_andMatrixInput_5_323) node decoder_decoded_andMatrixOutputs_hi_lo_317 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_219, decoder_decoded_andMatrixOutputs_hi_lo_lo_178) node decoder_decoded_andMatrixOutputs_hi_hi_lo_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_325, decoder_decoded_andMatrixOutputs_andMatrixInput_3_325) node decoder_decoded_andMatrixOutputs_hi_hi_hi_265 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_325, decoder_decoded_andMatrixOutputs_andMatrixInput_1_325) node decoder_decoded_andMatrixOutputs_hi_hi_325 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_265, decoder_decoded_andMatrixOutputs_hi_hi_lo_206) node decoder_decoded_andMatrixOutputs_hi_325 = cat(decoder_decoded_andMatrixOutputs_hi_hi_325, decoder_decoded_andMatrixOutputs_hi_lo_317) node _decoder_decoded_andMatrixOutputs_T_325 = cat(decoder_decoded_andMatrixOutputs_hi_325, decoder_decoded_andMatrixOutputs_lo_325) node decoder_decoded_andMatrixOutputs_138_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_325) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_326 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_326 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_326 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_326 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_326 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_324 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_318 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_304 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_266 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_226 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_220 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_214 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_207 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_203 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_179 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_108 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_108 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_179, decoder_decoded_andMatrixOutputs_andMatrixInput_15_108) node decoder_decoded_andMatrixOutputs_lo_lo_hi_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_207, decoder_decoded_andMatrixOutputs_andMatrixInput_13_203) node decoder_decoded_andMatrixOutputs_lo_lo_304 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_214, decoder_decoded_andMatrixOutputs_lo_lo_lo_108) node decoder_decoded_andMatrixOutputs_lo_hi_lo_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_220, decoder_decoded_andMatrixOutputs_andMatrixInput_11_214) node decoder_decoded_andMatrixOutputs_lo_hi_hi_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_266, decoder_decoded_andMatrixOutputs_andMatrixInput_9_226) node decoder_decoded_andMatrixOutputs_lo_hi_324 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_226, decoder_decoded_andMatrixOutputs_lo_hi_lo_203) node decoder_decoded_andMatrixOutputs_lo_326 = cat(decoder_decoded_andMatrixOutputs_lo_hi_324, decoder_decoded_andMatrixOutputs_lo_lo_304) node decoder_decoded_andMatrixOutputs_hi_lo_lo_179 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_318, decoder_decoded_andMatrixOutputs_andMatrixInput_7_304) node decoder_decoded_andMatrixOutputs_hi_lo_hi_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_326, decoder_decoded_andMatrixOutputs_andMatrixInput_5_324) node decoder_decoded_andMatrixOutputs_hi_lo_318 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_220, decoder_decoded_andMatrixOutputs_hi_lo_lo_179) node decoder_decoded_andMatrixOutputs_hi_hi_lo_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_326, decoder_decoded_andMatrixOutputs_andMatrixInput_3_326) node decoder_decoded_andMatrixOutputs_hi_hi_hi_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_326, decoder_decoded_andMatrixOutputs_andMatrixInput_1_326) node decoder_decoded_andMatrixOutputs_hi_hi_326 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_266, decoder_decoded_andMatrixOutputs_hi_hi_lo_207) node decoder_decoded_andMatrixOutputs_hi_326 = cat(decoder_decoded_andMatrixOutputs_hi_hi_326, decoder_decoded_andMatrixOutputs_hi_lo_318) node _decoder_decoded_andMatrixOutputs_T_326 = cat(decoder_decoded_andMatrixOutputs_hi_326, decoder_decoded_andMatrixOutputs_lo_326) node decoder_decoded_andMatrixOutputs_178_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_326) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_327 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_327 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_327 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_327 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_327 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_325 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_319 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_305 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_267 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_227 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_221 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_215 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_208 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_204 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_180 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_208, decoder_decoded_andMatrixOutputs_andMatrixInput_13_204) node decoder_decoded_andMatrixOutputs_lo_lo_305 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_14_180) node decoder_decoded_andMatrixOutputs_lo_hi_lo_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_221, decoder_decoded_andMatrixOutputs_andMatrixInput_11_215) node decoder_decoded_andMatrixOutputs_lo_hi_hi_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_267, decoder_decoded_andMatrixOutputs_andMatrixInput_9_227) node decoder_decoded_andMatrixOutputs_lo_hi_325 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_227, decoder_decoded_andMatrixOutputs_lo_hi_lo_204) node decoder_decoded_andMatrixOutputs_lo_327 = cat(decoder_decoded_andMatrixOutputs_lo_hi_325, decoder_decoded_andMatrixOutputs_lo_lo_305) node decoder_decoded_andMatrixOutputs_hi_lo_lo_180 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_319, decoder_decoded_andMatrixOutputs_andMatrixInput_7_305) node decoder_decoded_andMatrixOutputs_hi_lo_hi_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_327, decoder_decoded_andMatrixOutputs_andMatrixInput_5_325) node decoder_decoded_andMatrixOutputs_hi_lo_319 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_221, decoder_decoded_andMatrixOutputs_hi_lo_lo_180) node decoder_decoded_andMatrixOutputs_hi_hi_lo_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_327, decoder_decoded_andMatrixOutputs_andMatrixInput_3_327) node decoder_decoded_andMatrixOutputs_hi_hi_hi_267 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_327, decoder_decoded_andMatrixOutputs_andMatrixInput_1_327) node decoder_decoded_andMatrixOutputs_hi_hi_327 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_267, decoder_decoded_andMatrixOutputs_hi_hi_lo_208) node decoder_decoded_andMatrixOutputs_hi_327 = cat(decoder_decoded_andMatrixOutputs_hi_hi_327, decoder_decoded_andMatrixOutputs_hi_lo_319) node _decoder_decoded_andMatrixOutputs_T_327 = cat(decoder_decoded_andMatrixOutputs_hi_327, decoder_decoded_andMatrixOutputs_lo_327) node decoder_decoded_andMatrixOutputs_174_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_327) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_328 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_328 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_328 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_328 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_328 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_326 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_320 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_306 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_268 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_228 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_222 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_216 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_209 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_205 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_181 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_109 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_109 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_181, decoder_decoded_andMatrixOutputs_andMatrixInput_15_109) node decoder_decoded_andMatrixOutputs_lo_lo_hi_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_209, decoder_decoded_andMatrixOutputs_andMatrixInput_13_205) node decoder_decoded_andMatrixOutputs_lo_lo_306 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_216, decoder_decoded_andMatrixOutputs_lo_lo_lo_109) node decoder_decoded_andMatrixOutputs_lo_hi_lo_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_222, decoder_decoded_andMatrixOutputs_andMatrixInput_11_216) node decoder_decoded_andMatrixOutputs_lo_hi_hi_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_268, decoder_decoded_andMatrixOutputs_andMatrixInput_9_228) node decoder_decoded_andMatrixOutputs_lo_hi_326 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_228, decoder_decoded_andMatrixOutputs_lo_hi_lo_205) node decoder_decoded_andMatrixOutputs_lo_328 = cat(decoder_decoded_andMatrixOutputs_lo_hi_326, decoder_decoded_andMatrixOutputs_lo_lo_306) node decoder_decoded_andMatrixOutputs_hi_lo_lo_181 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_320, decoder_decoded_andMatrixOutputs_andMatrixInput_7_306) node decoder_decoded_andMatrixOutputs_hi_lo_hi_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_328, decoder_decoded_andMatrixOutputs_andMatrixInput_5_326) node decoder_decoded_andMatrixOutputs_hi_lo_320 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_222, decoder_decoded_andMatrixOutputs_hi_lo_lo_181) node decoder_decoded_andMatrixOutputs_hi_hi_lo_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_328, decoder_decoded_andMatrixOutputs_andMatrixInput_3_328) node decoder_decoded_andMatrixOutputs_hi_hi_hi_268 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_328, decoder_decoded_andMatrixOutputs_andMatrixInput_1_328) node decoder_decoded_andMatrixOutputs_hi_hi_328 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_268, decoder_decoded_andMatrixOutputs_hi_hi_lo_209) node decoder_decoded_andMatrixOutputs_hi_328 = cat(decoder_decoded_andMatrixOutputs_hi_hi_328, decoder_decoded_andMatrixOutputs_hi_lo_320) node _decoder_decoded_andMatrixOutputs_T_328 = cat(decoder_decoded_andMatrixOutputs_hi_328, decoder_decoded_andMatrixOutputs_lo_328) node decoder_decoded_andMatrixOutputs_120_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_328) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_329 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_329 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_329 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_329 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_329 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_327 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_321 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_307 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_269 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_229 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_223 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_217 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_210 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_206 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_182 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_110 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_110 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_182, decoder_decoded_andMatrixOutputs_andMatrixInput_15_110) node decoder_decoded_andMatrixOutputs_lo_lo_hi_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_210, decoder_decoded_andMatrixOutputs_andMatrixInput_13_206) node decoder_decoded_andMatrixOutputs_lo_lo_307 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_217, decoder_decoded_andMatrixOutputs_lo_lo_lo_110) node decoder_decoded_andMatrixOutputs_lo_hi_lo_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_223, decoder_decoded_andMatrixOutputs_andMatrixInput_11_217) node decoder_decoded_andMatrixOutputs_lo_hi_hi_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_269, decoder_decoded_andMatrixOutputs_andMatrixInput_9_229) node decoder_decoded_andMatrixOutputs_lo_hi_327 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_229, decoder_decoded_andMatrixOutputs_lo_hi_lo_206) node decoder_decoded_andMatrixOutputs_lo_329 = cat(decoder_decoded_andMatrixOutputs_lo_hi_327, decoder_decoded_andMatrixOutputs_lo_lo_307) node decoder_decoded_andMatrixOutputs_hi_lo_lo_182 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_321, decoder_decoded_andMatrixOutputs_andMatrixInput_7_307) node decoder_decoded_andMatrixOutputs_hi_lo_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_329, decoder_decoded_andMatrixOutputs_andMatrixInput_5_327) node decoder_decoded_andMatrixOutputs_hi_lo_321 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_223, decoder_decoded_andMatrixOutputs_hi_lo_lo_182) node decoder_decoded_andMatrixOutputs_hi_hi_lo_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_329, decoder_decoded_andMatrixOutputs_andMatrixInput_3_329) node decoder_decoded_andMatrixOutputs_hi_hi_hi_269 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_329, decoder_decoded_andMatrixOutputs_andMatrixInput_1_329) node decoder_decoded_andMatrixOutputs_hi_hi_329 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_269, decoder_decoded_andMatrixOutputs_hi_hi_lo_210) node decoder_decoded_andMatrixOutputs_hi_329 = cat(decoder_decoded_andMatrixOutputs_hi_hi_329, decoder_decoded_andMatrixOutputs_hi_lo_321) node _decoder_decoded_andMatrixOutputs_T_329 = cat(decoder_decoded_andMatrixOutputs_hi_329, decoder_decoded_andMatrixOutputs_lo_329) node decoder_decoded_andMatrixOutputs_19_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_329) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_330 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_330 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_330 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_330 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_330 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_328 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_322 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_308 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_270 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_230 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_224 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_218 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_211 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_207 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_183 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_211, decoder_decoded_andMatrixOutputs_andMatrixInput_13_207) node decoder_decoded_andMatrixOutputs_lo_lo_308 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_218, decoder_decoded_andMatrixOutputs_andMatrixInput_14_183) node decoder_decoded_andMatrixOutputs_lo_hi_lo_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_224, decoder_decoded_andMatrixOutputs_andMatrixInput_11_218) node decoder_decoded_andMatrixOutputs_lo_hi_hi_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_270, decoder_decoded_andMatrixOutputs_andMatrixInput_9_230) node decoder_decoded_andMatrixOutputs_lo_hi_328 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_230, decoder_decoded_andMatrixOutputs_lo_hi_lo_207) node decoder_decoded_andMatrixOutputs_lo_330 = cat(decoder_decoded_andMatrixOutputs_lo_hi_328, decoder_decoded_andMatrixOutputs_lo_lo_308) node decoder_decoded_andMatrixOutputs_hi_lo_lo_183 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_322, decoder_decoded_andMatrixOutputs_andMatrixInput_7_308) node decoder_decoded_andMatrixOutputs_hi_lo_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_330, decoder_decoded_andMatrixOutputs_andMatrixInput_5_328) node decoder_decoded_andMatrixOutputs_hi_lo_322 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_224, decoder_decoded_andMatrixOutputs_hi_lo_lo_183) node decoder_decoded_andMatrixOutputs_hi_hi_lo_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_330, decoder_decoded_andMatrixOutputs_andMatrixInput_3_330) node decoder_decoded_andMatrixOutputs_hi_hi_hi_270 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_330, decoder_decoded_andMatrixOutputs_andMatrixInput_1_330) node decoder_decoded_andMatrixOutputs_hi_hi_330 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_270, decoder_decoded_andMatrixOutputs_hi_hi_lo_211) node decoder_decoded_andMatrixOutputs_hi_330 = cat(decoder_decoded_andMatrixOutputs_hi_hi_330, decoder_decoded_andMatrixOutputs_hi_lo_322) node _decoder_decoded_andMatrixOutputs_T_330 = cat(decoder_decoded_andMatrixOutputs_hi_330, decoder_decoded_andMatrixOutputs_lo_330) node decoder_decoded_andMatrixOutputs_63_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_330) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_331 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_331 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_331 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_331 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_331 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_329 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_323 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_309 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_271 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_231 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_225 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_219 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_212 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_208 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_184 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_111 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_111 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_184, decoder_decoded_andMatrixOutputs_andMatrixInput_15_111) node decoder_decoded_andMatrixOutputs_lo_lo_hi_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_212, decoder_decoded_andMatrixOutputs_andMatrixInput_13_208) node decoder_decoded_andMatrixOutputs_lo_lo_309 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_219, decoder_decoded_andMatrixOutputs_lo_lo_lo_111) node decoder_decoded_andMatrixOutputs_lo_hi_lo_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_225, decoder_decoded_andMatrixOutputs_andMatrixInput_11_219) node decoder_decoded_andMatrixOutputs_lo_hi_hi_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_271, decoder_decoded_andMatrixOutputs_andMatrixInput_9_231) node decoder_decoded_andMatrixOutputs_lo_hi_329 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_231, decoder_decoded_andMatrixOutputs_lo_hi_lo_208) node decoder_decoded_andMatrixOutputs_lo_331 = cat(decoder_decoded_andMatrixOutputs_lo_hi_329, decoder_decoded_andMatrixOutputs_lo_lo_309) node decoder_decoded_andMatrixOutputs_hi_lo_lo_184 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_323, decoder_decoded_andMatrixOutputs_andMatrixInput_7_309) node decoder_decoded_andMatrixOutputs_hi_lo_hi_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_331, decoder_decoded_andMatrixOutputs_andMatrixInput_5_329) node decoder_decoded_andMatrixOutputs_hi_lo_323 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_225, decoder_decoded_andMatrixOutputs_hi_lo_lo_184) node decoder_decoded_andMatrixOutputs_hi_hi_lo_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_331, decoder_decoded_andMatrixOutputs_andMatrixInput_3_331) node decoder_decoded_andMatrixOutputs_hi_hi_hi_271 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_331, decoder_decoded_andMatrixOutputs_andMatrixInput_1_331) node decoder_decoded_andMatrixOutputs_hi_hi_331 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_271, decoder_decoded_andMatrixOutputs_hi_hi_lo_212) node decoder_decoded_andMatrixOutputs_hi_331 = cat(decoder_decoded_andMatrixOutputs_hi_hi_331, decoder_decoded_andMatrixOutputs_hi_lo_323) node _decoder_decoded_andMatrixOutputs_T_331 = cat(decoder_decoded_andMatrixOutputs_hi_331, decoder_decoded_andMatrixOutputs_lo_331) node decoder_decoded_andMatrixOutputs_142_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_331) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_332 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_332 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_332 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_332 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_332 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_330 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_324 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_310 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_272 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_232 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_226 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_220 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_213 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_209 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_185 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_112 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_112 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_185, decoder_decoded_andMatrixOutputs_andMatrixInput_15_112) node decoder_decoded_andMatrixOutputs_lo_lo_hi_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_213, decoder_decoded_andMatrixOutputs_andMatrixInput_13_209) node decoder_decoded_andMatrixOutputs_lo_lo_310 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_220, decoder_decoded_andMatrixOutputs_lo_lo_lo_112) node decoder_decoded_andMatrixOutputs_lo_hi_lo_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_226, decoder_decoded_andMatrixOutputs_andMatrixInput_11_220) node decoder_decoded_andMatrixOutputs_lo_hi_hi_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_272, decoder_decoded_andMatrixOutputs_andMatrixInput_9_232) node decoder_decoded_andMatrixOutputs_lo_hi_330 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_232, decoder_decoded_andMatrixOutputs_lo_hi_lo_209) node decoder_decoded_andMatrixOutputs_lo_332 = cat(decoder_decoded_andMatrixOutputs_lo_hi_330, decoder_decoded_andMatrixOutputs_lo_lo_310) node decoder_decoded_andMatrixOutputs_hi_lo_lo_185 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_324, decoder_decoded_andMatrixOutputs_andMatrixInput_7_310) node decoder_decoded_andMatrixOutputs_hi_lo_hi_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_332, decoder_decoded_andMatrixOutputs_andMatrixInput_5_330) node decoder_decoded_andMatrixOutputs_hi_lo_324 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_226, decoder_decoded_andMatrixOutputs_hi_lo_lo_185) node decoder_decoded_andMatrixOutputs_hi_hi_lo_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_332, decoder_decoded_andMatrixOutputs_andMatrixInput_3_332) node decoder_decoded_andMatrixOutputs_hi_hi_hi_272 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_332, decoder_decoded_andMatrixOutputs_andMatrixInput_1_332) node decoder_decoded_andMatrixOutputs_hi_hi_332 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_272, decoder_decoded_andMatrixOutputs_hi_hi_lo_213) node decoder_decoded_andMatrixOutputs_hi_332 = cat(decoder_decoded_andMatrixOutputs_hi_hi_332, decoder_decoded_andMatrixOutputs_hi_lo_324) node _decoder_decoded_andMatrixOutputs_T_332 = cat(decoder_decoded_andMatrixOutputs_hi_332, decoder_decoded_andMatrixOutputs_lo_332) node decoder_decoded_andMatrixOutputs_11_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_332) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_333 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_333 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_333 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_333 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_333 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_331 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_325 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_311 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_273 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_233 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_227 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_221 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_214 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_210 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_186 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_113 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_63 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_113 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_113, decoder_decoded_andMatrixOutputs_andMatrixInput_16_63) node decoder_decoded_andMatrixOutputs_lo_lo_hi_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_210, decoder_decoded_andMatrixOutputs_andMatrixInput_14_186) node decoder_decoded_andMatrixOutputs_lo_lo_311 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_221, decoder_decoded_andMatrixOutputs_lo_lo_lo_113) node decoder_decoded_andMatrixOutputs_lo_hi_lo_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_221, decoder_decoded_andMatrixOutputs_andMatrixInput_12_214) node decoder_decoded_andMatrixOutputs_lo_hi_hi_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_233, decoder_decoded_andMatrixOutputs_andMatrixInput_10_227) node decoder_decoded_andMatrixOutputs_lo_hi_331 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_233, decoder_decoded_andMatrixOutputs_lo_hi_lo_210) node decoder_decoded_andMatrixOutputs_lo_333 = cat(decoder_decoded_andMatrixOutputs_lo_hi_331, decoder_decoded_andMatrixOutputs_lo_lo_311) node decoder_decoded_andMatrixOutputs_hi_lo_lo_186 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_311, decoder_decoded_andMatrixOutputs_andMatrixInput_8_273) node decoder_decoded_andMatrixOutputs_hi_lo_hi_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_331, decoder_decoded_andMatrixOutputs_andMatrixInput_6_325) node decoder_decoded_andMatrixOutputs_hi_lo_325 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_227, decoder_decoded_andMatrixOutputs_hi_lo_lo_186) node decoder_decoded_andMatrixOutputs_hi_hi_lo_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_333, decoder_decoded_andMatrixOutputs_andMatrixInput_4_333) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_333, decoder_decoded_andMatrixOutputs_andMatrixInput_1_333) node decoder_decoded_andMatrixOutputs_hi_hi_hi_273 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_2_333) node decoder_decoded_andMatrixOutputs_hi_hi_333 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_273, decoder_decoded_andMatrixOutputs_hi_hi_lo_214) node decoder_decoded_andMatrixOutputs_hi_333 = cat(decoder_decoded_andMatrixOutputs_hi_hi_333, decoder_decoded_andMatrixOutputs_hi_lo_325) node _decoder_decoded_andMatrixOutputs_T_333 = cat(decoder_decoded_andMatrixOutputs_hi_333, decoder_decoded_andMatrixOutputs_lo_333) node decoder_decoded_andMatrixOutputs_47_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_333) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_334 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_334 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_334 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_334 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_334 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_332 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_326 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_312 = bits(decoder_decoded_plaInput_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_274 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_234 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_228 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_222 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_215 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_211 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_187 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_114 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_64 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_114 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_114, decoder_decoded_andMatrixOutputs_andMatrixInput_16_64) node decoder_decoded_andMatrixOutputs_lo_lo_hi_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_211, decoder_decoded_andMatrixOutputs_andMatrixInput_14_187) node decoder_decoded_andMatrixOutputs_lo_lo_312 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_222, decoder_decoded_andMatrixOutputs_lo_lo_lo_114) node decoder_decoded_andMatrixOutputs_lo_hi_lo_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_222, decoder_decoded_andMatrixOutputs_andMatrixInput_12_215) node decoder_decoded_andMatrixOutputs_lo_hi_hi_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_234, decoder_decoded_andMatrixOutputs_andMatrixInput_10_228) node decoder_decoded_andMatrixOutputs_lo_hi_332 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_234, decoder_decoded_andMatrixOutputs_lo_hi_lo_211) node decoder_decoded_andMatrixOutputs_lo_334 = cat(decoder_decoded_andMatrixOutputs_lo_hi_332, decoder_decoded_andMatrixOutputs_lo_lo_312) node decoder_decoded_andMatrixOutputs_hi_lo_lo_187 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_312, decoder_decoded_andMatrixOutputs_andMatrixInput_8_274) node decoder_decoded_andMatrixOutputs_hi_lo_hi_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_332, decoder_decoded_andMatrixOutputs_andMatrixInput_6_326) node decoder_decoded_andMatrixOutputs_hi_lo_326 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_228, decoder_decoded_andMatrixOutputs_hi_lo_lo_187) node decoder_decoded_andMatrixOutputs_hi_hi_lo_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_334, decoder_decoded_andMatrixOutputs_andMatrixInput_4_334) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_334, decoder_decoded_andMatrixOutputs_andMatrixInput_1_334) node decoder_decoded_andMatrixOutputs_hi_hi_hi_274 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_2_334) node decoder_decoded_andMatrixOutputs_hi_hi_334 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_274, decoder_decoded_andMatrixOutputs_hi_hi_lo_215) node decoder_decoded_andMatrixOutputs_hi_334 = cat(decoder_decoded_andMatrixOutputs_hi_hi_334, decoder_decoded_andMatrixOutputs_hi_lo_326) node _decoder_decoded_andMatrixOutputs_T_334 = cat(decoder_decoded_andMatrixOutputs_hi_334, decoder_decoded_andMatrixOutputs_lo_334) node decoder_decoded_andMatrixOutputs_141_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_334) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_335 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_335 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_335 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_335 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_335 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_333 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_327 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_313 = bits(decoder_decoded_plaInput_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_275 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_235 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_229 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_223 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_216 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_212 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_188 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_115 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_65 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_46 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_115 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_65, decoder_decoded_andMatrixOutputs_andMatrixInput_17_46) node decoder_decoded_andMatrixOutputs_lo_lo_hi_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_188, decoder_decoded_andMatrixOutputs_andMatrixInput_15_115) node decoder_decoded_andMatrixOutputs_lo_lo_313 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_223, decoder_decoded_andMatrixOutputs_lo_lo_lo_115) node decoder_decoded_andMatrixOutputs_lo_hi_lo_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_216, decoder_decoded_andMatrixOutputs_andMatrixInput_13_212) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_235, decoder_decoded_andMatrixOutputs_andMatrixInput_10_229) node decoder_decoded_andMatrixOutputs_lo_hi_hi_235 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_223) node decoder_decoded_andMatrixOutputs_lo_hi_333 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_235, decoder_decoded_andMatrixOutputs_lo_hi_lo_212) node decoder_decoded_andMatrixOutputs_lo_335 = cat(decoder_decoded_andMatrixOutputs_lo_hi_333, decoder_decoded_andMatrixOutputs_lo_lo_313) node decoder_decoded_andMatrixOutputs_hi_lo_lo_188 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_313, decoder_decoded_andMatrixOutputs_andMatrixInput_8_275) node decoder_decoded_andMatrixOutputs_hi_lo_hi_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_333, decoder_decoded_andMatrixOutputs_andMatrixInput_6_327) node decoder_decoded_andMatrixOutputs_hi_lo_327 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_229, decoder_decoded_andMatrixOutputs_hi_lo_lo_188) node decoder_decoded_andMatrixOutputs_hi_hi_lo_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_335, decoder_decoded_andMatrixOutputs_andMatrixInput_4_335) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_335, decoder_decoded_andMatrixOutputs_andMatrixInput_1_335) node decoder_decoded_andMatrixOutputs_hi_hi_hi_275 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_andMatrixInput_2_335) node decoder_decoded_andMatrixOutputs_hi_hi_335 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_275, decoder_decoded_andMatrixOutputs_hi_hi_lo_216) node decoder_decoded_andMatrixOutputs_hi_335 = cat(decoder_decoded_andMatrixOutputs_hi_hi_335, decoder_decoded_andMatrixOutputs_hi_lo_327) node _decoder_decoded_andMatrixOutputs_T_335 = cat(decoder_decoded_andMatrixOutputs_hi_335, decoder_decoded_andMatrixOutputs_lo_335) node decoder_decoded_andMatrixOutputs_114_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_335) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_336 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_336 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_336 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_336 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_336 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_334 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_328 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_314 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_276 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_236 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_230 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_224 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_217 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_213 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_189 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_116 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_66 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_116 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_116, decoder_decoded_andMatrixOutputs_andMatrixInput_16_66) node decoder_decoded_andMatrixOutputs_lo_lo_hi_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_213, decoder_decoded_andMatrixOutputs_andMatrixInput_14_189) node decoder_decoded_andMatrixOutputs_lo_lo_314 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_224, decoder_decoded_andMatrixOutputs_lo_lo_lo_116) node decoder_decoded_andMatrixOutputs_lo_hi_lo_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_224, decoder_decoded_andMatrixOutputs_andMatrixInput_12_217) node decoder_decoded_andMatrixOutputs_lo_hi_hi_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_236, decoder_decoded_andMatrixOutputs_andMatrixInput_10_230) node decoder_decoded_andMatrixOutputs_lo_hi_334 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_236, decoder_decoded_andMatrixOutputs_lo_hi_lo_213) node decoder_decoded_andMatrixOutputs_lo_336 = cat(decoder_decoded_andMatrixOutputs_lo_hi_334, decoder_decoded_andMatrixOutputs_lo_lo_314) node decoder_decoded_andMatrixOutputs_hi_lo_lo_189 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_314, decoder_decoded_andMatrixOutputs_andMatrixInput_8_276) node decoder_decoded_andMatrixOutputs_hi_lo_hi_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_334, decoder_decoded_andMatrixOutputs_andMatrixInput_6_328) node decoder_decoded_andMatrixOutputs_hi_lo_328 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_230, decoder_decoded_andMatrixOutputs_hi_lo_lo_189) node decoder_decoded_andMatrixOutputs_hi_hi_lo_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_336, decoder_decoded_andMatrixOutputs_andMatrixInput_4_336) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_336, decoder_decoded_andMatrixOutputs_andMatrixInput_1_336) node decoder_decoded_andMatrixOutputs_hi_hi_hi_276 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_andMatrixInput_2_336) node decoder_decoded_andMatrixOutputs_hi_hi_336 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_276, decoder_decoded_andMatrixOutputs_hi_hi_lo_217) node decoder_decoded_andMatrixOutputs_hi_336 = cat(decoder_decoded_andMatrixOutputs_hi_hi_336, decoder_decoded_andMatrixOutputs_hi_lo_328) node _decoder_decoded_andMatrixOutputs_T_336 = cat(decoder_decoded_andMatrixOutputs_hi_336, decoder_decoded_andMatrixOutputs_lo_336) node decoder_decoded_andMatrixOutputs_69_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_336) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_337 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_337 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_337 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_337 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_337 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_335 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_329 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_315 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_277 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_237 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_231 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_225 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_218 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_214 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_190 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_117 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_67 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_47 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_117 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_67, decoder_decoded_andMatrixOutputs_andMatrixInput_17_47) node decoder_decoded_andMatrixOutputs_lo_lo_hi_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_190, decoder_decoded_andMatrixOutputs_andMatrixInput_15_117) node decoder_decoded_andMatrixOutputs_lo_lo_315 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_225, decoder_decoded_andMatrixOutputs_lo_lo_lo_117) node decoder_decoded_andMatrixOutputs_lo_hi_lo_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_218, decoder_decoded_andMatrixOutputs_andMatrixInput_13_214) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_237, decoder_decoded_andMatrixOutputs_andMatrixInput_10_231) node decoder_decoded_andMatrixOutputs_lo_hi_hi_237 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_225) node decoder_decoded_andMatrixOutputs_lo_hi_335 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_237, decoder_decoded_andMatrixOutputs_lo_hi_lo_214) node decoder_decoded_andMatrixOutputs_lo_337 = cat(decoder_decoded_andMatrixOutputs_lo_hi_335, decoder_decoded_andMatrixOutputs_lo_lo_315) node decoder_decoded_andMatrixOutputs_hi_lo_lo_190 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_315, decoder_decoded_andMatrixOutputs_andMatrixInput_8_277) node decoder_decoded_andMatrixOutputs_hi_lo_hi_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_335, decoder_decoded_andMatrixOutputs_andMatrixInput_6_329) node decoder_decoded_andMatrixOutputs_hi_lo_329 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_231, decoder_decoded_andMatrixOutputs_hi_lo_lo_190) node decoder_decoded_andMatrixOutputs_hi_hi_lo_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_337, decoder_decoded_andMatrixOutputs_andMatrixInput_4_337) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_337, decoder_decoded_andMatrixOutputs_andMatrixInput_1_337) node decoder_decoded_andMatrixOutputs_hi_hi_hi_277 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_andMatrixInput_2_337) node decoder_decoded_andMatrixOutputs_hi_hi_337 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_277, decoder_decoded_andMatrixOutputs_hi_hi_lo_218) node decoder_decoded_andMatrixOutputs_hi_337 = cat(decoder_decoded_andMatrixOutputs_hi_hi_337, decoder_decoded_andMatrixOutputs_hi_lo_329) node _decoder_decoded_andMatrixOutputs_T_337 = cat(decoder_decoded_andMatrixOutputs_hi_337, decoder_decoded_andMatrixOutputs_lo_337) node decoder_decoded_andMatrixOutputs_71_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_337) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_338 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_338 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_338 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_338 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_338 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_336 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_330 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_316 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_278 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_238 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_232 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_226 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_219 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_215 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_191 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_118 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_68 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_118 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_118, decoder_decoded_andMatrixOutputs_andMatrixInput_16_68) node decoder_decoded_andMatrixOutputs_lo_lo_hi_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_215, decoder_decoded_andMatrixOutputs_andMatrixInput_14_191) node decoder_decoded_andMatrixOutputs_lo_lo_316 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_226, decoder_decoded_andMatrixOutputs_lo_lo_lo_118) node decoder_decoded_andMatrixOutputs_lo_hi_lo_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_226, decoder_decoded_andMatrixOutputs_andMatrixInput_12_219) node decoder_decoded_andMatrixOutputs_lo_hi_hi_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_238, decoder_decoded_andMatrixOutputs_andMatrixInput_10_232) node decoder_decoded_andMatrixOutputs_lo_hi_336 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_238, decoder_decoded_andMatrixOutputs_lo_hi_lo_215) node decoder_decoded_andMatrixOutputs_lo_338 = cat(decoder_decoded_andMatrixOutputs_lo_hi_336, decoder_decoded_andMatrixOutputs_lo_lo_316) node decoder_decoded_andMatrixOutputs_hi_lo_lo_191 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_316, decoder_decoded_andMatrixOutputs_andMatrixInput_8_278) node decoder_decoded_andMatrixOutputs_hi_lo_hi_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_336, decoder_decoded_andMatrixOutputs_andMatrixInput_6_330) node decoder_decoded_andMatrixOutputs_hi_lo_330 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_232, decoder_decoded_andMatrixOutputs_hi_lo_lo_191) node decoder_decoded_andMatrixOutputs_hi_hi_lo_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_338, decoder_decoded_andMatrixOutputs_andMatrixInput_4_338) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_338, decoder_decoded_andMatrixOutputs_andMatrixInput_1_338) node decoder_decoded_andMatrixOutputs_hi_hi_hi_278 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_andMatrixInput_2_338) node decoder_decoded_andMatrixOutputs_hi_hi_338 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_278, decoder_decoded_andMatrixOutputs_hi_hi_lo_219) node decoder_decoded_andMatrixOutputs_hi_338 = cat(decoder_decoded_andMatrixOutputs_hi_hi_338, decoder_decoded_andMatrixOutputs_hi_lo_330) node _decoder_decoded_andMatrixOutputs_T_338 = cat(decoder_decoded_andMatrixOutputs_hi_338, decoder_decoded_andMatrixOutputs_lo_338) node decoder_decoded_andMatrixOutputs_175_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_338) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_339 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_339 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_339 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_339 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_339 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_337 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_331 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_317 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_279 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_239 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_233 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_227 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_220 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_216 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_192 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_119 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_69 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_48 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_119 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_69, decoder_decoded_andMatrixOutputs_andMatrixInput_17_48) node decoder_decoded_andMatrixOutputs_lo_lo_hi_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_192, decoder_decoded_andMatrixOutputs_andMatrixInput_15_119) node decoder_decoded_andMatrixOutputs_lo_lo_317 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_227, decoder_decoded_andMatrixOutputs_lo_lo_lo_119) node decoder_decoded_andMatrixOutputs_lo_hi_lo_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_220, decoder_decoded_andMatrixOutputs_andMatrixInput_13_216) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_239, decoder_decoded_andMatrixOutputs_andMatrixInput_10_233) node decoder_decoded_andMatrixOutputs_lo_hi_hi_239 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_227) node decoder_decoded_andMatrixOutputs_lo_hi_337 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_239, decoder_decoded_andMatrixOutputs_lo_hi_lo_216) node decoder_decoded_andMatrixOutputs_lo_339 = cat(decoder_decoded_andMatrixOutputs_lo_hi_337, decoder_decoded_andMatrixOutputs_lo_lo_317) node decoder_decoded_andMatrixOutputs_hi_lo_lo_192 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_317, decoder_decoded_andMatrixOutputs_andMatrixInput_8_279) node decoder_decoded_andMatrixOutputs_hi_lo_hi_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_337, decoder_decoded_andMatrixOutputs_andMatrixInput_6_331) node decoder_decoded_andMatrixOutputs_hi_lo_331 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_233, decoder_decoded_andMatrixOutputs_hi_lo_lo_192) node decoder_decoded_andMatrixOutputs_hi_hi_lo_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_339, decoder_decoded_andMatrixOutputs_andMatrixInput_4_339) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_339, decoder_decoded_andMatrixOutputs_andMatrixInput_1_339) node decoder_decoded_andMatrixOutputs_hi_hi_hi_279 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_andMatrixInput_2_339) node decoder_decoded_andMatrixOutputs_hi_hi_339 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_279, decoder_decoded_andMatrixOutputs_hi_hi_lo_220) node decoder_decoded_andMatrixOutputs_hi_339 = cat(decoder_decoded_andMatrixOutputs_hi_hi_339, decoder_decoded_andMatrixOutputs_hi_lo_331) node _decoder_decoded_andMatrixOutputs_T_339 = cat(decoder_decoded_andMatrixOutputs_hi_339, decoder_decoded_andMatrixOutputs_lo_339) node decoder_decoded_andMatrixOutputs_80_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_339) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_340 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_340 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_340 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_340 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_340 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_338 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_332 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_318 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_280 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_240 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_234 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_228 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_221 = bits(decoder_decoded_plaInput_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_217 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_193 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_120 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_70 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_120 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_120, decoder_decoded_andMatrixOutputs_andMatrixInput_16_70) node decoder_decoded_andMatrixOutputs_lo_lo_hi_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_217, decoder_decoded_andMatrixOutputs_andMatrixInput_14_193) node decoder_decoded_andMatrixOutputs_lo_lo_318 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_228, decoder_decoded_andMatrixOutputs_lo_lo_lo_120) node decoder_decoded_andMatrixOutputs_lo_hi_lo_217 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_228, decoder_decoded_andMatrixOutputs_andMatrixInput_12_221) node decoder_decoded_andMatrixOutputs_lo_hi_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_240, decoder_decoded_andMatrixOutputs_andMatrixInput_10_234) node decoder_decoded_andMatrixOutputs_lo_hi_338 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_240, decoder_decoded_andMatrixOutputs_lo_hi_lo_217) node decoder_decoded_andMatrixOutputs_lo_340 = cat(decoder_decoded_andMatrixOutputs_lo_hi_338, decoder_decoded_andMatrixOutputs_lo_lo_318) node decoder_decoded_andMatrixOutputs_hi_lo_lo_193 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_318, decoder_decoded_andMatrixOutputs_andMatrixInput_8_280) node decoder_decoded_andMatrixOutputs_hi_lo_hi_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_338, decoder_decoded_andMatrixOutputs_andMatrixInput_6_332) node decoder_decoded_andMatrixOutputs_hi_lo_332 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_234, decoder_decoded_andMatrixOutputs_hi_lo_lo_193) node decoder_decoded_andMatrixOutputs_hi_hi_lo_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_340, decoder_decoded_andMatrixOutputs_andMatrixInput_4_340) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_340, decoder_decoded_andMatrixOutputs_andMatrixInput_1_340) node decoder_decoded_andMatrixOutputs_hi_hi_hi_280 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_andMatrixInput_2_340) node decoder_decoded_andMatrixOutputs_hi_hi_340 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_280, decoder_decoded_andMatrixOutputs_hi_hi_lo_221) node decoder_decoded_andMatrixOutputs_hi_340 = cat(decoder_decoded_andMatrixOutputs_hi_hi_340, decoder_decoded_andMatrixOutputs_hi_lo_332) node _decoder_decoded_andMatrixOutputs_T_340 = cat(decoder_decoded_andMatrixOutputs_hi_340, decoder_decoded_andMatrixOutputs_lo_340) node decoder_decoded_andMatrixOutputs_130_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_340) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_341 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_341 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_341 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_341 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_341 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_339 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_333 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_319 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_281 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_241 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_235 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_229 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_222 = bits(decoder_decoded_plaInput_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_218 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_194 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_121 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_71 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_49 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_121 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_71, decoder_decoded_andMatrixOutputs_andMatrixInput_17_49) node decoder_decoded_andMatrixOutputs_lo_lo_hi_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_194, decoder_decoded_andMatrixOutputs_andMatrixInput_15_121) node decoder_decoded_andMatrixOutputs_lo_lo_319 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_229, decoder_decoded_andMatrixOutputs_lo_lo_lo_121) node decoder_decoded_andMatrixOutputs_lo_hi_lo_218 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_222, decoder_decoded_andMatrixOutputs_andMatrixInput_13_218) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_241, decoder_decoded_andMatrixOutputs_andMatrixInput_10_235) node decoder_decoded_andMatrixOutputs_lo_hi_hi_241 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_229) node decoder_decoded_andMatrixOutputs_lo_hi_339 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_241, decoder_decoded_andMatrixOutputs_lo_hi_lo_218) node decoder_decoded_andMatrixOutputs_lo_341 = cat(decoder_decoded_andMatrixOutputs_lo_hi_339, decoder_decoded_andMatrixOutputs_lo_lo_319) node decoder_decoded_andMatrixOutputs_hi_lo_lo_194 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_319, decoder_decoded_andMatrixOutputs_andMatrixInput_8_281) node decoder_decoded_andMatrixOutputs_hi_lo_hi_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_339, decoder_decoded_andMatrixOutputs_andMatrixInput_6_333) node decoder_decoded_andMatrixOutputs_hi_lo_333 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_235, decoder_decoded_andMatrixOutputs_hi_lo_lo_194) node decoder_decoded_andMatrixOutputs_hi_hi_lo_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_341, decoder_decoded_andMatrixOutputs_andMatrixInput_4_341) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_341, decoder_decoded_andMatrixOutputs_andMatrixInput_1_341) node decoder_decoded_andMatrixOutputs_hi_hi_hi_281 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_andMatrixInput_2_341) node decoder_decoded_andMatrixOutputs_hi_hi_341 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_281, decoder_decoded_andMatrixOutputs_hi_hi_lo_222) node decoder_decoded_andMatrixOutputs_hi_341 = cat(decoder_decoded_andMatrixOutputs_hi_hi_341, decoder_decoded_andMatrixOutputs_hi_lo_333) node _decoder_decoded_andMatrixOutputs_T_341 = cat(decoder_decoded_andMatrixOutputs_hi_341, decoder_decoded_andMatrixOutputs_lo_341) node decoder_decoded_andMatrixOutputs_157_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_341) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_342 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_342 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_342 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_342 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_342 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_340 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_334 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_320 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_282 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_242 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_236 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_230 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_223 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_219 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_195 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_223, decoder_decoded_andMatrixOutputs_andMatrixInput_13_219) node decoder_decoded_andMatrixOutputs_lo_lo_320 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_230, decoder_decoded_andMatrixOutputs_andMatrixInput_14_195) node decoder_decoded_andMatrixOutputs_lo_hi_lo_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_236, decoder_decoded_andMatrixOutputs_andMatrixInput_11_230) node decoder_decoded_andMatrixOutputs_lo_hi_hi_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_282, decoder_decoded_andMatrixOutputs_andMatrixInput_9_242) node decoder_decoded_andMatrixOutputs_lo_hi_340 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_242, decoder_decoded_andMatrixOutputs_lo_hi_lo_219) node decoder_decoded_andMatrixOutputs_lo_342 = cat(decoder_decoded_andMatrixOutputs_lo_hi_340, decoder_decoded_andMatrixOutputs_lo_lo_320) node decoder_decoded_andMatrixOutputs_hi_lo_lo_195 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_334, decoder_decoded_andMatrixOutputs_andMatrixInput_7_320) node decoder_decoded_andMatrixOutputs_hi_lo_hi_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_342, decoder_decoded_andMatrixOutputs_andMatrixInput_5_340) node decoder_decoded_andMatrixOutputs_hi_lo_334 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_236, decoder_decoded_andMatrixOutputs_hi_lo_lo_195) node decoder_decoded_andMatrixOutputs_hi_hi_lo_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_342, decoder_decoded_andMatrixOutputs_andMatrixInput_3_342) node decoder_decoded_andMatrixOutputs_hi_hi_hi_282 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_342, decoder_decoded_andMatrixOutputs_andMatrixInput_1_342) node decoder_decoded_andMatrixOutputs_hi_hi_342 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_282, decoder_decoded_andMatrixOutputs_hi_hi_lo_223) node decoder_decoded_andMatrixOutputs_hi_342 = cat(decoder_decoded_andMatrixOutputs_hi_hi_342, decoder_decoded_andMatrixOutputs_hi_lo_334) node _decoder_decoded_andMatrixOutputs_T_342 = cat(decoder_decoded_andMatrixOutputs_hi_342, decoder_decoded_andMatrixOutputs_lo_342) node decoder_decoded_andMatrixOutputs_67_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_342) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_343 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_343 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_343 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_343 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_343 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_341 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_335 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_321 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_283 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_243 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_237 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_231 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_224 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_220 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_196 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_224, decoder_decoded_andMatrixOutputs_andMatrixInput_13_220) node decoder_decoded_andMatrixOutputs_lo_lo_321 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_231, decoder_decoded_andMatrixOutputs_andMatrixInput_14_196) node decoder_decoded_andMatrixOutputs_lo_hi_lo_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_237, decoder_decoded_andMatrixOutputs_andMatrixInput_11_231) node decoder_decoded_andMatrixOutputs_lo_hi_hi_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_283, decoder_decoded_andMatrixOutputs_andMatrixInput_9_243) node decoder_decoded_andMatrixOutputs_lo_hi_341 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_243, decoder_decoded_andMatrixOutputs_lo_hi_lo_220) node decoder_decoded_andMatrixOutputs_lo_343 = cat(decoder_decoded_andMatrixOutputs_lo_hi_341, decoder_decoded_andMatrixOutputs_lo_lo_321) node decoder_decoded_andMatrixOutputs_hi_lo_lo_196 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_335, decoder_decoded_andMatrixOutputs_andMatrixInput_7_321) node decoder_decoded_andMatrixOutputs_hi_lo_hi_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_343, decoder_decoded_andMatrixOutputs_andMatrixInput_5_341) node decoder_decoded_andMatrixOutputs_hi_lo_335 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_237, decoder_decoded_andMatrixOutputs_hi_lo_lo_196) node decoder_decoded_andMatrixOutputs_hi_hi_lo_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_343, decoder_decoded_andMatrixOutputs_andMatrixInput_3_343) node decoder_decoded_andMatrixOutputs_hi_hi_hi_283 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_343, decoder_decoded_andMatrixOutputs_andMatrixInput_1_343) node decoder_decoded_andMatrixOutputs_hi_hi_343 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_283, decoder_decoded_andMatrixOutputs_hi_hi_lo_224) node decoder_decoded_andMatrixOutputs_hi_343 = cat(decoder_decoded_andMatrixOutputs_hi_hi_343, decoder_decoded_andMatrixOutputs_hi_lo_335) node _decoder_decoded_andMatrixOutputs_T_343 = cat(decoder_decoded_andMatrixOutputs_hi_343, decoder_decoded_andMatrixOutputs_lo_343) node decoder_decoded_andMatrixOutputs_42_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_343) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_344 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_344 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_344 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_344 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_344 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_342 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_336 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_322 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_284 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_244 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_238 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_232 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_225 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_221 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_197 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_122 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_122 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_197, decoder_decoded_andMatrixOutputs_andMatrixInput_15_122) node decoder_decoded_andMatrixOutputs_lo_lo_hi_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_225, decoder_decoded_andMatrixOutputs_andMatrixInput_13_221) node decoder_decoded_andMatrixOutputs_lo_lo_322 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_232, decoder_decoded_andMatrixOutputs_lo_lo_lo_122) node decoder_decoded_andMatrixOutputs_lo_hi_lo_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_238, decoder_decoded_andMatrixOutputs_andMatrixInput_11_232) node decoder_decoded_andMatrixOutputs_lo_hi_hi_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_284, decoder_decoded_andMatrixOutputs_andMatrixInput_9_244) node decoder_decoded_andMatrixOutputs_lo_hi_342 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_244, decoder_decoded_andMatrixOutputs_lo_hi_lo_221) node decoder_decoded_andMatrixOutputs_lo_344 = cat(decoder_decoded_andMatrixOutputs_lo_hi_342, decoder_decoded_andMatrixOutputs_lo_lo_322) node decoder_decoded_andMatrixOutputs_hi_lo_lo_197 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_336, decoder_decoded_andMatrixOutputs_andMatrixInput_7_322) node decoder_decoded_andMatrixOutputs_hi_lo_hi_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_344, decoder_decoded_andMatrixOutputs_andMatrixInput_5_342) node decoder_decoded_andMatrixOutputs_hi_lo_336 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_238, decoder_decoded_andMatrixOutputs_hi_lo_lo_197) node decoder_decoded_andMatrixOutputs_hi_hi_lo_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_344, decoder_decoded_andMatrixOutputs_andMatrixInput_3_344) node decoder_decoded_andMatrixOutputs_hi_hi_hi_284 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_344, decoder_decoded_andMatrixOutputs_andMatrixInput_1_344) node decoder_decoded_andMatrixOutputs_hi_hi_344 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_284, decoder_decoded_andMatrixOutputs_hi_hi_lo_225) node decoder_decoded_andMatrixOutputs_hi_344 = cat(decoder_decoded_andMatrixOutputs_hi_hi_344, decoder_decoded_andMatrixOutputs_hi_lo_336) node _decoder_decoded_andMatrixOutputs_T_344 = cat(decoder_decoded_andMatrixOutputs_hi_344, decoder_decoded_andMatrixOutputs_lo_344) node decoder_decoded_andMatrixOutputs_53_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_344) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_345 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_345 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_345 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_345 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_345 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_343 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_337 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_323 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_285 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_245 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_239 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_233 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_226 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_222 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_198 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_123 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_123 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_198, decoder_decoded_andMatrixOutputs_andMatrixInput_15_123) node decoder_decoded_andMatrixOutputs_lo_lo_hi_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_226, decoder_decoded_andMatrixOutputs_andMatrixInput_13_222) node decoder_decoded_andMatrixOutputs_lo_lo_323 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_233, decoder_decoded_andMatrixOutputs_lo_lo_lo_123) node decoder_decoded_andMatrixOutputs_lo_hi_lo_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_239, decoder_decoded_andMatrixOutputs_andMatrixInput_11_233) node decoder_decoded_andMatrixOutputs_lo_hi_hi_245 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_285, decoder_decoded_andMatrixOutputs_andMatrixInput_9_245) node decoder_decoded_andMatrixOutputs_lo_hi_343 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_245, decoder_decoded_andMatrixOutputs_lo_hi_lo_222) node decoder_decoded_andMatrixOutputs_lo_345 = cat(decoder_decoded_andMatrixOutputs_lo_hi_343, decoder_decoded_andMatrixOutputs_lo_lo_323) node decoder_decoded_andMatrixOutputs_hi_lo_lo_198 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_337, decoder_decoded_andMatrixOutputs_andMatrixInput_7_323) node decoder_decoded_andMatrixOutputs_hi_lo_hi_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_345, decoder_decoded_andMatrixOutputs_andMatrixInput_5_343) node decoder_decoded_andMatrixOutputs_hi_lo_337 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_239, decoder_decoded_andMatrixOutputs_hi_lo_lo_198) node decoder_decoded_andMatrixOutputs_hi_hi_lo_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_345, decoder_decoded_andMatrixOutputs_andMatrixInput_3_345) node decoder_decoded_andMatrixOutputs_hi_hi_hi_285 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_345, decoder_decoded_andMatrixOutputs_andMatrixInput_1_345) node decoder_decoded_andMatrixOutputs_hi_hi_345 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_285, decoder_decoded_andMatrixOutputs_hi_hi_lo_226) node decoder_decoded_andMatrixOutputs_hi_345 = cat(decoder_decoded_andMatrixOutputs_hi_hi_345, decoder_decoded_andMatrixOutputs_hi_lo_337) node _decoder_decoded_andMatrixOutputs_T_345 = cat(decoder_decoded_andMatrixOutputs_hi_345, decoder_decoded_andMatrixOutputs_lo_345) node decoder_decoded_andMatrixOutputs_62_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_345) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_346 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_346 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_346 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_346 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_346 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_344 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_338 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_324 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_286 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_246 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_240 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_234 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_227 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_223 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_199 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_124 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_124 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_199, decoder_decoded_andMatrixOutputs_andMatrixInput_15_124) node decoder_decoded_andMatrixOutputs_lo_lo_hi_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_227, decoder_decoded_andMatrixOutputs_andMatrixInput_13_223) node decoder_decoded_andMatrixOutputs_lo_lo_324 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_234, decoder_decoded_andMatrixOutputs_lo_lo_lo_124) node decoder_decoded_andMatrixOutputs_lo_hi_lo_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_240, decoder_decoded_andMatrixOutputs_andMatrixInput_11_234) node decoder_decoded_andMatrixOutputs_lo_hi_hi_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_286, decoder_decoded_andMatrixOutputs_andMatrixInput_9_246) node decoder_decoded_andMatrixOutputs_lo_hi_344 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_246, decoder_decoded_andMatrixOutputs_lo_hi_lo_223) node decoder_decoded_andMatrixOutputs_lo_346 = cat(decoder_decoded_andMatrixOutputs_lo_hi_344, decoder_decoded_andMatrixOutputs_lo_lo_324) node decoder_decoded_andMatrixOutputs_hi_lo_lo_199 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_338, decoder_decoded_andMatrixOutputs_andMatrixInput_7_324) node decoder_decoded_andMatrixOutputs_hi_lo_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_346, decoder_decoded_andMatrixOutputs_andMatrixInput_5_344) node decoder_decoded_andMatrixOutputs_hi_lo_338 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_240, decoder_decoded_andMatrixOutputs_hi_lo_lo_199) node decoder_decoded_andMatrixOutputs_hi_hi_lo_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_346, decoder_decoded_andMatrixOutputs_andMatrixInput_3_346) node decoder_decoded_andMatrixOutputs_hi_hi_hi_286 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_346, decoder_decoded_andMatrixOutputs_andMatrixInput_1_346) node decoder_decoded_andMatrixOutputs_hi_hi_346 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_286, decoder_decoded_andMatrixOutputs_hi_hi_lo_227) node decoder_decoded_andMatrixOutputs_hi_346 = cat(decoder_decoded_andMatrixOutputs_hi_hi_346, decoder_decoded_andMatrixOutputs_hi_lo_338) node _decoder_decoded_andMatrixOutputs_T_346 = cat(decoder_decoded_andMatrixOutputs_hi_346, decoder_decoded_andMatrixOutputs_lo_346) node decoder_decoded_andMatrixOutputs_68_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_346) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_347 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_347 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_347 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_347 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_347 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_345 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_339 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_325 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_287 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_247 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_241 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_235 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_228 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_224 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_200 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_125 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_72 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_125 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_125, decoder_decoded_andMatrixOutputs_andMatrixInput_16_72) node decoder_decoded_andMatrixOutputs_lo_lo_hi_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_224, decoder_decoded_andMatrixOutputs_andMatrixInput_14_200) node decoder_decoded_andMatrixOutputs_lo_lo_325 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_235, decoder_decoded_andMatrixOutputs_lo_lo_lo_125) node decoder_decoded_andMatrixOutputs_lo_hi_lo_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_235, decoder_decoded_andMatrixOutputs_andMatrixInput_12_228) node decoder_decoded_andMatrixOutputs_lo_hi_hi_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_247, decoder_decoded_andMatrixOutputs_andMatrixInput_10_241) node decoder_decoded_andMatrixOutputs_lo_hi_345 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_247, decoder_decoded_andMatrixOutputs_lo_hi_lo_224) node decoder_decoded_andMatrixOutputs_lo_347 = cat(decoder_decoded_andMatrixOutputs_lo_hi_345, decoder_decoded_andMatrixOutputs_lo_lo_325) node decoder_decoded_andMatrixOutputs_hi_lo_lo_200 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_325, decoder_decoded_andMatrixOutputs_andMatrixInput_8_287) node decoder_decoded_andMatrixOutputs_hi_lo_hi_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_345, decoder_decoded_andMatrixOutputs_andMatrixInput_6_339) node decoder_decoded_andMatrixOutputs_hi_lo_339 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_241, decoder_decoded_andMatrixOutputs_hi_lo_lo_200) node decoder_decoded_andMatrixOutputs_hi_hi_lo_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_347, decoder_decoded_andMatrixOutputs_andMatrixInput_4_347) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_72 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_347, decoder_decoded_andMatrixOutputs_andMatrixInput_1_347) node decoder_decoded_andMatrixOutputs_hi_hi_hi_287 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_72, decoder_decoded_andMatrixOutputs_andMatrixInput_2_347) node decoder_decoded_andMatrixOutputs_hi_hi_347 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_287, decoder_decoded_andMatrixOutputs_hi_hi_lo_228) node decoder_decoded_andMatrixOutputs_hi_347 = cat(decoder_decoded_andMatrixOutputs_hi_hi_347, decoder_decoded_andMatrixOutputs_hi_lo_339) node _decoder_decoded_andMatrixOutputs_T_347 = cat(decoder_decoded_andMatrixOutputs_hi_347, decoder_decoded_andMatrixOutputs_lo_347) node decoder_decoded_andMatrixOutputs_183_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_347) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_348 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_348 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_348 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_348 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_348 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_346 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_340 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_326 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_288 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_248 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_242 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_236 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_229 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_225 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_201 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_126 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_73 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_50 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_126 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_73, decoder_decoded_andMatrixOutputs_andMatrixInput_17_50) node decoder_decoded_andMatrixOutputs_lo_lo_hi_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_201, decoder_decoded_andMatrixOutputs_andMatrixInput_15_126) node decoder_decoded_andMatrixOutputs_lo_lo_326 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_236, decoder_decoded_andMatrixOutputs_lo_lo_lo_126) node decoder_decoded_andMatrixOutputs_lo_hi_lo_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_229, decoder_decoded_andMatrixOutputs_andMatrixInput_13_225) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_248, decoder_decoded_andMatrixOutputs_andMatrixInput_10_242) node decoder_decoded_andMatrixOutputs_lo_hi_hi_248 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_236) node decoder_decoded_andMatrixOutputs_lo_hi_346 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_248, decoder_decoded_andMatrixOutputs_lo_hi_lo_225) node decoder_decoded_andMatrixOutputs_lo_348 = cat(decoder_decoded_andMatrixOutputs_lo_hi_346, decoder_decoded_andMatrixOutputs_lo_lo_326) node decoder_decoded_andMatrixOutputs_hi_lo_lo_201 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_326, decoder_decoded_andMatrixOutputs_andMatrixInput_8_288) node decoder_decoded_andMatrixOutputs_hi_lo_hi_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_346, decoder_decoded_andMatrixOutputs_andMatrixInput_6_340) node decoder_decoded_andMatrixOutputs_hi_lo_340 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_242, decoder_decoded_andMatrixOutputs_hi_lo_lo_201) node decoder_decoded_andMatrixOutputs_hi_hi_lo_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_348, decoder_decoded_andMatrixOutputs_andMatrixInput_4_348) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_73 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_348, decoder_decoded_andMatrixOutputs_andMatrixInput_1_348) node decoder_decoded_andMatrixOutputs_hi_hi_hi_288 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_73, decoder_decoded_andMatrixOutputs_andMatrixInput_2_348) node decoder_decoded_andMatrixOutputs_hi_hi_348 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_288, decoder_decoded_andMatrixOutputs_hi_hi_lo_229) node decoder_decoded_andMatrixOutputs_hi_348 = cat(decoder_decoded_andMatrixOutputs_hi_hi_348, decoder_decoded_andMatrixOutputs_hi_lo_340) node _decoder_decoded_andMatrixOutputs_T_348 = cat(decoder_decoded_andMatrixOutputs_hi_348, decoder_decoded_andMatrixOutputs_lo_348) node decoder_decoded_andMatrixOutputs_50_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_348) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_349 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_349 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_349 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_349 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_349 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_347 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_341 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_327 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_289 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_249 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_243 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_237 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_230 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_226 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_202 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_127 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_74 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_51 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_127 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_74, decoder_decoded_andMatrixOutputs_andMatrixInput_17_51) node decoder_decoded_andMatrixOutputs_lo_lo_hi_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_202, decoder_decoded_andMatrixOutputs_andMatrixInput_15_127) node decoder_decoded_andMatrixOutputs_lo_lo_327 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_237, decoder_decoded_andMatrixOutputs_lo_lo_lo_127) node decoder_decoded_andMatrixOutputs_lo_hi_lo_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_230, decoder_decoded_andMatrixOutputs_andMatrixInput_13_226) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_249, decoder_decoded_andMatrixOutputs_andMatrixInput_10_243) node decoder_decoded_andMatrixOutputs_lo_hi_hi_249 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_237) node decoder_decoded_andMatrixOutputs_lo_hi_347 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_249, decoder_decoded_andMatrixOutputs_lo_hi_lo_226) node decoder_decoded_andMatrixOutputs_lo_349 = cat(decoder_decoded_andMatrixOutputs_lo_hi_347, decoder_decoded_andMatrixOutputs_lo_lo_327) node decoder_decoded_andMatrixOutputs_hi_lo_lo_202 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_327, decoder_decoded_andMatrixOutputs_andMatrixInput_8_289) node decoder_decoded_andMatrixOutputs_hi_lo_hi_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_347, decoder_decoded_andMatrixOutputs_andMatrixInput_6_341) node decoder_decoded_andMatrixOutputs_hi_lo_341 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_243, decoder_decoded_andMatrixOutputs_hi_lo_lo_202) node decoder_decoded_andMatrixOutputs_hi_hi_lo_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_349, decoder_decoded_andMatrixOutputs_andMatrixInput_4_349) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_74 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_349, decoder_decoded_andMatrixOutputs_andMatrixInput_1_349) node decoder_decoded_andMatrixOutputs_hi_hi_hi_289 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_2_349) node decoder_decoded_andMatrixOutputs_hi_hi_349 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_289, decoder_decoded_andMatrixOutputs_hi_hi_lo_230) node decoder_decoded_andMatrixOutputs_hi_349 = cat(decoder_decoded_andMatrixOutputs_hi_hi_349, decoder_decoded_andMatrixOutputs_hi_lo_341) node _decoder_decoded_andMatrixOutputs_T_349 = cat(decoder_decoded_andMatrixOutputs_hi_349, decoder_decoded_andMatrixOutputs_lo_349) node decoder_decoded_andMatrixOutputs_136_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_349) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_350 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_350 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_350 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_350 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_350 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_348 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_342 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_328 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_290 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_250 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_244 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_238 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_231 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_227 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_203 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_128 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_75 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_52 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_38 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_128 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_52, decoder_decoded_andMatrixOutputs_andMatrixInput_18_38) node decoder_decoded_andMatrixOutputs_lo_lo_hi_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_128, decoder_decoded_andMatrixOutputs_andMatrixInput_16_75) node decoder_decoded_andMatrixOutputs_lo_lo_328 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_238, decoder_decoded_andMatrixOutputs_lo_lo_lo_128) node decoder_decoded_andMatrixOutputs_lo_hi_lo_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_227, decoder_decoded_andMatrixOutputs_andMatrixInput_14_203) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_244, decoder_decoded_andMatrixOutputs_andMatrixInput_11_238) node decoder_decoded_andMatrixOutputs_lo_hi_hi_250 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_231) node decoder_decoded_andMatrixOutputs_lo_hi_348 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_250, decoder_decoded_andMatrixOutputs_lo_hi_lo_227) node decoder_decoded_andMatrixOutputs_lo_350 = cat(decoder_decoded_andMatrixOutputs_lo_hi_348, decoder_decoded_andMatrixOutputs_lo_lo_328) node decoder_decoded_andMatrixOutputs_hi_lo_lo_203 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_290, decoder_decoded_andMatrixOutputs_andMatrixInput_9_250) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_348, decoder_decoded_andMatrixOutputs_andMatrixInput_6_342) node decoder_decoded_andMatrixOutputs_hi_lo_hi_244 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_andMatrixInput_7_328) node decoder_decoded_andMatrixOutputs_hi_lo_342 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_244, decoder_decoded_andMatrixOutputs_hi_lo_lo_203) node decoder_decoded_andMatrixOutputs_hi_hi_lo_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_350, decoder_decoded_andMatrixOutputs_andMatrixInput_4_350) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_75 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_350, decoder_decoded_andMatrixOutputs_andMatrixInput_1_350) node decoder_decoded_andMatrixOutputs_hi_hi_hi_290 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_75, decoder_decoded_andMatrixOutputs_andMatrixInput_2_350) node decoder_decoded_andMatrixOutputs_hi_hi_350 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_290, decoder_decoded_andMatrixOutputs_hi_hi_lo_231) node decoder_decoded_andMatrixOutputs_hi_350 = cat(decoder_decoded_andMatrixOutputs_hi_hi_350, decoder_decoded_andMatrixOutputs_hi_lo_342) node _decoder_decoded_andMatrixOutputs_T_350 = cat(decoder_decoded_andMatrixOutputs_hi_350, decoder_decoded_andMatrixOutputs_lo_350) node decoder_decoded_andMatrixOutputs_127_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_350) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_351 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_351 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_351 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_351 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_351 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_349 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_343 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_329 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_291 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_251 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_245 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_239 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_232 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_228 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_204 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_129 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_76 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_129 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_129, decoder_decoded_andMatrixOutputs_andMatrixInput_16_76) node decoder_decoded_andMatrixOutputs_lo_lo_hi_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_228, decoder_decoded_andMatrixOutputs_andMatrixInput_14_204) node decoder_decoded_andMatrixOutputs_lo_lo_329 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_239, decoder_decoded_andMatrixOutputs_lo_lo_lo_129) node decoder_decoded_andMatrixOutputs_lo_hi_lo_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_239, decoder_decoded_andMatrixOutputs_andMatrixInput_12_232) node decoder_decoded_andMatrixOutputs_lo_hi_hi_251 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_251, decoder_decoded_andMatrixOutputs_andMatrixInput_10_245) node decoder_decoded_andMatrixOutputs_lo_hi_349 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_251, decoder_decoded_andMatrixOutputs_lo_hi_lo_228) node decoder_decoded_andMatrixOutputs_lo_351 = cat(decoder_decoded_andMatrixOutputs_lo_hi_349, decoder_decoded_andMatrixOutputs_lo_lo_329) node decoder_decoded_andMatrixOutputs_hi_lo_lo_204 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_329, decoder_decoded_andMatrixOutputs_andMatrixInput_8_291) node decoder_decoded_andMatrixOutputs_hi_lo_hi_245 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_349, decoder_decoded_andMatrixOutputs_andMatrixInput_6_343) node decoder_decoded_andMatrixOutputs_hi_lo_343 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_245, decoder_decoded_andMatrixOutputs_hi_lo_lo_204) node decoder_decoded_andMatrixOutputs_hi_hi_lo_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_351, decoder_decoded_andMatrixOutputs_andMatrixInput_4_351) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_76 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_351, decoder_decoded_andMatrixOutputs_andMatrixInput_1_351) node decoder_decoded_andMatrixOutputs_hi_hi_hi_291 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_76, decoder_decoded_andMatrixOutputs_andMatrixInput_2_351) node decoder_decoded_andMatrixOutputs_hi_hi_351 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_291, decoder_decoded_andMatrixOutputs_hi_hi_lo_232) node decoder_decoded_andMatrixOutputs_hi_351 = cat(decoder_decoded_andMatrixOutputs_hi_hi_351, decoder_decoded_andMatrixOutputs_hi_lo_343) node _decoder_decoded_andMatrixOutputs_T_351 = cat(decoder_decoded_andMatrixOutputs_hi_351, decoder_decoded_andMatrixOutputs_lo_351) node decoder_decoded_andMatrixOutputs_151_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_351) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_352 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_352 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_352 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_352 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_352 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_350 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_344 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_330 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_292 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_252 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_246 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_240 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_233 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_229 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_205 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_130 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_77 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_130 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_130, decoder_decoded_andMatrixOutputs_andMatrixInput_16_77) node decoder_decoded_andMatrixOutputs_lo_lo_hi_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_229, decoder_decoded_andMatrixOutputs_andMatrixInput_14_205) node decoder_decoded_andMatrixOutputs_lo_lo_330 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_240, decoder_decoded_andMatrixOutputs_lo_lo_lo_130) node decoder_decoded_andMatrixOutputs_lo_hi_lo_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_240, decoder_decoded_andMatrixOutputs_andMatrixInput_12_233) node decoder_decoded_andMatrixOutputs_lo_hi_hi_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_252, decoder_decoded_andMatrixOutputs_andMatrixInput_10_246) node decoder_decoded_andMatrixOutputs_lo_hi_350 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_252, decoder_decoded_andMatrixOutputs_lo_hi_lo_229) node decoder_decoded_andMatrixOutputs_lo_352 = cat(decoder_decoded_andMatrixOutputs_lo_hi_350, decoder_decoded_andMatrixOutputs_lo_lo_330) node decoder_decoded_andMatrixOutputs_hi_lo_lo_205 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_330, decoder_decoded_andMatrixOutputs_andMatrixInput_8_292) node decoder_decoded_andMatrixOutputs_hi_lo_hi_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_350, decoder_decoded_andMatrixOutputs_andMatrixInput_6_344) node decoder_decoded_andMatrixOutputs_hi_lo_344 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_246, decoder_decoded_andMatrixOutputs_hi_lo_lo_205) node decoder_decoded_andMatrixOutputs_hi_hi_lo_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_352, decoder_decoded_andMatrixOutputs_andMatrixInput_4_352) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_77 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_352, decoder_decoded_andMatrixOutputs_andMatrixInput_1_352) node decoder_decoded_andMatrixOutputs_hi_hi_hi_292 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_2_352) node decoder_decoded_andMatrixOutputs_hi_hi_352 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_292, decoder_decoded_andMatrixOutputs_hi_hi_lo_233) node decoder_decoded_andMatrixOutputs_hi_352 = cat(decoder_decoded_andMatrixOutputs_hi_hi_352, decoder_decoded_andMatrixOutputs_hi_lo_344) node _decoder_decoded_andMatrixOutputs_T_352 = cat(decoder_decoded_andMatrixOutputs_hi_352, decoder_decoded_andMatrixOutputs_lo_352) node decoder_decoded_andMatrixOutputs_1_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_352) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_353 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_353 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_353 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_353 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_353 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_351 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_345 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_331 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_293 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_253 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_247 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_241 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_234 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_230 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_206 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_131 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_78 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_131 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_131, decoder_decoded_andMatrixOutputs_andMatrixInput_16_78) node decoder_decoded_andMatrixOutputs_lo_lo_hi_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_230, decoder_decoded_andMatrixOutputs_andMatrixInput_14_206) node decoder_decoded_andMatrixOutputs_lo_lo_331 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_241, decoder_decoded_andMatrixOutputs_lo_lo_lo_131) node decoder_decoded_andMatrixOutputs_lo_hi_lo_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_241, decoder_decoded_andMatrixOutputs_andMatrixInput_12_234) node decoder_decoded_andMatrixOutputs_lo_hi_hi_253 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_253, decoder_decoded_andMatrixOutputs_andMatrixInput_10_247) node decoder_decoded_andMatrixOutputs_lo_hi_351 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_253, decoder_decoded_andMatrixOutputs_lo_hi_lo_230) node decoder_decoded_andMatrixOutputs_lo_353 = cat(decoder_decoded_andMatrixOutputs_lo_hi_351, decoder_decoded_andMatrixOutputs_lo_lo_331) node decoder_decoded_andMatrixOutputs_hi_lo_lo_206 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_331, decoder_decoded_andMatrixOutputs_andMatrixInput_8_293) node decoder_decoded_andMatrixOutputs_hi_lo_hi_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_351, decoder_decoded_andMatrixOutputs_andMatrixInput_6_345) node decoder_decoded_andMatrixOutputs_hi_lo_345 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_247, decoder_decoded_andMatrixOutputs_hi_lo_lo_206) node decoder_decoded_andMatrixOutputs_hi_hi_lo_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_353, decoder_decoded_andMatrixOutputs_andMatrixInput_4_353) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_78 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_353, decoder_decoded_andMatrixOutputs_andMatrixInput_1_353) node decoder_decoded_andMatrixOutputs_hi_hi_hi_293 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_78, decoder_decoded_andMatrixOutputs_andMatrixInput_2_353) node decoder_decoded_andMatrixOutputs_hi_hi_353 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_293, decoder_decoded_andMatrixOutputs_hi_hi_lo_234) node decoder_decoded_andMatrixOutputs_hi_353 = cat(decoder_decoded_andMatrixOutputs_hi_hi_353, decoder_decoded_andMatrixOutputs_hi_lo_345) node _decoder_decoded_andMatrixOutputs_T_353 = cat(decoder_decoded_andMatrixOutputs_hi_353, decoder_decoded_andMatrixOutputs_lo_353) node decoder_decoded_andMatrixOutputs_99_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_353) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_354 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_354 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_354 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_354 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_354 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_352 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_346 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_332 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_294 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_254 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_248 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_242 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_235 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_231 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_207 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_132 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_79 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_53 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_39 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_35 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_132 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_39, decoder_decoded_andMatrixOutputs_andMatrixInput_19_35) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_132, decoder_decoded_andMatrixOutputs_andMatrixInput_16_79) node decoder_decoded_andMatrixOutputs_lo_lo_hi_242 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_17_53) node decoder_decoded_andMatrixOutputs_lo_lo_332 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_242, decoder_decoded_andMatrixOutputs_lo_lo_lo_132) node decoder_decoded_andMatrixOutputs_lo_hi_lo_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_231, decoder_decoded_andMatrixOutputs_andMatrixInput_14_207) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_248, decoder_decoded_andMatrixOutputs_andMatrixInput_11_242) node decoder_decoded_andMatrixOutputs_lo_hi_hi_254 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_235) node decoder_decoded_andMatrixOutputs_lo_hi_352 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_254, decoder_decoded_andMatrixOutputs_lo_hi_lo_231) node decoder_decoded_andMatrixOutputs_lo_354 = cat(decoder_decoded_andMatrixOutputs_lo_hi_352, decoder_decoded_andMatrixOutputs_lo_lo_332) node decoder_decoded_andMatrixOutputs_hi_lo_lo_207 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_294, decoder_decoded_andMatrixOutputs_andMatrixInput_9_254) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_352, decoder_decoded_andMatrixOutputs_andMatrixInput_6_346) node decoder_decoded_andMatrixOutputs_hi_lo_hi_248 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_7_332) node decoder_decoded_andMatrixOutputs_hi_lo_346 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_248, decoder_decoded_andMatrixOutputs_hi_lo_lo_207) node decoder_decoded_andMatrixOutputs_hi_hi_lo_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_354, decoder_decoded_andMatrixOutputs_andMatrixInput_4_354) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_79 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_354, decoder_decoded_andMatrixOutputs_andMatrixInput_1_354) node decoder_decoded_andMatrixOutputs_hi_hi_hi_294 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_79, decoder_decoded_andMatrixOutputs_andMatrixInput_2_354) node decoder_decoded_andMatrixOutputs_hi_hi_354 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_294, decoder_decoded_andMatrixOutputs_hi_hi_lo_235) node decoder_decoded_andMatrixOutputs_hi_354 = cat(decoder_decoded_andMatrixOutputs_hi_hi_354, decoder_decoded_andMatrixOutputs_hi_lo_346) node _decoder_decoded_andMatrixOutputs_T_354 = cat(decoder_decoded_andMatrixOutputs_hi_354, decoder_decoded_andMatrixOutputs_lo_354) node decoder_decoded_andMatrixOutputs_104_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_354) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_355 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_355 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_355 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_355 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_355 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_353 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_347 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_333 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_295 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_255 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_249 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_243 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_236 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_232 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_208 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_133 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_80 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_54 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_40 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_36 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_133 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_40, decoder_decoded_andMatrixOutputs_andMatrixInput_19_36) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_133, decoder_decoded_andMatrixOutputs_andMatrixInput_16_80) node decoder_decoded_andMatrixOutputs_lo_lo_hi_243 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_17_54) node decoder_decoded_andMatrixOutputs_lo_lo_333 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_243, decoder_decoded_andMatrixOutputs_lo_lo_lo_133) node decoder_decoded_andMatrixOutputs_lo_hi_lo_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_232, decoder_decoded_andMatrixOutputs_andMatrixInput_14_208) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_249, decoder_decoded_andMatrixOutputs_andMatrixInput_11_243) node decoder_decoded_andMatrixOutputs_lo_hi_hi_255 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_12_236) node decoder_decoded_andMatrixOutputs_lo_hi_353 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_255, decoder_decoded_andMatrixOutputs_lo_hi_lo_232) node decoder_decoded_andMatrixOutputs_lo_355 = cat(decoder_decoded_andMatrixOutputs_lo_hi_353, decoder_decoded_andMatrixOutputs_lo_lo_333) node decoder_decoded_andMatrixOutputs_hi_lo_lo_208 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_295, decoder_decoded_andMatrixOutputs_andMatrixInput_9_255) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_353, decoder_decoded_andMatrixOutputs_andMatrixInput_6_347) node decoder_decoded_andMatrixOutputs_hi_lo_hi_249 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_7_333) node decoder_decoded_andMatrixOutputs_hi_lo_347 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_249, decoder_decoded_andMatrixOutputs_hi_lo_lo_208) node decoder_decoded_andMatrixOutputs_hi_hi_lo_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_355, decoder_decoded_andMatrixOutputs_andMatrixInput_4_355) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_80 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_355, decoder_decoded_andMatrixOutputs_andMatrixInput_1_355) node decoder_decoded_andMatrixOutputs_hi_hi_hi_295 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_80, decoder_decoded_andMatrixOutputs_andMatrixInput_2_355) node decoder_decoded_andMatrixOutputs_hi_hi_355 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_295, decoder_decoded_andMatrixOutputs_hi_hi_lo_236) node decoder_decoded_andMatrixOutputs_hi_355 = cat(decoder_decoded_andMatrixOutputs_hi_hi_355, decoder_decoded_andMatrixOutputs_hi_lo_347) node _decoder_decoded_andMatrixOutputs_T_355 = cat(decoder_decoded_andMatrixOutputs_hi_355, decoder_decoded_andMatrixOutputs_lo_355) node decoder_decoded_andMatrixOutputs_186_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_355) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_356 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_356 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_356 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_356 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_356 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_354 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_348 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_334 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_296 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_256 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_250 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_244 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_237 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_233 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_209 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_134 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_81 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_55 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_41 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_37 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_26 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_134 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_37, decoder_decoded_andMatrixOutputs_andMatrixInput_20_26) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_81, decoder_decoded_andMatrixOutputs_andMatrixInput_17_55) node decoder_decoded_andMatrixOutputs_lo_lo_hi_244 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_18_41) node decoder_decoded_andMatrixOutputs_lo_lo_334 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_244, decoder_decoded_andMatrixOutputs_lo_lo_lo_134) node decoder_decoded_andMatrixOutputs_lo_hi_lo_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_209, decoder_decoded_andMatrixOutputs_andMatrixInput_15_134) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_244, decoder_decoded_andMatrixOutputs_andMatrixInput_12_237) node decoder_decoded_andMatrixOutputs_lo_hi_hi_256 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_233) node decoder_decoded_andMatrixOutputs_lo_hi_354 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_256, decoder_decoded_andMatrixOutputs_lo_hi_lo_233) node decoder_decoded_andMatrixOutputs_lo_356 = cat(decoder_decoded_andMatrixOutputs_lo_hi_354, decoder_decoded_andMatrixOutputs_lo_lo_334) node decoder_decoded_andMatrixOutputs_hi_lo_lo_209 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_256, decoder_decoded_andMatrixOutputs_andMatrixInput_10_250) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_348, decoder_decoded_andMatrixOutputs_andMatrixInput_7_334) node decoder_decoded_andMatrixOutputs_hi_lo_hi_250 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_296) node decoder_decoded_andMatrixOutputs_hi_lo_348 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_250, decoder_decoded_andMatrixOutputs_hi_lo_lo_209) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_356, decoder_decoded_andMatrixOutputs_andMatrixInput_4_356) node decoder_decoded_andMatrixOutputs_hi_hi_lo_237 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_354) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_81 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_356, decoder_decoded_andMatrixOutputs_andMatrixInput_1_356) node decoder_decoded_andMatrixOutputs_hi_hi_hi_296 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_81, decoder_decoded_andMatrixOutputs_andMatrixInput_2_356) node decoder_decoded_andMatrixOutputs_hi_hi_356 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_296, decoder_decoded_andMatrixOutputs_hi_hi_lo_237) node decoder_decoded_andMatrixOutputs_hi_356 = cat(decoder_decoded_andMatrixOutputs_hi_hi_356, decoder_decoded_andMatrixOutputs_hi_lo_348) node _decoder_decoded_andMatrixOutputs_T_356 = cat(decoder_decoded_andMatrixOutputs_hi_356, decoder_decoded_andMatrixOutputs_lo_356) node decoder_decoded_andMatrixOutputs_18_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_356) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_357 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_357 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_357 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_357 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_357 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_355 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_349 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_335 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_297 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_257 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_251 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_245 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_238 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_234 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_210 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_135 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_82 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_56 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_42 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_38 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_135 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_42, decoder_decoded_andMatrixOutputs_andMatrixInput_19_38) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_135, decoder_decoded_andMatrixOutputs_andMatrixInput_16_82) node decoder_decoded_andMatrixOutputs_lo_lo_hi_245 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_andMatrixInput_17_56) node decoder_decoded_andMatrixOutputs_lo_lo_335 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_245, decoder_decoded_andMatrixOutputs_lo_lo_lo_135) node decoder_decoded_andMatrixOutputs_lo_hi_lo_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_234, decoder_decoded_andMatrixOutputs_andMatrixInput_14_210) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_251, decoder_decoded_andMatrixOutputs_andMatrixInput_11_245) node decoder_decoded_andMatrixOutputs_lo_hi_hi_257 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_12_238) node decoder_decoded_andMatrixOutputs_lo_hi_355 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_257, decoder_decoded_andMatrixOutputs_lo_hi_lo_234) node decoder_decoded_andMatrixOutputs_lo_357 = cat(decoder_decoded_andMatrixOutputs_lo_hi_355, decoder_decoded_andMatrixOutputs_lo_lo_335) node decoder_decoded_andMatrixOutputs_hi_lo_lo_210 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_297, decoder_decoded_andMatrixOutputs_andMatrixInput_9_257) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_355, decoder_decoded_andMatrixOutputs_andMatrixInput_6_349) node decoder_decoded_andMatrixOutputs_hi_lo_hi_251 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_7_335) node decoder_decoded_andMatrixOutputs_hi_lo_349 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_251, decoder_decoded_andMatrixOutputs_hi_lo_lo_210) node decoder_decoded_andMatrixOutputs_hi_hi_lo_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_357, decoder_decoded_andMatrixOutputs_andMatrixInput_4_357) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_82 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_357, decoder_decoded_andMatrixOutputs_andMatrixInput_1_357) node decoder_decoded_andMatrixOutputs_hi_hi_hi_297 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_82, decoder_decoded_andMatrixOutputs_andMatrixInput_2_357) node decoder_decoded_andMatrixOutputs_hi_hi_357 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_297, decoder_decoded_andMatrixOutputs_hi_hi_lo_238) node decoder_decoded_andMatrixOutputs_hi_357 = cat(decoder_decoded_andMatrixOutputs_hi_hi_357, decoder_decoded_andMatrixOutputs_hi_lo_349) node _decoder_decoded_andMatrixOutputs_T_357 = cat(decoder_decoded_andMatrixOutputs_hi_357, decoder_decoded_andMatrixOutputs_lo_357) node decoder_decoded_andMatrixOutputs_106_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_357) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_358 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_358 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_358 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_358 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_358 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_356 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_350 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_336 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_298 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_258 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_252 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_246 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_239 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_235 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_211 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_239, decoder_decoded_andMatrixOutputs_andMatrixInput_13_235) node decoder_decoded_andMatrixOutputs_lo_lo_336 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_246, decoder_decoded_andMatrixOutputs_andMatrixInput_14_211) node decoder_decoded_andMatrixOutputs_lo_hi_lo_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_252, decoder_decoded_andMatrixOutputs_andMatrixInput_11_246) node decoder_decoded_andMatrixOutputs_lo_hi_hi_258 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_298, decoder_decoded_andMatrixOutputs_andMatrixInput_9_258) node decoder_decoded_andMatrixOutputs_lo_hi_356 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_258, decoder_decoded_andMatrixOutputs_lo_hi_lo_235) node decoder_decoded_andMatrixOutputs_lo_358 = cat(decoder_decoded_andMatrixOutputs_lo_hi_356, decoder_decoded_andMatrixOutputs_lo_lo_336) node decoder_decoded_andMatrixOutputs_hi_lo_lo_211 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_350, decoder_decoded_andMatrixOutputs_andMatrixInput_7_336) node decoder_decoded_andMatrixOutputs_hi_lo_hi_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_358, decoder_decoded_andMatrixOutputs_andMatrixInput_5_356) node decoder_decoded_andMatrixOutputs_hi_lo_350 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_252, decoder_decoded_andMatrixOutputs_hi_lo_lo_211) node decoder_decoded_andMatrixOutputs_hi_hi_lo_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_358, decoder_decoded_andMatrixOutputs_andMatrixInput_3_358) node decoder_decoded_andMatrixOutputs_hi_hi_hi_298 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_358, decoder_decoded_andMatrixOutputs_andMatrixInput_1_358) node decoder_decoded_andMatrixOutputs_hi_hi_358 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_298, decoder_decoded_andMatrixOutputs_hi_hi_lo_239) node decoder_decoded_andMatrixOutputs_hi_358 = cat(decoder_decoded_andMatrixOutputs_hi_hi_358, decoder_decoded_andMatrixOutputs_hi_lo_350) node _decoder_decoded_andMatrixOutputs_T_358 = cat(decoder_decoded_andMatrixOutputs_hi_358, decoder_decoded_andMatrixOutputs_lo_358) node decoder_decoded_andMatrixOutputs_88_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_358) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_359 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_359 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_359 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_359 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_359 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_357 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_351 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_337 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_299 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_259 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_253 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_247 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_240 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_236 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_212 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_136 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_136 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_212, decoder_decoded_andMatrixOutputs_andMatrixInput_15_136) node decoder_decoded_andMatrixOutputs_lo_lo_hi_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_240, decoder_decoded_andMatrixOutputs_andMatrixInput_13_236) node decoder_decoded_andMatrixOutputs_lo_lo_337 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_247, decoder_decoded_andMatrixOutputs_lo_lo_lo_136) node decoder_decoded_andMatrixOutputs_lo_hi_lo_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_253, decoder_decoded_andMatrixOutputs_andMatrixInput_11_247) node decoder_decoded_andMatrixOutputs_lo_hi_hi_259 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_299, decoder_decoded_andMatrixOutputs_andMatrixInput_9_259) node decoder_decoded_andMatrixOutputs_lo_hi_357 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_259, decoder_decoded_andMatrixOutputs_lo_hi_lo_236) node decoder_decoded_andMatrixOutputs_lo_359 = cat(decoder_decoded_andMatrixOutputs_lo_hi_357, decoder_decoded_andMatrixOutputs_lo_lo_337) node decoder_decoded_andMatrixOutputs_hi_lo_lo_212 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_351, decoder_decoded_andMatrixOutputs_andMatrixInput_7_337) node decoder_decoded_andMatrixOutputs_hi_lo_hi_253 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_359, decoder_decoded_andMatrixOutputs_andMatrixInput_5_357) node decoder_decoded_andMatrixOutputs_hi_lo_351 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_253, decoder_decoded_andMatrixOutputs_hi_lo_lo_212) node decoder_decoded_andMatrixOutputs_hi_hi_lo_240 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_359, decoder_decoded_andMatrixOutputs_andMatrixInput_3_359) node decoder_decoded_andMatrixOutputs_hi_hi_hi_299 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_359, decoder_decoded_andMatrixOutputs_andMatrixInput_1_359) node decoder_decoded_andMatrixOutputs_hi_hi_359 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_299, decoder_decoded_andMatrixOutputs_hi_hi_lo_240) node decoder_decoded_andMatrixOutputs_hi_359 = cat(decoder_decoded_andMatrixOutputs_hi_hi_359, decoder_decoded_andMatrixOutputs_hi_lo_351) node _decoder_decoded_andMatrixOutputs_T_359 = cat(decoder_decoded_andMatrixOutputs_hi_359, decoder_decoded_andMatrixOutputs_lo_359) node decoder_decoded_andMatrixOutputs_61_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_359) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_360 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_360 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_360 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_360 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_360 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_358 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_352 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_338 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_300 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_260 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_254 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_248 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_241 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_237 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_213 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_137 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_137 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_213, decoder_decoded_andMatrixOutputs_andMatrixInput_15_137) node decoder_decoded_andMatrixOutputs_lo_lo_hi_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_241, decoder_decoded_andMatrixOutputs_andMatrixInput_13_237) node decoder_decoded_andMatrixOutputs_lo_lo_338 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_248, decoder_decoded_andMatrixOutputs_lo_lo_lo_137) node decoder_decoded_andMatrixOutputs_lo_hi_lo_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_254, decoder_decoded_andMatrixOutputs_andMatrixInput_11_248) node decoder_decoded_andMatrixOutputs_lo_hi_hi_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_300, decoder_decoded_andMatrixOutputs_andMatrixInput_9_260) node decoder_decoded_andMatrixOutputs_lo_hi_358 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_260, decoder_decoded_andMatrixOutputs_lo_hi_lo_237) node decoder_decoded_andMatrixOutputs_lo_360 = cat(decoder_decoded_andMatrixOutputs_lo_hi_358, decoder_decoded_andMatrixOutputs_lo_lo_338) node decoder_decoded_andMatrixOutputs_hi_lo_lo_213 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_352, decoder_decoded_andMatrixOutputs_andMatrixInput_7_338) node decoder_decoded_andMatrixOutputs_hi_lo_hi_254 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_360, decoder_decoded_andMatrixOutputs_andMatrixInput_5_358) node decoder_decoded_andMatrixOutputs_hi_lo_352 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_254, decoder_decoded_andMatrixOutputs_hi_lo_lo_213) node decoder_decoded_andMatrixOutputs_hi_hi_lo_241 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_360, decoder_decoded_andMatrixOutputs_andMatrixInput_3_360) node decoder_decoded_andMatrixOutputs_hi_hi_hi_300 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_360, decoder_decoded_andMatrixOutputs_andMatrixInput_1_360) node decoder_decoded_andMatrixOutputs_hi_hi_360 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_300, decoder_decoded_andMatrixOutputs_hi_hi_lo_241) node decoder_decoded_andMatrixOutputs_hi_360 = cat(decoder_decoded_andMatrixOutputs_hi_hi_360, decoder_decoded_andMatrixOutputs_hi_lo_352) node _decoder_decoded_andMatrixOutputs_T_360 = cat(decoder_decoded_andMatrixOutputs_hi_360, decoder_decoded_andMatrixOutputs_lo_360) node decoder_decoded_andMatrixOutputs_149_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_360) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_361 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_361 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_361 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_361 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_361 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_359 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_353 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_339 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_301 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_261 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_255 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_249 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_242 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_238 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_214 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_138 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_138 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_214, decoder_decoded_andMatrixOutputs_andMatrixInput_15_138) node decoder_decoded_andMatrixOutputs_lo_lo_hi_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_242, decoder_decoded_andMatrixOutputs_andMatrixInput_13_238) node decoder_decoded_andMatrixOutputs_lo_lo_339 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_249, decoder_decoded_andMatrixOutputs_lo_lo_lo_138) node decoder_decoded_andMatrixOutputs_lo_hi_lo_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_255, decoder_decoded_andMatrixOutputs_andMatrixInput_11_249) node decoder_decoded_andMatrixOutputs_lo_hi_hi_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_301, decoder_decoded_andMatrixOutputs_andMatrixInput_9_261) node decoder_decoded_andMatrixOutputs_lo_hi_359 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_261, decoder_decoded_andMatrixOutputs_lo_hi_lo_238) node decoder_decoded_andMatrixOutputs_lo_361 = cat(decoder_decoded_andMatrixOutputs_lo_hi_359, decoder_decoded_andMatrixOutputs_lo_lo_339) node decoder_decoded_andMatrixOutputs_hi_lo_lo_214 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_353, decoder_decoded_andMatrixOutputs_andMatrixInput_7_339) node decoder_decoded_andMatrixOutputs_hi_lo_hi_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_361, decoder_decoded_andMatrixOutputs_andMatrixInput_5_359) node decoder_decoded_andMatrixOutputs_hi_lo_353 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_255, decoder_decoded_andMatrixOutputs_hi_lo_lo_214) node decoder_decoded_andMatrixOutputs_hi_hi_lo_242 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_361, decoder_decoded_andMatrixOutputs_andMatrixInput_3_361) node decoder_decoded_andMatrixOutputs_hi_hi_hi_301 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_361, decoder_decoded_andMatrixOutputs_andMatrixInput_1_361) node decoder_decoded_andMatrixOutputs_hi_hi_361 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_301, decoder_decoded_andMatrixOutputs_hi_hi_lo_242) node decoder_decoded_andMatrixOutputs_hi_361 = cat(decoder_decoded_andMatrixOutputs_hi_hi_361, decoder_decoded_andMatrixOutputs_hi_lo_353) node _decoder_decoded_andMatrixOutputs_T_361 = cat(decoder_decoded_andMatrixOutputs_hi_361, decoder_decoded_andMatrixOutputs_lo_361) node decoder_decoded_andMatrixOutputs_173_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_361) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_362 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_362 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_362 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_362 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_362 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_360 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_354 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_340 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_302 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_262 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_256 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_250 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_243 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_239 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_215 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_139 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_139 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_215, decoder_decoded_andMatrixOutputs_andMatrixInput_15_139) node decoder_decoded_andMatrixOutputs_lo_lo_hi_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_243, decoder_decoded_andMatrixOutputs_andMatrixInput_13_239) node decoder_decoded_andMatrixOutputs_lo_lo_340 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_250, decoder_decoded_andMatrixOutputs_lo_lo_lo_139) node decoder_decoded_andMatrixOutputs_lo_hi_lo_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_256, decoder_decoded_andMatrixOutputs_andMatrixInput_11_250) node decoder_decoded_andMatrixOutputs_lo_hi_hi_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_302, decoder_decoded_andMatrixOutputs_andMatrixInput_9_262) node decoder_decoded_andMatrixOutputs_lo_hi_360 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_262, decoder_decoded_andMatrixOutputs_lo_hi_lo_239) node decoder_decoded_andMatrixOutputs_lo_362 = cat(decoder_decoded_andMatrixOutputs_lo_hi_360, decoder_decoded_andMatrixOutputs_lo_lo_340) node decoder_decoded_andMatrixOutputs_hi_lo_lo_215 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_354, decoder_decoded_andMatrixOutputs_andMatrixInput_7_340) node decoder_decoded_andMatrixOutputs_hi_lo_hi_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_362, decoder_decoded_andMatrixOutputs_andMatrixInput_5_360) node decoder_decoded_andMatrixOutputs_hi_lo_354 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_256, decoder_decoded_andMatrixOutputs_hi_lo_lo_215) node decoder_decoded_andMatrixOutputs_hi_hi_lo_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_362, decoder_decoded_andMatrixOutputs_andMatrixInput_3_362) node decoder_decoded_andMatrixOutputs_hi_hi_hi_302 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_362, decoder_decoded_andMatrixOutputs_andMatrixInput_1_362) node decoder_decoded_andMatrixOutputs_hi_hi_362 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_302, decoder_decoded_andMatrixOutputs_hi_hi_lo_243) node decoder_decoded_andMatrixOutputs_hi_362 = cat(decoder_decoded_andMatrixOutputs_hi_hi_362, decoder_decoded_andMatrixOutputs_hi_lo_354) node _decoder_decoded_andMatrixOutputs_T_362 = cat(decoder_decoded_andMatrixOutputs_hi_362, decoder_decoded_andMatrixOutputs_lo_362) node decoder_decoded_andMatrixOutputs_37_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_362) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_363 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_363 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_363 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_363 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_363 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_361 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_355 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_341 = bits(decoder_decoded_plaInput_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_303 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_263 = bits(decoder_decoded_plaInput_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_257 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_251 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_244 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_240 = bits(decoder_decoded_plaInput_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_216 = bits(decoder_decoded_plaInput_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_140 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_83 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_57 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_43 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_39 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_27 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_21 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_140 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_27, decoder_decoded_andMatrixOutputs_andMatrixInput_21_21) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_57, decoder_decoded_andMatrixOutputs_andMatrixInput_18_43) node decoder_decoded_andMatrixOutputs_lo_lo_hi_251 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_19_39) node decoder_decoded_andMatrixOutputs_lo_lo_341 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_251, decoder_decoded_andMatrixOutputs_lo_lo_lo_140) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_216, decoder_decoded_andMatrixOutputs_andMatrixInput_15_140) node decoder_decoded_andMatrixOutputs_lo_hi_lo_240 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_16_83) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_251, decoder_decoded_andMatrixOutputs_andMatrixInput_12_244) node decoder_decoded_andMatrixOutputs_lo_hi_hi_263 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_13_240) node decoder_decoded_andMatrixOutputs_lo_hi_361 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_263, decoder_decoded_andMatrixOutputs_lo_hi_lo_240) node decoder_decoded_andMatrixOutputs_lo_363 = cat(decoder_decoded_andMatrixOutputs_lo_hi_361, decoder_decoded_andMatrixOutputs_lo_lo_341) node decoder_decoded_andMatrixOutputs_hi_lo_lo_216 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_263, decoder_decoded_andMatrixOutputs_andMatrixInput_10_257) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_355, decoder_decoded_andMatrixOutputs_andMatrixInput_7_341) node decoder_decoded_andMatrixOutputs_hi_lo_hi_257 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_303) node decoder_decoded_andMatrixOutputs_hi_lo_355 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_257, decoder_decoded_andMatrixOutputs_hi_lo_lo_216) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_363, decoder_decoded_andMatrixOutputs_andMatrixInput_4_363) node decoder_decoded_andMatrixOutputs_hi_hi_lo_244 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_361) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_83 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_363, decoder_decoded_andMatrixOutputs_andMatrixInput_1_363) node decoder_decoded_andMatrixOutputs_hi_hi_hi_303 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_83, decoder_decoded_andMatrixOutputs_andMatrixInput_2_363) node decoder_decoded_andMatrixOutputs_hi_hi_363 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_303, decoder_decoded_andMatrixOutputs_hi_hi_lo_244) node decoder_decoded_andMatrixOutputs_hi_363 = cat(decoder_decoded_andMatrixOutputs_hi_hi_363, decoder_decoded_andMatrixOutputs_hi_lo_355) node _decoder_decoded_andMatrixOutputs_T_363 = cat(decoder_decoded_andMatrixOutputs_hi_363, decoder_decoded_andMatrixOutputs_lo_363) node decoder_decoded_andMatrixOutputs_122_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_363) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_364 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_364 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_364 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_364 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_364 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_362 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_356 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_342 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_304 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_264 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_258 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_252 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_245 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_241 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_217 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_141 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_84 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_58 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_44 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_40 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_28 = bits(decoder_decoded_plaInput_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_22 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_14 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_14 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_14 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_14 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_14 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_14 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_25_14, decoder_decoded_andMatrixOutputs_andMatrixInput_26_14) node decoder_decoded_andMatrixOutputs_lo_lo_lo_141 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_27_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_23_14, decoder_decoded_andMatrixOutputs_andMatrixInput_24_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_21_22, decoder_decoded_andMatrixOutputs_andMatrixInput_22_14) node decoder_decoded_andMatrixOutputs_lo_lo_hi_252 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_14) node decoder_decoded_andMatrixOutputs_lo_lo_342 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_252, decoder_decoded_andMatrixOutputs_lo_lo_lo_141) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_44, decoder_decoded_andMatrixOutputs_andMatrixInput_19_40) node decoder_decoded_andMatrixOutputs_lo_hi_lo_241 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_20_28) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_84, decoder_decoded_andMatrixOutputs_andMatrixInput_17_58) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_217, decoder_decoded_andMatrixOutputs_andMatrixInput_15_141) node decoder_decoded_andMatrixOutputs_lo_hi_hi_264 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_14) node decoder_decoded_andMatrixOutputs_lo_hi_362 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_264, decoder_decoded_andMatrixOutputs_lo_hi_lo_241) node decoder_decoded_andMatrixOutputs_lo_364 = cat(decoder_decoded_andMatrixOutputs_lo_hi_362, decoder_decoded_andMatrixOutputs_lo_lo_342) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_252, decoder_decoded_andMatrixOutputs_andMatrixInput_12_245) node decoder_decoded_andMatrixOutputs_hi_lo_lo_217 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_241) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_264, decoder_decoded_andMatrixOutputs_andMatrixInput_10_258) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_342, decoder_decoded_andMatrixOutputs_andMatrixInput_8_304) node decoder_decoded_andMatrixOutputs_hi_lo_hi_258 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_14) node decoder_decoded_andMatrixOutputs_hi_lo_356 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_258, decoder_decoded_andMatrixOutputs_hi_lo_lo_217) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_364, decoder_decoded_andMatrixOutputs_andMatrixInput_5_362) node decoder_decoded_andMatrixOutputs_hi_hi_lo_245 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_6_356) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_364, decoder_decoded_andMatrixOutputs_andMatrixInput_3_364) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_84 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_364, decoder_decoded_andMatrixOutputs_andMatrixInput_1_364) node decoder_decoded_andMatrixOutputs_hi_hi_hi_304 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_84, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_14) node decoder_decoded_andMatrixOutputs_hi_hi_364 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_304, decoder_decoded_andMatrixOutputs_hi_hi_lo_245) node decoder_decoded_andMatrixOutputs_hi_364 = cat(decoder_decoded_andMatrixOutputs_hi_hi_364, decoder_decoded_andMatrixOutputs_hi_lo_356) node _decoder_decoded_andMatrixOutputs_T_364 = cat(decoder_decoded_andMatrixOutputs_hi_364, decoder_decoded_andMatrixOutputs_lo_364) node decoder_decoded_andMatrixOutputs_81_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_364) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_365 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_365 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_365 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_365 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_365 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_363 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_357 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_343 = bits(decoder_decoded_invInputs_1, 7, 7) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_305 = bits(decoder_decoded_invInputs_1, 8, 8) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_265 = bits(decoder_decoded_invInputs_1, 9, 9) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_259 = bits(decoder_decoded_invInputs_1, 10, 10) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_253 = bits(decoder_decoded_invInputs_1, 11, 11) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_246 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_242 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_218 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_142 = bits(decoder_decoded_invInputs_1, 15, 15) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_85 = bits(decoder_decoded_invInputs_1, 16, 16) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_59 = bits(decoder_decoded_invInputs_1, 17, 17) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_45 = bits(decoder_decoded_invInputs_1, 18, 18) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_41 = bits(decoder_decoded_invInputs_1, 19, 19) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_29 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_23 = bits(decoder_decoded_plaInput_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_22_15 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_23_15 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_24_15 = bits(decoder_decoded_plaInput_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_25_15 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_26_15 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_27_15 = bits(decoder_decoded_plaInput_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_28_7 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_29_7 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_30_7 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_31_3 = bits(decoder_decoded_invInputs_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_30_7, decoder_decoded_andMatrixOutputs_andMatrixInput_31_3) node decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_28_7, decoder_decoded_andMatrixOutputs_andMatrixInput_29_7) node decoder_decoded_andMatrixOutputs_lo_lo_lo_142 = cat(decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_26_15, decoder_decoded_andMatrixOutputs_andMatrixInput_27_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_24_15, decoder_decoded_andMatrixOutputs_andMatrixInput_25_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_253 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_15) node decoder_decoded_andMatrixOutputs_lo_lo_343 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_253, decoder_decoded_andMatrixOutputs_lo_lo_lo_142) node decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_22_15, decoder_decoded_andMatrixOutputs_andMatrixInput_23_15) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_29, decoder_decoded_andMatrixOutputs_andMatrixInput_21_23) node decoder_decoded_andMatrixOutputs_lo_hi_lo_242 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_7) node decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_45, decoder_decoded_andMatrixOutputs_andMatrixInput_19_41) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_85, decoder_decoded_andMatrixOutputs_andMatrixInput_17_59) node decoder_decoded_andMatrixOutputs_lo_hi_hi_265 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_15) node decoder_decoded_andMatrixOutputs_lo_hi_363 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_265, decoder_decoded_andMatrixOutputs_lo_hi_lo_242) node decoder_decoded_andMatrixOutputs_lo_365 = cat(decoder_decoded_andMatrixOutputs_lo_hi_363, decoder_decoded_andMatrixOutputs_lo_lo_343) node decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_218, decoder_decoded_andMatrixOutputs_andMatrixInput_15_142) node decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_246, decoder_decoded_andMatrixOutputs_andMatrixInput_13_242) node decoder_decoded_andMatrixOutputs_hi_lo_lo_218 = cat(decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_259, decoder_decoded_andMatrixOutputs_andMatrixInput_11_253) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_305, decoder_decoded_andMatrixOutputs_andMatrixInput_9_265) node decoder_decoded_andMatrixOutputs_hi_lo_hi_259 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_15) node decoder_decoded_andMatrixOutputs_hi_lo_357 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_259, decoder_decoded_andMatrixOutputs_hi_lo_lo_218) node decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_357, decoder_decoded_andMatrixOutputs_andMatrixInput_7_343) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_365, decoder_decoded_andMatrixOutputs_andMatrixInput_5_363) node decoder_decoded_andMatrixOutputs_hi_hi_lo_246 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_365, decoder_decoded_andMatrixOutputs_andMatrixInput_3_365) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_85 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_365, decoder_decoded_andMatrixOutputs_andMatrixInput_1_365) node decoder_decoded_andMatrixOutputs_hi_hi_hi_305 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_15) node decoder_decoded_andMatrixOutputs_hi_hi_365 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_305, decoder_decoded_andMatrixOutputs_hi_hi_lo_246) node decoder_decoded_andMatrixOutputs_hi_365 = cat(decoder_decoded_andMatrixOutputs_hi_hi_365, decoder_decoded_andMatrixOutputs_hi_lo_357) node _decoder_decoded_andMatrixOutputs_T_365 = cat(decoder_decoded_andMatrixOutputs_hi_365, decoder_decoded_andMatrixOutputs_lo_365) node decoder_decoded_andMatrixOutputs_119_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_365) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_366 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_366 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_366 = bits(decoder_decoded_plaInput_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_366 = bits(decoder_decoded_plaInput_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_366 = bits(decoder_decoded_invInputs_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_364 = bits(decoder_decoded_plaInput_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_358 = bits(decoder_decoded_invInputs_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_344 = bits(decoder_decoded_plaInput_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_306 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_266 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_260 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_254 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_254 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_266, decoder_decoded_andMatrixOutputs_andMatrixInput_10_260) node decoder_decoded_andMatrixOutputs_lo_lo_344 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_254, decoder_decoded_andMatrixOutputs_andMatrixInput_11_254) node decoder_decoded_andMatrixOutputs_lo_hi_hi_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_358, decoder_decoded_andMatrixOutputs_andMatrixInput_7_344) node decoder_decoded_andMatrixOutputs_lo_hi_364 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_266, decoder_decoded_andMatrixOutputs_andMatrixInput_8_306) node decoder_decoded_andMatrixOutputs_lo_366 = cat(decoder_decoded_andMatrixOutputs_lo_hi_364, decoder_decoded_andMatrixOutputs_lo_lo_344) node decoder_decoded_andMatrixOutputs_hi_lo_hi_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_366, decoder_decoded_andMatrixOutputs_andMatrixInput_4_366) node decoder_decoded_andMatrixOutputs_hi_lo_358 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_260, decoder_decoded_andMatrixOutputs_andMatrixInput_5_364) node decoder_decoded_andMatrixOutputs_hi_hi_hi_306 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_366, decoder_decoded_andMatrixOutputs_andMatrixInput_1_366) node decoder_decoded_andMatrixOutputs_hi_hi_366 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_306, decoder_decoded_andMatrixOutputs_andMatrixInput_2_366) node decoder_decoded_andMatrixOutputs_hi_366 = cat(decoder_decoded_andMatrixOutputs_hi_hi_366, decoder_decoded_andMatrixOutputs_hi_lo_358) node _decoder_decoded_andMatrixOutputs_T_366 = cat(decoder_decoded_andMatrixOutputs_hi_366, decoder_decoded_andMatrixOutputs_lo_366) node decoder_decoded_andMatrixOutputs_171_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_366) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_367 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_367 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_367 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_367 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_367 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_365 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_359 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_345 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_307 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_267 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_261 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_255 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_247 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_243 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_219 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_247, decoder_decoded_andMatrixOutputs_andMatrixInput_13_243) node decoder_decoded_andMatrixOutputs_lo_lo_345 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_255, decoder_decoded_andMatrixOutputs_andMatrixInput_14_219) node decoder_decoded_andMatrixOutputs_lo_hi_lo_243 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_261, decoder_decoded_andMatrixOutputs_andMatrixInput_11_255) node decoder_decoded_andMatrixOutputs_lo_hi_hi_267 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_307, decoder_decoded_andMatrixOutputs_andMatrixInput_9_267) node decoder_decoded_andMatrixOutputs_lo_hi_365 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_267, decoder_decoded_andMatrixOutputs_lo_hi_lo_243) node decoder_decoded_andMatrixOutputs_lo_367 = cat(decoder_decoded_andMatrixOutputs_lo_hi_365, decoder_decoded_andMatrixOutputs_lo_lo_345) node decoder_decoded_andMatrixOutputs_hi_lo_lo_219 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_359, decoder_decoded_andMatrixOutputs_andMatrixInput_7_345) node decoder_decoded_andMatrixOutputs_hi_lo_hi_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_367, decoder_decoded_andMatrixOutputs_andMatrixInput_5_365) node decoder_decoded_andMatrixOutputs_hi_lo_359 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_261, decoder_decoded_andMatrixOutputs_hi_lo_lo_219) node decoder_decoded_andMatrixOutputs_hi_hi_lo_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_367, decoder_decoded_andMatrixOutputs_andMatrixInput_3_367) node decoder_decoded_andMatrixOutputs_hi_hi_hi_307 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_367, decoder_decoded_andMatrixOutputs_andMatrixInput_1_367) node decoder_decoded_andMatrixOutputs_hi_hi_367 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_307, decoder_decoded_andMatrixOutputs_hi_hi_lo_247) node decoder_decoded_andMatrixOutputs_hi_367 = cat(decoder_decoded_andMatrixOutputs_hi_hi_367, decoder_decoded_andMatrixOutputs_hi_lo_359) node _decoder_decoded_andMatrixOutputs_T_367 = cat(decoder_decoded_andMatrixOutputs_hi_367, decoder_decoded_andMatrixOutputs_lo_367) node decoder_decoded_andMatrixOutputs_56_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_367) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_368 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_368 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_368 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_368 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_368 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_366 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_360 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_346 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_308 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_268 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_262 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_256 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_248 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_244 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_220 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_248, decoder_decoded_andMatrixOutputs_andMatrixInput_13_244) node decoder_decoded_andMatrixOutputs_lo_lo_346 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_256, decoder_decoded_andMatrixOutputs_andMatrixInput_14_220) node decoder_decoded_andMatrixOutputs_lo_hi_lo_244 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_262, decoder_decoded_andMatrixOutputs_andMatrixInput_11_256) node decoder_decoded_andMatrixOutputs_lo_hi_hi_268 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_308, decoder_decoded_andMatrixOutputs_andMatrixInput_9_268) node decoder_decoded_andMatrixOutputs_lo_hi_366 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_268, decoder_decoded_andMatrixOutputs_lo_hi_lo_244) node decoder_decoded_andMatrixOutputs_lo_368 = cat(decoder_decoded_andMatrixOutputs_lo_hi_366, decoder_decoded_andMatrixOutputs_lo_lo_346) node decoder_decoded_andMatrixOutputs_hi_lo_lo_220 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_360, decoder_decoded_andMatrixOutputs_andMatrixInput_7_346) node decoder_decoded_andMatrixOutputs_hi_lo_hi_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_368, decoder_decoded_andMatrixOutputs_andMatrixInput_5_366) node decoder_decoded_andMatrixOutputs_hi_lo_360 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_262, decoder_decoded_andMatrixOutputs_hi_lo_lo_220) node decoder_decoded_andMatrixOutputs_hi_hi_lo_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_368, decoder_decoded_andMatrixOutputs_andMatrixInput_3_368) node decoder_decoded_andMatrixOutputs_hi_hi_hi_308 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_368, decoder_decoded_andMatrixOutputs_andMatrixInput_1_368) node decoder_decoded_andMatrixOutputs_hi_hi_368 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_308, decoder_decoded_andMatrixOutputs_hi_hi_lo_248) node decoder_decoded_andMatrixOutputs_hi_368 = cat(decoder_decoded_andMatrixOutputs_hi_hi_368, decoder_decoded_andMatrixOutputs_hi_lo_360) node _decoder_decoded_andMatrixOutputs_T_368 = cat(decoder_decoded_andMatrixOutputs_hi_368, decoder_decoded_andMatrixOutputs_lo_368) node decoder_decoded_andMatrixOutputs_79_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_368) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_369 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_369 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_369 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_369 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_369 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_367 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_361 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_347 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_309 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_269 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_263 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_257 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_249 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_245 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_221 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_257 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_249, decoder_decoded_andMatrixOutputs_andMatrixInput_13_245) node decoder_decoded_andMatrixOutputs_lo_lo_347 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_257, decoder_decoded_andMatrixOutputs_andMatrixInput_14_221) node decoder_decoded_andMatrixOutputs_lo_hi_lo_245 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_263, decoder_decoded_andMatrixOutputs_andMatrixInput_11_257) node decoder_decoded_andMatrixOutputs_lo_hi_hi_269 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_309, decoder_decoded_andMatrixOutputs_andMatrixInput_9_269) node decoder_decoded_andMatrixOutputs_lo_hi_367 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_269, decoder_decoded_andMatrixOutputs_lo_hi_lo_245) node decoder_decoded_andMatrixOutputs_lo_369 = cat(decoder_decoded_andMatrixOutputs_lo_hi_367, decoder_decoded_andMatrixOutputs_lo_lo_347) node decoder_decoded_andMatrixOutputs_hi_lo_lo_221 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_361, decoder_decoded_andMatrixOutputs_andMatrixInput_7_347) node decoder_decoded_andMatrixOutputs_hi_lo_hi_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_369, decoder_decoded_andMatrixOutputs_andMatrixInput_5_367) node decoder_decoded_andMatrixOutputs_hi_lo_361 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_263, decoder_decoded_andMatrixOutputs_hi_lo_lo_221) node decoder_decoded_andMatrixOutputs_hi_hi_lo_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_369, decoder_decoded_andMatrixOutputs_andMatrixInput_3_369) node decoder_decoded_andMatrixOutputs_hi_hi_hi_309 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_369, decoder_decoded_andMatrixOutputs_andMatrixInput_1_369) node decoder_decoded_andMatrixOutputs_hi_hi_369 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_309, decoder_decoded_andMatrixOutputs_hi_hi_lo_249) node decoder_decoded_andMatrixOutputs_hi_369 = cat(decoder_decoded_andMatrixOutputs_hi_hi_369, decoder_decoded_andMatrixOutputs_hi_lo_361) node _decoder_decoded_andMatrixOutputs_T_369 = cat(decoder_decoded_andMatrixOutputs_hi_369, decoder_decoded_andMatrixOutputs_lo_369) node decoder_decoded_andMatrixOutputs_168_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_369) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_370 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_370 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_370 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_370 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_370 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_368 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_362 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_348 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_310 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_270 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_264 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_258 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_250 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_246 = bits(decoder_decoded_invInputs_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_222 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_258 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_250, decoder_decoded_andMatrixOutputs_andMatrixInput_13_246) node decoder_decoded_andMatrixOutputs_lo_lo_348 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_258, decoder_decoded_andMatrixOutputs_andMatrixInput_14_222) node decoder_decoded_andMatrixOutputs_lo_hi_lo_246 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_264, decoder_decoded_andMatrixOutputs_andMatrixInput_11_258) node decoder_decoded_andMatrixOutputs_lo_hi_hi_270 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_310, decoder_decoded_andMatrixOutputs_andMatrixInput_9_270) node decoder_decoded_andMatrixOutputs_lo_hi_368 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_270, decoder_decoded_andMatrixOutputs_lo_hi_lo_246) node decoder_decoded_andMatrixOutputs_lo_370 = cat(decoder_decoded_andMatrixOutputs_lo_hi_368, decoder_decoded_andMatrixOutputs_lo_lo_348) node decoder_decoded_andMatrixOutputs_hi_lo_lo_222 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_362, decoder_decoded_andMatrixOutputs_andMatrixInput_7_348) node decoder_decoded_andMatrixOutputs_hi_lo_hi_264 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_370, decoder_decoded_andMatrixOutputs_andMatrixInput_5_368) node decoder_decoded_andMatrixOutputs_hi_lo_362 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_264, decoder_decoded_andMatrixOutputs_hi_lo_lo_222) node decoder_decoded_andMatrixOutputs_hi_hi_lo_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_370, decoder_decoded_andMatrixOutputs_andMatrixInput_3_370) node decoder_decoded_andMatrixOutputs_hi_hi_hi_310 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_370, decoder_decoded_andMatrixOutputs_andMatrixInput_1_370) node decoder_decoded_andMatrixOutputs_hi_hi_370 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_310, decoder_decoded_andMatrixOutputs_hi_hi_lo_250) node decoder_decoded_andMatrixOutputs_hi_370 = cat(decoder_decoded_andMatrixOutputs_hi_hi_370, decoder_decoded_andMatrixOutputs_hi_lo_362) node _decoder_decoded_andMatrixOutputs_T_370 = cat(decoder_decoded_andMatrixOutputs_hi_370, decoder_decoded_andMatrixOutputs_lo_370) node decoder_decoded_andMatrixOutputs_154_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_370) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_371 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_371 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_371 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_371 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_371 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_369 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_363 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_349 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_311 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_271 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_265 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_259 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_251 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_247 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_223 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_143 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_143 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_223, decoder_decoded_andMatrixOutputs_andMatrixInput_15_143) node decoder_decoded_andMatrixOutputs_lo_lo_hi_259 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_251, decoder_decoded_andMatrixOutputs_andMatrixInput_13_247) node decoder_decoded_andMatrixOutputs_lo_lo_349 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_259, decoder_decoded_andMatrixOutputs_lo_lo_lo_143) node decoder_decoded_andMatrixOutputs_lo_hi_lo_247 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_265, decoder_decoded_andMatrixOutputs_andMatrixInput_11_259) node decoder_decoded_andMatrixOutputs_lo_hi_hi_271 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_311, decoder_decoded_andMatrixOutputs_andMatrixInput_9_271) node decoder_decoded_andMatrixOutputs_lo_hi_369 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_271, decoder_decoded_andMatrixOutputs_lo_hi_lo_247) node decoder_decoded_andMatrixOutputs_lo_371 = cat(decoder_decoded_andMatrixOutputs_lo_hi_369, decoder_decoded_andMatrixOutputs_lo_lo_349) node decoder_decoded_andMatrixOutputs_hi_lo_lo_223 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_363, decoder_decoded_andMatrixOutputs_andMatrixInput_7_349) node decoder_decoded_andMatrixOutputs_hi_lo_hi_265 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_371, decoder_decoded_andMatrixOutputs_andMatrixInput_5_369) node decoder_decoded_andMatrixOutputs_hi_lo_363 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_265, decoder_decoded_andMatrixOutputs_hi_lo_lo_223) node decoder_decoded_andMatrixOutputs_hi_hi_lo_251 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_371, decoder_decoded_andMatrixOutputs_andMatrixInput_3_371) node decoder_decoded_andMatrixOutputs_hi_hi_hi_311 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_371, decoder_decoded_andMatrixOutputs_andMatrixInput_1_371) node decoder_decoded_andMatrixOutputs_hi_hi_371 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_311, decoder_decoded_andMatrixOutputs_hi_hi_lo_251) node decoder_decoded_andMatrixOutputs_hi_371 = cat(decoder_decoded_andMatrixOutputs_hi_hi_371, decoder_decoded_andMatrixOutputs_hi_lo_363) node _decoder_decoded_andMatrixOutputs_T_371 = cat(decoder_decoded_andMatrixOutputs_hi_371, decoder_decoded_andMatrixOutputs_lo_371) node decoder_decoded_andMatrixOutputs_192_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_371) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_372 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_372 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_372 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_372 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_372 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_370 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_364 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_350 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_312 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_272 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_266 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_260 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_252 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_248 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_224 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_144 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_144 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_224, decoder_decoded_andMatrixOutputs_andMatrixInput_15_144) node decoder_decoded_andMatrixOutputs_lo_lo_hi_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_252, decoder_decoded_andMatrixOutputs_andMatrixInput_13_248) node decoder_decoded_andMatrixOutputs_lo_lo_350 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_260, decoder_decoded_andMatrixOutputs_lo_lo_lo_144) node decoder_decoded_andMatrixOutputs_lo_hi_lo_248 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_266, decoder_decoded_andMatrixOutputs_andMatrixInput_11_260) node decoder_decoded_andMatrixOutputs_lo_hi_hi_272 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_312, decoder_decoded_andMatrixOutputs_andMatrixInput_9_272) node decoder_decoded_andMatrixOutputs_lo_hi_370 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_272, decoder_decoded_andMatrixOutputs_lo_hi_lo_248) node decoder_decoded_andMatrixOutputs_lo_372 = cat(decoder_decoded_andMatrixOutputs_lo_hi_370, decoder_decoded_andMatrixOutputs_lo_lo_350) node decoder_decoded_andMatrixOutputs_hi_lo_lo_224 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_364, decoder_decoded_andMatrixOutputs_andMatrixInput_7_350) node decoder_decoded_andMatrixOutputs_hi_lo_hi_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_372, decoder_decoded_andMatrixOutputs_andMatrixInput_5_370) node decoder_decoded_andMatrixOutputs_hi_lo_364 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_266, decoder_decoded_andMatrixOutputs_hi_lo_lo_224) node decoder_decoded_andMatrixOutputs_hi_hi_lo_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_372, decoder_decoded_andMatrixOutputs_andMatrixInput_3_372) node decoder_decoded_andMatrixOutputs_hi_hi_hi_312 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_372, decoder_decoded_andMatrixOutputs_andMatrixInput_1_372) node decoder_decoded_andMatrixOutputs_hi_hi_372 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_312, decoder_decoded_andMatrixOutputs_hi_hi_lo_252) node decoder_decoded_andMatrixOutputs_hi_372 = cat(decoder_decoded_andMatrixOutputs_hi_hi_372, decoder_decoded_andMatrixOutputs_hi_lo_364) node _decoder_decoded_andMatrixOutputs_T_372 = cat(decoder_decoded_andMatrixOutputs_hi_372, decoder_decoded_andMatrixOutputs_lo_372) node decoder_decoded_andMatrixOutputs_38_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_372) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_373 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_373 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_373 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_373 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_373 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_371 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_365 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_351 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_313 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_273 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_267 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_261 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_253 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_249 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_225 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_253, decoder_decoded_andMatrixOutputs_andMatrixInput_13_249) node decoder_decoded_andMatrixOutputs_lo_lo_351 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_261, decoder_decoded_andMatrixOutputs_andMatrixInput_14_225) node decoder_decoded_andMatrixOutputs_lo_hi_lo_249 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_267, decoder_decoded_andMatrixOutputs_andMatrixInput_11_261) node decoder_decoded_andMatrixOutputs_lo_hi_hi_273 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_313, decoder_decoded_andMatrixOutputs_andMatrixInput_9_273) node decoder_decoded_andMatrixOutputs_lo_hi_371 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_273, decoder_decoded_andMatrixOutputs_lo_hi_lo_249) node decoder_decoded_andMatrixOutputs_lo_373 = cat(decoder_decoded_andMatrixOutputs_lo_hi_371, decoder_decoded_andMatrixOutputs_lo_lo_351) node decoder_decoded_andMatrixOutputs_hi_lo_lo_225 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_365, decoder_decoded_andMatrixOutputs_andMatrixInput_7_351) node decoder_decoded_andMatrixOutputs_hi_lo_hi_267 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_373, decoder_decoded_andMatrixOutputs_andMatrixInput_5_371) node decoder_decoded_andMatrixOutputs_hi_lo_365 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_267, decoder_decoded_andMatrixOutputs_hi_lo_lo_225) node decoder_decoded_andMatrixOutputs_hi_hi_lo_253 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_373, decoder_decoded_andMatrixOutputs_andMatrixInput_3_373) node decoder_decoded_andMatrixOutputs_hi_hi_hi_313 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_373, decoder_decoded_andMatrixOutputs_andMatrixInput_1_373) node decoder_decoded_andMatrixOutputs_hi_hi_373 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_313, decoder_decoded_andMatrixOutputs_hi_hi_lo_253) node decoder_decoded_andMatrixOutputs_hi_373 = cat(decoder_decoded_andMatrixOutputs_hi_hi_373, decoder_decoded_andMatrixOutputs_hi_lo_365) node _decoder_decoded_andMatrixOutputs_T_373 = cat(decoder_decoded_andMatrixOutputs_hi_373, decoder_decoded_andMatrixOutputs_lo_373) node decoder_decoded_andMatrixOutputs_158_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_373) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_374 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_374 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_374 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_374 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_374 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_372 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_366 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_352 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_314 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_274 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_268 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_262 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_254 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_250 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_226 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_254, decoder_decoded_andMatrixOutputs_andMatrixInput_13_250) node decoder_decoded_andMatrixOutputs_lo_lo_352 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_262, decoder_decoded_andMatrixOutputs_andMatrixInput_14_226) node decoder_decoded_andMatrixOutputs_lo_hi_lo_250 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_268, decoder_decoded_andMatrixOutputs_andMatrixInput_11_262) node decoder_decoded_andMatrixOutputs_lo_hi_hi_274 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_314, decoder_decoded_andMatrixOutputs_andMatrixInput_9_274) node decoder_decoded_andMatrixOutputs_lo_hi_372 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_274, decoder_decoded_andMatrixOutputs_lo_hi_lo_250) node decoder_decoded_andMatrixOutputs_lo_374 = cat(decoder_decoded_andMatrixOutputs_lo_hi_372, decoder_decoded_andMatrixOutputs_lo_lo_352) node decoder_decoded_andMatrixOutputs_hi_lo_lo_226 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_366, decoder_decoded_andMatrixOutputs_andMatrixInput_7_352) node decoder_decoded_andMatrixOutputs_hi_lo_hi_268 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_374, decoder_decoded_andMatrixOutputs_andMatrixInput_5_372) node decoder_decoded_andMatrixOutputs_hi_lo_366 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_268, decoder_decoded_andMatrixOutputs_hi_lo_lo_226) node decoder_decoded_andMatrixOutputs_hi_hi_lo_254 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_374, decoder_decoded_andMatrixOutputs_andMatrixInput_3_374) node decoder_decoded_andMatrixOutputs_hi_hi_hi_314 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_374, decoder_decoded_andMatrixOutputs_andMatrixInput_1_374) node decoder_decoded_andMatrixOutputs_hi_hi_374 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_314, decoder_decoded_andMatrixOutputs_hi_hi_lo_254) node decoder_decoded_andMatrixOutputs_hi_374 = cat(decoder_decoded_andMatrixOutputs_hi_hi_374, decoder_decoded_andMatrixOutputs_hi_lo_366) node _decoder_decoded_andMatrixOutputs_T_374 = cat(decoder_decoded_andMatrixOutputs_hi_374, decoder_decoded_andMatrixOutputs_lo_374) node decoder_decoded_andMatrixOutputs_109_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_374) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_375 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_375 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_375 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_375 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_375 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_373 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_367 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_353 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_315 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_275 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_269 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_263 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_255 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_251 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_227 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_145 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_145 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_227, decoder_decoded_andMatrixOutputs_andMatrixInput_15_145) node decoder_decoded_andMatrixOutputs_lo_lo_hi_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_255, decoder_decoded_andMatrixOutputs_andMatrixInput_13_251) node decoder_decoded_andMatrixOutputs_lo_lo_353 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_263, decoder_decoded_andMatrixOutputs_lo_lo_lo_145) node decoder_decoded_andMatrixOutputs_lo_hi_lo_251 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_269, decoder_decoded_andMatrixOutputs_andMatrixInput_11_263) node decoder_decoded_andMatrixOutputs_lo_hi_hi_275 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_315, decoder_decoded_andMatrixOutputs_andMatrixInput_9_275) node decoder_decoded_andMatrixOutputs_lo_hi_373 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_275, decoder_decoded_andMatrixOutputs_lo_hi_lo_251) node decoder_decoded_andMatrixOutputs_lo_375 = cat(decoder_decoded_andMatrixOutputs_lo_hi_373, decoder_decoded_andMatrixOutputs_lo_lo_353) node decoder_decoded_andMatrixOutputs_hi_lo_lo_227 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_367, decoder_decoded_andMatrixOutputs_andMatrixInput_7_353) node decoder_decoded_andMatrixOutputs_hi_lo_hi_269 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_375, decoder_decoded_andMatrixOutputs_andMatrixInput_5_373) node decoder_decoded_andMatrixOutputs_hi_lo_367 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_269, decoder_decoded_andMatrixOutputs_hi_lo_lo_227) node decoder_decoded_andMatrixOutputs_hi_hi_lo_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_375, decoder_decoded_andMatrixOutputs_andMatrixInput_3_375) node decoder_decoded_andMatrixOutputs_hi_hi_hi_315 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_375, decoder_decoded_andMatrixOutputs_andMatrixInput_1_375) node decoder_decoded_andMatrixOutputs_hi_hi_375 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_315, decoder_decoded_andMatrixOutputs_hi_hi_lo_255) node decoder_decoded_andMatrixOutputs_hi_375 = cat(decoder_decoded_andMatrixOutputs_hi_hi_375, decoder_decoded_andMatrixOutputs_hi_lo_367) node _decoder_decoded_andMatrixOutputs_T_375 = cat(decoder_decoded_andMatrixOutputs_hi_375, decoder_decoded_andMatrixOutputs_lo_375) node decoder_decoded_andMatrixOutputs_23_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_375) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_376 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_376 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_376 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_376 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_376 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_374 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_368 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_354 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_316 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_276 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_270 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_264 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_256 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_252 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_228 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_146 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_146 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_228, decoder_decoded_andMatrixOutputs_andMatrixInput_15_146) node decoder_decoded_andMatrixOutputs_lo_lo_hi_264 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_256, decoder_decoded_andMatrixOutputs_andMatrixInput_13_252) node decoder_decoded_andMatrixOutputs_lo_lo_354 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_264, decoder_decoded_andMatrixOutputs_lo_lo_lo_146) node decoder_decoded_andMatrixOutputs_lo_hi_lo_252 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_270, decoder_decoded_andMatrixOutputs_andMatrixInput_11_264) node decoder_decoded_andMatrixOutputs_lo_hi_hi_276 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_316, decoder_decoded_andMatrixOutputs_andMatrixInput_9_276) node decoder_decoded_andMatrixOutputs_lo_hi_374 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_276, decoder_decoded_andMatrixOutputs_lo_hi_lo_252) node decoder_decoded_andMatrixOutputs_lo_376 = cat(decoder_decoded_andMatrixOutputs_lo_hi_374, decoder_decoded_andMatrixOutputs_lo_lo_354) node decoder_decoded_andMatrixOutputs_hi_lo_lo_228 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_368, decoder_decoded_andMatrixOutputs_andMatrixInput_7_354) node decoder_decoded_andMatrixOutputs_hi_lo_hi_270 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_376, decoder_decoded_andMatrixOutputs_andMatrixInput_5_374) node decoder_decoded_andMatrixOutputs_hi_lo_368 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_270, decoder_decoded_andMatrixOutputs_hi_lo_lo_228) node decoder_decoded_andMatrixOutputs_hi_hi_lo_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_376, decoder_decoded_andMatrixOutputs_andMatrixInput_3_376) node decoder_decoded_andMatrixOutputs_hi_hi_hi_316 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_376, decoder_decoded_andMatrixOutputs_andMatrixInput_1_376) node decoder_decoded_andMatrixOutputs_hi_hi_376 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_316, decoder_decoded_andMatrixOutputs_hi_hi_lo_256) node decoder_decoded_andMatrixOutputs_hi_376 = cat(decoder_decoded_andMatrixOutputs_hi_hi_376, decoder_decoded_andMatrixOutputs_hi_lo_368) node _decoder_decoded_andMatrixOutputs_T_376 = cat(decoder_decoded_andMatrixOutputs_hi_376, decoder_decoded_andMatrixOutputs_lo_376) node decoder_decoded_andMatrixOutputs_100_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_376) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_377 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_377 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_377 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_377 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_377 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_375 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_369 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_355 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_317 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_277 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_271 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_265 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_257 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_253 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_229 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_147 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_147 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_229, decoder_decoded_andMatrixOutputs_andMatrixInput_15_147) node decoder_decoded_andMatrixOutputs_lo_lo_hi_265 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_257, decoder_decoded_andMatrixOutputs_andMatrixInput_13_253) node decoder_decoded_andMatrixOutputs_lo_lo_355 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_265, decoder_decoded_andMatrixOutputs_lo_lo_lo_147) node decoder_decoded_andMatrixOutputs_lo_hi_lo_253 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_271, decoder_decoded_andMatrixOutputs_andMatrixInput_11_265) node decoder_decoded_andMatrixOutputs_lo_hi_hi_277 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_317, decoder_decoded_andMatrixOutputs_andMatrixInput_9_277) node decoder_decoded_andMatrixOutputs_lo_hi_375 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_277, decoder_decoded_andMatrixOutputs_lo_hi_lo_253) node decoder_decoded_andMatrixOutputs_lo_377 = cat(decoder_decoded_andMatrixOutputs_lo_hi_375, decoder_decoded_andMatrixOutputs_lo_lo_355) node decoder_decoded_andMatrixOutputs_hi_lo_lo_229 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_369, decoder_decoded_andMatrixOutputs_andMatrixInput_7_355) node decoder_decoded_andMatrixOutputs_hi_lo_hi_271 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_377, decoder_decoded_andMatrixOutputs_andMatrixInput_5_375) node decoder_decoded_andMatrixOutputs_hi_lo_369 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_271, decoder_decoded_andMatrixOutputs_hi_lo_lo_229) node decoder_decoded_andMatrixOutputs_hi_hi_lo_257 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_377, decoder_decoded_andMatrixOutputs_andMatrixInput_3_377) node decoder_decoded_andMatrixOutputs_hi_hi_hi_317 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_377, decoder_decoded_andMatrixOutputs_andMatrixInput_1_377) node decoder_decoded_andMatrixOutputs_hi_hi_377 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_317, decoder_decoded_andMatrixOutputs_hi_hi_lo_257) node decoder_decoded_andMatrixOutputs_hi_377 = cat(decoder_decoded_andMatrixOutputs_hi_hi_377, decoder_decoded_andMatrixOutputs_hi_lo_369) node _decoder_decoded_andMatrixOutputs_T_377 = cat(decoder_decoded_andMatrixOutputs_hi_377, decoder_decoded_andMatrixOutputs_lo_377) node decoder_decoded_andMatrixOutputs_118_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_377) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_378 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_378 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_378 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_378 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_378 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_376 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_370 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_356 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_318 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_278 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_272 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_266 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_258 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_254 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_230 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_148 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_148 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_230, decoder_decoded_andMatrixOutputs_andMatrixInput_15_148) node decoder_decoded_andMatrixOutputs_lo_lo_hi_266 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_258, decoder_decoded_andMatrixOutputs_andMatrixInput_13_254) node decoder_decoded_andMatrixOutputs_lo_lo_356 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_266, decoder_decoded_andMatrixOutputs_lo_lo_lo_148) node decoder_decoded_andMatrixOutputs_lo_hi_lo_254 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_272, decoder_decoded_andMatrixOutputs_andMatrixInput_11_266) node decoder_decoded_andMatrixOutputs_lo_hi_hi_278 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_318, decoder_decoded_andMatrixOutputs_andMatrixInput_9_278) node decoder_decoded_andMatrixOutputs_lo_hi_376 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_278, decoder_decoded_andMatrixOutputs_lo_hi_lo_254) node decoder_decoded_andMatrixOutputs_lo_378 = cat(decoder_decoded_andMatrixOutputs_lo_hi_376, decoder_decoded_andMatrixOutputs_lo_lo_356) node decoder_decoded_andMatrixOutputs_hi_lo_lo_230 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_370, decoder_decoded_andMatrixOutputs_andMatrixInput_7_356) node decoder_decoded_andMatrixOutputs_hi_lo_hi_272 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_378, decoder_decoded_andMatrixOutputs_andMatrixInput_5_376) node decoder_decoded_andMatrixOutputs_hi_lo_370 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_272, decoder_decoded_andMatrixOutputs_hi_lo_lo_230) node decoder_decoded_andMatrixOutputs_hi_hi_lo_258 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_378, decoder_decoded_andMatrixOutputs_andMatrixInput_3_378) node decoder_decoded_andMatrixOutputs_hi_hi_hi_318 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_378, decoder_decoded_andMatrixOutputs_andMatrixInput_1_378) node decoder_decoded_andMatrixOutputs_hi_hi_378 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_318, decoder_decoded_andMatrixOutputs_hi_hi_lo_258) node decoder_decoded_andMatrixOutputs_hi_378 = cat(decoder_decoded_andMatrixOutputs_hi_hi_378, decoder_decoded_andMatrixOutputs_hi_lo_370) node _decoder_decoded_andMatrixOutputs_T_378 = cat(decoder_decoded_andMatrixOutputs_hi_378, decoder_decoded_andMatrixOutputs_lo_378) node decoder_decoded_andMatrixOutputs_116_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_378) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_379 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_379 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_379 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_379 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_379 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_377 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_371 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_357 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_319 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_279 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_273 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_267 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_259 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_255 = bits(decoder_decoded_invInputs_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_231 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_149 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_149 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_231, decoder_decoded_andMatrixOutputs_andMatrixInput_15_149) node decoder_decoded_andMatrixOutputs_lo_lo_hi_267 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_259, decoder_decoded_andMatrixOutputs_andMatrixInput_13_255) node decoder_decoded_andMatrixOutputs_lo_lo_357 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_267, decoder_decoded_andMatrixOutputs_lo_lo_lo_149) node decoder_decoded_andMatrixOutputs_lo_hi_lo_255 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_273, decoder_decoded_andMatrixOutputs_andMatrixInput_11_267) node decoder_decoded_andMatrixOutputs_lo_hi_hi_279 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_319, decoder_decoded_andMatrixOutputs_andMatrixInput_9_279) node decoder_decoded_andMatrixOutputs_lo_hi_377 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_279, decoder_decoded_andMatrixOutputs_lo_hi_lo_255) node decoder_decoded_andMatrixOutputs_lo_379 = cat(decoder_decoded_andMatrixOutputs_lo_hi_377, decoder_decoded_andMatrixOutputs_lo_lo_357) node decoder_decoded_andMatrixOutputs_hi_lo_lo_231 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_371, decoder_decoded_andMatrixOutputs_andMatrixInput_7_357) node decoder_decoded_andMatrixOutputs_hi_lo_hi_273 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_379, decoder_decoded_andMatrixOutputs_andMatrixInput_5_377) node decoder_decoded_andMatrixOutputs_hi_lo_371 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_273, decoder_decoded_andMatrixOutputs_hi_lo_lo_231) node decoder_decoded_andMatrixOutputs_hi_hi_lo_259 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_379, decoder_decoded_andMatrixOutputs_andMatrixInput_3_379) node decoder_decoded_andMatrixOutputs_hi_hi_hi_319 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_379, decoder_decoded_andMatrixOutputs_andMatrixInput_1_379) node decoder_decoded_andMatrixOutputs_hi_hi_379 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_319, decoder_decoded_andMatrixOutputs_hi_hi_lo_259) node decoder_decoded_andMatrixOutputs_hi_379 = cat(decoder_decoded_andMatrixOutputs_hi_hi_379, decoder_decoded_andMatrixOutputs_hi_lo_371) node _decoder_decoded_andMatrixOutputs_T_379 = cat(decoder_decoded_andMatrixOutputs_hi_379, decoder_decoded_andMatrixOutputs_lo_379) node decoder_decoded_andMatrixOutputs_156_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_379) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_380 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_380 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_380 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_380 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_380 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_378 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_372 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_358 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_320 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_280 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_274 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_268 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_260 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_256 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_232 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_150 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_86 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_60 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_46 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_42 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_150 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_46, decoder_decoded_andMatrixOutputs_andMatrixInput_19_42) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_150, decoder_decoded_andMatrixOutputs_andMatrixInput_16_86) node decoder_decoded_andMatrixOutputs_lo_lo_hi_268 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_17_60) node decoder_decoded_andMatrixOutputs_lo_lo_358 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_268, decoder_decoded_andMatrixOutputs_lo_lo_lo_150) node decoder_decoded_andMatrixOutputs_lo_hi_lo_256 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_256, decoder_decoded_andMatrixOutputs_andMatrixInput_14_232) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_274, decoder_decoded_andMatrixOutputs_andMatrixInput_11_268) node decoder_decoded_andMatrixOutputs_lo_hi_hi_280 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_260) node decoder_decoded_andMatrixOutputs_lo_hi_378 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_280, decoder_decoded_andMatrixOutputs_lo_hi_lo_256) node decoder_decoded_andMatrixOutputs_lo_380 = cat(decoder_decoded_andMatrixOutputs_lo_hi_378, decoder_decoded_andMatrixOutputs_lo_lo_358) node decoder_decoded_andMatrixOutputs_hi_lo_lo_232 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_320, decoder_decoded_andMatrixOutputs_andMatrixInput_9_280) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_378, decoder_decoded_andMatrixOutputs_andMatrixInput_6_372) node decoder_decoded_andMatrixOutputs_hi_lo_hi_274 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_7_358) node decoder_decoded_andMatrixOutputs_hi_lo_372 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_274, decoder_decoded_andMatrixOutputs_hi_lo_lo_232) node decoder_decoded_andMatrixOutputs_hi_hi_lo_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_380, decoder_decoded_andMatrixOutputs_andMatrixInput_4_380) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_86 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_380, decoder_decoded_andMatrixOutputs_andMatrixInput_1_380) node decoder_decoded_andMatrixOutputs_hi_hi_hi_320 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_86, decoder_decoded_andMatrixOutputs_andMatrixInput_2_380) node decoder_decoded_andMatrixOutputs_hi_hi_380 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_320, decoder_decoded_andMatrixOutputs_hi_hi_lo_260) node decoder_decoded_andMatrixOutputs_hi_380 = cat(decoder_decoded_andMatrixOutputs_hi_hi_380, decoder_decoded_andMatrixOutputs_hi_lo_372) node _decoder_decoded_andMatrixOutputs_T_380 = cat(decoder_decoded_andMatrixOutputs_hi_380, decoder_decoded_andMatrixOutputs_lo_380) node decoder_decoded_andMatrixOutputs_113_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_380) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_381 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_381 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_381 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_381 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_381 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_379 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_373 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_359 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_321 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_281 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_275 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_269 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_261 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_257 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_233 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_151 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_87 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_61 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_47 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_43 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_151 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_47, decoder_decoded_andMatrixOutputs_andMatrixInput_19_43) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_151, decoder_decoded_andMatrixOutputs_andMatrixInput_16_87) node decoder_decoded_andMatrixOutputs_lo_lo_hi_269 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_17_61) node decoder_decoded_andMatrixOutputs_lo_lo_359 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_269, decoder_decoded_andMatrixOutputs_lo_lo_lo_151) node decoder_decoded_andMatrixOutputs_lo_hi_lo_257 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_257, decoder_decoded_andMatrixOutputs_andMatrixInput_14_233) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_275, decoder_decoded_andMatrixOutputs_andMatrixInput_11_269) node decoder_decoded_andMatrixOutputs_lo_hi_hi_281 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_261) node decoder_decoded_andMatrixOutputs_lo_hi_379 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_281, decoder_decoded_andMatrixOutputs_lo_hi_lo_257) node decoder_decoded_andMatrixOutputs_lo_381 = cat(decoder_decoded_andMatrixOutputs_lo_hi_379, decoder_decoded_andMatrixOutputs_lo_lo_359) node decoder_decoded_andMatrixOutputs_hi_lo_lo_233 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_321, decoder_decoded_andMatrixOutputs_andMatrixInput_9_281) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_379, decoder_decoded_andMatrixOutputs_andMatrixInput_6_373) node decoder_decoded_andMatrixOutputs_hi_lo_hi_275 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_7_359) node decoder_decoded_andMatrixOutputs_hi_lo_373 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_275, decoder_decoded_andMatrixOutputs_hi_lo_lo_233) node decoder_decoded_andMatrixOutputs_hi_hi_lo_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_381, decoder_decoded_andMatrixOutputs_andMatrixInput_4_381) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_87 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_381, decoder_decoded_andMatrixOutputs_andMatrixInput_1_381) node decoder_decoded_andMatrixOutputs_hi_hi_hi_321 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_87, decoder_decoded_andMatrixOutputs_andMatrixInput_2_381) node decoder_decoded_andMatrixOutputs_hi_hi_381 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_321, decoder_decoded_andMatrixOutputs_hi_hi_lo_261) node decoder_decoded_andMatrixOutputs_hi_381 = cat(decoder_decoded_andMatrixOutputs_hi_hi_381, decoder_decoded_andMatrixOutputs_hi_lo_373) node _decoder_decoded_andMatrixOutputs_T_381 = cat(decoder_decoded_andMatrixOutputs_hi_381, decoder_decoded_andMatrixOutputs_lo_381) node decoder_decoded_andMatrixOutputs_105_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_381) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_382 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_382 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_382 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_382 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_382 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_380 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_374 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_360 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_322 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_282 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_276 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_270 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_262 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_258 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_234 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_152 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_88 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_62 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_48 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_44 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_152 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_48, decoder_decoded_andMatrixOutputs_andMatrixInput_19_44) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_152, decoder_decoded_andMatrixOutputs_andMatrixInput_16_88) node decoder_decoded_andMatrixOutputs_lo_lo_hi_270 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_17_62) node decoder_decoded_andMatrixOutputs_lo_lo_360 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_270, decoder_decoded_andMatrixOutputs_lo_lo_lo_152) node decoder_decoded_andMatrixOutputs_lo_hi_lo_258 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_258, decoder_decoded_andMatrixOutputs_andMatrixInput_14_234) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_276, decoder_decoded_andMatrixOutputs_andMatrixInput_11_270) node decoder_decoded_andMatrixOutputs_lo_hi_hi_282 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_262) node decoder_decoded_andMatrixOutputs_lo_hi_380 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_282, decoder_decoded_andMatrixOutputs_lo_hi_lo_258) node decoder_decoded_andMatrixOutputs_lo_382 = cat(decoder_decoded_andMatrixOutputs_lo_hi_380, decoder_decoded_andMatrixOutputs_lo_lo_360) node decoder_decoded_andMatrixOutputs_hi_lo_lo_234 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_322, decoder_decoded_andMatrixOutputs_andMatrixInput_9_282) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_380, decoder_decoded_andMatrixOutputs_andMatrixInput_6_374) node decoder_decoded_andMatrixOutputs_hi_lo_hi_276 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_7_360) node decoder_decoded_andMatrixOutputs_hi_lo_374 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_276, decoder_decoded_andMatrixOutputs_hi_lo_lo_234) node decoder_decoded_andMatrixOutputs_hi_hi_lo_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_382, decoder_decoded_andMatrixOutputs_andMatrixInput_4_382) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_88 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_382, decoder_decoded_andMatrixOutputs_andMatrixInput_1_382) node decoder_decoded_andMatrixOutputs_hi_hi_hi_322 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_88, decoder_decoded_andMatrixOutputs_andMatrixInput_2_382) node decoder_decoded_andMatrixOutputs_hi_hi_382 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_322, decoder_decoded_andMatrixOutputs_hi_hi_lo_262) node decoder_decoded_andMatrixOutputs_hi_382 = cat(decoder_decoded_andMatrixOutputs_hi_hi_382, decoder_decoded_andMatrixOutputs_hi_lo_374) node _decoder_decoded_andMatrixOutputs_T_382 = cat(decoder_decoded_andMatrixOutputs_hi_382, decoder_decoded_andMatrixOutputs_lo_382) node decoder_decoded_andMatrixOutputs_83_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_382) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_383 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_383 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_383 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_383 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_383 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_381 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_375 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_361 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_323 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_283 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_277 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_271 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_263 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_259 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_235 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_153 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_89 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_63 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_49 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_45 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_153 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_49, decoder_decoded_andMatrixOutputs_andMatrixInput_19_45) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_153, decoder_decoded_andMatrixOutputs_andMatrixInput_16_89) node decoder_decoded_andMatrixOutputs_lo_lo_hi_271 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_17_63) node decoder_decoded_andMatrixOutputs_lo_lo_361 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_271, decoder_decoded_andMatrixOutputs_lo_lo_lo_153) node decoder_decoded_andMatrixOutputs_lo_hi_lo_259 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_259, decoder_decoded_andMatrixOutputs_andMatrixInput_14_235) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_277, decoder_decoded_andMatrixOutputs_andMatrixInput_11_271) node decoder_decoded_andMatrixOutputs_lo_hi_hi_283 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_263) node decoder_decoded_andMatrixOutputs_lo_hi_381 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_283, decoder_decoded_andMatrixOutputs_lo_hi_lo_259) node decoder_decoded_andMatrixOutputs_lo_383 = cat(decoder_decoded_andMatrixOutputs_lo_hi_381, decoder_decoded_andMatrixOutputs_lo_lo_361) node decoder_decoded_andMatrixOutputs_hi_lo_lo_235 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_323, decoder_decoded_andMatrixOutputs_andMatrixInput_9_283) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_381, decoder_decoded_andMatrixOutputs_andMatrixInput_6_375) node decoder_decoded_andMatrixOutputs_hi_lo_hi_277 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_7_361) node decoder_decoded_andMatrixOutputs_hi_lo_375 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_277, decoder_decoded_andMatrixOutputs_hi_lo_lo_235) node decoder_decoded_andMatrixOutputs_hi_hi_lo_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_383, decoder_decoded_andMatrixOutputs_andMatrixInput_4_383) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_89 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_383, decoder_decoded_andMatrixOutputs_andMatrixInput_1_383) node decoder_decoded_andMatrixOutputs_hi_hi_hi_323 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_89, decoder_decoded_andMatrixOutputs_andMatrixInput_2_383) node decoder_decoded_andMatrixOutputs_hi_hi_383 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_323, decoder_decoded_andMatrixOutputs_hi_hi_lo_263) node decoder_decoded_andMatrixOutputs_hi_383 = cat(decoder_decoded_andMatrixOutputs_hi_hi_383, decoder_decoded_andMatrixOutputs_hi_lo_375) node _decoder_decoded_andMatrixOutputs_T_383 = cat(decoder_decoded_andMatrixOutputs_hi_383, decoder_decoded_andMatrixOutputs_lo_383) node decoder_decoded_andMatrixOutputs_33_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_383) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_384 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_384 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_384 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_384 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_384 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_382 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_376 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_362 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_324 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_284 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_278 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_272 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_264 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_260 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_236 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_154 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_90 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_64 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_50 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_46 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_30 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_154 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_46, decoder_decoded_andMatrixOutputs_andMatrixInput_20_30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_90, decoder_decoded_andMatrixOutputs_andMatrixInput_17_64) node decoder_decoded_andMatrixOutputs_lo_lo_hi_272 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_18_50) node decoder_decoded_andMatrixOutputs_lo_lo_362 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_272, decoder_decoded_andMatrixOutputs_lo_lo_lo_154) node decoder_decoded_andMatrixOutputs_lo_hi_lo_260 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_236, decoder_decoded_andMatrixOutputs_andMatrixInput_15_154) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_272, decoder_decoded_andMatrixOutputs_andMatrixInput_12_264) node decoder_decoded_andMatrixOutputs_lo_hi_hi_284 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_13_260) node decoder_decoded_andMatrixOutputs_lo_hi_382 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_284, decoder_decoded_andMatrixOutputs_lo_hi_lo_260) node decoder_decoded_andMatrixOutputs_lo_384 = cat(decoder_decoded_andMatrixOutputs_lo_hi_382, decoder_decoded_andMatrixOutputs_lo_lo_362) node decoder_decoded_andMatrixOutputs_hi_lo_lo_236 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_284, decoder_decoded_andMatrixOutputs_andMatrixInput_10_278) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_376, decoder_decoded_andMatrixOutputs_andMatrixInput_7_362) node decoder_decoded_andMatrixOutputs_hi_lo_hi_278 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_8_324) node decoder_decoded_andMatrixOutputs_hi_lo_376 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_278, decoder_decoded_andMatrixOutputs_hi_lo_lo_236) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_384, decoder_decoded_andMatrixOutputs_andMatrixInput_4_384) node decoder_decoded_andMatrixOutputs_hi_hi_lo_264 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_382) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_90 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_384, decoder_decoded_andMatrixOutputs_andMatrixInput_1_384) node decoder_decoded_andMatrixOutputs_hi_hi_hi_324 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_90, decoder_decoded_andMatrixOutputs_andMatrixInput_2_384) node decoder_decoded_andMatrixOutputs_hi_hi_384 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_324, decoder_decoded_andMatrixOutputs_hi_hi_lo_264) node decoder_decoded_andMatrixOutputs_hi_384 = cat(decoder_decoded_andMatrixOutputs_hi_hi_384, decoder_decoded_andMatrixOutputs_hi_lo_376) node _decoder_decoded_andMatrixOutputs_T_384 = cat(decoder_decoded_andMatrixOutputs_hi_384, decoder_decoded_andMatrixOutputs_lo_384) node decoder_decoded_andMatrixOutputs_84_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_384) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_385 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_385 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_385 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_385 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_385 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_383 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_377 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_363 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_325 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_285 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_279 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_273 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_265 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_261 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_237 = bits(decoder_decoded_plaInput_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_155 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_91 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_65 = bits(decoder_decoded_invInputs_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_51 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_47 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_31 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_155 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_47, decoder_decoded_andMatrixOutputs_andMatrixInput_20_31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_91, decoder_decoded_andMatrixOutputs_andMatrixInput_17_65) node decoder_decoded_andMatrixOutputs_lo_lo_hi_273 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_18_51) node decoder_decoded_andMatrixOutputs_lo_lo_363 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_273, decoder_decoded_andMatrixOutputs_lo_lo_lo_155) node decoder_decoded_andMatrixOutputs_lo_hi_lo_261 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_237, decoder_decoded_andMatrixOutputs_andMatrixInput_15_155) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_273, decoder_decoded_andMatrixOutputs_andMatrixInput_12_265) node decoder_decoded_andMatrixOutputs_lo_hi_hi_285 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_andMatrixInput_13_261) node decoder_decoded_andMatrixOutputs_lo_hi_383 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_285, decoder_decoded_andMatrixOutputs_lo_hi_lo_261) node decoder_decoded_andMatrixOutputs_lo_385 = cat(decoder_decoded_andMatrixOutputs_lo_hi_383, decoder_decoded_andMatrixOutputs_lo_lo_363) node decoder_decoded_andMatrixOutputs_hi_lo_lo_237 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_285, decoder_decoded_andMatrixOutputs_andMatrixInput_10_279) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_377, decoder_decoded_andMatrixOutputs_andMatrixInput_7_363) node decoder_decoded_andMatrixOutputs_hi_lo_hi_279 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_8_325) node decoder_decoded_andMatrixOutputs_hi_lo_377 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_279, decoder_decoded_andMatrixOutputs_hi_lo_lo_237) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_385, decoder_decoded_andMatrixOutputs_andMatrixInput_4_385) node decoder_decoded_andMatrixOutputs_hi_hi_lo_265 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_383) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_91 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_385, decoder_decoded_andMatrixOutputs_andMatrixInput_1_385) node decoder_decoded_andMatrixOutputs_hi_hi_hi_325 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_91, decoder_decoded_andMatrixOutputs_andMatrixInput_2_385) node decoder_decoded_andMatrixOutputs_hi_hi_385 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_325, decoder_decoded_andMatrixOutputs_hi_hi_lo_265) node decoder_decoded_andMatrixOutputs_hi_385 = cat(decoder_decoded_andMatrixOutputs_hi_hi_385, decoder_decoded_andMatrixOutputs_hi_lo_377) node _decoder_decoded_andMatrixOutputs_T_385 = cat(decoder_decoded_andMatrixOutputs_hi_385, decoder_decoded_andMatrixOutputs_lo_385) node decoder_decoded_andMatrixOutputs_40_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_385) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_386 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_386 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_386 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_386 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_386 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_384 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_378 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_364 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_326 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_286 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_280 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_274 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_266 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_262 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_238 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_156 = bits(decoder_decoded_invInputs_1, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_92 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_66 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_52 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_48 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_32 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_156 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_48, decoder_decoded_andMatrixOutputs_andMatrixInput_20_32) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_92, decoder_decoded_andMatrixOutputs_andMatrixInput_17_66) node decoder_decoded_andMatrixOutputs_lo_lo_hi_274 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_18_52) node decoder_decoded_andMatrixOutputs_lo_lo_364 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_274, decoder_decoded_andMatrixOutputs_lo_lo_lo_156) node decoder_decoded_andMatrixOutputs_lo_hi_lo_262 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_238, decoder_decoded_andMatrixOutputs_andMatrixInput_15_156) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_274, decoder_decoded_andMatrixOutputs_andMatrixInput_12_266) node decoder_decoded_andMatrixOutputs_lo_hi_hi_286 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_andMatrixInput_13_262) node decoder_decoded_andMatrixOutputs_lo_hi_384 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_286, decoder_decoded_andMatrixOutputs_lo_hi_lo_262) node decoder_decoded_andMatrixOutputs_lo_386 = cat(decoder_decoded_andMatrixOutputs_lo_hi_384, decoder_decoded_andMatrixOutputs_lo_lo_364) node decoder_decoded_andMatrixOutputs_hi_lo_lo_238 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_286, decoder_decoded_andMatrixOutputs_andMatrixInput_10_280) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_378, decoder_decoded_andMatrixOutputs_andMatrixInput_7_364) node decoder_decoded_andMatrixOutputs_hi_lo_hi_280 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_8_326) node decoder_decoded_andMatrixOutputs_hi_lo_378 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_280, decoder_decoded_andMatrixOutputs_hi_lo_lo_238) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_386, decoder_decoded_andMatrixOutputs_andMatrixInput_4_386) node decoder_decoded_andMatrixOutputs_hi_hi_lo_266 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_384) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_92 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_386, decoder_decoded_andMatrixOutputs_andMatrixInput_1_386) node decoder_decoded_andMatrixOutputs_hi_hi_hi_326 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_92, decoder_decoded_andMatrixOutputs_andMatrixInput_2_386) node decoder_decoded_andMatrixOutputs_hi_hi_386 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_326, decoder_decoded_andMatrixOutputs_hi_hi_lo_266) node decoder_decoded_andMatrixOutputs_hi_386 = cat(decoder_decoded_andMatrixOutputs_hi_hi_386, decoder_decoded_andMatrixOutputs_hi_lo_378) node _decoder_decoded_andMatrixOutputs_T_386 = cat(decoder_decoded_andMatrixOutputs_hi_386, decoder_decoded_andMatrixOutputs_lo_386) node decoder_decoded_andMatrixOutputs_12_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_386) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_387 = bits(decoder_decoded_plaInput_1, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_387 = bits(decoder_decoded_plaInput_1, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_387 = bits(decoder_decoded_invInputs_1, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_387 = bits(decoder_decoded_invInputs_1, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_387 = bits(decoder_decoded_plaInput_1, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_385 = bits(decoder_decoded_invInputs_1, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_379 = bits(decoder_decoded_plaInput_1, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_365 = bits(decoder_decoded_invInputs_1, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_327 = bits(decoder_decoded_invInputs_1, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_287 = bits(decoder_decoded_invInputs_1, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_281 = bits(decoder_decoded_invInputs_1, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_275 = bits(decoder_decoded_invInputs_1, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_267 = bits(decoder_decoded_invInputs_1, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_263 = bits(decoder_decoded_invInputs_1, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_239 = bits(decoder_decoded_invInputs_1, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_157 = bits(decoder_decoded_invInputs_1, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_93 = bits(decoder_decoded_invInputs_1, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_67 = bits(decoder_decoded_plaInput_1, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_53 = bits(decoder_decoded_plaInput_1, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_49 = bits(decoder_decoded_plaInput_1, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_33 = bits(decoder_decoded_plaInput_1, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_157 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_49, decoder_decoded_andMatrixOutputs_andMatrixInput_20_33) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_93, decoder_decoded_andMatrixOutputs_andMatrixInput_17_67) node decoder_decoded_andMatrixOutputs_lo_lo_hi_275 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_18_53) node decoder_decoded_andMatrixOutputs_lo_lo_365 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_275, decoder_decoded_andMatrixOutputs_lo_lo_lo_157) node decoder_decoded_andMatrixOutputs_lo_hi_lo_263 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_239, decoder_decoded_andMatrixOutputs_andMatrixInput_15_157) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_275, decoder_decoded_andMatrixOutputs_andMatrixInput_12_267) node decoder_decoded_andMatrixOutputs_lo_hi_hi_287 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_andMatrixInput_13_263) node decoder_decoded_andMatrixOutputs_lo_hi_385 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_287, decoder_decoded_andMatrixOutputs_lo_hi_lo_263) node decoder_decoded_andMatrixOutputs_lo_387 = cat(decoder_decoded_andMatrixOutputs_lo_hi_385, decoder_decoded_andMatrixOutputs_lo_lo_365) node decoder_decoded_andMatrixOutputs_hi_lo_lo_239 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_287, decoder_decoded_andMatrixOutputs_andMatrixInput_10_281) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_379, decoder_decoded_andMatrixOutputs_andMatrixInput_7_365) node decoder_decoded_andMatrixOutputs_hi_lo_hi_281 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_8_327) node decoder_decoded_andMatrixOutputs_hi_lo_379 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_281, decoder_decoded_andMatrixOutputs_hi_lo_lo_239) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_387, decoder_decoded_andMatrixOutputs_andMatrixInput_4_387) node decoder_decoded_andMatrixOutputs_hi_hi_lo_267 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_385) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_93 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_387, decoder_decoded_andMatrixOutputs_andMatrixInput_1_387) node decoder_decoded_andMatrixOutputs_hi_hi_hi_327 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_93, decoder_decoded_andMatrixOutputs_andMatrixInput_2_387) node decoder_decoded_andMatrixOutputs_hi_hi_387 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_327, decoder_decoded_andMatrixOutputs_hi_hi_lo_267) node decoder_decoded_andMatrixOutputs_hi_387 = cat(decoder_decoded_andMatrixOutputs_hi_hi_387, decoder_decoded_andMatrixOutputs_hi_lo_379) node _decoder_decoded_andMatrixOutputs_T_387 = cat(decoder_decoded_andMatrixOutputs_hi_387, decoder_decoded_andMatrixOutputs_lo_387) node decoder_decoded_andMatrixOutputs_74_2_1 = andr(_decoder_decoded_andMatrixOutputs_T_387) node decoder_decoded_orMatrixOutputs_lo_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_118_2_1, decoder_decoded_andMatrixOutputs_84_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_21 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_40_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_114_2_1, decoder_decoded_andMatrixOutputs_175_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_23 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_127_2_1) node decoder_decoded_orMatrixOutputs_lo_27 = cat(decoder_decoded_orMatrixOutputs_lo_hi_23, decoder_decoded_orMatrixOutputs_lo_lo_21) node decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_85_2_1, decoder_decoded_andMatrixOutputs_10_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_22 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_92_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_148_2_1, decoder_decoded_andMatrixOutputs_75_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_24 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_86_2_1) node decoder_decoded_orMatrixOutputs_hi_29 = cat(decoder_decoded_orMatrixOutputs_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_22) node _decoder_decoded_orMatrixOutputs_T_72 = cat(decoder_decoded_orMatrixOutputs_hi_29, decoder_decoded_orMatrixOutputs_lo_27) node _decoder_decoded_orMatrixOutputs_T_73 = orr(_decoder_decoded_orMatrixOutputs_T_72) node decoder_decoded_orMatrixOutputs_hi_30 = cat(decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_0_2_1) node _decoder_decoded_orMatrixOutputs_T_74 = cat(decoder_decoded_orMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_137_2_1) node _decoder_decoded_orMatrixOutputs_T_75 = orr(_decoder_decoded_orMatrixOutputs_T_74) node _decoder_decoded_orMatrixOutputs_T_76 = orr(decoder_decoded_andMatrixOutputs_117_2_1) node _decoder_decoded_orMatrixOutputs_T_77 = orr(decoder_decoded_andMatrixOutputs_21_2_1) node _decoder_decoded_orMatrixOutputs_T_78 = orr(decoder_decoded_andMatrixOutputs_185_2_1) node _decoder_decoded_orMatrixOutputs_T_79 = orr(decoder_decoded_andMatrixOutputs_155_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_161_2_1, decoder_decoded_andMatrixOutputs_82_2_1) node decoder_decoded_orMatrixOutputs_lo_28 = cat(decoder_decoded_orMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_81_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_155_2_1, decoder_decoded_andMatrixOutputs_58_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_54_2_1, decoder_decoded_andMatrixOutputs_185_2_1) node decoder_decoded_orMatrixOutputs_hi_31 = cat(decoder_decoded_orMatrixOutputs_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_23) node _decoder_decoded_orMatrixOutputs_T_80 = cat(decoder_decoded_orMatrixOutputs_hi_31, decoder_decoded_orMatrixOutputs_lo_28) node _decoder_decoded_orMatrixOutputs_T_81 = orr(_decoder_decoded_orMatrixOutputs_T_80) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_83_2_1, decoder_decoded_andMatrixOutputs_33_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_154_2_1, decoder_decoded_andMatrixOutputs_23_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_100_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_14 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_7) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_56_2_1, decoder_decoded_andMatrixOutputs_79_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_168_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_99_2_1, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_19 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7) node decoder_decoded_orMatrixOutputs_lo_lo_22 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_lo_lo_14) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_68_2_1, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_1_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_51_2_1, decoder_decoded_andMatrixOutputs_174_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_42_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_16 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_7) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_188_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_137_2_1, decoder_decoded_andMatrixOutputs_159_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7) node decoder_decoded_orMatrixOutputs_lo_hi_25 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_lo_hi_lo_16) node decoder_decoded_orMatrixOutputs_lo_29 = cat(decoder_decoded_orMatrixOutputs_lo_hi_25, decoder_decoded_orMatrixOutputs_lo_lo_22) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_41_2_1, decoder_decoded_andMatrixOutputs_8_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_15 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_7) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_155_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_126_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_103_2_1, decoder_decoded_andMatrixOutputs_185_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_17_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7) node decoder_decoded_orMatrixOutputs_hi_lo_24 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_lo_15) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_191_2_1, decoder_decoded_andMatrixOutputs_165_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_121_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_97_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_70_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_17 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_7) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_35_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_190_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_139_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_8) node decoder_decoded_orMatrixOutputs_hi_hi_26 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_hi_lo_17) node decoder_decoded_orMatrixOutputs_hi_32 = cat(decoder_decoded_orMatrixOutputs_hi_hi_26, decoder_decoded_orMatrixOutputs_hi_lo_24) node _decoder_decoded_orMatrixOutputs_T_82 = cat(decoder_decoded_orMatrixOutputs_hi_32, decoder_decoded_orMatrixOutputs_lo_29) node _decoder_decoded_orMatrixOutputs_T_83 = orr(_decoder_decoded_orMatrixOutputs_T_82) node _decoder_decoded_orMatrixOutputs_T_84 = orr(decoder_decoded_andMatrixOutputs_8_2_1) node _decoder_decoded_orMatrixOutputs_T_85 = cat(decoder_decoded_andMatrixOutputs_167_2_1, decoder_decoded_andMatrixOutputs_108_2_1) node _decoder_decoded_orMatrixOutputs_T_86 = orr(_decoder_decoded_orMatrixOutputs_T_85) node decoder_decoded_orMatrixOutputs_lo_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_12_2_1, decoder_decoded_andMatrixOutputs_74_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_116_2_1, decoder_decoded_andMatrixOutputs_156_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_23 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_lo_15) node decoder_decoded_orMatrixOutputs_lo_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_50_2_1, decoder_decoded_andMatrixOutputs_136_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_71_2_1, decoder_decoded_andMatrixOutputs_80_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_22 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_157_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_26 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_22, decoder_decoded_orMatrixOutputs_lo_hi_lo_17) node decoder_decoded_orMatrixOutputs_lo_30 = cat(decoder_decoded_orMatrixOutputs_lo_hi_26, decoder_decoded_orMatrixOutputs_lo_lo_23) node decoder_decoded_orMatrixOutputs_hi_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_46_2_1, decoder_decoded_andMatrixOutputs_114_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_153_2_1, decoder_decoded_andMatrixOutputs_107_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_21 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_187_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_25 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_lo_16) node decoder_decoded_orMatrixOutputs_hi_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_76_2_1, decoder_decoded_andMatrixOutputs_91_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_181_2_1, decoder_decoded_andMatrixOutputs_20_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_22_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_27 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_hi_lo_18) node decoder_decoded_orMatrixOutputs_hi_33 = cat(decoder_decoded_orMatrixOutputs_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_lo_25) node _decoder_decoded_orMatrixOutputs_T_87 = cat(decoder_decoded_orMatrixOutputs_hi_33, decoder_decoded_orMatrixOutputs_lo_30) node _decoder_decoded_orMatrixOutputs_T_88 = orr(_decoder_decoded_orMatrixOutputs_T_87) node _decoder_decoded_orMatrixOutputs_T_89 = orr(decoder_decoded_andMatrixOutputs_181_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_107_2_1, decoder_decoded_andMatrixOutputs_50_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_24 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_136_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_6_2_1, decoder_decoded_andMatrixOutputs_134_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_27 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_153_2_1) node decoder_decoded_orMatrixOutputs_lo_31 = cat(decoder_decoded_orMatrixOutputs_lo_hi_27, decoder_decoded_orMatrixOutputs_lo_lo_24) node decoder_decoded_orMatrixOutputs_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_123_2_1, decoder_decoded_andMatrixOutputs_124_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_26 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_49_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_22_2_1, decoder_decoded_andMatrixOutputs_160_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_181_2_1, decoder_decoded_andMatrixOutputs_20_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_28 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_hi_lo_19) node decoder_decoded_orMatrixOutputs_hi_34 = cat(decoder_decoded_orMatrixOutputs_hi_hi_28, decoder_decoded_orMatrixOutputs_hi_lo_26) node _decoder_decoded_orMatrixOutputs_T_90 = cat(decoder_decoded_orMatrixOutputs_hi_34, decoder_decoded_orMatrixOutputs_lo_31) node _decoder_decoded_orMatrixOutputs_T_91 = orr(_decoder_decoded_orMatrixOutputs_T_90) node decoder_decoded_orMatrixOutputs_lo_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_83_2_1, decoder_decoded_andMatrixOutputs_33_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_23_2_1, decoder_decoded_andMatrixOutputs_100_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_25 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_22, decoder_decoded_orMatrixOutputs_lo_lo_lo_16) node decoder_decoded_orMatrixOutputs_lo_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_50_2_1, decoder_decoded_andMatrixOutputs_136_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_69_2_1, decoder_decoded_andMatrixOutputs_175_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_24 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_130_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_28 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_24, decoder_decoded_orMatrixOutputs_lo_hi_lo_18) node decoder_decoded_orMatrixOutputs_lo_32 = cat(decoder_decoded_orMatrixOutputs_lo_hi_28, decoder_decoded_orMatrixOutputs_lo_lo_25) node decoder_decoded_orMatrixOutputs_hi_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_107_2_1, decoder_decoded_andMatrixOutputs_141_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_6_2_1, decoder_decoded_andMatrixOutputs_134_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_23 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_153_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_27 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_23, decoder_decoded_orMatrixOutputs_hi_lo_lo_17) node decoder_decoded_orMatrixOutputs_hi_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_124_2_1, decoder_decoded_andMatrixOutputs_49_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_181_2_1, decoder_decoded_andMatrixOutputs_20_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_25 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_22_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_29 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_hi_lo_20) node decoder_decoded_orMatrixOutputs_hi_35 = cat(decoder_decoded_orMatrixOutputs_hi_hi_29, decoder_decoded_orMatrixOutputs_hi_lo_27) node _decoder_decoded_orMatrixOutputs_T_92 = cat(decoder_decoded_orMatrixOutputs_hi_35, decoder_decoded_orMatrixOutputs_lo_32) node _decoder_decoded_orMatrixOutputs_T_93 = orr(_decoder_decoded_orMatrixOutputs_T_92) node decoder_decoded_orMatrixOutputs_lo_33 = cat(decoder_decoded_andMatrixOutputs_64_2_1, decoder_decoded_andMatrixOutputs_78_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_128_2_1, decoder_decoded_andMatrixOutputs_166_2_1) node decoder_decoded_orMatrixOutputs_hi_36 = cat(decoder_decoded_orMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_177_2_1) node _decoder_decoded_orMatrixOutputs_T_94 = cat(decoder_decoded_orMatrixOutputs_hi_36, decoder_decoded_orMatrixOutputs_lo_33) node _decoder_decoded_orMatrixOutputs_T_95 = orr(_decoder_decoded_orMatrixOutputs_T_94) node decoder_decoded_orMatrixOutputs_hi_37 = cat(decoder_decoded_andMatrixOutputs_137_2_1, decoder_decoded_andMatrixOutputs_64_2_1) node _decoder_decoded_orMatrixOutputs_T_96 = cat(decoder_decoded_orMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_57_2_1) node _decoder_decoded_orMatrixOutputs_T_97 = orr(_decoder_decoded_orMatrixOutputs_T_96) node decoder_decoded_orMatrixOutputs_lo_34 = cat(decoder_decoded_andMatrixOutputs_82_2_1, decoder_decoded_andMatrixOutputs_171_2_1) node decoder_decoded_orMatrixOutputs_hi_38 = cat(decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_137_2_1) node _decoder_decoded_orMatrixOutputs_T_98 = cat(decoder_decoded_orMatrixOutputs_hi_38, decoder_decoded_orMatrixOutputs_lo_34) node _decoder_decoded_orMatrixOutputs_T_99 = orr(_decoder_decoded_orMatrixOutputs_T_98) node _decoder_decoded_orMatrixOutputs_T_100 = orr(decoder_decoded_andMatrixOutputs_14_2_1) node _decoder_decoded_orMatrixOutputs_T_101 = orr(decoder_decoded_andMatrixOutputs_82_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_73_2_1, decoder_decoded_andMatrixOutputs_110_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_0_2_1) node decoder_decoded_orMatrixOutputs_lo_35 = cat(decoder_decoded_orMatrixOutputs_lo_hi_29, decoder_decoded_orMatrixOutputs_lo_lo_26) node decoder_decoded_orMatrixOutputs_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_140_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_101_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_31 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_39 = cat(decoder_decoded_orMatrixOutputs_hi_hi_31, decoder_decoded_orMatrixOutputs_hi_lo_28) node _decoder_decoded_orMatrixOutputs_T_102 = cat(decoder_decoded_orMatrixOutputs_hi_39, decoder_decoded_orMatrixOutputs_lo_35) node _decoder_decoded_orMatrixOutputs_T_103 = orr(_decoder_decoded_orMatrixOutputs_T_102) node decoder_decoded_orMatrixOutputs_lo_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_142_2_1, decoder_decoded_andMatrixOutputs_47_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_27 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_149_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_169_2_1, decoder_decoded_andMatrixOutputs_138_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_102_2_1, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_30 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_25, decoder_decoded_orMatrixOutputs_lo_hi_lo_19) node decoder_decoded_orMatrixOutputs_lo_36 = cat(decoder_decoded_orMatrixOutputs_lo_hi_30, decoder_decoded_orMatrixOutputs_lo_lo_27) node decoder_decoded_orMatrixOutputs_hi_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_15_2_1, decoder_decoded_andMatrixOutputs_144_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_93_2_1, decoder_decoded_andMatrixOutputs_125_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_29 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_lo_18) node decoder_decoded_orMatrixOutputs_hi_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_55_2_1, decoder_decoded_andMatrixOutputs_179_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_103_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_32 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_hi_lo_21) node decoder_decoded_orMatrixOutputs_hi_40 = cat(decoder_decoded_orMatrixOutputs_hi_hi_32, decoder_decoded_orMatrixOutputs_hi_lo_29) node _decoder_decoded_orMatrixOutputs_T_104 = cat(decoder_decoded_orMatrixOutputs_hi_40, decoder_decoded_orMatrixOutputs_lo_36) node _decoder_decoded_orMatrixOutputs_T_105 = orr(_decoder_decoded_orMatrixOutputs_T_104) node decoder_decoded_orMatrixOutputs_lo_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_63_2_1, decoder_decoded_andMatrixOutputs_142_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_138_2_1, decoder_decoded_andMatrixOutputs_174_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_28 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_24, decoder_decoded_orMatrixOutputs_lo_lo_lo_17) node decoder_decoded_orMatrixOutputs_lo_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_25_2_1, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_44_2_1, decoder_decoded_andMatrixOutputs_3_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_26 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_4_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_31 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_26, decoder_decoded_orMatrixOutputs_lo_hi_lo_20) node decoder_decoded_orMatrixOutputs_lo_37 = cat(decoder_decoded_orMatrixOutputs_lo_hi_31, decoder_decoded_orMatrixOutputs_lo_lo_28) node decoder_decoded_orMatrixOutputs_hi_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_72_2_1, decoder_decoded_andMatrixOutputs_164_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_170_2_1, decoder_decoded_andMatrixOutputs_36_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_30 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_lo_19) node decoder_decoded_orMatrixOutputs_hi_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_111_2_1, decoder_decoded_andMatrixOutputs_172_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_39_2_1, decoder_decoded_andMatrixOutputs_115_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_28 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_163_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_33 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_28, decoder_decoded_orMatrixOutputs_hi_hi_lo_22) node decoder_decoded_orMatrixOutputs_hi_41 = cat(decoder_decoded_orMatrixOutputs_hi_hi_33, decoder_decoded_orMatrixOutputs_hi_lo_30) node _decoder_decoded_orMatrixOutputs_T_106 = cat(decoder_decoded_orMatrixOutputs_hi_41, decoder_decoded_orMatrixOutputs_lo_37) node _decoder_decoded_orMatrixOutputs_T_107 = orr(_decoder_decoded_orMatrixOutputs_T_106) node decoder_decoded_orMatrixOutputs_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_5_2_1, decoder_decoded_andMatrixOutputs_41_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_32 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_8_2_1) node decoder_decoded_orMatrixOutputs_lo_38 = cat(decoder_decoded_orMatrixOutputs_lo_hi_32, decoder_decoded_orMatrixOutputs_lo_lo_29) node decoder_decoded_orMatrixOutputs_hi_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_150_2_1, decoder_decoded_andMatrixOutputs_162_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_31 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_133_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_132_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_34 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_45_2_1) node decoder_decoded_orMatrixOutputs_hi_42 = cat(decoder_decoded_orMatrixOutputs_hi_hi_34, decoder_decoded_orMatrixOutputs_hi_lo_31) node _decoder_decoded_orMatrixOutputs_T_108 = cat(decoder_decoded_orMatrixOutputs_hi_42, decoder_decoded_orMatrixOutputs_lo_38) node _decoder_decoded_orMatrixOutputs_T_109 = orr(_decoder_decoded_orMatrixOutputs_T_108) node decoder_decoded_orMatrixOutputs_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_53_2_1, decoder_decoded_andMatrixOutputs_183_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_147_2_1, decoder_decoded_andMatrixOutputs_178_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_33 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_19_2_1) node decoder_decoded_orMatrixOutputs_lo_39 = cat(decoder_decoded_orMatrixOutputs_lo_hi_33, decoder_decoded_orMatrixOutputs_lo_lo_30) node decoder_decoded_orMatrixOutputs_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_43_2_1, decoder_decoded_andMatrixOutputs_25_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_129_2_1, decoder_decoded_andMatrixOutputs_48_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_35 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_162_2_1) node decoder_decoded_orMatrixOutputs_hi_43 = cat(decoder_decoded_orMatrixOutputs_hi_hi_35, decoder_decoded_orMatrixOutputs_hi_lo_32) node _decoder_decoded_orMatrixOutputs_T_110 = cat(decoder_decoded_orMatrixOutputs_hi_43, decoder_decoded_orMatrixOutputs_lo_39) node _decoder_decoded_orMatrixOutputs_T_111 = orr(_decoder_decoded_orMatrixOutputs_T_110) node decoder_decoded_orMatrixOutputs_lo_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_173_2_1, decoder_decoded_andMatrixOutputs_37_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_31 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_106_2_1, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_104_2_1, decoder_decoded_andMatrixOutputs_186_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_34 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_29, decoder_decoded_orMatrixOutputs_lo_hi_lo_21) node decoder_decoded_orMatrixOutputs_lo_40 = cat(decoder_decoded_orMatrixOutputs_lo_hi_34, decoder_decoded_orMatrixOutputs_lo_lo_31) node decoder_decoded_orMatrixOutputs_hi_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_11_2_1, decoder_decoded_andMatrixOutputs_42_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_33 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_68_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_27_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_43_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_36 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_31, decoder_decoded_orMatrixOutputs_hi_hi_lo_23) node decoder_decoded_orMatrixOutputs_hi_44 = cat(decoder_decoded_orMatrixOutputs_hi_hi_36, decoder_decoded_orMatrixOutputs_hi_lo_33) node _decoder_decoded_orMatrixOutputs_T_112 = cat(decoder_decoded_orMatrixOutputs_hi_44, decoder_decoded_orMatrixOutputs_lo_40) node _decoder_decoded_orMatrixOutputs_T_113 = orr(_decoder_decoded_orMatrixOutputs_T_112) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_61_2_1, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_151_2_1, decoder_decoded_andMatrixOutputs_18_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_18 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_8) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_68_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_135_2_1, decoder_decoded_andMatrixOutputs_188_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_26 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_8) node decoder_decoded_orMatrixOutputs_lo_lo_32 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_26, decoder_decoded_orMatrixOutputs_lo_lo_lo_18) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_34_2_1, decoder_decoded_andMatrixOutputs_180_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_82_2_1, decoder_decoded_andMatrixOutputs_159_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_22 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_8) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_137_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_189_2_1, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_0_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_30 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_8) node decoder_decoded_orMatrixOutputs_lo_hi_35 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_30, decoder_decoded_orMatrixOutputs_lo_hi_lo_22) node decoder_decoded_orMatrixOutputs_lo_41 = cat(decoder_decoded_orMatrixOutputs_lo_hi_35, decoder_decoded_orMatrixOutputs_lo_lo_32) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_162_2_1, decoder_decoded_andMatrixOutputs_41_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_155_2_1, decoder_decoded_andMatrixOutputs_126_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_20 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_8) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_14_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_94_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_16 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_140_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_28 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_8) node decoder_decoded_orMatrixOutputs_hi_lo_34 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_28, decoder_decoded_orMatrixOutputs_hi_lo_lo_20) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_165_2_1, decoder_decoded_andMatrixOutputs_30_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_131_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_24 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_8) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_77_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_32 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_9) node decoder_decoded_orMatrixOutputs_hi_hi_37 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_32, decoder_decoded_orMatrixOutputs_hi_hi_lo_24) node decoder_decoded_orMatrixOutputs_hi_45 = cat(decoder_decoded_orMatrixOutputs_hi_hi_37, decoder_decoded_orMatrixOutputs_hi_lo_34) node _decoder_decoded_orMatrixOutputs_T_114 = cat(decoder_decoded_orMatrixOutputs_hi_45, decoder_decoded_orMatrixOutputs_lo_41) node _decoder_decoded_orMatrixOutputs_T_115 = orr(_decoder_decoded_orMatrixOutputs_T_114) node decoder_decoded_orMatrixOutputs_lo_42 = cat(decoder_decoded_andMatrixOutputs_65_2_1, decoder_decoded_andMatrixOutputs_146_2_1) node decoder_decoded_orMatrixOutputs_hi_46 = cat(decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_165_2_1) node _decoder_decoded_orMatrixOutputs_T_116 = cat(decoder_decoded_orMatrixOutputs_hi_46, decoder_decoded_orMatrixOutputs_lo_42) node _decoder_decoded_orMatrixOutputs_T_117 = orr(_decoder_decoded_orMatrixOutputs_T_116) node _decoder_decoded_orMatrixOutputs_T_118 = cat(decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_165_2_1) node _decoder_decoded_orMatrixOutputs_T_119 = orr(_decoder_decoded_orMatrixOutputs_T_118) node decoder_decoded_orMatrixOutputs_lo_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_99_2_1, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_27 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_1_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_33 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_27, decoder_decoded_orMatrixOutputs_lo_lo_lo_19) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_23 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_120_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_31 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_180_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_36 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_31, decoder_decoded_orMatrixOutputs_lo_hi_lo_23) node decoder_decoded_orMatrixOutputs_lo_43 = cat(decoder_decoded_orMatrixOutputs_lo_hi_36, decoder_decoded_orMatrixOutputs_lo_lo_33) node decoder_decoded_orMatrixOutputs_hi_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_90_2_1, decoder_decoded_andMatrixOutputs_2_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_24_2_1, decoder_decoded_andMatrixOutputs_52_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_29 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_17_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_35 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_29, decoder_decoded_orMatrixOutputs_hi_lo_lo_21) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_191_2_1, decoder_decoded_andMatrixOutputs_26_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_25 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_60_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_33 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_95_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_38 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_33, decoder_decoded_orMatrixOutputs_hi_hi_lo_25) node decoder_decoded_orMatrixOutputs_hi_47 = cat(decoder_decoded_orMatrixOutputs_hi_hi_38, decoder_decoded_orMatrixOutputs_hi_lo_35) node _decoder_decoded_orMatrixOutputs_T_120 = cat(decoder_decoded_orMatrixOutputs_hi_47, decoder_decoded_orMatrixOutputs_lo_43) node _decoder_decoded_orMatrixOutputs_T_121 = orr(_decoder_decoded_orMatrixOutputs_T_120) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_12_2_1, decoder_decoded_andMatrixOutputs_74_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_122_2_1, decoder_decoded_andMatrixOutputs_116_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_156_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_20 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_9) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_1_2_1, decoder_decoded_andMatrixOutputs_99_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_68_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_28 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_9) node decoder_decoded_orMatrixOutputs_lo_lo_34 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_28, decoder_decoded_orMatrixOutputs_lo_lo_lo_20) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_51_2_1, decoder_decoded_andMatrixOutputs_174_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_188_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_24 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_9) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_31_2_1, decoder_decoded_andMatrixOutputs_159_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_137_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_32 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_9) node decoder_decoded_orMatrixOutputs_lo_hi_37 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_32, decoder_decoded_orMatrixOutputs_lo_hi_lo_24) node decoder_decoded_orMatrixOutputs_lo_44 = cat(decoder_decoded_orMatrixOutputs_lo_hi_37, decoder_decoded_orMatrixOutputs_lo_lo_34) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_8_2_1, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_162_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_41_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_22 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_9) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_14_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_184_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_103_2_1, decoder_decoded_andMatrixOutputs_16_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_18 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_140_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_30 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_9) node decoder_decoded_orMatrixOutputs_hi_lo_36 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_30, decoder_decoded_orMatrixOutputs_hi_lo_lo_22) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_121_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_97_2_1, decoder_decoded_andMatrixOutputs_70_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_131_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_26 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_9) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_190_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_7_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_34 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_10) node decoder_decoded_orMatrixOutputs_hi_hi_39 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_34, decoder_decoded_orMatrixOutputs_hi_hi_lo_26) node decoder_decoded_orMatrixOutputs_hi_48 = cat(decoder_decoded_orMatrixOutputs_hi_hi_39, decoder_decoded_orMatrixOutputs_hi_lo_36) node _decoder_decoded_orMatrixOutputs_T_122 = cat(decoder_decoded_orMatrixOutputs_hi_48, decoder_decoded_orMatrixOutputs_lo_44) node _decoder_decoded_orMatrixOutputs_T_123 = orr(_decoder_decoded_orMatrixOutputs_T_122) node decoder_decoded_orMatrixOutputs_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_159_2_1) node decoder_decoded_orMatrixOutputs_lo_45 = cat(decoder_decoded_orMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_182_2_1, decoder_decoded_andMatrixOutputs_165_2_1) node decoder_decoded_orMatrixOutputs_hi_49 = cat(decoder_decoded_orMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_189_2_1) node _decoder_decoded_orMatrixOutputs_T_124 = cat(decoder_decoded_orMatrixOutputs_hi_49, decoder_decoded_orMatrixOutputs_lo_45) node _decoder_decoded_orMatrixOutputs_T_125 = orr(_decoder_decoded_orMatrixOutputs_T_124) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_1_2_1, decoder_decoded_andMatrixOutputs_99_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_21 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_120_2_1, decoder_decoded_andMatrixOutputs_42_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_29 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_35 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_29, decoder_decoded_orMatrixOutputs_lo_lo_lo_21) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_188_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_25 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_2_2_1, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_33 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_39 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_33, decoder_decoded_orMatrixOutputs_lo_hi_lo_25) node decoder_decoded_orMatrixOutputs_lo_46 = cat(decoder_decoded_orMatrixOutputs_lo_hi_39, decoder_decoded_orMatrixOutputs_lo_lo_35) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_140_2_1, decoder_decoded_andMatrixOutputs_17_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_23 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_90_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_60_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_31 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_24_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_37 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_31, decoder_decoded_orMatrixOutputs_hi_lo_lo_23) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_191_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_27 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_165_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_29_2_1, decoder_decoded_andMatrixOutputs_95_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_35 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_11) node decoder_decoded_orMatrixOutputs_hi_hi_41 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_35, decoder_decoded_orMatrixOutputs_hi_hi_lo_27) node decoder_decoded_orMatrixOutputs_hi_50 = cat(decoder_decoded_orMatrixOutputs_hi_hi_41, decoder_decoded_orMatrixOutputs_hi_lo_37) node _decoder_decoded_orMatrixOutputs_T_126 = cat(decoder_decoded_orMatrixOutputs_hi_50, decoder_decoded_orMatrixOutputs_lo_46) node _decoder_decoded_orMatrixOutputs_T_127 = orr(_decoder_decoded_orMatrixOutputs_T_126) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_88_2_1, decoder_decoded_andMatrixOutputs_122_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_1_2_1, decoder_decoded_andMatrixOutputs_99_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_22 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_10) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_142_2_1, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_138_2_1, decoder_decoded_andMatrixOutputs_174_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_30 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_10) node decoder_decoded_orMatrixOutputs_lo_lo_36 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_30, decoder_decoded_orMatrixOutputs_lo_lo_lo_22) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_159_2_1, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_26 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_10) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_146_2_1, decoder_decoded_andMatrixOutputs_41_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_22 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_8_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_34 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_10) node decoder_decoded_orMatrixOutputs_lo_hi_40 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_34, decoder_decoded_orMatrixOutputs_lo_hi_lo_26) node decoder_decoded_orMatrixOutputs_lo_47 = cat(decoder_decoded_orMatrixOutputs_lo_hi_40, decoder_decoded_orMatrixOutputs_lo_lo_36) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_65_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_140_2_1, decoder_decoded_andMatrixOutputs_17_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_24 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_10) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_103_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_131_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_30_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_32 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_10) node decoder_decoded_orMatrixOutputs_hi_lo_38 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_32, decoder_decoded_orMatrixOutputs_hi_lo_lo_24) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_97_2_1, decoder_decoded_andMatrixOutputs_70_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_190_2_1, decoder_decoded_andMatrixOutputs_7_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_28 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_10) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_35_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_22 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_36 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_12) node decoder_decoded_orMatrixOutputs_hi_hi_42 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_36, decoder_decoded_orMatrixOutputs_hi_hi_lo_28) node decoder_decoded_orMatrixOutputs_hi_51 = cat(decoder_decoded_orMatrixOutputs_hi_hi_42, decoder_decoded_orMatrixOutputs_hi_lo_38) node _decoder_decoded_orMatrixOutputs_T_128 = cat(decoder_decoded_orMatrixOutputs_hi_51, decoder_decoded_orMatrixOutputs_lo_47) node _decoder_decoded_orMatrixOutputs_T_129 = orr(_decoder_decoded_orMatrixOutputs_T_128) node decoder_decoded_orMatrixOutputs_lo_48 = cat(decoder_decoded_andMatrixOutputs_67_2_1, decoder_decoded_andMatrixOutputs_62_2_1) node decoder_decoded_orMatrixOutputs_hi_52 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node _decoder_decoded_orMatrixOutputs_T_130 = cat(decoder_decoded_orMatrixOutputs_hi_52, decoder_decoded_orMatrixOutputs_lo_48) node _decoder_decoded_orMatrixOutputs_T_131 = orr(_decoder_decoded_orMatrixOutputs_T_130) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_12_2_1, decoder_decoded_andMatrixOutputs_74_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_122_2_1, decoder_decoded_andMatrixOutputs_116_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_156_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_23 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_11) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_1_2_1, decoder_decoded_andMatrixOutputs_99_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_68_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_17 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_151_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_31 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_11) node decoder_decoded_orMatrixOutputs_lo_lo_37 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_31, decoder_decoded_orMatrixOutputs_lo_lo_lo_23) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_51_2_1, decoder_decoded_andMatrixOutputs_174_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_16 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_188_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_27 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_11) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_31_2_1, decoder_decoded_andMatrixOutputs_159_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_59_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_23 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_137_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_35 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_11) node decoder_decoded_orMatrixOutputs_lo_hi_41 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_35, decoder_decoded_orMatrixOutputs_lo_hi_lo_27) node decoder_decoded_orMatrixOutputs_lo_49 = cat(decoder_decoded_orMatrixOutputs_lo_hi_41, decoder_decoded_orMatrixOutputs_lo_lo_37) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_8_2_1, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_162_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_13 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_41_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_25 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_11) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_14_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_11 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_184_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_103_2_1, decoder_decoded_andMatrixOutputs_16_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_21 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_140_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_33 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_11) node decoder_decoded_orMatrixOutputs_hi_lo_39 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_33, decoder_decoded_orMatrixOutputs_hi_lo_lo_25) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_121_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_97_2_1, decoder_decoded_andMatrixOutputs_70_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_17 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_131_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_29 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_17, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_11) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_190_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_13 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_7_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_23 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_37 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_13) node decoder_decoded_orMatrixOutputs_hi_hi_43 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_37, decoder_decoded_orMatrixOutputs_hi_hi_lo_29) node decoder_decoded_orMatrixOutputs_hi_53 = cat(decoder_decoded_orMatrixOutputs_hi_hi_43, decoder_decoded_orMatrixOutputs_hi_lo_39) node _decoder_decoded_orMatrixOutputs_T_132 = cat(decoder_decoded_orMatrixOutputs_hi_53, decoder_decoded_orMatrixOutputs_lo_49) node _decoder_decoded_orMatrixOutputs_T_133 = orr(_decoder_decoded_orMatrixOutputs_T_132) node decoder_decoded_orMatrixOutputs_lo_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_68_2_1, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_159_2_1, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_32 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_38 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_32, decoder_decoded_orMatrixOutputs_lo_lo_lo_24) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_137_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_28 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_13_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_41_2_1, decoder_decoded_andMatrixOutputs_8_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_36 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_28_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_42 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_36, decoder_decoded_orMatrixOutputs_lo_hi_lo_28) node decoder_decoded_orMatrixOutputs_lo_50 = cat(decoder_decoded_orMatrixOutputs_lo_hi_42, decoder_decoded_orMatrixOutputs_lo_lo_38) node decoder_decoded_orMatrixOutputs_hi_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_162_2_1, decoder_decoded_andMatrixOutputs_87_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_70_2_1, decoder_decoded_andMatrixOutputs_14_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_34 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_126_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_40 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_34, decoder_decoded_orMatrixOutputs_hi_lo_lo_26) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_97_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_30 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_32_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_128_2_1, decoder_decoded_andMatrixOutputs_66_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_38 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_190_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_44 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_38, decoder_decoded_orMatrixOutputs_hi_hi_lo_30) node decoder_decoded_orMatrixOutputs_hi_54 = cat(decoder_decoded_orMatrixOutputs_hi_hi_44, decoder_decoded_orMatrixOutputs_hi_lo_40) node _decoder_decoded_orMatrixOutputs_T_134 = cat(decoder_decoded_orMatrixOutputs_hi_54, decoder_decoded_orMatrixOutputs_lo_50) node _decoder_decoded_orMatrixOutputs_T_135 = orr(_decoder_decoded_orMatrixOutputs_T_134) node _decoder_decoded_orMatrixOutputs_T_136 = orr(decoder_decoded_andMatrixOutputs_191_2_1) node _decoder_decoded_orMatrixOutputs_T_137 = orr(decoder_decoded_andMatrixOutputs_165_2_1) node _decoder_decoded_orMatrixOutputs_T_138 = cat(decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_162_2_1) node _decoder_decoded_orMatrixOutputs_T_139 = orr(_decoder_decoded_orMatrixOutputs_T_138) node decoder_decoded_orMatrixOutputs_lo_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_158_2_1, decoder_decoded_andMatrixOutputs_109_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_136_2_1, decoder_decoded_andMatrixOutputs_192_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_33 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_38_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_39 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_33, decoder_decoded_orMatrixOutputs_lo_lo_lo_25) node decoder_decoded_orMatrixOutputs_lo_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_130_2_1, decoder_decoded_andMatrixOutputs_50_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_141_2_1, decoder_decoded_andMatrixOutputs_69_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_37 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_175_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_43 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_37, decoder_decoded_orMatrixOutputs_lo_hi_lo_29) node decoder_decoded_orMatrixOutputs_lo_51 = cat(decoder_decoded_orMatrixOutputs_lo_hi_43, decoder_decoded_orMatrixOutputs_lo_lo_39) node decoder_decoded_orMatrixOutputs_hi_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_153_2_1, decoder_decoded_andMatrixOutputs_107_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_49_2_1, decoder_decoded_andMatrixOutputs_6_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_35 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_134_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_41 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_35, decoder_decoded_orMatrixOutputs_hi_lo_lo_27) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_176_2_1, decoder_decoded_andMatrixOutputs_193_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_31 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_124_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_181_2_1, decoder_decoded_andMatrixOutputs_20_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_39 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_22_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_45 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_39, decoder_decoded_orMatrixOutputs_hi_hi_lo_31) node decoder_decoded_orMatrixOutputs_hi_55 = cat(decoder_decoded_orMatrixOutputs_hi_hi_45, decoder_decoded_orMatrixOutputs_hi_lo_41) node _decoder_decoded_orMatrixOutputs_T_140 = cat(decoder_decoded_orMatrixOutputs_hi_55, decoder_decoded_orMatrixOutputs_lo_51) node _decoder_decoded_orMatrixOutputs_T_141 = orr(_decoder_decoded_orMatrixOutputs_T_140) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_83_2_1, decoder_decoded_andMatrixOutputs_33_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_113_2_1, decoder_decoded_andMatrixOutputs_105_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_158_2_1, decoder_decoded_andMatrixOutputs_109_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_122_2_1, decoder_decoded_andMatrixOutputs_119_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_lo_26 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_12) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_106_2_1, decoder_decoded_andMatrixOutputs_88_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_104_2_1, decoder_decoded_andMatrixOutputs_186_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_50_2_1, decoder_decoded_andMatrixOutputs_136_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_130_2_1, decoder_decoded_andMatrixOutputs_42_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_68_2_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_20 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_lo_hi_34 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_12) node decoder_decoded_orMatrixOutputs_lo_lo_40 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_34, decoder_decoded_orMatrixOutputs_lo_lo_lo_26) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_69_2_1, decoder_decoded_andMatrixOutputs_175_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_174_2_1, decoder_decoded_andMatrixOutputs_141_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_51_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_18 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_30 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_12) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_159_2_1, decoder_decoded_andMatrixOutputs_34_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_153_2_1, decoder_decoded_andMatrixOutputs_107_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_6_2_1, decoder_decoded_andMatrixOutputs_134_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_110_2_1, decoder_decoded_andMatrixOutputs_124_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_49_2_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_26 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_hi_38 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_26, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_12) node decoder_decoded_orMatrixOutputs_lo_hi_44 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_38, decoder_decoded_orMatrixOutputs_lo_hi_lo_30) node decoder_decoded_orMatrixOutputs_lo_52 = cat(decoder_decoded_orMatrixOutputs_lo_hi_44, decoder_decoded_orMatrixOutputs_lo_lo_40) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_152_2_1, decoder_decoded_andMatrixOutputs_112_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_73_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_0_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_41_2_1, decoder_decoded_andMatrixOutputs_8_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_14 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_lo_28 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_12) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_162_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_155_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_140_2_1, decoder_decoded_andMatrixOutputs_17_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_103_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_94_2_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_24 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_hi_36 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_12) node decoder_decoded_orMatrixOutputs_hi_lo_42 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_36, decoder_decoded_orMatrixOutputs_hi_lo_lo_28) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_89_2_1, decoder_decoded_andMatrixOutputs_30_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_131_2_1, decoder_decoded_andMatrixOutputs_165_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_20_2_1, decoder_decoded_andMatrixOutputs_22_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_70_2_1, decoder_decoded_andMatrixOutputs_145_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_143_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_20 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_32 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_12) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_97_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_190_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_14 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_117_2_1, decoder_decoded_andMatrixOutputs_95_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_29_2_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_26 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_hi_40 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_14) node decoder_decoded_orMatrixOutputs_hi_hi_46 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_40, decoder_decoded_orMatrixOutputs_hi_hi_lo_32) node decoder_decoded_orMatrixOutputs_hi_56 = cat(decoder_decoded_orMatrixOutputs_hi_hi_46, decoder_decoded_orMatrixOutputs_hi_lo_42) node _decoder_decoded_orMatrixOutputs_T_142 = cat(decoder_decoded_orMatrixOutputs_hi_56, decoder_decoded_orMatrixOutputs_lo_52) node _decoder_decoded_orMatrixOutputs_T_143 = orr(_decoder_decoded_orMatrixOutputs_T_142) node decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_75, _decoder_decoded_orMatrixOutputs_T_73) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_78, _decoder_decoded_orMatrixOutputs_T_77) node decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_15 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_76) node decoder_decoded_orMatrixOutputs_lo_lo_lo_27 = cat(decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_13) node decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_81, _decoder_decoded_orMatrixOutputs_T_79) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_11 = cat(_decoder_decoded_orMatrixOutputs_T_86, _decoder_decoded_orMatrixOutputs_T_84) node decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_21 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_11, _decoder_decoded_orMatrixOutputs_T_83) node decoder_decoded_orMatrixOutputs_lo_lo_hi_35 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_13) node decoder_decoded_orMatrixOutputs_lo_lo_41 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_35, decoder_decoded_orMatrixOutputs_lo_lo_lo_27) node decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_89, _decoder_decoded_orMatrixOutputs_T_88) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_95, _decoder_decoded_orMatrixOutputs_T_93) node decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_19 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_91) node decoder_decoded_orMatrixOutputs_lo_hi_lo_31 = cat(decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_13) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_100, _decoder_decoded_orMatrixOutputs_T_99) node decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_13 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_9, _decoder_decoded_orMatrixOutputs_T_97) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_13 = cat(_decoder_decoded_orMatrixOutputs_T_105, _decoder_decoded_orMatrixOutputs_T_103) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_27 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_13, _decoder_decoded_orMatrixOutputs_T_101) node decoder_decoded_orMatrixOutputs_lo_hi_hi_39 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_13) node decoder_decoded_orMatrixOutputs_lo_hi_45 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_39, decoder_decoded_orMatrixOutputs_lo_hi_lo_31) node decoder_decoded_orMatrixOutputs_lo_53 = cat(decoder_decoded_orMatrixOutputs_lo_hi_45, decoder_decoded_orMatrixOutputs_lo_lo_41) node decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_109, _decoder_decoded_orMatrixOutputs_T_107) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_115, _decoder_decoded_orMatrixOutputs_T_113) node decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_15 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_111) node decoder_decoded_orMatrixOutputs_hi_lo_lo_29 = cat(decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_13) node decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_119, _decoder_decoded_orMatrixOutputs_T_117) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_13 = cat(_decoder_decoded_orMatrixOutputs_T_125, _decoder_decoded_orMatrixOutputs_T_123) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_25 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_13, _decoder_decoded_orMatrixOutputs_T_121) node decoder_decoded_orMatrixOutputs_hi_lo_hi_37 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_13) node decoder_decoded_orMatrixOutputs_hi_lo_43 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_37, decoder_decoded_orMatrixOutputs_hi_lo_lo_29) node decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_13 = cat(_decoder_decoded_orMatrixOutputs_T_129, _decoder_decoded_orMatrixOutputs_T_127) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_135, _decoder_decoded_orMatrixOutputs_T_133) node decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_21 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_131) node decoder_decoded_orMatrixOutputs_hi_hi_lo_33 = cat(decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_21, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_13) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_9 = cat(_decoder_decoded_orMatrixOutputs_T_139, _decoder_decoded_orMatrixOutputs_T_137) node decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_15 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_9, _decoder_decoded_orMatrixOutputs_T_136) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_13 = cat(_decoder_decoded_orMatrixOutputs_T_143, _decoder_decoded_orMatrixOutputs_T_141) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_27 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_13, UInt<1>(0h0)) node decoder_decoded_orMatrixOutputs_hi_hi_hi_41 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_15) node decoder_decoded_orMatrixOutputs_hi_hi_47 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_41, decoder_decoded_orMatrixOutputs_hi_hi_lo_33) node decoder_decoded_orMatrixOutputs_hi_57 = cat(decoder_decoded_orMatrixOutputs_hi_hi_47, decoder_decoded_orMatrixOutputs_hi_lo_43) node decoder_decoded_orMatrixOutputs_1 = cat(decoder_decoded_orMatrixOutputs_hi_57, decoder_decoded_orMatrixOutputs_lo_53) node _decoder_decoded_invMatrixOutputs_T_42 = bits(decoder_decoded_orMatrixOutputs_1, 0, 0) node _decoder_decoded_invMatrixOutputs_T_43 = bits(decoder_decoded_orMatrixOutputs_1, 1, 1) node _decoder_decoded_invMatrixOutputs_T_44 = bits(decoder_decoded_orMatrixOutputs_1, 2, 2) node _decoder_decoded_invMatrixOutputs_T_45 = bits(decoder_decoded_orMatrixOutputs_1, 3, 3) node _decoder_decoded_invMatrixOutputs_T_46 = bits(decoder_decoded_orMatrixOutputs_1, 4, 4) node _decoder_decoded_invMatrixOutputs_T_47 = bits(decoder_decoded_orMatrixOutputs_1, 5, 5) node _decoder_decoded_invMatrixOutputs_T_48 = bits(decoder_decoded_orMatrixOutputs_1, 6, 6) node _decoder_decoded_invMatrixOutputs_T_49 = bits(decoder_decoded_orMatrixOutputs_1, 7, 7) node _decoder_decoded_invMatrixOutputs_T_50 = bits(decoder_decoded_orMatrixOutputs_1, 8, 8) node _decoder_decoded_invMatrixOutputs_T_51 = bits(decoder_decoded_orMatrixOutputs_1, 9, 9) node _decoder_decoded_invMatrixOutputs_T_52 = bits(decoder_decoded_orMatrixOutputs_1, 10, 10) node _decoder_decoded_invMatrixOutputs_T_53 = bits(decoder_decoded_orMatrixOutputs_1, 11, 11) node _decoder_decoded_invMatrixOutputs_T_54 = bits(decoder_decoded_orMatrixOutputs_1, 12, 12) node _decoder_decoded_invMatrixOutputs_T_55 = bits(decoder_decoded_orMatrixOutputs_1, 13, 13) node _decoder_decoded_invMatrixOutputs_T_56 = bits(decoder_decoded_orMatrixOutputs_1, 14, 14) node _decoder_decoded_invMatrixOutputs_T_57 = bits(decoder_decoded_orMatrixOutputs_1, 15, 15) node _decoder_decoded_invMatrixOutputs_T_58 = bits(decoder_decoded_orMatrixOutputs_1, 16, 16) node _decoder_decoded_invMatrixOutputs_T_59 = bits(decoder_decoded_orMatrixOutputs_1, 17, 17) node _decoder_decoded_invMatrixOutputs_T_60 = bits(decoder_decoded_orMatrixOutputs_1, 18, 18) node _decoder_decoded_invMatrixOutputs_T_61 = bits(decoder_decoded_orMatrixOutputs_1, 19, 19) node _decoder_decoded_invMatrixOutputs_T_62 = bits(decoder_decoded_orMatrixOutputs_1, 20, 20) node _decoder_decoded_invMatrixOutputs_T_63 = bits(decoder_decoded_orMatrixOutputs_1, 21, 21) node _decoder_decoded_invMatrixOutputs_T_64 = bits(decoder_decoded_orMatrixOutputs_1, 22, 22) node _decoder_decoded_invMatrixOutputs_T_65 = bits(decoder_decoded_orMatrixOutputs_1, 23, 23) node _decoder_decoded_invMatrixOutputs_T_66 = bits(decoder_decoded_orMatrixOutputs_1, 24, 24) node _decoder_decoded_invMatrixOutputs_T_67 = bits(decoder_decoded_orMatrixOutputs_1, 25, 25) node _decoder_decoded_invMatrixOutputs_T_68 = bits(decoder_decoded_orMatrixOutputs_1, 26, 26) node _decoder_decoded_invMatrixOutputs_T_69 = bits(decoder_decoded_orMatrixOutputs_1, 27, 27) node _decoder_decoded_invMatrixOutputs_T_70 = bits(decoder_decoded_orMatrixOutputs_1, 28, 28) node _decoder_decoded_invMatrixOutputs_T_71 = bits(decoder_decoded_orMatrixOutputs_1, 29, 29) node _decoder_decoded_invMatrixOutputs_T_72 = bits(decoder_decoded_orMatrixOutputs_1, 30, 30) node _decoder_decoded_invMatrixOutputs_T_73 = bits(decoder_decoded_orMatrixOutputs_1, 31, 31) node _decoder_decoded_invMatrixOutputs_T_74 = bits(decoder_decoded_orMatrixOutputs_1, 32, 32) node _decoder_decoded_invMatrixOutputs_T_75 = bits(decoder_decoded_orMatrixOutputs_1, 33, 33) node _decoder_decoded_invMatrixOutputs_T_76 = bits(decoder_decoded_orMatrixOutputs_1, 34, 34) node _decoder_decoded_invMatrixOutputs_T_77 = bits(decoder_decoded_orMatrixOutputs_1, 35, 35) node _decoder_decoded_invMatrixOutputs_T_78 = bits(decoder_decoded_orMatrixOutputs_1, 36, 36) node _decoder_decoded_invMatrixOutputs_T_79 = bits(decoder_decoded_orMatrixOutputs_1, 37, 37) node _decoder_decoded_invMatrixOutputs_T_80 = bits(decoder_decoded_orMatrixOutputs_1, 38, 38) node _decoder_decoded_invMatrixOutputs_T_81 = bits(decoder_decoded_orMatrixOutputs_1, 39, 39) node _decoder_decoded_invMatrixOutputs_T_82 = bits(decoder_decoded_orMatrixOutputs_1, 40, 40) node _decoder_decoded_invMatrixOutputs_T_83 = bits(decoder_decoded_orMatrixOutputs_1, 41, 41) node decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_43, _decoder_decoded_invMatrixOutputs_T_42) node decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_46, _decoder_decoded_invMatrixOutputs_T_45) node decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_44) node decoder_decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_1) node decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_48, _decoder_decoded_invMatrixOutputs_T_47) node decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_51, _decoder_decoded_invMatrixOutputs_T_50) node decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_49) node decoder_decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_1) node decoder_decoded_invMatrixOutputs_lo_lo_1 = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_lo_1) node decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_53, _decoder_decoded_invMatrixOutputs_T_52) node decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_56, _decoder_decoded_invMatrixOutputs_T_55) node decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_54) node decoder_decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_1) node decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_59, _decoder_decoded_invMatrixOutputs_T_58) node decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_1, _decoder_decoded_invMatrixOutputs_T_57) node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_62, _decoder_decoded_invMatrixOutputs_T_61) node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_60) node decoder_decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_1) node decoder_decoded_invMatrixOutputs_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_lo_1) node decoder_decoded_invMatrixOutputs_lo_1 = cat(decoder_decoded_invMatrixOutputs_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_1) node decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_64, _decoder_decoded_invMatrixOutputs_T_63) node decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_67, _decoder_decoded_invMatrixOutputs_T_66) node decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_65) node decoder_decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_1) node decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_69, _decoder_decoded_invMatrixOutputs_T_68) node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_72, _decoder_decoded_invMatrixOutputs_T_71) node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_70) node decoder_decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_1) node decoder_decoded_invMatrixOutputs_hi_lo_1 = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_lo_1) node decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoder_decoded_invMatrixOutputs_T_74, _decoder_decoded_invMatrixOutputs_T_73) node decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_77, _decoder_decoded_invMatrixOutputs_T_76) node decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_75) node decoder_decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_1) node decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_80, _decoder_decoded_invMatrixOutputs_T_79) node decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_1, _decoder_decoded_invMatrixOutputs_T_78) node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(_decoder_decoded_invMatrixOutputs_T_83, _decoder_decoded_invMatrixOutputs_T_82) node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_81) node decoder_decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_1) node decoder_decoded_invMatrixOutputs_hi_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_lo_1) node decoder_decoded_invMatrixOutputs_hi_1 = cat(decoder_decoded_invMatrixOutputs_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_1) node decoder_decoded_invMatrixOutputs_1 = cat(decoder_decoded_invMatrixOutputs_hi_1, decoder_decoded_invMatrixOutputs_lo_1) connect decoder_decoded_1, decoder_decoded_invMatrixOutputs_1 connect decoder_decoded_plaInput_1, io.imem.resp[1].bits.inst node decoder_0_1 = bits(decoder_decoded_1, 41, 41) node decoder_1_1 = bits(decoder_decoded_1, 40, 40) node decoder_2_1 = bits(decoder_decoded_1, 39, 39) node decoder_3_1 = bits(decoder_decoded_1, 38, 38) node decoder_4_1 = bits(decoder_decoded_1, 37, 37) node decoder_5_1 = bits(decoder_decoded_1, 36, 36) node decoder_6_1 = bits(decoder_decoded_1, 35, 35) node decoder_7_1 = bits(decoder_decoded_1, 34, 34) node decoder_8_1 = bits(decoder_decoded_1, 33, 31) node decoder_9_1 = bits(decoder_decoded_1, 30, 29) node decoder_10_1 = bits(decoder_decoded_1, 28, 26) node decoder_11_1 = bits(decoder_decoded_1, 25, 25) node decoder_12_1 = bits(decoder_decoded_1, 24, 20) node decoder_13_1 = bits(decoder_decoded_1, 19, 19) node decoder_14_1 = bits(decoder_decoded_1, 18, 14) node decoder_15_1 = bits(decoder_decoded_1, 13, 13) node decoder_16_1 = bits(decoder_decoded_1, 12, 12) node decoder_17_1 = bits(decoder_decoded_1, 11, 11) node decoder_18_1 = bits(decoder_decoded_1, 10, 10) node decoder_19_1 = bits(decoder_decoded_1, 9, 9) node decoder_20_1 = bits(decoder_decoded_1, 8, 8) node decoder_21_1 = bits(decoder_decoded_1, 7, 7) node decoder_22_1 = bits(decoder_decoded_1, 6, 4) node decoder_23_1 = bits(decoder_decoded_1, 3, 3) node decoder_24_1 = bits(decoder_decoded_1, 2, 2) node decoder_25_1 = bits(decoder_decoded_1, 1, 1) node decoder_26_1 = bits(decoder_decoded_1, 0, 0) connect rrd_uops[1].bits.ctrl.legal, decoder_0_1 connect rrd_uops[1].bits.ctrl.fp, decoder_1_1 connect rrd_uops[1].bits.ctrl.rocc, decoder_2_1 connect rrd_uops[1].bits.ctrl.branch, decoder_3_1 connect rrd_uops[1].bits.ctrl.jal, decoder_4_1 connect rrd_uops[1].bits.ctrl.jalr, decoder_5_1 connect rrd_uops[1].bits.ctrl.rxs2, decoder_6_1 connect rrd_uops[1].bits.ctrl.rxs1, decoder_7_1 connect rrd_uops[1].bits.ctrl.sel_alu2, decoder_8_1 connect rrd_uops[1].bits.ctrl.sel_alu1, decoder_9_1 connect rrd_uops[1].bits.ctrl.sel_imm, decoder_10_1 connect rrd_uops[1].bits.ctrl.alu_dw, decoder_11_1 connect rrd_uops[1].bits.ctrl.alu_fn, decoder_12_1 connect rrd_uops[1].bits.ctrl.mem, decoder_13_1 connect rrd_uops[1].bits.ctrl.mem_cmd, decoder_14_1 connect rrd_uops[1].bits.ctrl.rfs1, decoder_15_1 connect rrd_uops[1].bits.ctrl.rfs2, decoder_16_1 connect rrd_uops[1].bits.ctrl.rfs3, decoder_17_1 connect rrd_uops[1].bits.ctrl.wfd, decoder_18_1 connect rrd_uops[1].bits.ctrl.mul, decoder_19_1 connect rrd_uops[1].bits.ctrl.div, decoder_20_1 connect rrd_uops[1].bits.ctrl.wxd, decoder_21_1 connect rrd_uops[1].bits.ctrl.csr, decoder_22_1 connect rrd_uops[1].bits.ctrl.fence_i, decoder_23_1 connect rrd_uops[1].bits.ctrl.fence, decoder_24_1 connect rrd_uops[1].bits.ctrl.amo, decoder_25_1 connect rrd_uops[1].bits.ctrl.dp, decoder_26_1 inst rrd_uops_1_bits_fp_ctrl_fp_decoder of FPUDecoder_1 connect rrd_uops_1_bits_fp_ctrl_fp_decoder.clock, clock connect rrd_uops_1_bits_fp_ctrl_fp_decoder.reset, reset connect rrd_uops_1_bits_fp_ctrl_fp_decoder.io.inst, io.imem.resp[1].bits.inst connect rrd_uops[1].bits.fp_ctrl, rrd_uops_1_bits_fp_ctrl_fp_decoder.io.sigs node _rrd_uops_1_bits_sets_vcfg_T = and(io.imem.resp[1].bits.inst, UInt<32>(0h8000707f)) node _rrd_uops_1_bits_sets_vcfg_T_1 = eq(UInt<15>(0h7057), _rrd_uops_1_bits_sets_vcfg_T) node _rrd_uops_1_bits_sets_vcfg_T_2 = and(io.imem.resp[1].bits.inst, UInt<32>(0hc000707f)) node _rrd_uops_1_bits_sets_vcfg_T_3 = eq(UInt<32>(0hc0007057), _rrd_uops_1_bits_sets_vcfg_T_2) node _rrd_uops_1_bits_sets_vcfg_T_4 = and(io.imem.resp[1].bits.inst, UInt<32>(0hfe00707f)) node _rrd_uops_1_bits_sets_vcfg_T_5 = eq(UInt<32>(0h80007057), _rrd_uops_1_bits_sets_vcfg_T_4) node _rrd_uops_1_bits_sets_vcfg_T_6 = or(_rrd_uops_1_bits_sets_vcfg_T_1, _rrd_uops_1_bits_sets_vcfg_T_3) node _rrd_uops_1_bits_sets_vcfg_T_7 = or(_rrd_uops_1_bits_sets_vcfg_T_6, _rrd_uops_1_bits_sets_vcfg_T_5) node _rrd_uops_1_bits_sets_vcfg_T_8 = and(_rrd_uops_1_bits_sets_vcfg_T_7, UInt<1>(0h0)) connect rrd_uops[1].bits.sets_vcfg, _rrd_uops_1_bits_sets_vcfg_T_8 connect csr.io.decode[0].inst, rrd_uops[0].bits.inst connect csr.io.decode[1].inst, rrd_uops[1].bits.inst wire rrd_illegal_insn : UInt<1>[2] node _illegal_rm_T = bits(rrd_uops[0].bits.inst, 14, 12) node _illegal_rm_T_1 = eq(_illegal_rm_T, UInt<3>(0h5)) node _illegal_rm_T_2 = eq(_illegal_rm_T, UInt<3>(0h6)) node _illegal_rm_T_3 = or(_illegal_rm_T_1, _illegal_rm_T_2) node _illegal_rm_T_4 = bits(rrd_uops[0].bits.inst, 14, 12) node _illegal_rm_T_5 = eq(_illegal_rm_T_4, UInt<3>(0h7)) node _illegal_rm_T_6 = geq(csr.io.fcsr_rm, UInt<3>(0h5)) node _illegal_rm_T_7 = and(_illegal_rm_T_5, _illegal_rm_T_6) node illegal_rm = or(_illegal_rm_T_3, _illegal_rm_T_7) node _fp_illegal_T = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _fp_illegal_T_1 = and(illegal_rm, _fp_illegal_T) node fp_illegal = or(csr.io.decode[0].fp_illegal, _fp_illegal_T_1) node _csr_en_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _csr_en_T_1 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _csr_en_T_2 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _csr_en_T_3 = or(_csr_en_T, _csr_en_T_1) node csr_en = or(_csr_en_T_3, _csr_en_T_2) node _csr_ren_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = bits(rrd_uops[0].bits.inst, 19, 15) node _csr_ren_T_4 = eq(_csr_ren_T_3, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_4) node _csr_wen_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _csr_wen_T_1 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _csr_wen_T_2 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _csr_wen_T_6 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _csr_wen_T_7 = or(_csr_wen_T_5, _csr_wen_T_6) node _csr_wen_T_8 = bits(rrd_uops[0].bits.inst, 19, 15) node _csr_wen_T_9 = eq(_csr_wen_T_8, UInt<1>(0h0)) node _csr_wen_T_10 = and(_csr_wen_T_7, _csr_wen_T_9) node _csr_wen_T_11 = eq(_csr_wen_T_10, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_11) node csr_wen_illegal = and(csr_wen, csr.io.decode[0].write_illegal) node _sfence_T = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node sfence = and(rrd_uops[0].bits.ctrl.mem, _sfence_T) node system_insn = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h4)) node _rrd_uops_0_bits_flush_pipe_T = or(sfence, system_insn) node _rrd_uops_0_bits_flush_pipe_T_1 = and(csr_wen, csr.io.decode[0].write_flush) node _rrd_uops_0_bits_flush_pipe_T_2 = or(_rrd_uops_0_bits_flush_pipe_T, _rrd_uops_0_bits_flush_pipe_T_1) connect rrd_uops[0].bits.flush_pipe, _rrd_uops_0_bits_flush_pipe_T_2 node _rrd_illegal_insn_0_T = eq(rrd_uops[0].bits.ctrl.legal, UInt<1>(0h0)) node _rrd_illegal_insn_0_T_1 = and(rrd_uops[0].bits.ctrl.fp, fp_illegal) node _rrd_illegal_insn_0_T_2 = or(_rrd_illegal_insn_0_T, _rrd_illegal_insn_0_T_1) node _rrd_illegal_insn_0_T_3 = and(rrd_uops[0].bits.ctrl.rocc, csr.io.decode[0].rocc_illegal) node _rrd_illegal_insn_0_T_4 = or(_rrd_illegal_insn_0_T_2, _rrd_illegal_insn_0_T_3) node _rrd_illegal_insn_0_T_5 = or(csr.io.decode[0].vector_illegal, UInt<1>(0h1)) node _rrd_illegal_insn_0_T_6 = and(rrd_uops[0].bits.ctrl.vec, _rrd_illegal_insn_0_T_5) node _rrd_illegal_insn_0_T_7 = or(_rrd_illegal_insn_0_T_4, _rrd_illegal_insn_0_T_6) node _rrd_illegal_insn_0_T_8 = or(csr.io.decode[0].read_illegal, csr_wen_illegal) node _rrd_illegal_insn_0_T_9 = and(csr_en, _rrd_illegal_insn_0_T_8) node _rrd_illegal_insn_0_T_10 = or(_rrd_illegal_insn_0_T_7, _rrd_illegal_insn_0_T_9) node _rrd_illegal_insn_0_T_11 = eq(rrd_uops[0].bits.rvc, UInt<1>(0h0)) node _rrd_illegal_insn_0_T_12 = or(sfence, system_insn) node _rrd_illegal_insn_0_T_13 = and(_rrd_illegal_insn_0_T_12, csr.io.decode[0].system_illegal) node _rrd_illegal_insn_0_T_14 = and(_rrd_illegal_insn_0_T_11, _rrd_illegal_insn_0_T_13) node _rrd_illegal_insn_0_T_15 = or(_rrd_illegal_insn_0_T_10, _rrd_illegal_insn_0_T_14) connect rrd_illegal_insn[0], _rrd_illegal_insn_0_T_15 node _illegal_rm_T_8 = bits(rrd_uops[1].bits.inst, 14, 12) node _illegal_rm_T_9 = eq(_illegal_rm_T_8, UInt<3>(0h5)) node _illegal_rm_T_10 = eq(_illegal_rm_T_8, UInt<3>(0h6)) node _illegal_rm_T_11 = or(_illegal_rm_T_9, _illegal_rm_T_10) node _illegal_rm_T_12 = bits(rrd_uops[1].bits.inst, 14, 12) node _illegal_rm_T_13 = eq(_illegal_rm_T_12, UInt<3>(0h7)) node _illegal_rm_T_14 = geq(csr.io.fcsr_rm, UInt<3>(0h5)) node _illegal_rm_T_15 = and(_illegal_rm_T_13, _illegal_rm_T_14) node illegal_rm_1 = or(_illegal_rm_T_11, _illegal_rm_T_15) node _fp_illegal_T_2 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _fp_illegal_T_3 = and(illegal_rm_1, _fp_illegal_T_2) node fp_illegal_1 = or(csr.io.decode[1].fp_illegal, _fp_illegal_T_3) node _csr_en_T_4 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _csr_en_T_5 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _csr_en_T_6 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _csr_en_T_7 = or(_csr_en_T_4, _csr_en_T_5) node csr_en_1 = or(_csr_en_T_7, _csr_en_T_6) node _csr_ren_T_5 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _csr_ren_T_6 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _csr_ren_T_7 = or(_csr_ren_T_5, _csr_ren_T_6) node _csr_ren_T_8 = bits(rrd_uops[1].bits.inst, 19, 15) node _csr_ren_T_9 = eq(_csr_ren_T_8, UInt<1>(0h0)) node csr_ren_1 = and(_csr_ren_T_7, _csr_ren_T_9) node _csr_wen_T_12 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _csr_wen_T_13 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _csr_wen_T_14 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _csr_wen_T_15 = or(_csr_wen_T_12, _csr_wen_T_13) node _csr_wen_T_16 = or(_csr_wen_T_15, _csr_wen_T_14) node _csr_wen_T_17 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _csr_wen_T_18 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _csr_wen_T_19 = or(_csr_wen_T_17, _csr_wen_T_18) node _csr_wen_T_20 = bits(rrd_uops[1].bits.inst, 19, 15) node _csr_wen_T_21 = eq(_csr_wen_T_20, UInt<1>(0h0)) node _csr_wen_T_22 = and(_csr_wen_T_19, _csr_wen_T_21) node _csr_wen_T_23 = eq(_csr_wen_T_22, UInt<1>(0h0)) node csr_wen_1 = and(_csr_wen_T_16, _csr_wen_T_23) node csr_wen_illegal_1 = and(csr_wen_1, csr.io.decode[1].write_illegal) node _sfence_T_1 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node sfence_1 = and(rrd_uops[1].bits.ctrl.mem, _sfence_T_1) node system_insn_1 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h4)) node _rrd_uops_1_bits_flush_pipe_T = or(sfence_1, system_insn_1) node _rrd_uops_1_bits_flush_pipe_T_1 = and(csr_wen_1, csr.io.decode[1].write_flush) node _rrd_uops_1_bits_flush_pipe_T_2 = or(_rrd_uops_1_bits_flush_pipe_T, _rrd_uops_1_bits_flush_pipe_T_1) connect rrd_uops[1].bits.flush_pipe, _rrd_uops_1_bits_flush_pipe_T_2 node _rrd_illegal_insn_1_T = eq(rrd_uops[1].bits.ctrl.legal, UInt<1>(0h0)) node _rrd_illegal_insn_1_T_1 = and(rrd_uops[1].bits.ctrl.fp, fp_illegal_1) node _rrd_illegal_insn_1_T_2 = or(_rrd_illegal_insn_1_T, _rrd_illegal_insn_1_T_1) node _rrd_illegal_insn_1_T_3 = and(rrd_uops[1].bits.ctrl.rocc, csr.io.decode[1].rocc_illegal) node _rrd_illegal_insn_1_T_4 = or(_rrd_illegal_insn_1_T_2, _rrd_illegal_insn_1_T_3) node _rrd_illegal_insn_1_T_5 = or(csr.io.decode[0].vector_illegal, UInt<1>(0h1)) node _rrd_illegal_insn_1_T_6 = and(rrd_uops[1].bits.ctrl.vec, _rrd_illegal_insn_1_T_5) node _rrd_illegal_insn_1_T_7 = or(_rrd_illegal_insn_1_T_4, _rrd_illegal_insn_1_T_6) node _rrd_illegal_insn_1_T_8 = or(csr.io.decode[1].read_illegal, csr_wen_illegal_1) node _rrd_illegal_insn_1_T_9 = and(csr_en_1, _rrd_illegal_insn_1_T_8) node _rrd_illegal_insn_1_T_10 = or(_rrd_illegal_insn_1_T_7, _rrd_illegal_insn_1_T_9) node _rrd_illegal_insn_1_T_11 = eq(rrd_uops[1].bits.rvc, UInt<1>(0h0)) node _rrd_illegal_insn_1_T_12 = or(sfence_1, system_insn_1) node _rrd_illegal_insn_1_T_13 = and(_rrd_illegal_insn_1_T_12, csr.io.decode[1].system_illegal) node _rrd_illegal_insn_1_T_14 = and(_rrd_illegal_insn_1_T_11, _rrd_illegal_insn_1_T_13) node _rrd_illegal_insn_1_T_15 = or(_rrd_illegal_insn_1_T_10, _rrd_illegal_insn_1_T_14) connect rrd_illegal_insn[1], _rrd_illegal_insn_1_T_15 node _T_19 = or(csr.io.interrupt, io.imem.resp[0].bits.xcpt) node xcpt = or(_T_19, rrd_illegal_insn[0]) node _T_20 = mux(io.imem.resp[0].bits.xcpt, io.imem.resp[0].bits.xcpt_cause, UInt<2>(0h2)) node cause = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_20) connect rrd_uops[0].bits.xcpt, xcpt connect rrd_uops[0].bits.xcpt_cause, cause when xcpt : connect rrd_uops[0].bits.ctrl.alu_fn, UInt<1>(0h0) connect rrd_uops[0].bits.ctrl.alu_dw, UInt<1>(0h1) connect rrd_uops[0].bits.ctrl.sel_alu1, UInt<2>(0h1) connect rrd_uops[0].bits.ctrl.sel_alu2, UInt<3>(0h0) when io.imem.resp[0].bits.xcpt : connect rrd_uops[0].bits.ctrl.sel_alu1, UInt<2>(0h2) node _rrd_uops_0_bits_ctrl_sel_alu2_T = mux(io.imem.resp[0].bits.edge_inst, UInt<3>(0h1), UInt<3>(0h0)) connect rrd_uops[0].bits.ctrl.sel_alu2, _rrd_uops_0_bits_ctrl_sel_alu2_T when io.imem.resp[0].bits.edge_inst : connect ex_uops_reg[0].bits.rvc, UInt<1>(0h1) node _T_21 = or(csr.io.interrupt, io.imem.resp[1].bits.xcpt) node xcpt_1 = or(_T_21, rrd_illegal_insn[1]) node _T_22 = mux(io.imem.resp[1].bits.xcpt, io.imem.resp[1].bits.xcpt_cause, UInt<2>(0h2)) node cause_1 = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_22) connect rrd_uops[1].bits.xcpt, xcpt_1 connect rrd_uops[1].bits.xcpt_cause, cause_1 when xcpt_1 : connect rrd_uops[1].bits.ctrl.alu_fn, UInt<1>(0h0) connect rrd_uops[1].bits.ctrl.alu_dw, UInt<1>(0h1) connect rrd_uops[1].bits.ctrl.sel_alu1, UInt<2>(0h1) connect rrd_uops[1].bits.ctrl.sel_alu2, UInt<3>(0h0) when io.imem.resp[1].bits.xcpt : connect rrd_uops[1].bits.ctrl.sel_alu1, UInt<2>(0h2) node _rrd_uops_1_bits_ctrl_sel_alu2_T = mux(io.imem.resp[1].bits.edge_inst, UInt<3>(0h1), UInt<3>(0h0)) connect rrd_uops[1].bits.ctrl.sel_alu2, _rrd_uops_1_bits_ctrl_sel_alu2_T when io.imem.resp[1].bits.edge_inst : connect ex_uops_reg[1].bits.rvc, UInt<1>(0h1) node _io_imem_resp_0_ready_T = eq(rrd_stall[0], UInt<1>(0h0)) connect io.imem.resp[0].ready, _io_imem_resp_0_ready_T node _io_imem_resp_1_ready_T = eq(rrd_stall[1], UInt<1>(0h0)) connect io.imem.resp[1].ready, _io_imem_resp_1_ready_T reg iregfile : UInt<64>[32], clock reg isboard : UInt<1>[32], clock wire _isboard_clear_WIRE : UInt<1>[32] connect _isboard_clear_WIRE[0], UInt<1>(0h0) connect _isboard_clear_WIRE[1], UInt<1>(0h0) connect _isboard_clear_WIRE[2], UInt<1>(0h0) connect _isboard_clear_WIRE[3], UInt<1>(0h0) connect _isboard_clear_WIRE[4], UInt<1>(0h0) connect _isboard_clear_WIRE[5], UInt<1>(0h0) connect _isboard_clear_WIRE[6], UInt<1>(0h0) connect _isboard_clear_WIRE[7], UInt<1>(0h0) connect _isboard_clear_WIRE[8], UInt<1>(0h0) connect _isboard_clear_WIRE[9], UInt<1>(0h0) connect _isboard_clear_WIRE[10], UInt<1>(0h0) connect _isboard_clear_WIRE[11], UInt<1>(0h0) connect _isboard_clear_WIRE[12], UInt<1>(0h0) connect _isboard_clear_WIRE[13], UInt<1>(0h0) connect _isboard_clear_WIRE[14], UInt<1>(0h0) connect _isboard_clear_WIRE[15], UInt<1>(0h0) connect _isboard_clear_WIRE[16], UInt<1>(0h0) connect _isboard_clear_WIRE[17], UInt<1>(0h0) connect _isboard_clear_WIRE[18], UInt<1>(0h0) connect _isboard_clear_WIRE[19], UInt<1>(0h0) connect _isboard_clear_WIRE[20], UInt<1>(0h0) connect _isboard_clear_WIRE[21], UInt<1>(0h0) connect _isboard_clear_WIRE[22], UInt<1>(0h0) connect _isboard_clear_WIRE[23], UInt<1>(0h0) connect _isboard_clear_WIRE[24], UInt<1>(0h0) connect _isboard_clear_WIRE[25], UInt<1>(0h0) connect _isboard_clear_WIRE[26], UInt<1>(0h0) connect _isboard_clear_WIRE[27], UInt<1>(0h0) connect _isboard_clear_WIRE[28], UInt<1>(0h0) connect _isboard_clear_WIRE[29], UInt<1>(0h0) connect _isboard_clear_WIRE[30], UInt<1>(0h0) connect _isboard_clear_WIRE[31], UInt<1>(0h0) wire isboard_clear : UInt<1>[32] connect isboard_clear, _isboard_clear_WIRE wire _isboard_set_WIRE : UInt<1>[32] connect _isboard_set_WIRE[0], UInt<1>(0h0) connect _isboard_set_WIRE[1], UInt<1>(0h0) connect _isboard_set_WIRE[2], UInt<1>(0h0) connect _isboard_set_WIRE[3], UInt<1>(0h0) connect _isboard_set_WIRE[4], UInt<1>(0h0) connect _isboard_set_WIRE[5], UInt<1>(0h0) connect _isboard_set_WIRE[6], UInt<1>(0h0) connect _isboard_set_WIRE[7], UInt<1>(0h0) connect _isboard_set_WIRE[8], UInt<1>(0h0) connect _isboard_set_WIRE[9], UInt<1>(0h0) connect _isboard_set_WIRE[10], UInt<1>(0h0) connect _isboard_set_WIRE[11], UInt<1>(0h0) connect _isboard_set_WIRE[12], UInt<1>(0h0) connect _isboard_set_WIRE[13], UInt<1>(0h0) connect _isboard_set_WIRE[14], UInt<1>(0h0) connect _isboard_set_WIRE[15], UInt<1>(0h0) connect _isboard_set_WIRE[16], UInt<1>(0h0) connect _isboard_set_WIRE[17], UInt<1>(0h0) connect _isboard_set_WIRE[18], UInt<1>(0h0) connect _isboard_set_WIRE[19], UInt<1>(0h0) connect _isboard_set_WIRE[20], UInt<1>(0h0) connect _isboard_set_WIRE[21], UInt<1>(0h0) connect _isboard_set_WIRE[22], UInt<1>(0h0) connect _isboard_set_WIRE[23], UInt<1>(0h0) connect _isboard_set_WIRE[24], UInt<1>(0h0) connect _isboard_set_WIRE[25], UInt<1>(0h0) connect _isboard_set_WIRE[26], UInt<1>(0h0) connect _isboard_set_WIRE[27], UInt<1>(0h0) connect _isboard_set_WIRE[28], UInt<1>(0h0) connect _isboard_set_WIRE[29], UInt<1>(0h0) connect _isboard_set_WIRE[30], UInt<1>(0h0) connect _isboard_set_WIRE[31], UInt<1>(0h0) wire isboard_set : UInt<1>[32] connect isboard_set, _isboard_set_WIRE node _isboard_0_T = eq(isboard_clear[0], UInt<1>(0h0)) node _isboard_0_T_1 = and(isboard[0], _isboard_0_T) node _isboard_0_T_2 = or(_isboard_0_T_1, isboard_set[0]) connect isboard[0], _isboard_0_T_2 node _isboard_1_T = eq(isboard_clear[1], UInt<1>(0h0)) node _isboard_1_T_1 = and(isboard[1], _isboard_1_T) node _isboard_1_T_2 = or(_isboard_1_T_1, isboard_set[1]) connect isboard[1], _isboard_1_T_2 node _isboard_2_T = eq(isboard_clear[2], UInt<1>(0h0)) node _isboard_2_T_1 = and(isboard[2], _isboard_2_T) node _isboard_2_T_2 = or(_isboard_2_T_1, isboard_set[2]) connect isboard[2], _isboard_2_T_2 node _isboard_3_T = eq(isboard_clear[3], UInt<1>(0h0)) node _isboard_3_T_1 = and(isboard[3], _isboard_3_T) node _isboard_3_T_2 = or(_isboard_3_T_1, isboard_set[3]) connect isboard[3], _isboard_3_T_2 node _isboard_4_T = eq(isboard_clear[4], UInt<1>(0h0)) node _isboard_4_T_1 = and(isboard[4], _isboard_4_T) node _isboard_4_T_2 = or(_isboard_4_T_1, isboard_set[4]) connect isboard[4], _isboard_4_T_2 node _isboard_5_T = eq(isboard_clear[5], UInt<1>(0h0)) node _isboard_5_T_1 = and(isboard[5], _isboard_5_T) node _isboard_5_T_2 = or(_isboard_5_T_1, isboard_set[5]) connect isboard[5], _isboard_5_T_2 node _isboard_6_T = eq(isboard_clear[6], UInt<1>(0h0)) node _isboard_6_T_1 = and(isboard[6], _isboard_6_T) node _isboard_6_T_2 = or(_isboard_6_T_1, isboard_set[6]) connect isboard[6], _isboard_6_T_2 node _isboard_7_T = eq(isboard_clear[7], UInt<1>(0h0)) node _isboard_7_T_1 = and(isboard[7], _isboard_7_T) node _isboard_7_T_2 = or(_isboard_7_T_1, isboard_set[7]) connect isboard[7], _isboard_7_T_2 node _isboard_8_T = eq(isboard_clear[8], UInt<1>(0h0)) node _isboard_8_T_1 = and(isboard[8], _isboard_8_T) node _isboard_8_T_2 = or(_isboard_8_T_1, isboard_set[8]) connect isboard[8], _isboard_8_T_2 node _isboard_9_T = eq(isboard_clear[9], UInt<1>(0h0)) node _isboard_9_T_1 = and(isboard[9], _isboard_9_T) node _isboard_9_T_2 = or(_isboard_9_T_1, isboard_set[9]) connect isboard[9], _isboard_9_T_2 node _isboard_10_T = eq(isboard_clear[10], UInt<1>(0h0)) node _isboard_10_T_1 = and(isboard[10], _isboard_10_T) node _isboard_10_T_2 = or(_isboard_10_T_1, isboard_set[10]) connect isboard[10], _isboard_10_T_2 node _isboard_11_T = eq(isboard_clear[11], UInt<1>(0h0)) node _isboard_11_T_1 = and(isboard[11], _isboard_11_T) node _isboard_11_T_2 = or(_isboard_11_T_1, isboard_set[11]) connect isboard[11], _isboard_11_T_2 node _isboard_12_T = eq(isboard_clear[12], UInt<1>(0h0)) node _isboard_12_T_1 = and(isboard[12], _isboard_12_T) node _isboard_12_T_2 = or(_isboard_12_T_1, isboard_set[12]) connect isboard[12], _isboard_12_T_2 node _isboard_13_T = eq(isboard_clear[13], UInt<1>(0h0)) node _isboard_13_T_1 = and(isboard[13], _isboard_13_T) node _isboard_13_T_2 = or(_isboard_13_T_1, isboard_set[13]) connect isboard[13], _isboard_13_T_2 node _isboard_14_T = eq(isboard_clear[14], UInt<1>(0h0)) node _isboard_14_T_1 = and(isboard[14], _isboard_14_T) node _isboard_14_T_2 = or(_isboard_14_T_1, isboard_set[14]) connect isboard[14], _isboard_14_T_2 node _isboard_15_T = eq(isboard_clear[15], UInt<1>(0h0)) node _isboard_15_T_1 = and(isboard[15], _isboard_15_T) node _isboard_15_T_2 = or(_isboard_15_T_1, isboard_set[15]) connect isboard[15], _isboard_15_T_2 node _isboard_16_T = eq(isboard_clear[16], UInt<1>(0h0)) node _isboard_16_T_1 = and(isboard[16], _isboard_16_T) node _isboard_16_T_2 = or(_isboard_16_T_1, isboard_set[16]) connect isboard[16], _isboard_16_T_2 node _isboard_17_T = eq(isboard_clear[17], UInt<1>(0h0)) node _isboard_17_T_1 = and(isboard[17], _isboard_17_T) node _isboard_17_T_2 = or(_isboard_17_T_1, isboard_set[17]) connect isboard[17], _isboard_17_T_2 node _isboard_18_T = eq(isboard_clear[18], UInt<1>(0h0)) node _isboard_18_T_1 = and(isboard[18], _isboard_18_T) node _isboard_18_T_2 = or(_isboard_18_T_1, isboard_set[18]) connect isboard[18], _isboard_18_T_2 node _isboard_19_T = eq(isboard_clear[19], UInt<1>(0h0)) node _isboard_19_T_1 = and(isboard[19], _isboard_19_T) node _isboard_19_T_2 = or(_isboard_19_T_1, isboard_set[19]) connect isboard[19], _isboard_19_T_2 node _isboard_20_T = eq(isboard_clear[20], UInt<1>(0h0)) node _isboard_20_T_1 = and(isboard[20], _isboard_20_T) node _isboard_20_T_2 = or(_isboard_20_T_1, isboard_set[20]) connect isboard[20], _isboard_20_T_2 node _isboard_21_T = eq(isboard_clear[21], UInt<1>(0h0)) node _isboard_21_T_1 = and(isboard[21], _isboard_21_T) node _isboard_21_T_2 = or(_isboard_21_T_1, isboard_set[21]) connect isboard[21], _isboard_21_T_2 node _isboard_22_T = eq(isboard_clear[22], UInt<1>(0h0)) node _isboard_22_T_1 = and(isboard[22], _isboard_22_T) node _isboard_22_T_2 = or(_isboard_22_T_1, isboard_set[22]) connect isboard[22], _isboard_22_T_2 node _isboard_23_T = eq(isboard_clear[23], UInt<1>(0h0)) node _isboard_23_T_1 = and(isboard[23], _isboard_23_T) node _isboard_23_T_2 = or(_isboard_23_T_1, isboard_set[23]) connect isboard[23], _isboard_23_T_2 node _isboard_24_T = eq(isboard_clear[24], UInt<1>(0h0)) node _isboard_24_T_1 = and(isboard[24], _isboard_24_T) node _isboard_24_T_2 = or(_isboard_24_T_1, isboard_set[24]) connect isboard[24], _isboard_24_T_2 node _isboard_25_T = eq(isboard_clear[25], UInt<1>(0h0)) node _isboard_25_T_1 = and(isboard[25], _isboard_25_T) node _isboard_25_T_2 = or(_isboard_25_T_1, isboard_set[25]) connect isboard[25], _isboard_25_T_2 node _isboard_26_T = eq(isboard_clear[26], UInt<1>(0h0)) node _isboard_26_T_1 = and(isboard[26], _isboard_26_T) node _isboard_26_T_2 = or(_isboard_26_T_1, isboard_set[26]) connect isboard[26], _isboard_26_T_2 node _isboard_27_T = eq(isboard_clear[27], UInt<1>(0h0)) node _isboard_27_T_1 = and(isboard[27], _isboard_27_T) node _isboard_27_T_2 = or(_isboard_27_T_1, isboard_set[27]) connect isboard[27], _isboard_27_T_2 node _isboard_28_T = eq(isboard_clear[28], UInt<1>(0h0)) node _isboard_28_T_1 = and(isboard[28], _isboard_28_T) node _isboard_28_T_2 = or(_isboard_28_T_1, isboard_set[28]) connect isboard[28], _isboard_28_T_2 node _isboard_29_T = eq(isboard_clear[29], UInt<1>(0h0)) node _isboard_29_T_1 = and(isboard[29], _isboard_29_T) node _isboard_29_T_2 = or(_isboard_29_T_1, isboard_set[29]) connect isboard[29], _isboard_29_T_2 node _isboard_30_T = eq(isboard_clear[30], UInt<1>(0h0)) node _isboard_30_T_1 = and(isboard[30], _isboard_30_T) node _isboard_30_T_2 = or(_isboard_30_T_1, isboard_set[30]) connect isboard[30], _isboard_30_T_2 node _isboard_31_T = eq(isboard_clear[31], UInt<1>(0h0)) node _isboard_31_T_1 = and(isboard[31], _isboard_31_T) node _isboard_31_T_2 = or(_isboard_31_T_1, isboard_set[31]) connect isboard[31], _isboard_31_T_2 connect isboard[0], UInt<1>(0h1) node _isboard_bsy_T = and(isboard[0], isboard[1]) node _isboard_bsy_T_1 = and(_isboard_bsy_T, isboard[2]) node _isboard_bsy_T_2 = and(_isboard_bsy_T_1, isboard[3]) node _isboard_bsy_T_3 = and(_isboard_bsy_T_2, isboard[4]) node _isboard_bsy_T_4 = and(_isboard_bsy_T_3, isboard[5]) node _isboard_bsy_T_5 = and(_isboard_bsy_T_4, isboard[6]) node _isboard_bsy_T_6 = and(_isboard_bsy_T_5, isboard[7]) node _isboard_bsy_T_7 = and(_isboard_bsy_T_6, isboard[8]) node _isboard_bsy_T_8 = and(_isboard_bsy_T_7, isboard[9]) node _isboard_bsy_T_9 = and(_isboard_bsy_T_8, isboard[10]) node _isboard_bsy_T_10 = and(_isboard_bsy_T_9, isboard[11]) node _isboard_bsy_T_11 = and(_isboard_bsy_T_10, isboard[12]) node _isboard_bsy_T_12 = and(_isboard_bsy_T_11, isboard[13]) node _isboard_bsy_T_13 = and(_isboard_bsy_T_12, isboard[14]) node _isboard_bsy_T_14 = and(_isboard_bsy_T_13, isboard[15]) node _isboard_bsy_T_15 = and(_isboard_bsy_T_14, isboard[16]) node _isboard_bsy_T_16 = and(_isboard_bsy_T_15, isboard[17]) node _isboard_bsy_T_17 = and(_isboard_bsy_T_16, isboard[18]) node _isboard_bsy_T_18 = and(_isboard_bsy_T_17, isboard[19]) node _isboard_bsy_T_19 = and(_isboard_bsy_T_18, isboard[20]) node _isboard_bsy_T_20 = and(_isboard_bsy_T_19, isboard[21]) node _isboard_bsy_T_21 = and(_isboard_bsy_T_20, isboard[22]) node _isboard_bsy_T_22 = and(_isboard_bsy_T_21, isboard[23]) node _isboard_bsy_T_23 = and(_isboard_bsy_T_22, isboard[24]) node _isboard_bsy_T_24 = and(_isboard_bsy_T_23, isboard[25]) node _isboard_bsy_T_25 = and(_isboard_bsy_T_24, isboard[26]) node _isboard_bsy_T_26 = and(_isboard_bsy_T_25, isboard[27]) node _isboard_bsy_T_27 = and(_isboard_bsy_T_26, isboard[28]) node _isboard_bsy_T_28 = and(_isboard_bsy_T_27, isboard[29]) node _isboard_bsy_T_29 = and(_isboard_bsy_T_28, isboard[30]) node _isboard_bsy_T_30 = and(_isboard_bsy_T_29, isboard[31]) node isboard_bsy = eq(_isboard_bsy_T_30, UInt<1>(0h0)) node _T_23 = asUInt(reset) when _T_23 : connect isboard[0], UInt<1>(0h1) connect isboard[1], UInt<1>(0h1) connect isboard[2], UInt<1>(0h1) connect isboard[3], UInt<1>(0h1) connect isboard[4], UInt<1>(0h1) connect isboard[5], UInt<1>(0h1) connect isboard[6], UInt<1>(0h1) connect isboard[7], UInt<1>(0h1) connect isboard[8], UInt<1>(0h1) connect isboard[9], UInt<1>(0h1) connect isboard[10], UInt<1>(0h1) connect isboard[11], UInt<1>(0h1) connect isboard[12], UInt<1>(0h1) connect isboard[13], UInt<1>(0h1) connect isboard[14], UInt<1>(0h1) connect isboard[15], UInt<1>(0h1) connect isboard[16], UInt<1>(0h1) connect isboard[17], UInt<1>(0h1) connect isboard[18], UInt<1>(0h1) connect isboard[19], UInt<1>(0h1) connect isboard[20], UInt<1>(0h1) connect isboard[21], UInt<1>(0h1) connect isboard[22], UInt<1>(0h1) connect isboard[23], UInt<1>(0h1) connect isboard[24], UInt<1>(0h1) connect isboard[25], UInt<1>(0h1) connect isboard[26], UInt<1>(0h1) connect isboard[27], UInt<1>(0h1) connect isboard[28], UInt<1>(0h1) connect isboard[29], UInt<1>(0h1) connect isboard[30], UInt<1>(0h1) connect isboard[31], UInt<1>(0h1) wire rrd_stall_data : UInt<1>[2] wire rrd_irf_writes : { valid : UInt<1>, bits : UInt<5>}[2] node _rrd_p0_can_forward_x_to_m_T = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_1 = and(rrd_uops[0].bits.ctrl.wxd, _rrd_p0_can_forward_x_to_m_T) node _rrd_p0_can_forward_x_to_m_T_2 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_3 = and(_rrd_p0_can_forward_x_to_m_T_1, _rrd_p0_can_forward_x_to_m_T_2) node _rrd_p0_can_forward_x_to_m_T_4 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_5 = and(_rrd_p0_can_forward_x_to_m_T_3, _rrd_p0_can_forward_x_to_m_T_4) node _rrd_p0_can_forward_x_to_m_T_6 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rrd_p0_can_forward_x_to_m_T_7 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rrd_p0_can_forward_x_to_m_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rrd_p0_can_forward_x_to_m_T_9 = or(_rrd_p0_can_forward_x_to_m_T_6, _rrd_p0_can_forward_x_to_m_T_7) node _rrd_p0_can_forward_x_to_m_T_10 = or(_rrd_p0_can_forward_x_to_m_T_9, _rrd_p0_can_forward_x_to_m_T_8) node _rrd_p0_can_forward_x_to_m_T_11 = eq(_rrd_p0_can_forward_x_to_m_T_10, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_12 = and(_rrd_p0_can_forward_x_to_m_T_5, _rrd_p0_can_forward_x_to_m_T_11) node _rrd_p0_can_forward_x_to_m_T_13 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_14 = and(_rrd_p0_can_forward_x_to_m_T_12, _rrd_p0_can_forward_x_to_m_T_13) node _rrd_p0_can_forward_x_to_m_T_15 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_16 = and(_rrd_p0_can_forward_x_to_m_T_14, _rrd_p0_can_forward_x_to_m_T_15) node _rrd_p0_can_forward_x_to_m_T_17 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_18 = and(_rrd_p0_can_forward_x_to_m_T_16, _rrd_p0_can_forward_x_to_m_T_17) node _rrd_p0_can_forward_x_to_m_T_19 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rrd_p0_can_forward_x_to_m_T_20 = and(_rrd_p0_can_forward_x_to_m_T_18, _rrd_p0_can_forward_x_to_m_T_19) node _rrd_p0_can_forward_x_to_m_T_21 = and(rrd_uops[0].bits.ctrl.wxd, _rrd_p0_can_forward_x_to_m_T_20) node rrd_p0_can_forward_x_to_m = and(_rrd_p0_can_forward_x_to_m_T_21, UInt<1>(0h1)) node _rrd_p0_can_forward_w_to_l_T = and(rrd_uops[0].bits.ctrl.wxd, rrd_uops[0].bits.ctrl.mem) node rrd_p0_can_forward_w_to_l = and(_rrd_p0_can_forward_w_to_l_T, UInt<1>(0h1)) node rs1 = bits(rrd_uops[0].bits.inst, 19, 15) node rs2 = bits(rrd_uops[0].bits.inst, 24, 20) node rs3 = bits(rrd_uops[0].bits.inst, 31, 27) node rd = bits(rrd_uops[0].bits.inst, 11, 7) node sfb_shadow = and(UInt<1>(0h0), rrd_uops[0].bits.sfb_br) wire bypass_hit : UInt<1> connect bypass_hit, isboard[rs1] wire rs1_data : UInt connect rs1_data, iregfile[rs1] node _T_24 = eq(ll_bypass_0.dst, rs1) node _T_25 = and(ll_bypass_0.valid, _T_24) when _T_25 : connect bypass_hit, ll_bypass_0.can_bypass connect rs1_data, ll_bypass_0.data node _T_26 = eq(wb_bypasses_0.dst, rs1) node _T_27 = and(wb_bypasses_0.valid, _T_26) when _T_27 : connect bypass_hit, wb_bypasses_0.can_bypass connect rs1_data, wb_bypasses_0.data node _T_28 = eq(wb_bypasses_1.dst, rs1) node _T_29 = and(wb_bypasses_1.valid, _T_28) when _T_29 : connect bypass_hit, wb_bypasses_1.can_bypass connect rs1_data, wb_bypasses_1.data node _T_30 = eq(com_bypasses_0.dst, rs1) node _T_31 = and(com_bypasses_0.valid, _T_30) when _T_31 : connect bypass_hit, com_bypasses_0.can_bypass connect rs1_data, com_bypasses_0.data node _T_32 = eq(com_bypasses_1.dst, rs1) node _T_33 = and(com_bypasses_1.valid, _T_32) when _T_33 : connect bypass_hit, com_bypasses_1.can_bypass connect rs1_data, com_bypasses_1.data node _T_34 = eq(mem_bypasses_0.dst, rs1) node _T_35 = and(mem_bypasses_0.valid, _T_34) when _T_35 : connect bypass_hit, mem_bypasses_0.can_bypass connect rs1_data, mem_bypasses_0.data node _T_36 = eq(mem_bypasses_1.dst, rs1) node _T_37 = and(mem_bypasses_1.valid, _T_36) when _T_37 : connect bypass_hit, mem_bypasses_1.can_bypass connect rs1_data, mem_bypasses_1.data node _T_38 = eq(ex_bypasses_0.dst, rs1) node _T_39 = and(ex_bypasses_0.valid, _T_38) when _T_39 : connect bypass_hit, ex_bypasses_0.can_bypass connect rs1_data, ex_bypasses_0.data node _T_40 = eq(ex_bypasses_1.dst, rs1) node _T_41 = and(ex_bypasses_1.valid, _T_40) when _T_41 : connect bypass_hit, ex_bypasses_1.can_bypass connect rs1_data, ex_bypasses_1.data node rs1_older_hazard = eq(bypass_hit, UInt<1>(0h0)) wire bypass_hit_1 : UInt<1> connect bypass_hit_1, isboard[rs2] wire rs2_data : UInt connect rs2_data, iregfile[rs2] node _T_42 = eq(ll_bypass_0.dst, rs2) node _T_43 = and(ll_bypass_0.valid, _T_42) when _T_43 : connect bypass_hit_1, ll_bypass_0.can_bypass connect rs2_data, ll_bypass_0.data node _T_44 = eq(wb_bypasses_0.dst, rs2) node _T_45 = and(wb_bypasses_0.valid, _T_44) when _T_45 : connect bypass_hit_1, wb_bypasses_0.can_bypass connect rs2_data, wb_bypasses_0.data node _T_46 = eq(wb_bypasses_1.dst, rs2) node _T_47 = and(wb_bypasses_1.valid, _T_46) when _T_47 : connect bypass_hit_1, wb_bypasses_1.can_bypass connect rs2_data, wb_bypasses_1.data node _T_48 = eq(com_bypasses_0.dst, rs2) node _T_49 = and(com_bypasses_0.valid, _T_48) when _T_49 : connect bypass_hit_1, com_bypasses_0.can_bypass connect rs2_data, com_bypasses_0.data node _T_50 = eq(com_bypasses_1.dst, rs2) node _T_51 = and(com_bypasses_1.valid, _T_50) when _T_51 : connect bypass_hit_1, com_bypasses_1.can_bypass connect rs2_data, com_bypasses_1.data node _T_52 = eq(mem_bypasses_0.dst, rs2) node _T_53 = and(mem_bypasses_0.valid, _T_52) when _T_53 : connect bypass_hit_1, mem_bypasses_0.can_bypass connect rs2_data, mem_bypasses_0.data node _T_54 = eq(mem_bypasses_1.dst, rs2) node _T_55 = and(mem_bypasses_1.valid, _T_54) when _T_55 : connect bypass_hit_1, mem_bypasses_1.can_bypass connect rs2_data, mem_bypasses_1.data node _T_56 = eq(ex_bypasses_0.dst, rs2) node _T_57 = and(ex_bypasses_0.valid, _T_56) when _T_57 : connect bypass_hit_1, ex_bypasses_0.can_bypass connect rs2_data, ex_bypasses_0.data node _T_58 = eq(ex_bypasses_1.dst, rs2) node _T_59 = and(ex_bypasses_1.valid, _T_58) when _T_59 : connect bypass_hit_1, ex_bypasses_1.can_bypass connect rs2_data, ex_bypasses_1.data node rs2_older_hazard = eq(bypass_hit_1, UInt<1>(0h0)) wire rd_older_hazard_bypass_hit : UInt<1> connect rd_older_hazard_bypass_hit, isboard[rd] wire rd_older_hazard_bypass_data : UInt<1> connect rd_older_hazard_bypass_data, UInt<1>(0h0) node _rd_older_hazard_T = eq(ll_bypass_0.dst, rd) node _rd_older_hazard_T_1 = and(ll_bypass_0.valid, _rd_older_hazard_T) when _rd_older_hazard_T_1 : connect rd_older_hazard_bypass_hit, ll_bypass_0.can_bypass connect rd_older_hazard_bypass_data, ll_bypass_0.data node _rd_older_hazard_T_2 = eq(wb_bypasses_0.dst, rd) node _rd_older_hazard_T_3 = and(wb_bypasses_0.valid, _rd_older_hazard_T_2) when _rd_older_hazard_T_3 : connect rd_older_hazard_bypass_hit, wb_bypasses_0.can_bypass connect rd_older_hazard_bypass_data, wb_bypasses_0.data node _rd_older_hazard_T_4 = eq(wb_bypasses_1.dst, rd) node _rd_older_hazard_T_5 = and(wb_bypasses_1.valid, _rd_older_hazard_T_4) when _rd_older_hazard_T_5 : connect rd_older_hazard_bypass_hit, wb_bypasses_1.can_bypass connect rd_older_hazard_bypass_data, wb_bypasses_1.data node _rd_older_hazard_T_6 = eq(com_bypasses_0.dst, rd) node _rd_older_hazard_T_7 = and(com_bypasses_0.valid, _rd_older_hazard_T_6) when _rd_older_hazard_T_7 : connect rd_older_hazard_bypass_hit, com_bypasses_0.can_bypass connect rd_older_hazard_bypass_data, com_bypasses_0.data node _rd_older_hazard_T_8 = eq(com_bypasses_1.dst, rd) node _rd_older_hazard_T_9 = and(com_bypasses_1.valid, _rd_older_hazard_T_8) when _rd_older_hazard_T_9 : connect rd_older_hazard_bypass_hit, com_bypasses_1.can_bypass connect rd_older_hazard_bypass_data, com_bypasses_1.data node _rd_older_hazard_T_10 = eq(mem_bypasses_0.dst, rd) node _rd_older_hazard_T_11 = and(mem_bypasses_0.valid, _rd_older_hazard_T_10) when _rd_older_hazard_T_11 : connect rd_older_hazard_bypass_hit, mem_bypasses_0.can_bypass connect rd_older_hazard_bypass_data, mem_bypasses_0.data node _rd_older_hazard_T_12 = eq(mem_bypasses_1.dst, rd) node _rd_older_hazard_T_13 = and(mem_bypasses_1.valid, _rd_older_hazard_T_12) when _rd_older_hazard_T_13 : connect rd_older_hazard_bypass_hit, mem_bypasses_1.can_bypass connect rd_older_hazard_bypass_data, mem_bypasses_1.data node _rd_older_hazard_T_14 = eq(ex_bypasses_0.dst, rd) node _rd_older_hazard_T_15 = and(ex_bypasses_0.valid, _rd_older_hazard_T_14) when _rd_older_hazard_T_15 : connect rd_older_hazard_bypass_hit, ex_bypasses_0.can_bypass connect rd_older_hazard_bypass_data, ex_bypasses_0.data node _rd_older_hazard_T_16 = eq(ex_bypasses_1.dst, rd) node _rd_older_hazard_T_17 = and(ex_bypasses_1.valid, _rd_older_hazard_T_16) when _rd_older_hazard_T_17 : connect rd_older_hazard_bypass_hit, ex_bypasses_1.can_bypass connect rd_older_hazard_bypass_data, ex_bypasses_1.data node rd_older_hazard = eq(rd_older_hazard_bypass_hit, UInt<1>(0h0)) node _rrd_uops_0_bits_rs1_data_T = eq(rs1, UInt<1>(0h0)) node _rrd_uops_0_bits_rs1_data_T_1 = mux(_rrd_uops_0_bits_rs1_data_T, UInt<1>(0h0), rs1_data) connect rrd_uops[0].bits.rs1_data, _rrd_uops_0_bits_rs1_data_T_1 node _T_60 = eq(rrd_uops[0].bits.xcpt_cause, UInt<2>(0h2)) node _T_61 = and(rrd_uops[0].bits.xcpt, _T_60) when _T_61 : connect rrd_uops[0].bits.rs1_data, io.imem.resp[0].bits.raw_inst node _rrd_uops_0_bits_rs2_data_T = eq(rs2, UInt<1>(0h0)) node _rrd_uops_0_bits_rs2_data_T_1 = mux(_rrd_uops_0_bits_rs2_data_T, UInt<1>(0h0), rs2_data) connect rrd_uops[0].bits.rs2_data, _rrd_uops_0_bits_rs2_data_T_1 node _rs1_w0_hit_T = eq(rrd_irf_writes[0].bits, rs1) node rs1_w0_hit = and(rrd_irf_writes[0].valid, _rs1_w0_hit_T) node _rs2_w0_hit_T = eq(rrd_irf_writes[0].bits, rs2) node rs2_w0_hit = and(rrd_irf_writes[0].valid, _rs2_w0_hit_T) node memalu_will_be_latealu = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.uses_latealu) node _rs1_can_forward_from_x_p0_T = and(UInt<1>(0h0), rrd_p0_can_forward_x_to_m) node _rs1_can_forward_from_x_p0_T_1 = and(_rs1_can_forward_from_x_p0_T, rs1_w0_hit) node _rs1_can_forward_from_x_p0_T_2 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_3 = and(rrd_uops[0].bits.ctrl.wxd, _rs1_can_forward_from_x_p0_T_2) node _rs1_can_forward_from_x_p0_T_4 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_5 = and(_rs1_can_forward_from_x_p0_T_3, _rs1_can_forward_from_x_p0_T_4) node _rs1_can_forward_from_x_p0_T_6 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_7 = and(_rs1_can_forward_from_x_p0_T_5, _rs1_can_forward_from_x_p0_T_6) node _rs1_can_forward_from_x_p0_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rs1_can_forward_from_x_p0_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rs1_can_forward_from_x_p0_T_10 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rs1_can_forward_from_x_p0_T_11 = or(_rs1_can_forward_from_x_p0_T_8, _rs1_can_forward_from_x_p0_T_9) node _rs1_can_forward_from_x_p0_T_12 = or(_rs1_can_forward_from_x_p0_T_11, _rs1_can_forward_from_x_p0_T_10) node _rs1_can_forward_from_x_p0_T_13 = eq(_rs1_can_forward_from_x_p0_T_12, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_14 = and(_rs1_can_forward_from_x_p0_T_7, _rs1_can_forward_from_x_p0_T_13) node _rs1_can_forward_from_x_p0_T_15 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_16 = and(_rs1_can_forward_from_x_p0_T_14, _rs1_can_forward_from_x_p0_T_15) node _rs1_can_forward_from_x_p0_T_17 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_18 = and(_rs1_can_forward_from_x_p0_T_16, _rs1_can_forward_from_x_p0_T_17) node _rs1_can_forward_from_x_p0_T_19 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_20 = and(_rs1_can_forward_from_x_p0_T_18, _rs1_can_forward_from_x_p0_T_19) node _rs1_can_forward_from_x_p0_T_21 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_22 = and(_rs1_can_forward_from_x_p0_T_20, _rs1_can_forward_from_x_p0_T_21) node _rs1_can_forward_from_x_p0_T_23 = and(_rs1_can_forward_from_x_p0_T_1, _rs1_can_forward_from_x_p0_T_22) node _rs1_can_forward_from_x_p0_T_24 = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _rs1_can_forward_from_x_p0_T_25 = or(_rs1_can_forward_from_x_p0_T_24, rrd_uops[0].bits.ctrl.jalr) node _rs1_can_forward_from_x_p0_T_26 = eq(_rs1_can_forward_from_x_p0_T_25, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_27 = and(_rs1_can_forward_from_x_p0_T_23, _rs1_can_forward_from_x_p0_T_26) node _rs1_can_forward_from_x_p0_T_28 = eq(rrd_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_29 = and(_rs1_can_forward_from_x_p0_T_27, _rs1_can_forward_from_x_p0_T_28) node _rs1_can_forward_from_x_p0_T_30 = neq(rs1, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_31 = and(_rs1_can_forward_from_x_p0_T_29, _rs1_can_forward_from_x_p0_T_30) node _rs1_can_forward_from_x_p0_T_32 = eq(memalu_will_be_latealu, UInt<1>(0h0)) node rs1_can_forward_from_x_p0 = and(_rs1_can_forward_from_x_p0_T_31, _rs1_can_forward_from_x_p0_T_32) node _rs2_can_forward_from_x_p0_T = and(UInt<1>(0h0), rrd_p0_can_forward_x_to_m) node _rs2_can_forward_from_x_p0_T_1 = and(_rs2_can_forward_from_x_p0_T, rs2_w0_hit) node _rs2_can_forward_from_x_p0_T_2 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_3 = and(rrd_uops[0].bits.ctrl.wxd, _rs2_can_forward_from_x_p0_T_2) node _rs2_can_forward_from_x_p0_T_4 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_5 = and(_rs2_can_forward_from_x_p0_T_3, _rs2_can_forward_from_x_p0_T_4) node _rs2_can_forward_from_x_p0_T_6 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_7 = and(_rs2_can_forward_from_x_p0_T_5, _rs2_can_forward_from_x_p0_T_6) node _rs2_can_forward_from_x_p0_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rs2_can_forward_from_x_p0_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rs2_can_forward_from_x_p0_T_10 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rs2_can_forward_from_x_p0_T_11 = or(_rs2_can_forward_from_x_p0_T_8, _rs2_can_forward_from_x_p0_T_9) node _rs2_can_forward_from_x_p0_T_12 = or(_rs2_can_forward_from_x_p0_T_11, _rs2_can_forward_from_x_p0_T_10) node _rs2_can_forward_from_x_p0_T_13 = eq(_rs2_can_forward_from_x_p0_T_12, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_14 = and(_rs2_can_forward_from_x_p0_T_7, _rs2_can_forward_from_x_p0_T_13) node _rs2_can_forward_from_x_p0_T_15 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_16 = and(_rs2_can_forward_from_x_p0_T_14, _rs2_can_forward_from_x_p0_T_15) node _rs2_can_forward_from_x_p0_T_17 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_18 = and(_rs2_can_forward_from_x_p0_T_16, _rs2_can_forward_from_x_p0_T_17) node _rs2_can_forward_from_x_p0_T_19 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_20 = and(_rs2_can_forward_from_x_p0_T_18, _rs2_can_forward_from_x_p0_T_19) node _rs2_can_forward_from_x_p0_T_21 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_22 = and(_rs2_can_forward_from_x_p0_T_20, _rs2_can_forward_from_x_p0_T_21) node _rs2_can_forward_from_x_p0_T_23 = and(_rs2_can_forward_from_x_p0_T_1, _rs2_can_forward_from_x_p0_T_22) node _rs2_can_forward_from_x_p0_T_24 = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _rs2_can_forward_from_x_p0_T_25 = or(_rs2_can_forward_from_x_p0_T_24, rrd_uops[0].bits.ctrl.jalr) node _rs2_can_forward_from_x_p0_T_26 = eq(_rs2_can_forward_from_x_p0_T_25, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_27 = and(_rs2_can_forward_from_x_p0_T_23, _rs2_can_forward_from_x_p0_T_26) node _rs2_can_forward_from_x_p0_T_28 = eq(rrd_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_29 = and(_rs2_can_forward_from_x_p0_T_27, _rs2_can_forward_from_x_p0_T_28) node _rs2_can_forward_from_x_p0_T_30 = neq(rs2, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_31 = and(_rs2_can_forward_from_x_p0_T_29, _rs2_can_forward_from_x_p0_T_30) node _rs2_can_forward_from_x_p0_T_32 = eq(memalu_will_be_latealu, UInt<1>(0h0)) node rs2_can_forward_from_x_p0 = and(_rs2_can_forward_from_x_p0_T_31, _rs2_can_forward_from_x_p0_T_32) node _rs1_can_forward_from_w_p0_T = and(UInt<1>(0h0), rrd_p0_can_forward_w_to_l) node _rs1_can_forward_from_w_p0_T_1 = and(_rs1_can_forward_from_w_p0_T, rs1_w0_hit) node _rs1_can_forward_from_w_p0_T_2 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_3 = and(rrd_uops[0].bits.ctrl.wxd, _rs1_can_forward_from_w_p0_T_2) node _rs1_can_forward_from_w_p0_T_4 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_5 = and(_rs1_can_forward_from_w_p0_T_3, _rs1_can_forward_from_w_p0_T_4) node _rs1_can_forward_from_w_p0_T_6 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_7 = and(_rs1_can_forward_from_w_p0_T_5, _rs1_can_forward_from_w_p0_T_6) node _rs1_can_forward_from_w_p0_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rs1_can_forward_from_w_p0_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rs1_can_forward_from_w_p0_T_10 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rs1_can_forward_from_w_p0_T_11 = or(_rs1_can_forward_from_w_p0_T_8, _rs1_can_forward_from_w_p0_T_9) node _rs1_can_forward_from_w_p0_T_12 = or(_rs1_can_forward_from_w_p0_T_11, _rs1_can_forward_from_w_p0_T_10) node _rs1_can_forward_from_w_p0_T_13 = eq(_rs1_can_forward_from_w_p0_T_12, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_14 = and(_rs1_can_forward_from_w_p0_T_7, _rs1_can_forward_from_w_p0_T_13) node _rs1_can_forward_from_w_p0_T_15 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_16 = and(_rs1_can_forward_from_w_p0_T_14, _rs1_can_forward_from_w_p0_T_15) node _rs1_can_forward_from_w_p0_T_17 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_18 = and(_rs1_can_forward_from_w_p0_T_16, _rs1_can_forward_from_w_p0_T_17) node _rs1_can_forward_from_w_p0_T_19 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_20 = and(_rs1_can_forward_from_w_p0_T_18, _rs1_can_forward_from_w_p0_T_19) node _rs1_can_forward_from_w_p0_T_21 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_22 = and(_rs1_can_forward_from_w_p0_T_20, _rs1_can_forward_from_w_p0_T_21) node _rs1_can_forward_from_w_p0_T_23 = and(_rs1_can_forward_from_w_p0_T_1, _rs1_can_forward_from_w_p0_T_22) node _rs1_can_forward_from_w_p0_T_24 = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _rs1_can_forward_from_w_p0_T_25 = or(_rs1_can_forward_from_w_p0_T_24, rrd_uops[0].bits.ctrl.jalr) node _rs1_can_forward_from_w_p0_T_26 = eq(_rs1_can_forward_from_w_p0_T_25, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_27 = and(_rs1_can_forward_from_w_p0_T_23, _rs1_can_forward_from_w_p0_T_26) node _rs1_can_forward_from_w_p0_T_28 = eq(rrd_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_29 = and(_rs1_can_forward_from_w_p0_T_27, _rs1_can_forward_from_w_p0_T_28) node _rs1_can_forward_from_w_p0_T_30 = neq(rs1, UInt<1>(0h0)) node rs1_can_forward_from_w_p0 = and(_rs1_can_forward_from_w_p0_T_29, _rs1_can_forward_from_w_p0_T_30) node _rs2_can_forward_from_w_p0_T = and(UInt<1>(0h0), rrd_p0_can_forward_w_to_l) node _rs2_can_forward_from_w_p0_T_1 = and(_rs2_can_forward_from_w_p0_T, rs2_w0_hit) node _rs2_can_forward_from_w_p0_T_2 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_3 = and(rrd_uops[0].bits.ctrl.wxd, _rs2_can_forward_from_w_p0_T_2) node _rs2_can_forward_from_w_p0_T_4 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_5 = and(_rs2_can_forward_from_w_p0_T_3, _rs2_can_forward_from_w_p0_T_4) node _rs2_can_forward_from_w_p0_T_6 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_7 = and(_rs2_can_forward_from_w_p0_T_5, _rs2_can_forward_from_w_p0_T_6) node _rs2_can_forward_from_w_p0_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rs2_can_forward_from_w_p0_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rs2_can_forward_from_w_p0_T_10 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rs2_can_forward_from_w_p0_T_11 = or(_rs2_can_forward_from_w_p0_T_8, _rs2_can_forward_from_w_p0_T_9) node _rs2_can_forward_from_w_p0_T_12 = or(_rs2_can_forward_from_w_p0_T_11, _rs2_can_forward_from_w_p0_T_10) node _rs2_can_forward_from_w_p0_T_13 = eq(_rs2_can_forward_from_w_p0_T_12, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_14 = and(_rs2_can_forward_from_w_p0_T_7, _rs2_can_forward_from_w_p0_T_13) node _rs2_can_forward_from_w_p0_T_15 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_16 = and(_rs2_can_forward_from_w_p0_T_14, _rs2_can_forward_from_w_p0_T_15) node _rs2_can_forward_from_w_p0_T_17 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_18 = and(_rs2_can_forward_from_w_p0_T_16, _rs2_can_forward_from_w_p0_T_17) node _rs2_can_forward_from_w_p0_T_19 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_20 = and(_rs2_can_forward_from_w_p0_T_18, _rs2_can_forward_from_w_p0_T_19) node _rs2_can_forward_from_w_p0_T_21 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_22 = and(_rs2_can_forward_from_w_p0_T_20, _rs2_can_forward_from_w_p0_T_21) node _rs2_can_forward_from_w_p0_T_23 = and(_rs2_can_forward_from_w_p0_T_1, _rs2_can_forward_from_w_p0_T_22) node _rs2_can_forward_from_w_p0_T_24 = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _rs2_can_forward_from_w_p0_T_25 = or(_rs2_can_forward_from_w_p0_T_24, rrd_uops[0].bits.ctrl.jalr) node _rs2_can_forward_from_w_p0_T_26 = eq(_rs2_can_forward_from_w_p0_T_25, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_27 = and(_rs2_can_forward_from_w_p0_T_23, _rs2_can_forward_from_w_p0_T_26) node _rs2_can_forward_from_w_p0_T_28 = eq(rrd_uops[0].bits.sets_vcfg, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_29 = and(_rs2_can_forward_from_w_p0_T_27, _rs2_can_forward_from_w_p0_T_28) node _rs2_can_forward_from_w_p0_T_30 = neq(rs2, UInt<1>(0h0)) node rs2_can_forward_from_w_p0 = and(_rs2_can_forward_from_w_p0_T_29, _rs2_can_forward_from_w_p0_T_30) node _rs1_data_hazard_T = or(rs1_older_hazard, UInt<1>(0h0)) node _rs1_data_hazard_T_1 = and(_rs1_data_hazard_T, rrd_uops[0].bits.ctrl.rxs1) node _rs1_data_hazard_T_2 = neq(rs1, UInt<1>(0h0)) node rs1_data_hazard = and(_rs1_data_hazard_T_1, _rs1_data_hazard_T_2) node _rs2_data_hazard_T = or(rs2_older_hazard, UInt<1>(0h0)) node _rs2_data_hazard_T_1 = and(_rs2_data_hazard_T, rrd_uops[0].bits.ctrl.rxs2) node _rs2_data_hazard_T_2 = neq(rs2, UInt<1>(0h0)) node rs2_data_hazard = and(_rs2_data_hazard_T_1, _rs2_data_hazard_T_2) node _rd_data_hazard_T = or(rd_older_hazard, UInt<1>(0h0)) node _rd_data_hazard_T_1 = and(_rd_data_hazard_T, rrd_uops[0].bits.ctrl.wxd) node _rd_data_hazard_T_2 = neq(rd, UInt<1>(0h0)) node rd_data_hazard = and(_rd_data_hazard_T_1, _rd_data_hazard_T_2) node _frs1_same_hazard_T = and(UInt<1>(0h1), UInt<1>(0h0)) node frs1_same_hazard = and(_frs1_same_hazard_T, rrd_uops[0].bits.ctrl.rfs1) node _frs2_same_hazard_T = and(UInt<1>(0h1), UInt<1>(0h0)) node frs2_same_hazard = and(_frs2_same_hazard_T, rrd_uops[0].bits.ctrl.rfs2) node _frs3_same_hazard_T = and(UInt<1>(0h1), UInt<1>(0h0)) node frs3_same_hazard = and(_frs3_same_hazard_T, rrd_uops[0].bits.ctrl.rfs3) node _frd_same_hazard_T = and(UInt<1>(0h1), UInt<1>(0h0)) node frd_same_hazard = and(_frd_same_hazard_T, rrd_uops[0].bits.ctrl.wfd) node _rrd_stall_data_0_T = or(rs1_data_hazard, rs2_data_hazard) node _rrd_stall_data_0_T_1 = or(_rrd_stall_data_0_T, rd_data_hazard) node _rrd_stall_data_0_T_2 = or(_rrd_stall_data_0_T_1, frs1_same_hazard) node _rrd_stall_data_0_T_3 = or(_rrd_stall_data_0_T_2, frs2_same_hazard) node _rrd_stall_data_0_T_4 = or(_rrd_stall_data_0_T_3, frs3_same_hazard) node _rrd_stall_data_0_T_5 = or(_rrd_stall_data_0_T_4, frd_same_hazard) connect rrd_stall_data[0], _rrd_stall_data_0_T_5 node _rrd_uops_0_bits_uses_memalu_T = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_1 = and(rrd_uops[0].bits.ctrl.wxd, _rrd_uops_0_bits_uses_memalu_T) node _rrd_uops_0_bits_uses_memalu_T_2 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_3 = and(_rrd_uops_0_bits_uses_memalu_T_1, _rrd_uops_0_bits_uses_memalu_T_2) node _rrd_uops_0_bits_uses_memalu_T_4 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_5 = and(_rrd_uops_0_bits_uses_memalu_T_3, _rrd_uops_0_bits_uses_memalu_T_4) node _rrd_uops_0_bits_uses_memalu_T_6 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rrd_uops_0_bits_uses_memalu_T_7 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rrd_uops_0_bits_uses_memalu_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rrd_uops_0_bits_uses_memalu_T_9 = or(_rrd_uops_0_bits_uses_memalu_T_6, _rrd_uops_0_bits_uses_memalu_T_7) node _rrd_uops_0_bits_uses_memalu_T_10 = or(_rrd_uops_0_bits_uses_memalu_T_9, _rrd_uops_0_bits_uses_memalu_T_8) node _rrd_uops_0_bits_uses_memalu_T_11 = eq(_rrd_uops_0_bits_uses_memalu_T_10, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_12 = and(_rrd_uops_0_bits_uses_memalu_T_5, _rrd_uops_0_bits_uses_memalu_T_11) node _rrd_uops_0_bits_uses_memalu_T_13 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_14 = and(_rrd_uops_0_bits_uses_memalu_T_12, _rrd_uops_0_bits_uses_memalu_T_13) node _rrd_uops_0_bits_uses_memalu_T_15 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_16 = and(_rrd_uops_0_bits_uses_memalu_T_14, _rrd_uops_0_bits_uses_memalu_T_15) node _rrd_uops_0_bits_uses_memalu_T_17 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_18 = and(_rrd_uops_0_bits_uses_memalu_T_16, _rrd_uops_0_bits_uses_memalu_T_17) node _rrd_uops_0_bits_uses_memalu_T_19 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_20 = and(_rrd_uops_0_bits_uses_memalu_T_18, _rrd_uops_0_bits_uses_memalu_T_19) node _rrd_uops_0_bits_uses_memalu_T_21 = and(rs1_w0_hit, rs1_can_forward_from_x_p0) node _rrd_uops_0_bits_uses_memalu_T_22 = and(rs2_w0_hit, rs2_can_forward_from_x_p0) node _rrd_uops_0_bits_uses_memalu_T_23 = or(_rrd_uops_0_bits_uses_memalu_T_21, _rrd_uops_0_bits_uses_memalu_T_22) node _rrd_uops_0_bits_uses_memalu_T_24 = and(_rrd_uops_0_bits_uses_memalu_T_20, _rrd_uops_0_bits_uses_memalu_T_23) node _rrd_uops_0_bits_uses_memalu_T_25 = and(_rrd_uops_0_bits_uses_memalu_T_24, UInt<1>(0h1)) node _rrd_uops_0_bits_uses_memalu_T_26 = eq(sfb_shadow, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_memalu_T_27 = and(_rrd_uops_0_bits_uses_memalu_T_25, _rrd_uops_0_bits_uses_memalu_T_26) connect rrd_uops[0].bits.uses_memalu, _rrd_uops_0_bits_uses_memalu_T_27 node _rrd_uops_0_bits_uses_latealu_T = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_1 = and(rrd_uops[0].bits.ctrl.wxd, _rrd_uops_0_bits_uses_latealu_T) node _rrd_uops_0_bits_uses_latealu_T_2 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_3 = and(_rrd_uops_0_bits_uses_latealu_T_1, _rrd_uops_0_bits_uses_latealu_T_2) node _rrd_uops_0_bits_uses_latealu_T_4 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_5 = and(_rrd_uops_0_bits_uses_latealu_T_3, _rrd_uops_0_bits_uses_latealu_T_4) node _rrd_uops_0_bits_uses_latealu_T_6 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rrd_uops_0_bits_uses_latealu_T_7 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rrd_uops_0_bits_uses_latealu_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rrd_uops_0_bits_uses_latealu_T_9 = or(_rrd_uops_0_bits_uses_latealu_T_6, _rrd_uops_0_bits_uses_latealu_T_7) node _rrd_uops_0_bits_uses_latealu_T_10 = or(_rrd_uops_0_bits_uses_latealu_T_9, _rrd_uops_0_bits_uses_latealu_T_8) node _rrd_uops_0_bits_uses_latealu_T_11 = eq(_rrd_uops_0_bits_uses_latealu_T_10, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_12 = and(_rrd_uops_0_bits_uses_latealu_T_5, _rrd_uops_0_bits_uses_latealu_T_11) node _rrd_uops_0_bits_uses_latealu_T_13 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_14 = and(_rrd_uops_0_bits_uses_latealu_T_12, _rrd_uops_0_bits_uses_latealu_T_13) node _rrd_uops_0_bits_uses_latealu_T_15 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_16 = and(_rrd_uops_0_bits_uses_latealu_T_14, _rrd_uops_0_bits_uses_latealu_T_15) node _rrd_uops_0_bits_uses_latealu_T_17 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_18 = and(_rrd_uops_0_bits_uses_latealu_T_16, _rrd_uops_0_bits_uses_latealu_T_17) node _rrd_uops_0_bits_uses_latealu_T_19 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_20 = and(_rrd_uops_0_bits_uses_latealu_T_18, _rrd_uops_0_bits_uses_latealu_T_19) node _rrd_uops_0_bits_uses_latealu_T_21 = and(rs1_w0_hit, rs1_can_forward_from_w_p0) node _rrd_uops_0_bits_uses_latealu_T_22 = and(rs2_w0_hit, rs2_can_forward_from_w_p0) node _rrd_uops_0_bits_uses_latealu_T_23 = or(_rrd_uops_0_bits_uses_latealu_T_21, _rrd_uops_0_bits_uses_latealu_T_22) node _rrd_uops_0_bits_uses_latealu_T_24 = and(_rrd_uops_0_bits_uses_latealu_T_20, _rrd_uops_0_bits_uses_latealu_T_23) node _rrd_uops_0_bits_uses_latealu_T_25 = and(_rrd_uops_0_bits_uses_latealu_T_24, UInt<1>(0h1)) node _rrd_uops_0_bits_uses_latealu_T_26 = eq(sfb_shadow, UInt<1>(0h0)) node _rrd_uops_0_bits_uses_latealu_T_27 = and(_rrd_uops_0_bits_uses_latealu_T_25, _rrd_uops_0_bits_uses_latealu_T_26) connect rrd_uops[0].bits.uses_latealu, _rrd_uops_0_bits_uses_latealu_T_27 connect rrd_uops[0].bits.sfb_shadow, sfb_shadow node _rrd_irf_writes_0_valid_T = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.wxd) connect rrd_irf_writes[0].valid, _rrd_irf_writes_0_valid_T node _rrd_irf_writes_0_bits_T = bits(rrd_uops[0].bits.inst, 11, 7) connect rrd_irf_writes[0].bits, _rrd_irf_writes_0_bits_T node _T_62 = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.fp) when _T_62 : when rrd_uops[0].bits.fp_ctrl.ren1 : node _T_63 = eq(rrd_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) when _T_63 : node _rrd_uops_0_bits_fra1_T = bits(rrd_uops[0].bits.inst, 19, 15) connect rrd_uops[0].bits.fra1, _rrd_uops_0_bits_fra1_T when rrd_uops[0].bits.fp_ctrl.swap12 : node _rrd_uops_0_bits_fra2_T = bits(rrd_uops[0].bits.inst, 19, 15) connect rrd_uops[0].bits.fra2, _rrd_uops_0_bits_fra2_T when rrd_uops[0].bits.fp_ctrl.ren2 : when rrd_uops[0].bits.fp_ctrl.swap12 : node _rrd_uops_0_bits_fra1_T_1 = bits(rrd_uops[0].bits.inst, 24, 20) connect rrd_uops[0].bits.fra1, _rrd_uops_0_bits_fra1_T_1 when rrd_uops[0].bits.fp_ctrl.swap23 : node _rrd_uops_0_bits_fra3_T = bits(rrd_uops[0].bits.inst, 24, 20) connect rrd_uops[0].bits.fra3, _rrd_uops_0_bits_fra3_T node _T_64 = eq(rrd_uops[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _T_65 = eq(rrd_uops[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) when _T_66 : node _rrd_uops_0_bits_fra2_T_1 = bits(rrd_uops[0].bits.inst, 24, 20) connect rrd_uops[0].bits.fra2, _rrd_uops_0_bits_fra2_T_1 when rrd_uops[0].bits.fp_ctrl.ren3 : node _rrd_uops_0_bits_fra3_T_1 = bits(rrd_uops[0].bits.inst, 31, 27) connect rrd_uops[0].bits.fra3, _rrd_uops_0_bits_fra3_T_1 node _T_67 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _T_68 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<3>(0h5)) node _T_69 = or(_T_67, _T_68) when _T_69 : node _rrd_uops_0_bits_mem_size_T = neq(rs2, UInt<1>(0h0)) node _rrd_uops_0_bits_mem_size_T_1 = neq(rs1, UInt<1>(0h0)) node _rrd_uops_0_bits_mem_size_T_2 = cat(_rrd_uops_0_bits_mem_size_T, _rrd_uops_0_bits_mem_size_T_1) connect rrd_uops[0].bits.mem_size, _rrd_uops_0_bits_mem_size_T_2 node rs1_1 = bits(rrd_uops[1].bits.inst, 19, 15) node rs2_1 = bits(rrd_uops[1].bits.inst, 24, 20) node rs3_1 = bits(rrd_uops[1].bits.inst, 31, 27) node rd_1 = bits(rrd_uops[1].bits.inst, 11, 7) node sfb_shadow_1 = and(UInt<1>(0h1), rrd_uops[0].bits.sfb_br) wire bypass_hit_2 : UInt<1> connect bypass_hit_2, isboard[rs1_1] wire rs1_data_1 : UInt connect rs1_data_1, iregfile[rs1_1] node _T_70 = eq(ll_bypass_0.dst, rs1_1) node _T_71 = and(ll_bypass_0.valid, _T_70) when _T_71 : connect bypass_hit_2, ll_bypass_0.can_bypass connect rs1_data_1, ll_bypass_0.data node _T_72 = eq(wb_bypasses_0.dst, rs1_1) node _T_73 = and(wb_bypasses_0.valid, _T_72) when _T_73 : connect bypass_hit_2, wb_bypasses_0.can_bypass connect rs1_data_1, wb_bypasses_0.data node _T_74 = eq(wb_bypasses_1.dst, rs1_1) node _T_75 = and(wb_bypasses_1.valid, _T_74) when _T_75 : connect bypass_hit_2, wb_bypasses_1.can_bypass connect rs1_data_1, wb_bypasses_1.data node _T_76 = eq(com_bypasses_0.dst, rs1_1) node _T_77 = and(com_bypasses_0.valid, _T_76) when _T_77 : connect bypass_hit_2, com_bypasses_0.can_bypass connect rs1_data_1, com_bypasses_0.data node _T_78 = eq(com_bypasses_1.dst, rs1_1) node _T_79 = and(com_bypasses_1.valid, _T_78) when _T_79 : connect bypass_hit_2, com_bypasses_1.can_bypass connect rs1_data_1, com_bypasses_1.data node _T_80 = eq(mem_bypasses_0.dst, rs1_1) node _T_81 = and(mem_bypasses_0.valid, _T_80) when _T_81 : connect bypass_hit_2, mem_bypasses_0.can_bypass connect rs1_data_1, mem_bypasses_0.data node _T_82 = eq(mem_bypasses_1.dst, rs1_1) node _T_83 = and(mem_bypasses_1.valid, _T_82) when _T_83 : connect bypass_hit_2, mem_bypasses_1.can_bypass connect rs1_data_1, mem_bypasses_1.data node _T_84 = eq(ex_bypasses_0.dst, rs1_1) node _T_85 = and(ex_bypasses_0.valid, _T_84) when _T_85 : connect bypass_hit_2, ex_bypasses_0.can_bypass connect rs1_data_1, ex_bypasses_0.data node _T_86 = eq(ex_bypasses_1.dst, rs1_1) node _T_87 = and(ex_bypasses_1.valid, _T_86) when _T_87 : connect bypass_hit_2, ex_bypasses_1.can_bypass connect rs1_data_1, ex_bypasses_1.data node rs1_older_hazard_1 = eq(bypass_hit_2, UInt<1>(0h0)) wire bypass_hit_3 : UInt<1> connect bypass_hit_3, isboard[rs2_1] wire rs2_data_1 : UInt connect rs2_data_1, iregfile[rs2_1] node _T_88 = eq(ll_bypass_0.dst, rs2_1) node _T_89 = and(ll_bypass_0.valid, _T_88) when _T_89 : connect bypass_hit_3, ll_bypass_0.can_bypass connect rs2_data_1, ll_bypass_0.data node _T_90 = eq(wb_bypasses_0.dst, rs2_1) node _T_91 = and(wb_bypasses_0.valid, _T_90) when _T_91 : connect bypass_hit_3, wb_bypasses_0.can_bypass connect rs2_data_1, wb_bypasses_0.data node _T_92 = eq(wb_bypasses_1.dst, rs2_1) node _T_93 = and(wb_bypasses_1.valid, _T_92) when _T_93 : connect bypass_hit_3, wb_bypasses_1.can_bypass connect rs2_data_1, wb_bypasses_1.data node _T_94 = eq(com_bypasses_0.dst, rs2_1) node _T_95 = and(com_bypasses_0.valid, _T_94) when _T_95 : connect bypass_hit_3, com_bypasses_0.can_bypass connect rs2_data_1, com_bypasses_0.data node _T_96 = eq(com_bypasses_1.dst, rs2_1) node _T_97 = and(com_bypasses_1.valid, _T_96) when _T_97 : connect bypass_hit_3, com_bypasses_1.can_bypass connect rs2_data_1, com_bypasses_1.data node _T_98 = eq(mem_bypasses_0.dst, rs2_1) node _T_99 = and(mem_bypasses_0.valid, _T_98) when _T_99 : connect bypass_hit_3, mem_bypasses_0.can_bypass connect rs2_data_1, mem_bypasses_0.data node _T_100 = eq(mem_bypasses_1.dst, rs2_1) node _T_101 = and(mem_bypasses_1.valid, _T_100) when _T_101 : connect bypass_hit_3, mem_bypasses_1.can_bypass connect rs2_data_1, mem_bypasses_1.data node _T_102 = eq(ex_bypasses_0.dst, rs2_1) node _T_103 = and(ex_bypasses_0.valid, _T_102) when _T_103 : connect bypass_hit_3, ex_bypasses_0.can_bypass connect rs2_data_1, ex_bypasses_0.data node _T_104 = eq(ex_bypasses_1.dst, rs2_1) node _T_105 = and(ex_bypasses_1.valid, _T_104) when _T_105 : connect bypass_hit_3, ex_bypasses_1.can_bypass connect rs2_data_1, ex_bypasses_1.data node rs2_older_hazard_1 = eq(bypass_hit_3, UInt<1>(0h0)) wire rd_older_hazard_bypass_hit_1 : UInt<1> connect rd_older_hazard_bypass_hit_1, isboard[rd_1] wire rd_older_hazard_bypass_data_1 : UInt<1> connect rd_older_hazard_bypass_data_1, UInt<1>(0h0) node _rd_older_hazard_T_18 = eq(ll_bypass_0.dst, rd_1) node _rd_older_hazard_T_19 = and(ll_bypass_0.valid, _rd_older_hazard_T_18) when _rd_older_hazard_T_19 : connect rd_older_hazard_bypass_hit_1, ll_bypass_0.can_bypass connect rd_older_hazard_bypass_data_1, ll_bypass_0.data node _rd_older_hazard_T_20 = eq(wb_bypasses_0.dst, rd_1) node _rd_older_hazard_T_21 = and(wb_bypasses_0.valid, _rd_older_hazard_T_20) when _rd_older_hazard_T_21 : connect rd_older_hazard_bypass_hit_1, wb_bypasses_0.can_bypass connect rd_older_hazard_bypass_data_1, wb_bypasses_0.data node _rd_older_hazard_T_22 = eq(wb_bypasses_1.dst, rd_1) node _rd_older_hazard_T_23 = and(wb_bypasses_1.valid, _rd_older_hazard_T_22) when _rd_older_hazard_T_23 : connect rd_older_hazard_bypass_hit_1, wb_bypasses_1.can_bypass connect rd_older_hazard_bypass_data_1, wb_bypasses_1.data node _rd_older_hazard_T_24 = eq(com_bypasses_0.dst, rd_1) node _rd_older_hazard_T_25 = and(com_bypasses_0.valid, _rd_older_hazard_T_24) when _rd_older_hazard_T_25 : connect rd_older_hazard_bypass_hit_1, com_bypasses_0.can_bypass connect rd_older_hazard_bypass_data_1, com_bypasses_0.data node _rd_older_hazard_T_26 = eq(com_bypasses_1.dst, rd_1) node _rd_older_hazard_T_27 = and(com_bypasses_1.valid, _rd_older_hazard_T_26) when _rd_older_hazard_T_27 : connect rd_older_hazard_bypass_hit_1, com_bypasses_1.can_bypass connect rd_older_hazard_bypass_data_1, com_bypasses_1.data node _rd_older_hazard_T_28 = eq(mem_bypasses_0.dst, rd_1) node _rd_older_hazard_T_29 = and(mem_bypasses_0.valid, _rd_older_hazard_T_28) when _rd_older_hazard_T_29 : connect rd_older_hazard_bypass_hit_1, mem_bypasses_0.can_bypass connect rd_older_hazard_bypass_data_1, mem_bypasses_0.data node _rd_older_hazard_T_30 = eq(mem_bypasses_1.dst, rd_1) node _rd_older_hazard_T_31 = and(mem_bypasses_1.valid, _rd_older_hazard_T_30) when _rd_older_hazard_T_31 : connect rd_older_hazard_bypass_hit_1, mem_bypasses_1.can_bypass connect rd_older_hazard_bypass_data_1, mem_bypasses_1.data node _rd_older_hazard_T_32 = eq(ex_bypasses_0.dst, rd_1) node _rd_older_hazard_T_33 = and(ex_bypasses_0.valid, _rd_older_hazard_T_32) when _rd_older_hazard_T_33 : connect rd_older_hazard_bypass_hit_1, ex_bypasses_0.can_bypass connect rd_older_hazard_bypass_data_1, ex_bypasses_0.data node _rd_older_hazard_T_34 = eq(ex_bypasses_1.dst, rd_1) node _rd_older_hazard_T_35 = and(ex_bypasses_1.valid, _rd_older_hazard_T_34) when _rd_older_hazard_T_35 : connect rd_older_hazard_bypass_hit_1, ex_bypasses_1.can_bypass connect rd_older_hazard_bypass_data_1, ex_bypasses_1.data node rd_older_hazard_1 = eq(rd_older_hazard_bypass_hit_1, UInt<1>(0h0)) node _rrd_uops_1_bits_rs1_data_T = eq(rs1_1, UInt<1>(0h0)) node _rrd_uops_1_bits_rs1_data_T_1 = mux(_rrd_uops_1_bits_rs1_data_T, UInt<1>(0h0), rs1_data_1) connect rrd_uops[1].bits.rs1_data, _rrd_uops_1_bits_rs1_data_T_1 node _T_106 = eq(rrd_uops[1].bits.xcpt_cause, UInt<2>(0h2)) node _T_107 = and(rrd_uops[1].bits.xcpt, _T_106) when _T_107 : connect rrd_uops[1].bits.rs1_data, io.imem.resp[1].bits.raw_inst node _rrd_uops_1_bits_rs2_data_T = eq(rs2_1, UInt<1>(0h0)) node _rrd_uops_1_bits_rs2_data_T_1 = mux(_rrd_uops_1_bits_rs2_data_T, UInt<1>(0h0), rs2_data_1) connect rrd_uops[1].bits.rs2_data, _rrd_uops_1_bits_rs2_data_T_1 node _rs1_w0_hit_T_1 = eq(rrd_irf_writes[0].bits, rs1_1) node rs1_w0_hit_1 = and(rrd_irf_writes[0].valid, _rs1_w0_hit_T_1) node _rs2_w0_hit_T_1 = eq(rrd_irf_writes[0].bits, rs2_1) node rs2_w0_hit_1 = and(rrd_irf_writes[0].valid, _rs2_w0_hit_T_1) node memalu_will_be_latealu_1 = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.uses_latealu) node _rs1_can_forward_from_x_p0_T_33 = and(UInt<1>(0h1), rrd_p0_can_forward_x_to_m) node _rs1_can_forward_from_x_p0_T_34 = and(_rs1_can_forward_from_x_p0_T_33, rs1_w0_hit_1) node _rs1_can_forward_from_x_p0_T_35 = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_36 = and(rrd_uops[1].bits.ctrl.wxd, _rs1_can_forward_from_x_p0_T_35) node _rs1_can_forward_from_x_p0_T_37 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_38 = and(_rs1_can_forward_from_x_p0_T_36, _rs1_can_forward_from_x_p0_T_37) node _rs1_can_forward_from_x_p0_T_39 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_40 = and(_rs1_can_forward_from_x_p0_T_38, _rs1_can_forward_from_x_p0_T_39) node _rs1_can_forward_from_x_p0_T_41 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rs1_can_forward_from_x_p0_T_42 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rs1_can_forward_from_x_p0_T_43 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rs1_can_forward_from_x_p0_T_44 = or(_rs1_can_forward_from_x_p0_T_41, _rs1_can_forward_from_x_p0_T_42) node _rs1_can_forward_from_x_p0_T_45 = or(_rs1_can_forward_from_x_p0_T_44, _rs1_can_forward_from_x_p0_T_43) node _rs1_can_forward_from_x_p0_T_46 = eq(_rs1_can_forward_from_x_p0_T_45, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_47 = and(_rs1_can_forward_from_x_p0_T_40, _rs1_can_forward_from_x_p0_T_46) node _rs1_can_forward_from_x_p0_T_48 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_49 = and(_rs1_can_forward_from_x_p0_T_47, _rs1_can_forward_from_x_p0_T_48) node _rs1_can_forward_from_x_p0_T_50 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_51 = and(_rs1_can_forward_from_x_p0_T_49, _rs1_can_forward_from_x_p0_T_50) node _rs1_can_forward_from_x_p0_T_52 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_53 = and(_rs1_can_forward_from_x_p0_T_51, _rs1_can_forward_from_x_p0_T_52) node _rs1_can_forward_from_x_p0_T_54 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_55 = and(_rs1_can_forward_from_x_p0_T_53, _rs1_can_forward_from_x_p0_T_54) node _rs1_can_forward_from_x_p0_T_56 = and(_rs1_can_forward_from_x_p0_T_34, _rs1_can_forward_from_x_p0_T_55) node _rs1_can_forward_from_x_p0_T_57 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _rs1_can_forward_from_x_p0_T_58 = or(_rs1_can_forward_from_x_p0_T_57, rrd_uops[1].bits.ctrl.jalr) node _rs1_can_forward_from_x_p0_T_59 = eq(_rs1_can_forward_from_x_p0_T_58, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_60 = and(_rs1_can_forward_from_x_p0_T_56, _rs1_can_forward_from_x_p0_T_59) node _rs1_can_forward_from_x_p0_T_61 = eq(rrd_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_62 = and(_rs1_can_forward_from_x_p0_T_60, _rs1_can_forward_from_x_p0_T_61) node _rs1_can_forward_from_x_p0_T_63 = neq(rs1_1, UInt<1>(0h0)) node _rs1_can_forward_from_x_p0_T_64 = and(_rs1_can_forward_from_x_p0_T_62, _rs1_can_forward_from_x_p0_T_63) node _rs1_can_forward_from_x_p0_T_65 = eq(memalu_will_be_latealu_1, UInt<1>(0h0)) node rs1_can_forward_from_x_p0_1 = and(_rs1_can_forward_from_x_p0_T_64, _rs1_can_forward_from_x_p0_T_65) node _rs2_can_forward_from_x_p0_T_33 = and(UInt<1>(0h1), rrd_p0_can_forward_x_to_m) node _rs2_can_forward_from_x_p0_T_34 = and(_rs2_can_forward_from_x_p0_T_33, rs2_w0_hit_1) node _rs2_can_forward_from_x_p0_T_35 = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_36 = and(rrd_uops[1].bits.ctrl.wxd, _rs2_can_forward_from_x_p0_T_35) node _rs2_can_forward_from_x_p0_T_37 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_38 = and(_rs2_can_forward_from_x_p0_T_36, _rs2_can_forward_from_x_p0_T_37) node _rs2_can_forward_from_x_p0_T_39 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_40 = and(_rs2_can_forward_from_x_p0_T_38, _rs2_can_forward_from_x_p0_T_39) node _rs2_can_forward_from_x_p0_T_41 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rs2_can_forward_from_x_p0_T_42 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rs2_can_forward_from_x_p0_T_43 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rs2_can_forward_from_x_p0_T_44 = or(_rs2_can_forward_from_x_p0_T_41, _rs2_can_forward_from_x_p0_T_42) node _rs2_can_forward_from_x_p0_T_45 = or(_rs2_can_forward_from_x_p0_T_44, _rs2_can_forward_from_x_p0_T_43) node _rs2_can_forward_from_x_p0_T_46 = eq(_rs2_can_forward_from_x_p0_T_45, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_47 = and(_rs2_can_forward_from_x_p0_T_40, _rs2_can_forward_from_x_p0_T_46) node _rs2_can_forward_from_x_p0_T_48 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_49 = and(_rs2_can_forward_from_x_p0_T_47, _rs2_can_forward_from_x_p0_T_48) node _rs2_can_forward_from_x_p0_T_50 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_51 = and(_rs2_can_forward_from_x_p0_T_49, _rs2_can_forward_from_x_p0_T_50) node _rs2_can_forward_from_x_p0_T_52 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_53 = and(_rs2_can_forward_from_x_p0_T_51, _rs2_can_forward_from_x_p0_T_52) node _rs2_can_forward_from_x_p0_T_54 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_55 = and(_rs2_can_forward_from_x_p0_T_53, _rs2_can_forward_from_x_p0_T_54) node _rs2_can_forward_from_x_p0_T_56 = and(_rs2_can_forward_from_x_p0_T_34, _rs2_can_forward_from_x_p0_T_55) node _rs2_can_forward_from_x_p0_T_57 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _rs2_can_forward_from_x_p0_T_58 = or(_rs2_can_forward_from_x_p0_T_57, rrd_uops[1].bits.ctrl.jalr) node _rs2_can_forward_from_x_p0_T_59 = eq(_rs2_can_forward_from_x_p0_T_58, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_60 = and(_rs2_can_forward_from_x_p0_T_56, _rs2_can_forward_from_x_p0_T_59) node _rs2_can_forward_from_x_p0_T_61 = eq(rrd_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_62 = and(_rs2_can_forward_from_x_p0_T_60, _rs2_can_forward_from_x_p0_T_61) node _rs2_can_forward_from_x_p0_T_63 = neq(rs2_1, UInt<1>(0h0)) node _rs2_can_forward_from_x_p0_T_64 = and(_rs2_can_forward_from_x_p0_T_62, _rs2_can_forward_from_x_p0_T_63) node _rs2_can_forward_from_x_p0_T_65 = eq(memalu_will_be_latealu_1, UInt<1>(0h0)) node rs2_can_forward_from_x_p0_1 = and(_rs2_can_forward_from_x_p0_T_64, _rs2_can_forward_from_x_p0_T_65) node _rs1_can_forward_from_w_p0_T_31 = and(UInt<1>(0h1), rrd_p0_can_forward_w_to_l) node _rs1_can_forward_from_w_p0_T_32 = and(_rs1_can_forward_from_w_p0_T_31, rs1_w0_hit_1) node _rs1_can_forward_from_w_p0_T_33 = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_34 = and(rrd_uops[1].bits.ctrl.wxd, _rs1_can_forward_from_w_p0_T_33) node _rs1_can_forward_from_w_p0_T_35 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_36 = and(_rs1_can_forward_from_w_p0_T_34, _rs1_can_forward_from_w_p0_T_35) node _rs1_can_forward_from_w_p0_T_37 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_38 = and(_rs1_can_forward_from_w_p0_T_36, _rs1_can_forward_from_w_p0_T_37) node _rs1_can_forward_from_w_p0_T_39 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rs1_can_forward_from_w_p0_T_40 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rs1_can_forward_from_w_p0_T_41 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rs1_can_forward_from_w_p0_T_42 = or(_rs1_can_forward_from_w_p0_T_39, _rs1_can_forward_from_w_p0_T_40) node _rs1_can_forward_from_w_p0_T_43 = or(_rs1_can_forward_from_w_p0_T_42, _rs1_can_forward_from_w_p0_T_41) node _rs1_can_forward_from_w_p0_T_44 = eq(_rs1_can_forward_from_w_p0_T_43, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_45 = and(_rs1_can_forward_from_w_p0_T_38, _rs1_can_forward_from_w_p0_T_44) node _rs1_can_forward_from_w_p0_T_46 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_47 = and(_rs1_can_forward_from_w_p0_T_45, _rs1_can_forward_from_w_p0_T_46) node _rs1_can_forward_from_w_p0_T_48 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_49 = and(_rs1_can_forward_from_w_p0_T_47, _rs1_can_forward_from_w_p0_T_48) node _rs1_can_forward_from_w_p0_T_50 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_51 = and(_rs1_can_forward_from_w_p0_T_49, _rs1_can_forward_from_w_p0_T_50) node _rs1_can_forward_from_w_p0_T_52 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_53 = and(_rs1_can_forward_from_w_p0_T_51, _rs1_can_forward_from_w_p0_T_52) node _rs1_can_forward_from_w_p0_T_54 = and(_rs1_can_forward_from_w_p0_T_32, _rs1_can_forward_from_w_p0_T_53) node _rs1_can_forward_from_w_p0_T_55 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _rs1_can_forward_from_w_p0_T_56 = or(_rs1_can_forward_from_w_p0_T_55, rrd_uops[1].bits.ctrl.jalr) node _rs1_can_forward_from_w_p0_T_57 = eq(_rs1_can_forward_from_w_p0_T_56, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_58 = and(_rs1_can_forward_from_w_p0_T_54, _rs1_can_forward_from_w_p0_T_57) node _rs1_can_forward_from_w_p0_T_59 = eq(rrd_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _rs1_can_forward_from_w_p0_T_60 = and(_rs1_can_forward_from_w_p0_T_58, _rs1_can_forward_from_w_p0_T_59) node _rs1_can_forward_from_w_p0_T_61 = neq(rs1_1, UInt<1>(0h0)) node rs1_can_forward_from_w_p0_1 = and(_rs1_can_forward_from_w_p0_T_60, _rs1_can_forward_from_w_p0_T_61) node _rs2_can_forward_from_w_p0_T_31 = and(UInt<1>(0h1), rrd_p0_can_forward_w_to_l) node _rs2_can_forward_from_w_p0_T_32 = and(_rs2_can_forward_from_w_p0_T_31, rs2_w0_hit_1) node _rs2_can_forward_from_w_p0_T_33 = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_34 = and(rrd_uops[1].bits.ctrl.wxd, _rs2_can_forward_from_w_p0_T_33) node _rs2_can_forward_from_w_p0_T_35 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_36 = and(_rs2_can_forward_from_w_p0_T_34, _rs2_can_forward_from_w_p0_T_35) node _rs2_can_forward_from_w_p0_T_37 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_38 = and(_rs2_can_forward_from_w_p0_T_36, _rs2_can_forward_from_w_p0_T_37) node _rs2_can_forward_from_w_p0_T_39 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rs2_can_forward_from_w_p0_T_40 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rs2_can_forward_from_w_p0_T_41 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rs2_can_forward_from_w_p0_T_42 = or(_rs2_can_forward_from_w_p0_T_39, _rs2_can_forward_from_w_p0_T_40) node _rs2_can_forward_from_w_p0_T_43 = or(_rs2_can_forward_from_w_p0_T_42, _rs2_can_forward_from_w_p0_T_41) node _rs2_can_forward_from_w_p0_T_44 = eq(_rs2_can_forward_from_w_p0_T_43, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_45 = and(_rs2_can_forward_from_w_p0_T_38, _rs2_can_forward_from_w_p0_T_44) node _rs2_can_forward_from_w_p0_T_46 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_47 = and(_rs2_can_forward_from_w_p0_T_45, _rs2_can_forward_from_w_p0_T_46) node _rs2_can_forward_from_w_p0_T_48 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_49 = and(_rs2_can_forward_from_w_p0_T_47, _rs2_can_forward_from_w_p0_T_48) node _rs2_can_forward_from_w_p0_T_50 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_51 = and(_rs2_can_forward_from_w_p0_T_49, _rs2_can_forward_from_w_p0_T_50) node _rs2_can_forward_from_w_p0_T_52 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_53 = and(_rs2_can_forward_from_w_p0_T_51, _rs2_can_forward_from_w_p0_T_52) node _rs2_can_forward_from_w_p0_T_54 = and(_rs2_can_forward_from_w_p0_T_32, _rs2_can_forward_from_w_p0_T_53) node _rs2_can_forward_from_w_p0_T_55 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _rs2_can_forward_from_w_p0_T_56 = or(_rs2_can_forward_from_w_p0_T_55, rrd_uops[1].bits.ctrl.jalr) node _rs2_can_forward_from_w_p0_T_57 = eq(_rs2_can_forward_from_w_p0_T_56, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_58 = and(_rs2_can_forward_from_w_p0_T_54, _rs2_can_forward_from_w_p0_T_57) node _rs2_can_forward_from_w_p0_T_59 = eq(rrd_uops[1].bits.sets_vcfg, UInt<1>(0h0)) node _rs2_can_forward_from_w_p0_T_60 = and(_rs2_can_forward_from_w_p0_T_58, _rs2_can_forward_from_w_p0_T_59) node _rs2_can_forward_from_w_p0_T_61 = neq(rs2_1, UInt<1>(0h0)) node rs2_can_forward_from_w_p0_1 = and(_rs2_can_forward_from_w_p0_T_60, _rs2_can_forward_from_w_p0_T_61) node _rs1_same_hazard_T = eq(rs1_can_forward_from_x_p0_1, UInt<1>(0h0)) node _rs1_same_hazard_T_1 = and(rs1_w0_hit_1, _rs1_same_hazard_T) node _rs1_same_hazard_T_2 = eq(rs1_can_forward_from_w_p0_1, UInt<1>(0h0)) node rs1_same_hazard = and(_rs1_same_hazard_T_1, _rs1_same_hazard_T_2) node _rs2_same_hazard_T = eq(rs2_can_forward_from_x_p0_1, UInt<1>(0h0)) node _rs2_same_hazard_T_1 = and(rs2_w0_hit_1, _rs2_same_hazard_T) node _rs2_same_hazard_T_2 = eq(rs2_can_forward_from_w_p0_1, UInt<1>(0h0)) node rs2_same_hazard = and(_rs2_same_hazard_T_1, _rs2_same_hazard_T_2) node _rd_same_hazard_T = eq(rrd_irf_writes[0].bits, rd_1) node _rd_same_hazard_T_1 = and(rrd_irf_writes[0].valid, _rd_same_hazard_T) node _rd_same_hazard_T_2 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _rd_same_hazard_T_3 = and(rrd_uops[0].bits.ctrl.wxd, _rd_same_hazard_T_2) node _rd_same_hazard_T_4 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _rd_same_hazard_T_5 = and(_rd_same_hazard_T_3, _rd_same_hazard_T_4) node _rd_same_hazard_T_6 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _rd_same_hazard_T_7 = and(_rd_same_hazard_T_5, _rd_same_hazard_T_6) node _rd_same_hazard_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _rd_same_hazard_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _rd_same_hazard_T_10 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _rd_same_hazard_T_11 = or(_rd_same_hazard_T_8, _rd_same_hazard_T_9) node _rd_same_hazard_T_12 = or(_rd_same_hazard_T_11, _rd_same_hazard_T_10) node _rd_same_hazard_T_13 = eq(_rd_same_hazard_T_12, UInt<1>(0h0)) node _rd_same_hazard_T_14 = and(_rd_same_hazard_T_7, _rd_same_hazard_T_13) node _rd_same_hazard_T_15 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _rd_same_hazard_T_16 = and(_rd_same_hazard_T_14, _rd_same_hazard_T_15) node _rd_same_hazard_T_17 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _rd_same_hazard_T_18 = and(_rd_same_hazard_T_16, _rd_same_hazard_T_17) node _rd_same_hazard_T_19 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _rd_same_hazard_T_20 = and(_rd_same_hazard_T_18, _rd_same_hazard_T_19) node _rd_same_hazard_T_21 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _rd_same_hazard_T_22 = and(_rd_same_hazard_T_20, _rd_same_hazard_T_21) node _rd_same_hazard_T_23 = eq(_rd_same_hazard_T_22, UInt<1>(0h0)) node _rd_same_hazard_T_24 = and(_rd_same_hazard_T_1, _rd_same_hazard_T_23) node _rd_same_hazard_T_25 = eq(rrd_uops[1].bits.uses_latealu, UInt<1>(0h0)) node rd_same_hazard = and(_rd_same_hazard_T_24, _rd_same_hazard_T_25) node _rs1_data_hazard_T_3 = or(rs1_older_hazard_1, rs1_same_hazard) node _rs1_data_hazard_T_4 = and(_rs1_data_hazard_T_3, rrd_uops[1].bits.ctrl.rxs1) node _rs1_data_hazard_T_5 = neq(rs1_1, UInt<1>(0h0)) node rs1_data_hazard_1 = and(_rs1_data_hazard_T_4, _rs1_data_hazard_T_5) node _rs2_data_hazard_T_3 = or(rs2_older_hazard_1, rs2_same_hazard) node _rs2_data_hazard_T_4 = and(_rs2_data_hazard_T_3, rrd_uops[1].bits.ctrl.rxs2) node _rs2_data_hazard_T_5 = neq(rs2_1, UInt<1>(0h0)) node rs2_data_hazard_1 = and(_rs2_data_hazard_T_4, _rs2_data_hazard_T_5) node _rd_data_hazard_T_3 = or(rd_older_hazard_1, rd_same_hazard) node _rd_data_hazard_T_4 = and(_rd_data_hazard_T_3, rrd_uops[1].bits.ctrl.wxd) node _rd_data_hazard_T_5 = neq(rd_1, UInt<1>(0h0)) node rd_data_hazard_1 = and(_rd_data_hazard_T_4, _rd_data_hazard_T_5) node _frs1_same_hazard_T_1 = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.wfd) node _frs1_same_hazard_T_2 = bits(rrd_uops[0].bits.inst, 11, 7) node _frs1_same_hazard_T_3 = eq(_frs1_same_hazard_T_2, rs1_1) node _frs1_same_hazard_T_4 = and(_frs1_same_hazard_T_1, _frs1_same_hazard_T_3) node _frs1_same_hazard_T_5 = and(UInt<1>(0h0), _frs1_same_hazard_T_4) node frs1_same_hazard_1 = and(_frs1_same_hazard_T_5, rrd_uops[1].bits.ctrl.rfs1) node _frs2_same_hazard_T_1 = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.wfd) node _frs2_same_hazard_T_2 = bits(rrd_uops[0].bits.inst, 11, 7) node _frs2_same_hazard_T_3 = eq(_frs2_same_hazard_T_2, rs2_1) node _frs2_same_hazard_T_4 = and(_frs2_same_hazard_T_1, _frs2_same_hazard_T_3) node _frs2_same_hazard_T_5 = and(UInt<1>(0h0), _frs2_same_hazard_T_4) node frs2_same_hazard_1 = and(_frs2_same_hazard_T_5, rrd_uops[1].bits.ctrl.rfs2) node _frs3_same_hazard_T_1 = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.wfd) node _frs3_same_hazard_T_2 = bits(rrd_uops[0].bits.inst, 11, 7) node _frs3_same_hazard_T_3 = eq(_frs3_same_hazard_T_2, rs3_1) node _frs3_same_hazard_T_4 = and(_frs3_same_hazard_T_1, _frs3_same_hazard_T_3) node _frs3_same_hazard_T_5 = and(UInt<1>(0h0), _frs3_same_hazard_T_4) node frs3_same_hazard_1 = and(_frs3_same_hazard_T_5, rrd_uops[1].bits.ctrl.rfs3) node _frd_same_hazard_T_1 = and(rrd_uops[0].valid, rrd_uops[0].bits.ctrl.wfd) node _frd_same_hazard_T_2 = bits(rrd_uops[0].bits.inst, 11, 7) node _frd_same_hazard_T_3 = eq(_frd_same_hazard_T_2, rd_1) node _frd_same_hazard_T_4 = and(_frd_same_hazard_T_1, _frd_same_hazard_T_3) node _frd_same_hazard_T_5 = and(UInt<1>(0h0), _frd_same_hazard_T_4) node frd_same_hazard_1 = and(_frd_same_hazard_T_5, rrd_uops[1].bits.ctrl.wfd) node _rrd_stall_data_1_T = or(rs1_data_hazard_1, rs2_data_hazard_1) node _rrd_stall_data_1_T_1 = or(_rrd_stall_data_1_T, rd_data_hazard_1) node _rrd_stall_data_1_T_2 = or(_rrd_stall_data_1_T_1, frs1_same_hazard_1) node _rrd_stall_data_1_T_3 = or(_rrd_stall_data_1_T_2, frs2_same_hazard_1) node _rrd_stall_data_1_T_4 = or(_rrd_stall_data_1_T_3, frs3_same_hazard_1) node _rrd_stall_data_1_T_5 = or(_rrd_stall_data_1_T_4, frd_same_hazard_1) connect rrd_stall_data[1], _rrd_stall_data_1_T_5 node _rrd_uops_1_bits_uses_memalu_T = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_1 = and(rrd_uops[1].bits.ctrl.wxd, _rrd_uops_1_bits_uses_memalu_T) node _rrd_uops_1_bits_uses_memalu_T_2 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_3 = and(_rrd_uops_1_bits_uses_memalu_T_1, _rrd_uops_1_bits_uses_memalu_T_2) node _rrd_uops_1_bits_uses_memalu_T_4 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_5 = and(_rrd_uops_1_bits_uses_memalu_T_3, _rrd_uops_1_bits_uses_memalu_T_4) node _rrd_uops_1_bits_uses_memalu_T_6 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rrd_uops_1_bits_uses_memalu_T_7 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rrd_uops_1_bits_uses_memalu_T_8 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rrd_uops_1_bits_uses_memalu_T_9 = or(_rrd_uops_1_bits_uses_memalu_T_6, _rrd_uops_1_bits_uses_memalu_T_7) node _rrd_uops_1_bits_uses_memalu_T_10 = or(_rrd_uops_1_bits_uses_memalu_T_9, _rrd_uops_1_bits_uses_memalu_T_8) node _rrd_uops_1_bits_uses_memalu_T_11 = eq(_rrd_uops_1_bits_uses_memalu_T_10, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_12 = and(_rrd_uops_1_bits_uses_memalu_T_5, _rrd_uops_1_bits_uses_memalu_T_11) node _rrd_uops_1_bits_uses_memalu_T_13 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_14 = and(_rrd_uops_1_bits_uses_memalu_T_12, _rrd_uops_1_bits_uses_memalu_T_13) node _rrd_uops_1_bits_uses_memalu_T_15 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_16 = and(_rrd_uops_1_bits_uses_memalu_T_14, _rrd_uops_1_bits_uses_memalu_T_15) node _rrd_uops_1_bits_uses_memalu_T_17 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_18 = and(_rrd_uops_1_bits_uses_memalu_T_16, _rrd_uops_1_bits_uses_memalu_T_17) node _rrd_uops_1_bits_uses_memalu_T_19 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_20 = and(_rrd_uops_1_bits_uses_memalu_T_18, _rrd_uops_1_bits_uses_memalu_T_19) node _rrd_uops_1_bits_uses_memalu_T_21 = and(rs1_w0_hit_1, rs1_can_forward_from_x_p0_1) node _rrd_uops_1_bits_uses_memalu_T_22 = and(rs2_w0_hit_1, rs2_can_forward_from_x_p0_1) node _rrd_uops_1_bits_uses_memalu_T_23 = or(_rrd_uops_1_bits_uses_memalu_T_21, _rrd_uops_1_bits_uses_memalu_T_22) node _rrd_uops_1_bits_uses_memalu_T_24 = and(_rrd_uops_1_bits_uses_memalu_T_20, _rrd_uops_1_bits_uses_memalu_T_23) node _rrd_uops_1_bits_uses_memalu_T_25 = and(_rrd_uops_1_bits_uses_memalu_T_24, UInt<1>(0h1)) node _rrd_uops_1_bits_uses_memalu_T_26 = eq(sfb_shadow_1, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_memalu_T_27 = and(_rrd_uops_1_bits_uses_memalu_T_25, _rrd_uops_1_bits_uses_memalu_T_26) connect rrd_uops[1].bits.uses_memalu, _rrd_uops_1_bits_uses_memalu_T_27 node _rrd_uops_1_bits_uses_latealu_T = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_1 = and(rrd_uops[1].bits.ctrl.wxd, _rrd_uops_1_bits_uses_latealu_T) node _rrd_uops_1_bits_uses_latealu_T_2 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_3 = and(_rrd_uops_1_bits_uses_latealu_T_1, _rrd_uops_1_bits_uses_latealu_T_2) node _rrd_uops_1_bits_uses_latealu_T_4 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_5 = and(_rrd_uops_1_bits_uses_latealu_T_3, _rrd_uops_1_bits_uses_latealu_T_4) node _rrd_uops_1_bits_uses_latealu_T_6 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _rrd_uops_1_bits_uses_latealu_T_7 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _rrd_uops_1_bits_uses_latealu_T_8 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _rrd_uops_1_bits_uses_latealu_T_9 = or(_rrd_uops_1_bits_uses_latealu_T_6, _rrd_uops_1_bits_uses_latealu_T_7) node _rrd_uops_1_bits_uses_latealu_T_10 = or(_rrd_uops_1_bits_uses_latealu_T_9, _rrd_uops_1_bits_uses_latealu_T_8) node _rrd_uops_1_bits_uses_latealu_T_11 = eq(_rrd_uops_1_bits_uses_latealu_T_10, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_12 = and(_rrd_uops_1_bits_uses_latealu_T_5, _rrd_uops_1_bits_uses_latealu_T_11) node _rrd_uops_1_bits_uses_latealu_T_13 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_14 = and(_rrd_uops_1_bits_uses_latealu_T_12, _rrd_uops_1_bits_uses_latealu_T_13) node _rrd_uops_1_bits_uses_latealu_T_15 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_16 = and(_rrd_uops_1_bits_uses_latealu_T_14, _rrd_uops_1_bits_uses_latealu_T_15) node _rrd_uops_1_bits_uses_latealu_T_17 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_18 = and(_rrd_uops_1_bits_uses_latealu_T_16, _rrd_uops_1_bits_uses_latealu_T_17) node _rrd_uops_1_bits_uses_latealu_T_19 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_20 = and(_rrd_uops_1_bits_uses_latealu_T_18, _rrd_uops_1_bits_uses_latealu_T_19) node _rrd_uops_1_bits_uses_latealu_T_21 = and(rs1_w0_hit_1, rs1_can_forward_from_w_p0_1) node _rrd_uops_1_bits_uses_latealu_T_22 = and(rs2_w0_hit_1, rs2_can_forward_from_w_p0_1) node _rrd_uops_1_bits_uses_latealu_T_23 = or(_rrd_uops_1_bits_uses_latealu_T_21, _rrd_uops_1_bits_uses_latealu_T_22) node _rrd_uops_1_bits_uses_latealu_T_24 = and(_rrd_uops_1_bits_uses_latealu_T_20, _rrd_uops_1_bits_uses_latealu_T_23) node _rrd_uops_1_bits_uses_latealu_T_25 = and(_rrd_uops_1_bits_uses_latealu_T_24, UInt<1>(0h1)) node _rrd_uops_1_bits_uses_latealu_T_26 = eq(sfb_shadow_1, UInt<1>(0h0)) node _rrd_uops_1_bits_uses_latealu_T_27 = and(_rrd_uops_1_bits_uses_latealu_T_25, _rrd_uops_1_bits_uses_latealu_T_26) connect rrd_uops[1].bits.uses_latealu, _rrd_uops_1_bits_uses_latealu_T_27 connect rrd_uops[1].bits.sfb_shadow, sfb_shadow_1 node _rrd_irf_writes_1_valid_T = and(rrd_uops[1].valid, rrd_uops[1].bits.ctrl.wxd) connect rrd_irf_writes[1].valid, _rrd_irf_writes_1_valid_T node _rrd_irf_writes_1_bits_T = bits(rrd_uops[1].bits.inst, 11, 7) connect rrd_irf_writes[1].bits, _rrd_irf_writes_1_bits_T node _T_108 = and(rrd_uops[1].valid, rrd_uops[1].bits.ctrl.fp) when _T_108 : when rrd_uops[1].bits.fp_ctrl.ren1 : node _T_109 = eq(rrd_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) when _T_109 : node _rrd_uops_1_bits_fra1_T = bits(rrd_uops[1].bits.inst, 19, 15) connect rrd_uops[1].bits.fra1, _rrd_uops_1_bits_fra1_T when rrd_uops[1].bits.fp_ctrl.swap12 : node _rrd_uops_1_bits_fra2_T = bits(rrd_uops[1].bits.inst, 19, 15) connect rrd_uops[1].bits.fra2, _rrd_uops_1_bits_fra2_T when rrd_uops[1].bits.fp_ctrl.ren2 : when rrd_uops[1].bits.fp_ctrl.swap12 : node _rrd_uops_1_bits_fra1_T_1 = bits(rrd_uops[1].bits.inst, 24, 20) connect rrd_uops[1].bits.fra1, _rrd_uops_1_bits_fra1_T_1 when rrd_uops[1].bits.fp_ctrl.swap23 : node _rrd_uops_1_bits_fra3_T = bits(rrd_uops[1].bits.inst, 24, 20) connect rrd_uops[1].bits.fra3, _rrd_uops_1_bits_fra3_T node _T_110 = eq(rrd_uops[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _T_111 = eq(rrd_uops[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _T_112 = and(_T_110, _T_111) when _T_112 : node _rrd_uops_1_bits_fra2_T_1 = bits(rrd_uops[1].bits.inst, 24, 20) connect rrd_uops[1].bits.fra2, _rrd_uops_1_bits_fra2_T_1 when rrd_uops[1].bits.fp_ctrl.ren3 : node _rrd_uops_1_bits_fra3_T_1 = bits(rrd_uops[1].bits.inst, 31, 27) connect rrd_uops[1].bits.fra3, _rrd_uops_1_bits_fra3_T_1 node _T_113 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _T_114 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<3>(0h5)) node _T_115 = or(_T_113, _T_114) when _T_115 : node _rrd_uops_1_bits_mem_size_T = neq(rs2_1, UInt<1>(0h0)) node _rrd_uops_1_bits_mem_size_T_1 = neq(rs1_1, UInt<1>(0h0)) node _rrd_uops_1_bits_mem_size_T_2 = cat(_rrd_uops_1_bits_mem_size_T, _rrd_uops_1_bits_mem_size_T_1) connect rrd_uops[1].bits.mem_size, _rrd_uops_1_bits_mem_size_T_2 wire fsboard_bsy : UInt<1> node _amo_fence_T = bits(rrd_uops[0].bits.inst, 26, 25) node _amo_fence_T_1 = neq(_amo_fence_T, UInt<1>(0h0)) node amo_fence = and(rrd_uops[0].bits.ctrl.amo, _amo_fence_T_1) node _rrd_fence_stall_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h4)) node _rrd_fence_stall_T_1 = or(_rrd_fence_stall_T, rrd_uops[0].bits.ctrl.fence) node _rrd_fence_stall_T_2 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _rrd_fence_stall_T_3 = and(rrd_uops[0].bits.ctrl.mem, _rrd_fence_stall_T_2) node _rrd_fence_stall_T_4 = or(_rrd_fence_stall_T_1, _rrd_fence_stall_T_3) node _rrd_fence_stall_T_5 = or(_rrd_fence_stall_T_4, rrd_uops[0].bits.ctrl.fence_i) node _rrd_fence_stall_T_6 = or(_rrd_fence_stall_T_5, amo_fence) node _rrd_fence_stall_T_7 = or(ex_bsy, mem_bsy) node _rrd_fence_stall_T_8 = or(_rrd_fence_stall_T_7, com_bsy) node _rrd_fence_stall_T_9 = or(_rrd_fence_stall_T_8, isboard_bsy) node _rrd_fence_stall_T_10 = or(_rrd_fence_stall_T_9, fsboard_bsy) node _rrd_fence_stall_T_11 = eq(io.dmem.ordered, UInt<1>(0h0)) node _rrd_fence_stall_T_12 = or(_rrd_fence_stall_T_10, _rrd_fence_stall_T_11) node _rrd_fence_stall_T_13 = or(_rrd_fence_stall_T_12, io.rocc.busy) node _rrd_fence_stall_T_14 = or(_rrd_fence_stall_T_13, UInt<1>(0h0)) node _rrd_fence_stall_T_15 = and(_rrd_fence_stall_T_6, _rrd_fence_stall_T_14) node rrd_fence_stall = and(UInt<1>(0h1), _rrd_fence_stall_T_15) node _rrd_rocc_stall_T = and(UInt<1>(0h1), rrd_uops[0].bits.ctrl.rocc) node _rrd_rocc_stall_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node rrd_rocc_stall = and(_rrd_rocc_stall_T, _rrd_rocc_stall_T_1) node _brjmp_T = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _brjmp_T_1 = or(_brjmp_T, rrd_uops[0].bits.ctrl.jalr) node _brjmp_T_2 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _brjmp_T_3 = and(rrd_uops[0].bits.ctrl.mem, _brjmp_T_2) node _brjmp_T_4 = or(_brjmp_T_1, _brjmp_T_3) node brjmp = or(_brjmp_T_4, rrd_uops[0].bits.next_pc.valid) node _is_pipe0_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h4)) node _is_pipe0_T_1 = eq(rrd_uops[0].bits.ctrl.mem, UInt<1>(0h0)) node _is_pipe0_T_2 = and(rrd_uops[0].bits.ctrl.wxd, _is_pipe0_T_1) node _is_pipe0_T_3 = eq(rrd_uops[0].bits.ctrl.div, UInt<1>(0h0)) node _is_pipe0_T_4 = and(_is_pipe0_T_2, _is_pipe0_T_3) node _is_pipe0_T_5 = eq(rrd_uops[0].bits.ctrl.mul, UInt<1>(0h0)) node _is_pipe0_T_6 = and(_is_pipe0_T_4, _is_pipe0_T_5) node _is_pipe0_T_7 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _is_pipe0_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _is_pipe0_T_9 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _is_pipe0_T_10 = or(_is_pipe0_T_7, _is_pipe0_T_8) node _is_pipe0_T_11 = or(_is_pipe0_T_10, _is_pipe0_T_9) node _is_pipe0_T_12 = eq(_is_pipe0_T_11, UInt<1>(0h0)) node _is_pipe0_T_13 = and(_is_pipe0_T_6, _is_pipe0_T_12) node _is_pipe0_T_14 = eq(rrd_uops[0].bits.ctrl.fp, UInt<1>(0h0)) node _is_pipe0_T_15 = and(_is_pipe0_T_13, _is_pipe0_T_14) node _is_pipe0_T_16 = eq(rrd_uops[0].bits.ctrl.rocc, UInt<1>(0h0)) node _is_pipe0_T_17 = and(_is_pipe0_T_15, _is_pipe0_T_16) node _is_pipe0_T_18 = eq(rrd_uops[0].bits.ctrl.jalr, UInt<1>(0h0)) node _is_pipe0_T_19 = and(_is_pipe0_T_17, _is_pipe0_T_18) node _is_pipe0_T_20 = eq(rrd_uops[0].bits.ctrl.vec, UInt<1>(0h0)) node _is_pipe0_T_21 = and(_is_pipe0_T_19, _is_pipe0_T_20) node _is_pipe0_T_22 = eq(_is_pipe0_T_21, UInt<1>(0h0)) node _is_pipe0_T_23 = or(rrd_uops[0].bits.ctrl.branch, rrd_uops[0].bits.ctrl.jal) node _is_pipe0_T_24 = or(_is_pipe0_T_23, rrd_uops[0].bits.ctrl.jalr) node _is_pipe0_T_25 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _is_pipe0_T_26 = and(rrd_uops[0].bits.ctrl.mem, _is_pipe0_T_25) node _is_pipe0_T_27 = or(_is_pipe0_T_24, _is_pipe0_T_26) node _is_pipe0_T_28 = or(_is_pipe0_T_22, _is_pipe0_T_27) node _is_pipe0_T_29 = and(rrd_uops[0].bits.sfb_shadow, _is_pipe0_T_28) node _is_pipe0_T_30 = or(_is_pipe0_T, _is_pipe0_T_29) node _is_pipe0_T_31 = eq(rrd_uops[0].bits.rvc, UInt<1>(0h0)) node _is_pipe0_T_32 = and(rrd_uops[0].bits.sfb_shadow, _is_pipe0_T_31) node _is_pipe0_T_33 = or(_is_pipe0_T_30, _is_pipe0_T_32) node _is_pipe0_T_34 = or(_is_pipe0_T_33, rrd_uops[0].bits.sfb_br) node _is_pipe0_T_35 = or(_is_pipe0_T_34, rrd_uops[0].bits.ctrl.vec) node _is_pipe0_T_36 = and(UInt<1>(0h0), rrd_uops[0].bits.sets_vcfg) node _is_pipe0_T_37 = or(_is_pipe0_T_35, _is_pipe0_T_36) node _is_pipe0_T_38 = or(_is_pipe0_T_37, rrd_uops[0].bits.ctrl.fence) node _is_pipe0_T_39 = or(_is_pipe0_T_38, rrd_uops[0].bits.ctrl.amo) node _is_pipe0_T_40 = or(_is_pipe0_T_39, rrd_uops[0].bits.ctrl.fence_i) node _is_pipe0_T_41 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _is_pipe0_T_42 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _is_pipe0_T_43 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _is_pipe0_T_44 = or(_is_pipe0_T_41, _is_pipe0_T_42) node _is_pipe0_T_45 = or(_is_pipe0_T_44, _is_pipe0_T_43) node _is_pipe0_T_46 = or(_is_pipe0_T_40, _is_pipe0_T_45) node _is_pipe0_T_47 = eq(rrd_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _is_pipe0_T_48 = and(rrd_uops[0].bits.ctrl.mem, _is_pipe0_T_47) node _is_pipe0_T_49 = or(_is_pipe0_T_46, _is_pipe0_T_48) node _is_pipe0_T_50 = neq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h0)) node _is_pipe0_T_51 = or(_is_pipe0_T_49, _is_pipe0_T_50) node _is_pipe0_T_52 = or(_is_pipe0_T_51, rrd_uops[0].bits.xcpt) node _is_pipe0_T_53 = or(_is_pipe0_T_52, rrd_uops[0].bits.ctrl.mul) node _is_pipe0_T_54 = or(_is_pipe0_T_53, rrd_uops[0].bits.ctrl.div) node _is_pipe0_T_55 = or(_is_pipe0_T_54, rrd_uops[0].bits.ctrl.rocc) node _is_pipe0_T_56 = and(rrd_uops[0].bits.fp_ctrl.ldst, rrd_uops[0].bits.fp_ctrl.wen) node _is_pipe0_T_57 = eq(_is_pipe0_T_56, UInt<1>(0h0)) node _is_pipe0_T_58 = and(rrd_uops[0].bits.ctrl.fp, _is_pipe0_T_57) node is_pipe0 = or(_is_pipe0_T_55, _is_pipe0_T_58) node _is_youngest_T = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _is_youngest_T_1 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _is_youngest_T_2 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _is_youngest_T_3 = or(_is_youngest_T, _is_youngest_T_1) node _is_youngest_T_4 = or(_is_youngest_T_3, _is_youngest_T_2) node _is_youngest_T_5 = or(rrd_uops[0].bits.xcpt, _is_youngest_T_4) node _is_youngest_T_6 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h4)) node is_youngest = or(_is_youngest_T_5, _is_youngest_T_6) node _rrd_stall_0_T = or(rrd_stall_data[0], rrd_fence_stall) node _rrd_stall_0_T_1 = or(_rrd_stall_0_T, rrd_rocc_stall) node _rrd_stall_0_T_2 = and(is_pipe0, UInt<1>(0h0)) node _rrd_stall_0_T_3 = or(_rrd_stall_0_T_1, _rrd_stall_0_T_2) node _rrd_stall_0_T_4 = and(UInt<1>(0h0), rrd_uops[0].bits.ctrl.mem) node _rrd_stall_0_T_5 = or(_rrd_stall_0_T_3, _rrd_stall_0_T_4) node _rrd_stall_0_T_6 = and(UInt<1>(0h0), rrd_uops[0].bits.sets_vcfg) node _rrd_stall_0_T_7 = or(_rrd_stall_0_T_5, _rrd_stall_0_T_6) node _rrd_stall_0_T_8 = and(UInt<1>(0h0), brjmp) node _rrd_stall_0_T_9 = or(_rrd_stall_0_T_7, _rrd_stall_0_T_8) node _rrd_stall_0_T_10 = or(_rrd_stall_0_T_9, UInt<1>(0h0)) node _rrd_stall_0_T_11 = or(_rrd_stall_0_T_10, csr.io.csr_stall) node _rrd_stall_0_T_12 = or(_rrd_stall_0_T_11, ex_stall) connect rrd_stall[0], _rrd_stall_0_T_12 node _T_116 = or(rrd_stall[0], is_youngest) node _T_117 = or(UInt<1>(0h0), rrd_uops[0].bits.ctrl.mem) node _T_118 = or(UInt<1>(0h0), brjmp) node _T_119 = or(UInt<1>(0h0), rrd_uops[0].bits.sets_vcfg) node _amo_fence_T_2 = bits(rrd_uops[1].bits.inst, 26, 25) node _amo_fence_T_3 = neq(_amo_fence_T_2, UInt<1>(0h0)) node amo_fence_1 = and(rrd_uops[1].bits.ctrl.amo, _amo_fence_T_3) node _rrd_fence_stall_T_16 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h4)) node _rrd_fence_stall_T_17 = or(_rrd_fence_stall_T_16, rrd_uops[1].bits.ctrl.fence) node _rrd_fence_stall_T_18 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _rrd_fence_stall_T_19 = and(rrd_uops[1].bits.ctrl.mem, _rrd_fence_stall_T_18) node _rrd_fence_stall_T_20 = or(_rrd_fence_stall_T_17, _rrd_fence_stall_T_19) node _rrd_fence_stall_T_21 = or(_rrd_fence_stall_T_20, rrd_uops[1].bits.ctrl.fence_i) node _rrd_fence_stall_T_22 = or(_rrd_fence_stall_T_21, amo_fence_1) node _rrd_fence_stall_T_23 = or(ex_bsy, mem_bsy) node _rrd_fence_stall_T_24 = or(_rrd_fence_stall_T_23, com_bsy) node _rrd_fence_stall_T_25 = or(_rrd_fence_stall_T_24, isboard_bsy) node _rrd_fence_stall_T_26 = or(_rrd_fence_stall_T_25, fsboard_bsy) node _rrd_fence_stall_T_27 = eq(io.dmem.ordered, UInt<1>(0h0)) node _rrd_fence_stall_T_28 = or(_rrd_fence_stall_T_26, _rrd_fence_stall_T_27) node _rrd_fence_stall_T_29 = or(_rrd_fence_stall_T_28, io.rocc.busy) node _rrd_fence_stall_T_30 = or(_rrd_fence_stall_T_29, UInt<1>(0h0)) node _rrd_fence_stall_T_31 = and(_rrd_fence_stall_T_22, _rrd_fence_stall_T_30) node rrd_fence_stall_1 = and(UInt<1>(0h0), _rrd_fence_stall_T_31) node _rrd_rocc_stall_T_2 = and(UInt<1>(0h0), rrd_uops[1].bits.ctrl.rocc) node _rrd_rocc_stall_T_3 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node rrd_rocc_stall_1 = and(_rrd_rocc_stall_T_2, _rrd_rocc_stall_T_3) node _brjmp_T_5 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _brjmp_T_6 = or(_brjmp_T_5, rrd_uops[1].bits.ctrl.jalr) node _brjmp_T_7 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _brjmp_T_8 = and(rrd_uops[1].bits.ctrl.mem, _brjmp_T_7) node _brjmp_T_9 = or(_brjmp_T_6, _brjmp_T_8) node brjmp_1 = or(_brjmp_T_9, rrd_uops[1].bits.next_pc.valid) node _is_pipe0_T_59 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h4)) node _is_pipe0_T_60 = eq(rrd_uops[1].bits.ctrl.mem, UInt<1>(0h0)) node _is_pipe0_T_61 = and(rrd_uops[1].bits.ctrl.wxd, _is_pipe0_T_60) node _is_pipe0_T_62 = eq(rrd_uops[1].bits.ctrl.div, UInt<1>(0h0)) node _is_pipe0_T_63 = and(_is_pipe0_T_61, _is_pipe0_T_62) node _is_pipe0_T_64 = eq(rrd_uops[1].bits.ctrl.mul, UInt<1>(0h0)) node _is_pipe0_T_65 = and(_is_pipe0_T_63, _is_pipe0_T_64) node _is_pipe0_T_66 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _is_pipe0_T_67 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _is_pipe0_T_68 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _is_pipe0_T_69 = or(_is_pipe0_T_66, _is_pipe0_T_67) node _is_pipe0_T_70 = or(_is_pipe0_T_69, _is_pipe0_T_68) node _is_pipe0_T_71 = eq(_is_pipe0_T_70, UInt<1>(0h0)) node _is_pipe0_T_72 = and(_is_pipe0_T_65, _is_pipe0_T_71) node _is_pipe0_T_73 = eq(rrd_uops[1].bits.ctrl.fp, UInt<1>(0h0)) node _is_pipe0_T_74 = and(_is_pipe0_T_72, _is_pipe0_T_73) node _is_pipe0_T_75 = eq(rrd_uops[1].bits.ctrl.rocc, UInt<1>(0h0)) node _is_pipe0_T_76 = and(_is_pipe0_T_74, _is_pipe0_T_75) node _is_pipe0_T_77 = eq(rrd_uops[1].bits.ctrl.jalr, UInt<1>(0h0)) node _is_pipe0_T_78 = and(_is_pipe0_T_76, _is_pipe0_T_77) node _is_pipe0_T_79 = eq(rrd_uops[1].bits.ctrl.vec, UInt<1>(0h0)) node _is_pipe0_T_80 = and(_is_pipe0_T_78, _is_pipe0_T_79) node _is_pipe0_T_81 = eq(_is_pipe0_T_80, UInt<1>(0h0)) node _is_pipe0_T_82 = or(rrd_uops[1].bits.ctrl.branch, rrd_uops[1].bits.ctrl.jal) node _is_pipe0_T_83 = or(_is_pipe0_T_82, rrd_uops[1].bits.ctrl.jalr) node _is_pipe0_T_84 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _is_pipe0_T_85 = and(rrd_uops[1].bits.ctrl.mem, _is_pipe0_T_84) node _is_pipe0_T_86 = or(_is_pipe0_T_83, _is_pipe0_T_85) node _is_pipe0_T_87 = or(_is_pipe0_T_81, _is_pipe0_T_86) node _is_pipe0_T_88 = and(rrd_uops[1].bits.sfb_shadow, _is_pipe0_T_87) node _is_pipe0_T_89 = or(_is_pipe0_T_59, _is_pipe0_T_88) node _is_pipe0_T_90 = eq(rrd_uops[1].bits.rvc, UInt<1>(0h0)) node _is_pipe0_T_91 = and(rrd_uops[1].bits.sfb_shadow, _is_pipe0_T_90) node _is_pipe0_T_92 = or(_is_pipe0_T_89, _is_pipe0_T_91) node _is_pipe0_T_93 = or(_is_pipe0_T_92, rrd_uops[1].bits.sfb_br) node _is_pipe0_T_94 = or(_is_pipe0_T_93, rrd_uops[1].bits.ctrl.vec) node _is_pipe0_T_95 = and(UInt<1>(0h0), rrd_uops[1].bits.sets_vcfg) node _is_pipe0_T_96 = or(_is_pipe0_T_94, _is_pipe0_T_95) node _is_pipe0_T_97 = or(_is_pipe0_T_96, rrd_uops[1].bits.ctrl.fence) node _is_pipe0_T_98 = or(_is_pipe0_T_97, rrd_uops[1].bits.ctrl.amo) node _is_pipe0_T_99 = or(_is_pipe0_T_98, rrd_uops[1].bits.ctrl.fence_i) node _is_pipe0_T_100 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _is_pipe0_T_101 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _is_pipe0_T_102 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _is_pipe0_T_103 = or(_is_pipe0_T_100, _is_pipe0_T_101) node _is_pipe0_T_104 = or(_is_pipe0_T_103, _is_pipe0_T_102) node _is_pipe0_T_105 = or(_is_pipe0_T_99, _is_pipe0_T_104) node _is_pipe0_T_106 = eq(rrd_uops[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _is_pipe0_T_107 = and(rrd_uops[1].bits.ctrl.mem, _is_pipe0_T_106) node _is_pipe0_T_108 = or(_is_pipe0_T_105, _is_pipe0_T_107) node _is_pipe0_T_109 = neq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h0)) node _is_pipe0_T_110 = or(_is_pipe0_T_108, _is_pipe0_T_109) node _is_pipe0_T_111 = or(_is_pipe0_T_110, rrd_uops[1].bits.xcpt) node _is_pipe0_T_112 = or(_is_pipe0_T_111, rrd_uops[1].bits.ctrl.mul) node _is_pipe0_T_113 = or(_is_pipe0_T_112, rrd_uops[1].bits.ctrl.div) node _is_pipe0_T_114 = or(_is_pipe0_T_113, rrd_uops[1].bits.ctrl.rocc) node _is_pipe0_T_115 = and(rrd_uops[1].bits.fp_ctrl.ldst, rrd_uops[1].bits.fp_ctrl.wen) node _is_pipe0_T_116 = eq(_is_pipe0_T_115, UInt<1>(0h0)) node _is_pipe0_T_117 = and(rrd_uops[1].bits.ctrl.fp, _is_pipe0_T_116) node is_pipe0_1 = or(_is_pipe0_T_114, _is_pipe0_T_117) node _is_youngest_T_7 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _is_youngest_T_8 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _is_youngest_T_9 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _is_youngest_T_10 = or(_is_youngest_T_7, _is_youngest_T_8) node _is_youngest_T_11 = or(_is_youngest_T_10, _is_youngest_T_9) node _is_youngest_T_12 = or(rrd_uops[1].bits.xcpt, _is_youngest_T_11) node _is_youngest_T_13 = eq(rrd_uops[1].bits.ctrl.csr, UInt<3>(0h4)) node is_youngest_1 = or(_is_youngest_T_12, _is_youngest_T_13) node _rrd_stall_1_T = or(rrd_stall_data[1], rrd_fence_stall_1) node _rrd_stall_1_T_1 = or(_rrd_stall_1_T, rrd_rocc_stall_1) node _rrd_stall_1_T_2 = and(is_pipe0_1, UInt<1>(0h1)) node _rrd_stall_1_T_3 = or(_rrd_stall_1_T_1, _rrd_stall_1_T_2) node _rrd_stall_1_T_4 = and(_T_117, rrd_uops[1].bits.ctrl.mem) node _rrd_stall_1_T_5 = or(_rrd_stall_1_T_3, _rrd_stall_1_T_4) node _rrd_stall_1_T_6 = and(_T_119, rrd_uops[1].bits.sets_vcfg) node _rrd_stall_1_T_7 = or(_rrd_stall_1_T_5, _rrd_stall_1_T_6) node _rrd_stall_1_T_8 = and(_T_118, brjmp_1) node _rrd_stall_1_T_9 = or(_rrd_stall_1_T_7, _rrd_stall_1_T_8) node _rrd_stall_1_T_10 = or(_rrd_stall_1_T_9, _T_116) node _rrd_stall_1_T_11 = or(_rrd_stall_1_T_10, csr.io.csr_stall) node _rrd_stall_1_T_12 = or(_rrd_stall_1_T_11, ex_stall) connect rrd_stall[1], _rrd_stall_1_T_12 node _T_120 = or(rrd_stall[1], is_youngest_1) node _T_121 = or(_T_117, rrd_uops[1].bits.ctrl.mem) node _T_122 = or(_T_118, brjmp_1) node _T_123 = or(_T_119, rrd_uops[1].bits.sets_vcfg) node _io_imem_redirect_flush_T = eq(rrd_stall[0], UInt<1>(0h0)) node _io_imem_redirect_flush_T_1 = and(rrd_uops[0].valid, _io_imem_redirect_flush_T) node _io_imem_redirect_flush_T_2 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _io_imem_redirect_flush_T_3 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _io_imem_redirect_flush_T_4 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _io_imem_redirect_flush_T_5 = or(_io_imem_redirect_flush_T_2, _io_imem_redirect_flush_T_3) node _io_imem_redirect_flush_T_6 = or(_io_imem_redirect_flush_T_5, _io_imem_redirect_flush_T_4) node _io_imem_redirect_flush_T_7 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _io_imem_redirect_flush_T_8 = eq(rrd_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _io_imem_redirect_flush_T_9 = or(_io_imem_redirect_flush_T_7, _io_imem_redirect_flush_T_8) node _io_imem_redirect_flush_T_10 = bits(rrd_uops[0].bits.inst, 19, 15) node _io_imem_redirect_flush_T_11 = eq(_io_imem_redirect_flush_T_10, UInt<1>(0h0)) node _io_imem_redirect_flush_T_12 = and(_io_imem_redirect_flush_T_9, _io_imem_redirect_flush_T_11) node _io_imem_redirect_flush_T_13 = eq(_io_imem_redirect_flush_T_12, UInt<1>(0h0)) node _io_imem_redirect_flush_T_14 = and(_io_imem_redirect_flush_T_6, _io_imem_redirect_flush_T_13) node _io_imem_redirect_flush_T_15 = and(_io_imem_redirect_flush_T_1, _io_imem_redirect_flush_T_14) connect io.imem.redirect_flush, _io_imem_redirect_flush_T_15 reg fregfile : UInt<65>[32], clock reg fsboard : UInt<1>[32], clock node _fsboard_bsy_T = and(fsboard[0], fsboard[1]) node _fsboard_bsy_T_1 = and(_fsboard_bsy_T, fsboard[2]) node _fsboard_bsy_T_2 = and(_fsboard_bsy_T_1, fsboard[3]) node _fsboard_bsy_T_3 = and(_fsboard_bsy_T_2, fsboard[4]) node _fsboard_bsy_T_4 = and(_fsboard_bsy_T_3, fsboard[5]) node _fsboard_bsy_T_5 = and(_fsboard_bsy_T_4, fsboard[6]) node _fsboard_bsy_T_6 = and(_fsboard_bsy_T_5, fsboard[7]) node _fsboard_bsy_T_7 = and(_fsboard_bsy_T_6, fsboard[8]) node _fsboard_bsy_T_8 = and(_fsboard_bsy_T_7, fsboard[9]) node _fsboard_bsy_T_9 = and(_fsboard_bsy_T_8, fsboard[10]) node _fsboard_bsy_T_10 = and(_fsboard_bsy_T_9, fsboard[11]) node _fsboard_bsy_T_11 = and(_fsboard_bsy_T_10, fsboard[12]) node _fsboard_bsy_T_12 = and(_fsboard_bsy_T_11, fsboard[13]) node _fsboard_bsy_T_13 = and(_fsboard_bsy_T_12, fsboard[14]) node _fsboard_bsy_T_14 = and(_fsboard_bsy_T_13, fsboard[15]) node _fsboard_bsy_T_15 = and(_fsboard_bsy_T_14, fsboard[16]) node _fsboard_bsy_T_16 = and(_fsboard_bsy_T_15, fsboard[17]) node _fsboard_bsy_T_17 = and(_fsboard_bsy_T_16, fsboard[18]) node _fsboard_bsy_T_18 = and(_fsboard_bsy_T_17, fsboard[19]) node _fsboard_bsy_T_19 = and(_fsboard_bsy_T_18, fsboard[20]) node _fsboard_bsy_T_20 = and(_fsboard_bsy_T_19, fsboard[21]) node _fsboard_bsy_T_21 = and(_fsboard_bsy_T_20, fsboard[22]) node _fsboard_bsy_T_22 = and(_fsboard_bsy_T_21, fsboard[23]) node _fsboard_bsy_T_23 = and(_fsboard_bsy_T_22, fsboard[24]) node _fsboard_bsy_T_24 = and(_fsboard_bsy_T_23, fsboard[25]) node _fsboard_bsy_T_25 = and(_fsboard_bsy_T_24, fsboard[26]) node _fsboard_bsy_T_26 = and(_fsboard_bsy_T_25, fsboard[27]) node _fsboard_bsy_T_27 = and(_fsboard_bsy_T_26, fsboard[28]) node _fsboard_bsy_T_28 = and(_fsboard_bsy_T_27, fsboard[29]) node _fsboard_bsy_T_29 = and(_fsboard_bsy_T_28, fsboard[30]) node _fsboard_bsy_T_30 = and(_fsboard_bsy_T_29, fsboard[31]) node _fsboard_bsy_T_31 = eq(_fsboard_bsy_T_30, UInt<1>(0h0)) connect fsboard_bsy, _fsboard_bsy_T_31 wire _fsboard_set_WIRE : UInt<1>[32] connect _fsboard_set_WIRE[0], UInt<1>(0h0) connect _fsboard_set_WIRE[1], UInt<1>(0h0) connect _fsboard_set_WIRE[2], UInt<1>(0h0) connect _fsboard_set_WIRE[3], UInt<1>(0h0) connect _fsboard_set_WIRE[4], UInt<1>(0h0) connect _fsboard_set_WIRE[5], UInt<1>(0h0) connect _fsboard_set_WIRE[6], UInt<1>(0h0) connect _fsboard_set_WIRE[7], UInt<1>(0h0) connect _fsboard_set_WIRE[8], UInt<1>(0h0) connect _fsboard_set_WIRE[9], UInt<1>(0h0) connect _fsboard_set_WIRE[10], UInt<1>(0h0) connect _fsboard_set_WIRE[11], UInt<1>(0h0) connect _fsboard_set_WIRE[12], UInt<1>(0h0) connect _fsboard_set_WIRE[13], UInt<1>(0h0) connect _fsboard_set_WIRE[14], UInt<1>(0h0) connect _fsboard_set_WIRE[15], UInt<1>(0h0) connect _fsboard_set_WIRE[16], UInt<1>(0h0) connect _fsboard_set_WIRE[17], UInt<1>(0h0) connect _fsboard_set_WIRE[18], UInt<1>(0h0) connect _fsboard_set_WIRE[19], UInt<1>(0h0) connect _fsboard_set_WIRE[20], UInt<1>(0h0) connect _fsboard_set_WIRE[21], UInt<1>(0h0) connect _fsboard_set_WIRE[22], UInt<1>(0h0) connect _fsboard_set_WIRE[23], UInt<1>(0h0) connect _fsboard_set_WIRE[24], UInt<1>(0h0) connect _fsboard_set_WIRE[25], UInt<1>(0h0) connect _fsboard_set_WIRE[26], UInt<1>(0h0) connect _fsboard_set_WIRE[27], UInt<1>(0h0) connect _fsboard_set_WIRE[28], UInt<1>(0h0) connect _fsboard_set_WIRE[29], UInt<1>(0h0) connect _fsboard_set_WIRE[30], UInt<1>(0h0) connect _fsboard_set_WIRE[31], UInt<1>(0h0) wire fsboard_set : UInt<1>[32] connect fsboard_set, _fsboard_set_WIRE wire _fsboard_clear_WIRE : UInt<1>[32] connect _fsboard_clear_WIRE[0], UInt<1>(0h0) connect _fsboard_clear_WIRE[1], UInt<1>(0h0) connect _fsboard_clear_WIRE[2], UInt<1>(0h0) connect _fsboard_clear_WIRE[3], UInt<1>(0h0) connect _fsboard_clear_WIRE[4], UInt<1>(0h0) connect _fsboard_clear_WIRE[5], UInt<1>(0h0) connect _fsboard_clear_WIRE[6], UInt<1>(0h0) connect _fsboard_clear_WIRE[7], UInt<1>(0h0) connect _fsboard_clear_WIRE[8], UInt<1>(0h0) connect _fsboard_clear_WIRE[9], UInt<1>(0h0) connect _fsboard_clear_WIRE[10], UInt<1>(0h0) connect _fsboard_clear_WIRE[11], UInt<1>(0h0) connect _fsboard_clear_WIRE[12], UInt<1>(0h0) connect _fsboard_clear_WIRE[13], UInt<1>(0h0) connect _fsboard_clear_WIRE[14], UInt<1>(0h0) connect _fsboard_clear_WIRE[15], UInt<1>(0h0) connect _fsboard_clear_WIRE[16], UInt<1>(0h0) connect _fsboard_clear_WIRE[17], UInt<1>(0h0) connect _fsboard_clear_WIRE[18], UInt<1>(0h0) connect _fsboard_clear_WIRE[19], UInt<1>(0h0) connect _fsboard_clear_WIRE[20], UInt<1>(0h0) connect _fsboard_clear_WIRE[21], UInt<1>(0h0) connect _fsboard_clear_WIRE[22], UInt<1>(0h0) connect _fsboard_clear_WIRE[23], UInt<1>(0h0) connect _fsboard_clear_WIRE[24], UInt<1>(0h0) connect _fsboard_clear_WIRE[25], UInt<1>(0h0) connect _fsboard_clear_WIRE[26], UInt<1>(0h0) connect _fsboard_clear_WIRE[27], UInt<1>(0h0) connect _fsboard_clear_WIRE[28], UInt<1>(0h0) connect _fsboard_clear_WIRE[29], UInt<1>(0h0) connect _fsboard_clear_WIRE[30], UInt<1>(0h0) connect _fsboard_clear_WIRE[31], UInt<1>(0h0) wire fsboard_clear : UInt<1>[32] connect fsboard_clear, _fsboard_clear_WIRE node _fsboard_0_T = eq(fsboard_clear[0], UInt<1>(0h0)) node _fsboard_0_T_1 = and(fsboard[0], _fsboard_0_T) node _fsboard_0_T_2 = or(_fsboard_0_T_1, fsboard_set[0]) connect fsboard[0], _fsboard_0_T_2 node _fsboard_1_T = eq(fsboard_clear[1], UInt<1>(0h0)) node _fsboard_1_T_1 = and(fsboard[1], _fsboard_1_T) node _fsboard_1_T_2 = or(_fsboard_1_T_1, fsboard_set[1]) connect fsboard[1], _fsboard_1_T_2 node _fsboard_2_T = eq(fsboard_clear[2], UInt<1>(0h0)) node _fsboard_2_T_1 = and(fsboard[2], _fsboard_2_T) node _fsboard_2_T_2 = or(_fsboard_2_T_1, fsboard_set[2]) connect fsboard[2], _fsboard_2_T_2 node _fsboard_3_T = eq(fsboard_clear[3], UInt<1>(0h0)) node _fsboard_3_T_1 = and(fsboard[3], _fsboard_3_T) node _fsboard_3_T_2 = or(_fsboard_3_T_1, fsboard_set[3]) connect fsboard[3], _fsboard_3_T_2 node _fsboard_4_T = eq(fsboard_clear[4], UInt<1>(0h0)) node _fsboard_4_T_1 = and(fsboard[4], _fsboard_4_T) node _fsboard_4_T_2 = or(_fsboard_4_T_1, fsboard_set[4]) connect fsboard[4], _fsboard_4_T_2 node _fsboard_5_T = eq(fsboard_clear[5], UInt<1>(0h0)) node _fsboard_5_T_1 = and(fsboard[5], _fsboard_5_T) node _fsboard_5_T_2 = or(_fsboard_5_T_1, fsboard_set[5]) connect fsboard[5], _fsboard_5_T_2 node _fsboard_6_T = eq(fsboard_clear[6], UInt<1>(0h0)) node _fsboard_6_T_1 = and(fsboard[6], _fsboard_6_T) node _fsboard_6_T_2 = or(_fsboard_6_T_1, fsboard_set[6]) connect fsboard[6], _fsboard_6_T_2 node _fsboard_7_T = eq(fsboard_clear[7], UInt<1>(0h0)) node _fsboard_7_T_1 = and(fsboard[7], _fsboard_7_T) node _fsboard_7_T_2 = or(_fsboard_7_T_1, fsboard_set[7]) connect fsboard[7], _fsboard_7_T_2 node _fsboard_8_T = eq(fsboard_clear[8], UInt<1>(0h0)) node _fsboard_8_T_1 = and(fsboard[8], _fsboard_8_T) node _fsboard_8_T_2 = or(_fsboard_8_T_1, fsboard_set[8]) connect fsboard[8], _fsboard_8_T_2 node _fsboard_9_T = eq(fsboard_clear[9], UInt<1>(0h0)) node _fsboard_9_T_1 = and(fsboard[9], _fsboard_9_T) node _fsboard_9_T_2 = or(_fsboard_9_T_1, fsboard_set[9]) connect fsboard[9], _fsboard_9_T_2 node _fsboard_10_T = eq(fsboard_clear[10], UInt<1>(0h0)) node _fsboard_10_T_1 = and(fsboard[10], _fsboard_10_T) node _fsboard_10_T_2 = or(_fsboard_10_T_1, fsboard_set[10]) connect fsboard[10], _fsboard_10_T_2 node _fsboard_11_T = eq(fsboard_clear[11], UInt<1>(0h0)) node _fsboard_11_T_1 = and(fsboard[11], _fsboard_11_T) node _fsboard_11_T_2 = or(_fsboard_11_T_1, fsboard_set[11]) connect fsboard[11], _fsboard_11_T_2 node _fsboard_12_T = eq(fsboard_clear[12], UInt<1>(0h0)) node _fsboard_12_T_1 = and(fsboard[12], _fsboard_12_T) node _fsboard_12_T_2 = or(_fsboard_12_T_1, fsboard_set[12]) connect fsboard[12], _fsboard_12_T_2 node _fsboard_13_T = eq(fsboard_clear[13], UInt<1>(0h0)) node _fsboard_13_T_1 = and(fsboard[13], _fsboard_13_T) node _fsboard_13_T_2 = or(_fsboard_13_T_1, fsboard_set[13]) connect fsboard[13], _fsboard_13_T_2 node _fsboard_14_T = eq(fsboard_clear[14], UInt<1>(0h0)) node _fsboard_14_T_1 = and(fsboard[14], _fsboard_14_T) node _fsboard_14_T_2 = or(_fsboard_14_T_1, fsboard_set[14]) connect fsboard[14], _fsboard_14_T_2 node _fsboard_15_T = eq(fsboard_clear[15], UInt<1>(0h0)) node _fsboard_15_T_1 = and(fsboard[15], _fsboard_15_T) node _fsboard_15_T_2 = or(_fsboard_15_T_1, fsboard_set[15]) connect fsboard[15], _fsboard_15_T_2 node _fsboard_16_T = eq(fsboard_clear[16], UInt<1>(0h0)) node _fsboard_16_T_1 = and(fsboard[16], _fsboard_16_T) node _fsboard_16_T_2 = or(_fsboard_16_T_1, fsboard_set[16]) connect fsboard[16], _fsboard_16_T_2 node _fsboard_17_T = eq(fsboard_clear[17], UInt<1>(0h0)) node _fsboard_17_T_1 = and(fsboard[17], _fsboard_17_T) node _fsboard_17_T_2 = or(_fsboard_17_T_1, fsboard_set[17]) connect fsboard[17], _fsboard_17_T_2 node _fsboard_18_T = eq(fsboard_clear[18], UInt<1>(0h0)) node _fsboard_18_T_1 = and(fsboard[18], _fsboard_18_T) node _fsboard_18_T_2 = or(_fsboard_18_T_1, fsboard_set[18]) connect fsboard[18], _fsboard_18_T_2 node _fsboard_19_T = eq(fsboard_clear[19], UInt<1>(0h0)) node _fsboard_19_T_1 = and(fsboard[19], _fsboard_19_T) node _fsboard_19_T_2 = or(_fsboard_19_T_1, fsboard_set[19]) connect fsboard[19], _fsboard_19_T_2 node _fsboard_20_T = eq(fsboard_clear[20], UInt<1>(0h0)) node _fsboard_20_T_1 = and(fsboard[20], _fsboard_20_T) node _fsboard_20_T_2 = or(_fsboard_20_T_1, fsboard_set[20]) connect fsboard[20], _fsboard_20_T_2 node _fsboard_21_T = eq(fsboard_clear[21], UInt<1>(0h0)) node _fsboard_21_T_1 = and(fsboard[21], _fsboard_21_T) node _fsboard_21_T_2 = or(_fsboard_21_T_1, fsboard_set[21]) connect fsboard[21], _fsboard_21_T_2 node _fsboard_22_T = eq(fsboard_clear[22], UInt<1>(0h0)) node _fsboard_22_T_1 = and(fsboard[22], _fsboard_22_T) node _fsboard_22_T_2 = or(_fsboard_22_T_1, fsboard_set[22]) connect fsboard[22], _fsboard_22_T_2 node _fsboard_23_T = eq(fsboard_clear[23], UInt<1>(0h0)) node _fsboard_23_T_1 = and(fsboard[23], _fsboard_23_T) node _fsboard_23_T_2 = or(_fsboard_23_T_1, fsboard_set[23]) connect fsboard[23], _fsboard_23_T_2 node _fsboard_24_T = eq(fsboard_clear[24], UInt<1>(0h0)) node _fsboard_24_T_1 = and(fsboard[24], _fsboard_24_T) node _fsboard_24_T_2 = or(_fsboard_24_T_1, fsboard_set[24]) connect fsboard[24], _fsboard_24_T_2 node _fsboard_25_T = eq(fsboard_clear[25], UInt<1>(0h0)) node _fsboard_25_T_1 = and(fsboard[25], _fsboard_25_T) node _fsboard_25_T_2 = or(_fsboard_25_T_1, fsboard_set[25]) connect fsboard[25], _fsboard_25_T_2 node _fsboard_26_T = eq(fsboard_clear[26], UInt<1>(0h0)) node _fsboard_26_T_1 = and(fsboard[26], _fsboard_26_T) node _fsboard_26_T_2 = or(_fsboard_26_T_1, fsboard_set[26]) connect fsboard[26], _fsboard_26_T_2 node _fsboard_27_T = eq(fsboard_clear[27], UInt<1>(0h0)) node _fsboard_27_T_1 = and(fsboard[27], _fsboard_27_T) node _fsboard_27_T_2 = or(_fsboard_27_T_1, fsboard_set[27]) connect fsboard[27], _fsboard_27_T_2 node _fsboard_28_T = eq(fsboard_clear[28], UInt<1>(0h0)) node _fsboard_28_T_1 = and(fsboard[28], _fsboard_28_T) node _fsboard_28_T_2 = or(_fsboard_28_T_1, fsboard_set[28]) connect fsboard[28], _fsboard_28_T_2 node _fsboard_29_T = eq(fsboard_clear[29], UInt<1>(0h0)) node _fsboard_29_T_1 = and(fsboard[29], _fsboard_29_T) node _fsboard_29_T_2 = or(_fsboard_29_T_1, fsboard_set[29]) connect fsboard[29], _fsboard_29_T_2 node _fsboard_30_T = eq(fsboard_clear[30], UInt<1>(0h0)) node _fsboard_30_T_1 = and(fsboard[30], _fsboard_30_T) node _fsboard_30_T_2 = or(_fsboard_30_T_1, fsboard_set[30]) connect fsboard[30], _fsboard_30_T_2 node _fsboard_31_T = eq(fsboard_clear[31], UInt<1>(0h0)) node _fsboard_31_T_1 = and(fsboard[31], _fsboard_31_T) node _fsboard_31_T_2 = or(_fsboard_31_T_1, fsboard_set[31]) connect fsboard[31], _fsboard_31_T_2 node _T_124 = asUInt(reset) when _T_124 : connect fsboard[0], UInt<1>(0h1) connect fsboard[1], UInt<1>(0h1) connect fsboard[2], UInt<1>(0h1) connect fsboard[3], UInt<1>(0h1) connect fsboard[4], UInt<1>(0h1) connect fsboard[5], UInt<1>(0h1) connect fsboard[6], UInt<1>(0h1) connect fsboard[7], UInt<1>(0h1) connect fsboard[8], UInt<1>(0h1) connect fsboard[9], UInt<1>(0h1) connect fsboard[10], UInt<1>(0h1) connect fsboard[11], UInt<1>(0h1) connect fsboard[12], UInt<1>(0h1) connect fsboard[13], UInt<1>(0h1) connect fsboard[14], UInt<1>(0h1) connect fsboard[15], UInt<1>(0h1) connect fsboard[16], UInt<1>(0h1) connect fsboard[17], UInt<1>(0h1) connect fsboard[18], UInt<1>(0h1) connect fsboard[19], UInt<1>(0h1) connect fsboard[20], UInt<1>(0h1) connect fsboard[21], UInt<1>(0h1) connect fsboard[22], UInt<1>(0h1) connect fsboard[23], UInt<1>(0h1) connect fsboard[24], UInt<1>(0h1) connect fsboard[25], UInt<1>(0h1) connect fsboard[26], UInt<1>(0h1) connect fsboard[27], UInt<1>(0h1) connect fsboard[28], UInt<1>(0h1) connect fsboard[29], UInt<1>(0h1) connect fsboard[30], UInt<1>(0h1) connect fsboard[31], UInt<1>(0h1) inst fp_pipe of ShuttleFPPipe connect fp_pipe.clock, clock connect fp_pipe.reset, reset wire ex_fp_data_hazard_0 : UInt<1> connect ex_fp_data_hazard_0, UInt<1>(0h0) wire ex_fp_data_hazard_1 : UInt<1> connect ex_fp_data_hazard_1, UInt<1>(0h0) node ex_frd = bits(ex_uops_reg[0].bits.inst, 11, 7) wire frd_maybe_hazard_bypass_hit : UInt<1> connect frd_maybe_hazard_bypass_hit, fsboard[ex_frd] wire frd_maybe_hazard_bypass_data : UInt<1> connect frd_maybe_hazard_bypass_data, UInt<1>(0h0) node _frd_maybe_hazard_T = eq(fp_com_bypasses_0.dst, ex_frd) node _frd_maybe_hazard_T_1 = and(fp_com_bypasses_0.valid, _frd_maybe_hazard_T) when _frd_maybe_hazard_T_1 : connect frd_maybe_hazard_bypass_hit, fp_com_bypasses_0.can_bypass connect frd_maybe_hazard_bypass_data, fp_com_bypasses_0.data node _frd_maybe_hazard_T_2 = eq(fp_com_bypasses_1.dst, ex_frd) node _frd_maybe_hazard_T_3 = and(fp_com_bypasses_1.valid, _frd_maybe_hazard_T_2) when _frd_maybe_hazard_T_3 : connect frd_maybe_hazard_bypass_hit, fp_com_bypasses_1.can_bypass connect frd_maybe_hazard_bypass_data, fp_com_bypasses_1.data node _frd_maybe_hazard_T_4 = eq(fp_mem_bypasses_0.dst, ex_frd) node _frd_maybe_hazard_T_5 = and(fp_mem_bypasses_0.valid, _frd_maybe_hazard_T_4) when _frd_maybe_hazard_T_5 : connect frd_maybe_hazard_bypass_hit, fp_mem_bypasses_0.can_bypass connect frd_maybe_hazard_bypass_data, fp_mem_bypasses_0.data node _frd_maybe_hazard_T_6 = eq(fp_mem_bypasses_1.dst, ex_frd) node _frd_maybe_hazard_T_7 = and(fp_mem_bypasses_1.valid, _frd_maybe_hazard_T_6) when _frd_maybe_hazard_T_7 : connect frd_maybe_hazard_bypass_hit, fp_mem_bypasses_1.can_bypass connect frd_maybe_hazard_bypass_data, fp_mem_bypasses_1.data node frd_maybe_hazard = eq(frd_maybe_hazard_bypass_hit, UInt<1>(0h0)) node _frd_data_hazard_T = and(frd_maybe_hazard, ex_uops_reg[0].valid) node frd_data_hazard = and(_frd_data_hazard_T, ex_uops_reg[0].bits.ctrl.wfd) connect ex_fp_data_hazard_0, frd_data_hazard node ex_frs1 = bits(ex_uops_reg[0].bits.inst, 19, 15) node ex_frs2 = bits(ex_uops_reg[0].bits.inst, 24, 20) node ex_frs3 = bits(ex_uops_reg[0].bits.inst, 31, 27) wire frs1_hazard_bypass_hit : UInt<1> connect frs1_hazard_bypass_hit, fsboard[ex_frs1] wire frs1_hazard_bypass_data : UInt<1> connect frs1_hazard_bypass_data, UInt<1>(0h0) node _frs1_hazard_T = eq(fp_com_bypasses_0.dst, ex_frs1) node _frs1_hazard_T_1 = and(fp_com_bypasses_0.valid, _frs1_hazard_T) when _frs1_hazard_T_1 : connect frs1_hazard_bypass_hit, fp_com_bypasses_0.can_bypass connect frs1_hazard_bypass_data, fp_com_bypasses_0.data node _frs1_hazard_T_2 = eq(fp_com_bypasses_1.dst, ex_frs1) node _frs1_hazard_T_3 = and(fp_com_bypasses_1.valid, _frs1_hazard_T_2) when _frs1_hazard_T_3 : connect frs1_hazard_bypass_hit, fp_com_bypasses_1.can_bypass connect frs1_hazard_bypass_data, fp_com_bypasses_1.data node _frs1_hazard_T_4 = eq(fp_mem_bypasses_0.dst, ex_frs1) node _frs1_hazard_T_5 = and(fp_mem_bypasses_0.valid, _frs1_hazard_T_4) when _frs1_hazard_T_5 : connect frs1_hazard_bypass_hit, fp_mem_bypasses_0.can_bypass connect frs1_hazard_bypass_data, fp_mem_bypasses_0.data node _frs1_hazard_T_6 = eq(fp_mem_bypasses_1.dst, ex_frs1) node _frs1_hazard_T_7 = and(fp_mem_bypasses_1.valid, _frs1_hazard_T_6) when _frs1_hazard_T_7 : connect frs1_hazard_bypass_hit, fp_mem_bypasses_1.can_bypass connect frs1_hazard_bypass_data, fp_mem_bypasses_1.data node frs1_hazard = eq(frs1_hazard_bypass_hit, UInt<1>(0h0)) wire frs2_hazard_bypass_hit : UInt<1> connect frs2_hazard_bypass_hit, fsboard[ex_frs2] wire frs2_hazard_bypass_data : UInt<1> connect frs2_hazard_bypass_data, UInt<1>(0h0) node _frs2_hazard_T = eq(fp_com_bypasses_0.dst, ex_frs2) node _frs2_hazard_T_1 = and(fp_com_bypasses_0.valid, _frs2_hazard_T) when _frs2_hazard_T_1 : connect frs2_hazard_bypass_hit, fp_com_bypasses_0.can_bypass connect frs2_hazard_bypass_data, fp_com_bypasses_0.data node _frs2_hazard_T_2 = eq(fp_com_bypasses_1.dst, ex_frs2) node _frs2_hazard_T_3 = and(fp_com_bypasses_1.valid, _frs2_hazard_T_2) when _frs2_hazard_T_3 : connect frs2_hazard_bypass_hit, fp_com_bypasses_1.can_bypass connect frs2_hazard_bypass_data, fp_com_bypasses_1.data node _frs2_hazard_T_4 = eq(fp_mem_bypasses_0.dst, ex_frs2) node _frs2_hazard_T_5 = and(fp_mem_bypasses_0.valid, _frs2_hazard_T_4) when _frs2_hazard_T_5 : connect frs2_hazard_bypass_hit, fp_mem_bypasses_0.can_bypass connect frs2_hazard_bypass_data, fp_mem_bypasses_0.data node _frs2_hazard_T_6 = eq(fp_mem_bypasses_1.dst, ex_frs2) node _frs2_hazard_T_7 = and(fp_mem_bypasses_1.valid, _frs2_hazard_T_6) when _frs2_hazard_T_7 : connect frs2_hazard_bypass_hit, fp_mem_bypasses_1.can_bypass connect frs2_hazard_bypass_data, fp_mem_bypasses_1.data node frs2_hazard = eq(frs2_hazard_bypass_hit, UInt<1>(0h0)) wire frs3_hazard_bypass_hit : UInt<1> connect frs3_hazard_bypass_hit, fsboard[ex_frs3] wire frs3_hazard_bypass_data : UInt<1> connect frs3_hazard_bypass_data, UInt<1>(0h0) node _frs3_hazard_T = eq(fp_com_bypasses_0.dst, ex_frs3) node _frs3_hazard_T_1 = and(fp_com_bypasses_0.valid, _frs3_hazard_T) when _frs3_hazard_T_1 : connect frs3_hazard_bypass_hit, fp_com_bypasses_0.can_bypass connect frs3_hazard_bypass_data, fp_com_bypasses_0.data node _frs3_hazard_T_2 = eq(fp_com_bypasses_1.dst, ex_frs3) node _frs3_hazard_T_3 = and(fp_com_bypasses_1.valid, _frs3_hazard_T_2) when _frs3_hazard_T_3 : connect frs3_hazard_bypass_hit, fp_com_bypasses_1.can_bypass connect frs3_hazard_bypass_data, fp_com_bypasses_1.data node _frs3_hazard_T_4 = eq(fp_mem_bypasses_0.dst, ex_frs3) node _frs3_hazard_T_5 = and(fp_mem_bypasses_0.valid, _frs3_hazard_T_4) when _frs3_hazard_T_5 : connect frs3_hazard_bypass_hit, fp_mem_bypasses_0.can_bypass connect frs3_hazard_bypass_data, fp_mem_bypasses_0.data node _frs3_hazard_T_6 = eq(fp_mem_bypasses_1.dst, ex_frs3) node _frs3_hazard_T_7 = and(fp_mem_bypasses_1.valid, _frs3_hazard_T_6) when _frs3_hazard_T_7 : connect frs3_hazard_bypass_hit, fp_mem_bypasses_1.can_bypass connect frs3_hazard_bypass_data, fp_mem_bypasses_1.data node frs3_hazard = eq(frs3_hazard_bypass_hit, UInt<1>(0h0)) node frs1_data_hazard = and(frs1_hazard, ex_uops_reg[0].bits.ctrl.rfs1) node frs2_data_hazard = and(frs2_hazard, ex_uops_reg[0].bits.ctrl.rfs2) node frs3_data_hazard = and(frs3_hazard, ex_uops_reg[0].bits.ctrl.rfs3) node _ex_fp_data_hazard_0_T = or(frs1_data_hazard, frs2_data_hazard) node _ex_fp_data_hazard_0_T_1 = or(_ex_fp_data_hazard_0_T, frs3_data_hazard) node _ex_fp_data_hazard_0_T_2 = or(_ex_fp_data_hazard_0_T_1, frd_data_hazard) node _ex_fp_data_hazard_0_T_3 = and(_ex_fp_data_hazard_0_T_2, ex_uops_reg[0].valid) connect ex_fp_data_hazard_0, _ex_fp_data_hazard_0_T_3 node _fp_pipe_io_in_valid_T = and(ex_uops_reg[0].bits.fp_ctrl.ldst, ex_uops_reg[0].bits.fp_ctrl.wen) node _fp_pipe_io_in_valid_T_1 = eq(_fp_pipe_io_in_valid_T, UInt<1>(0h0)) node _fp_pipe_io_in_valid_T_2 = and(ex_uops_reg[0].bits.ctrl.fp, _fp_pipe_io_in_valid_T_1) node _fp_pipe_io_in_valid_T_3 = and(ex_uops_reg[0].valid, _fp_pipe_io_in_valid_T_2) node _fp_pipe_io_in_valid_T_4 = eq(ex_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _fp_pipe_io_in_valid_T_5 = and(_fp_pipe_io_in_valid_T_3, _fp_pipe_io_in_valid_T_4) node _fp_pipe_io_in_valid_T_6 = eq(ex_stall, UInt<1>(0h0)) node _fp_pipe_io_in_valid_T_7 = and(_fp_pipe_io_in_valid_T_5, _fp_pipe_io_in_valid_T_6) node _fp_pipe_io_in_valid_T_8 = eq(flush_rrd_ex, UInt<1>(0h0)) node _fp_pipe_io_in_valid_T_9 = and(_fp_pipe_io_in_valid_T_7, _fp_pipe_io_in_valid_T_8) connect fp_pipe.io.in.valid, _fp_pipe_io_in_valid_T_9 connect fp_pipe.io.in.bits.flush_pipe, ex_uops_reg[0].bits.flush_pipe connect fp_pipe.io.in.bits.mem_size, ex_uops_reg[0].bits.mem_size connect fp_pipe.io.in.bits.fdivin.in3, ex_uops_reg[0].bits.fdivin.in3 connect fp_pipe.io.in.bits.fdivin.in2, ex_uops_reg[0].bits.fdivin.in2 connect fp_pipe.io.in.bits.fdivin.in1, ex_uops_reg[0].bits.fdivin.in1 connect fp_pipe.io.in.bits.fdivin.fmt, ex_uops_reg[0].bits.fdivin.fmt connect fp_pipe.io.in.bits.fdivin.typ, ex_uops_reg[0].bits.fdivin.typ connect fp_pipe.io.in.bits.fdivin.fmaCmd, ex_uops_reg[0].bits.fdivin.fmaCmd connect fp_pipe.io.in.bits.fdivin.rm, ex_uops_reg[0].bits.fdivin.rm connect fp_pipe.io.in.bits.fdivin.vec, ex_uops_reg[0].bits.fdivin.vec connect fp_pipe.io.in.bits.fdivin.wflags, ex_uops_reg[0].bits.fdivin.wflags connect fp_pipe.io.in.bits.fdivin.sqrt, ex_uops_reg[0].bits.fdivin.sqrt connect fp_pipe.io.in.bits.fdivin.div, ex_uops_reg[0].bits.fdivin.div connect fp_pipe.io.in.bits.fdivin.fma, ex_uops_reg[0].bits.fdivin.fma connect fp_pipe.io.in.bits.fdivin.fastpipe, ex_uops_reg[0].bits.fdivin.fastpipe connect fp_pipe.io.in.bits.fdivin.toint, ex_uops_reg[0].bits.fdivin.toint connect fp_pipe.io.in.bits.fdivin.fromint, ex_uops_reg[0].bits.fdivin.fromint connect fp_pipe.io.in.bits.fdivin.typeTagOut, ex_uops_reg[0].bits.fdivin.typeTagOut connect fp_pipe.io.in.bits.fdivin.typeTagIn, ex_uops_reg[0].bits.fdivin.typeTagIn connect fp_pipe.io.in.bits.fdivin.swap23, ex_uops_reg[0].bits.fdivin.swap23 connect fp_pipe.io.in.bits.fdivin.swap12, ex_uops_reg[0].bits.fdivin.swap12 connect fp_pipe.io.in.bits.fdivin.ren3, ex_uops_reg[0].bits.fdivin.ren3 connect fp_pipe.io.in.bits.fdivin.ren2, ex_uops_reg[0].bits.fdivin.ren2 connect fp_pipe.io.in.bits.fdivin.ren1, ex_uops_reg[0].bits.fdivin.ren1 connect fp_pipe.io.in.bits.fdivin.wen, ex_uops_reg[0].bits.fdivin.wen connect fp_pipe.io.in.bits.fdivin.ldst, ex_uops_reg[0].bits.fdivin.ldst connect fp_pipe.io.in.bits.fexc, ex_uops_reg[0].bits.fexc connect fp_pipe.io.in.bits.fra3, ex_uops_reg[0].bits.fra3 connect fp_pipe.io.in.bits.fra2, ex_uops_reg[0].bits.fra2 connect fp_pipe.io.in.bits.fra1, ex_uops_reg[0].bits.fra1 connect fp_pipe.io.in.bits.wdata.bits, ex_uops_reg[0].bits.wdata.bits connect fp_pipe.io.in.bits.wdata.valid, ex_uops_reg[0].bits.wdata.valid connect fp_pipe.io.in.bits.uses_latealu, ex_uops_reg[0].bits.uses_latealu connect fp_pipe.io.in.bits.uses_memalu, ex_uops_reg[0].bits.uses_memalu connect fp_pipe.io.in.bits.rs3_data, ex_uops_reg[0].bits.rs3_data connect fp_pipe.io.in.bits.rs2_data, ex_uops_reg[0].bits.rs2_data connect fp_pipe.io.in.bits.rs1_data, ex_uops_reg[0].bits.rs1_data connect fp_pipe.io.in.bits.needs_replay, ex_uops_reg[0].bits.needs_replay connect fp_pipe.io.in.bits.xcpt_cause, ex_uops_reg[0].bits.xcpt_cause connect fp_pipe.io.in.bits.xcpt, ex_uops_reg[0].bits.xcpt connect fp_pipe.io.in.bits.taken, ex_uops_reg[0].bits.taken connect fp_pipe.io.in.bits.ras_head, ex_uops_reg[0].bits.ras_head connect fp_pipe.io.in.bits.next_pc.bits, ex_uops_reg[0].bits.next_pc.bits connect fp_pipe.io.in.bits.next_pc.valid, ex_uops_reg[0].bits.next_pc.valid connect fp_pipe.io.in.bits.sfb_shadow, ex_uops_reg[0].bits.sfb_shadow connect fp_pipe.io.in.bits.sfb_br, ex_uops_reg[0].bits.sfb_br connect fp_pipe.io.in.bits.btb_resp.bits.bht.value, ex_uops_reg[0].bits.btb_resp.bits.bht.value connect fp_pipe.io.in.bits.btb_resp.bits.bht.history, ex_uops_reg[0].bits.btb_resp.bits.bht.history connect fp_pipe.io.in.bits.btb_resp.bits.entry, ex_uops_reg[0].bits.btb_resp.bits.entry connect fp_pipe.io.in.bits.btb_resp.bits.target, ex_uops_reg[0].bits.btb_resp.bits.target connect fp_pipe.io.in.bits.btb_resp.bits.bridx, ex_uops_reg[0].bits.btb_resp.bits.bridx connect fp_pipe.io.in.bits.btb_resp.bits.mask, ex_uops_reg[0].bits.btb_resp.bits.mask connect fp_pipe.io.in.bits.btb_resp.bits.taken, ex_uops_reg[0].bits.btb_resp.bits.taken connect fp_pipe.io.in.bits.btb_resp.bits.cfiType, ex_uops_reg[0].bits.btb_resp.bits.cfiType connect fp_pipe.io.in.bits.btb_resp.valid, ex_uops_reg[0].bits.btb_resp.valid connect fp_pipe.io.in.bits.sets_vcfg, ex_uops_reg[0].bits.sets_vcfg connect fp_pipe.io.in.bits.rvc, ex_uops_reg[0].bits.rvc connect fp_pipe.io.in.bits.fp_ctrl.vec, ex_uops_reg[0].bits.fp_ctrl.vec connect fp_pipe.io.in.bits.fp_ctrl.wflags, ex_uops_reg[0].bits.fp_ctrl.wflags connect fp_pipe.io.in.bits.fp_ctrl.sqrt, ex_uops_reg[0].bits.fp_ctrl.sqrt connect fp_pipe.io.in.bits.fp_ctrl.div, ex_uops_reg[0].bits.fp_ctrl.div connect fp_pipe.io.in.bits.fp_ctrl.fma, ex_uops_reg[0].bits.fp_ctrl.fma connect fp_pipe.io.in.bits.fp_ctrl.fastpipe, ex_uops_reg[0].bits.fp_ctrl.fastpipe connect fp_pipe.io.in.bits.fp_ctrl.toint, ex_uops_reg[0].bits.fp_ctrl.toint connect fp_pipe.io.in.bits.fp_ctrl.fromint, ex_uops_reg[0].bits.fp_ctrl.fromint connect fp_pipe.io.in.bits.fp_ctrl.typeTagOut, ex_uops_reg[0].bits.fp_ctrl.typeTagOut connect fp_pipe.io.in.bits.fp_ctrl.typeTagIn, ex_uops_reg[0].bits.fp_ctrl.typeTagIn connect fp_pipe.io.in.bits.fp_ctrl.swap23, ex_uops_reg[0].bits.fp_ctrl.swap23 connect fp_pipe.io.in.bits.fp_ctrl.swap12, ex_uops_reg[0].bits.fp_ctrl.swap12 connect fp_pipe.io.in.bits.fp_ctrl.ren3, ex_uops_reg[0].bits.fp_ctrl.ren3 connect fp_pipe.io.in.bits.fp_ctrl.ren2, ex_uops_reg[0].bits.fp_ctrl.ren2 connect fp_pipe.io.in.bits.fp_ctrl.ren1, ex_uops_reg[0].bits.fp_ctrl.ren1 connect fp_pipe.io.in.bits.fp_ctrl.wen, ex_uops_reg[0].bits.fp_ctrl.wen connect fp_pipe.io.in.bits.fp_ctrl.ldst, ex_uops_reg[0].bits.fp_ctrl.ldst connect fp_pipe.io.in.bits.ctrl.vec, ex_uops_reg[0].bits.ctrl.vec connect fp_pipe.io.in.bits.ctrl.dp, ex_uops_reg[0].bits.ctrl.dp connect fp_pipe.io.in.bits.ctrl.amo, ex_uops_reg[0].bits.ctrl.amo connect fp_pipe.io.in.bits.ctrl.fence, ex_uops_reg[0].bits.ctrl.fence connect fp_pipe.io.in.bits.ctrl.fence_i, ex_uops_reg[0].bits.ctrl.fence_i connect fp_pipe.io.in.bits.ctrl.csr, ex_uops_reg[0].bits.ctrl.csr connect fp_pipe.io.in.bits.ctrl.wxd, ex_uops_reg[0].bits.ctrl.wxd connect fp_pipe.io.in.bits.ctrl.div, ex_uops_reg[0].bits.ctrl.div connect fp_pipe.io.in.bits.ctrl.mul, ex_uops_reg[0].bits.ctrl.mul connect fp_pipe.io.in.bits.ctrl.wfd, ex_uops_reg[0].bits.ctrl.wfd connect fp_pipe.io.in.bits.ctrl.rfs3, ex_uops_reg[0].bits.ctrl.rfs3 connect fp_pipe.io.in.bits.ctrl.rfs2, ex_uops_reg[0].bits.ctrl.rfs2 connect fp_pipe.io.in.bits.ctrl.rfs1, ex_uops_reg[0].bits.ctrl.rfs1 connect fp_pipe.io.in.bits.ctrl.mem_cmd, ex_uops_reg[0].bits.ctrl.mem_cmd connect fp_pipe.io.in.bits.ctrl.mem, ex_uops_reg[0].bits.ctrl.mem connect fp_pipe.io.in.bits.ctrl.alu_fn, ex_uops_reg[0].bits.ctrl.alu_fn connect fp_pipe.io.in.bits.ctrl.alu_dw, ex_uops_reg[0].bits.ctrl.alu_dw connect fp_pipe.io.in.bits.ctrl.sel_imm, ex_uops_reg[0].bits.ctrl.sel_imm connect fp_pipe.io.in.bits.ctrl.sel_alu1, ex_uops_reg[0].bits.ctrl.sel_alu1 connect fp_pipe.io.in.bits.ctrl.sel_alu2, ex_uops_reg[0].bits.ctrl.sel_alu2 connect fp_pipe.io.in.bits.ctrl.rxs1, ex_uops_reg[0].bits.ctrl.rxs1 connect fp_pipe.io.in.bits.ctrl.rxs2, ex_uops_reg[0].bits.ctrl.rxs2 connect fp_pipe.io.in.bits.ctrl.jalr, ex_uops_reg[0].bits.ctrl.jalr connect fp_pipe.io.in.bits.ctrl.jal, ex_uops_reg[0].bits.ctrl.jal connect fp_pipe.io.in.bits.ctrl.branch, ex_uops_reg[0].bits.ctrl.branch connect fp_pipe.io.in.bits.ctrl.rocc, ex_uops_reg[0].bits.ctrl.rocc connect fp_pipe.io.in.bits.ctrl.fp, ex_uops_reg[0].bits.ctrl.fp connect fp_pipe.io.in.bits.ctrl.legal, ex_uops_reg[0].bits.ctrl.legal connect fp_pipe.io.in.bits.edge_inst, ex_uops_reg[0].bits.edge_inst connect fp_pipe.io.in.bits.pc, ex_uops_reg[0].bits.pc connect fp_pipe.io.in.bits.raw_inst, ex_uops_reg[0].bits.raw_inst connect fp_pipe.io.in.bits.inst, ex_uops_reg[0].bits.inst connect fp_pipe.io.frs1_data, fregfile[ex_uops_reg[0].bits.fra1] connect fp_pipe.io.frs2_data, fregfile[ex_uops_reg[0].bits.fra2] connect fp_pipe.io.frs3_data, fregfile[ex_uops_reg[0].bits.fra3] connect fp_pipe.io.fcsr_rm, csr.io.fcsr_rm node ex_frd_1 = bits(ex_uops_reg[1].bits.inst, 11, 7) wire frd_maybe_hazard_bypass_hit_1 : UInt<1> connect frd_maybe_hazard_bypass_hit_1, fsboard[ex_frd_1] wire frd_maybe_hazard_bypass_data_1 : UInt<1> connect frd_maybe_hazard_bypass_data_1, UInt<1>(0h0) node _frd_maybe_hazard_T_8 = eq(fp_com_bypasses_0.dst, ex_frd_1) node _frd_maybe_hazard_T_9 = and(fp_com_bypasses_0.valid, _frd_maybe_hazard_T_8) when _frd_maybe_hazard_T_9 : connect frd_maybe_hazard_bypass_hit_1, fp_com_bypasses_0.can_bypass connect frd_maybe_hazard_bypass_data_1, fp_com_bypasses_0.data node _frd_maybe_hazard_T_10 = eq(fp_com_bypasses_1.dst, ex_frd_1) node _frd_maybe_hazard_T_11 = and(fp_com_bypasses_1.valid, _frd_maybe_hazard_T_10) when _frd_maybe_hazard_T_11 : connect frd_maybe_hazard_bypass_hit_1, fp_com_bypasses_1.can_bypass connect frd_maybe_hazard_bypass_data_1, fp_com_bypasses_1.data node _frd_maybe_hazard_T_12 = eq(fp_mem_bypasses_0.dst, ex_frd_1) node _frd_maybe_hazard_T_13 = and(fp_mem_bypasses_0.valid, _frd_maybe_hazard_T_12) when _frd_maybe_hazard_T_13 : connect frd_maybe_hazard_bypass_hit_1, fp_mem_bypasses_0.can_bypass connect frd_maybe_hazard_bypass_data_1, fp_mem_bypasses_0.data node _frd_maybe_hazard_T_14 = eq(fp_mem_bypasses_1.dst, ex_frd_1) node _frd_maybe_hazard_T_15 = and(fp_mem_bypasses_1.valid, _frd_maybe_hazard_T_14) when _frd_maybe_hazard_T_15 : connect frd_maybe_hazard_bypass_hit_1, fp_mem_bypasses_1.can_bypass connect frd_maybe_hazard_bypass_data_1, fp_mem_bypasses_1.data node frd_maybe_hazard_1 = eq(frd_maybe_hazard_bypass_hit_1, UInt<1>(0h0)) node _frd_data_hazard_T_1 = and(frd_maybe_hazard_1, ex_uops_reg[1].valid) node frd_data_hazard_1 = and(_frd_data_hazard_T_1, ex_uops_reg[1].bits.ctrl.wfd) connect ex_fp_data_hazard_1, frd_data_hazard_1 node _ex_fcsr_data_hazard_T = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h6)) node _ex_fcsr_data_hazard_T_1 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h7)) node _ex_fcsr_data_hazard_T_2 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h5)) node _ex_fcsr_data_hazard_T_3 = or(_ex_fcsr_data_hazard_T, _ex_fcsr_data_hazard_T_1) node _ex_fcsr_data_hazard_T_4 = or(_ex_fcsr_data_hazard_T_3, _ex_fcsr_data_hazard_T_2) node _ex_fcsr_data_hazard_T_5 = and(ex_uops_reg[0].valid, _ex_fcsr_data_hazard_T_4) node _ex_fcsr_data_hazard_T_6 = or(fsboard_bsy, mem_bsy) node _ex_fcsr_data_hazard_T_7 = or(_ex_fcsr_data_hazard_T_6, com_bsy) node ex_fcsr_data_hazard = and(_ex_fcsr_data_hazard_T_5, _ex_fcsr_data_hazard_T_7) node ex_setvcfg_valid_0 = and(ex_uops_reg[0].valid, ex_uops_reg[0].bits.sets_vcfg) node ex_setvcfg_valid_1 = and(ex_uops_reg[1].valid, ex_uops_reg[1].bits.sets_vcfg) wire _ex_setvcfg_uop_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ex_setvcfg_uop_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ex_setvcfg_uop_T = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.flush_pipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_1 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.flush_pipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_2 = or(_ex_setvcfg_uop_T, _ex_setvcfg_uop_T_1) wire _ex_setvcfg_uop_WIRE_2 : UInt<1> connect _ex_setvcfg_uop_WIRE_2, _ex_setvcfg_uop_T_2 connect _ex_setvcfg_uop_WIRE_1.flush_pipe, _ex_setvcfg_uop_WIRE_2 node _ex_setvcfg_uop_T_3 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.mem_size, UInt<1>(0h0)) node _ex_setvcfg_uop_T_4 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.mem_size, UInt<1>(0h0)) node _ex_setvcfg_uop_T_5 = or(_ex_setvcfg_uop_T_3, _ex_setvcfg_uop_T_4) wire _ex_setvcfg_uop_WIRE_3 : UInt<2> connect _ex_setvcfg_uop_WIRE_3, _ex_setvcfg_uop_T_5 connect _ex_setvcfg_uop_WIRE_1.mem_size, _ex_setvcfg_uop_WIRE_3 wire _ex_setvcfg_uop_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ex_setvcfg_uop_T_6 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.in3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_7 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.in3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_8 = or(_ex_setvcfg_uop_T_6, _ex_setvcfg_uop_T_7) wire _ex_setvcfg_uop_WIRE_5 : UInt<65> connect _ex_setvcfg_uop_WIRE_5, _ex_setvcfg_uop_T_8 connect _ex_setvcfg_uop_WIRE_4.in3, _ex_setvcfg_uop_WIRE_5 node _ex_setvcfg_uop_T_9 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.in2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_10 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.in2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_11 = or(_ex_setvcfg_uop_T_9, _ex_setvcfg_uop_T_10) wire _ex_setvcfg_uop_WIRE_6 : UInt<65> connect _ex_setvcfg_uop_WIRE_6, _ex_setvcfg_uop_T_11 connect _ex_setvcfg_uop_WIRE_4.in2, _ex_setvcfg_uop_WIRE_6 node _ex_setvcfg_uop_T_12 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.in1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_13 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.in1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_14 = or(_ex_setvcfg_uop_T_12, _ex_setvcfg_uop_T_13) wire _ex_setvcfg_uop_WIRE_7 : UInt<65> connect _ex_setvcfg_uop_WIRE_7, _ex_setvcfg_uop_T_14 connect _ex_setvcfg_uop_WIRE_4.in1, _ex_setvcfg_uop_WIRE_7 node _ex_setvcfg_uop_T_15 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_16 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_17 = or(_ex_setvcfg_uop_T_15, _ex_setvcfg_uop_T_16) wire _ex_setvcfg_uop_WIRE_8 : UInt<2> connect _ex_setvcfg_uop_WIRE_8, _ex_setvcfg_uop_T_17 connect _ex_setvcfg_uop_WIRE_4.fmt, _ex_setvcfg_uop_WIRE_8 node _ex_setvcfg_uop_T_18 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.typ, UInt<1>(0h0)) node _ex_setvcfg_uop_T_19 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.typ, UInt<1>(0h0)) node _ex_setvcfg_uop_T_20 = or(_ex_setvcfg_uop_T_18, _ex_setvcfg_uop_T_19) wire _ex_setvcfg_uop_WIRE_9 : UInt<2> connect _ex_setvcfg_uop_WIRE_9, _ex_setvcfg_uop_T_20 connect _ex_setvcfg_uop_WIRE_4.typ, _ex_setvcfg_uop_WIRE_9 node _ex_setvcfg_uop_T_21 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_22 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_23 = or(_ex_setvcfg_uop_T_21, _ex_setvcfg_uop_T_22) wire _ex_setvcfg_uop_WIRE_10 : UInt<2> connect _ex_setvcfg_uop_WIRE_10, _ex_setvcfg_uop_T_23 connect _ex_setvcfg_uop_WIRE_4.fmaCmd, _ex_setvcfg_uop_WIRE_10 node _ex_setvcfg_uop_T_24 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.rm, UInt<1>(0h0)) node _ex_setvcfg_uop_T_25 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.rm, UInt<1>(0h0)) node _ex_setvcfg_uop_T_26 = or(_ex_setvcfg_uop_T_24, _ex_setvcfg_uop_T_25) wire _ex_setvcfg_uop_WIRE_11 : UInt<3> connect _ex_setvcfg_uop_WIRE_11, _ex_setvcfg_uop_T_26 connect _ex_setvcfg_uop_WIRE_4.rm, _ex_setvcfg_uop_WIRE_11 node _ex_setvcfg_uop_T_27 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_28 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_29 = or(_ex_setvcfg_uop_T_27, _ex_setvcfg_uop_T_28) wire _ex_setvcfg_uop_WIRE_12 : UInt<1> connect _ex_setvcfg_uop_WIRE_12, _ex_setvcfg_uop_T_29 connect _ex_setvcfg_uop_WIRE_4.vec, _ex_setvcfg_uop_WIRE_12 node _ex_setvcfg_uop_T_30 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ex_setvcfg_uop_T_31 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ex_setvcfg_uop_T_32 = or(_ex_setvcfg_uop_T_30, _ex_setvcfg_uop_T_31) wire _ex_setvcfg_uop_WIRE_13 : UInt<1> connect _ex_setvcfg_uop_WIRE_13, _ex_setvcfg_uop_T_32 connect _ex_setvcfg_uop_WIRE_4.wflags, _ex_setvcfg_uop_WIRE_13 node _ex_setvcfg_uop_T_33 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_34 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_35 = or(_ex_setvcfg_uop_T_33, _ex_setvcfg_uop_T_34) wire _ex_setvcfg_uop_WIRE_14 : UInt<1> connect _ex_setvcfg_uop_WIRE_14, _ex_setvcfg_uop_T_35 connect _ex_setvcfg_uop_WIRE_4.sqrt, _ex_setvcfg_uop_WIRE_14 node _ex_setvcfg_uop_T_36 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_37 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_38 = or(_ex_setvcfg_uop_T_36, _ex_setvcfg_uop_T_37) wire _ex_setvcfg_uop_WIRE_15 : UInt<1> connect _ex_setvcfg_uop_WIRE_15, _ex_setvcfg_uop_T_38 connect _ex_setvcfg_uop_WIRE_4.div, _ex_setvcfg_uop_WIRE_15 node _ex_setvcfg_uop_T_39 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.fma, UInt<1>(0h0)) node _ex_setvcfg_uop_T_40 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.fma, UInt<1>(0h0)) node _ex_setvcfg_uop_T_41 = or(_ex_setvcfg_uop_T_39, _ex_setvcfg_uop_T_40) wire _ex_setvcfg_uop_WIRE_16 : UInt<1> connect _ex_setvcfg_uop_WIRE_16, _ex_setvcfg_uop_T_41 connect _ex_setvcfg_uop_WIRE_4.fma, _ex_setvcfg_uop_WIRE_16 node _ex_setvcfg_uop_T_42 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_43 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_44 = or(_ex_setvcfg_uop_T_42, _ex_setvcfg_uop_T_43) wire _ex_setvcfg_uop_WIRE_17 : UInt<1> connect _ex_setvcfg_uop_WIRE_17, _ex_setvcfg_uop_T_44 connect _ex_setvcfg_uop_WIRE_4.fastpipe, _ex_setvcfg_uop_WIRE_17 node _ex_setvcfg_uop_T_45 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.toint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_46 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.toint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_47 = or(_ex_setvcfg_uop_T_45, _ex_setvcfg_uop_T_46) wire _ex_setvcfg_uop_WIRE_18 : UInt<1> connect _ex_setvcfg_uop_WIRE_18, _ex_setvcfg_uop_T_47 connect _ex_setvcfg_uop_WIRE_4.toint, _ex_setvcfg_uop_WIRE_18 node _ex_setvcfg_uop_T_48 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_49 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_50 = or(_ex_setvcfg_uop_T_48, _ex_setvcfg_uop_T_49) wire _ex_setvcfg_uop_WIRE_19 : UInt<1> connect _ex_setvcfg_uop_WIRE_19, _ex_setvcfg_uop_T_50 connect _ex_setvcfg_uop_WIRE_4.fromint, _ex_setvcfg_uop_WIRE_19 node _ex_setvcfg_uop_T_51 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ex_setvcfg_uop_T_52 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ex_setvcfg_uop_T_53 = or(_ex_setvcfg_uop_T_51, _ex_setvcfg_uop_T_52) wire _ex_setvcfg_uop_WIRE_20 : UInt<2> connect _ex_setvcfg_uop_WIRE_20, _ex_setvcfg_uop_T_53 connect _ex_setvcfg_uop_WIRE_4.typeTagOut, _ex_setvcfg_uop_WIRE_20 node _ex_setvcfg_uop_T_54 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_55 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_56 = or(_ex_setvcfg_uop_T_54, _ex_setvcfg_uop_T_55) wire _ex_setvcfg_uop_WIRE_21 : UInt<2> connect _ex_setvcfg_uop_WIRE_21, _ex_setvcfg_uop_T_56 connect _ex_setvcfg_uop_WIRE_4.typeTagIn, _ex_setvcfg_uop_WIRE_21 node _ex_setvcfg_uop_T_57 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ex_setvcfg_uop_T_58 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ex_setvcfg_uop_T_59 = or(_ex_setvcfg_uop_T_57, _ex_setvcfg_uop_T_58) wire _ex_setvcfg_uop_WIRE_22 : UInt<1> connect _ex_setvcfg_uop_WIRE_22, _ex_setvcfg_uop_T_59 connect _ex_setvcfg_uop_WIRE_4.swap23, _ex_setvcfg_uop_WIRE_22 node _ex_setvcfg_uop_T_60 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ex_setvcfg_uop_T_61 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ex_setvcfg_uop_T_62 = or(_ex_setvcfg_uop_T_60, _ex_setvcfg_uop_T_61) wire _ex_setvcfg_uop_WIRE_23 : UInt<1> connect _ex_setvcfg_uop_WIRE_23, _ex_setvcfg_uop_T_62 connect _ex_setvcfg_uop_WIRE_4.swap12, _ex_setvcfg_uop_WIRE_23 node _ex_setvcfg_uop_T_63 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_64 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_65 = or(_ex_setvcfg_uop_T_63, _ex_setvcfg_uop_T_64) wire _ex_setvcfg_uop_WIRE_24 : UInt<1> connect _ex_setvcfg_uop_WIRE_24, _ex_setvcfg_uop_T_65 connect _ex_setvcfg_uop_WIRE_4.ren3, _ex_setvcfg_uop_WIRE_24 node _ex_setvcfg_uop_T_66 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_67 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_68 = or(_ex_setvcfg_uop_T_66, _ex_setvcfg_uop_T_67) wire _ex_setvcfg_uop_WIRE_25 : UInt<1> connect _ex_setvcfg_uop_WIRE_25, _ex_setvcfg_uop_T_68 connect _ex_setvcfg_uop_WIRE_4.ren2, _ex_setvcfg_uop_WIRE_25 node _ex_setvcfg_uop_T_69 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_70 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_71 = or(_ex_setvcfg_uop_T_69, _ex_setvcfg_uop_T_70) wire _ex_setvcfg_uop_WIRE_26 : UInt<1> connect _ex_setvcfg_uop_WIRE_26, _ex_setvcfg_uop_T_71 connect _ex_setvcfg_uop_WIRE_4.ren1, _ex_setvcfg_uop_WIRE_26 node _ex_setvcfg_uop_T_72 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.wen, UInt<1>(0h0)) node _ex_setvcfg_uop_T_73 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.wen, UInt<1>(0h0)) node _ex_setvcfg_uop_T_74 = or(_ex_setvcfg_uop_T_72, _ex_setvcfg_uop_T_73) wire _ex_setvcfg_uop_WIRE_27 : UInt<1> connect _ex_setvcfg_uop_WIRE_27, _ex_setvcfg_uop_T_74 connect _ex_setvcfg_uop_WIRE_4.wen, _ex_setvcfg_uop_WIRE_27 node _ex_setvcfg_uop_T_75 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_76 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_77 = or(_ex_setvcfg_uop_T_75, _ex_setvcfg_uop_T_76) wire _ex_setvcfg_uop_WIRE_28 : UInt<1> connect _ex_setvcfg_uop_WIRE_28, _ex_setvcfg_uop_T_77 connect _ex_setvcfg_uop_WIRE_4.ldst, _ex_setvcfg_uop_WIRE_28 connect _ex_setvcfg_uop_WIRE_1.fdivin, _ex_setvcfg_uop_WIRE_4 node _ex_setvcfg_uop_T_78 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fexc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_79 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fexc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_80 = or(_ex_setvcfg_uop_T_78, _ex_setvcfg_uop_T_79) wire _ex_setvcfg_uop_WIRE_29 : UInt<5> connect _ex_setvcfg_uop_WIRE_29, _ex_setvcfg_uop_T_80 connect _ex_setvcfg_uop_WIRE_1.fexc, _ex_setvcfg_uop_WIRE_29 node _ex_setvcfg_uop_T_81 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fra3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_82 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fra3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_83 = or(_ex_setvcfg_uop_T_81, _ex_setvcfg_uop_T_82) wire _ex_setvcfg_uop_WIRE_30 : UInt<5> connect _ex_setvcfg_uop_WIRE_30, _ex_setvcfg_uop_T_83 connect _ex_setvcfg_uop_WIRE_1.fra3, _ex_setvcfg_uop_WIRE_30 node _ex_setvcfg_uop_T_84 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fra2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_85 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fra2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_86 = or(_ex_setvcfg_uop_T_84, _ex_setvcfg_uop_T_85) wire _ex_setvcfg_uop_WIRE_31 : UInt<5> connect _ex_setvcfg_uop_WIRE_31, _ex_setvcfg_uop_T_86 connect _ex_setvcfg_uop_WIRE_1.fra2, _ex_setvcfg_uop_WIRE_31 node _ex_setvcfg_uop_T_87 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fra1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_88 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fra1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_89 = or(_ex_setvcfg_uop_T_87, _ex_setvcfg_uop_T_88) wire _ex_setvcfg_uop_WIRE_32 : UInt<5> connect _ex_setvcfg_uop_WIRE_32, _ex_setvcfg_uop_T_89 connect _ex_setvcfg_uop_WIRE_1.fra1, _ex_setvcfg_uop_WIRE_32 wire _ex_setvcfg_uop_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _ex_setvcfg_uop_T_90 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.wdata.bits, UInt<1>(0h0)) node _ex_setvcfg_uop_T_91 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.wdata.bits, UInt<1>(0h0)) node _ex_setvcfg_uop_T_92 = or(_ex_setvcfg_uop_T_90, _ex_setvcfg_uop_T_91) wire _ex_setvcfg_uop_WIRE_34 : UInt<64> connect _ex_setvcfg_uop_WIRE_34, _ex_setvcfg_uop_T_92 connect _ex_setvcfg_uop_WIRE_33.bits, _ex_setvcfg_uop_WIRE_34 node _ex_setvcfg_uop_T_93 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.wdata.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_94 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.wdata.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_95 = or(_ex_setvcfg_uop_T_93, _ex_setvcfg_uop_T_94) wire _ex_setvcfg_uop_WIRE_35 : UInt<1> connect _ex_setvcfg_uop_WIRE_35, _ex_setvcfg_uop_T_95 connect _ex_setvcfg_uop_WIRE_33.valid, _ex_setvcfg_uop_WIRE_35 connect _ex_setvcfg_uop_WIRE_1.wdata, _ex_setvcfg_uop_WIRE_33 node _ex_setvcfg_uop_T_96 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _ex_setvcfg_uop_T_97 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _ex_setvcfg_uop_T_98 = or(_ex_setvcfg_uop_T_96, _ex_setvcfg_uop_T_97) wire _ex_setvcfg_uop_WIRE_36 : UInt<1> connect _ex_setvcfg_uop_WIRE_36, _ex_setvcfg_uop_T_98 connect _ex_setvcfg_uop_WIRE_1.uses_latealu, _ex_setvcfg_uop_WIRE_36 node _ex_setvcfg_uop_T_99 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _ex_setvcfg_uop_T_100 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _ex_setvcfg_uop_T_101 = or(_ex_setvcfg_uop_T_99, _ex_setvcfg_uop_T_100) wire _ex_setvcfg_uop_WIRE_37 : UInt<1> connect _ex_setvcfg_uop_WIRE_37, _ex_setvcfg_uop_T_101 connect _ex_setvcfg_uop_WIRE_1.uses_memalu, _ex_setvcfg_uop_WIRE_37 node _ex_setvcfg_uop_T_102 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.rs3_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_103 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.rs3_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_104 = or(_ex_setvcfg_uop_T_102, _ex_setvcfg_uop_T_103) wire _ex_setvcfg_uop_WIRE_38 : UInt<64> connect _ex_setvcfg_uop_WIRE_38, _ex_setvcfg_uop_T_104 connect _ex_setvcfg_uop_WIRE_1.rs3_data, _ex_setvcfg_uop_WIRE_38 node _ex_setvcfg_uop_T_105 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.rs2_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_106 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.rs2_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_107 = or(_ex_setvcfg_uop_T_105, _ex_setvcfg_uop_T_106) wire _ex_setvcfg_uop_WIRE_39 : UInt<64> connect _ex_setvcfg_uop_WIRE_39, _ex_setvcfg_uop_T_107 connect _ex_setvcfg_uop_WIRE_1.rs2_data, _ex_setvcfg_uop_WIRE_39 node _ex_setvcfg_uop_T_108 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.rs1_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_109 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.rs1_data, UInt<1>(0h0)) node _ex_setvcfg_uop_T_110 = or(_ex_setvcfg_uop_T_108, _ex_setvcfg_uop_T_109) wire _ex_setvcfg_uop_WIRE_40 : UInt<64> connect _ex_setvcfg_uop_WIRE_40, _ex_setvcfg_uop_T_110 connect _ex_setvcfg_uop_WIRE_1.rs1_data, _ex_setvcfg_uop_WIRE_40 node _ex_setvcfg_uop_T_111 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.needs_replay, UInt<1>(0h0)) node _ex_setvcfg_uop_T_112 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.needs_replay, UInt<1>(0h0)) node _ex_setvcfg_uop_T_113 = or(_ex_setvcfg_uop_T_111, _ex_setvcfg_uop_T_112) wire _ex_setvcfg_uop_WIRE_41 : UInt<1> connect _ex_setvcfg_uop_WIRE_41, _ex_setvcfg_uop_T_113 connect _ex_setvcfg_uop_WIRE_1.needs_replay, _ex_setvcfg_uop_WIRE_41 node _ex_setvcfg_uop_T_114 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.xcpt_cause, UInt<1>(0h0)) node _ex_setvcfg_uop_T_115 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.xcpt_cause, UInt<1>(0h0)) node _ex_setvcfg_uop_T_116 = or(_ex_setvcfg_uop_T_114, _ex_setvcfg_uop_T_115) wire _ex_setvcfg_uop_WIRE_42 : UInt<64> connect _ex_setvcfg_uop_WIRE_42, _ex_setvcfg_uop_T_116 connect _ex_setvcfg_uop_WIRE_1.xcpt_cause, _ex_setvcfg_uop_WIRE_42 node _ex_setvcfg_uop_T_117 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_118 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.xcpt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_119 = or(_ex_setvcfg_uop_T_117, _ex_setvcfg_uop_T_118) wire _ex_setvcfg_uop_WIRE_43 : UInt<1> connect _ex_setvcfg_uop_WIRE_43, _ex_setvcfg_uop_T_119 connect _ex_setvcfg_uop_WIRE_1.xcpt, _ex_setvcfg_uop_WIRE_43 node _ex_setvcfg_uop_T_120 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.taken, UInt<1>(0h0)) node _ex_setvcfg_uop_T_121 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.taken, UInt<1>(0h0)) node _ex_setvcfg_uop_T_122 = or(_ex_setvcfg_uop_T_120, _ex_setvcfg_uop_T_121) wire _ex_setvcfg_uop_WIRE_44 : UInt<1> connect _ex_setvcfg_uop_WIRE_44, _ex_setvcfg_uop_T_122 connect _ex_setvcfg_uop_WIRE_1.taken, _ex_setvcfg_uop_WIRE_44 node _ex_setvcfg_uop_T_123 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ras_head, UInt<1>(0h0)) node _ex_setvcfg_uop_T_124 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ras_head, UInt<1>(0h0)) node _ex_setvcfg_uop_T_125 = or(_ex_setvcfg_uop_T_123, _ex_setvcfg_uop_T_124) wire _ex_setvcfg_uop_WIRE_45 : UInt<3> connect _ex_setvcfg_uop_WIRE_45, _ex_setvcfg_uop_T_125 connect _ex_setvcfg_uop_WIRE_1.ras_head, _ex_setvcfg_uop_WIRE_45 wire _ex_setvcfg_uop_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _ex_setvcfg_uop_T_126 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.next_pc.bits, UInt<1>(0h0)) node _ex_setvcfg_uop_T_127 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.next_pc.bits, UInt<1>(0h0)) node _ex_setvcfg_uop_T_128 = or(_ex_setvcfg_uop_T_126, _ex_setvcfg_uop_T_127) wire _ex_setvcfg_uop_WIRE_47 : UInt<40> connect _ex_setvcfg_uop_WIRE_47, _ex_setvcfg_uop_T_128 connect _ex_setvcfg_uop_WIRE_46.bits, _ex_setvcfg_uop_WIRE_47 node _ex_setvcfg_uop_T_129 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.next_pc.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_130 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.next_pc.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_131 = or(_ex_setvcfg_uop_T_129, _ex_setvcfg_uop_T_130) wire _ex_setvcfg_uop_WIRE_48 : UInt<1> connect _ex_setvcfg_uop_WIRE_48, _ex_setvcfg_uop_T_131 connect _ex_setvcfg_uop_WIRE_46.valid, _ex_setvcfg_uop_WIRE_48 connect _ex_setvcfg_uop_WIRE_1.next_pc, _ex_setvcfg_uop_WIRE_46 node _ex_setvcfg_uop_T_132 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.sfb_shadow, UInt<1>(0h0)) node _ex_setvcfg_uop_T_133 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _ex_setvcfg_uop_T_134 = or(_ex_setvcfg_uop_T_132, _ex_setvcfg_uop_T_133) wire _ex_setvcfg_uop_WIRE_49 : UInt<1> connect _ex_setvcfg_uop_WIRE_49, _ex_setvcfg_uop_T_134 connect _ex_setvcfg_uop_WIRE_1.sfb_shadow, _ex_setvcfg_uop_WIRE_49 node _ex_setvcfg_uop_T_135 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.sfb_br, UInt<1>(0h0)) node _ex_setvcfg_uop_T_136 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.sfb_br, UInt<1>(0h0)) node _ex_setvcfg_uop_T_137 = or(_ex_setvcfg_uop_T_135, _ex_setvcfg_uop_T_136) wire _ex_setvcfg_uop_WIRE_50 : UInt<1> connect _ex_setvcfg_uop_WIRE_50, _ex_setvcfg_uop_T_137 connect _ex_setvcfg_uop_WIRE_1.sfb_br, _ex_setvcfg_uop_WIRE_50 wire _ex_setvcfg_uop_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ex_setvcfg_uop_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ex_setvcfg_uop_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _ex_setvcfg_uop_T_138 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ex_setvcfg_uop_T_139 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ex_setvcfg_uop_T_140 = or(_ex_setvcfg_uop_T_138, _ex_setvcfg_uop_T_139) wire _ex_setvcfg_uop_WIRE_54 : UInt<2> connect _ex_setvcfg_uop_WIRE_54, _ex_setvcfg_uop_T_140 connect _ex_setvcfg_uop_WIRE_53.value, _ex_setvcfg_uop_WIRE_54 node _ex_setvcfg_uop_T_141 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ex_setvcfg_uop_T_142 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ex_setvcfg_uop_T_143 = or(_ex_setvcfg_uop_T_141, _ex_setvcfg_uop_T_142) wire _ex_setvcfg_uop_WIRE_55 : UInt<8> connect _ex_setvcfg_uop_WIRE_55, _ex_setvcfg_uop_T_143 connect _ex_setvcfg_uop_WIRE_53.history, _ex_setvcfg_uop_WIRE_55 connect _ex_setvcfg_uop_WIRE_52.bht, _ex_setvcfg_uop_WIRE_53 node _ex_setvcfg_uop_T_144 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ex_setvcfg_uop_T_145 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ex_setvcfg_uop_T_146 = or(_ex_setvcfg_uop_T_144, _ex_setvcfg_uop_T_145) wire _ex_setvcfg_uop_WIRE_56 : UInt<6> connect _ex_setvcfg_uop_WIRE_56, _ex_setvcfg_uop_T_146 connect _ex_setvcfg_uop_WIRE_52.entry, _ex_setvcfg_uop_WIRE_56 node _ex_setvcfg_uop_T_147 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ex_setvcfg_uop_T_148 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ex_setvcfg_uop_T_149 = or(_ex_setvcfg_uop_T_147, _ex_setvcfg_uop_T_148) wire _ex_setvcfg_uop_WIRE_57 : UInt<39> connect _ex_setvcfg_uop_WIRE_57, _ex_setvcfg_uop_T_149 connect _ex_setvcfg_uop_WIRE_52.target, _ex_setvcfg_uop_WIRE_57 node _ex_setvcfg_uop_T_150 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ex_setvcfg_uop_T_151 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ex_setvcfg_uop_T_152 = or(_ex_setvcfg_uop_T_150, _ex_setvcfg_uop_T_151) wire _ex_setvcfg_uop_WIRE_58 : UInt<2> connect _ex_setvcfg_uop_WIRE_58, _ex_setvcfg_uop_T_152 connect _ex_setvcfg_uop_WIRE_52.bridx, _ex_setvcfg_uop_WIRE_58 node _ex_setvcfg_uop_T_153 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ex_setvcfg_uop_T_154 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ex_setvcfg_uop_T_155 = or(_ex_setvcfg_uop_T_153, _ex_setvcfg_uop_T_154) wire _ex_setvcfg_uop_WIRE_59 : UInt<4> connect _ex_setvcfg_uop_WIRE_59, _ex_setvcfg_uop_T_155 connect _ex_setvcfg_uop_WIRE_52.mask, _ex_setvcfg_uop_WIRE_59 node _ex_setvcfg_uop_T_156 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ex_setvcfg_uop_T_157 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ex_setvcfg_uop_T_158 = or(_ex_setvcfg_uop_T_156, _ex_setvcfg_uop_T_157) wire _ex_setvcfg_uop_WIRE_60 : UInt<1> connect _ex_setvcfg_uop_WIRE_60, _ex_setvcfg_uop_T_158 connect _ex_setvcfg_uop_WIRE_52.taken, _ex_setvcfg_uop_WIRE_60 node _ex_setvcfg_uop_T_159 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ex_setvcfg_uop_T_160 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ex_setvcfg_uop_T_161 = or(_ex_setvcfg_uop_T_159, _ex_setvcfg_uop_T_160) wire _ex_setvcfg_uop_WIRE_61 : UInt<2> connect _ex_setvcfg_uop_WIRE_61, _ex_setvcfg_uop_T_161 connect _ex_setvcfg_uop_WIRE_52.cfiType, _ex_setvcfg_uop_WIRE_61 connect _ex_setvcfg_uop_WIRE_51.bits, _ex_setvcfg_uop_WIRE_52 node _ex_setvcfg_uop_T_162 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_163 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_164 = or(_ex_setvcfg_uop_T_162, _ex_setvcfg_uop_T_163) wire _ex_setvcfg_uop_WIRE_62 : UInt<1> connect _ex_setvcfg_uop_WIRE_62, _ex_setvcfg_uop_T_164 connect _ex_setvcfg_uop_WIRE_51.valid, _ex_setvcfg_uop_WIRE_62 connect _ex_setvcfg_uop_WIRE_1.btb_resp, _ex_setvcfg_uop_WIRE_51 node _ex_setvcfg_uop_T_165 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.sets_vcfg, UInt<1>(0h0)) node _ex_setvcfg_uop_T_166 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.sets_vcfg, UInt<1>(0h0)) node _ex_setvcfg_uop_T_167 = or(_ex_setvcfg_uop_T_165, _ex_setvcfg_uop_T_166) wire _ex_setvcfg_uop_WIRE_63 : UInt<1> connect _ex_setvcfg_uop_WIRE_63, _ex_setvcfg_uop_T_167 connect _ex_setvcfg_uop_WIRE_1.sets_vcfg, _ex_setvcfg_uop_WIRE_63 node _ex_setvcfg_uop_T_168 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.rvc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_169 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.rvc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_170 = or(_ex_setvcfg_uop_T_168, _ex_setvcfg_uop_T_169) wire _ex_setvcfg_uop_WIRE_64 : UInt<1> connect _ex_setvcfg_uop_WIRE_64, _ex_setvcfg_uop_T_170 connect _ex_setvcfg_uop_WIRE_1.rvc, _ex_setvcfg_uop_WIRE_64 wire _ex_setvcfg_uop_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ex_setvcfg_uop_T_171 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_172 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_173 = or(_ex_setvcfg_uop_T_171, _ex_setvcfg_uop_T_172) wire _ex_setvcfg_uop_WIRE_66 : UInt<1> connect _ex_setvcfg_uop_WIRE_66, _ex_setvcfg_uop_T_173 connect _ex_setvcfg_uop_WIRE_65.vec, _ex_setvcfg_uop_WIRE_66 node _ex_setvcfg_uop_T_174 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ex_setvcfg_uop_T_175 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ex_setvcfg_uop_T_176 = or(_ex_setvcfg_uop_T_174, _ex_setvcfg_uop_T_175) wire _ex_setvcfg_uop_WIRE_67 : UInt<1> connect _ex_setvcfg_uop_WIRE_67, _ex_setvcfg_uop_T_176 connect _ex_setvcfg_uop_WIRE_65.wflags, _ex_setvcfg_uop_WIRE_67 node _ex_setvcfg_uop_T_177 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_178 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ex_setvcfg_uop_T_179 = or(_ex_setvcfg_uop_T_177, _ex_setvcfg_uop_T_178) wire _ex_setvcfg_uop_WIRE_68 : UInt<1> connect _ex_setvcfg_uop_WIRE_68, _ex_setvcfg_uop_T_179 connect _ex_setvcfg_uop_WIRE_65.sqrt, _ex_setvcfg_uop_WIRE_68 node _ex_setvcfg_uop_T_180 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_181 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_182 = or(_ex_setvcfg_uop_T_180, _ex_setvcfg_uop_T_181) wire _ex_setvcfg_uop_WIRE_69 : UInt<1> connect _ex_setvcfg_uop_WIRE_69, _ex_setvcfg_uop_T_182 connect _ex_setvcfg_uop_WIRE_65.div, _ex_setvcfg_uop_WIRE_69 node _ex_setvcfg_uop_T_183 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ex_setvcfg_uop_T_184 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ex_setvcfg_uop_T_185 = or(_ex_setvcfg_uop_T_183, _ex_setvcfg_uop_T_184) wire _ex_setvcfg_uop_WIRE_70 : UInt<1> connect _ex_setvcfg_uop_WIRE_70, _ex_setvcfg_uop_T_185 connect _ex_setvcfg_uop_WIRE_65.fma, _ex_setvcfg_uop_WIRE_70 node _ex_setvcfg_uop_T_186 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_187 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ex_setvcfg_uop_T_188 = or(_ex_setvcfg_uop_T_186, _ex_setvcfg_uop_T_187) wire _ex_setvcfg_uop_WIRE_71 : UInt<1> connect _ex_setvcfg_uop_WIRE_71, _ex_setvcfg_uop_T_188 connect _ex_setvcfg_uop_WIRE_65.fastpipe, _ex_setvcfg_uop_WIRE_71 node _ex_setvcfg_uop_T_189 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_190 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_191 = or(_ex_setvcfg_uop_T_189, _ex_setvcfg_uop_T_190) wire _ex_setvcfg_uop_WIRE_72 : UInt<1> connect _ex_setvcfg_uop_WIRE_72, _ex_setvcfg_uop_T_191 connect _ex_setvcfg_uop_WIRE_65.toint, _ex_setvcfg_uop_WIRE_72 node _ex_setvcfg_uop_T_192 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_193 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ex_setvcfg_uop_T_194 = or(_ex_setvcfg_uop_T_192, _ex_setvcfg_uop_T_193) wire _ex_setvcfg_uop_WIRE_73 : UInt<1> connect _ex_setvcfg_uop_WIRE_73, _ex_setvcfg_uop_T_194 connect _ex_setvcfg_uop_WIRE_65.fromint, _ex_setvcfg_uop_WIRE_73 node _ex_setvcfg_uop_T_195 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ex_setvcfg_uop_T_196 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ex_setvcfg_uop_T_197 = or(_ex_setvcfg_uop_T_195, _ex_setvcfg_uop_T_196) wire _ex_setvcfg_uop_WIRE_74 : UInt<2> connect _ex_setvcfg_uop_WIRE_74, _ex_setvcfg_uop_T_197 connect _ex_setvcfg_uop_WIRE_65.typeTagOut, _ex_setvcfg_uop_WIRE_74 node _ex_setvcfg_uop_T_198 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_199 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_200 = or(_ex_setvcfg_uop_T_198, _ex_setvcfg_uop_T_199) wire _ex_setvcfg_uop_WIRE_75 : UInt<2> connect _ex_setvcfg_uop_WIRE_75, _ex_setvcfg_uop_T_200 connect _ex_setvcfg_uop_WIRE_65.typeTagIn, _ex_setvcfg_uop_WIRE_75 node _ex_setvcfg_uop_T_201 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ex_setvcfg_uop_T_202 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ex_setvcfg_uop_T_203 = or(_ex_setvcfg_uop_T_201, _ex_setvcfg_uop_T_202) wire _ex_setvcfg_uop_WIRE_76 : UInt<1> connect _ex_setvcfg_uop_WIRE_76, _ex_setvcfg_uop_T_203 connect _ex_setvcfg_uop_WIRE_65.swap23, _ex_setvcfg_uop_WIRE_76 node _ex_setvcfg_uop_T_204 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ex_setvcfg_uop_T_205 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ex_setvcfg_uop_T_206 = or(_ex_setvcfg_uop_T_204, _ex_setvcfg_uop_T_205) wire _ex_setvcfg_uop_WIRE_77 : UInt<1> connect _ex_setvcfg_uop_WIRE_77, _ex_setvcfg_uop_T_206 connect _ex_setvcfg_uop_WIRE_65.swap12, _ex_setvcfg_uop_WIRE_77 node _ex_setvcfg_uop_T_207 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_208 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_209 = or(_ex_setvcfg_uop_T_207, _ex_setvcfg_uop_T_208) wire _ex_setvcfg_uop_WIRE_78 : UInt<1> connect _ex_setvcfg_uop_WIRE_78, _ex_setvcfg_uop_T_209 connect _ex_setvcfg_uop_WIRE_65.ren3, _ex_setvcfg_uop_WIRE_78 node _ex_setvcfg_uop_T_210 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_211 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_212 = or(_ex_setvcfg_uop_T_210, _ex_setvcfg_uop_T_211) wire _ex_setvcfg_uop_WIRE_79 : UInt<1> connect _ex_setvcfg_uop_WIRE_79, _ex_setvcfg_uop_T_212 connect _ex_setvcfg_uop_WIRE_65.ren2, _ex_setvcfg_uop_WIRE_79 node _ex_setvcfg_uop_T_213 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_214 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_215 = or(_ex_setvcfg_uop_T_213, _ex_setvcfg_uop_T_214) wire _ex_setvcfg_uop_WIRE_80 : UInt<1> connect _ex_setvcfg_uop_WIRE_80, _ex_setvcfg_uop_T_215 connect _ex_setvcfg_uop_WIRE_65.ren1, _ex_setvcfg_uop_WIRE_80 node _ex_setvcfg_uop_T_216 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ex_setvcfg_uop_T_217 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ex_setvcfg_uop_T_218 = or(_ex_setvcfg_uop_T_216, _ex_setvcfg_uop_T_217) wire _ex_setvcfg_uop_WIRE_81 : UInt<1> connect _ex_setvcfg_uop_WIRE_81, _ex_setvcfg_uop_T_218 connect _ex_setvcfg_uop_WIRE_65.wen, _ex_setvcfg_uop_WIRE_81 node _ex_setvcfg_uop_T_219 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_220 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_221 = or(_ex_setvcfg_uop_T_219, _ex_setvcfg_uop_T_220) wire _ex_setvcfg_uop_WIRE_82 : UInt<1> connect _ex_setvcfg_uop_WIRE_82, _ex_setvcfg_uop_T_221 connect _ex_setvcfg_uop_WIRE_65.ldst, _ex_setvcfg_uop_WIRE_82 connect _ex_setvcfg_uop_WIRE_1.fp_ctrl, _ex_setvcfg_uop_WIRE_65 wire _ex_setvcfg_uop_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ex_setvcfg_uop_T_222 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_223 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _ex_setvcfg_uop_T_224 = or(_ex_setvcfg_uop_T_222, _ex_setvcfg_uop_T_223) wire _ex_setvcfg_uop_WIRE_84 : UInt<1> connect _ex_setvcfg_uop_WIRE_84, _ex_setvcfg_uop_T_224 connect _ex_setvcfg_uop_WIRE_83.vec, _ex_setvcfg_uop_WIRE_84 node _ex_setvcfg_uop_T_225 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.dp, UInt<1>(0h0)) node _ex_setvcfg_uop_T_226 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.dp, UInt<1>(0h0)) node _ex_setvcfg_uop_T_227 = or(_ex_setvcfg_uop_T_225, _ex_setvcfg_uop_T_226) wire _ex_setvcfg_uop_WIRE_85 : UInt<1> connect _ex_setvcfg_uop_WIRE_85, _ex_setvcfg_uop_T_227 connect _ex_setvcfg_uop_WIRE_83.dp, _ex_setvcfg_uop_WIRE_85 node _ex_setvcfg_uop_T_228 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.amo, UInt<1>(0h0)) node _ex_setvcfg_uop_T_229 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.amo, UInt<1>(0h0)) node _ex_setvcfg_uop_T_230 = or(_ex_setvcfg_uop_T_228, _ex_setvcfg_uop_T_229) wire _ex_setvcfg_uop_WIRE_86 : UInt<1> connect _ex_setvcfg_uop_WIRE_86, _ex_setvcfg_uop_T_230 connect _ex_setvcfg_uop_WIRE_83.amo, _ex_setvcfg_uop_WIRE_86 node _ex_setvcfg_uop_T_231 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.fence, UInt<1>(0h0)) node _ex_setvcfg_uop_T_232 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.fence, UInt<1>(0h0)) node _ex_setvcfg_uop_T_233 = or(_ex_setvcfg_uop_T_231, _ex_setvcfg_uop_T_232) wire _ex_setvcfg_uop_WIRE_87 : UInt<1> connect _ex_setvcfg_uop_WIRE_87, _ex_setvcfg_uop_T_233 connect _ex_setvcfg_uop_WIRE_83.fence, _ex_setvcfg_uop_WIRE_87 node _ex_setvcfg_uop_T_234 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ex_setvcfg_uop_T_235 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ex_setvcfg_uop_T_236 = or(_ex_setvcfg_uop_T_234, _ex_setvcfg_uop_T_235) wire _ex_setvcfg_uop_WIRE_88 : UInt<1> connect _ex_setvcfg_uop_WIRE_88, _ex_setvcfg_uop_T_236 connect _ex_setvcfg_uop_WIRE_83.fence_i, _ex_setvcfg_uop_WIRE_88 node _ex_setvcfg_uop_T_237 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.csr, UInt<1>(0h0)) node _ex_setvcfg_uop_T_238 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.csr, UInt<1>(0h0)) node _ex_setvcfg_uop_T_239 = or(_ex_setvcfg_uop_T_237, _ex_setvcfg_uop_T_238) wire _ex_setvcfg_uop_WIRE_89 : UInt<3> connect _ex_setvcfg_uop_WIRE_89, _ex_setvcfg_uop_T_239 connect _ex_setvcfg_uop_WIRE_83.csr, _ex_setvcfg_uop_WIRE_89 node _ex_setvcfg_uop_T_240 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_241 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_242 = or(_ex_setvcfg_uop_T_240, _ex_setvcfg_uop_T_241) wire _ex_setvcfg_uop_WIRE_90 : UInt<1> connect _ex_setvcfg_uop_WIRE_90, _ex_setvcfg_uop_T_242 connect _ex_setvcfg_uop_WIRE_83.wxd, _ex_setvcfg_uop_WIRE_90 node _ex_setvcfg_uop_T_243 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_244 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _ex_setvcfg_uop_T_245 = or(_ex_setvcfg_uop_T_243, _ex_setvcfg_uop_T_244) wire _ex_setvcfg_uop_WIRE_91 : UInt<1> connect _ex_setvcfg_uop_WIRE_91, _ex_setvcfg_uop_T_245 connect _ex_setvcfg_uop_WIRE_83.div, _ex_setvcfg_uop_WIRE_91 node _ex_setvcfg_uop_T_246 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _ex_setvcfg_uop_T_247 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _ex_setvcfg_uop_T_248 = or(_ex_setvcfg_uop_T_246, _ex_setvcfg_uop_T_247) wire _ex_setvcfg_uop_WIRE_92 : UInt<1> connect _ex_setvcfg_uop_WIRE_92, _ex_setvcfg_uop_T_248 connect _ex_setvcfg_uop_WIRE_83.mul, _ex_setvcfg_uop_WIRE_92 node _ex_setvcfg_uop_T_249 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_250 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_251 = or(_ex_setvcfg_uop_T_249, _ex_setvcfg_uop_T_250) wire _ex_setvcfg_uop_WIRE_93 : UInt<1> connect _ex_setvcfg_uop_WIRE_93, _ex_setvcfg_uop_T_251 connect _ex_setvcfg_uop_WIRE_83.wfd, _ex_setvcfg_uop_WIRE_93 node _ex_setvcfg_uop_T_252 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_253 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ex_setvcfg_uop_T_254 = or(_ex_setvcfg_uop_T_252, _ex_setvcfg_uop_T_253) wire _ex_setvcfg_uop_WIRE_94 : UInt<1> connect _ex_setvcfg_uop_WIRE_94, _ex_setvcfg_uop_T_254 connect _ex_setvcfg_uop_WIRE_83.rfs3, _ex_setvcfg_uop_WIRE_94 node _ex_setvcfg_uop_T_255 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_256 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_257 = or(_ex_setvcfg_uop_T_255, _ex_setvcfg_uop_T_256) wire _ex_setvcfg_uop_WIRE_95 : UInt<1> connect _ex_setvcfg_uop_WIRE_95, _ex_setvcfg_uop_T_257 connect _ex_setvcfg_uop_WIRE_83.rfs2, _ex_setvcfg_uop_WIRE_95 node _ex_setvcfg_uop_T_258 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_259 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_260 = or(_ex_setvcfg_uop_T_258, _ex_setvcfg_uop_T_259) wire _ex_setvcfg_uop_WIRE_96 : UInt<1> connect _ex_setvcfg_uop_WIRE_96, _ex_setvcfg_uop_T_260 connect _ex_setvcfg_uop_WIRE_83.rfs1, _ex_setvcfg_uop_WIRE_96 node _ex_setvcfg_uop_T_261 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_262 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ex_setvcfg_uop_T_263 = or(_ex_setvcfg_uop_T_261, _ex_setvcfg_uop_T_262) wire _ex_setvcfg_uop_WIRE_97 : UInt<5> connect _ex_setvcfg_uop_WIRE_97, _ex_setvcfg_uop_T_263 connect _ex_setvcfg_uop_WIRE_83.mem_cmd, _ex_setvcfg_uop_WIRE_97 node _ex_setvcfg_uop_T_264 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _ex_setvcfg_uop_T_265 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _ex_setvcfg_uop_T_266 = or(_ex_setvcfg_uop_T_264, _ex_setvcfg_uop_T_265) wire _ex_setvcfg_uop_WIRE_98 : UInt<1> connect _ex_setvcfg_uop_WIRE_98, _ex_setvcfg_uop_T_266 connect _ex_setvcfg_uop_WIRE_83.mem, _ex_setvcfg_uop_WIRE_98 node _ex_setvcfg_uop_T_267 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_268 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ex_setvcfg_uop_T_269 = or(_ex_setvcfg_uop_T_267, _ex_setvcfg_uop_T_268) wire _ex_setvcfg_uop_WIRE_99 : UInt<5> connect _ex_setvcfg_uop_WIRE_99, _ex_setvcfg_uop_T_269 connect _ex_setvcfg_uop_WIRE_83.alu_fn, _ex_setvcfg_uop_WIRE_99 node _ex_setvcfg_uop_T_270 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ex_setvcfg_uop_T_271 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ex_setvcfg_uop_T_272 = or(_ex_setvcfg_uop_T_270, _ex_setvcfg_uop_T_271) wire _ex_setvcfg_uop_WIRE_100 : UInt<1> connect _ex_setvcfg_uop_WIRE_100, _ex_setvcfg_uop_T_272 connect _ex_setvcfg_uop_WIRE_83.alu_dw, _ex_setvcfg_uop_WIRE_100 node _ex_setvcfg_uop_T_273 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ex_setvcfg_uop_T_274 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ex_setvcfg_uop_T_275 = or(_ex_setvcfg_uop_T_273, _ex_setvcfg_uop_T_274) wire _ex_setvcfg_uop_WIRE_101 : UInt<3> connect _ex_setvcfg_uop_WIRE_101, _ex_setvcfg_uop_T_275 connect _ex_setvcfg_uop_WIRE_83.sel_imm, _ex_setvcfg_uop_WIRE_101 node _ex_setvcfg_uop_T_276 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_277 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_278 = or(_ex_setvcfg_uop_T_276, _ex_setvcfg_uop_T_277) wire _ex_setvcfg_uop_WIRE_102 : UInt<2> connect _ex_setvcfg_uop_WIRE_102, _ex_setvcfg_uop_T_278 connect _ex_setvcfg_uop_WIRE_83.sel_alu1, _ex_setvcfg_uop_WIRE_102 node _ex_setvcfg_uop_T_279 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_280 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_281 = or(_ex_setvcfg_uop_T_279, _ex_setvcfg_uop_T_280) wire _ex_setvcfg_uop_WIRE_103 : UInt<3> connect _ex_setvcfg_uop_WIRE_103, _ex_setvcfg_uop_T_281 connect _ex_setvcfg_uop_WIRE_83.sel_alu2, _ex_setvcfg_uop_WIRE_103 node _ex_setvcfg_uop_T_282 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_283 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ex_setvcfg_uop_T_284 = or(_ex_setvcfg_uop_T_282, _ex_setvcfg_uop_T_283) wire _ex_setvcfg_uop_WIRE_104 : UInt<1> connect _ex_setvcfg_uop_WIRE_104, _ex_setvcfg_uop_T_284 connect _ex_setvcfg_uop_WIRE_83.rxs1, _ex_setvcfg_uop_WIRE_104 node _ex_setvcfg_uop_T_285 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_286 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ex_setvcfg_uop_T_287 = or(_ex_setvcfg_uop_T_285, _ex_setvcfg_uop_T_286) wire _ex_setvcfg_uop_WIRE_105 : UInt<1> connect _ex_setvcfg_uop_WIRE_105, _ex_setvcfg_uop_T_287 connect _ex_setvcfg_uop_WIRE_83.rxs2, _ex_setvcfg_uop_WIRE_105 node _ex_setvcfg_uop_T_288 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_setvcfg_uop_T_289 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_setvcfg_uop_T_290 = or(_ex_setvcfg_uop_T_288, _ex_setvcfg_uop_T_289) wire _ex_setvcfg_uop_WIRE_106 : UInt<1> connect _ex_setvcfg_uop_WIRE_106, _ex_setvcfg_uop_T_290 connect _ex_setvcfg_uop_WIRE_83.jalr, _ex_setvcfg_uop_WIRE_106 node _ex_setvcfg_uop_T_291 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.jal, UInt<1>(0h0)) node _ex_setvcfg_uop_T_292 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.jal, UInt<1>(0h0)) node _ex_setvcfg_uop_T_293 = or(_ex_setvcfg_uop_T_291, _ex_setvcfg_uop_T_292) wire _ex_setvcfg_uop_WIRE_107 : UInt<1> connect _ex_setvcfg_uop_WIRE_107, _ex_setvcfg_uop_T_293 connect _ex_setvcfg_uop_WIRE_83.jal, _ex_setvcfg_uop_WIRE_107 node _ex_setvcfg_uop_T_294 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.branch, UInt<1>(0h0)) node _ex_setvcfg_uop_T_295 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.branch, UInt<1>(0h0)) node _ex_setvcfg_uop_T_296 = or(_ex_setvcfg_uop_T_294, _ex_setvcfg_uop_T_295) wire _ex_setvcfg_uop_WIRE_108 : UInt<1> connect _ex_setvcfg_uop_WIRE_108, _ex_setvcfg_uop_T_296 connect _ex_setvcfg_uop_WIRE_83.branch, _ex_setvcfg_uop_WIRE_108 node _ex_setvcfg_uop_T_297 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_298 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_299 = or(_ex_setvcfg_uop_T_297, _ex_setvcfg_uop_T_298) wire _ex_setvcfg_uop_WIRE_109 : UInt<1> connect _ex_setvcfg_uop_WIRE_109, _ex_setvcfg_uop_T_299 connect _ex_setvcfg_uop_WIRE_83.rocc, _ex_setvcfg_uop_WIRE_109 node _ex_setvcfg_uop_T_300 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _ex_setvcfg_uop_T_301 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _ex_setvcfg_uop_T_302 = or(_ex_setvcfg_uop_T_300, _ex_setvcfg_uop_T_301) wire _ex_setvcfg_uop_WIRE_110 : UInt<1> connect _ex_setvcfg_uop_WIRE_110, _ex_setvcfg_uop_T_302 connect _ex_setvcfg_uop_WIRE_83.fp, _ex_setvcfg_uop_WIRE_110 node _ex_setvcfg_uop_T_303 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.ctrl.legal, UInt<1>(0h0)) node _ex_setvcfg_uop_T_304 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.ctrl.legal, UInt<1>(0h0)) node _ex_setvcfg_uop_T_305 = or(_ex_setvcfg_uop_T_303, _ex_setvcfg_uop_T_304) wire _ex_setvcfg_uop_WIRE_111 : UInt<1> connect _ex_setvcfg_uop_WIRE_111, _ex_setvcfg_uop_T_305 connect _ex_setvcfg_uop_WIRE_83.legal, _ex_setvcfg_uop_WIRE_111 connect _ex_setvcfg_uop_WIRE_1.ctrl, _ex_setvcfg_uop_WIRE_83 node _ex_setvcfg_uop_T_306 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.edge_inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_307 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.edge_inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_308 = or(_ex_setvcfg_uop_T_306, _ex_setvcfg_uop_T_307) wire _ex_setvcfg_uop_WIRE_112 : UInt<1> connect _ex_setvcfg_uop_WIRE_112, _ex_setvcfg_uop_T_308 connect _ex_setvcfg_uop_WIRE_1.edge_inst, _ex_setvcfg_uop_WIRE_112 node _ex_setvcfg_uop_T_309 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.pc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_310 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.pc, UInt<1>(0h0)) node _ex_setvcfg_uop_T_311 = or(_ex_setvcfg_uop_T_309, _ex_setvcfg_uop_T_310) wire _ex_setvcfg_uop_WIRE_113 : UInt<40> connect _ex_setvcfg_uop_WIRE_113, _ex_setvcfg_uop_T_311 connect _ex_setvcfg_uop_WIRE_1.pc, _ex_setvcfg_uop_WIRE_113 node _ex_setvcfg_uop_T_312 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.raw_inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_313 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.raw_inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_314 = or(_ex_setvcfg_uop_T_312, _ex_setvcfg_uop_T_313) wire _ex_setvcfg_uop_WIRE_114 : UInt<32> connect _ex_setvcfg_uop_WIRE_114, _ex_setvcfg_uop_T_314 connect _ex_setvcfg_uop_WIRE_1.raw_inst, _ex_setvcfg_uop_WIRE_114 node _ex_setvcfg_uop_T_315 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].bits.inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_316 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].bits.inst, UInt<1>(0h0)) node _ex_setvcfg_uop_T_317 = or(_ex_setvcfg_uop_T_315, _ex_setvcfg_uop_T_316) wire _ex_setvcfg_uop_WIRE_115 : UInt<32> connect _ex_setvcfg_uop_WIRE_115, _ex_setvcfg_uop_T_317 connect _ex_setvcfg_uop_WIRE_1.inst, _ex_setvcfg_uop_WIRE_115 connect _ex_setvcfg_uop_WIRE.bits, _ex_setvcfg_uop_WIRE_1 node _ex_setvcfg_uop_T_318 = mux(ex_setvcfg_valid_0, ex_uops_reg[0].valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_319 = mux(ex_setvcfg_valid_1, ex_uops_reg[1].valid, UInt<1>(0h0)) node _ex_setvcfg_uop_T_320 = or(_ex_setvcfg_uop_T_318, _ex_setvcfg_uop_T_319) wire _ex_setvcfg_uop_WIRE_116 : UInt<1> connect _ex_setvcfg_uop_WIRE_116, _ex_setvcfg_uop_T_320 connect _ex_setvcfg_uop_WIRE.valid, _ex_setvcfg_uop_WIRE_116 inst mul of PipelinedMultiplier connect mul.clock, clock connect mul.reset, reset node _mul_io_req_valid_T = and(ex_uops_reg[0].valid, ex_uops_reg[0].bits.ctrl.mul) node _mul_io_req_valid_T_1 = eq(ex_stall, UInt<1>(0h0)) node _mul_io_req_valid_T_2 = and(_mul_io_req_valid_T, _mul_io_req_valid_T_1) connect mul.io.req.valid, _mul_io_req_valid_T_2 connect mul.io.req.bits.dw, ex_uops_reg[0].bits.ctrl.alu_dw connect mul.io.req.bits.fn, ex_uops_reg[0].bits.ctrl.alu_fn connect mul.io.req.bits.in1, ex_uops_reg[0].bits.rs1_data connect mul.io.req.bits.in2, ex_uops_reg[0].bits.rs2_data node _mul_io_req_bits_tag_T = bits(ex_uops_reg[0].bits.inst, 11, 7) connect mul.io.req.bits.tag, _mul_io_req_bits_tag_T node ex_dmem_oh_0 = and(ex_uops_reg[0].valid, ex_uops_reg[0].bits.ctrl.mem) node ex_dmem_oh_1 = and(ex_uops_reg[1].valid, ex_uops_reg[1].bits.ctrl.mem) wire ex_dmem_uop : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _ex_dmem_uop_WIRE : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _ex_dmem_uop_T = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.flush_pipe, UInt<1>(0h0)) node _ex_dmem_uop_T_1 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.flush_pipe, UInt<1>(0h0)) node _ex_dmem_uop_T_2 = or(_ex_dmem_uop_T, _ex_dmem_uop_T_1) wire _ex_dmem_uop_WIRE_1 : UInt<1> connect _ex_dmem_uop_WIRE_1, _ex_dmem_uop_T_2 connect _ex_dmem_uop_WIRE.flush_pipe, _ex_dmem_uop_WIRE_1 node _ex_dmem_uop_T_3 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.mem_size, UInt<1>(0h0)) node _ex_dmem_uop_T_4 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.mem_size, UInt<1>(0h0)) node _ex_dmem_uop_T_5 = or(_ex_dmem_uop_T_3, _ex_dmem_uop_T_4) wire _ex_dmem_uop_WIRE_2 : UInt<2> connect _ex_dmem_uop_WIRE_2, _ex_dmem_uop_T_5 connect _ex_dmem_uop_WIRE.mem_size, _ex_dmem_uop_WIRE_2 wire _ex_dmem_uop_WIRE_3 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _ex_dmem_uop_T_6 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.in3, UInt<1>(0h0)) node _ex_dmem_uop_T_7 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.in3, UInt<1>(0h0)) node _ex_dmem_uop_T_8 = or(_ex_dmem_uop_T_6, _ex_dmem_uop_T_7) wire _ex_dmem_uop_WIRE_4 : UInt<65> connect _ex_dmem_uop_WIRE_4, _ex_dmem_uop_T_8 connect _ex_dmem_uop_WIRE_3.in3, _ex_dmem_uop_WIRE_4 node _ex_dmem_uop_T_9 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.in2, UInt<1>(0h0)) node _ex_dmem_uop_T_10 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.in2, UInt<1>(0h0)) node _ex_dmem_uop_T_11 = or(_ex_dmem_uop_T_9, _ex_dmem_uop_T_10) wire _ex_dmem_uop_WIRE_5 : UInt<65> connect _ex_dmem_uop_WIRE_5, _ex_dmem_uop_T_11 connect _ex_dmem_uop_WIRE_3.in2, _ex_dmem_uop_WIRE_5 node _ex_dmem_uop_T_12 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.in1, UInt<1>(0h0)) node _ex_dmem_uop_T_13 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.in1, UInt<1>(0h0)) node _ex_dmem_uop_T_14 = or(_ex_dmem_uop_T_12, _ex_dmem_uop_T_13) wire _ex_dmem_uop_WIRE_6 : UInt<65> connect _ex_dmem_uop_WIRE_6, _ex_dmem_uop_T_14 connect _ex_dmem_uop_WIRE_3.in1, _ex_dmem_uop_WIRE_6 node _ex_dmem_uop_T_15 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.fmt, UInt<1>(0h0)) node _ex_dmem_uop_T_16 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.fmt, UInt<1>(0h0)) node _ex_dmem_uop_T_17 = or(_ex_dmem_uop_T_15, _ex_dmem_uop_T_16) wire _ex_dmem_uop_WIRE_7 : UInt<2> connect _ex_dmem_uop_WIRE_7, _ex_dmem_uop_T_17 connect _ex_dmem_uop_WIRE_3.fmt, _ex_dmem_uop_WIRE_7 node _ex_dmem_uop_T_18 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.typ, UInt<1>(0h0)) node _ex_dmem_uop_T_19 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.typ, UInt<1>(0h0)) node _ex_dmem_uop_T_20 = or(_ex_dmem_uop_T_18, _ex_dmem_uop_T_19) wire _ex_dmem_uop_WIRE_8 : UInt<2> connect _ex_dmem_uop_WIRE_8, _ex_dmem_uop_T_20 connect _ex_dmem_uop_WIRE_3.typ, _ex_dmem_uop_WIRE_8 node _ex_dmem_uop_T_21 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ex_dmem_uop_T_22 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _ex_dmem_uop_T_23 = or(_ex_dmem_uop_T_21, _ex_dmem_uop_T_22) wire _ex_dmem_uop_WIRE_9 : UInt<2> connect _ex_dmem_uop_WIRE_9, _ex_dmem_uop_T_23 connect _ex_dmem_uop_WIRE_3.fmaCmd, _ex_dmem_uop_WIRE_9 node _ex_dmem_uop_T_24 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.rm, UInt<1>(0h0)) node _ex_dmem_uop_T_25 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.rm, UInt<1>(0h0)) node _ex_dmem_uop_T_26 = or(_ex_dmem_uop_T_24, _ex_dmem_uop_T_25) wire _ex_dmem_uop_WIRE_10 : UInt<3> connect _ex_dmem_uop_WIRE_10, _ex_dmem_uop_T_26 connect _ex_dmem_uop_WIRE_3.rm, _ex_dmem_uop_WIRE_10 node _ex_dmem_uop_T_27 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_28 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_29 = or(_ex_dmem_uop_T_27, _ex_dmem_uop_T_28) wire _ex_dmem_uop_WIRE_11 : UInt<1> connect _ex_dmem_uop_WIRE_11, _ex_dmem_uop_T_29 connect _ex_dmem_uop_WIRE_3.vec, _ex_dmem_uop_WIRE_11 node _ex_dmem_uop_T_30 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.wflags, UInt<1>(0h0)) node _ex_dmem_uop_T_31 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.wflags, UInt<1>(0h0)) node _ex_dmem_uop_T_32 = or(_ex_dmem_uop_T_30, _ex_dmem_uop_T_31) wire _ex_dmem_uop_WIRE_12 : UInt<1> connect _ex_dmem_uop_WIRE_12, _ex_dmem_uop_T_32 connect _ex_dmem_uop_WIRE_3.wflags, _ex_dmem_uop_WIRE_12 node _ex_dmem_uop_T_33 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _ex_dmem_uop_T_34 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _ex_dmem_uop_T_35 = or(_ex_dmem_uop_T_33, _ex_dmem_uop_T_34) wire _ex_dmem_uop_WIRE_13 : UInt<1> connect _ex_dmem_uop_WIRE_13, _ex_dmem_uop_T_35 connect _ex_dmem_uop_WIRE_3.sqrt, _ex_dmem_uop_WIRE_13 node _ex_dmem_uop_T_36 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.div, UInt<1>(0h0)) node _ex_dmem_uop_T_37 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.div, UInt<1>(0h0)) node _ex_dmem_uop_T_38 = or(_ex_dmem_uop_T_36, _ex_dmem_uop_T_37) wire _ex_dmem_uop_WIRE_14 : UInt<1> connect _ex_dmem_uop_WIRE_14, _ex_dmem_uop_T_38 connect _ex_dmem_uop_WIRE_3.div, _ex_dmem_uop_WIRE_14 node _ex_dmem_uop_T_39 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.fma, UInt<1>(0h0)) node _ex_dmem_uop_T_40 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.fma, UInt<1>(0h0)) node _ex_dmem_uop_T_41 = or(_ex_dmem_uop_T_39, _ex_dmem_uop_T_40) wire _ex_dmem_uop_WIRE_15 : UInt<1> connect _ex_dmem_uop_WIRE_15, _ex_dmem_uop_T_41 connect _ex_dmem_uop_WIRE_3.fma, _ex_dmem_uop_WIRE_15 node _ex_dmem_uop_T_42 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ex_dmem_uop_T_43 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _ex_dmem_uop_T_44 = or(_ex_dmem_uop_T_42, _ex_dmem_uop_T_43) wire _ex_dmem_uop_WIRE_16 : UInt<1> connect _ex_dmem_uop_WIRE_16, _ex_dmem_uop_T_44 connect _ex_dmem_uop_WIRE_3.fastpipe, _ex_dmem_uop_WIRE_16 node _ex_dmem_uop_T_45 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.toint, UInt<1>(0h0)) node _ex_dmem_uop_T_46 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.toint, UInt<1>(0h0)) node _ex_dmem_uop_T_47 = or(_ex_dmem_uop_T_45, _ex_dmem_uop_T_46) wire _ex_dmem_uop_WIRE_17 : UInt<1> connect _ex_dmem_uop_WIRE_17, _ex_dmem_uop_T_47 connect _ex_dmem_uop_WIRE_3.toint, _ex_dmem_uop_WIRE_17 node _ex_dmem_uop_T_48 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.fromint, UInt<1>(0h0)) node _ex_dmem_uop_T_49 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.fromint, UInt<1>(0h0)) node _ex_dmem_uop_T_50 = or(_ex_dmem_uop_T_48, _ex_dmem_uop_T_49) wire _ex_dmem_uop_WIRE_18 : UInt<1> connect _ex_dmem_uop_WIRE_18, _ex_dmem_uop_T_50 connect _ex_dmem_uop_WIRE_3.fromint, _ex_dmem_uop_WIRE_18 node _ex_dmem_uop_T_51 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ex_dmem_uop_T_52 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _ex_dmem_uop_T_53 = or(_ex_dmem_uop_T_51, _ex_dmem_uop_T_52) wire _ex_dmem_uop_WIRE_19 : UInt<2> connect _ex_dmem_uop_WIRE_19, _ex_dmem_uop_T_53 connect _ex_dmem_uop_WIRE_3.typeTagOut, _ex_dmem_uop_WIRE_19 node _ex_dmem_uop_T_54 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ex_dmem_uop_T_55 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _ex_dmem_uop_T_56 = or(_ex_dmem_uop_T_54, _ex_dmem_uop_T_55) wire _ex_dmem_uop_WIRE_20 : UInt<2> connect _ex_dmem_uop_WIRE_20, _ex_dmem_uop_T_56 connect _ex_dmem_uop_WIRE_3.typeTagIn, _ex_dmem_uop_WIRE_20 node _ex_dmem_uop_T_57 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.swap23, UInt<1>(0h0)) node _ex_dmem_uop_T_58 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.swap23, UInt<1>(0h0)) node _ex_dmem_uop_T_59 = or(_ex_dmem_uop_T_57, _ex_dmem_uop_T_58) wire _ex_dmem_uop_WIRE_21 : UInt<1> connect _ex_dmem_uop_WIRE_21, _ex_dmem_uop_T_59 connect _ex_dmem_uop_WIRE_3.swap23, _ex_dmem_uop_WIRE_21 node _ex_dmem_uop_T_60 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.swap12, UInt<1>(0h0)) node _ex_dmem_uop_T_61 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.swap12, UInt<1>(0h0)) node _ex_dmem_uop_T_62 = or(_ex_dmem_uop_T_60, _ex_dmem_uop_T_61) wire _ex_dmem_uop_WIRE_22 : UInt<1> connect _ex_dmem_uop_WIRE_22, _ex_dmem_uop_T_62 connect _ex_dmem_uop_WIRE_3.swap12, _ex_dmem_uop_WIRE_22 node _ex_dmem_uop_T_63 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.ren3, UInt<1>(0h0)) node _ex_dmem_uop_T_64 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.ren3, UInt<1>(0h0)) node _ex_dmem_uop_T_65 = or(_ex_dmem_uop_T_63, _ex_dmem_uop_T_64) wire _ex_dmem_uop_WIRE_23 : UInt<1> connect _ex_dmem_uop_WIRE_23, _ex_dmem_uop_T_65 connect _ex_dmem_uop_WIRE_3.ren3, _ex_dmem_uop_WIRE_23 node _ex_dmem_uop_T_66 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.ren2, UInt<1>(0h0)) node _ex_dmem_uop_T_67 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.ren2, UInt<1>(0h0)) node _ex_dmem_uop_T_68 = or(_ex_dmem_uop_T_66, _ex_dmem_uop_T_67) wire _ex_dmem_uop_WIRE_24 : UInt<1> connect _ex_dmem_uop_WIRE_24, _ex_dmem_uop_T_68 connect _ex_dmem_uop_WIRE_3.ren2, _ex_dmem_uop_WIRE_24 node _ex_dmem_uop_T_69 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.ren1, UInt<1>(0h0)) node _ex_dmem_uop_T_70 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.ren1, UInt<1>(0h0)) node _ex_dmem_uop_T_71 = or(_ex_dmem_uop_T_69, _ex_dmem_uop_T_70) wire _ex_dmem_uop_WIRE_25 : UInt<1> connect _ex_dmem_uop_WIRE_25, _ex_dmem_uop_T_71 connect _ex_dmem_uop_WIRE_3.ren1, _ex_dmem_uop_WIRE_25 node _ex_dmem_uop_T_72 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.wen, UInt<1>(0h0)) node _ex_dmem_uop_T_73 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.wen, UInt<1>(0h0)) node _ex_dmem_uop_T_74 = or(_ex_dmem_uop_T_72, _ex_dmem_uop_T_73) wire _ex_dmem_uop_WIRE_26 : UInt<1> connect _ex_dmem_uop_WIRE_26, _ex_dmem_uop_T_74 connect _ex_dmem_uop_WIRE_3.wen, _ex_dmem_uop_WIRE_26 node _ex_dmem_uop_T_75 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fdivin.ldst, UInt<1>(0h0)) node _ex_dmem_uop_T_76 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fdivin.ldst, UInt<1>(0h0)) node _ex_dmem_uop_T_77 = or(_ex_dmem_uop_T_75, _ex_dmem_uop_T_76) wire _ex_dmem_uop_WIRE_27 : UInt<1> connect _ex_dmem_uop_WIRE_27, _ex_dmem_uop_T_77 connect _ex_dmem_uop_WIRE_3.ldst, _ex_dmem_uop_WIRE_27 connect _ex_dmem_uop_WIRE.fdivin, _ex_dmem_uop_WIRE_3 node _ex_dmem_uop_T_78 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fexc, UInt<1>(0h0)) node _ex_dmem_uop_T_79 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fexc, UInt<1>(0h0)) node _ex_dmem_uop_T_80 = or(_ex_dmem_uop_T_78, _ex_dmem_uop_T_79) wire _ex_dmem_uop_WIRE_28 : UInt<5> connect _ex_dmem_uop_WIRE_28, _ex_dmem_uop_T_80 connect _ex_dmem_uop_WIRE.fexc, _ex_dmem_uop_WIRE_28 node _ex_dmem_uop_T_81 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fra3, UInt<1>(0h0)) node _ex_dmem_uop_T_82 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fra3, UInt<1>(0h0)) node _ex_dmem_uop_T_83 = or(_ex_dmem_uop_T_81, _ex_dmem_uop_T_82) wire _ex_dmem_uop_WIRE_29 : UInt<5> connect _ex_dmem_uop_WIRE_29, _ex_dmem_uop_T_83 connect _ex_dmem_uop_WIRE.fra3, _ex_dmem_uop_WIRE_29 node _ex_dmem_uop_T_84 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fra2, UInt<1>(0h0)) node _ex_dmem_uop_T_85 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fra2, UInt<1>(0h0)) node _ex_dmem_uop_T_86 = or(_ex_dmem_uop_T_84, _ex_dmem_uop_T_85) wire _ex_dmem_uop_WIRE_30 : UInt<5> connect _ex_dmem_uop_WIRE_30, _ex_dmem_uop_T_86 connect _ex_dmem_uop_WIRE.fra2, _ex_dmem_uop_WIRE_30 node _ex_dmem_uop_T_87 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fra1, UInt<1>(0h0)) node _ex_dmem_uop_T_88 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fra1, UInt<1>(0h0)) node _ex_dmem_uop_T_89 = or(_ex_dmem_uop_T_87, _ex_dmem_uop_T_88) wire _ex_dmem_uop_WIRE_31 : UInt<5> connect _ex_dmem_uop_WIRE_31, _ex_dmem_uop_T_89 connect _ex_dmem_uop_WIRE.fra1, _ex_dmem_uop_WIRE_31 wire _ex_dmem_uop_WIRE_32 : { valid : UInt<1>, bits : UInt<64>} node _ex_dmem_uop_T_90 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.wdata.bits, UInt<1>(0h0)) node _ex_dmem_uop_T_91 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.wdata.bits, UInt<1>(0h0)) node _ex_dmem_uop_T_92 = or(_ex_dmem_uop_T_90, _ex_dmem_uop_T_91) wire _ex_dmem_uop_WIRE_33 : UInt<64> connect _ex_dmem_uop_WIRE_33, _ex_dmem_uop_T_92 connect _ex_dmem_uop_WIRE_32.bits, _ex_dmem_uop_WIRE_33 node _ex_dmem_uop_T_93 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.wdata.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_94 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.wdata.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_95 = or(_ex_dmem_uop_T_93, _ex_dmem_uop_T_94) wire _ex_dmem_uop_WIRE_34 : UInt<1> connect _ex_dmem_uop_WIRE_34, _ex_dmem_uop_T_95 connect _ex_dmem_uop_WIRE_32.valid, _ex_dmem_uop_WIRE_34 connect _ex_dmem_uop_WIRE.wdata, _ex_dmem_uop_WIRE_32 node _ex_dmem_uop_T_96 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _ex_dmem_uop_T_97 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _ex_dmem_uop_T_98 = or(_ex_dmem_uop_T_96, _ex_dmem_uop_T_97) wire _ex_dmem_uop_WIRE_35 : UInt<1> connect _ex_dmem_uop_WIRE_35, _ex_dmem_uop_T_98 connect _ex_dmem_uop_WIRE.uses_latealu, _ex_dmem_uop_WIRE_35 node _ex_dmem_uop_T_99 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _ex_dmem_uop_T_100 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _ex_dmem_uop_T_101 = or(_ex_dmem_uop_T_99, _ex_dmem_uop_T_100) wire _ex_dmem_uop_WIRE_36 : UInt<1> connect _ex_dmem_uop_WIRE_36, _ex_dmem_uop_T_101 connect _ex_dmem_uop_WIRE.uses_memalu, _ex_dmem_uop_WIRE_36 node _ex_dmem_uop_T_102 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.rs3_data, UInt<1>(0h0)) node _ex_dmem_uop_T_103 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.rs3_data, UInt<1>(0h0)) node _ex_dmem_uop_T_104 = or(_ex_dmem_uop_T_102, _ex_dmem_uop_T_103) wire _ex_dmem_uop_WIRE_37 : UInt<64> connect _ex_dmem_uop_WIRE_37, _ex_dmem_uop_T_104 connect _ex_dmem_uop_WIRE.rs3_data, _ex_dmem_uop_WIRE_37 node _ex_dmem_uop_T_105 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.rs2_data, UInt<1>(0h0)) node _ex_dmem_uop_T_106 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.rs2_data, UInt<1>(0h0)) node _ex_dmem_uop_T_107 = or(_ex_dmem_uop_T_105, _ex_dmem_uop_T_106) wire _ex_dmem_uop_WIRE_38 : UInt<64> connect _ex_dmem_uop_WIRE_38, _ex_dmem_uop_T_107 connect _ex_dmem_uop_WIRE.rs2_data, _ex_dmem_uop_WIRE_38 node _ex_dmem_uop_T_108 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.rs1_data, UInt<1>(0h0)) node _ex_dmem_uop_T_109 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.rs1_data, UInt<1>(0h0)) node _ex_dmem_uop_T_110 = or(_ex_dmem_uop_T_108, _ex_dmem_uop_T_109) wire _ex_dmem_uop_WIRE_39 : UInt<64> connect _ex_dmem_uop_WIRE_39, _ex_dmem_uop_T_110 connect _ex_dmem_uop_WIRE.rs1_data, _ex_dmem_uop_WIRE_39 node _ex_dmem_uop_T_111 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.needs_replay, UInt<1>(0h0)) node _ex_dmem_uop_T_112 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.needs_replay, UInt<1>(0h0)) node _ex_dmem_uop_T_113 = or(_ex_dmem_uop_T_111, _ex_dmem_uop_T_112) wire _ex_dmem_uop_WIRE_40 : UInt<1> connect _ex_dmem_uop_WIRE_40, _ex_dmem_uop_T_113 connect _ex_dmem_uop_WIRE.needs_replay, _ex_dmem_uop_WIRE_40 node _ex_dmem_uop_T_114 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.xcpt_cause, UInt<1>(0h0)) node _ex_dmem_uop_T_115 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.xcpt_cause, UInt<1>(0h0)) node _ex_dmem_uop_T_116 = or(_ex_dmem_uop_T_114, _ex_dmem_uop_T_115) wire _ex_dmem_uop_WIRE_41 : UInt<64> connect _ex_dmem_uop_WIRE_41, _ex_dmem_uop_T_116 connect _ex_dmem_uop_WIRE.xcpt_cause, _ex_dmem_uop_WIRE_41 node _ex_dmem_uop_T_117 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _ex_dmem_uop_T_118 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.xcpt, UInt<1>(0h0)) node _ex_dmem_uop_T_119 = or(_ex_dmem_uop_T_117, _ex_dmem_uop_T_118) wire _ex_dmem_uop_WIRE_42 : UInt<1> connect _ex_dmem_uop_WIRE_42, _ex_dmem_uop_T_119 connect _ex_dmem_uop_WIRE.xcpt, _ex_dmem_uop_WIRE_42 node _ex_dmem_uop_T_120 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.taken, UInt<1>(0h0)) node _ex_dmem_uop_T_121 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.taken, UInt<1>(0h0)) node _ex_dmem_uop_T_122 = or(_ex_dmem_uop_T_120, _ex_dmem_uop_T_121) wire _ex_dmem_uop_WIRE_43 : UInt<1> connect _ex_dmem_uop_WIRE_43, _ex_dmem_uop_T_122 connect _ex_dmem_uop_WIRE.taken, _ex_dmem_uop_WIRE_43 node _ex_dmem_uop_T_123 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ras_head, UInt<1>(0h0)) node _ex_dmem_uop_T_124 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ras_head, UInt<1>(0h0)) node _ex_dmem_uop_T_125 = or(_ex_dmem_uop_T_123, _ex_dmem_uop_T_124) wire _ex_dmem_uop_WIRE_44 : UInt<3> connect _ex_dmem_uop_WIRE_44, _ex_dmem_uop_T_125 connect _ex_dmem_uop_WIRE.ras_head, _ex_dmem_uop_WIRE_44 wire _ex_dmem_uop_WIRE_45 : { valid : UInt<1>, bits : UInt<40>} node _ex_dmem_uop_T_126 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.next_pc.bits, UInt<1>(0h0)) node _ex_dmem_uop_T_127 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.next_pc.bits, UInt<1>(0h0)) node _ex_dmem_uop_T_128 = or(_ex_dmem_uop_T_126, _ex_dmem_uop_T_127) wire _ex_dmem_uop_WIRE_46 : UInt<40> connect _ex_dmem_uop_WIRE_46, _ex_dmem_uop_T_128 connect _ex_dmem_uop_WIRE_45.bits, _ex_dmem_uop_WIRE_46 node _ex_dmem_uop_T_129 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.next_pc.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_130 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.next_pc.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_131 = or(_ex_dmem_uop_T_129, _ex_dmem_uop_T_130) wire _ex_dmem_uop_WIRE_47 : UInt<1> connect _ex_dmem_uop_WIRE_47, _ex_dmem_uop_T_131 connect _ex_dmem_uop_WIRE_45.valid, _ex_dmem_uop_WIRE_47 connect _ex_dmem_uop_WIRE.next_pc, _ex_dmem_uop_WIRE_45 node _ex_dmem_uop_T_132 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.sfb_shadow, UInt<1>(0h0)) node _ex_dmem_uop_T_133 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _ex_dmem_uop_T_134 = or(_ex_dmem_uop_T_132, _ex_dmem_uop_T_133) wire _ex_dmem_uop_WIRE_48 : UInt<1> connect _ex_dmem_uop_WIRE_48, _ex_dmem_uop_T_134 connect _ex_dmem_uop_WIRE.sfb_shadow, _ex_dmem_uop_WIRE_48 node _ex_dmem_uop_T_135 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.sfb_br, UInt<1>(0h0)) node _ex_dmem_uop_T_136 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.sfb_br, UInt<1>(0h0)) node _ex_dmem_uop_T_137 = or(_ex_dmem_uop_T_135, _ex_dmem_uop_T_136) wire _ex_dmem_uop_WIRE_49 : UInt<1> connect _ex_dmem_uop_WIRE_49, _ex_dmem_uop_T_137 connect _ex_dmem_uop_WIRE.sfb_br, _ex_dmem_uop_WIRE_49 wire _ex_dmem_uop_WIRE_50 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _ex_dmem_uop_WIRE_51 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _ex_dmem_uop_WIRE_52 : { history : UInt<8>, value : UInt<2>} node _ex_dmem_uop_T_138 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ex_dmem_uop_T_139 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _ex_dmem_uop_T_140 = or(_ex_dmem_uop_T_138, _ex_dmem_uop_T_139) wire _ex_dmem_uop_WIRE_53 : UInt<2> connect _ex_dmem_uop_WIRE_53, _ex_dmem_uop_T_140 connect _ex_dmem_uop_WIRE_52.value, _ex_dmem_uop_WIRE_53 node _ex_dmem_uop_T_141 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ex_dmem_uop_T_142 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _ex_dmem_uop_T_143 = or(_ex_dmem_uop_T_141, _ex_dmem_uop_T_142) wire _ex_dmem_uop_WIRE_54 : UInt<8> connect _ex_dmem_uop_WIRE_54, _ex_dmem_uop_T_143 connect _ex_dmem_uop_WIRE_52.history, _ex_dmem_uop_WIRE_54 connect _ex_dmem_uop_WIRE_51.bht, _ex_dmem_uop_WIRE_52 node _ex_dmem_uop_T_144 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ex_dmem_uop_T_145 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _ex_dmem_uop_T_146 = or(_ex_dmem_uop_T_144, _ex_dmem_uop_T_145) wire _ex_dmem_uop_WIRE_55 : UInt<6> connect _ex_dmem_uop_WIRE_55, _ex_dmem_uop_T_146 connect _ex_dmem_uop_WIRE_51.entry, _ex_dmem_uop_WIRE_55 node _ex_dmem_uop_T_147 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ex_dmem_uop_T_148 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _ex_dmem_uop_T_149 = or(_ex_dmem_uop_T_147, _ex_dmem_uop_T_148) wire _ex_dmem_uop_WIRE_56 : UInt<39> connect _ex_dmem_uop_WIRE_56, _ex_dmem_uop_T_149 connect _ex_dmem_uop_WIRE_51.target, _ex_dmem_uop_WIRE_56 node _ex_dmem_uop_T_150 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ex_dmem_uop_T_151 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _ex_dmem_uop_T_152 = or(_ex_dmem_uop_T_150, _ex_dmem_uop_T_151) wire _ex_dmem_uop_WIRE_57 : UInt<2> connect _ex_dmem_uop_WIRE_57, _ex_dmem_uop_T_152 connect _ex_dmem_uop_WIRE_51.bridx, _ex_dmem_uop_WIRE_57 node _ex_dmem_uop_T_153 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ex_dmem_uop_T_154 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _ex_dmem_uop_T_155 = or(_ex_dmem_uop_T_153, _ex_dmem_uop_T_154) wire _ex_dmem_uop_WIRE_58 : UInt<4> connect _ex_dmem_uop_WIRE_58, _ex_dmem_uop_T_155 connect _ex_dmem_uop_WIRE_51.mask, _ex_dmem_uop_WIRE_58 node _ex_dmem_uop_T_156 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ex_dmem_uop_T_157 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _ex_dmem_uop_T_158 = or(_ex_dmem_uop_T_156, _ex_dmem_uop_T_157) wire _ex_dmem_uop_WIRE_59 : UInt<1> connect _ex_dmem_uop_WIRE_59, _ex_dmem_uop_T_158 connect _ex_dmem_uop_WIRE_51.taken, _ex_dmem_uop_WIRE_59 node _ex_dmem_uop_T_159 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ex_dmem_uop_T_160 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _ex_dmem_uop_T_161 = or(_ex_dmem_uop_T_159, _ex_dmem_uop_T_160) wire _ex_dmem_uop_WIRE_60 : UInt<2> connect _ex_dmem_uop_WIRE_60, _ex_dmem_uop_T_161 connect _ex_dmem_uop_WIRE_51.cfiType, _ex_dmem_uop_WIRE_60 connect _ex_dmem_uop_WIRE_50.bits, _ex_dmem_uop_WIRE_51 node _ex_dmem_uop_T_162 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.btb_resp.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_163 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.btb_resp.valid, UInt<1>(0h0)) node _ex_dmem_uop_T_164 = or(_ex_dmem_uop_T_162, _ex_dmem_uop_T_163) wire _ex_dmem_uop_WIRE_61 : UInt<1> connect _ex_dmem_uop_WIRE_61, _ex_dmem_uop_T_164 connect _ex_dmem_uop_WIRE_50.valid, _ex_dmem_uop_WIRE_61 connect _ex_dmem_uop_WIRE.btb_resp, _ex_dmem_uop_WIRE_50 node _ex_dmem_uop_T_165 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.sets_vcfg, UInt<1>(0h0)) node _ex_dmem_uop_T_166 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.sets_vcfg, UInt<1>(0h0)) node _ex_dmem_uop_T_167 = or(_ex_dmem_uop_T_165, _ex_dmem_uop_T_166) wire _ex_dmem_uop_WIRE_62 : UInt<1> connect _ex_dmem_uop_WIRE_62, _ex_dmem_uop_T_167 connect _ex_dmem_uop_WIRE.sets_vcfg, _ex_dmem_uop_WIRE_62 node _ex_dmem_uop_T_168 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.rvc, UInt<1>(0h0)) node _ex_dmem_uop_T_169 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.rvc, UInt<1>(0h0)) node _ex_dmem_uop_T_170 = or(_ex_dmem_uop_T_168, _ex_dmem_uop_T_169) wire _ex_dmem_uop_WIRE_63 : UInt<1> connect _ex_dmem_uop_WIRE_63, _ex_dmem_uop_T_170 connect _ex_dmem_uop_WIRE.rvc, _ex_dmem_uop_WIRE_63 wire _ex_dmem_uop_WIRE_64 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _ex_dmem_uop_T_171 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_172 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_173 = or(_ex_dmem_uop_T_171, _ex_dmem_uop_T_172) wire _ex_dmem_uop_WIRE_65 : UInt<1> connect _ex_dmem_uop_WIRE_65, _ex_dmem_uop_T_173 connect _ex_dmem_uop_WIRE_64.vec, _ex_dmem_uop_WIRE_65 node _ex_dmem_uop_T_174 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ex_dmem_uop_T_175 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _ex_dmem_uop_T_176 = or(_ex_dmem_uop_T_174, _ex_dmem_uop_T_175) wire _ex_dmem_uop_WIRE_66 : UInt<1> connect _ex_dmem_uop_WIRE_66, _ex_dmem_uop_T_176 connect _ex_dmem_uop_WIRE_64.wflags, _ex_dmem_uop_WIRE_66 node _ex_dmem_uop_T_177 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ex_dmem_uop_T_178 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _ex_dmem_uop_T_179 = or(_ex_dmem_uop_T_177, _ex_dmem_uop_T_178) wire _ex_dmem_uop_WIRE_67 : UInt<1> connect _ex_dmem_uop_WIRE_67, _ex_dmem_uop_T_179 connect _ex_dmem_uop_WIRE_64.sqrt, _ex_dmem_uop_WIRE_67 node _ex_dmem_uop_T_180 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _ex_dmem_uop_T_181 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _ex_dmem_uop_T_182 = or(_ex_dmem_uop_T_180, _ex_dmem_uop_T_181) wire _ex_dmem_uop_WIRE_68 : UInt<1> connect _ex_dmem_uop_WIRE_68, _ex_dmem_uop_T_182 connect _ex_dmem_uop_WIRE_64.div, _ex_dmem_uop_WIRE_68 node _ex_dmem_uop_T_183 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ex_dmem_uop_T_184 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _ex_dmem_uop_T_185 = or(_ex_dmem_uop_T_183, _ex_dmem_uop_T_184) wire _ex_dmem_uop_WIRE_69 : UInt<1> connect _ex_dmem_uop_WIRE_69, _ex_dmem_uop_T_185 connect _ex_dmem_uop_WIRE_64.fma, _ex_dmem_uop_WIRE_69 node _ex_dmem_uop_T_186 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ex_dmem_uop_T_187 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _ex_dmem_uop_T_188 = or(_ex_dmem_uop_T_186, _ex_dmem_uop_T_187) wire _ex_dmem_uop_WIRE_70 : UInt<1> connect _ex_dmem_uop_WIRE_70, _ex_dmem_uop_T_188 connect _ex_dmem_uop_WIRE_64.fastpipe, _ex_dmem_uop_WIRE_70 node _ex_dmem_uop_T_189 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ex_dmem_uop_T_190 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _ex_dmem_uop_T_191 = or(_ex_dmem_uop_T_189, _ex_dmem_uop_T_190) wire _ex_dmem_uop_WIRE_71 : UInt<1> connect _ex_dmem_uop_WIRE_71, _ex_dmem_uop_T_191 connect _ex_dmem_uop_WIRE_64.toint, _ex_dmem_uop_WIRE_71 node _ex_dmem_uop_T_192 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ex_dmem_uop_T_193 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _ex_dmem_uop_T_194 = or(_ex_dmem_uop_T_192, _ex_dmem_uop_T_193) wire _ex_dmem_uop_WIRE_72 : UInt<1> connect _ex_dmem_uop_WIRE_72, _ex_dmem_uop_T_194 connect _ex_dmem_uop_WIRE_64.fromint, _ex_dmem_uop_WIRE_72 node _ex_dmem_uop_T_195 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ex_dmem_uop_T_196 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _ex_dmem_uop_T_197 = or(_ex_dmem_uop_T_195, _ex_dmem_uop_T_196) wire _ex_dmem_uop_WIRE_73 : UInt<2> connect _ex_dmem_uop_WIRE_73, _ex_dmem_uop_T_197 connect _ex_dmem_uop_WIRE_64.typeTagOut, _ex_dmem_uop_WIRE_73 node _ex_dmem_uop_T_198 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ex_dmem_uop_T_199 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _ex_dmem_uop_T_200 = or(_ex_dmem_uop_T_198, _ex_dmem_uop_T_199) wire _ex_dmem_uop_WIRE_74 : UInt<2> connect _ex_dmem_uop_WIRE_74, _ex_dmem_uop_T_200 connect _ex_dmem_uop_WIRE_64.typeTagIn, _ex_dmem_uop_WIRE_74 node _ex_dmem_uop_T_201 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ex_dmem_uop_T_202 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _ex_dmem_uop_T_203 = or(_ex_dmem_uop_T_201, _ex_dmem_uop_T_202) wire _ex_dmem_uop_WIRE_75 : UInt<1> connect _ex_dmem_uop_WIRE_75, _ex_dmem_uop_T_203 connect _ex_dmem_uop_WIRE_64.swap23, _ex_dmem_uop_WIRE_75 node _ex_dmem_uop_T_204 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ex_dmem_uop_T_205 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _ex_dmem_uop_T_206 = or(_ex_dmem_uop_T_204, _ex_dmem_uop_T_205) wire _ex_dmem_uop_WIRE_76 : UInt<1> connect _ex_dmem_uop_WIRE_76, _ex_dmem_uop_T_206 connect _ex_dmem_uop_WIRE_64.swap12, _ex_dmem_uop_WIRE_76 node _ex_dmem_uop_T_207 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ex_dmem_uop_T_208 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _ex_dmem_uop_T_209 = or(_ex_dmem_uop_T_207, _ex_dmem_uop_T_208) wire _ex_dmem_uop_WIRE_77 : UInt<1> connect _ex_dmem_uop_WIRE_77, _ex_dmem_uop_T_209 connect _ex_dmem_uop_WIRE_64.ren3, _ex_dmem_uop_WIRE_77 node _ex_dmem_uop_T_210 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ex_dmem_uop_T_211 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _ex_dmem_uop_T_212 = or(_ex_dmem_uop_T_210, _ex_dmem_uop_T_211) wire _ex_dmem_uop_WIRE_78 : UInt<1> connect _ex_dmem_uop_WIRE_78, _ex_dmem_uop_T_212 connect _ex_dmem_uop_WIRE_64.ren2, _ex_dmem_uop_WIRE_78 node _ex_dmem_uop_T_213 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ex_dmem_uop_T_214 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _ex_dmem_uop_T_215 = or(_ex_dmem_uop_T_213, _ex_dmem_uop_T_214) wire _ex_dmem_uop_WIRE_79 : UInt<1> connect _ex_dmem_uop_WIRE_79, _ex_dmem_uop_T_215 connect _ex_dmem_uop_WIRE_64.ren1, _ex_dmem_uop_WIRE_79 node _ex_dmem_uop_T_216 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ex_dmem_uop_T_217 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _ex_dmem_uop_T_218 = or(_ex_dmem_uop_T_216, _ex_dmem_uop_T_217) wire _ex_dmem_uop_WIRE_80 : UInt<1> connect _ex_dmem_uop_WIRE_80, _ex_dmem_uop_T_218 connect _ex_dmem_uop_WIRE_64.wen, _ex_dmem_uop_WIRE_80 node _ex_dmem_uop_T_219 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ex_dmem_uop_T_220 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _ex_dmem_uop_T_221 = or(_ex_dmem_uop_T_219, _ex_dmem_uop_T_220) wire _ex_dmem_uop_WIRE_81 : UInt<1> connect _ex_dmem_uop_WIRE_81, _ex_dmem_uop_T_221 connect _ex_dmem_uop_WIRE_64.ldst, _ex_dmem_uop_WIRE_81 connect _ex_dmem_uop_WIRE.fp_ctrl, _ex_dmem_uop_WIRE_64 wire _ex_dmem_uop_WIRE_82 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _ex_dmem_uop_T_222 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_223 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _ex_dmem_uop_T_224 = or(_ex_dmem_uop_T_222, _ex_dmem_uop_T_223) wire _ex_dmem_uop_WIRE_83 : UInt<1> connect _ex_dmem_uop_WIRE_83, _ex_dmem_uop_T_224 connect _ex_dmem_uop_WIRE_82.vec, _ex_dmem_uop_WIRE_83 node _ex_dmem_uop_T_225 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.dp, UInt<1>(0h0)) node _ex_dmem_uop_T_226 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.dp, UInt<1>(0h0)) node _ex_dmem_uop_T_227 = or(_ex_dmem_uop_T_225, _ex_dmem_uop_T_226) wire _ex_dmem_uop_WIRE_84 : UInt<1> connect _ex_dmem_uop_WIRE_84, _ex_dmem_uop_T_227 connect _ex_dmem_uop_WIRE_82.dp, _ex_dmem_uop_WIRE_84 node _ex_dmem_uop_T_228 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.amo, UInt<1>(0h0)) node _ex_dmem_uop_T_229 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.amo, UInt<1>(0h0)) node _ex_dmem_uop_T_230 = or(_ex_dmem_uop_T_228, _ex_dmem_uop_T_229) wire _ex_dmem_uop_WIRE_85 : UInt<1> connect _ex_dmem_uop_WIRE_85, _ex_dmem_uop_T_230 connect _ex_dmem_uop_WIRE_82.amo, _ex_dmem_uop_WIRE_85 node _ex_dmem_uop_T_231 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.fence, UInt<1>(0h0)) node _ex_dmem_uop_T_232 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.fence, UInt<1>(0h0)) node _ex_dmem_uop_T_233 = or(_ex_dmem_uop_T_231, _ex_dmem_uop_T_232) wire _ex_dmem_uop_WIRE_86 : UInt<1> connect _ex_dmem_uop_WIRE_86, _ex_dmem_uop_T_233 connect _ex_dmem_uop_WIRE_82.fence, _ex_dmem_uop_WIRE_86 node _ex_dmem_uop_T_234 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _ex_dmem_uop_T_235 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _ex_dmem_uop_T_236 = or(_ex_dmem_uop_T_234, _ex_dmem_uop_T_235) wire _ex_dmem_uop_WIRE_87 : UInt<1> connect _ex_dmem_uop_WIRE_87, _ex_dmem_uop_T_236 connect _ex_dmem_uop_WIRE_82.fence_i, _ex_dmem_uop_WIRE_87 node _ex_dmem_uop_T_237 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.csr, UInt<1>(0h0)) node _ex_dmem_uop_T_238 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.csr, UInt<1>(0h0)) node _ex_dmem_uop_T_239 = or(_ex_dmem_uop_T_237, _ex_dmem_uop_T_238) wire _ex_dmem_uop_WIRE_88 : UInt<3> connect _ex_dmem_uop_WIRE_88, _ex_dmem_uop_T_239 connect _ex_dmem_uop_WIRE_82.csr, _ex_dmem_uop_WIRE_88 node _ex_dmem_uop_T_240 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.wxd, UInt<1>(0h0)) node _ex_dmem_uop_T_241 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.wxd, UInt<1>(0h0)) node _ex_dmem_uop_T_242 = or(_ex_dmem_uop_T_240, _ex_dmem_uop_T_241) wire _ex_dmem_uop_WIRE_89 : UInt<1> connect _ex_dmem_uop_WIRE_89, _ex_dmem_uop_T_242 connect _ex_dmem_uop_WIRE_82.wxd, _ex_dmem_uop_WIRE_89 node _ex_dmem_uop_T_243 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _ex_dmem_uop_T_244 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _ex_dmem_uop_T_245 = or(_ex_dmem_uop_T_243, _ex_dmem_uop_T_244) wire _ex_dmem_uop_WIRE_90 : UInt<1> connect _ex_dmem_uop_WIRE_90, _ex_dmem_uop_T_245 connect _ex_dmem_uop_WIRE_82.div, _ex_dmem_uop_WIRE_90 node _ex_dmem_uop_T_246 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _ex_dmem_uop_T_247 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _ex_dmem_uop_T_248 = or(_ex_dmem_uop_T_246, _ex_dmem_uop_T_247) wire _ex_dmem_uop_WIRE_91 : UInt<1> connect _ex_dmem_uop_WIRE_91, _ex_dmem_uop_T_248 connect _ex_dmem_uop_WIRE_82.mul, _ex_dmem_uop_WIRE_91 node _ex_dmem_uop_T_249 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.wfd, UInt<1>(0h0)) node _ex_dmem_uop_T_250 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.wfd, UInt<1>(0h0)) node _ex_dmem_uop_T_251 = or(_ex_dmem_uop_T_249, _ex_dmem_uop_T_250) wire _ex_dmem_uop_WIRE_92 : UInt<1> connect _ex_dmem_uop_WIRE_92, _ex_dmem_uop_T_251 connect _ex_dmem_uop_WIRE_82.wfd, _ex_dmem_uop_WIRE_92 node _ex_dmem_uop_T_252 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _ex_dmem_uop_T_253 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _ex_dmem_uop_T_254 = or(_ex_dmem_uop_T_252, _ex_dmem_uop_T_253) wire _ex_dmem_uop_WIRE_93 : UInt<1> connect _ex_dmem_uop_WIRE_93, _ex_dmem_uop_T_254 connect _ex_dmem_uop_WIRE_82.rfs3, _ex_dmem_uop_WIRE_93 node _ex_dmem_uop_T_255 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _ex_dmem_uop_T_256 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _ex_dmem_uop_T_257 = or(_ex_dmem_uop_T_255, _ex_dmem_uop_T_256) wire _ex_dmem_uop_WIRE_94 : UInt<1> connect _ex_dmem_uop_WIRE_94, _ex_dmem_uop_T_257 connect _ex_dmem_uop_WIRE_82.rfs2, _ex_dmem_uop_WIRE_94 node _ex_dmem_uop_T_258 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _ex_dmem_uop_T_259 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _ex_dmem_uop_T_260 = or(_ex_dmem_uop_T_258, _ex_dmem_uop_T_259) wire _ex_dmem_uop_WIRE_95 : UInt<1> connect _ex_dmem_uop_WIRE_95, _ex_dmem_uop_T_260 connect _ex_dmem_uop_WIRE_82.rfs1, _ex_dmem_uop_WIRE_95 node _ex_dmem_uop_T_261 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ex_dmem_uop_T_262 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _ex_dmem_uop_T_263 = or(_ex_dmem_uop_T_261, _ex_dmem_uop_T_262) wire _ex_dmem_uop_WIRE_96 : UInt<5> connect _ex_dmem_uop_WIRE_96, _ex_dmem_uop_T_263 connect _ex_dmem_uop_WIRE_82.mem_cmd, _ex_dmem_uop_WIRE_96 node _ex_dmem_uop_T_264 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _ex_dmem_uop_T_265 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _ex_dmem_uop_T_266 = or(_ex_dmem_uop_T_264, _ex_dmem_uop_T_265) wire _ex_dmem_uop_WIRE_97 : UInt<1> connect _ex_dmem_uop_WIRE_97, _ex_dmem_uop_T_266 connect _ex_dmem_uop_WIRE_82.mem, _ex_dmem_uop_WIRE_97 node _ex_dmem_uop_T_267 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ex_dmem_uop_T_268 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _ex_dmem_uop_T_269 = or(_ex_dmem_uop_T_267, _ex_dmem_uop_T_268) wire _ex_dmem_uop_WIRE_98 : UInt<5> connect _ex_dmem_uop_WIRE_98, _ex_dmem_uop_T_269 connect _ex_dmem_uop_WIRE_82.alu_fn, _ex_dmem_uop_WIRE_98 node _ex_dmem_uop_T_270 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ex_dmem_uop_T_271 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _ex_dmem_uop_T_272 = or(_ex_dmem_uop_T_270, _ex_dmem_uop_T_271) wire _ex_dmem_uop_WIRE_99 : UInt<1> connect _ex_dmem_uop_WIRE_99, _ex_dmem_uop_T_272 connect _ex_dmem_uop_WIRE_82.alu_dw, _ex_dmem_uop_WIRE_99 node _ex_dmem_uop_T_273 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ex_dmem_uop_T_274 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _ex_dmem_uop_T_275 = or(_ex_dmem_uop_T_273, _ex_dmem_uop_T_274) wire _ex_dmem_uop_WIRE_100 : UInt<3> connect _ex_dmem_uop_WIRE_100, _ex_dmem_uop_T_275 connect _ex_dmem_uop_WIRE_82.sel_imm, _ex_dmem_uop_WIRE_100 node _ex_dmem_uop_T_276 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ex_dmem_uop_T_277 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _ex_dmem_uop_T_278 = or(_ex_dmem_uop_T_276, _ex_dmem_uop_T_277) wire _ex_dmem_uop_WIRE_101 : UInt<2> connect _ex_dmem_uop_WIRE_101, _ex_dmem_uop_T_278 connect _ex_dmem_uop_WIRE_82.sel_alu1, _ex_dmem_uop_WIRE_101 node _ex_dmem_uop_T_279 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ex_dmem_uop_T_280 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _ex_dmem_uop_T_281 = or(_ex_dmem_uop_T_279, _ex_dmem_uop_T_280) wire _ex_dmem_uop_WIRE_102 : UInt<3> connect _ex_dmem_uop_WIRE_102, _ex_dmem_uop_T_281 connect _ex_dmem_uop_WIRE_82.sel_alu2, _ex_dmem_uop_WIRE_102 node _ex_dmem_uop_T_282 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _ex_dmem_uop_T_283 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _ex_dmem_uop_T_284 = or(_ex_dmem_uop_T_282, _ex_dmem_uop_T_283) wire _ex_dmem_uop_WIRE_103 : UInt<1> connect _ex_dmem_uop_WIRE_103, _ex_dmem_uop_T_284 connect _ex_dmem_uop_WIRE_82.rxs1, _ex_dmem_uop_WIRE_103 node _ex_dmem_uop_T_285 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _ex_dmem_uop_T_286 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _ex_dmem_uop_T_287 = or(_ex_dmem_uop_T_285, _ex_dmem_uop_T_286) wire _ex_dmem_uop_WIRE_104 : UInt<1> connect _ex_dmem_uop_WIRE_104, _ex_dmem_uop_T_287 connect _ex_dmem_uop_WIRE_82.rxs2, _ex_dmem_uop_WIRE_104 node _ex_dmem_uop_T_288 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_dmem_uop_T_289 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_dmem_uop_T_290 = or(_ex_dmem_uop_T_288, _ex_dmem_uop_T_289) wire _ex_dmem_uop_WIRE_105 : UInt<1> connect _ex_dmem_uop_WIRE_105, _ex_dmem_uop_T_290 connect _ex_dmem_uop_WIRE_82.jalr, _ex_dmem_uop_WIRE_105 node _ex_dmem_uop_T_291 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.jal, UInt<1>(0h0)) node _ex_dmem_uop_T_292 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.jal, UInt<1>(0h0)) node _ex_dmem_uop_T_293 = or(_ex_dmem_uop_T_291, _ex_dmem_uop_T_292) wire _ex_dmem_uop_WIRE_106 : UInt<1> connect _ex_dmem_uop_WIRE_106, _ex_dmem_uop_T_293 connect _ex_dmem_uop_WIRE_82.jal, _ex_dmem_uop_WIRE_106 node _ex_dmem_uop_T_294 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.branch, UInt<1>(0h0)) node _ex_dmem_uop_T_295 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.branch, UInt<1>(0h0)) node _ex_dmem_uop_T_296 = or(_ex_dmem_uop_T_294, _ex_dmem_uop_T_295) wire _ex_dmem_uop_WIRE_107 : UInt<1> connect _ex_dmem_uop_WIRE_107, _ex_dmem_uop_T_296 connect _ex_dmem_uop_WIRE_82.branch, _ex_dmem_uop_WIRE_107 node _ex_dmem_uop_T_297 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_dmem_uop_T_298 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_dmem_uop_T_299 = or(_ex_dmem_uop_T_297, _ex_dmem_uop_T_298) wire _ex_dmem_uop_WIRE_108 : UInt<1> connect _ex_dmem_uop_WIRE_108, _ex_dmem_uop_T_299 connect _ex_dmem_uop_WIRE_82.rocc, _ex_dmem_uop_WIRE_108 node _ex_dmem_uop_T_300 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _ex_dmem_uop_T_301 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _ex_dmem_uop_T_302 = or(_ex_dmem_uop_T_300, _ex_dmem_uop_T_301) wire _ex_dmem_uop_WIRE_109 : UInt<1> connect _ex_dmem_uop_WIRE_109, _ex_dmem_uop_T_302 connect _ex_dmem_uop_WIRE_82.fp, _ex_dmem_uop_WIRE_109 node _ex_dmem_uop_T_303 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.ctrl.legal, UInt<1>(0h0)) node _ex_dmem_uop_T_304 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.ctrl.legal, UInt<1>(0h0)) node _ex_dmem_uop_T_305 = or(_ex_dmem_uop_T_303, _ex_dmem_uop_T_304) wire _ex_dmem_uop_WIRE_110 : UInt<1> connect _ex_dmem_uop_WIRE_110, _ex_dmem_uop_T_305 connect _ex_dmem_uop_WIRE_82.legal, _ex_dmem_uop_WIRE_110 connect _ex_dmem_uop_WIRE.ctrl, _ex_dmem_uop_WIRE_82 node _ex_dmem_uop_T_306 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.edge_inst, UInt<1>(0h0)) node _ex_dmem_uop_T_307 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.edge_inst, UInt<1>(0h0)) node _ex_dmem_uop_T_308 = or(_ex_dmem_uop_T_306, _ex_dmem_uop_T_307) wire _ex_dmem_uop_WIRE_111 : UInt<1> connect _ex_dmem_uop_WIRE_111, _ex_dmem_uop_T_308 connect _ex_dmem_uop_WIRE.edge_inst, _ex_dmem_uop_WIRE_111 node _ex_dmem_uop_T_309 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.pc, UInt<1>(0h0)) node _ex_dmem_uop_T_310 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.pc, UInt<1>(0h0)) node _ex_dmem_uop_T_311 = or(_ex_dmem_uop_T_309, _ex_dmem_uop_T_310) wire _ex_dmem_uop_WIRE_112 : UInt<40> connect _ex_dmem_uop_WIRE_112, _ex_dmem_uop_T_311 connect _ex_dmem_uop_WIRE.pc, _ex_dmem_uop_WIRE_112 node _ex_dmem_uop_T_312 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.raw_inst, UInt<1>(0h0)) node _ex_dmem_uop_T_313 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.raw_inst, UInt<1>(0h0)) node _ex_dmem_uop_T_314 = or(_ex_dmem_uop_T_312, _ex_dmem_uop_T_313) wire _ex_dmem_uop_WIRE_113 : UInt<32> connect _ex_dmem_uop_WIRE_113, _ex_dmem_uop_T_314 connect _ex_dmem_uop_WIRE.raw_inst, _ex_dmem_uop_WIRE_113 node _ex_dmem_uop_T_315 = mux(ex_dmem_oh_0, ex_uops_reg[0].bits.inst, UInt<1>(0h0)) node _ex_dmem_uop_T_316 = mux(ex_dmem_oh_1, ex_uops_reg[1].bits.inst, UInt<1>(0h0)) node _ex_dmem_uop_T_317 = or(_ex_dmem_uop_T_315, _ex_dmem_uop_T_316) wire _ex_dmem_uop_WIRE_114 : UInt<32> connect _ex_dmem_uop_WIRE_114, _ex_dmem_uop_T_317 connect _ex_dmem_uop_WIRE.inst, _ex_dmem_uop_WIRE_114 connect ex_dmem_uop.bits, _ex_dmem_uop_WIRE node _ex_dmem_uop_T_318 = mux(ex_dmem_oh_0, ex_uops_reg[0].valid, UInt<1>(0h0)) node _ex_dmem_uop_T_319 = mux(ex_dmem_oh_1, ex_uops_reg[1].valid, UInt<1>(0h0)) node _ex_dmem_uop_T_320 = or(_ex_dmem_uop_T_318, _ex_dmem_uop_T_319) wire _ex_dmem_uop_WIRE_115 : UInt<1> connect _ex_dmem_uop_WIRE_115, _ex_dmem_uop_T_320 connect ex_dmem_uop.valid, _ex_dmem_uop_WIRE_115 wire ex_dmem_addrs : UInt[2] node _io_dmem_req_valid_T = or(ex_dmem_oh_0, ex_dmem_oh_1) node _io_dmem_req_valid_T_1 = eq(ex_dmem_uop.bits.xcpt, UInt<1>(0h0)) node _io_dmem_req_valid_T_2 = and(_io_dmem_req_valid_T, _io_dmem_req_valid_T_1) connect io.dmem.req.valid, _io_dmem_req_valid_T_2 invalidate io.dmem.req.bits.mask invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.signed invalidate io.dmem.req.bits.size invalidate io.dmem.req.bits.cmd invalidate io.dmem.req.bits.tag invalidate io.dmem.req.bits.addr node _io_dmem_req_bits_tag_T = bits(ex_dmem_uop.bits.inst, 11, 7) node _io_dmem_req_bits_tag_T_1 = cat(_io_dmem_req_bits_tag_T, ex_dmem_uop.bits.ctrl.fp) connect io.dmem.req.bits.tag, _io_dmem_req_bits_tag_T_1 connect io.dmem.req.bits.cmd, ex_dmem_uop.bits.ctrl.mem_cmd connect io.dmem.req.bits.size, ex_dmem_uop.bits.mem_size node _io_dmem_req_bits_signed_T = bits(ex_dmem_uop.bits.inst, 14, 14) node _io_dmem_req_bits_signed_T_1 = eq(_io_dmem_req_bits_signed_T, UInt<1>(0h0)) connect io.dmem.req.bits.signed, _io_dmem_req_bits_signed_T_1 node _io_dmem_req_bits_addr_T = mux(ex_dmem_oh_0, ex_dmem_addrs[0], UInt<1>(0h0)) node _io_dmem_req_bits_addr_T_1 = mux(ex_dmem_oh_1, ex_dmem_addrs[1], UInt<1>(0h0)) node _io_dmem_req_bits_addr_T_2 = or(_io_dmem_req_bits_addr_T, _io_dmem_req_bits_addr_T_1) wire _io_dmem_req_bits_addr_WIRE : UInt connect _io_dmem_req_bits_addr_WIRE, _io_dmem_req_bits_addr_T_2 connect io.dmem.req.bits.addr, _io_dmem_req_bits_addr_WIRE connect io.dmem.s1_kill, UInt<1>(0h0) connect io.dmem.s2_kill, UInt<1>(0h0) node _kill_T = or(ex_stall, flush_rrd_ex) node _kill_T_1 = and(io.dmem.req.ready, io.dmem.req.valid) reg kill_r : UInt<1>, clock when _kill_T_1 : connect kill_r, _kill_T node kill = or(kill_r, kill_mem) node _T_125 = and(io.dmem.req.ready, io.dmem.req.valid) node _T_126 = and(_T_125, ex_dmem_oh_0) reg REG : UInt<1>, clock connect REG, _T_126 node _T_127 = and(REG, kill) when _T_127 : connect io.dmem.s1_kill, UInt<1>(0h1) node _kill_T_2 = or(ex_stall, flush_rrd_ex) node _kill_T_3 = and(io.dmem.req.ready, io.dmem.req.valid) reg kill_r_1 : UInt<1>, clock when _kill_T_3 : connect kill_r_1, _kill_T_2 node kill_1 = or(kill_r_1, kill_mem) node _T_128 = and(io.dmem.req.ready, io.dmem.req.valid) node _T_129 = and(_T_128, ex_dmem_oh_1) reg REG_1 : UInt<1>, clock connect REG_1, _T_129 node _T_130 = and(REG_1, kill_1) when _T_130 : connect io.dmem.s1_kill, UInt<1>(0h1) inst alu of ALU connect alu.clock, clock connect alu.reset, reset node _imm_sign_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_sign_T_1 = bits(ex_uops_reg[0].bits.inst, 31, 31) node _imm_sign_T_2 = asSInt(_imm_sign_T_1) node imm_sign = mux(_imm_sign_T, asSInt(UInt<1>(0h0)), _imm_sign_T_2) node _imm_b30_20_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b30_20_T_1 = bits(ex_uops_reg[0].bits.inst, 30, 20) node _imm_b30_20_T_2 = asSInt(_imm_b30_20_T_1) node imm_b30_20 = mux(_imm_b30_20_T, _imm_b30_20_T_2, imm_sign) node _imm_b19_12_T = neq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b19_12_T_1 = neq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b19_12_T_2 = and(_imm_b19_12_T, _imm_b19_12_T_1) node _imm_b19_12_T_3 = bits(ex_uops_reg[0].bits.inst, 19, 12) node _imm_b19_12_T_4 = asSInt(_imm_b19_12_T_3) node imm_b19_12 = mux(_imm_b19_12_T_2, imm_sign, _imm_b19_12_T_4) node _imm_b11_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b11_T_1 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b11_T_2 = or(_imm_b11_T, _imm_b11_T_1) node _imm_b11_T_3 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b11_T_4 = bits(ex_uops_reg[0].bits.inst, 20, 20) node _imm_b11_T_5 = asSInt(_imm_b11_T_4) node _imm_b11_T_6 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b11_T_7 = bits(ex_uops_reg[0].bits.inst, 7, 7) node _imm_b11_T_8 = asSInt(_imm_b11_T_7) node _imm_b11_T_9 = mux(_imm_b11_T_6, _imm_b11_T_8, imm_sign) node _imm_b11_T_10 = mux(_imm_b11_T_3, _imm_b11_T_5, _imm_b11_T_9) node imm_b11 = mux(_imm_b11_T_2, asSInt(UInt<1>(0h0)), _imm_b11_T_10) node _imm_b10_5_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b10_5_T_1 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b10_5_T_2 = or(_imm_b10_5_T, _imm_b10_5_T_1) node _imm_b10_5_T_3 = bits(ex_uops_reg[0].bits.inst, 30, 25) node imm_b10_5 = mux(_imm_b10_5_T_2, UInt<1>(0h0), _imm_b10_5_T_3) node _imm_b4_1_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b4_1_T_1 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b4_1_T_2 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b4_1_T_3 = or(_imm_b4_1_T_1, _imm_b4_1_T_2) node _imm_b4_1_T_4 = bits(ex_uops_reg[0].bits.inst, 11, 8) node _imm_b4_1_T_5 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b4_1_T_6 = bits(ex_uops_reg[0].bits.inst, 19, 16) node _imm_b4_1_T_7 = bits(ex_uops_reg[0].bits.inst, 24, 21) node _imm_b4_1_T_8 = mux(_imm_b4_1_T_5, _imm_b4_1_T_6, _imm_b4_1_T_7) node _imm_b4_1_T_9 = mux(_imm_b4_1_T_3, _imm_b4_1_T_4, _imm_b4_1_T_8) node imm_b4_1 = mux(_imm_b4_1_T, UInt<1>(0h0), _imm_b4_1_T_9) node _imm_b0_T = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b0_T_1 = bits(ex_uops_reg[0].bits.inst, 7, 7) node _imm_b0_T_2 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h4)) node _imm_b0_T_3 = bits(ex_uops_reg[0].bits.inst, 20, 20) node _imm_b0_T_4 = eq(ex_uops_reg[0].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b0_T_5 = bits(ex_uops_reg[0].bits.inst, 15, 15) node _imm_b0_T_6 = mux(_imm_b0_T_4, _imm_b0_T_5, UInt<1>(0h0)) node _imm_b0_T_7 = mux(_imm_b0_T_2, _imm_b0_T_3, _imm_b0_T_6) node imm_b0 = mux(_imm_b0_T, _imm_b0_T_1, _imm_b0_T_7) node imm_lo_hi = cat(imm_b10_5, imm_b4_1) node imm_lo = cat(imm_lo_hi, imm_b0) node imm_hi_lo_lo = asUInt(imm_b11) node imm_hi_lo_hi = asUInt(imm_b19_12) node imm_hi_lo = cat(imm_hi_lo_hi, imm_hi_lo_lo) node imm_hi_hi_lo = asUInt(imm_b30_20) node imm_hi_hi_hi = asUInt(imm_sign) node imm_hi_hi = cat(imm_hi_hi_hi, imm_hi_hi_lo) node imm_hi = cat(imm_hi_hi, imm_hi_lo) node _imm_T = cat(imm_hi, imm_lo) node imm = asSInt(_imm_T) wire sel_alu1 : UInt connect sel_alu1, ex_uops_reg[0].bits.ctrl.sel_alu1 wire sel_alu2 : UInt connect sel_alu2, ex_uops_reg[0].bits.ctrl.sel_alu2 node _ex_op1_T = asSInt(ex_uops_reg[0].bits.rs1_data) node _ex_op1_T_1 = asSInt(ex_uops_reg[0].bits.pc) node _ex_op1_T_2 = bits(ex_uops_reg[0].bits.inst, 3, 3) node _ex_op1_T_3 = bits(ex_uops_reg[0].bits.rs1_data, 31, 0) node _ex_op1_T_4 = mux(_ex_op1_T_2, _ex_op1_T_3, ex_uops_reg[0].bits.rs1_data) node _ex_op1_T_5 = bits(ex_uops_reg[0].bits.inst, 14, 13) node _ex_op1_T_6 = dshl(_ex_op1_T_4, _ex_op1_T_5) node _ex_op1_T_7 = asSInt(_ex_op1_T_6) node _ex_op1_T_8 = eq(UInt<2>(0h1), sel_alu1) node _ex_op1_T_9 = mux(_ex_op1_T_8, _ex_op1_T, asSInt(UInt<1>(0h0))) node _ex_op1_T_10 = eq(UInt<2>(0h2), sel_alu1) node _ex_op1_T_11 = mux(_ex_op1_T_10, _ex_op1_T_1, _ex_op1_T_9) node _ex_op1_T_12 = eq(UInt<2>(0h3), sel_alu1) node ex_op1 = mux(_ex_op1_T_12, _ex_op1_T_7, _ex_op1_T_11) node _ex_op2_oh_T = bits(ex_uops_reg[0].bits.ctrl.sel_alu2, 0, 0) node _ex_op2_oh_T_1 = shr(ex_uops_reg[0].bits.inst, 20) node _ex_op2_oh_T_2 = mux(_ex_op2_oh_T, _ex_op2_oh_T_1, ex_uops_reg[0].bits.rs2_data) node _ex_op2_oh_T_3 = bits(_ex_op2_oh_T_2, 5, 0) node _ex_op2_oh_T_4 = dshl(UInt<1>(0h1), _ex_op2_oh_T_3) node ex_op2_oh = asSInt(_ex_op2_oh_T_4) node _ex_op2_T = asSInt(ex_uops_reg[0].bits.rs2_data) node _ex_op2_T_1 = mux(ex_uops_reg[0].bits.rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _ex_op2_T_2 = eq(UInt<3>(0h2), sel_alu2) node _ex_op2_T_3 = mux(_ex_op2_T_2, _ex_op2_T, asSInt(UInt<1>(0h0))) node _ex_op2_T_4 = eq(UInt<3>(0h3), sel_alu2) node _ex_op2_T_5 = mux(_ex_op2_T_4, imm, _ex_op2_T_3) node _ex_op2_T_6 = eq(UInt<3>(0h1), sel_alu2) node _ex_op2_T_7 = mux(_ex_op2_T_6, _ex_op2_T_1, _ex_op2_T_5) node _ex_op2_T_8 = eq(UInt<3>(0h4), sel_alu2) node _ex_op2_T_9 = mux(_ex_op2_T_8, ex_op2_oh, _ex_op2_T_7) node _ex_op2_T_10 = eq(UInt<3>(0h5), sel_alu2) node ex_op2 = mux(_ex_op2_T_10, ex_op2_oh, _ex_op2_T_9) connect alu.io.dw, ex_uops_reg[0].bits.ctrl.alu_dw connect alu.io.fn, ex_uops_reg[0].bits.ctrl.alu_fn node _alu_io_in2_T = asUInt(ex_op2) connect alu.io.in2, _alu_io_in2_T node _alu_io_in1_T = asUInt(ex_op1) connect alu.io.in1, _alu_io_in1_T node _mem_uops_reg_0_bits_wdata_valid_T = eq(ex_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_1 = and(ex_uops_reg[0].bits.ctrl.wxd, _mem_uops_reg_0_bits_wdata_valid_T) node _mem_uops_reg_0_bits_wdata_valid_T_2 = eq(ex_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_3 = and(_mem_uops_reg_0_bits_wdata_valid_T_1, _mem_uops_reg_0_bits_wdata_valid_T_2) node _mem_uops_reg_0_bits_wdata_valid_T_4 = eq(ex_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_5 = and(_mem_uops_reg_0_bits_wdata_valid_T_3, _mem_uops_reg_0_bits_wdata_valid_T_4) node _mem_uops_reg_0_bits_wdata_valid_T_6 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h6)) node _mem_uops_reg_0_bits_wdata_valid_T_7 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h7)) node _mem_uops_reg_0_bits_wdata_valid_T_8 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h5)) node _mem_uops_reg_0_bits_wdata_valid_T_9 = or(_mem_uops_reg_0_bits_wdata_valid_T_6, _mem_uops_reg_0_bits_wdata_valid_T_7) node _mem_uops_reg_0_bits_wdata_valid_T_10 = or(_mem_uops_reg_0_bits_wdata_valid_T_9, _mem_uops_reg_0_bits_wdata_valid_T_8) node _mem_uops_reg_0_bits_wdata_valid_T_11 = eq(_mem_uops_reg_0_bits_wdata_valid_T_10, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_12 = and(_mem_uops_reg_0_bits_wdata_valid_T_5, _mem_uops_reg_0_bits_wdata_valid_T_11) node _mem_uops_reg_0_bits_wdata_valid_T_13 = eq(ex_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_14 = and(_mem_uops_reg_0_bits_wdata_valid_T_12, _mem_uops_reg_0_bits_wdata_valid_T_13) node _mem_uops_reg_0_bits_wdata_valid_T_15 = eq(ex_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_16 = and(_mem_uops_reg_0_bits_wdata_valid_T_14, _mem_uops_reg_0_bits_wdata_valid_T_15) node _mem_uops_reg_0_bits_wdata_valid_T_17 = eq(ex_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_18 = and(_mem_uops_reg_0_bits_wdata_valid_T_16, _mem_uops_reg_0_bits_wdata_valid_T_17) node _mem_uops_reg_0_bits_wdata_valid_T_19 = eq(ex_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_20 = and(_mem_uops_reg_0_bits_wdata_valid_T_18, _mem_uops_reg_0_bits_wdata_valid_T_19) node _mem_uops_reg_0_bits_wdata_valid_T_21 = eq(ex_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_22 = and(_mem_uops_reg_0_bits_wdata_valid_T_20, _mem_uops_reg_0_bits_wdata_valid_T_21) node _mem_uops_reg_0_bits_wdata_valid_T_23 = eq(ex_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_valid_T_24 = and(_mem_uops_reg_0_bits_wdata_valid_T_22, _mem_uops_reg_0_bits_wdata_valid_T_23) connect mem_uops_reg[0].bits.wdata.valid, _mem_uops_reg_0_bits_wdata_valid_T_24 node _mem_uops_reg_0_bits_wdata_bits_T = eq(ex_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _mem_uops_reg_0_bits_wdata_bits_T_1 = and(ex_uops_reg[0].bits.sets_vcfg, _mem_uops_reg_0_bits_wdata_bits_T) node _mem_uops_reg_0_bits_wdata_bits_T_2 = mux(_mem_uops_reg_0_bits_wdata_bits_T_1, alu.io.out, alu.io.out) connect mem_uops_reg[0].bits.wdata.bits, _mem_uops_reg_0_bits_wdata_bits_T_2 connect mem_uops_reg[0].bits.taken, alu.io.cmp_out node _ex_bypasses_0_valid_T = and(ex_uops_reg[0].valid, ex_uops_reg[0].bits.ctrl.wxd) connect ex_bypasses_0.valid, _ex_bypasses_0_valid_T node _ex_bypasses_0_dst_T = bits(ex_uops_reg[0].bits.inst, 11, 7) connect ex_bypasses_0.dst, _ex_bypasses_0_dst_T node _ex_bypasses_0_can_bypass_T = eq(ex_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_1 = and(ex_uops_reg[0].bits.ctrl.wxd, _ex_bypasses_0_can_bypass_T) node _ex_bypasses_0_can_bypass_T_2 = eq(ex_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_3 = and(_ex_bypasses_0_can_bypass_T_1, _ex_bypasses_0_can_bypass_T_2) node _ex_bypasses_0_can_bypass_T_4 = eq(ex_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_5 = and(_ex_bypasses_0_can_bypass_T_3, _ex_bypasses_0_can_bypass_T_4) node _ex_bypasses_0_can_bypass_T_6 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h6)) node _ex_bypasses_0_can_bypass_T_7 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h7)) node _ex_bypasses_0_can_bypass_T_8 = eq(ex_uops_reg[0].bits.ctrl.csr, UInt<3>(0h5)) node _ex_bypasses_0_can_bypass_T_9 = or(_ex_bypasses_0_can_bypass_T_6, _ex_bypasses_0_can_bypass_T_7) node _ex_bypasses_0_can_bypass_T_10 = or(_ex_bypasses_0_can_bypass_T_9, _ex_bypasses_0_can_bypass_T_8) node _ex_bypasses_0_can_bypass_T_11 = eq(_ex_bypasses_0_can_bypass_T_10, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_12 = and(_ex_bypasses_0_can_bypass_T_5, _ex_bypasses_0_can_bypass_T_11) node _ex_bypasses_0_can_bypass_T_13 = eq(ex_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_14 = and(_ex_bypasses_0_can_bypass_T_12, _ex_bypasses_0_can_bypass_T_13) node _ex_bypasses_0_can_bypass_T_15 = eq(ex_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_16 = and(_ex_bypasses_0_can_bypass_T_14, _ex_bypasses_0_can_bypass_T_15) node _ex_bypasses_0_can_bypass_T_17 = eq(ex_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_18 = and(_ex_bypasses_0_can_bypass_T_16, _ex_bypasses_0_can_bypass_T_17) node _ex_bypasses_0_can_bypass_T_19 = eq(ex_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_20 = and(_ex_bypasses_0_can_bypass_T_18, _ex_bypasses_0_can_bypass_T_19) node _ex_bypasses_0_can_bypass_T_21 = eq(ex_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_22 = and(_ex_bypasses_0_can_bypass_T_20, _ex_bypasses_0_can_bypass_T_21) node _ex_bypasses_0_can_bypass_T_23 = eq(ex_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_24 = and(_ex_bypasses_0_can_bypass_T_22, _ex_bypasses_0_can_bypass_T_23) node _ex_bypasses_0_can_bypass_T_25 = eq(ex_uops_reg[0].bits.sfb_shadow, UInt<1>(0h0)) node _ex_bypasses_0_can_bypass_T_26 = and(_ex_bypasses_0_can_bypass_T_24, _ex_bypasses_0_can_bypass_T_25) connect ex_bypasses_0.can_bypass, _ex_bypasses_0_can_bypass_T_26 node _ex_bypasses_0_data_T = mux(ex_uops_reg[0].bits.sets_vcfg, alu.io.out, alu.io.out) connect ex_bypasses_0.data, _ex_bypasses_0_data_T node _ex_dmem_addrs_0_a_T = asSInt(ex_uops_reg[0].bits.rs1_data) node ex_dmem_addrs_0_a = shr(_ex_dmem_addrs_0_a_T, 39) node _ex_dmem_addrs_0_msb_T = eq(ex_dmem_addrs_0_a, asSInt(UInt<1>(0h0))) node _ex_dmem_addrs_0_msb_T_1 = eq(ex_dmem_addrs_0_a, asSInt(UInt<1>(0h1))) node _ex_dmem_addrs_0_msb_T_2 = or(_ex_dmem_addrs_0_msb_T, _ex_dmem_addrs_0_msb_T_1) node _ex_dmem_addrs_0_msb_T_3 = bits(alu.io.adder_out, 39, 39) node _ex_dmem_addrs_0_msb_T_4 = bits(alu.io.adder_out, 38, 38) node _ex_dmem_addrs_0_msb_T_5 = eq(_ex_dmem_addrs_0_msb_T_4, UInt<1>(0h0)) node ex_dmem_addrs_0_msb = mux(_ex_dmem_addrs_0_msb_T_2, _ex_dmem_addrs_0_msb_T_3, _ex_dmem_addrs_0_msb_T_5) node _ex_dmem_addrs_0_T = bits(alu.io.adder_out, 38, 0) node _ex_dmem_addrs_0_T_1 = cat(ex_dmem_addrs_0_msb, _ex_dmem_addrs_0_T) connect ex_dmem_addrs[0], _ex_dmem_addrs_0_T_1 node _T_131 = or(ex_uops_reg[0].bits.ctrl.mem, ex_uops_reg[0].bits.ctrl.rocc) node _T_132 = eq(ex_uops_reg[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _T_133 = and(ex_uops_reg[0].bits.ctrl.mem, _T_132) node _T_134 = or(_T_131, _T_133) node _T_135 = and(ex_uops_reg[0].bits.ctrl.rxs2, _T_134) when _T_135 : node size = mux(ex_uops_reg[0].bits.ctrl.rocc, UInt<2>(0h3), ex_uops_reg[0].bits.mem_size) wire mem_uops_reg_0_bits_rs2_data_size : UInt<2> connect mem_uops_reg_0_bits_rs2_data_size, size node _mem_uops_reg_0_bits_rs2_data_T = eq(mem_uops_reg_0_bits_rs2_data_size, UInt<1>(0h0)) node _mem_uops_reg_0_bits_rs2_data_T_1 = bits(ex_uops_reg[0].bits.rs2_data, 7, 0) node _mem_uops_reg_0_bits_rs2_data_T_2 = cat(_mem_uops_reg_0_bits_rs2_data_T_1, _mem_uops_reg_0_bits_rs2_data_T_1) node _mem_uops_reg_0_bits_rs2_data_T_3 = cat(_mem_uops_reg_0_bits_rs2_data_T_2, _mem_uops_reg_0_bits_rs2_data_T_2) node _mem_uops_reg_0_bits_rs2_data_T_4 = cat(_mem_uops_reg_0_bits_rs2_data_T_3, _mem_uops_reg_0_bits_rs2_data_T_3) node _mem_uops_reg_0_bits_rs2_data_T_5 = eq(mem_uops_reg_0_bits_rs2_data_size, UInt<1>(0h1)) node _mem_uops_reg_0_bits_rs2_data_T_6 = bits(ex_uops_reg[0].bits.rs2_data, 15, 0) node _mem_uops_reg_0_bits_rs2_data_T_7 = cat(_mem_uops_reg_0_bits_rs2_data_T_6, _mem_uops_reg_0_bits_rs2_data_T_6) node _mem_uops_reg_0_bits_rs2_data_T_8 = cat(_mem_uops_reg_0_bits_rs2_data_T_7, _mem_uops_reg_0_bits_rs2_data_T_7) node _mem_uops_reg_0_bits_rs2_data_T_9 = eq(mem_uops_reg_0_bits_rs2_data_size, UInt<2>(0h2)) node _mem_uops_reg_0_bits_rs2_data_T_10 = bits(ex_uops_reg[0].bits.rs2_data, 31, 0) node _mem_uops_reg_0_bits_rs2_data_T_11 = cat(_mem_uops_reg_0_bits_rs2_data_T_10, _mem_uops_reg_0_bits_rs2_data_T_10) node _mem_uops_reg_0_bits_rs2_data_T_12 = mux(_mem_uops_reg_0_bits_rs2_data_T_9, _mem_uops_reg_0_bits_rs2_data_T_11, ex_uops_reg[0].bits.rs2_data) node _mem_uops_reg_0_bits_rs2_data_T_13 = mux(_mem_uops_reg_0_bits_rs2_data_T_5, _mem_uops_reg_0_bits_rs2_data_T_8, _mem_uops_reg_0_bits_rs2_data_T_12) node _mem_uops_reg_0_bits_rs2_data_T_14 = mux(_mem_uops_reg_0_bits_rs2_data_T, _mem_uops_reg_0_bits_rs2_data_T_4, _mem_uops_reg_0_bits_rs2_data_T_13) connect mem_uops_reg[0].bits.rs2_data, _mem_uops_reg_0_bits_rs2_data_T_14 inst alu_1 of ALU_1 connect alu_1.clock, clock connect alu_1.reset, reset node _imm_sign_T_3 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_sign_T_4 = bits(ex_uops_reg[1].bits.inst, 31, 31) node _imm_sign_T_5 = asSInt(_imm_sign_T_4) node imm_sign_1 = mux(_imm_sign_T_3, asSInt(UInt<1>(0h0)), _imm_sign_T_5) node _imm_b30_20_T_3 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b30_20_T_4 = bits(ex_uops_reg[1].bits.inst, 30, 20) node _imm_b30_20_T_5 = asSInt(_imm_b30_20_T_4) node imm_b30_20_1 = mux(_imm_b30_20_T_3, _imm_b30_20_T_5, imm_sign_1) node _imm_b19_12_T_5 = neq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b19_12_T_6 = neq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b19_12_T_7 = and(_imm_b19_12_T_5, _imm_b19_12_T_6) node _imm_b19_12_T_8 = bits(ex_uops_reg[1].bits.inst, 19, 12) node _imm_b19_12_T_9 = asSInt(_imm_b19_12_T_8) node imm_b19_12_1 = mux(_imm_b19_12_T_7, imm_sign_1, _imm_b19_12_T_9) node _imm_b11_T_11 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b11_T_12 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b11_T_13 = or(_imm_b11_T_11, _imm_b11_T_12) node _imm_b11_T_14 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b11_T_15 = bits(ex_uops_reg[1].bits.inst, 20, 20) node _imm_b11_T_16 = asSInt(_imm_b11_T_15) node _imm_b11_T_17 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b11_T_18 = bits(ex_uops_reg[1].bits.inst, 7, 7) node _imm_b11_T_19 = asSInt(_imm_b11_T_18) node _imm_b11_T_20 = mux(_imm_b11_T_17, _imm_b11_T_19, imm_sign_1) node _imm_b11_T_21 = mux(_imm_b11_T_14, _imm_b11_T_16, _imm_b11_T_20) node imm_b11_1 = mux(_imm_b11_T_13, asSInt(UInt<1>(0h0)), _imm_b11_T_21) node _imm_b10_5_T_4 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b10_5_T_5 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b10_5_T_6 = or(_imm_b10_5_T_4, _imm_b10_5_T_5) node _imm_b10_5_T_7 = bits(ex_uops_reg[1].bits.inst, 30, 25) node imm_b10_5_1 = mux(_imm_b10_5_T_6, UInt<1>(0h0), _imm_b10_5_T_7) node _imm_b4_1_T_10 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b4_1_T_11 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b4_1_T_12 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b4_1_T_13 = or(_imm_b4_1_T_11, _imm_b4_1_T_12) node _imm_b4_1_T_14 = bits(ex_uops_reg[1].bits.inst, 11, 8) node _imm_b4_1_T_15 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b4_1_T_16 = bits(ex_uops_reg[1].bits.inst, 19, 16) node _imm_b4_1_T_17 = bits(ex_uops_reg[1].bits.inst, 24, 21) node _imm_b4_1_T_18 = mux(_imm_b4_1_T_15, _imm_b4_1_T_16, _imm_b4_1_T_17) node _imm_b4_1_T_19 = mux(_imm_b4_1_T_13, _imm_b4_1_T_14, _imm_b4_1_T_18) node imm_b4_1_1 = mux(_imm_b4_1_T_10, UInt<1>(0h0), _imm_b4_1_T_19) node _imm_b0_T_8 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b0_T_9 = bits(ex_uops_reg[1].bits.inst, 7, 7) node _imm_b0_T_10 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h4)) node _imm_b0_T_11 = bits(ex_uops_reg[1].bits.inst, 20, 20) node _imm_b0_T_12 = eq(ex_uops_reg[1].bits.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b0_T_13 = bits(ex_uops_reg[1].bits.inst, 15, 15) node _imm_b0_T_14 = mux(_imm_b0_T_12, _imm_b0_T_13, UInt<1>(0h0)) node _imm_b0_T_15 = mux(_imm_b0_T_10, _imm_b0_T_11, _imm_b0_T_14) node imm_b0_1 = mux(_imm_b0_T_8, _imm_b0_T_9, _imm_b0_T_15) node imm_lo_hi_1 = cat(imm_b10_5_1, imm_b4_1_1) node imm_lo_1 = cat(imm_lo_hi_1, imm_b0_1) node imm_hi_lo_lo_1 = asUInt(imm_b11_1) node imm_hi_lo_hi_1 = asUInt(imm_b19_12_1) node imm_hi_lo_1 = cat(imm_hi_lo_hi_1, imm_hi_lo_lo_1) node imm_hi_hi_lo_1 = asUInt(imm_b30_20_1) node imm_hi_hi_hi_1 = asUInt(imm_sign_1) node imm_hi_hi_1 = cat(imm_hi_hi_hi_1, imm_hi_hi_lo_1) node imm_hi_1 = cat(imm_hi_hi_1, imm_hi_lo_1) node _imm_T_1 = cat(imm_hi_1, imm_lo_1) node imm_1 = asSInt(_imm_T_1) wire sel_alu1_1 : UInt connect sel_alu1_1, ex_uops_reg[1].bits.ctrl.sel_alu1 wire sel_alu2_1 : UInt connect sel_alu2_1, ex_uops_reg[1].bits.ctrl.sel_alu2 node _ex_op1_T_13 = asSInt(ex_uops_reg[1].bits.rs1_data) node _ex_op1_T_14 = asSInt(ex_uops_reg[1].bits.pc) node _ex_op1_T_15 = bits(ex_uops_reg[1].bits.inst, 3, 3) node _ex_op1_T_16 = bits(ex_uops_reg[1].bits.rs1_data, 31, 0) node _ex_op1_T_17 = mux(_ex_op1_T_15, _ex_op1_T_16, ex_uops_reg[1].bits.rs1_data) node _ex_op1_T_18 = bits(ex_uops_reg[1].bits.inst, 14, 13) node _ex_op1_T_19 = dshl(_ex_op1_T_17, _ex_op1_T_18) node _ex_op1_T_20 = asSInt(_ex_op1_T_19) node _ex_op1_T_21 = eq(UInt<2>(0h1), sel_alu1_1) node _ex_op1_T_22 = mux(_ex_op1_T_21, _ex_op1_T_13, asSInt(UInt<1>(0h0))) node _ex_op1_T_23 = eq(UInt<2>(0h2), sel_alu1_1) node _ex_op1_T_24 = mux(_ex_op1_T_23, _ex_op1_T_14, _ex_op1_T_22) node _ex_op1_T_25 = eq(UInt<2>(0h3), sel_alu1_1) node ex_op1_1 = mux(_ex_op1_T_25, _ex_op1_T_20, _ex_op1_T_24) node _ex_op2_oh_T_5 = bits(ex_uops_reg[1].bits.ctrl.sel_alu2, 0, 0) node _ex_op2_oh_T_6 = shr(ex_uops_reg[1].bits.inst, 20) node _ex_op2_oh_T_7 = mux(_ex_op2_oh_T_5, _ex_op2_oh_T_6, ex_uops_reg[1].bits.rs2_data) node _ex_op2_oh_T_8 = bits(_ex_op2_oh_T_7, 5, 0) node _ex_op2_oh_T_9 = dshl(UInt<1>(0h1), _ex_op2_oh_T_8) node ex_op2_oh_1 = asSInt(_ex_op2_oh_T_9) node _ex_op2_T_11 = asSInt(ex_uops_reg[1].bits.rs2_data) node _ex_op2_T_12 = mux(ex_uops_reg[1].bits.rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _ex_op2_T_13 = eq(UInt<3>(0h2), sel_alu2_1) node _ex_op2_T_14 = mux(_ex_op2_T_13, _ex_op2_T_11, asSInt(UInt<1>(0h0))) node _ex_op2_T_15 = eq(UInt<3>(0h3), sel_alu2_1) node _ex_op2_T_16 = mux(_ex_op2_T_15, imm_1, _ex_op2_T_14) node _ex_op2_T_17 = eq(UInt<3>(0h1), sel_alu2_1) node _ex_op2_T_18 = mux(_ex_op2_T_17, _ex_op2_T_12, _ex_op2_T_16) node _ex_op2_T_19 = eq(UInt<3>(0h4), sel_alu2_1) node _ex_op2_T_20 = mux(_ex_op2_T_19, ex_op2_oh_1, _ex_op2_T_18) node _ex_op2_T_21 = eq(UInt<3>(0h5), sel_alu2_1) node ex_op2_1 = mux(_ex_op2_T_21, ex_op2_oh_1, _ex_op2_T_20) connect alu_1.io.dw, ex_uops_reg[1].bits.ctrl.alu_dw connect alu_1.io.fn, ex_uops_reg[1].bits.ctrl.alu_fn node _alu_io_in2_T_1 = asUInt(ex_op2_1) connect alu_1.io.in2, _alu_io_in2_T_1 node _alu_io_in1_T_1 = asUInt(ex_op1_1) connect alu_1.io.in1, _alu_io_in1_T_1 node _mem_uops_reg_1_bits_wdata_valid_T = eq(ex_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_1 = and(ex_uops_reg[1].bits.ctrl.wxd, _mem_uops_reg_1_bits_wdata_valid_T) node _mem_uops_reg_1_bits_wdata_valid_T_2 = eq(ex_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_3 = and(_mem_uops_reg_1_bits_wdata_valid_T_1, _mem_uops_reg_1_bits_wdata_valid_T_2) node _mem_uops_reg_1_bits_wdata_valid_T_4 = eq(ex_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_5 = and(_mem_uops_reg_1_bits_wdata_valid_T_3, _mem_uops_reg_1_bits_wdata_valid_T_4) node _mem_uops_reg_1_bits_wdata_valid_T_6 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h6)) node _mem_uops_reg_1_bits_wdata_valid_T_7 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h7)) node _mem_uops_reg_1_bits_wdata_valid_T_8 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h5)) node _mem_uops_reg_1_bits_wdata_valid_T_9 = or(_mem_uops_reg_1_bits_wdata_valid_T_6, _mem_uops_reg_1_bits_wdata_valid_T_7) node _mem_uops_reg_1_bits_wdata_valid_T_10 = or(_mem_uops_reg_1_bits_wdata_valid_T_9, _mem_uops_reg_1_bits_wdata_valid_T_8) node _mem_uops_reg_1_bits_wdata_valid_T_11 = eq(_mem_uops_reg_1_bits_wdata_valid_T_10, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_12 = and(_mem_uops_reg_1_bits_wdata_valid_T_5, _mem_uops_reg_1_bits_wdata_valid_T_11) node _mem_uops_reg_1_bits_wdata_valid_T_13 = eq(ex_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_14 = and(_mem_uops_reg_1_bits_wdata_valid_T_12, _mem_uops_reg_1_bits_wdata_valid_T_13) node _mem_uops_reg_1_bits_wdata_valid_T_15 = eq(ex_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_16 = and(_mem_uops_reg_1_bits_wdata_valid_T_14, _mem_uops_reg_1_bits_wdata_valid_T_15) node _mem_uops_reg_1_bits_wdata_valid_T_17 = eq(ex_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_18 = and(_mem_uops_reg_1_bits_wdata_valid_T_16, _mem_uops_reg_1_bits_wdata_valid_T_17) node _mem_uops_reg_1_bits_wdata_valid_T_19 = eq(ex_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_20 = and(_mem_uops_reg_1_bits_wdata_valid_T_18, _mem_uops_reg_1_bits_wdata_valid_T_19) node _mem_uops_reg_1_bits_wdata_valid_T_21 = eq(ex_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_22 = and(_mem_uops_reg_1_bits_wdata_valid_T_20, _mem_uops_reg_1_bits_wdata_valid_T_21) node _mem_uops_reg_1_bits_wdata_valid_T_23 = eq(ex_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_valid_T_24 = and(_mem_uops_reg_1_bits_wdata_valid_T_22, _mem_uops_reg_1_bits_wdata_valid_T_23) connect mem_uops_reg[1].bits.wdata.valid, _mem_uops_reg_1_bits_wdata_valid_T_24 node _mem_uops_reg_1_bits_wdata_bits_T = eq(ex_uops_reg[1].bits.xcpt, UInt<1>(0h0)) node _mem_uops_reg_1_bits_wdata_bits_T_1 = and(ex_uops_reg[1].bits.sets_vcfg, _mem_uops_reg_1_bits_wdata_bits_T) node _mem_uops_reg_1_bits_wdata_bits_T_2 = mux(_mem_uops_reg_1_bits_wdata_bits_T_1, alu_1.io.out, alu_1.io.out) connect mem_uops_reg[1].bits.wdata.bits, _mem_uops_reg_1_bits_wdata_bits_T_2 connect mem_uops_reg[1].bits.taken, alu_1.io.cmp_out node _ex_bypasses_1_valid_T = and(ex_uops_reg[1].valid, ex_uops_reg[1].bits.ctrl.wxd) connect ex_bypasses_1.valid, _ex_bypasses_1_valid_T node _ex_bypasses_1_dst_T = bits(ex_uops_reg[1].bits.inst, 11, 7) connect ex_bypasses_1.dst, _ex_bypasses_1_dst_T node _ex_bypasses_1_can_bypass_T = eq(ex_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_1 = and(ex_uops_reg[1].bits.ctrl.wxd, _ex_bypasses_1_can_bypass_T) node _ex_bypasses_1_can_bypass_T_2 = eq(ex_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_3 = and(_ex_bypasses_1_can_bypass_T_1, _ex_bypasses_1_can_bypass_T_2) node _ex_bypasses_1_can_bypass_T_4 = eq(ex_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_5 = and(_ex_bypasses_1_can_bypass_T_3, _ex_bypasses_1_can_bypass_T_4) node _ex_bypasses_1_can_bypass_T_6 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h6)) node _ex_bypasses_1_can_bypass_T_7 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h7)) node _ex_bypasses_1_can_bypass_T_8 = eq(ex_uops_reg[1].bits.ctrl.csr, UInt<3>(0h5)) node _ex_bypasses_1_can_bypass_T_9 = or(_ex_bypasses_1_can_bypass_T_6, _ex_bypasses_1_can_bypass_T_7) node _ex_bypasses_1_can_bypass_T_10 = or(_ex_bypasses_1_can_bypass_T_9, _ex_bypasses_1_can_bypass_T_8) node _ex_bypasses_1_can_bypass_T_11 = eq(_ex_bypasses_1_can_bypass_T_10, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_12 = and(_ex_bypasses_1_can_bypass_T_5, _ex_bypasses_1_can_bypass_T_11) node _ex_bypasses_1_can_bypass_T_13 = eq(ex_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_14 = and(_ex_bypasses_1_can_bypass_T_12, _ex_bypasses_1_can_bypass_T_13) node _ex_bypasses_1_can_bypass_T_15 = eq(ex_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_16 = and(_ex_bypasses_1_can_bypass_T_14, _ex_bypasses_1_can_bypass_T_15) node _ex_bypasses_1_can_bypass_T_17 = eq(ex_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_18 = and(_ex_bypasses_1_can_bypass_T_16, _ex_bypasses_1_can_bypass_T_17) node _ex_bypasses_1_can_bypass_T_19 = eq(ex_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_20 = and(_ex_bypasses_1_can_bypass_T_18, _ex_bypasses_1_can_bypass_T_19) node _ex_bypasses_1_can_bypass_T_21 = eq(ex_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_22 = and(_ex_bypasses_1_can_bypass_T_20, _ex_bypasses_1_can_bypass_T_21) node _ex_bypasses_1_can_bypass_T_23 = eq(ex_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_24 = and(_ex_bypasses_1_can_bypass_T_22, _ex_bypasses_1_can_bypass_T_23) node _ex_bypasses_1_can_bypass_T_25 = eq(ex_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _ex_bypasses_1_can_bypass_T_26 = and(_ex_bypasses_1_can_bypass_T_24, _ex_bypasses_1_can_bypass_T_25) connect ex_bypasses_1.can_bypass, _ex_bypasses_1_can_bypass_T_26 node _ex_bypasses_1_data_T = mux(ex_uops_reg[1].bits.sets_vcfg, alu_1.io.out, alu_1.io.out) connect ex_bypasses_1.data, _ex_bypasses_1_data_T node _ex_dmem_addrs_1_a_T = asSInt(ex_uops_reg[1].bits.rs1_data) node ex_dmem_addrs_1_a = shr(_ex_dmem_addrs_1_a_T, 39) node _ex_dmem_addrs_1_msb_T = eq(ex_dmem_addrs_1_a, asSInt(UInt<1>(0h0))) node _ex_dmem_addrs_1_msb_T_1 = eq(ex_dmem_addrs_1_a, asSInt(UInt<1>(0h1))) node _ex_dmem_addrs_1_msb_T_2 = or(_ex_dmem_addrs_1_msb_T, _ex_dmem_addrs_1_msb_T_1) node _ex_dmem_addrs_1_msb_T_3 = bits(alu_1.io.adder_out, 39, 39) node _ex_dmem_addrs_1_msb_T_4 = bits(alu_1.io.adder_out, 38, 38) node _ex_dmem_addrs_1_msb_T_5 = eq(_ex_dmem_addrs_1_msb_T_4, UInt<1>(0h0)) node ex_dmem_addrs_1_msb = mux(_ex_dmem_addrs_1_msb_T_2, _ex_dmem_addrs_1_msb_T_3, _ex_dmem_addrs_1_msb_T_5) node _ex_dmem_addrs_1_T = bits(alu_1.io.adder_out, 38, 0) node _ex_dmem_addrs_1_T_1 = cat(ex_dmem_addrs_1_msb, _ex_dmem_addrs_1_T) connect ex_dmem_addrs[1], _ex_dmem_addrs_1_T_1 node _T_136 = or(ex_uops_reg[1].bits.ctrl.mem, ex_uops_reg[1].bits.ctrl.rocc) node _T_137 = eq(ex_uops_reg[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _T_138 = and(ex_uops_reg[1].bits.ctrl.mem, _T_137) node _T_139 = or(_T_136, _T_138) node _T_140 = and(ex_uops_reg[1].bits.ctrl.rxs2, _T_139) when _T_140 : node size_1 = mux(ex_uops_reg[1].bits.ctrl.rocc, UInt<2>(0h3), ex_uops_reg[1].bits.mem_size) wire mem_uops_reg_1_bits_rs2_data_size : UInt<2> connect mem_uops_reg_1_bits_rs2_data_size, size_1 node _mem_uops_reg_1_bits_rs2_data_T = eq(mem_uops_reg_1_bits_rs2_data_size, UInt<1>(0h0)) node _mem_uops_reg_1_bits_rs2_data_T_1 = bits(ex_uops_reg[1].bits.rs2_data, 7, 0) node _mem_uops_reg_1_bits_rs2_data_T_2 = cat(_mem_uops_reg_1_bits_rs2_data_T_1, _mem_uops_reg_1_bits_rs2_data_T_1) node _mem_uops_reg_1_bits_rs2_data_T_3 = cat(_mem_uops_reg_1_bits_rs2_data_T_2, _mem_uops_reg_1_bits_rs2_data_T_2) node _mem_uops_reg_1_bits_rs2_data_T_4 = cat(_mem_uops_reg_1_bits_rs2_data_T_3, _mem_uops_reg_1_bits_rs2_data_T_3) node _mem_uops_reg_1_bits_rs2_data_T_5 = eq(mem_uops_reg_1_bits_rs2_data_size, UInt<1>(0h1)) node _mem_uops_reg_1_bits_rs2_data_T_6 = bits(ex_uops_reg[1].bits.rs2_data, 15, 0) node _mem_uops_reg_1_bits_rs2_data_T_7 = cat(_mem_uops_reg_1_bits_rs2_data_T_6, _mem_uops_reg_1_bits_rs2_data_T_6) node _mem_uops_reg_1_bits_rs2_data_T_8 = cat(_mem_uops_reg_1_bits_rs2_data_T_7, _mem_uops_reg_1_bits_rs2_data_T_7) node _mem_uops_reg_1_bits_rs2_data_T_9 = eq(mem_uops_reg_1_bits_rs2_data_size, UInt<2>(0h2)) node _mem_uops_reg_1_bits_rs2_data_T_10 = bits(ex_uops_reg[1].bits.rs2_data, 31, 0) node _mem_uops_reg_1_bits_rs2_data_T_11 = cat(_mem_uops_reg_1_bits_rs2_data_T_10, _mem_uops_reg_1_bits_rs2_data_T_10) node _mem_uops_reg_1_bits_rs2_data_T_12 = mux(_mem_uops_reg_1_bits_rs2_data_T_9, _mem_uops_reg_1_bits_rs2_data_T_11, ex_uops_reg[1].bits.rs2_data) node _mem_uops_reg_1_bits_rs2_data_T_13 = mux(_mem_uops_reg_1_bits_rs2_data_T_5, _mem_uops_reg_1_bits_rs2_data_T_8, _mem_uops_reg_1_bits_rs2_data_T_12) node _mem_uops_reg_1_bits_rs2_data_T_14 = mux(_mem_uops_reg_1_bits_rs2_data_T, _mem_uops_reg_1_bits_rs2_data_T_4, _mem_uops_reg_1_bits_rs2_data_T_13) connect mem_uops_reg[1].bits.rs2_data, _mem_uops_reg_1_bits_rs2_data_T_14 node _ex_dmem_structural_hazard_T = eq(io.dmem.req.ready, UInt<1>(0h0)) node ex_dmem_structural_hazard = and(io.dmem.req.valid, _ex_dmem_structural_hazard_T) node _ex_stall_T = or(ex_uops_reg[0].valid, ex_uops_reg[1].valid) node _ex_stall_T_1 = or(UInt<1>(0h0), ex_fcsr_data_hazard) node _ex_stall_T_2 = or(_ex_stall_T_1, ex_dmem_structural_hazard) node _ex_stall_T_3 = or(ex_fp_data_hazard_0, ex_fp_data_hazard_1) node _ex_stall_T_4 = or(_ex_stall_T_2, _ex_stall_T_3) node _ex_stall_T_5 = and(_ex_stall_T, _ex_stall_T_4) connect ex_stall, _ex_stall_T_5 inst dtlb of ShuttleDTLB connect dtlb.clock, clock connect dtlb.reset, reset connect fp_pipe.io.s1_kill, kill_mem node _mem_brjmp_oh_T = or(mem_uops_reg[0].bits.ctrl.branch, mem_uops_reg[0].bits.ctrl.jal) node _mem_brjmp_oh_T_1 = or(_mem_brjmp_oh_T, mem_uops_reg[0].bits.ctrl.jalr) node _mem_brjmp_oh_T_2 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _mem_brjmp_oh_T_3 = and(mem_uops_reg[0].bits.ctrl.mem, _mem_brjmp_oh_T_2) node _mem_brjmp_oh_T_4 = or(_mem_brjmp_oh_T_1, _mem_brjmp_oh_T_3) node _mem_brjmp_oh_T_5 = or(_mem_brjmp_oh_T_4, mem_uops_reg[0].bits.next_pc.valid) node mem_brjmp_oh_0 = and(mem_uops_reg[0].valid, _mem_brjmp_oh_T_5) node _mem_brjmp_oh_T_6 = or(mem_uops_reg[1].bits.ctrl.branch, mem_uops_reg[1].bits.ctrl.jal) node _mem_brjmp_oh_T_7 = or(_mem_brjmp_oh_T_6, mem_uops_reg[1].bits.ctrl.jalr) node _mem_brjmp_oh_T_8 = eq(mem_uops_reg[1].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _mem_brjmp_oh_T_9 = and(mem_uops_reg[1].bits.ctrl.mem, _mem_brjmp_oh_T_8) node _mem_brjmp_oh_T_10 = or(_mem_brjmp_oh_T_7, _mem_brjmp_oh_T_9) node _mem_brjmp_oh_T_11 = or(_mem_brjmp_oh_T_10, mem_uops_reg[1].bits.next_pc.valid) node mem_brjmp_oh_1 = and(mem_uops_reg[1].valid, _mem_brjmp_oh_T_11) node _T_141 = add(mem_brjmp_oh_0, mem_brjmp_oh_1) node _T_142 = bits(_T_141, 1, 0) node _T_143 = leq(_T_142, UInt<1>(0h1)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:641 assert(PopCount(mem_brjmp_oh) <= 1.U)\n") : printf_1 assert(clock, _T_143, UInt<1>(0h1), "") : assert_1 node mem_brjmp_val = or(mem_brjmp_oh_0, mem_brjmp_oh_1) wire _mem_brjmp_uop_WIRE : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _mem_brjmp_uop_WIRE_1 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _mem_brjmp_uop_T = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.flush_pipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_1 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.flush_pipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_2 = or(_mem_brjmp_uop_T, _mem_brjmp_uop_T_1) wire _mem_brjmp_uop_WIRE_2 : UInt<1> connect _mem_brjmp_uop_WIRE_2, _mem_brjmp_uop_T_2 connect _mem_brjmp_uop_WIRE_1.flush_pipe, _mem_brjmp_uop_WIRE_2 node _mem_brjmp_uop_T_3 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.mem_size, UInt<1>(0h0)) node _mem_brjmp_uop_T_4 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.mem_size, UInt<1>(0h0)) node _mem_brjmp_uop_T_5 = or(_mem_brjmp_uop_T_3, _mem_brjmp_uop_T_4) wire _mem_brjmp_uop_WIRE_3 : UInt<2> connect _mem_brjmp_uop_WIRE_3, _mem_brjmp_uop_T_5 connect _mem_brjmp_uop_WIRE_1.mem_size, _mem_brjmp_uop_WIRE_3 wire _mem_brjmp_uop_WIRE_4 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _mem_brjmp_uop_T_6 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.in3, UInt<1>(0h0)) node _mem_brjmp_uop_T_7 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.in3, UInt<1>(0h0)) node _mem_brjmp_uop_T_8 = or(_mem_brjmp_uop_T_6, _mem_brjmp_uop_T_7) wire _mem_brjmp_uop_WIRE_5 : UInt<65> connect _mem_brjmp_uop_WIRE_5, _mem_brjmp_uop_T_8 connect _mem_brjmp_uop_WIRE_4.in3, _mem_brjmp_uop_WIRE_5 node _mem_brjmp_uop_T_9 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.in2, UInt<1>(0h0)) node _mem_brjmp_uop_T_10 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.in2, UInt<1>(0h0)) node _mem_brjmp_uop_T_11 = or(_mem_brjmp_uop_T_9, _mem_brjmp_uop_T_10) wire _mem_brjmp_uop_WIRE_6 : UInt<65> connect _mem_brjmp_uop_WIRE_6, _mem_brjmp_uop_T_11 connect _mem_brjmp_uop_WIRE_4.in2, _mem_brjmp_uop_WIRE_6 node _mem_brjmp_uop_T_12 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.in1, UInt<1>(0h0)) node _mem_brjmp_uop_T_13 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.in1, UInt<1>(0h0)) node _mem_brjmp_uop_T_14 = or(_mem_brjmp_uop_T_12, _mem_brjmp_uop_T_13) wire _mem_brjmp_uop_WIRE_7 : UInt<65> connect _mem_brjmp_uop_WIRE_7, _mem_brjmp_uop_T_14 connect _mem_brjmp_uop_WIRE_4.in1, _mem_brjmp_uop_WIRE_7 node _mem_brjmp_uop_T_15 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.fmt, UInt<1>(0h0)) node _mem_brjmp_uop_T_16 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.fmt, UInt<1>(0h0)) node _mem_brjmp_uop_T_17 = or(_mem_brjmp_uop_T_15, _mem_brjmp_uop_T_16) wire _mem_brjmp_uop_WIRE_8 : UInt<2> connect _mem_brjmp_uop_WIRE_8, _mem_brjmp_uop_T_17 connect _mem_brjmp_uop_WIRE_4.fmt, _mem_brjmp_uop_WIRE_8 node _mem_brjmp_uop_T_18 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.typ, UInt<1>(0h0)) node _mem_brjmp_uop_T_19 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.typ, UInt<1>(0h0)) node _mem_brjmp_uop_T_20 = or(_mem_brjmp_uop_T_18, _mem_brjmp_uop_T_19) wire _mem_brjmp_uop_WIRE_9 : UInt<2> connect _mem_brjmp_uop_WIRE_9, _mem_brjmp_uop_T_20 connect _mem_brjmp_uop_WIRE_4.typ, _mem_brjmp_uop_WIRE_9 node _mem_brjmp_uop_T_21 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _mem_brjmp_uop_T_22 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _mem_brjmp_uop_T_23 = or(_mem_brjmp_uop_T_21, _mem_brjmp_uop_T_22) wire _mem_brjmp_uop_WIRE_10 : UInt<2> connect _mem_brjmp_uop_WIRE_10, _mem_brjmp_uop_T_23 connect _mem_brjmp_uop_WIRE_4.fmaCmd, _mem_brjmp_uop_WIRE_10 node _mem_brjmp_uop_T_24 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.rm, UInt<1>(0h0)) node _mem_brjmp_uop_T_25 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.rm, UInt<1>(0h0)) node _mem_brjmp_uop_T_26 = or(_mem_brjmp_uop_T_24, _mem_brjmp_uop_T_25) wire _mem_brjmp_uop_WIRE_11 : UInt<3> connect _mem_brjmp_uop_WIRE_11, _mem_brjmp_uop_T_26 connect _mem_brjmp_uop_WIRE_4.rm, _mem_brjmp_uop_WIRE_11 node _mem_brjmp_uop_T_27 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_28 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_29 = or(_mem_brjmp_uop_T_27, _mem_brjmp_uop_T_28) wire _mem_brjmp_uop_WIRE_12 : UInt<1> connect _mem_brjmp_uop_WIRE_12, _mem_brjmp_uop_T_29 connect _mem_brjmp_uop_WIRE_4.vec, _mem_brjmp_uop_WIRE_12 node _mem_brjmp_uop_T_30 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.wflags, UInt<1>(0h0)) node _mem_brjmp_uop_T_31 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.wflags, UInt<1>(0h0)) node _mem_brjmp_uop_T_32 = or(_mem_brjmp_uop_T_30, _mem_brjmp_uop_T_31) wire _mem_brjmp_uop_WIRE_13 : UInt<1> connect _mem_brjmp_uop_WIRE_13, _mem_brjmp_uop_T_32 connect _mem_brjmp_uop_WIRE_4.wflags, _mem_brjmp_uop_WIRE_13 node _mem_brjmp_uop_T_33 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _mem_brjmp_uop_T_34 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _mem_brjmp_uop_T_35 = or(_mem_brjmp_uop_T_33, _mem_brjmp_uop_T_34) wire _mem_brjmp_uop_WIRE_14 : UInt<1> connect _mem_brjmp_uop_WIRE_14, _mem_brjmp_uop_T_35 connect _mem_brjmp_uop_WIRE_4.sqrt, _mem_brjmp_uop_WIRE_14 node _mem_brjmp_uop_T_36 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_37 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_38 = or(_mem_brjmp_uop_T_36, _mem_brjmp_uop_T_37) wire _mem_brjmp_uop_WIRE_15 : UInt<1> connect _mem_brjmp_uop_WIRE_15, _mem_brjmp_uop_T_38 connect _mem_brjmp_uop_WIRE_4.div, _mem_brjmp_uop_WIRE_15 node _mem_brjmp_uop_T_39 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.fma, UInt<1>(0h0)) node _mem_brjmp_uop_T_40 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.fma, UInt<1>(0h0)) node _mem_brjmp_uop_T_41 = or(_mem_brjmp_uop_T_39, _mem_brjmp_uop_T_40) wire _mem_brjmp_uop_WIRE_16 : UInt<1> connect _mem_brjmp_uop_WIRE_16, _mem_brjmp_uop_T_41 connect _mem_brjmp_uop_WIRE_4.fma, _mem_brjmp_uop_WIRE_16 node _mem_brjmp_uop_T_42 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_43 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_44 = or(_mem_brjmp_uop_T_42, _mem_brjmp_uop_T_43) wire _mem_brjmp_uop_WIRE_17 : UInt<1> connect _mem_brjmp_uop_WIRE_17, _mem_brjmp_uop_T_44 connect _mem_brjmp_uop_WIRE_4.fastpipe, _mem_brjmp_uop_WIRE_17 node _mem_brjmp_uop_T_45 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.toint, UInt<1>(0h0)) node _mem_brjmp_uop_T_46 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.toint, UInt<1>(0h0)) node _mem_brjmp_uop_T_47 = or(_mem_brjmp_uop_T_45, _mem_brjmp_uop_T_46) wire _mem_brjmp_uop_WIRE_18 : UInt<1> connect _mem_brjmp_uop_WIRE_18, _mem_brjmp_uop_T_47 connect _mem_brjmp_uop_WIRE_4.toint, _mem_brjmp_uop_WIRE_18 node _mem_brjmp_uop_T_48 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.fromint, UInt<1>(0h0)) node _mem_brjmp_uop_T_49 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.fromint, UInt<1>(0h0)) node _mem_brjmp_uop_T_50 = or(_mem_brjmp_uop_T_48, _mem_brjmp_uop_T_49) wire _mem_brjmp_uop_WIRE_19 : UInt<1> connect _mem_brjmp_uop_WIRE_19, _mem_brjmp_uop_T_50 connect _mem_brjmp_uop_WIRE_4.fromint, _mem_brjmp_uop_WIRE_19 node _mem_brjmp_uop_T_51 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _mem_brjmp_uop_T_52 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _mem_brjmp_uop_T_53 = or(_mem_brjmp_uop_T_51, _mem_brjmp_uop_T_52) wire _mem_brjmp_uop_WIRE_20 : UInt<2> connect _mem_brjmp_uop_WIRE_20, _mem_brjmp_uop_T_53 connect _mem_brjmp_uop_WIRE_4.typeTagOut, _mem_brjmp_uop_WIRE_20 node _mem_brjmp_uop_T_54 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _mem_brjmp_uop_T_55 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _mem_brjmp_uop_T_56 = or(_mem_brjmp_uop_T_54, _mem_brjmp_uop_T_55) wire _mem_brjmp_uop_WIRE_21 : UInt<2> connect _mem_brjmp_uop_WIRE_21, _mem_brjmp_uop_T_56 connect _mem_brjmp_uop_WIRE_4.typeTagIn, _mem_brjmp_uop_WIRE_21 node _mem_brjmp_uop_T_57 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.swap23, UInt<1>(0h0)) node _mem_brjmp_uop_T_58 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.swap23, UInt<1>(0h0)) node _mem_brjmp_uop_T_59 = or(_mem_brjmp_uop_T_57, _mem_brjmp_uop_T_58) wire _mem_brjmp_uop_WIRE_22 : UInt<1> connect _mem_brjmp_uop_WIRE_22, _mem_brjmp_uop_T_59 connect _mem_brjmp_uop_WIRE_4.swap23, _mem_brjmp_uop_WIRE_22 node _mem_brjmp_uop_T_60 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.swap12, UInt<1>(0h0)) node _mem_brjmp_uop_T_61 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.swap12, UInt<1>(0h0)) node _mem_brjmp_uop_T_62 = or(_mem_brjmp_uop_T_60, _mem_brjmp_uop_T_61) wire _mem_brjmp_uop_WIRE_23 : UInt<1> connect _mem_brjmp_uop_WIRE_23, _mem_brjmp_uop_T_62 connect _mem_brjmp_uop_WIRE_4.swap12, _mem_brjmp_uop_WIRE_23 node _mem_brjmp_uop_T_63 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.ren3, UInt<1>(0h0)) node _mem_brjmp_uop_T_64 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.ren3, UInt<1>(0h0)) node _mem_brjmp_uop_T_65 = or(_mem_brjmp_uop_T_63, _mem_brjmp_uop_T_64) wire _mem_brjmp_uop_WIRE_24 : UInt<1> connect _mem_brjmp_uop_WIRE_24, _mem_brjmp_uop_T_65 connect _mem_brjmp_uop_WIRE_4.ren3, _mem_brjmp_uop_WIRE_24 node _mem_brjmp_uop_T_66 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.ren2, UInt<1>(0h0)) node _mem_brjmp_uop_T_67 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.ren2, UInt<1>(0h0)) node _mem_brjmp_uop_T_68 = or(_mem_brjmp_uop_T_66, _mem_brjmp_uop_T_67) wire _mem_brjmp_uop_WIRE_25 : UInt<1> connect _mem_brjmp_uop_WIRE_25, _mem_brjmp_uop_T_68 connect _mem_brjmp_uop_WIRE_4.ren2, _mem_brjmp_uop_WIRE_25 node _mem_brjmp_uop_T_69 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.ren1, UInt<1>(0h0)) node _mem_brjmp_uop_T_70 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.ren1, UInt<1>(0h0)) node _mem_brjmp_uop_T_71 = or(_mem_brjmp_uop_T_69, _mem_brjmp_uop_T_70) wire _mem_brjmp_uop_WIRE_26 : UInt<1> connect _mem_brjmp_uop_WIRE_26, _mem_brjmp_uop_T_71 connect _mem_brjmp_uop_WIRE_4.ren1, _mem_brjmp_uop_WIRE_26 node _mem_brjmp_uop_T_72 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.wen, UInt<1>(0h0)) node _mem_brjmp_uop_T_73 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.wen, UInt<1>(0h0)) node _mem_brjmp_uop_T_74 = or(_mem_brjmp_uop_T_72, _mem_brjmp_uop_T_73) wire _mem_brjmp_uop_WIRE_27 : UInt<1> connect _mem_brjmp_uop_WIRE_27, _mem_brjmp_uop_T_74 connect _mem_brjmp_uop_WIRE_4.wen, _mem_brjmp_uop_WIRE_27 node _mem_brjmp_uop_T_75 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fdivin.ldst, UInt<1>(0h0)) node _mem_brjmp_uop_T_76 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fdivin.ldst, UInt<1>(0h0)) node _mem_brjmp_uop_T_77 = or(_mem_brjmp_uop_T_75, _mem_brjmp_uop_T_76) wire _mem_brjmp_uop_WIRE_28 : UInt<1> connect _mem_brjmp_uop_WIRE_28, _mem_brjmp_uop_T_77 connect _mem_brjmp_uop_WIRE_4.ldst, _mem_brjmp_uop_WIRE_28 connect _mem_brjmp_uop_WIRE_1.fdivin, _mem_brjmp_uop_WIRE_4 node _mem_brjmp_uop_T_78 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fexc, UInt<1>(0h0)) node _mem_brjmp_uop_T_79 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fexc, UInt<1>(0h0)) node _mem_brjmp_uop_T_80 = or(_mem_brjmp_uop_T_78, _mem_brjmp_uop_T_79) wire _mem_brjmp_uop_WIRE_29 : UInt<5> connect _mem_brjmp_uop_WIRE_29, _mem_brjmp_uop_T_80 connect _mem_brjmp_uop_WIRE_1.fexc, _mem_brjmp_uop_WIRE_29 node _mem_brjmp_uop_T_81 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fra3, UInt<1>(0h0)) node _mem_brjmp_uop_T_82 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fra3, UInt<1>(0h0)) node _mem_brjmp_uop_T_83 = or(_mem_brjmp_uop_T_81, _mem_brjmp_uop_T_82) wire _mem_brjmp_uop_WIRE_30 : UInt<5> connect _mem_brjmp_uop_WIRE_30, _mem_brjmp_uop_T_83 connect _mem_brjmp_uop_WIRE_1.fra3, _mem_brjmp_uop_WIRE_30 node _mem_brjmp_uop_T_84 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fra2, UInt<1>(0h0)) node _mem_brjmp_uop_T_85 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fra2, UInt<1>(0h0)) node _mem_brjmp_uop_T_86 = or(_mem_brjmp_uop_T_84, _mem_brjmp_uop_T_85) wire _mem_brjmp_uop_WIRE_31 : UInt<5> connect _mem_brjmp_uop_WIRE_31, _mem_brjmp_uop_T_86 connect _mem_brjmp_uop_WIRE_1.fra2, _mem_brjmp_uop_WIRE_31 node _mem_brjmp_uop_T_87 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fra1, UInt<1>(0h0)) node _mem_brjmp_uop_T_88 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fra1, UInt<1>(0h0)) node _mem_brjmp_uop_T_89 = or(_mem_brjmp_uop_T_87, _mem_brjmp_uop_T_88) wire _mem_brjmp_uop_WIRE_32 : UInt<5> connect _mem_brjmp_uop_WIRE_32, _mem_brjmp_uop_T_89 connect _mem_brjmp_uop_WIRE_1.fra1, _mem_brjmp_uop_WIRE_32 wire _mem_brjmp_uop_WIRE_33 : { valid : UInt<1>, bits : UInt<64>} node _mem_brjmp_uop_T_90 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.wdata.bits, UInt<1>(0h0)) node _mem_brjmp_uop_T_91 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.wdata.bits, UInt<1>(0h0)) node _mem_brjmp_uop_T_92 = or(_mem_brjmp_uop_T_90, _mem_brjmp_uop_T_91) wire _mem_brjmp_uop_WIRE_34 : UInt<64> connect _mem_brjmp_uop_WIRE_34, _mem_brjmp_uop_T_92 connect _mem_brjmp_uop_WIRE_33.bits, _mem_brjmp_uop_WIRE_34 node _mem_brjmp_uop_T_93 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.wdata.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_94 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.wdata.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_95 = or(_mem_brjmp_uop_T_93, _mem_brjmp_uop_T_94) wire _mem_brjmp_uop_WIRE_35 : UInt<1> connect _mem_brjmp_uop_WIRE_35, _mem_brjmp_uop_T_95 connect _mem_brjmp_uop_WIRE_33.valid, _mem_brjmp_uop_WIRE_35 connect _mem_brjmp_uop_WIRE_1.wdata, _mem_brjmp_uop_WIRE_33 node _mem_brjmp_uop_T_96 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _mem_brjmp_uop_T_97 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _mem_brjmp_uop_T_98 = or(_mem_brjmp_uop_T_96, _mem_brjmp_uop_T_97) wire _mem_brjmp_uop_WIRE_36 : UInt<1> connect _mem_brjmp_uop_WIRE_36, _mem_brjmp_uop_T_98 connect _mem_brjmp_uop_WIRE_1.uses_latealu, _mem_brjmp_uop_WIRE_36 node _mem_brjmp_uop_T_99 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _mem_brjmp_uop_T_100 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _mem_brjmp_uop_T_101 = or(_mem_brjmp_uop_T_99, _mem_brjmp_uop_T_100) wire _mem_brjmp_uop_WIRE_37 : UInt<1> connect _mem_brjmp_uop_WIRE_37, _mem_brjmp_uop_T_101 connect _mem_brjmp_uop_WIRE_1.uses_memalu, _mem_brjmp_uop_WIRE_37 node _mem_brjmp_uop_T_102 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.rs3_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_103 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.rs3_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_104 = or(_mem_brjmp_uop_T_102, _mem_brjmp_uop_T_103) wire _mem_brjmp_uop_WIRE_38 : UInt<64> connect _mem_brjmp_uop_WIRE_38, _mem_brjmp_uop_T_104 connect _mem_brjmp_uop_WIRE_1.rs3_data, _mem_brjmp_uop_WIRE_38 node _mem_brjmp_uop_T_105 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.rs2_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_106 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.rs2_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_107 = or(_mem_brjmp_uop_T_105, _mem_brjmp_uop_T_106) wire _mem_brjmp_uop_WIRE_39 : UInt<64> connect _mem_brjmp_uop_WIRE_39, _mem_brjmp_uop_T_107 connect _mem_brjmp_uop_WIRE_1.rs2_data, _mem_brjmp_uop_WIRE_39 node _mem_brjmp_uop_T_108 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.rs1_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_109 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.rs1_data, UInt<1>(0h0)) node _mem_brjmp_uop_T_110 = or(_mem_brjmp_uop_T_108, _mem_brjmp_uop_T_109) wire _mem_brjmp_uop_WIRE_40 : UInt<64> connect _mem_brjmp_uop_WIRE_40, _mem_brjmp_uop_T_110 connect _mem_brjmp_uop_WIRE_1.rs1_data, _mem_brjmp_uop_WIRE_40 node _mem_brjmp_uop_T_111 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.needs_replay, UInt<1>(0h0)) node _mem_brjmp_uop_T_112 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.needs_replay, UInt<1>(0h0)) node _mem_brjmp_uop_T_113 = or(_mem_brjmp_uop_T_111, _mem_brjmp_uop_T_112) wire _mem_brjmp_uop_WIRE_41 : UInt<1> connect _mem_brjmp_uop_WIRE_41, _mem_brjmp_uop_T_113 connect _mem_brjmp_uop_WIRE_1.needs_replay, _mem_brjmp_uop_WIRE_41 node _mem_brjmp_uop_T_114 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.xcpt_cause, UInt<1>(0h0)) node _mem_brjmp_uop_T_115 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.xcpt_cause, UInt<1>(0h0)) node _mem_brjmp_uop_T_116 = or(_mem_brjmp_uop_T_114, _mem_brjmp_uop_T_115) wire _mem_brjmp_uop_WIRE_42 : UInt<64> connect _mem_brjmp_uop_WIRE_42, _mem_brjmp_uop_T_116 connect _mem_brjmp_uop_WIRE_1.xcpt_cause, _mem_brjmp_uop_WIRE_42 node _mem_brjmp_uop_T_117 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _mem_brjmp_uop_T_118 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.xcpt, UInt<1>(0h0)) node _mem_brjmp_uop_T_119 = or(_mem_brjmp_uop_T_117, _mem_brjmp_uop_T_118) wire _mem_brjmp_uop_WIRE_43 : UInt<1> connect _mem_brjmp_uop_WIRE_43, _mem_brjmp_uop_T_119 connect _mem_brjmp_uop_WIRE_1.xcpt, _mem_brjmp_uop_WIRE_43 node _mem_brjmp_uop_T_120 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.taken, UInt<1>(0h0)) node _mem_brjmp_uop_T_121 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.taken, UInt<1>(0h0)) node _mem_brjmp_uop_T_122 = or(_mem_brjmp_uop_T_120, _mem_brjmp_uop_T_121) wire _mem_brjmp_uop_WIRE_44 : UInt<1> connect _mem_brjmp_uop_WIRE_44, _mem_brjmp_uop_T_122 connect _mem_brjmp_uop_WIRE_1.taken, _mem_brjmp_uop_WIRE_44 node _mem_brjmp_uop_T_123 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ras_head, UInt<1>(0h0)) node _mem_brjmp_uop_T_124 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ras_head, UInt<1>(0h0)) node _mem_brjmp_uop_T_125 = or(_mem_brjmp_uop_T_123, _mem_brjmp_uop_T_124) wire _mem_brjmp_uop_WIRE_45 : UInt<3> connect _mem_brjmp_uop_WIRE_45, _mem_brjmp_uop_T_125 connect _mem_brjmp_uop_WIRE_1.ras_head, _mem_brjmp_uop_WIRE_45 wire _mem_brjmp_uop_WIRE_46 : { valid : UInt<1>, bits : UInt<40>} node _mem_brjmp_uop_T_126 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.next_pc.bits, UInt<1>(0h0)) node _mem_brjmp_uop_T_127 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.next_pc.bits, UInt<1>(0h0)) node _mem_brjmp_uop_T_128 = or(_mem_brjmp_uop_T_126, _mem_brjmp_uop_T_127) wire _mem_brjmp_uop_WIRE_47 : UInt<40> connect _mem_brjmp_uop_WIRE_47, _mem_brjmp_uop_T_128 connect _mem_brjmp_uop_WIRE_46.bits, _mem_brjmp_uop_WIRE_47 node _mem_brjmp_uop_T_129 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.next_pc.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_130 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.next_pc.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_131 = or(_mem_brjmp_uop_T_129, _mem_brjmp_uop_T_130) wire _mem_brjmp_uop_WIRE_48 : UInt<1> connect _mem_brjmp_uop_WIRE_48, _mem_brjmp_uop_T_131 connect _mem_brjmp_uop_WIRE_46.valid, _mem_brjmp_uop_WIRE_48 connect _mem_brjmp_uop_WIRE_1.next_pc, _mem_brjmp_uop_WIRE_46 node _mem_brjmp_uop_T_132 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.sfb_shadow, UInt<1>(0h0)) node _mem_brjmp_uop_T_133 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _mem_brjmp_uop_T_134 = or(_mem_brjmp_uop_T_132, _mem_brjmp_uop_T_133) wire _mem_brjmp_uop_WIRE_49 : UInt<1> connect _mem_brjmp_uop_WIRE_49, _mem_brjmp_uop_T_134 connect _mem_brjmp_uop_WIRE_1.sfb_shadow, _mem_brjmp_uop_WIRE_49 node _mem_brjmp_uop_T_135 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.sfb_br, UInt<1>(0h0)) node _mem_brjmp_uop_T_136 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.sfb_br, UInt<1>(0h0)) node _mem_brjmp_uop_T_137 = or(_mem_brjmp_uop_T_135, _mem_brjmp_uop_T_136) wire _mem_brjmp_uop_WIRE_50 : UInt<1> connect _mem_brjmp_uop_WIRE_50, _mem_brjmp_uop_T_137 connect _mem_brjmp_uop_WIRE_1.sfb_br, _mem_brjmp_uop_WIRE_50 wire _mem_brjmp_uop_WIRE_51 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _mem_brjmp_uop_WIRE_52 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _mem_brjmp_uop_WIRE_53 : { history : UInt<8>, value : UInt<2>} node _mem_brjmp_uop_T_138 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _mem_brjmp_uop_T_139 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _mem_brjmp_uop_T_140 = or(_mem_brjmp_uop_T_138, _mem_brjmp_uop_T_139) wire _mem_brjmp_uop_WIRE_54 : UInt<2> connect _mem_brjmp_uop_WIRE_54, _mem_brjmp_uop_T_140 connect _mem_brjmp_uop_WIRE_53.value, _mem_brjmp_uop_WIRE_54 node _mem_brjmp_uop_T_141 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _mem_brjmp_uop_T_142 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _mem_brjmp_uop_T_143 = or(_mem_brjmp_uop_T_141, _mem_brjmp_uop_T_142) wire _mem_brjmp_uop_WIRE_55 : UInt<8> connect _mem_brjmp_uop_WIRE_55, _mem_brjmp_uop_T_143 connect _mem_brjmp_uop_WIRE_53.history, _mem_brjmp_uop_WIRE_55 connect _mem_brjmp_uop_WIRE_52.bht, _mem_brjmp_uop_WIRE_53 node _mem_brjmp_uop_T_144 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _mem_brjmp_uop_T_145 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _mem_brjmp_uop_T_146 = or(_mem_brjmp_uop_T_144, _mem_brjmp_uop_T_145) wire _mem_brjmp_uop_WIRE_56 : UInt<6> connect _mem_brjmp_uop_WIRE_56, _mem_brjmp_uop_T_146 connect _mem_brjmp_uop_WIRE_52.entry, _mem_brjmp_uop_WIRE_56 node _mem_brjmp_uop_T_147 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _mem_brjmp_uop_T_148 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _mem_brjmp_uop_T_149 = or(_mem_brjmp_uop_T_147, _mem_brjmp_uop_T_148) wire _mem_brjmp_uop_WIRE_57 : UInt<39> connect _mem_brjmp_uop_WIRE_57, _mem_brjmp_uop_T_149 connect _mem_brjmp_uop_WIRE_52.target, _mem_brjmp_uop_WIRE_57 node _mem_brjmp_uop_T_150 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _mem_brjmp_uop_T_151 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _mem_brjmp_uop_T_152 = or(_mem_brjmp_uop_T_150, _mem_brjmp_uop_T_151) wire _mem_brjmp_uop_WIRE_58 : UInt<2> connect _mem_brjmp_uop_WIRE_58, _mem_brjmp_uop_T_152 connect _mem_brjmp_uop_WIRE_52.bridx, _mem_brjmp_uop_WIRE_58 node _mem_brjmp_uop_T_153 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _mem_brjmp_uop_T_154 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _mem_brjmp_uop_T_155 = or(_mem_brjmp_uop_T_153, _mem_brjmp_uop_T_154) wire _mem_brjmp_uop_WIRE_59 : UInt<4> connect _mem_brjmp_uop_WIRE_59, _mem_brjmp_uop_T_155 connect _mem_brjmp_uop_WIRE_52.mask, _mem_brjmp_uop_WIRE_59 node _mem_brjmp_uop_T_156 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _mem_brjmp_uop_T_157 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _mem_brjmp_uop_T_158 = or(_mem_brjmp_uop_T_156, _mem_brjmp_uop_T_157) wire _mem_brjmp_uop_WIRE_60 : UInt<1> connect _mem_brjmp_uop_WIRE_60, _mem_brjmp_uop_T_158 connect _mem_brjmp_uop_WIRE_52.taken, _mem_brjmp_uop_WIRE_60 node _mem_brjmp_uop_T_159 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _mem_brjmp_uop_T_160 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _mem_brjmp_uop_T_161 = or(_mem_brjmp_uop_T_159, _mem_brjmp_uop_T_160) wire _mem_brjmp_uop_WIRE_61 : UInt<2> connect _mem_brjmp_uop_WIRE_61, _mem_brjmp_uop_T_161 connect _mem_brjmp_uop_WIRE_52.cfiType, _mem_brjmp_uop_WIRE_61 connect _mem_brjmp_uop_WIRE_51.bits, _mem_brjmp_uop_WIRE_52 node _mem_brjmp_uop_T_162 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.btb_resp.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_163 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.btb_resp.valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_164 = or(_mem_brjmp_uop_T_162, _mem_brjmp_uop_T_163) wire _mem_brjmp_uop_WIRE_62 : UInt<1> connect _mem_brjmp_uop_WIRE_62, _mem_brjmp_uop_T_164 connect _mem_brjmp_uop_WIRE_51.valid, _mem_brjmp_uop_WIRE_62 connect _mem_brjmp_uop_WIRE_1.btb_resp, _mem_brjmp_uop_WIRE_51 node _mem_brjmp_uop_T_165 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.sets_vcfg, UInt<1>(0h0)) node _mem_brjmp_uop_T_166 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.sets_vcfg, UInt<1>(0h0)) node _mem_brjmp_uop_T_167 = or(_mem_brjmp_uop_T_165, _mem_brjmp_uop_T_166) wire _mem_brjmp_uop_WIRE_63 : UInt<1> connect _mem_brjmp_uop_WIRE_63, _mem_brjmp_uop_T_167 connect _mem_brjmp_uop_WIRE_1.sets_vcfg, _mem_brjmp_uop_WIRE_63 node _mem_brjmp_uop_T_168 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.rvc, UInt<1>(0h0)) node _mem_brjmp_uop_T_169 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.rvc, UInt<1>(0h0)) node _mem_brjmp_uop_T_170 = or(_mem_brjmp_uop_T_168, _mem_brjmp_uop_T_169) wire _mem_brjmp_uop_WIRE_64 : UInt<1> connect _mem_brjmp_uop_WIRE_64, _mem_brjmp_uop_T_170 connect _mem_brjmp_uop_WIRE_1.rvc, _mem_brjmp_uop_WIRE_64 wire _mem_brjmp_uop_WIRE_65 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _mem_brjmp_uop_T_171 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_172 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_173 = or(_mem_brjmp_uop_T_171, _mem_brjmp_uop_T_172) wire _mem_brjmp_uop_WIRE_66 : UInt<1> connect _mem_brjmp_uop_WIRE_66, _mem_brjmp_uop_T_173 connect _mem_brjmp_uop_WIRE_65.vec, _mem_brjmp_uop_WIRE_66 node _mem_brjmp_uop_T_174 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _mem_brjmp_uop_T_175 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _mem_brjmp_uop_T_176 = or(_mem_brjmp_uop_T_174, _mem_brjmp_uop_T_175) wire _mem_brjmp_uop_WIRE_67 : UInt<1> connect _mem_brjmp_uop_WIRE_67, _mem_brjmp_uop_T_176 connect _mem_brjmp_uop_WIRE_65.wflags, _mem_brjmp_uop_WIRE_67 node _mem_brjmp_uop_T_177 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _mem_brjmp_uop_T_178 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _mem_brjmp_uop_T_179 = or(_mem_brjmp_uop_T_177, _mem_brjmp_uop_T_178) wire _mem_brjmp_uop_WIRE_68 : UInt<1> connect _mem_brjmp_uop_WIRE_68, _mem_brjmp_uop_T_179 connect _mem_brjmp_uop_WIRE_65.sqrt, _mem_brjmp_uop_WIRE_68 node _mem_brjmp_uop_T_180 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_181 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_182 = or(_mem_brjmp_uop_T_180, _mem_brjmp_uop_T_181) wire _mem_brjmp_uop_WIRE_69 : UInt<1> connect _mem_brjmp_uop_WIRE_69, _mem_brjmp_uop_T_182 connect _mem_brjmp_uop_WIRE_65.div, _mem_brjmp_uop_WIRE_69 node _mem_brjmp_uop_T_183 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _mem_brjmp_uop_T_184 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _mem_brjmp_uop_T_185 = or(_mem_brjmp_uop_T_183, _mem_brjmp_uop_T_184) wire _mem_brjmp_uop_WIRE_70 : UInt<1> connect _mem_brjmp_uop_WIRE_70, _mem_brjmp_uop_T_185 connect _mem_brjmp_uop_WIRE_65.fma, _mem_brjmp_uop_WIRE_70 node _mem_brjmp_uop_T_186 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_187 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _mem_brjmp_uop_T_188 = or(_mem_brjmp_uop_T_186, _mem_brjmp_uop_T_187) wire _mem_brjmp_uop_WIRE_71 : UInt<1> connect _mem_brjmp_uop_WIRE_71, _mem_brjmp_uop_T_188 connect _mem_brjmp_uop_WIRE_65.fastpipe, _mem_brjmp_uop_WIRE_71 node _mem_brjmp_uop_T_189 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _mem_brjmp_uop_T_190 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _mem_brjmp_uop_T_191 = or(_mem_brjmp_uop_T_189, _mem_brjmp_uop_T_190) wire _mem_brjmp_uop_WIRE_72 : UInt<1> connect _mem_brjmp_uop_WIRE_72, _mem_brjmp_uop_T_191 connect _mem_brjmp_uop_WIRE_65.toint, _mem_brjmp_uop_WIRE_72 node _mem_brjmp_uop_T_192 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _mem_brjmp_uop_T_193 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _mem_brjmp_uop_T_194 = or(_mem_brjmp_uop_T_192, _mem_brjmp_uop_T_193) wire _mem_brjmp_uop_WIRE_73 : UInt<1> connect _mem_brjmp_uop_WIRE_73, _mem_brjmp_uop_T_194 connect _mem_brjmp_uop_WIRE_65.fromint, _mem_brjmp_uop_WIRE_73 node _mem_brjmp_uop_T_195 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _mem_brjmp_uop_T_196 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _mem_brjmp_uop_T_197 = or(_mem_brjmp_uop_T_195, _mem_brjmp_uop_T_196) wire _mem_brjmp_uop_WIRE_74 : UInt<2> connect _mem_brjmp_uop_WIRE_74, _mem_brjmp_uop_T_197 connect _mem_brjmp_uop_WIRE_65.typeTagOut, _mem_brjmp_uop_WIRE_74 node _mem_brjmp_uop_T_198 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _mem_brjmp_uop_T_199 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _mem_brjmp_uop_T_200 = or(_mem_brjmp_uop_T_198, _mem_brjmp_uop_T_199) wire _mem_brjmp_uop_WIRE_75 : UInt<2> connect _mem_brjmp_uop_WIRE_75, _mem_brjmp_uop_T_200 connect _mem_brjmp_uop_WIRE_65.typeTagIn, _mem_brjmp_uop_WIRE_75 node _mem_brjmp_uop_T_201 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _mem_brjmp_uop_T_202 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _mem_brjmp_uop_T_203 = or(_mem_brjmp_uop_T_201, _mem_brjmp_uop_T_202) wire _mem_brjmp_uop_WIRE_76 : UInt<1> connect _mem_brjmp_uop_WIRE_76, _mem_brjmp_uop_T_203 connect _mem_brjmp_uop_WIRE_65.swap23, _mem_brjmp_uop_WIRE_76 node _mem_brjmp_uop_T_204 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _mem_brjmp_uop_T_205 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _mem_brjmp_uop_T_206 = or(_mem_brjmp_uop_T_204, _mem_brjmp_uop_T_205) wire _mem_brjmp_uop_WIRE_77 : UInt<1> connect _mem_brjmp_uop_WIRE_77, _mem_brjmp_uop_T_206 connect _mem_brjmp_uop_WIRE_65.swap12, _mem_brjmp_uop_WIRE_77 node _mem_brjmp_uop_T_207 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _mem_brjmp_uop_T_208 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _mem_brjmp_uop_T_209 = or(_mem_brjmp_uop_T_207, _mem_brjmp_uop_T_208) wire _mem_brjmp_uop_WIRE_78 : UInt<1> connect _mem_brjmp_uop_WIRE_78, _mem_brjmp_uop_T_209 connect _mem_brjmp_uop_WIRE_65.ren3, _mem_brjmp_uop_WIRE_78 node _mem_brjmp_uop_T_210 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _mem_brjmp_uop_T_211 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _mem_brjmp_uop_T_212 = or(_mem_brjmp_uop_T_210, _mem_brjmp_uop_T_211) wire _mem_brjmp_uop_WIRE_79 : UInt<1> connect _mem_brjmp_uop_WIRE_79, _mem_brjmp_uop_T_212 connect _mem_brjmp_uop_WIRE_65.ren2, _mem_brjmp_uop_WIRE_79 node _mem_brjmp_uop_T_213 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _mem_brjmp_uop_T_214 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _mem_brjmp_uop_T_215 = or(_mem_brjmp_uop_T_213, _mem_brjmp_uop_T_214) wire _mem_brjmp_uop_WIRE_80 : UInt<1> connect _mem_brjmp_uop_WIRE_80, _mem_brjmp_uop_T_215 connect _mem_brjmp_uop_WIRE_65.ren1, _mem_brjmp_uop_WIRE_80 node _mem_brjmp_uop_T_216 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _mem_brjmp_uop_T_217 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _mem_brjmp_uop_T_218 = or(_mem_brjmp_uop_T_216, _mem_brjmp_uop_T_217) wire _mem_brjmp_uop_WIRE_81 : UInt<1> connect _mem_brjmp_uop_WIRE_81, _mem_brjmp_uop_T_218 connect _mem_brjmp_uop_WIRE_65.wen, _mem_brjmp_uop_WIRE_81 node _mem_brjmp_uop_T_219 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _mem_brjmp_uop_T_220 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _mem_brjmp_uop_T_221 = or(_mem_brjmp_uop_T_219, _mem_brjmp_uop_T_220) wire _mem_brjmp_uop_WIRE_82 : UInt<1> connect _mem_brjmp_uop_WIRE_82, _mem_brjmp_uop_T_221 connect _mem_brjmp_uop_WIRE_65.ldst, _mem_brjmp_uop_WIRE_82 connect _mem_brjmp_uop_WIRE_1.fp_ctrl, _mem_brjmp_uop_WIRE_65 wire _mem_brjmp_uop_WIRE_83 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _mem_brjmp_uop_T_222 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_223 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _mem_brjmp_uop_T_224 = or(_mem_brjmp_uop_T_222, _mem_brjmp_uop_T_223) wire _mem_brjmp_uop_WIRE_84 : UInt<1> connect _mem_brjmp_uop_WIRE_84, _mem_brjmp_uop_T_224 connect _mem_brjmp_uop_WIRE_83.vec, _mem_brjmp_uop_WIRE_84 node _mem_brjmp_uop_T_225 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.dp, UInt<1>(0h0)) node _mem_brjmp_uop_T_226 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.dp, UInt<1>(0h0)) node _mem_brjmp_uop_T_227 = or(_mem_brjmp_uop_T_225, _mem_brjmp_uop_T_226) wire _mem_brjmp_uop_WIRE_85 : UInt<1> connect _mem_brjmp_uop_WIRE_85, _mem_brjmp_uop_T_227 connect _mem_brjmp_uop_WIRE_83.dp, _mem_brjmp_uop_WIRE_85 node _mem_brjmp_uop_T_228 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.amo, UInt<1>(0h0)) node _mem_brjmp_uop_T_229 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.amo, UInt<1>(0h0)) node _mem_brjmp_uop_T_230 = or(_mem_brjmp_uop_T_228, _mem_brjmp_uop_T_229) wire _mem_brjmp_uop_WIRE_86 : UInt<1> connect _mem_brjmp_uop_WIRE_86, _mem_brjmp_uop_T_230 connect _mem_brjmp_uop_WIRE_83.amo, _mem_brjmp_uop_WIRE_86 node _mem_brjmp_uop_T_231 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.fence, UInt<1>(0h0)) node _mem_brjmp_uop_T_232 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.fence, UInt<1>(0h0)) node _mem_brjmp_uop_T_233 = or(_mem_brjmp_uop_T_231, _mem_brjmp_uop_T_232) wire _mem_brjmp_uop_WIRE_87 : UInt<1> connect _mem_brjmp_uop_WIRE_87, _mem_brjmp_uop_T_233 connect _mem_brjmp_uop_WIRE_83.fence, _mem_brjmp_uop_WIRE_87 node _mem_brjmp_uop_T_234 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _mem_brjmp_uop_T_235 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _mem_brjmp_uop_T_236 = or(_mem_brjmp_uop_T_234, _mem_brjmp_uop_T_235) wire _mem_brjmp_uop_WIRE_88 : UInt<1> connect _mem_brjmp_uop_WIRE_88, _mem_brjmp_uop_T_236 connect _mem_brjmp_uop_WIRE_83.fence_i, _mem_brjmp_uop_WIRE_88 node _mem_brjmp_uop_T_237 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.csr, UInt<1>(0h0)) node _mem_brjmp_uop_T_238 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.csr, UInt<1>(0h0)) node _mem_brjmp_uop_T_239 = or(_mem_brjmp_uop_T_237, _mem_brjmp_uop_T_238) wire _mem_brjmp_uop_WIRE_89 : UInt<3> connect _mem_brjmp_uop_WIRE_89, _mem_brjmp_uop_T_239 connect _mem_brjmp_uop_WIRE_83.csr, _mem_brjmp_uop_WIRE_89 node _mem_brjmp_uop_T_240 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.wxd, UInt<1>(0h0)) node _mem_brjmp_uop_T_241 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.wxd, UInt<1>(0h0)) node _mem_brjmp_uop_T_242 = or(_mem_brjmp_uop_T_240, _mem_brjmp_uop_T_241) wire _mem_brjmp_uop_WIRE_90 : UInt<1> connect _mem_brjmp_uop_WIRE_90, _mem_brjmp_uop_T_242 connect _mem_brjmp_uop_WIRE_83.wxd, _mem_brjmp_uop_WIRE_90 node _mem_brjmp_uop_T_243 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_244 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _mem_brjmp_uop_T_245 = or(_mem_brjmp_uop_T_243, _mem_brjmp_uop_T_244) wire _mem_brjmp_uop_WIRE_91 : UInt<1> connect _mem_brjmp_uop_WIRE_91, _mem_brjmp_uop_T_245 connect _mem_brjmp_uop_WIRE_83.div, _mem_brjmp_uop_WIRE_91 node _mem_brjmp_uop_T_246 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _mem_brjmp_uop_T_247 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _mem_brjmp_uop_T_248 = or(_mem_brjmp_uop_T_246, _mem_brjmp_uop_T_247) wire _mem_brjmp_uop_WIRE_92 : UInt<1> connect _mem_brjmp_uop_WIRE_92, _mem_brjmp_uop_T_248 connect _mem_brjmp_uop_WIRE_83.mul, _mem_brjmp_uop_WIRE_92 node _mem_brjmp_uop_T_249 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.wfd, UInt<1>(0h0)) node _mem_brjmp_uop_T_250 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.wfd, UInt<1>(0h0)) node _mem_brjmp_uop_T_251 = or(_mem_brjmp_uop_T_249, _mem_brjmp_uop_T_250) wire _mem_brjmp_uop_WIRE_93 : UInt<1> connect _mem_brjmp_uop_WIRE_93, _mem_brjmp_uop_T_251 connect _mem_brjmp_uop_WIRE_83.wfd, _mem_brjmp_uop_WIRE_93 node _mem_brjmp_uop_T_252 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _mem_brjmp_uop_T_253 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _mem_brjmp_uop_T_254 = or(_mem_brjmp_uop_T_252, _mem_brjmp_uop_T_253) wire _mem_brjmp_uop_WIRE_94 : UInt<1> connect _mem_brjmp_uop_WIRE_94, _mem_brjmp_uop_T_254 connect _mem_brjmp_uop_WIRE_83.rfs3, _mem_brjmp_uop_WIRE_94 node _mem_brjmp_uop_T_255 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _mem_brjmp_uop_T_256 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _mem_brjmp_uop_T_257 = or(_mem_brjmp_uop_T_255, _mem_brjmp_uop_T_256) wire _mem_brjmp_uop_WIRE_95 : UInt<1> connect _mem_brjmp_uop_WIRE_95, _mem_brjmp_uop_T_257 connect _mem_brjmp_uop_WIRE_83.rfs2, _mem_brjmp_uop_WIRE_95 node _mem_brjmp_uop_T_258 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _mem_brjmp_uop_T_259 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _mem_brjmp_uop_T_260 = or(_mem_brjmp_uop_T_258, _mem_brjmp_uop_T_259) wire _mem_brjmp_uop_WIRE_96 : UInt<1> connect _mem_brjmp_uop_WIRE_96, _mem_brjmp_uop_T_260 connect _mem_brjmp_uop_WIRE_83.rfs1, _mem_brjmp_uop_WIRE_96 node _mem_brjmp_uop_T_261 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _mem_brjmp_uop_T_262 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _mem_brjmp_uop_T_263 = or(_mem_brjmp_uop_T_261, _mem_brjmp_uop_T_262) wire _mem_brjmp_uop_WIRE_97 : UInt<5> connect _mem_brjmp_uop_WIRE_97, _mem_brjmp_uop_T_263 connect _mem_brjmp_uop_WIRE_83.mem_cmd, _mem_brjmp_uop_WIRE_97 node _mem_brjmp_uop_T_264 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _mem_brjmp_uop_T_265 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _mem_brjmp_uop_T_266 = or(_mem_brjmp_uop_T_264, _mem_brjmp_uop_T_265) wire _mem_brjmp_uop_WIRE_98 : UInt<1> connect _mem_brjmp_uop_WIRE_98, _mem_brjmp_uop_T_266 connect _mem_brjmp_uop_WIRE_83.mem, _mem_brjmp_uop_WIRE_98 node _mem_brjmp_uop_T_267 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _mem_brjmp_uop_T_268 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _mem_brjmp_uop_T_269 = or(_mem_brjmp_uop_T_267, _mem_brjmp_uop_T_268) wire _mem_brjmp_uop_WIRE_99 : UInt<5> connect _mem_brjmp_uop_WIRE_99, _mem_brjmp_uop_T_269 connect _mem_brjmp_uop_WIRE_83.alu_fn, _mem_brjmp_uop_WIRE_99 node _mem_brjmp_uop_T_270 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _mem_brjmp_uop_T_271 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _mem_brjmp_uop_T_272 = or(_mem_brjmp_uop_T_270, _mem_brjmp_uop_T_271) wire _mem_brjmp_uop_WIRE_100 : UInt<1> connect _mem_brjmp_uop_WIRE_100, _mem_brjmp_uop_T_272 connect _mem_brjmp_uop_WIRE_83.alu_dw, _mem_brjmp_uop_WIRE_100 node _mem_brjmp_uop_T_273 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _mem_brjmp_uop_T_274 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _mem_brjmp_uop_T_275 = or(_mem_brjmp_uop_T_273, _mem_brjmp_uop_T_274) wire _mem_brjmp_uop_WIRE_101 : UInt<3> connect _mem_brjmp_uop_WIRE_101, _mem_brjmp_uop_T_275 connect _mem_brjmp_uop_WIRE_83.sel_imm, _mem_brjmp_uop_WIRE_101 node _mem_brjmp_uop_T_276 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _mem_brjmp_uop_T_277 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _mem_brjmp_uop_T_278 = or(_mem_brjmp_uop_T_276, _mem_brjmp_uop_T_277) wire _mem_brjmp_uop_WIRE_102 : UInt<2> connect _mem_brjmp_uop_WIRE_102, _mem_brjmp_uop_T_278 connect _mem_brjmp_uop_WIRE_83.sel_alu1, _mem_brjmp_uop_WIRE_102 node _mem_brjmp_uop_T_279 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _mem_brjmp_uop_T_280 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _mem_brjmp_uop_T_281 = or(_mem_brjmp_uop_T_279, _mem_brjmp_uop_T_280) wire _mem_brjmp_uop_WIRE_103 : UInt<3> connect _mem_brjmp_uop_WIRE_103, _mem_brjmp_uop_T_281 connect _mem_brjmp_uop_WIRE_83.sel_alu2, _mem_brjmp_uop_WIRE_103 node _mem_brjmp_uop_T_282 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _mem_brjmp_uop_T_283 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _mem_brjmp_uop_T_284 = or(_mem_brjmp_uop_T_282, _mem_brjmp_uop_T_283) wire _mem_brjmp_uop_WIRE_104 : UInt<1> connect _mem_brjmp_uop_WIRE_104, _mem_brjmp_uop_T_284 connect _mem_brjmp_uop_WIRE_83.rxs1, _mem_brjmp_uop_WIRE_104 node _mem_brjmp_uop_T_285 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _mem_brjmp_uop_T_286 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _mem_brjmp_uop_T_287 = or(_mem_brjmp_uop_T_285, _mem_brjmp_uop_T_286) wire _mem_brjmp_uop_WIRE_105 : UInt<1> connect _mem_brjmp_uop_WIRE_105, _mem_brjmp_uop_T_287 connect _mem_brjmp_uop_WIRE_83.rxs2, _mem_brjmp_uop_WIRE_105 node _mem_brjmp_uop_T_288 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_brjmp_uop_T_289 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_brjmp_uop_T_290 = or(_mem_brjmp_uop_T_288, _mem_brjmp_uop_T_289) wire _mem_brjmp_uop_WIRE_106 : UInt<1> connect _mem_brjmp_uop_WIRE_106, _mem_brjmp_uop_T_290 connect _mem_brjmp_uop_WIRE_83.jalr, _mem_brjmp_uop_WIRE_106 node _mem_brjmp_uop_T_291 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.jal, UInt<1>(0h0)) node _mem_brjmp_uop_T_292 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.jal, UInt<1>(0h0)) node _mem_brjmp_uop_T_293 = or(_mem_brjmp_uop_T_291, _mem_brjmp_uop_T_292) wire _mem_brjmp_uop_WIRE_107 : UInt<1> connect _mem_brjmp_uop_WIRE_107, _mem_brjmp_uop_T_293 connect _mem_brjmp_uop_WIRE_83.jal, _mem_brjmp_uop_WIRE_107 node _mem_brjmp_uop_T_294 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.branch, UInt<1>(0h0)) node _mem_brjmp_uop_T_295 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.branch, UInt<1>(0h0)) node _mem_brjmp_uop_T_296 = or(_mem_brjmp_uop_T_294, _mem_brjmp_uop_T_295) wire _mem_brjmp_uop_WIRE_108 : UInt<1> connect _mem_brjmp_uop_WIRE_108, _mem_brjmp_uop_T_296 connect _mem_brjmp_uop_WIRE_83.branch, _mem_brjmp_uop_WIRE_108 node _mem_brjmp_uop_T_297 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_brjmp_uop_T_298 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_brjmp_uop_T_299 = or(_mem_brjmp_uop_T_297, _mem_brjmp_uop_T_298) wire _mem_brjmp_uop_WIRE_109 : UInt<1> connect _mem_brjmp_uop_WIRE_109, _mem_brjmp_uop_T_299 connect _mem_brjmp_uop_WIRE_83.rocc, _mem_brjmp_uop_WIRE_109 node _mem_brjmp_uop_T_300 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _mem_brjmp_uop_T_301 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _mem_brjmp_uop_T_302 = or(_mem_brjmp_uop_T_300, _mem_brjmp_uop_T_301) wire _mem_brjmp_uop_WIRE_110 : UInt<1> connect _mem_brjmp_uop_WIRE_110, _mem_brjmp_uop_T_302 connect _mem_brjmp_uop_WIRE_83.fp, _mem_brjmp_uop_WIRE_110 node _mem_brjmp_uop_T_303 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.legal, UInt<1>(0h0)) node _mem_brjmp_uop_T_304 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.legal, UInt<1>(0h0)) node _mem_brjmp_uop_T_305 = or(_mem_brjmp_uop_T_303, _mem_brjmp_uop_T_304) wire _mem_brjmp_uop_WIRE_111 : UInt<1> connect _mem_brjmp_uop_WIRE_111, _mem_brjmp_uop_T_305 connect _mem_brjmp_uop_WIRE_83.legal, _mem_brjmp_uop_WIRE_111 connect _mem_brjmp_uop_WIRE_1.ctrl, _mem_brjmp_uop_WIRE_83 node _mem_brjmp_uop_T_306 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.edge_inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_307 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.edge_inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_308 = or(_mem_brjmp_uop_T_306, _mem_brjmp_uop_T_307) wire _mem_brjmp_uop_WIRE_112 : UInt<1> connect _mem_brjmp_uop_WIRE_112, _mem_brjmp_uop_T_308 connect _mem_brjmp_uop_WIRE_1.edge_inst, _mem_brjmp_uop_WIRE_112 node _mem_brjmp_uop_T_309 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.pc, UInt<1>(0h0)) node _mem_brjmp_uop_T_310 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.pc, UInt<1>(0h0)) node _mem_brjmp_uop_T_311 = or(_mem_brjmp_uop_T_309, _mem_brjmp_uop_T_310) wire _mem_brjmp_uop_WIRE_113 : UInt<40> connect _mem_brjmp_uop_WIRE_113, _mem_brjmp_uop_T_311 connect _mem_brjmp_uop_WIRE_1.pc, _mem_brjmp_uop_WIRE_113 node _mem_brjmp_uop_T_312 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.raw_inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_313 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.raw_inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_314 = or(_mem_brjmp_uop_T_312, _mem_brjmp_uop_T_313) wire _mem_brjmp_uop_WIRE_114 : UInt<32> connect _mem_brjmp_uop_WIRE_114, _mem_brjmp_uop_T_314 connect _mem_brjmp_uop_WIRE_1.raw_inst, _mem_brjmp_uop_WIRE_114 node _mem_brjmp_uop_T_315 = mux(mem_brjmp_oh_0, mem_uops_reg[0].bits.inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_316 = mux(mem_brjmp_oh_1, mem_uops_reg[1].bits.inst, UInt<1>(0h0)) node _mem_brjmp_uop_T_317 = or(_mem_brjmp_uop_T_315, _mem_brjmp_uop_T_316) wire _mem_brjmp_uop_WIRE_115 : UInt<32> connect _mem_brjmp_uop_WIRE_115, _mem_brjmp_uop_T_317 connect _mem_brjmp_uop_WIRE_1.inst, _mem_brjmp_uop_WIRE_115 connect _mem_brjmp_uop_WIRE.bits, _mem_brjmp_uop_WIRE_1 node _mem_brjmp_uop_T_318 = mux(mem_brjmp_oh_0, mem_uops_reg[0].valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_319 = mux(mem_brjmp_oh_1, mem_uops_reg[1].valid, UInt<1>(0h0)) node _mem_brjmp_uop_T_320 = or(_mem_brjmp_uop_T_318, _mem_brjmp_uop_T_319) wire _mem_brjmp_uop_WIRE_116 : UInt<1> connect _mem_brjmp_uop_WIRE_116, _mem_brjmp_uop_T_320 connect _mem_brjmp_uop_WIRE.valid, _mem_brjmp_uop_WIRE_116 node _mem_brjmp_call_T = or(_mem_brjmp_uop_WIRE.bits.ctrl.jalr, _mem_brjmp_uop_WIRE.bits.ctrl.jal) node _mem_brjmp_call_T_1 = bits(_mem_brjmp_uop_WIRE.bits.inst, 11, 7) node _mem_brjmp_call_T_2 = eq(_mem_brjmp_call_T_1, UInt<1>(0h1)) node mem_brjmp_call = and(_mem_brjmp_call_T, _mem_brjmp_call_T_2) node _mem_brjmp_ret_T = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 15) node _mem_brjmp_ret_T_1 = eq(_mem_brjmp_ret_T, UInt<1>(0h1)) node _mem_brjmp_ret_T_2 = and(_mem_brjmp_uop_WIRE.bits.ctrl.jalr, _mem_brjmp_ret_T_1) node _mem_brjmp_ret_T_3 = bits(_mem_brjmp_uop_WIRE.bits.inst, 11, 7) node _mem_brjmp_ret_T_4 = eq(_mem_brjmp_ret_T_3, UInt<1>(0h0)) node mem_brjmp_ret = and(_mem_brjmp_ret_T_2, _mem_brjmp_ret_T_4) node _mem_brjmp_target_T = asSInt(_mem_brjmp_uop_WIRE.bits.pc) node _mem_brjmp_target_T_1 = and(_mem_brjmp_uop_WIRE.bits.ctrl.branch, _mem_brjmp_uop_WIRE.bits.taken) node _mem_brjmp_target_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_brjmp_target_sign_T_1 = bits(_mem_brjmp_uop_WIRE.bits.inst, 31, 31) node _mem_brjmp_target_sign_T_2 = asSInt(_mem_brjmp_target_sign_T_1) node mem_brjmp_target_sign = mux(_mem_brjmp_target_sign_T, asSInt(UInt<1>(0h0)), _mem_brjmp_target_sign_T_2) node _mem_brjmp_target_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_brjmp_target_b30_20_T_1 = bits(_mem_brjmp_uop_WIRE.bits.inst, 30, 20) node _mem_brjmp_target_b30_20_T_2 = asSInt(_mem_brjmp_target_b30_20_T_1) node mem_brjmp_target_b30_20 = mux(_mem_brjmp_target_b30_20_T, _mem_brjmp_target_b30_20_T_2, mem_brjmp_target_sign) node _mem_brjmp_target_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_brjmp_target_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _mem_brjmp_target_b19_12_T_2 = and(_mem_brjmp_target_b19_12_T, _mem_brjmp_target_b19_12_T_1) node _mem_brjmp_target_b19_12_T_3 = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 12) node _mem_brjmp_target_b19_12_T_4 = asSInt(_mem_brjmp_target_b19_12_T_3) node mem_brjmp_target_b19_12 = mux(_mem_brjmp_target_b19_12_T_2, mem_brjmp_target_sign, _mem_brjmp_target_b19_12_T_4) node _mem_brjmp_target_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_brjmp_target_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_brjmp_target_b11_T_2 = or(_mem_brjmp_target_b11_T, _mem_brjmp_target_b11_T_1) node _mem_brjmp_target_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _mem_brjmp_target_b11_T_4 = bits(_mem_brjmp_uop_WIRE.bits.inst, 20, 20) node _mem_brjmp_target_b11_T_5 = asSInt(_mem_brjmp_target_b11_T_4) node _mem_brjmp_target_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _mem_brjmp_target_b11_T_7 = bits(_mem_brjmp_uop_WIRE.bits.inst, 7, 7) node _mem_brjmp_target_b11_T_8 = asSInt(_mem_brjmp_target_b11_T_7) node _mem_brjmp_target_b11_T_9 = mux(_mem_brjmp_target_b11_T_6, _mem_brjmp_target_b11_T_8, mem_brjmp_target_sign) node _mem_brjmp_target_b11_T_10 = mux(_mem_brjmp_target_b11_T_3, _mem_brjmp_target_b11_T_5, _mem_brjmp_target_b11_T_9) node mem_brjmp_target_b11 = mux(_mem_brjmp_target_b11_T_2, asSInt(UInt<1>(0h0)), _mem_brjmp_target_b11_T_10) node _mem_brjmp_target_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_brjmp_target_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_brjmp_target_b10_5_T_2 = or(_mem_brjmp_target_b10_5_T, _mem_brjmp_target_b10_5_T_1) node _mem_brjmp_target_b10_5_T_3 = bits(_mem_brjmp_uop_WIRE.bits.inst, 30, 25) node mem_brjmp_target_b10_5 = mux(_mem_brjmp_target_b10_5_T_2, UInt<1>(0h0), _mem_brjmp_target_b10_5_T_3) node _mem_brjmp_target_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_brjmp_target_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _mem_brjmp_target_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _mem_brjmp_target_b4_1_T_3 = or(_mem_brjmp_target_b4_1_T_1, _mem_brjmp_target_b4_1_T_2) node _mem_brjmp_target_b4_1_T_4 = bits(_mem_brjmp_uop_WIRE.bits.inst, 11, 8) node _mem_brjmp_target_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_brjmp_target_b4_1_T_6 = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 16) node _mem_brjmp_target_b4_1_T_7 = bits(_mem_brjmp_uop_WIRE.bits.inst, 24, 21) node _mem_brjmp_target_b4_1_T_8 = mux(_mem_brjmp_target_b4_1_T_5, _mem_brjmp_target_b4_1_T_6, _mem_brjmp_target_b4_1_T_7) node _mem_brjmp_target_b4_1_T_9 = mux(_mem_brjmp_target_b4_1_T_3, _mem_brjmp_target_b4_1_T_4, _mem_brjmp_target_b4_1_T_8) node mem_brjmp_target_b4_1 = mux(_mem_brjmp_target_b4_1_T, UInt<1>(0h0), _mem_brjmp_target_b4_1_T_9) node _mem_brjmp_target_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _mem_brjmp_target_b0_T_1 = bits(_mem_brjmp_uop_WIRE.bits.inst, 7, 7) node _mem_brjmp_target_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _mem_brjmp_target_b0_T_3 = bits(_mem_brjmp_uop_WIRE.bits.inst, 20, 20) node _mem_brjmp_target_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_brjmp_target_b0_T_5 = bits(_mem_brjmp_uop_WIRE.bits.inst, 15, 15) node _mem_brjmp_target_b0_T_6 = mux(_mem_brjmp_target_b0_T_4, _mem_brjmp_target_b0_T_5, UInt<1>(0h0)) node _mem_brjmp_target_b0_T_7 = mux(_mem_brjmp_target_b0_T_2, _mem_brjmp_target_b0_T_3, _mem_brjmp_target_b0_T_6) node mem_brjmp_target_b0 = mux(_mem_brjmp_target_b0_T, _mem_brjmp_target_b0_T_1, _mem_brjmp_target_b0_T_7) node mem_brjmp_target_lo_hi = cat(mem_brjmp_target_b10_5, mem_brjmp_target_b4_1) node mem_brjmp_target_lo = cat(mem_brjmp_target_lo_hi, mem_brjmp_target_b0) node mem_brjmp_target_hi_lo_lo = asUInt(mem_brjmp_target_b11) node mem_brjmp_target_hi_lo_hi = asUInt(mem_brjmp_target_b19_12) node mem_brjmp_target_hi_lo = cat(mem_brjmp_target_hi_lo_hi, mem_brjmp_target_hi_lo_lo) node mem_brjmp_target_hi_hi_lo = asUInt(mem_brjmp_target_b30_20) node mem_brjmp_target_hi_hi_hi = asUInt(mem_brjmp_target_sign) node mem_brjmp_target_hi_hi = cat(mem_brjmp_target_hi_hi_hi, mem_brjmp_target_hi_hi_lo) node mem_brjmp_target_hi = cat(mem_brjmp_target_hi_hi, mem_brjmp_target_hi_lo) node _mem_brjmp_target_T_2 = cat(mem_brjmp_target_hi, mem_brjmp_target_lo) node _mem_brjmp_target_T_3 = asSInt(_mem_brjmp_target_T_2) node _mem_brjmp_target_sign_T_3 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_brjmp_target_sign_T_4 = bits(_mem_brjmp_uop_WIRE.bits.inst, 31, 31) node _mem_brjmp_target_sign_T_5 = asSInt(_mem_brjmp_target_sign_T_4) node mem_brjmp_target_sign_1 = mux(_mem_brjmp_target_sign_T_3, asSInt(UInt<1>(0h0)), _mem_brjmp_target_sign_T_5) node _mem_brjmp_target_b30_20_T_3 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_brjmp_target_b30_20_T_4 = bits(_mem_brjmp_uop_WIRE.bits.inst, 30, 20) node _mem_brjmp_target_b30_20_T_5 = asSInt(_mem_brjmp_target_b30_20_T_4) node mem_brjmp_target_b30_20_1 = mux(_mem_brjmp_target_b30_20_T_3, _mem_brjmp_target_b30_20_T_5, mem_brjmp_target_sign_1) node _mem_brjmp_target_b19_12_T_5 = neq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_brjmp_target_b19_12_T_6 = neq(UInt<3>(0h3), UInt<3>(0h3)) node _mem_brjmp_target_b19_12_T_7 = and(_mem_brjmp_target_b19_12_T_5, _mem_brjmp_target_b19_12_T_6) node _mem_brjmp_target_b19_12_T_8 = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 12) node _mem_brjmp_target_b19_12_T_9 = asSInt(_mem_brjmp_target_b19_12_T_8) node mem_brjmp_target_b19_12_1 = mux(_mem_brjmp_target_b19_12_T_7, mem_brjmp_target_sign_1, _mem_brjmp_target_b19_12_T_9) node _mem_brjmp_target_b11_T_11 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_brjmp_target_b11_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_brjmp_target_b11_T_13 = or(_mem_brjmp_target_b11_T_11, _mem_brjmp_target_b11_T_12) node _mem_brjmp_target_b11_T_14 = eq(UInt<3>(0h3), UInt<3>(0h3)) node _mem_brjmp_target_b11_T_15 = bits(_mem_brjmp_uop_WIRE.bits.inst, 20, 20) node _mem_brjmp_target_b11_T_16 = asSInt(_mem_brjmp_target_b11_T_15) node _mem_brjmp_target_b11_T_17 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _mem_brjmp_target_b11_T_18 = bits(_mem_brjmp_uop_WIRE.bits.inst, 7, 7) node _mem_brjmp_target_b11_T_19 = asSInt(_mem_brjmp_target_b11_T_18) node _mem_brjmp_target_b11_T_20 = mux(_mem_brjmp_target_b11_T_17, _mem_brjmp_target_b11_T_19, mem_brjmp_target_sign_1) node _mem_brjmp_target_b11_T_21 = mux(_mem_brjmp_target_b11_T_14, _mem_brjmp_target_b11_T_16, _mem_brjmp_target_b11_T_20) node mem_brjmp_target_b11_1 = mux(_mem_brjmp_target_b11_T_13, asSInt(UInt<1>(0h0)), _mem_brjmp_target_b11_T_21) node _mem_brjmp_target_b10_5_T_4 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_brjmp_target_b10_5_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_brjmp_target_b10_5_T_6 = or(_mem_brjmp_target_b10_5_T_4, _mem_brjmp_target_b10_5_T_5) node _mem_brjmp_target_b10_5_T_7 = bits(_mem_brjmp_uop_WIRE.bits.inst, 30, 25) node mem_brjmp_target_b10_5_1 = mux(_mem_brjmp_target_b10_5_T_6, UInt<1>(0h0), _mem_brjmp_target_b10_5_T_7) node _mem_brjmp_target_b4_1_T_10 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_brjmp_target_b4_1_T_11 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _mem_brjmp_target_b4_1_T_12 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _mem_brjmp_target_b4_1_T_13 = or(_mem_brjmp_target_b4_1_T_11, _mem_brjmp_target_b4_1_T_12) node _mem_brjmp_target_b4_1_T_14 = bits(_mem_brjmp_uop_WIRE.bits.inst, 11, 8) node _mem_brjmp_target_b4_1_T_15 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_brjmp_target_b4_1_T_16 = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 16) node _mem_brjmp_target_b4_1_T_17 = bits(_mem_brjmp_uop_WIRE.bits.inst, 24, 21) node _mem_brjmp_target_b4_1_T_18 = mux(_mem_brjmp_target_b4_1_T_15, _mem_brjmp_target_b4_1_T_16, _mem_brjmp_target_b4_1_T_17) node _mem_brjmp_target_b4_1_T_19 = mux(_mem_brjmp_target_b4_1_T_13, _mem_brjmp_target_b4_1_T_14, _mem_brjmp_target_b4_1_T_18) node mem_brjmp_target_b4_1_1 = mux(_mem_brjmp_target_b4_1_T_10, UInt<1>(0h0), _mem_brjmp_target_b4_1_T_19) node _mem_brjmp_target_b0_T_8 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _mem_brjmp_target_b0_T_9 = bits(_mem_brjmp_uop_WIRE.bits.inst, 7, 7) node _mem_brjmp_target_b0_T_10 = eq(UInt<3>(0h3), UInt<3>(0h4)) node _mem_brjmp_target_b0_T_11 = bits(_mem_brjmp_uop_WIRE.bits.inst, 20, 20) node _mem_brjmp_target_b0_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_brjmp_target_b0_T_13 = bits(_mem_brjmp_uop_WIRE.bits.inst, 15, 15) node _mem_brjmp_target_b0_T_14 = mux(_mem_brjmp_target_b0_T_12, _mem_brjmp_target_b0_T_13, UInt<1>(0h0)) node _mem_brjmp_target_b0_T_15 = mux(_mem_brjmp_target_b0_T_10, _mem_brjmp_target_b0_T_11, _mem_brjmp_target_b0_T_14) node mem_brjmp_target_b0_1 = mux(_mem_brjmp_target_b0_T_8, _mem_brjmp_target_b0_T_9, _mem_brjmp_target_b0_T_15) node mem_brjmp_target_lo_hi_1 = cat(mem_brjmp_target_b10_5_1, mem_brjmp_target_b4_1_1) node mem_brjmp_target_lo_1 = cat(mem_brjmp_target_lo_hi_1, mem_brjmp_target_b0_1) node mem_brjmp_target_hi_lo_lo_1 = asUInt(mem_brjmp_target_b11_1) node mem_brjmp_target_hi_lo_hi_1 = asUInt(mem_brjmp_target_b19_12_1) node mem_brjmp_target_hi_lo_1 = cat(mem_brjmp_target_hi_lo_hi_1, mem_brjmp_target_hi_lo_lo_1) node mem_brjmp_target_hi_hi_lo_1 = asUInt(mem_brjmp_target_b30_20_1) node mem_brjmp_target_hi_hi_hi_1 = asUInt(mem_brjmp_target_sign_1) node mem_brjmp_target_hi_hi_1 = cat(mem_brjmp_target_hi_hi_hi_1, mem_brjmp_target_hi_hi_lo_1) node mem_brjmp_target_hi_1 = cat(mem_brjmp_target_hi_hi_1, mem_brjmp_target_hi_lo_1) node _mem_brjmp_target_T_4 = cat(mem_brjmp_target_hi_1, mem_brjmp_target_lo_1) node _mem_brjmp_target_T_5 = asSInt(_mem_brjmp_target_T_4) node _mem_brjmp_target_T_6 = mux(_mem_brjmp_uop_WIRE.bits.rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _mem_brjmp_target_T_7 = mux(_mem_brjmp_uop_WIRE.bits.ctrl.jal, _mem_brjmp_target_T_5, _mem_brjmp_target_T_6) node _mem_brjmp_target_T_8 = mux(_mem_brjmp_target_T_1, _mem_brjmp_target_T_3, _mem_brjmp_target_T_7) node _mem_brjmp_target_T_9 = add(_mem_brjmp_target_T, _mem_brjmp_target_T_8) node _mem_brjmp_target_T_10 = tail(_mem_brjmp_target_T_9, 1) node mem_brjmp_target = asSInt(_mem_brjmp_target_T_10) node _mem_brjmp_npc_T = eq(_mem_brjmp_uop_WIRE.bits.ctrl.mem_cmd, UInt<5>(0h14)) node _mem_brjmp_npc_T_1 = and(_mem_brjmp_uop_WIRE.bits.ctrl.mem, _mem_brjmp_npc_T) node _mem_brjmp_npc_T_2 = or(_mem_brjmp_uop_WIRE.bits.ctrl.jalr, _mem_brjmp_npc_T_1) node _mem_brjmp_npc_a_T = asSInt(_mem_brjmp_uop_WIRE.bits.wdata.bits) node mem_brjmp_npc_a = shr(_mem_brjmp_npc_a_T, 39) node _mem_brjmp_npc_msb_T = eq(mem_brjmp_npc_a, asSInt(UInt<1>(0h0))) node _mem_brjmp_npc_msb_T_1 = eq(mem_brjmp_npc_a, asSInt(UInt<1>(0h1))) node _mem_brjmp_npc_msb_T_2 = or(_mem_brjmp_npc_msb_T, _mem_brjmp_npc_msb_T_1) node _mem_brjmp_npc_msb_T_3 = bits(_mem_brjmp_uop_WIRE.bits.wdata.bits, 39, 39) node _mem_brjmp_npc_msb_T_4 = bits(_mem_brjmp_uop_WIRE.bits.wdata.bits, 38, 38) node _mem_brjmp_npc_msb_T_5 = eq(_mem_brjmp_npc_msb_T_4, UInt<1>(0h0)) node mem_brjmp_npc_msb = mux(_mem_brjmp_npc_msb_T_2, _mem_brjmp_npc_msb_T_3, _mem_brjmp_npc_msb_T_5) node _mem_brjmp_npc_T_3 = bits(_mem_brjmp_uop_WIRE.bits.wdata.bits, 38, 0) node _mem_brjmp_npc_T_4 = cat(mem_brjmp_npc_msb, _mem_brjmp_npc_T_3) node _mem_brjmp_npc_T_5 = asSInt(_mem_brjmp_npc_T_4) node _mem_brjmp_npc_T_6 = mux(_mem_brjmp_npc_T_2, _mem_brjmp_npc_T_5, mem_brjmp_target) node _mem_brjmp_npc_T_7 = and(_mem_brjmp_npc_T_6, asSInt(UInt<2>(0h2))) node _mem_brjmp_npc_T_8 = asSInt(_mem_brjmp_npc_T_7) node mem_brjmp_npc = asUInt(_mem_brjmp_npc_T_8) node mem_brjmp_wrong_npc = neq(_mem_brjmp_uop_WIRE.bits.next_pc.bits, mem_brjmp_npc) node _mem_brjmp_taken_T = and(_mem_brjmp_uop_WIRE.bits.ctrl.branch, _mem_brjmp_uop_WIRE.bits.taken) node _mem_brjmp_taken_T_1 = or(_mem_brjmp_taken_T, _mem_brjmp_uop_WIRE.bits.ctrl.jalr) node mem_brjmp_taken = or(_mem_brjmp_taken_T_1, _mem_brjmp_uop_WIRE.bits.ctrl.jal) node _mem_brjmp_mispredict_taken_T = eq(_mem_brjmp_uop_WIRE.bits.next_pc.valid, UInt<1>(0h0)) node _mem_brjmp_mispredict_taken_T_1 = or(_mem_brjmp_mispredict_taken_T, mem_brjmp_wrong_npc) node mem_brjmp_mispredict_taken = and(mem_brjmp_taken, _mem_brjmp_mispredict_taken_T_1) node _mem_brjmp_mispredict_not_taken_T = eq(_mem_brjmp_uop_WIRE.bits.taken, UInt<1>(0h0)) node _mem_brjmp_mispredict_not_taken_T_1 = and(_mem_brjmp_uop_WIRE.bits.ctrl.branch, _mem_brjmp_mispredict_not_taken_T) node _mem_brjmp_mispredict_not_taken_T_2 = or(_mem_brjmp_uop_WIRE.bits.ctrl.branch, _mem_brjmp_uop_WIRE.bits.ctrl.jal) node _mem_brjmp_mispredict_not_taken_T_3 = or(_mem_brjmp_mispredict_not_taken_T_2, _mem_brjmp_uop_WIRE.bits.ctrl.jalr) node _mem_brjmp_mispredict_not_taken_T_4 = eq(_mem_brjmp_mispredict_not_taken_T_3, UInt<1>(0h0)) node _mem_brjmp_mispredict_not_taken_T_5 = or(_mem_brjmp_mispredict_not_taken_T_1, _mem_brjmp_mispredict_not_taken_T_4) node mem_brjmp_mispredict_not_taken = and(_mem_brjmp_mispredict_not_taken_T_5, _mem_brjmp_uop_WIRE.bits.next_pc.valid) node mem_brjmp_mispredict = or(mem_brjmp_mispredict_taken, mem_brjmp_mispredict_not_taken) node mem_brjmp_sfb = and(mem_uops_reg[0].bits.sfb_br, mem_uops_reg[1].valid) node _io_imem_btb_update_valid_T = eq(mem_brjmp_sfb, UInt<1>(0h0)) node _io_imem_btb_update_valid_T_1 = and(mem_brjmp_val, _io_imem_btb_update_valid_T) connect io.imem.btb_update.valid, _io_imem_btb_update_valid_T_1 connect io.imem.btb_update.bits.mispredict, mem_brjmp_mispredict connect io.imem.btb_update.bits.isValid, mem_brjmp_val node _io_imem_btb_update_bits_cfiType_T = or(_mem_brjmp_uop_WIRE.bits.ctrl.jal, _mem_brjmp_uop_WIRE.bits.ctrl.jalr) node _io_imem_btb_update_bits_cfiType_T_1 = bits(_mem_brjmp_uop_WIRE.bits.inst, 11, 7) node _io_imem_btb_update_bits_cfiType_T_2 = bits(_io_imem_btb_update_bits_cfiType_T_1, 0, 0) node _io_imem_btb_update_bits_cfiType_T_3 = and(_io_imem_btb_update_bits_cfiType_T, _io_imem_btb_update_bits_cfiType_T_2) node _io_imem_btb_update_bits_cfiType_T_4 = bits(_mem_brjmp_uop_WIRE.bits.inst, 19, 15) node _io_imem_btb_update_bits_cfiType_T_5 = and(_io_imem_btb_update_bits_cfiType_T_4, UInt<5>(0h1b)) node _io_imem_btb_update_bits_cfiType_T_6 = eq(UInt<1>(0h1), _io_imem_btb_update_bits_cfiType_T_5) node _io_imem_btb_update_bits_cfiType_T_7 = and(_mem_brjmp_uop_WIRE.bits.ctrl.jalr, _io_imem_btb_update_bits_cfiType_T_6) node _io_imem_btb_update_bits_cfiType_T_8 = or(_mem_brjmp_uop_WIRE.bits.ctrl.jal, _mem_brjmp_uop_WIRE.bits.ctrl.jalr) node _io_imem_btb_update_bits_cfiType_T_9 = mux(_io_imem_btb_update_bits_cfiType_T_8, UInt<1>(0h1), UInt<1>(0h0)) node _io_imem_btb_update_bits_cfiType_T_10 = mux(_io_imem_btb_update_bits_cfiType_T_7, UInt<2>(0h3), _io_imem_btb_update_bits_cfiType_T_9) node _io_imem_btb_update_bits_cfiType_T_11 = mux(_io_imem_btb_update_bits_cfiType_T_3, UInt<2>(0h2), _io_imem_btb_update_bits_cfiType_T_10) connect io.imem.btb_update.bits.cfiType, _io_imem_btb_update_bits_cfiType_T_11 node _mem_brjmp_bridx_T = shr(_mem_brjmp_uop_WIRE.bits.pc, 1) node mem_brjmp_bridx = bits(_mem_brjmp_bridx_T, 1, 0) node _mem_brjmp_is_last_over_edge_T = eq(mem_brjmp_bridx, UInt<2>(0h3)) node _mem_brjmp_is_last_over_edge_T_1 = eq(_mem_brjmp_uop_WIRE.bits.rvc, UInt<1>(0h0)) node mem_brjmp_is_last_over_edge = and(_mem_brjmp_is_last_over_edge_T, _mem_brjmp_is_last_over_edge_T_1) connect io.imem.btb_update.bits.target, mem_brjmp_npc node _io_imem_btb_update_bits_br_pc_T = mux(mem_brjmp_is_last_over_edge, UInt<2>(0h2), UInt<1>(0h0)) node _io_imem_btb_update_bits_br_pc_T_1 = add(_mem_brjmp_uop_WIRE.bits.pc, _io_imem_btb_update_bits_br_pc_T) node _io_imem_btb_update_bits_br_pc_T_2 = tail(_io_imem_btb_update_bits_br_pc_T_1, 1) connect io.imem.btb_update.bits.br_pc, _io_imem_btb_update_bits_br_pc_T_2 node _io_imem_btb_update_bits_pc_T = not(io.imem.btb_update.bits.br_pc) node _io_imem_btb_update_bits_pc_T_1 = or(_io_imem_btb_update_bits_pc_T, UInt<3>(0h7)) node _io_imem_btb_update_bits_pc_T_2 = not(_io_imem_btb_update_bits_pc_T_1) connect io.imem.btb_update.bits.pc, _io_imem_btb_update_bits_pc_T_2 connect io.imem.btb_update.bits.prediction, _mem_brjmp_uop_WIRE.bits.btb_resp.bits node _T_147 = eq(_mem_brjmp_uop_WIRE.bits.btb_resp.valid, UInt<1>(0h0)) when _T_147 : connect io.imem.btb_update.bits.prediction.entry, UInt<6>(0h20) invalidate io.imem.btb_update.bits.taken node _io_imem_bht_update_valid_T = eq(mem_brjmp_sfb, UInt<1>(0h0)) node _io_imem_bht_update_valid_T_1 = and(mem_brjmp_val, _io_imem_bht_update_valid_T) connect io.imem.bht_update.valid, _io_imem_bht_update_valid_T_1 connect io.imem.bht_update.bits.pc, io.imem.btb_update.bits.pc connect io.imem.bht_update.bits.taken, mem_brjmp_taken connect io.imem.bht_update.bits.mispredict, mem_brjmp_mispredict connect io.imem.bht_update.bits.branch, _mem_brjmp_uop_WIRE.bits.ctrl.branch connect io.imem.bht_update.bits.prediction, _mem_brjmp_uop_WIRE.bits.btb_resp.bits.bht node _io_imem_ras_update_valid_T = and(mem_brjmp_call, mem_brjmp_val) connect io.imem.ras_update.valid, _io_imem_ras_update_valid_T node _io_imem_ras_update_bits_head_T = eq(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<3>(0h5)) node _io_imem_ras_update_bits_head_T_1 = add(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<1>(0h1)) node _io_imem_ras_update_bits_head_T_2 = tail(_io_imem_ras_update_bits_head_T_1, 1) node _io_imem_ras_update_bits_head_T_3 = mux(_io_imem_ras_update_bits_head_T, UInt<1>(0h0), _io_imem_ras_update_bits_head_T_2) connect io.imem.ras_update.bits.head, _io_imem_ras_update_bits_head_T_3 connect io.imem.ras_update.bits.addr, _mem_brjmp_uop_WIRE.bits.wdata.bits connect io.imem.redirect_pc, mem_brjmp_npc node _io_imem_redirect_ras_head_T = eq(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<3>(0h5)) node _io_imem_redirect_ras_head_T_1 = add(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<1>(0h1)) node _io_imem_redirect_ras_head_T_2 = tail(_io_imem_redirect_ras_head_T_1, 1) node _io_imem_redirect_ras_head_T_3 = mux(_io_imem_redirect_ras_head_T, UInt<1>(0h0), _io_imem_redirect_ras_head_T_2) node _io_imem_redirect_ras_head_T_4 = eq(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<1>(0h0)) node _io_imem_redirect_ras_head_T_5 = sub(_mem_brjmp_uop_WIRE.bits.ras_head, UInt<1>(0h1)) node _io_imem_redirect_ras_head_T_6 = tail(_io_imem_redirect_ras_head_T_5, 1) node _io_imem_redirect_ras_head_T_7 = mux(_io_imem_redirect_ras_head_T_4, UInt<3>(0h5), _io_imem_redirect_ras_head_T_6) node _io_imem_redirect_ras_head_T_8 = mux(mem_brjmp_ret, _io_imem_redirect_ras_head_T_7, _mem_brjmp_uop_WIRE.bits.ras_head) node _io_imem_redirect_ras_head_T_9 = mux(mem_brjmp_call, _io_imem_redirect_ras_head_T_3, _io_imem_redirect_ras_head_T_8) connect io.imem.redirect_ras_head, _io_imem_redirect_ras_head_T_9 node _T_148 = and(mem_brjmp_val, mem_brjmp_mispredict) node _T_149 = eq(mem_brjmp_sfb, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) when _T_150 : connect flush_rrd_ex, UInt<1>(0h1) connect io.imem.redirect_val, UInt<1>(0h1) connect io.imem.redirect_flush, UInt<1>(0h1) node mem_dmem_oh_0 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.mem) node mem_dmem_oh_1 = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.mem) wire mem_dmem_uop : { valid : UInt<1>, bits : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>}} wire _mem_dmem_uop_WIRE : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} node _mem_dmem_uop_T = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.flush_pipe, UInt<1>(0h0)) node _mem_dmem_uop_T_1 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.flush_pipe, UInt<1>(0h0)) node _mem_dmem_uop_T_2 = or(_mem_dmem_uop_T, _mem_dmem_uop_T_1) wire _mem_dmem_uop_WIRE_1 : UInt<1> connect _mem_dmem_uop_WIRE_1, _mem_dmem_uop_T_2 connect _mem_dmem_uop_WIRE.flush_pipe, _mem_dmem_uop_WIRE_1 node _mem_dmem_uop_T_3 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.mem_size, UInt<1>(0h0)) node _mem_dmem_uop_T_4 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.mem_size, UInt<1>(0h0)) node _mem_dmem_uop_T_5 = or(_mem_dmem_uop_T_3, _mem_dmem_uop_T_4) wire _mem_dmem_uop_WIRE_2 : UInt<2> connect _mem_dmem_uop_WIRE_2, _mem_dmem_uop_T_5 connect _mem_dmem_uop_WIRE.mem_size, _mem_dmem_uop_WIRE_2 wire _mem_dmem_uop_WIRE_3 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} node _mem_dmem_uop_T_6 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.in3, UInt<1>(0h0)) node _mem_dmem_uop_T_7 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.in3, UInt<1>(0h0)) node _mem_dmem_uop_T_8 = or(_mem_dmem_uop_T_6, _mem_dmem_uop_T_7) wire _mem_dmem_uop_WIRE_4 : UInt<65> connect _mem_dmem_uop_WIRE_4, _mem_dmem_uop_T_8 connect _mem_dmem_uop_WIRE_3.in3, _mem_dmem_uop_WIRE_4 node _mem_dmem_uop_T_9 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.in2, UInt<1>(0h0)) node _mem_dmem_uop_T_10 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.in2, UInt<1>(0h0)) node _mem_dmem_uop_T_11 = or(_mem_dmem_uop_T_9, _mem_dmem_uop_T_10) wire _mem_dmem_uop_WIRE_5 : UInt<65> connect _mem_dmem_uop_WIRE_5, _mem_dmem_uop_T_11 connect _mem_dmem_uop_WIRE_3.in2, _mem_dmem_uop_WIRE_5 node _mem_dmem_uop_T_12 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.in1, UInt<1>(0h0)) node _mem_dmem_uop_T_13 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.in1, UInt<1>(0h0)) node _mem_dmem_uop_T_14 = or(_mem_dmem_uop_T_12, _mem_dmem_uop_T_13) wire _mem_dmem_uop_WIRE_6 : UInt<65> connect _mem_dmem_uop_WIRE_6, _mem_dmem_uop_T_14 connect _mem_dmem_uop_WIRE_3.in1, _mem_dmem_uop_WIRE_6 node _mem_dmem_uop_T_15 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.fmt, UInt<1>(0h0)) node _mem_dmem_uop_T_16 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.fmt, UInt<1>(0h0)) node _mem_dmem_uop_T_17 = or(_mem_dmem_uop_T_15, _mem_dmem_uop_T_16) wire _mem_dmem_uop_WIRE_7 : UInt<2> connect _mem_dmem_uop_WIRE_7, _mem_dmem_uop_T_17 connect _mem_dmem_uop_WIRE_3.fmt, _mem_dmem_uop_WIRE_7 node _mem_dmem_uop_T_18 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.typ, UInt<1>(0h0)) node _mem_dmem_uop_T_19 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.typ, UInt<1>(0h0)) node _mem_dmem_uop_T_20 = or(_mem_dmem_uop_T_18, _mem_dmem_uop_T_19) wire _mem_dmem_uop_WIRE_8 : UInt<2> connect _mem_dmem_uop_WIRE_8, _mem_dmem_uop_T_20 connect _mem_dmem_uop_WIRE_3.typ, _mem_dmem_uop_WIRE_8 node _mem_dmem_uop_T_21 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _mem_dmem_uop_T_22 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.fmaCmd, UInt<1>(0h0)) node _mem_dmem_uop_T_23 = or(_mem_dmem_uop_T_21, _mem_dmem_uop_T_22) wire _mem_dmem_uop_WIRE_9 : UInt<2> connect _mem_dmem_uop_WIRE_9, _mem_dmem_uop_T_23 connect _mem_dmem_uop_WIRE_3.fmaCmd, _mem_dmem_uop_WIRE_9 node _mem_dmem_uop_T_24 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.rm, UInt<1>(0h0)) node _mem_dmem_uop_T_25 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.rm, UInt<1>(0h0)) node _mem_dmem_uop_T_26 = or(_mem_dmem_uop_T_24, _mem_dmem_uop_T_25) wire _mem_dmem_uop_WIRE_10 : UInt<3> connect _mem_dmem_uop_WIRE_10, _mem_dmem_uop_T_26 connect _mem_dmem_uop_WIRE_3.rm, _mem_dmem_uop_WIRE_10 node _mem_dmem_uop_T_27 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_28 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_29 = or(_mem_dmem_uop_T_27, _mem_dmem_uop_T_28) wire _mem_dmem_uop_WIRE_11 : UInt<1> connect _mem_dmem_uop_WIRE_11, _mem_dmem_uop_T_29 connect _mem_dmem_uop_WIRE_3.vec, _mem_dmem_uop_WIRE_11 node _mem_dmem_uop_T_30 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.wflags, UInt<1>(0h0)) node _mem_dmem_uop_T_31 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.wflags, UInt<1>(0h0)) node _mem_dmem_uop_T_32 = or(_mem_dmem_uop_T_30, _mem_dmem_uop_T_31) wire _mem_dmem_uop_WIRE_12 : UInt<1> connect _mem_dmem_uop_WIRE_12, _mem_dmem_uop_T_32 connect _mem_dmem_uop_WIRE_3.wflags, _mem_dmem_uop_WIRE_12 node _mem_dmem_uop_T_33 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.sqrt, UInt<1>(0h0)) node _mem_dmem_uop_T_34 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.sqrt, UInt<1>(0h0)) node _mem_dmem_uop_T_35 = or(_mem_dmem_uop_T_33, _mem_dmem_uop_T_34) wire _mem_dmem_uop_WIRE_13 : UInt<1> connect _mem_dmem_uop_WIRE_13, _mem_dmem_uop_T_35 connect _mem_dmem_uop_WIRE_3.sqrt, _mem_dmem_uop_WIRE_13 node _mem_dmem_uop_T_36 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.div, UInt<1>(0h0)) node _mem_dmem_uop_T_37 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.div, UInt<1>(0h0)) node _mem_dmem_uop_T_38 = or(_mem_dmem_uop_T_36, _mem_dmem_uop_T_37) wire _mem_dmem_uop_WIRE_14 : UInt<1> connect _mem_dmem_uop_WIRE_14, _mem_dmem_uop_T_38 connect _mem_dmem_uop_WIRE_3.div, _mem_dmem_uop_WIRE_14 node _mem_dmem_uop_T_39 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.fma, UInt<1>(0h0)) node _mem_dmem_uop_T_40 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.fma, UInt<1>(0h0)) node _mem_dmem_uop_T_41 = or(_mem_dmem_uop_T_39, _mem_dmem_uop_T_40) wire _mem_dmem_uop_WIRE_15 : UInt<1> connect _mem_dmem_uop_WIRE_15, _mem_dmem_uop_T_41 connect _mem_dmem_uop_WIRE_3.fma, _mem_dmem_uop_WIRE_15 node _mem_dmem_uop_T_42 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.fastpipe, UInt<1>(0h0)) node _mem_dmem_uop_T_43 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.fastpipe, UInt<1>(0h0)) node _mem_dmem_uop_T_44 = or(_mem_dmem_uop_T_42, _mem_dmem_uop_T_43) wire _mem_dmem_uop_WIRE_16 : UInt<1> connect _mem_dmem_uop_WIRE_16, _mem_dmem_uop_T_44 connect _mem_dmem_uop_WIRE_3.fastpipe, _mem_dmem_uop_WIRE_16 node _mem_dmem_uop_T_45 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.toint, UInt<1>(0h0)) node _mem_dmem_uop_T_46 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.toint, UInt<1>(0h0)) node _mem_dmem_uop_T_47 = or(_mem_dmem_uop_T_45, _mem_dmem_uop_T_46) wire _mem_dmem_uop_WIRE_17 : UInt<1> connect _mem_dmem_uop_WIRE_17, _mem_dmem_uop_T_47 connect _mem_dmem_uop_WIRE_3.toint, _mem_dmem_uop_WIRE_17 node _mem_dmem_uop_T_48 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.fromint, UInt<1>(0h0)) node _mem_dmem_uop_T_49 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.fromint, UInt<1>(0h0)) node _mem_dmem_uop_T_50 = or(_mem_dmem_uop_T_48, _mem_dmem_uop_T_49) wire _mem_dmem_uop_WIRE_18 : UInt<1> connect _mem_dmem_uop_WIRE_18, _mem_dmem_uop_T_50 connect _mem_dmem_uop_WIRE_3.fromint, _mem_dmem_uop_WIRE_18 node _mem_dmem_uop_T_51 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _mem_dmem_uop_T_52 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.typeTagOut, UInt<1>(0h0)) node _mem_dmem_uop_T_53 = or(_mem_dmem_uop_T_51, _mem_dmem_uop_T_52) wire _mem_dmem_uop_WIRE_19 : UInt<2> connect _mem_dmem_uop_WIRE_19, _mem_dmem_uop_T_53 connect _mem_dmem_uop_WIRE_3.typeTagOut, _mem_dmem_uop_WIRE_19 node _mem_dmem_uop_T_54 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _mem_dmem_uop_T_55 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.typeTagIn, UInt<1>(0h0)) node _mem_dmem_uop_T_56 = or(_mem_dmem_uop_T_54, _mem_dmem_uop_T_55) wire _mem_dmem_uop_WIRE_20 : UInt<2> connect _mem_dmem_uop_WIRE_20, _mem_dmem_uop_T_56 connect _mem_dmem_uop_WIRE_3.typeTagIn, _mem_dmem_uop_WIRE_20 node _mem_dmem_uop_T_57 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.swap23, UInt<1>(0h0)) node _mem_dmem_uop_T_58 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.swap23, UInt<1>(0h0)) node _mem_dmem_uop_T_59 = or(_mem_dmem_uop_T_57, _mem_dmem_uop_T_58) wire _mem_dmem_uop_WIRE_21 : UInt<1> connect _mem_dmem_uop_WIRE_21, _mem_dmem_uop_T_59 connect _mem_dmem_uop_WIRE_3.swap23, _mem_dmem_uop_WIRE_21 node _mem_dmem_uop_T_60 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.swap12, UInt<1>(0h0)) node _mem_dmem_uop_T_61 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.swap12, UInt<1>(0h0)) node _mem_dmem_uop_T_62 = or(_mem_dmem_uop_T_60, _mem_dmem_uop_T_61) wire _mem_dmem_uop_WIRE_22 : UInt<1> connect _mem_dmem_uop_WIRE_22, _mem_dmem_uop_T_62 connect _mem_dmem_uop_WIRE_3.swap12, _mem_dmem_uop_WIRE_22 node _mem_dmem_uop_T_63 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.ren3, UInt<1>(0h0)) node _mem_dmem_uop_T_64 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.ren3, UInt<1>(0h0)) node _mem_dmem_uop_T_65 = or(_mem_dmem_uop_T_63, _mem_dmem_uop_T_64) wire _mem_dmem_uop_WIRE_23 : UInt<1> connect _mem_dmem_uop_WIRE_23, _mem_dmem_uop_T_65 connect _mem_dmem_uop_WIRE_3.ren3, _mem_dmem_uop_WIRE_23 node _mem_dmem_uop_T_66 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.ren2, UInt<1>(0h0)) node _mem_dmem_uop_T_67 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.ren2, UInt<1>(0h0)) node _mem_dmem_uop_T_68 = or(_mem_dmem_uop_T_66, _mem_dmem_uop_T_67) wire _mem_dmem_uop_WIRE_24 : UInt<1> connect _mem_dmem_uop_WIRE_24, _mem_dmem_uop_T_68 connect _mem_dmem_uop_WIRE_3.ren2, _mem_dmem_uop_WIRE_24 node _mem_dmem_uop_T_69 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.ren1, UInt<1>(0h0)) node _mem_dmem_uop_T_70 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.ren1, UInt<1>(0h0)) node _mem_dmem_uop_T_71 = or(_mem_dmem_uop_T_69, _mem_dmem_uop_T_70) wire _mem_dmem_uop_WIRE_25 : UInt<1> connect _mem_dmem_uop_WIRE_25, _mem_dmem_uop_T_71 connect _mem_dmem_uop_WIRE_3.ren1, _mem_dmem_uop_WIRE_25 node _mem_dmem_uop_T_72 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.wen, UInt<1>(0h0)) node _mem_dmem_uop_T_73 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.wen, UInt<1>(0h0)) node _mem_dmem_uop_T_74 = or(_mem_dmem_uop_T_72, _mem_dmem_uop_T_73) wire _mem_dmem_uop_WIRE_26 : UInt<1> connect _mem_dmem_uop_WIRE_26, _mem_dmem_uop_T_74 connect _mem_dmem_uop_WIRE_3.wen, _mem_dmem_uop_WIRE_26 node _mem_dmem_uop_T_75 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fdivin.ldst, UInt<1>(0h0)) node _mem_dmem_uop_T_76 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fdivin.ldst, UInt<1>(0h0)) node _mem_dmem_uop_T_77 = or(_mem_dmem_uop_T_75, _mem_dmem_uop_T_76) wire _mem_dmem_uop_WIRE_27 : UInt<1> connect _mem_dmem_uop_WIRE_27, _mem_dmem_uop_T_77 connect _mem_dmem_uop_WIRE_3.ldst, _mem_dmem_uop_WIRE_27 connect _mem_dmem_uop_WIRE.fdivin, _mem_dmem_uop_WIRE_3 node _mem_dmem_uop_T_78 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fexc, UInt<1>(0h0)) node _mem_dmem_uop_T_79 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fexc, UInt<1>(0h0)) node _mem_dmem_uop_T_80 = or(_mem_dmem_uop_T_78, _mem_dmem_uop_T_79) wire _mem_dmem_uop_WIRE_28 : UInt<5> connect _mem_dmem_uop_WIRE_28, _mem_dmem_uop_T_80 connect _mem_dmem_uop_WIRE.fexc, _mem_dmem_uop_WIRE_28 node _mem_dmem_uop_T_81 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fra3, UInt<1>(0h0)) node _mem_dmem_uop_T_82 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fra3, UInt<1>(0h0)) node _mem_dmem_uop_T_83 = or(_mem_dmem_uop_T_81, _mem_dmem_uop_T_82) wire _mem_dmem_uop_WIRE_29 : UInt<5> connect _mem_dmem_uop_WIRE_29, _mem_dmem_uop_T_83 connect _mem_dmem_uop_WIRE.fra3, _mem_dmem_uop_WIRE_29 node _mem_dmem_uop_T_84 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fra2, UInt<1>(0h0)) node _mem_dmem_uop_T_85 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fra2, UInt<1>(0h0)) node _mem_dmem_uop_T_86 = or(_mem_dmem_uop_T_84, _mem_dmem_uop_T_85) wire _mem_dmem_uop_WIRE_30 : UInt<5> connect _mem_dmem_uop_WIRE_30, _mem_dmem_uop_T_86 connect _mem_dmem_uop_WIRE.fra2, _mem_dmem_uop_WIRE_30 node _mem_dmem_uop_T_87 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fra1, UInt<1>(0h0)) node _mem_dmem_uop_T_88 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fra1, UInt<1>(0h0)) node _mem_dmem_uop_T_89 = or(_mem_dmem_uop_T_87, _mem_dmem_uop_T_88) wire _mem_dmem_uop_WIRE_31 : UInt<5> connect _mem_dmem_uop_WIRE_31, _mem_dmem_uop_T_89 connect _mem_dmem_uop_WIRE.fra1, _mem_dmem_uop_WIRE_31 wire _mem_dmem_uop_WIRE_32 : { valid : UInt<1>, bits : UInt<64>} node _mem_dmem_uop_T_90 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.wdata.bits, UInt<1>(0h0)) node _mem_dmem_uop_T_91 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.wdata.bits, UInt<1>(0h0)) node _mem_dmem_uop_T_92 = or(_mem_dmem_uop_T_90, _mem_dmem_uop_T_91) wire _mem_dmem_uop_WIRE_33 : UInt<64> connect _mem_dmem_uop_WIRE_33, _mem_dmem_uop_T_92 connect _mem_dmem_uop_WIRE_32.bits, _mem_dmem_uop_WIRE_33 node _mem_dmem_uop_T_93 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.wdata.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_94 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.wdata.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_95 = or(_mem_dmem_uop_T_93, _mem_dmem_uop_T_94) wire _mem_dmem_uop_WIRE_34 : UInt<1> connect _mem_dmem_uop_WIRE_34, _mem_dmem_uop_T_95 connect _mem_dmem_uop_WIRE_32.valid, _mem_dmem_uop_WIRE_34 connect _mem_dmem_uop_WIRE.wdata, _mem_dmem_uop_WIRE_32 node _mem_dmem_uop_T_96 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.uses_latealu, UInt<1>(0h0)) node _mem_dmem_uop_T_97 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.uses_latealu, UInt<1>(0h0)) node _mem_dmem_uop_T_98 = or(_mem_dmem_uop_T_96, _mem_dmem_uop_T_97) wire _mem_dmem_uop_WIRE_35 : UInt<1> connect _mem_dmem_uop_WIRE_35, _mem_dmem_uop_T_98 connect _mem_dmem_uop_WIRE.uses_latealu, _mem_dmem_uop_WIRE_35 node _mem_dmem_uop_T_99 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.uses_memalu, UInt<1>(0h0)) node _mem_dmem_uop_T_100 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.uses_memalu, UInt<1>(0h0)) node _mem_dmem_uop_T_101 = or(_mem_dmem_uop_T_99, _mem_dmem_uop_T_100) wire _mem_dmem_uop_WIRE_36 : UInt<1> connect _mem_dmem_uop_WIRE_36, _mem_dmem_uop_T_101 connect _mem_dmem_uop_WIRE.uses_memalu, _mem_dmem_uop_WIRE_36 node _mem_dmem_uop_T_102 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.rs3_data, UInt<1>(0h0)) node _mem_dmem_uop_T_103 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.rs3_data, UInt<1>(0h0)) node _mem_dmem_uop_T_104 = or(_mem_dmem_uop_T_102, _mem_dmem_uop_T_103) wire _mem_dmem_uop_WIRE_37 : UInt<64> connect _mem_dmem_uop_WIRE_37, _mem_dmem_uop_T_104 connect _mem_dmem_uop_WIRE.rs3_data, _mem_dmem_uop_WIRE_37 node _mem_dmem_uop_T_105 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.rs2_data, UInt<1>(0h0)) node _mem_dmem_uop_T_106 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.rs2_data, UInt<1>(0h0)) node _mem_dmem_uop_T_107 = or(_mem_dmem_uop_T_105, _mem_dmem_uop_T_106) wire _mem_dmem_uop_WIRE_38 : UInt<64> connect _mem_dmem_uop_WIRE_38, _mem_dmem_uop_T_107 connect _mem_dmem_uop_WIRE.rs2_data, _mem_dmem_uop_WIRE_38 node _mem_dmem_uop_T_108 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.rs1_data, UInt<1>(0h0)) node _mem_dmem_uop_T_109 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.rs1_data, UInt<1>(0h0)) node _mem_dmem_uop_T_110 = or(_mem_dmem_uop_T_108, _mem_dmem_uop_T_109) wire _mem_dmem_uop_WIRE_39 : UInt<64> connect _mem_dmem_uop_WIRE_39, _mem_dmem_uop_T_110 connect _mem_dmem_uop_WIRE.rs1_data, _mem_dmem_uop_WIRE_39 node _mem_dmem_uop_T_111 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.needs_replay, UInt<1>(0h0)) node _mem_dmem_uop_T_112 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.needs_replay, UInt<1>(0h0)) node _mem_dmem_uop_T_113 = or(_mem_dmem_uop_T_111, _mem_dmem_uop_T_112) wire _mem_dmem_uop_WIRE_40 : UInt<1> connect _mem_dmem_uop_WIRE_40, _mem_dmem_uop_T_113 connect _mem_dmem_uop_WIRE.needs_replay, _mem_dmem_uop_WIRE_40 node _mem_dmem_uop_T_114 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.xcpt_cause, UInt<1>(0h0)) node _mem_dmem_uop_T_115 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.xcpt_cause, UInt<1>(0h0)) node _mem_dmem_uop_T_116 = or(_mem_dmem_uop_T_114, _mem_dmem_uop_T_115) wire _mem_dmem_uop_WIRE_41 : UInt<64> connect _mem_dmem_uop_WIRE_41, _mem_dmem_uop_T_116 connect _mem_dmem_uop_WIRE.xcpt_cause, _mem_dmem_uop_WIRE_41 node _mem_dmem_uop_T_117 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _mem_dmem_uop_T_118 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.xcpt, UInt<1>(0h0)) node _mem_dmem_uop_T_119 = or(_mem_dmem_uop_T_117, _mem_dmem_uop_T_118) wire _mem_dmem_uop_WIRE_42 : UInt<1> connect _mem_dmem_uop_WIRE_42, _mem_dmem_uop_T_119 connect _mem_dmem_uop_WIRE.xcpt, _mem_dmem_uop_WIRE_42 node _mem_dmem_uop_T_120 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.taken, UInt<1>(0h0)) node _mem_dmem_uop_T_121 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.taken, UInt<1>(0h0)) node _mem_dmem_uop_T_122 = or(_mem_dmem_uop_T_120, _mem_dmem_uop_T_121) wire _mem_dmem_uop_WIRE_43 : UInt<1> connect _mem_dmem_uop_WIRE_43, _mem_dmem_uop_T_122 connect _mem_dmem_uop_WIRE.taken, _mem_dmem_uop_WIRE_43 node _mem_dmem_uop_T_123 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ras_head, UInt<1>(0h0)) node _mem_dmem_uop_T_124 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ras_head, UInt<1>(0h0)) node _mem_dmem_uop_T_125 = or(_mem_dmem_uop_T_123, _mem_dmem_uop_T_124) wire _mem_dmem_uop_WIRE_44 : UInt<3> connect _mem_dmem_uop_WIRE_44, _mem_dmem_uop_T_125 connect _mem_dmem_uop_WIRE.ras_head, _mem_dmem_uop_WIRE_44 wire _mem_dmem_uop_WIRE_45 : { valid : UInt<1>, bits : UInt<40>} node _mem_dmem_uop_T_126 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.next_pc.bits, UInt<1>(0h0)) node _mem_dmem_uop_T_127 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.next_pc.bits, UInt<1>(0h0)) node _mem_dmem_uop_T_128 = or(_mem_dmem_uop_T_126, _mem_dmem_uop_T_127) wire _mem_dmem_uop_WIRE_46 : UInt<40> connect _mem_dmem_uop_WIRE_46, _mem_dmem_uop_T_128 connect _mem_dmem_uop_WIRE_45.bits, _mem_dmem_uop_WIRE_46 node _mem_dmem_uop_T_129 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.next_pc.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_130 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.next_pc.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_131 = or(_mem_dmem_uop_T_129, _mem_dmem_uop_T_130) wire _mem_dmem_uop_WIRE_47 : UInt<1> connect _mem_dmem_uop_WIRE_47, _mem_dmem_uop_T_131 connect _mem_dmem_uop_WIRE_45.valid, _mem_dmem_uop_WIRE_47 connect _mem_dmem_uop_WIRE.next_pc, _mem_dmem_uop_WIRE_45 node _mem_dmem_uop_T_132 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.sfb_shadow, UInt<1>(0h0)) node _mem_dmem_uop_T_133 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _mem_dmem_uop_T_134 = or(_mem_dmem_uop_T_132, _mem_dmem_uop_T_133) wire _mem_dmem_uop_WIRE_48 : UInt<1> connect _mem_dmem_uop_WIRE_48, _mem_dmem_uop_T_134 connect _mem_dmem_uop_WIRE.sfb_shadow, _mem_dmem_uop_WIRE_48 node _mem_dmem_uop_T_135 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.sfb_br, UInt<1>(0h0)) node _mem_dmem_uop_T_136 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.sfb_br, UInt<1>(0h0)) node _mem_dmem_uop_T_137 = or(_mem_dmem_uop_T_135, _mem_dmem_uop_T_136) wire _mem_dmem_uop_WIRE_49 : UInt<1> connect _mem_dmem_uop_WIRE_49, _mem_dmem_uop_T_137 connect _mem_dmem_uop_WIRE.sfb_br, _mem_dmem_uop_WIRE_49 wire _mem_dmem_uop_WIRE_50 : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}} wire _mem_dmem_uop_WIRE_51 : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}} wire _mem_dmem_uop_WIRE_52 : { history : UInt<8>, value : UInt<2>} node _mem_dmem_uop_T_138 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _mem_dmem_uop_T_139 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bht.value, UInt<1>(0h0)) node _mem_dmem_uop_T_140 = or(_mem_dmem_uop_T_138, _mem_dmem_uop_T_139) wire _mem_dmem_uop_WIRE_53 : UInt<2> connect _mem_dmem_uop_WIRE_53, _mem_dmem_uop_T_140 connect _mem_dmem_uop_WIRE_52.value, _mem_dmem_uop_WIRE_53 node _mem_dmem_uop_T_141 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _mem_dmem_uop_T_142 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bht.history, UInt<1>(0h0)) node _mem_dmem_uop_T_143 = or(_mem_dmem_uop_T_141, _mem_dmem_uop_T_142) wire _mem_dmem_uop_WIRE_54 : UInt<8> connect _mem_dmem_uop_WIRE_54, _mem_dmem_uop_T_143 connect _mem_dmem_uop_WIRE_52.history, _mem_dmem_uop_WIRE_54 connect _mem_dmem_uop_WIRE_51.bht, _mem_dmem_uop_WIRE_52 node _mem_dmem_uop_T_144 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _mem_dmem_uop_T_145 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.entry, UInt<1>(0h0)) node _mem_dmem_uop_T_146 = or(_mem_dmem_uop_T_144, _mem_dmem_uop_T_145) wire _mem_dmem_uop_WIRE_55 : UInt<6> connect _mem_dmem_uop_WIRE_55, _mem_dmem_uop_T_146 connect _mem_dmem_uop_WIRE_51.entry, _mem_dmem_uop_WIRE_55 node _mem_dmem_uop_T_147 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.target, UInt<1>(0h0)) node _mem_dmem_uop_T_148 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.target, UInt<1>(0h0)) node _mem_dmem_uop_T_149 = or(_mem_dmem_uop_T_147, _mem_dmem_uop_T_148) wire _mem_dmem_uop_WIRE_56 : UInt<39> connect _mem_dmem_uop_WIRE_56, _mem_dmem_uop_T_149 connect _mem_dmem_uop_WIRE_51.target, _mem_dmem_uop_WIRE_56 node _mem_dmem_uop_T_150 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _mem_dmem_uop_T_151 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.bridx, UInt<1>(0h0)) node _mem_dmem_uop_T_152 = or(_mem_dmem_uop_T_150, _mem_dmem_uop_T_151) wire _mem_dmem_uop_WIRE_57 : UInt<2> connect _mem_dmem_uop_WIRE_57, _mem_dmem_uop_T_152 connect _mem_dmem_uop_WIRE_51.bridx, _mem_dmem_uop_WIRE_57 node _mem_dmem_uop_T_153 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _mem_dmem_uop_T_154 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.mask, UInt<1>(0h0)) node _mem_dmem_uop_T_155 = or(_mem_dmem_uop_T_153, _mem_dmem_uop_T_154) wire _mem_dmem_uop_WIRE_58 : UInt<4> connect _mem_dmem_uop_WIRE_58, _mem_dmem_uop_T_155 connect _mem_dmem_uop_WIRE_51.mask, _mem_dmem_uop_WIRE_58 node _mem_dmem_uop_T_156 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _mem_dmem_uop_T_157 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.taken, UInt<1>(0h0)) node _mem_dmem_uop_T_158 = or(_mem_dmem_uop_T_156, _mem_dmem_uop_T_157) wire _mem_dmem_uop_WIRE_59 : UInt<1> connect _mem_dmem_uop_WIRE_59, _mem_dmem_uop_T_158 connect _mem_dmem_uop_WIRE_51.taken, _mem_dmem_uop_WIRE_59 node _mem_dmem_uop_T_159 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _mem_dmem_uop_T_160 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.bits.cfiType, UInt<1>(0h0)) node _mem_dmem_uop_T_161 = or(_mem_dmem_uop_T_159, _mem_dmem_uop_T_160) wire _mem_dmem_uop_WIRE_60 : UInt<2> connect _mem_dmem_uop_WIRE_60, _mem_dmem_uop_T_161 connect _mem_dmem_uop_WIRE_51.cfiType, _mem_dmem_uop_WIRE_60 connect _mem_dmem_uop_WIRE_50.bits, _mem_dmem_uop_WIRE_51 node _mem_dmem_uop_T_162 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.btb_resp.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_163 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.btb_resp.valid, UInt<1>(0h0)) node _mem_dmem_uop_T_164 = or(_mem_dmem_uop_T_162, _mem_dmem_uop_T_163) wire _mem_dmem_uop_WIRE_61 : UInt<1> connect _mem_dmem_uop_WIRE_61, _mem_dmem_uop_T_164 connect _mem_dmem_uop_WIRE_50.valid, _mem_dmem_uop_WIRE_61 connect _mem_dmem_uop_WIRE.btb_resp, _mem_dmem_uop_WIRE_50 node _mem_dmem_uop_T_165 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.sets_vcfg, UInt<1>(0h0)) node _mem_dmem_uop_T_166 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.sets_vcfg, UInt<1>(0h0)) node _mem_dmem_uop_T_167 = or(_mem_dmem_uop_T_165, _mem_dmem_uop_T_166) wire _mem_dmem_uop_WIRE_62 : UInt<1> connect _mem_dmem_uop_WIRE_62, _mem_dmem_uop_T_167 connect _mem_dmem_uop_WIRE.sets_vcfg, _mem_dmem_uop_WIRE_62 node _mem_dmem_uop_T_168 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.rvc, UInt<1>(0h0)) node _mem_dmem_uop_T_169 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.rvc, UInt<1>(0h0)) node _mem_dmem_uop_T_170 = or(_mem_dmem_uop_T_168, _mem_dmem_uop_T_169) wire _mem_dmem_uop_WIRE_63 : UInt<1> connect _mem_dmem_uop_WIRE_63, _mem_dmem_uop_T_170 connect _mem_dmem_uop_WIRE.rvc, _mem_dmem_uop_WIRE_63 wire _mem_dmem_uop_WIRE_64 : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} node _mem_dmem_uop_T_171 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_172 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_173 = or(_mem_dmem_uop_T_171, _mem_dmem_uop_T_172) wire _mem_dmem_uop_WIRE_65 : UInt<1> connect _mem_dmem_uop_WIRE_65, _mem_dmem_uop_T_173 connect _mem_dmem_uop_WIRE_64.vec, _mem_dmem_uop_WIRE_65 node _mem_dmem_uop_T_174 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _mem_dmem_uop_T_175 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.wflags, UInt<1>(0h0)) node _mem_dmem_uop_T_176 = or(_mem_dmem_uop_T_174, _mem_dmem_uop_T_175) wire _mem_dmem_uop_WIRE_66 : UInt<1> connect _mem_dmem_uop_WIRE_66, _mem_dmem_uop_T_176 connect _mem_dmem_uop_WIRE_64.wflags, _mem_dmem_uop_WIRE_66 node _mem_dmem_uop_T_177 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _mem_dmem_uop_T_178 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.sqrt, UInt<1>(0h0)) node _mem_dmem_uop_T_179 = or(_mem_dmem_uop_T_177, _mem_dmem_uop_T_178) wire _mem_dmem_uop_WIRE_67 : UInt<1> connect _mem_dmem_uop_WIRE_67, _mem_dmem_uop_T_179 connect _mem_dmem_uop_WIRE_64.sqrt, _mem_dmem_uop_WIRE_67 node _mem_dmem_uop_T_180 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.div, UInt<1>(0h0)) node _mem_dmem_uop_T_181 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.div, UInt<1>(0h0)) node _mem_dmem_uop_T_182 = or(_mem_dmem_uop_T_180, _mem_dmem_uop_T_181) wire _mem_dmem_uop_WIRE_68 : UInt<1> connect _mem_dmem_uop_WIRE_68, _mem_dmem_uop_T_182 connect _mem_dmem_uop_WIRE_64.div, _mem_dmem_uop_WIRE_68 node _mem_dmem_uop_T_183 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.fma, UInt<1>(0h0)) node _mem_dmem_uop_T_184 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.fma, UInt<1>(0h0)) node _mem_dmem_uop_T_185 = or(_mem_dmem_uop_T_183, _mem_dmem_uop_T_184) wire _mem_dmem_uop_WIRE_69 : UInt<1> connect _mem_dmem_uop_WIRE_69, _mem_dmem_uop_T_185 connect _mem_dmem_uop_WIRE_64.fma, _mem_dmem_uop_WIRE_69 node _mem_dmem_uop_T_186 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _mem_dmem_uop_T_187 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.fastpipe, UInt<1>(0h0)) node _mem_dmem_uop_T_188 = or(_mem_dmem_uop_T_186, _mem_dmem_uop_T_187) wire _mem_dmem_uop_WIRE_70 : UInt<1> connect _mem_dmem_uop_WIRE_70, _mem_dmem_uop_T_188 connect _mem_dmem_uop_WIRE_64.fastpipe, _mem_dmem_uop_WIRE_70 node _mem_dmem_uop_T_189 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.toint, UInt<1>(0h0)) node _mem_dmem_uop_T_190 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.toint, UInt<1>(0h0)) node _mem_dmem_uop_T_191 = or(_mem_dmem_uop_T_189, _mem_dmem_uop_T_190) wire _mem_dmem_uop_WIRE_71 : UInt<1> connect _mem_dmem_uop_WIRE_71, _mem_dmem_uop_T_191 connect _mem_dmem_uop_WIRE_64.toint, _mem_dmem_uop_WIRE_71 node _mem_dmem_uop_T_192 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _mem_dmem_uop_T_193 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.fromint, UInt<1>(0h0)) node _mem_dmem_uop_T_194 = or(_mem_dmem_uop_T_192, _mem_dmem_uop_T_193) wire _mem_dmem_uop_WIRE_72 : UInt<1> connect _mem_dmem_uop_WIRE_72, _mem_dmem_uop_T_194 connect _mem_dmem_uop_WIRE_64.fromint, _mem_dmem_uop_WIRE_72 node _mem_dmem_uop_T_195 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _mem_dmem_uop_T_196 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _mem_dmem_uop_T_197 = or(_mem_dmem_uop_T_195, _mem_dmem_uop_T_196) wire _mem_dmem_uop_WIRE_73 : UInt<2> connect _mem_dmem_uop_WIRE_73, _mem_dmem_uop_T_197 connect _mem_dmem_uop_WIRE_64.typeTagOut, _mem_dmem_uop_WIRE_73 node _mem_dmem_uop_T_198 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _mem_dmem_uop_T_199 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _mem_dmem_uop_T_200 = or(_mem_dmem_uop_T_198, _mem_dmem_uop_T_199) wire _mem_dmem_uop_WIRE_74 : UInt<2> connect _mem_dmem_uop_WIRE_74, _mem_dmem_uop_T_200 connect _mem_dmem_uop_WIRE_64.typeTagIn, _mem_dmem_uop_WIRE_74 node _mem_dmem_uop_T_201 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _mem_dmem_uop_T_202 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.swap23, UInt<1>(0h0)) node _mem_dmem_uop_T_203 = or(_mem_dmem_uop_T_201, _mem_dmem_uop_T_202) wire _mem_dmem_uop_WIRE_75 : UInt<1> connect _mem_dmem_uop_WIRE_75, _mem_dmem_uop_T_203 connect _mem_dmem_uop_WIRE_64.swap23, _mem_dmem_uop_WIRE_75 node _mem_dmem_uop_T_204 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _mem_dmem_uop_T_205 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.swap12, UInt<1>(0h0)) node _mem_dmem_uop_T_206 = or(_mem_dmem_uop_T_204, _mem_dmem_uop_T_205) wire _mem_dmem_uop_WIRE_76 : UInt<1> connect _mem_dmem_uop_WIRE_76, _mem_dmem_uop_T_206 connect _mem_dmem_uop_WIRE_64.swap12, _mem_dmem_uop_WIRE_76 node _mem_dmem_uop_T_207 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _mem_dmem_uop_T_208 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren3, UInt<1>(0h0)) node _mem_dmem_uop_T_209 = or(_mem_dmem_uop_T_207, _mem_dmem_uop_T_208) wire _mem_dmem_uop_WIRE_77 : UInt<1> connect _mem_dmem_uop_WIRE_77, _mem_dmem_uop_T_209 connect _mem_dmem_uop_WIRE_64.ren3, _mem_dmem_uop_WIRE_77 node _mem_dmem_uop_T_210 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _mem_dmem_uop_T_211 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren2, UInt<1>(0h0)) node _mem_dmem_uop_T_212 = or(_mem_dmem_uop_T_210, _mem_dmem_uop_T_211) wire _mem_dmem_uop_WIRE_78 : UInt<1> connect _mem_dmem_uop_WIRE_78, _mem_dmem_uop_T_212 connect _mem_dmem_uop_WIRE_64.ren2, _mem_dmem_uop_WIRE_78 node _mem_dmem_uop_T_213 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _mem_dmem_uop_T_214 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.ren1, UInt<1>(0h0)) node _mem_dmem_uop_T_215 = or(_mem_dmem_uop_T_213, _mem_dmem_uop_T_214) wire _mem_dmem_uop_WIRE_79 : UInt<1> connect _mem_dmem_uop_WIRE_79, _mem_dmem_uop_T_215 connect _mem_dmem_uop_WIRE_64.ren1, _mem_dmem_uop_WIRE_79 node _mem_dmem_uop_T_216 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.wen, UInt<1>(0h0)) node _mem_dmem_uop_T_217 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.wen, UInt<1>(0h0)) node _mem_dmem_uop_T_218 = or(_mem_dmem_uop_T_216, _mem_dmem_uop_T_217) wire _mem_dmem_uop_WIRE_80 : UInt<1> connect _mem_dmem_uop_WIRE_80, _mem_dmem_uop_T_218 connect _mem_dmem_uop_WIRE_64.wen, _mem_dmem_uop_WIRE_80 node _mem_dmem_uop_T_219 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _mem_dmem_uop_T_220 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.fp_ctrl.ldst, UInt<1>(0h0)) node _mem_dmem_uop_T_221 = or(_mem_dmem_uop_T_219, _mem_dmem_uop_T_220) wire _mem_dmem_uop_WIRE_81 : UInt<1> connect _mem_dmem_uop_WIRE_81, _mem_dmem_uop_T_221 connect _mem_dmem_uop_WIRE_64.ldst, _mem_dmem_uop_WIRE_81 connect _mem_dmem_uop_WIRE.fp_ctrl, _mem_dmem_uop_WIRE_64 wire _mem_dmem_uop_WIRE_82 : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} node _mem_dmem_uop_T_222 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_223 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.vec, UInt<1>(0h0)) node _mem_dmem_uop_T_224 = or(_mem_dmem_uop_T_222, _mem_dmem_uop_T_223) wire _mem_dmem_uop_WIRE_83 : UInt<1> connect _mem_dmem_uop_WIRE_83, _mem_dmem_uop_T_224 connect _mem_dmem_uop_WIRE_82.vec, _mem_dmem_uop_WIRE_83 node _mem_dmem_uop_T_225 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.dp, UInt<1>(0h0)) node _mem_dmem_uop_T_226 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.dp, UInt<1>(0h0)) node _mem_dmem_uop_T_227 = or(_mem_dmem_uop_T_225, _mem_dmem_uop_T_226) wire _mem_dmem_uop_WIRE_84 : UInt<1> connect _mem_dmem_uop_WIRE_84, _mem_dmem_uop_T_227 connect _mem_dmem_uop_WIRE_82.dp, _mem_dmem_uop_WIRE_84 node _mem_dmem_uop_T_228 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.amo, UInt<1>(0h0)) node _mem_dmem_uop_T_229 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.amo, UInt<1>(0h0)) node _mem_dmem_uop_T_230 = or(_mem_dmem_uop_T_228, _mem_dmem_uop_T_229) wire _mem_dmem_uop_WIRE_85 : UInt<1> connect _mem_dmem_uop_WIRE_85, _mem_dmem_uop_T_230 connect _mem_dmem_uop_WIRE_82.amo, _mem_dmem_uop_WIRE_85 node _mem_dmem_uop_T_231 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.fence, UInt<1>(0h0)) node _mem_dmem_uop_T_232 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.fence, UInt<1>(0h0)) node _mem_dmem_uop_T_233 = or(_mem_dmem_uop_T_231, _mem_dmem_uop_T_232) wire _mem_dmem_uop_WIRE_86 : UInt<1> connect _mem_dmem_uop_WIRE_86, _mem_dmem_uop_T_233 connect _mem_dmem_uop_WIRE_82.fence, _mem_dmem_uop_WIRE_86 node _mem_dmem_uop_T_234 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.fence_i, UInt<1>(0h0)) node _mem_dmem_uop_T_235 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.fence_i, UInt<1>(0h0)) node _mem_dmem_uop_T_236 = or(_mem_dmem_uop_T_234, _mem_dmem_uop_T_235) wire _mem_dmem_uop_WIRE_87 : UInt<1> connect _mem_dmem_uop_WIRE_87, _mem_dmem_uop_T_236 connect _mem_dmem_uop_WIRE_82.fence_i, _mem_dmem_uop_WIRE_87 node _mem_dmem_uop_T_237 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.csr, UInt<1>(0h0)) node _mem_dmem_uop_T_238 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.csr, UInt<1>(0h0)) node _mem_dmem_uop_T_239 = or(_mem_dmem_uop_T_237, _mem_dmem_uop_T_238) wire _mem_dmem_uop_WIRE_88 : UInt<3> connect _mem_dmem_uop_WIRE_88, _mem_dmem_uop_T_239 connect _mem_dmem_uop_WIRE_82.csr, _mem_dmem_uop_WIRE_88 node _mem_dmem_uop_T_240 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.wxd, UInt<1>(0h0)) node _mem_dmem_uop_T_241 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.wxd, UInt<1>(0h0)) node _mem_dmem_uop_T_242 = or(_mem_dmem_uop_T_240, _mem_dmem_uop_T_241) wire _mem_dmem_uop_WIRE_89 : UInt<1> connect _mem_dmem_uop_WIRE_89, _mem_dmem_uop_T_242 connect _mem_dmem_uop_WIRE_82.wxd, _mem_dmem_uop_WIRE_89 node _mem_dmem_uop_T_243 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.div, UInt<1>(0h0)) node _mem_dmem_uop_T_244 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.div, UInt<1>(0h0)) node _mem_dmem_uop_T_245 = or(_mem_dmem_uop_T_243, _mem_dmem_uop_T_244) wire _mem_dmem_uop_WIRE_90 : UInt<1> connect _mem_dmem_uop_WIRE_90, _mem_dmem_uop_T_245 connect _mem_dmem_uop_WIRE_82.div, _mem_dmem_uop_WIRE_90 node _mem_dmem_uop_T_246 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.mul, UInt<1>(0h0)) node _mem_dmem_uop_T_247 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.mul, UInt<1>(0h0)) node _mem_dmem_uop_T_248 = or(_mem_dmem_uop_T_246, _mem_dmem_uop_T_247) wire _mem_dmem_uop_WIRE_91 : UInt<1> connect _mem_dmem_uop_WIRE_91, _mem_dmem_uop_T_248 connect _mem_dmem_uop_WIRE_82.mul, _mem_dmem_uop_WIRE_91 node _mem_dmem_uop_T_249 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.wfd, UInt<1>(0h0)) node _mem_dmem_uop_T_250 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.wfd, UInt<1>(0h0)) node _mem_dmem_uop_T_251 = or(_mem_dmem_uop_T_249, _mem_dmem_uop_T_250) wire _mem_dmem_uop_WIRE_92 : UInt<1> connect _mem_dmem_uop_WIRE_92, _mem_dmem_uop_T_251 connect _mem_dmem_uop_WIRE_82.wfd, _mem_dmem_uop_WIRE_92 node _mem_dmem_uop_T_252 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rfs3, UInt<1>(0h0)) node _mem_dmem_uop_T_253 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rfs3, UInt<1>(0h0)) node _mem_dmem_uop_T_254 = or(_mem_dmem_uop_T_252, _mem_dmem_uop_T_253) wire _mem_dmem_uop_WIRE_93 : UInt<1> connect _mem_dmem_uop_WIRE_93, _mem_dmem_uop_T_254 connect _mem_dmem_uop_WIRE_82.rfs3, _mem_dmem_uop_WIRE_93 node _mem_dmem_uop_T_255 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rfs2, UInt<1>(0h0)) node _mem_dmem_uop_T_256 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rfs2, UInt<1>(0h0)) node _mem_dmem_uop_T_257 = or(_mem_dmem_uop_T_255, _mem_dmem_uop_T_256) wire _mem_dmem_uop_WIRE_94 : UInt<1> connect _mem_dmem_uop_WIRE_94, _mem_dmem_uop_T_257 connect _mem_dmem_uop_WIRE_82.rfs2, _mem_dmem_uop_WIRE_94 node _mem_dmem_uop_T_258 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rfs1, UInt<1>(0h0)) node _mem_dmem_uop_T_259 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rfs1, UInt<1>(0h0)) node _mem_dmem_uop_T_260 = or(_mem_dmem_uop_T_258, _mem_dmem_uop_T_259) wire _mem_dmem_uop_WIRE_95 : UInt<1> connect _mem_dmem_uop_WIRE_95, _mem_dmem_uop_T_260 connect _mem_dmem_uop_WIRE_82.rfs1, _mem_dmem_uop_WIRE_95 node _mem_dmem_uop_T_261 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _mem_dmem_uop_T_262 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.mem_cmd, UInt<1>(0h0)) node _mem_dmem_uop_T_263 = or(_mem_dmem_uop_T_261, _mem_dmem_uop_T_262) wire _mem_dmem_uop_WIRE_96 : UInt<5> connect _mem_dmem_uop_WIRE_96, _mem_dmem_uop_T_263 connect _mem_dmem_uop_WIRE_82.mem_cmd, _mem_dmem_uop_WIRE_96 node _mem_dmem_uop_T_264 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.mem, UInt<1>(0h0)) node _mem_dmem_uop_T_265 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.mem, UInt<1>(0h0)) node _mem_dmem_uop_T_266 = or(_mem_dmem_uop_T_264, _mem_dmem_uop_T_265) wire _mem_dmem_uop_WIRE_97 : UInt<1> connect _mem_dmem_uop_WIRE_97, _mem_dmem_uop_T_266 connect _mem_dmem_uop_WIRE_82.mem, _mem_dmem_uop_WIRE_97 node _mem_dmem_uop_T_267 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.alu_fn, UInt<1>(0h0)) node _mem_dmem_uop_T_268 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.alu_fn, UInt<1>(0h0)) node _mem_dmem_uop_T_269 = or(_mem_dmem_uop_T_267, _mem_dmem_uop_T_268) wire _mem_dmem_uop_WIRE_98 : UInt<5> connect _mem_dmem_uop_WIRE_98, _mem_dmem_uop_T_269 connect _mem_dmem_uop_WIRE_82.alu_fn, _mem_dmem_uop_WIRE_98 node _mem_dmem_uop_T_270 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.alu_dw, UInt<1>(0h0)) node _mem_dmem_uop_T_271 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.alu_dw, UInt<1>(0h0)) node _mem_dmem_uop_T_272 = or(_mem_dmem_uop_T_270, _mem_dmem_uop_T_271) wire _mem_dmem_uop_WIRE_99 : UInt<1> connect _mem_dmem_uop_WIRE_99, _mem_dmem_uop_T_272 connect _mem_dmem_uop_WIRE_82.alu_dw, _mem_dmem_uop_WIRE_99 node _mem_dmem_uop_T_273 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.sel_imm, UInt<1>(0h0)) node _mem_dmem_uop_T_274 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.sel_imm, UInt<1>(0h0)) node _mem_dmem_uop_T_275 = or(_mem_dmem_uop_T_273, _mem_dmem_uop_T_274) wire _mem_dmem_uop_WIRE_100 : UInt<3> connect _mem_dmem_uop_WIRE_100, _mem_dmem_uop_T_275 connect _mem_dmem_uop_WIRE_82.sel_imm, _mem_dmem_uop_WIRE_100 node _mem_dmem_uop_T_276 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _mem_dmem_uop_T_277 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.sel_alu1, UInt<1>(0h0)) node _mem_dmem_uop_T_278 = or(_mem_dmem_uop_T_276, _mem_dmem_uop_T_277) wire _mem_dmem_uop_WIRE_101 : UInt<2> connect _mem_dmem_uop_WIRE_101, _mem_dmem_uop_T_278 connect _mem_dmem_uop_WIRE_82.sel_alu1, _mem_dmem_uop_WIRE_101 node _mem_dmem_uop_T_279 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _mem_dmem_uop_T_280 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.sel_alu2, UInt<1>(0h0)) node _mem_dmem_uop_T_281 = or(_mem_dmem_uop_T_279, _mem_dmem_uop_T_280) wire _mem_dmem_uop_WIRE_102 : UInt<3> connect _mem_dmem_uop_WIRE_102, _mem_dmem_uop_T_281 connect _mem_dmem_uop_WIRE_82.sel_alu2, _mem_dmem_uop_WIRE_102 node _mem_dmem_uop_T_282 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rxs1, UInt<1>(0h0)) node _mem_dmem_uop_T_283 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rxs1, UInt<1>(0h0)) node _mem_dmem_uop_T_284 = or(_mem_dmem_uop_T_282, _mem_dmem_uop_T_283) wire _mem_dmem_uop_WIRE_103 : UInt<1> connect _mem_dmem_uop_WIRE_103, _mem_dmem_uop_T_284 connect _mem_dmem_uop_WIRE_82.rxs1, _mem_dmem_uop_WIRE_103 node _mem_dmem_uop_T_285 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rxs2, UInt<1>(0h0)) node _mem_dmem_uop_T_286 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rxs2, UInt<1>(0h0)) node _mem_dmem_uop_T_287 = or(_mem_dmem_uop_T_285, _mem_dmem_uop_T_286) wire _mem_dmem_uop_WIRE_104 : UInt<1> connect _mem_dmem_uop_WIRE_104, _mem_dmem_uop_T_287 connect _mem_dmem_uop_WIRE_82.rxs2, _mem_dmem_uop_WIRE_104 node _mem_dmem_uop_T_288 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_dmem_uop_T_289 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.jalr, UInt<1>(0h0)) node _mem_dmem_uop_T_290 = or(_mem_dmem_uop_T_288, _mem_dmem_uop_T_289) wire _mem_dmem_uop_WIRE_105 : UInt<1> connect _mem_dmem_uop_WIRE_105, _mem_dmem_uop_T_290 connect _mem_dmem_uop_WIRE_82.jalr, _mem_dmem_uop_WIRE_105 node _mem_dmem_uop_T_291 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.jal, UInt<1>(0h0)) node _mem_dmem_uop_T_292 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.jal, UInt<1>(0h0)) node _mem_dmem_uop_T_293 = or(_mem_dmem_uop_T_291, _mem_dmem_uop_T_292) wire _mem_dmem_uop_WIRE_106 : UInt<1> connect _mem_dmem_uop_WIRE_106, _mem_dmem_uop_T_293 connect _mem_dmem_uop_WIRE_82.jal, _mem_dmem_uop_WIRE_106 node _mem_dmem_uop_T_294 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.branch, UInt<1>(0h0)) node _mem_dmem_uop_T_295 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.branch, UInt<1>(0h0)) node _mem_dmem_uop_T_296 = or(_mem_dmem_uop_T_294, _mem_dmem_uop_T_295) wire _mem_dmem_uop_WIRE_107 : UInt<1> connect _mem_dmem_uop_WIRE_107, _mem_dmem_uop_T_296 connect _mem_dmem_uop_WIRE_82.branch, _mem_dmem_uop_WIRE_107 node _mem_dmem_uop_T_297 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_dmem_uop_T_298 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.rocc, UInt<1>(0h0)) node _mem_dmem_uop_T_299 = or(_mem_dmem_uop_T_297, _mem_dmem_uop_T_298) wire _mem_dmem_uop_WIRE_108 : UInt<1> connect _mem_dmem_uop_WIRE_108, _mem_dmem_uop_T_299 connect _mem_dmem_uop_WIRE_82.rocc, _mem_dmem_uop_WIRE_108 node _mem_dmem_uop_T_300 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.fp, UInt<1>(0h0)) node _mem_dmem_uop_T_301 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.fp, UInt<1>(0h0)) node _mem_dmem_uop_T_302 = or(_mem_dmem_uop_T_300, _mem_dmem_uop_T_301) wire _mem_dmem_uop_WIRE_109 : UInt<1> connect _mem_dmem_uop_WIRE_109, _mem_dmem_uop_T_302 connect _mem_dmem_uop_WIRE_82.fp, _mem_dmem_uop_WIRE_109 node _mem_dmem_uop_T_303 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.ctrl.legal, UInt<1>(0h0)) node _mem_dmem_uop_T_304 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.ctrl.legal, UInt<1>(0h0)) node _mem_dmem_uop_T_305 = or(_mem_dmem_uop_T_303, _mem_dmem_uop_T_304) wire _mem_dmem_uop_WIRE_110 : UInt<1> connect _mem_dmem_uop_WIRE_110, _mem_dmem_uop_T_305 connect _mem_dmem_uop_WIRE_82.legal, _mem_dmem_uop_WIRE_110 connect _mem_dmem_uop_WIRE.ctrl, _mem_dmem_uop_WIRE_82 node _mem_dmem_uop_T_306 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.edge_inst, UInt<1>(0h0)) node _mem_dmem_uop_T_307 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.edge_inst, UInt<1>(0h0)) node _mem_dmem_uop_T_308 = or(_mem_dmem_uop_T_306, _mem_dmem_uop_T_307) wire _mem_dmem_uop_WIRE_111 : UInt<1> connect _mem_dmem_uop_WIRE_111, _mem_dmem_uop_T_308 connect _mem_dmem_uop_WIRE.edge_inst, _mem_dmem_uop_WIRE_111 node _mem_dmem_uop_T_309 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.pc, UInt<1>(0h0)) node _mem_dmem_uop_T_310 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.pc, UInt<1>(0h0)) node _mem_dmem_uop_T_311 = or(_mem_dmem_uop_T_309, _mem_dmem_uop_T_310) wire _mem_dmem_uop_WIRE_112 : UInt<40> connect _mem_dmem_uop_WIRE_112, _mem_dmem_uop_T_311 connect _mem_dmem_uop_WIRE.pc, _mem_dmem_uop_WIRE_112 node _mem_dmem_uop_T_312 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.raw_inst, UInt<1>(0h0)) node _mem_dmem_uop_T_313 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.raw_inst, UInt<1>(0h0)) node _mem_dmem_uop_T_314 = or(_mem_dmem_uop_T_312, _mem_dmem_uop_T_313) wire _mem_dmem_uop_WIRE_113 : UInt<32> connect _mem_dmem_uop_WIRE_113, _mem_dmem_uop_T_314 connect _mem_dmem_uop_WIRE.raw_inst, _mem_dmem_uop_WIRE_113 node _mem_dmem_uop_T_315 = mux(mem_dmem_oh_0, mem_uops_reg[0].bits.inst, UInt<1>(0h0)) node _mem_dmem_uop_T_316 = mux(mem_dmem_oh_1, mem_uops_reg[1].bits.inst, UInt<1>(0h0)) node _mem_dmem_uop_T_317 = or(_mem_dmem_uop_T_315, _mem_dmem_uop_T_316) wire _mem_dmem_uop_WIRE_114 : UInt<32> connect _mem_dmem_uop_WIRE_114, _mem_dmem_uop_T_317 connect _mem_dmem_uop_WIRE.inst, _mem_dmem_uop_WIRE_114 connect mem_dmem_uop.bits, _mem_dmem_uop_WIRE node _mem_dmem_uop_T_318 = mux(mem_dmem_oh_0, mem_uops_reg[0].valid, UInt<1>(0h0)) node _mem_dmem_uop_T_319 = mux(mem_dmem_oh_1, mem_uops_reg[1].valid, UInt<1>(0h0)) node _mem_dmem_uop_T_320 = or(_mem_dmem_uop_T_318, _mem_dmem_uop_T_319) wire _mem_dmem_uop_WIRE_115 : UInt<1> connect _mem_dmem_uop_WIRE_115, _mem_dmem_uop_T_320 connect mem_dmem_uop.valid, _mem_dmem_uop_WIRE_115 connect dtlb.io.ptw.customCSRs, io.ptw_tlb.customCSRs connect dtlb.io.ptw.gstatus, io.ptw_tlb.gstatus connect dtlb.io.ptw.hstatus, io.ptw_tlb.hstatus connect dtlb.io.ptw.status, io.ptw_tlb.status connect dtlb.io.ptw.vsatp, io.ptw_tlb.vsatp connect dtlb.io.ptw.hgatp, io.ptw_tlb.hgatp connect dtlb.io.ptw.ptbr, io.ptw_tlb.ptbr connect dtlb.io.ptw.resp, io.ptw_tlb.resp connect io.ptw_tlb.req.bits, dtlb.io.ptw.req.bits connect io.ptw_tlb.req.valid, dtlb.io.ptw.req.valid connect dtlb.io.ptw.req.ready, io.ptw_tlb.req.ready connect dtlb.io.req[0].valid, mem_dmem_uop.valid node _dtlb_io_req_0_bits_vaddr_T = or(ex_uops_reg[0].valid, ex_uops_reg[1].valid) reg dtlb_io_req_0_bits_vaddr_r : UInt<40>, clock when _dtlb_io_req_0_bits_vaddr_T : connect dtlb_io_req_0_bits_vaddr_r, io.dmem.req.bits.addr connect dtlb.io.req[0].bits.vaddr, dtlb_io_req_0_bits_vaddr_r connect dtlb.io.req[0].bits.size, mem_dmem_uop.bits.mem_size connect dtlb.io.req[0].bits.cmd, mem_dmem_uop.bits.ctrl.mem_cmd connect dtlb.io.req[0].bits.prv, csr.io.status.dprv node _dtlb_io_sfence_valid_T = eq(mem_dmem_uop.bits.ctrl.mem_cmd, UInt<5>(0h14)) node _dtlb_io_sfence_valid_T_1 = and(mem_dmem_uop.valid, _dtlb_io_sfence_valid_T) connect dtlb.io.sfence.valid, _dtlb_io_sfence_valid_T_1 node _dtlb_io_sfence_bits_rs1_T = bits(mem_dmem_uop.bits.mem_size, 0, 0) connect dtlb.io.sfence.bits.rs1, _dtlb_io_sfence_bits_rs1_T node _dtlb_io_sfence_bits_rs2_T = bits(mem_dmem_uop.bits.mem_size, 1, 1) connect dtlb.io.sfence.bits.rs2, _dtlb_io_sfence_bits_rs2_T connect dtlb.io.sfence.bits.addr, dtlb.io.req[0].bits.vaddr connect dtlb.io.sfence.bits.asid, mem_dmem_uop.bits.rs2_data connect dtlb.io.sfence.bits.hv, UInt<1>(0h0) connect dtlb.io.sfence.bits.hg, UInt<1>(0h0) connect io.dmem.keep_clock_enabled, UInt<1>(0h1) connect io.dmem.s1_paddr, dtlb.io.resp[0].paddr connect io.dmem.s1_data.data, mem_dmem_uop.bits.rs2_data invalidate io.dmem.s1_data.mask node _T_151 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.jalr) node _T_152 = and(_T_151, csr.io.status.debug) when _T_152 : connect io.imem.flush_icache, UInt<1>(0h1) node _T_153 = and(mem_brjmp_oh_0, mem_uops_reg[0].bits.ctrl.jalr) when _T_153 : connect com_uops_reg[0].bits.wdata.valid, UInt<1>(0h1) node _com_uops_reg_0_bits_wdata_bits_T = asUInt(mem_brjmp_target) node _com_uops_reg_0_bits_wdata_bits_T_1 = bits(_com_uops_reg_0_bits_wdata_bits_T, 39, 39) node _com_uops_reg_0_bits_wdata_bits_T_2 = mux(_com_uops_reg_0_bits_wdata_bits_T_1, UInt<24>(0hffffff), UInt<24>(0h0)) node _com_uops_reg_0_bits_wdata_bits_T_3 = cat(_com_uops_reg_0_bits_wdata_bits_T_2, _com_uops_reg_0_bits_wdata_bits_T) connect com_uops_reg[0].bits.wdata.bits, _com_uops_reg_0_bits_wdata_bits_T_3 node _T_154 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.mem) node _T_155 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<1>(0h1)) node _T_156 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<5>(0h11)) node _T_157 = or(_T_155, _T_156) node _T_158 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<3>(0h7)) node _T_159 = or(_T_157, _T_158) node _T_160 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<3>(0h4)) node _T_161 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0h9)) node _T_162 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0ha)) node _T_163 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0hb)) node _T_164 = or(_T_160, _T_161) node _T_165 = or(_T_164, _T_162) node _T_166 = or(_T_165, _T_163) node _T_167 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0h8)) node _T_168 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0hc)) node _T_169 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0hd)) node _T_170 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0he)) node _T_171 = eq(mem_uops_reg[0].bits.ctrl.mem_cmd, UInt<4>(0hf)) node _T_172 = or(_T_167, _T_168) node _T_173 = or(_T_172, _T_169) node _T_174 = or(_T_173, _T_170) node _T_175 = or(_T_174, _T_171) node _T_176 = or(_T_166, _T_175) node _T_177 = or(_T_159, _T_176) node _T_178 = and(_T_154, _T_177) node _T_179 = and(_T_178, mem_uops_reg[0].bits.ctrl.fp) when _T_179 : connect io.dmem.s1_data.data, fp_pipe.io.s1_store_data node _T_180 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.fp) node _T_181 = and(_T_180, mem_uops_reg[0].bits.ctrl.wxd) when _T_181 : connect com_uops_reg[0].bits.wdata.valid, UInt<1>(0h1) connect com_uops_reg[0].bits.wdata.bits, fp_pipe.io.s1_fpiu_toint connect com_uops_reg[0].bits.fexc, fp_pipe.io.s1_fpiu_fexc connect com_uops_reg[0].bits.fdivin, fp_pipe.io.s1_fpiu_fdiv node _T_182 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.mem) node _T_183 = eq(dtlb.io.sfence.valid, UInt<1>(0h0)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(dtlb.io.req[0].ready, UInt<1>(0h0)) node _T_186 = or(_T_185, dtlb.io.resp[0].miss) node _T_187 = and(_T_184, _T_186) when _T_187 : connect com_uops_reg[0].bits.needs_replay, UInt<1>(0h1) node _T_188 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].ma.st) node _T_189 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].ma.ld) node _T_190 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].pf.st) node _T_191 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].pf.ld) node _T_192 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].ae.st) node _T_193 = and(mem_uops_reg[0].bits.ctrl.mem, dtlb.io.resp[0].ae.ld) node _T_194 = or(mem_uops_reg[0].bits.xcpt, _T_188) node _T_195 = or(_T_194, _T_189) node _T_196 = or(_T_195, _T_190) node _T_197 = or(_T_196, _T_191) node _T_198 = or(_T_197, _T_192) node xcpt_2 = or(_T_198, _T_193) node _T_199 = mux(_T_192, UInt<3>(0h7), UInt<3>(0h5)) node _T_200 = mux(_T_191, UInt<4>(0hd), _T_199) node _T_201 = mux(_T_190, UInt<4>(0hf), _T_200) node _T_202 = mux(_T_189, UInt<3>(0h4), _T_201) node _T_203 = mux(_T_188, UInt<3>(0h6), _T_202) node cause_2 = mux(mem_uops_reg[0].bits.xcpt, mem_uops_reg[0].bits.xcpt_cause, _T_203) when mem_uops_reg[0].valid : connect com_uops_reg[0].bits.xcpt, xcpt_2 connect com_uops_reg[0].bits.xcpt_cause, cause_2 wire sfb_shadow_kill : UInt<1> connect sfb_shadow_kill, UInt<1>(0h0) node _mem_bypasses_0_valid_T = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.wxd) node _mem_bypasses_0_valid_T_1 = eq(sfb_shadow_kill, UInt<1>(0h0)) node _mem_bypasses_0_valid_T_2 = and(_mem_bypasses_0_valid_T, _mem_bypasses_0_valid_T_1) connect mem_bypasses_0.valid, _mem_bypasses_0_valid_T_2 node _mem_bypasses_0_dst_T = bits(mem_uops_reg[0].bits.inst, 11, 7) connect mem_bypasses_0.dst, _mem_bypasses_0_dst_T connect mem_bypasses_0.can_bypass, mem_uops_reg[0].bits.wdata.valid connect mem_bypasses_0.data, mem_uops_reg[0].bits.wdata.bits node _fp_mem_bypasses_0_valid_T = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.wfd) node _fp_mem_bypasses_0_valid_T_1 = eq(sfb_shadow_kill, UInt<1>(0h0)) node _fp_mem_bypasses_0_valid_T_2 = and(_fp_mem_bypasses_0_valid_T, _fp_mem_bypasses_0_valid_T_1) connect fp_mem_bypasses_0.valid, _fp_mem_bypasses_0_valid_T_2 node _fp_mem_bypasses_0_dst_T = bits(mem_uops_reg[0].bits.inst, 11, 7) connect fp_mem_bypasses_0.dst, _fp_mem_bypasses_0_dst_T connect fp_mem_bypasses_0.can_bypass, UInt<1>(0h0) invalidate fp_mem_bypasses_0.data node _T_204 = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.jalr) node _T_205 = and(_T_204, csr.io.status.debug) when _T_205 : connect io.imem.flush_icache, UInt<1>(0h1) node _T_206 = and(mem_brjmp_oh_1, mem_uops_reg[1].bits.ctrl.jalr) when _T_206 : connect com_uops_reg[1].bits.wdata.valid, UInt<1>(0h1) node _com_uops_reg_1_bits_wdata_bits_T = asUInt(mem_brjmp_target) node _com_uops_reg_1_bits_wdata_bits_T_1 = bits(_com_uops_reg_1_bits_wdata_bits_T, 39, 39) node _com_uops_reg_1_bits_wdata_bits_T_2 = mux(_com_uops_reg_1_bits_wdata_bits_T_1, UInt<24>(0hffffff), UInt<24>(0h0)) node _com_uops_reg_1_bits_wdata_bits_T_3 = cat(_com_uops_reg_1_bits_wdata_bits_T_2, _com_uops_reg_1_bits_wdata_bits_T) connect com_uops_reg[1].bits.wdata.bits, _com_uops_reg_1_bits_wdata_bits_T_3 node _T_207 = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.mem) node _T_208 = eq(dtlb.io.sfence.valid, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(dtlb.io.req[0].ready, UInt<1>(0h0)) node _T_211 = or(_T_210, dtlb.io.resp[0].miss) node _T_212 = and(_T_209, _T_211) when _T_212 : connect com_uops_reg[1].bits.needs_replay, UInt<1>(0h1) node _T_213 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].ma.st) node _T_214 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].ma.ld) node _T_215 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].pf.st) node _T_216 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].pf.ld) node _T_217 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].ae.st) node _T_218 = and(mem_uops_reg[1].bits.ctrl.mem, dtlb.io.resp[0].ae.ld) node _T_219 = or(mem_uops_reg[0].bits.xcpt, _T_213) node _T_220 = or(_T_219, _T_214) node _T_221 = or(_T_220, _T_215) node _T_222 = or(_T_221, _T_216) node _T_223 = or(_T_222, _T_217) node xcpt_3 = or(_T_223, _T_218) node _T_224 = mux(_T_217, UInt<3>(0h7), UInt<3>(0h5)) node _T_225 = mux(_T_216, UInt<4>(0hd), _T_224) node _T_226 = mux(_T_215, UInt<4>(0hf), _T_225) node _T_227 = mux(_T_214, UInt<3>(0h4), _T_226) node _T_228 = mux(_T_213, UInt<3>(0h6), _T_227) node cause_3 = mux(mem_uops_reg[0].bits.xcpt, mem_uops_reg[0].bits.xcpt_cause, _T_228) when mem_uops_reg[1].valid : connect com_uops_reg[1].bits.xcpt, xcpt_3 connect com_uops_reg[1].bits.xcpt_cause, cause_3 wire sfb_shadow_kill_1 : UInt<1> connect sfb_shadow_kill_1, UInt<1>(0h0) node _T_229 = and(mem_brjmp_taken, mem_uops_reg[1].bits.sfb_shadow) when _T_229 : connect sfb_shadow_kill_1, UInt<1>(0h1) connect com_uops_reg[1].valid, UInt<1>(0h0) node _T_230 = eq(mem_uops_reg[1].bits.sfb_shadow, UInt<1>(0h0)) node _T_231 = and(mem_brjmp_oh_0, _T_230) node _T_232 = and(_T_231, mem_brjmp_mispredict) when _T_232 : connect com_uops_reg[1].valid, UInt<1>(0h0) when mem_uops_reg[1].bits.ctrl.mem : connect io.dmem.s1_kill, UInt<1>(0h1) node _T_233 = and(mem_uops_reg[1].bits.fp_ctrl.ldst, mem_uops_reg[1].bits.fp_ctrl.wen) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = and(mem_uops_reg[1].bits.ctrl.fp, _T_234) when _T_235 : connect fp_pipe.io.s1_kill, UInt<1>(0h1) node _T_236 = and(UInt<1>(0h0), mem_uops_reg[0].bits.sets_vcfg) node _T_237 = or(mem_uops_reg[1].bits.ctrl.vec, _T_236) when _T_237 : skip node _mem_bypasses_1_valid_T = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.wxd) node _mem_bypasses_1_valid_T_1 = eq(sfb_shadow_kill_1, UInt<1>(0h0)) node _mem_bypasses_1_valid_T_2 = and(_mem_bypasses_1_valid_T, _mem_bypasses_1_valid_T_1) connect mem_bypasses_1.valid, _mem_bypasses_1_valid_T_2 node _mem_bypasses_1_dst_T = bits(mem_uops_reg[1].bits.inst, 11, 7) connect mem_bypasses_1.dst, _mem_bypasses_1_dst_T connect mem_bypasses_1.can_bypass, mem_uops_reg[1].bits.wdata.valid connect mem_bypasses_1.data, mem_uops_reg[1].bits.wdata.bits node _fp_mem_bypasses_1_valid_T = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.wfd) node _fp_mem_bypasses_1_valid_T_1 = eq(sfb_shadow_kill_1, UInt<1>(0h0)) node _fp_mem_bypasses_1_valid_T_2 = and(_fp_mem_bypasses_1_valid_T, _fp_mem_bypasses_1_valid_T_1) connect fp_mem_bypasses_1.valid, _fp_mem_bypasses_1_valid_T_2 node _fp_mem_bypasses_1_dst_T = bits(mem_uops_reg[1].bits.inst, 11, 7) connect fp_mem_bypasses_1.dst, _fp_mem_bypasses_1_dst_T connect fp_mem_bypasses_1.can_bypass, UInt<1>(0h0) invalidate fp_mem_bypasses_1.data wire mem_alu_uops_0 : { inst : UInt<32>, raw_inst : UInt<32>, pc : UInt<40>, edge_inst : UInt<1>, ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rvc : UInt<1>, sets_vcfg : UInt<1>, btb_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<4>, bridx : UInt<2>, target : UInt<39>, entry : UInt<6>, bht : { history : UInt<8>, value : UInt<2>}}}, sfb_br : UInt<1>, sfb_shadow : UInt<1>, next_pc : { valid : UInt<1>, bits : UInt<40>}, ras_head : UInt<3>, taken : UInt<1>, xcpt : UInt<1>, xcpt_cause : UInt<64>, needs_replay : UInt<1>, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, uses_memalu : UInt<1>, uses_latealu : UInt<1>, wdata : { valid : UInt<1>, bits : UInt<64>}, fra1 : UInt<5>, fra2 : UInt<5>, fra3 : UInt<5>, fexc : UInt<5>, fdivin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, mem_size : UInt<2>, flush_pipe : UInt<1>} inst mem_alus_0 of ALU_2 connect mem_alus_0.clock, clock connect mem_alus_0.reset, reset connect mem_alu_uops_0.flush_pipe, mem_uops_reg[1].bits.flush_pipe connect mem_alu_uops_0.mem_size, mem_uops_reg[1].bits.mem_size connect mem_alu_uops_0.fdivin, mem_uops_reg[1].bits.fdivin connect mem_alu_uops_0.fexc, mem_uops_reg[1].bits.fexc connect mem_alu_uops_0.fra3, mem_uops_reg[1].bits.fra3 connect mem_alu_uops_0.fra2, mem_uops_reg[1].bits.fra2 connect mem_alu_uops_0.fra1, mem_uops_reg[1].bits.fra1 connect mem_alu_uops_0.wdata, mem_uops_reg[1].bits.wdata connect mem_alu_uops_0.uses_latealu, mem_uops_reg[1].bits.uses_latealu connect mem_alu_uops_0.uses_memalu, mem_uops_reg[1].bits.uses_memalu connect mem_alu_uops_0.rs3_data, mem_uops_reg[1].bits.rs3_data connect mem_alu_uops_0.rs2_data, mem_uops_reg[1].bits.rs2_data connect mem_alu_uops_0.rs1_data, mem_uops_reg[1].bits.rs1_data connect mem_alu_uops_0.needs_replay, mem_uops_reg[1].bits.needs_replay connect mem_alu_uops_0.xcpt_cause, mem_uops_reg[1].bits.xcpt_cause connect mem_alu_uops_0.xcpt, mem_uops_reg[1].bits.xcpt connect mem_alu_uops_0.taken, mem_uops_reg[1].bits.taken connect mem_alu_uops_0.ras_head, mem_uops_reg[1].bits.ras_head connect mem_alu_uops_0.next_pc, mem_uops_reg[1].bits.next_pc connect mem_alu_uops_0.sfb_shadow, mem_uops_reg[1].bits.sfb_shadow connect mem_alu_uops_0.sfb_br, mem_uops_reg[1].bits.sfb_br connect mem_alu_uops_0.btb_resp, mem_uops_reg[1].bits.btb_resp connect mem_alu_uops_0.sets_vcfg, mem_uops_reg[1].bits.sets_vcfg connect mem_alu_uops_0.rvc, mem_uops_reg[1].bits.rvc connect mem_alu_uops_0.fp_ctrl, mem_uops_reg[1].bits.fp_ctrl connect mem_alu_uops_0.ctrl, mem_uops_reg[1].bits.ctrl connect mem_alu_uops_0.edge_inst, mem_uops_reg[1].bits.edge_inst connect mem_alu_uops_0.pc, mem_uops_reg[1].bits.pc connect mem_alu_uops_0.raw_inst, mem_uops_reg[1].bits.raw_inst connect mem_alu_uops_0.inst, mem_uops_reg[1].bits.inst node _T_238 = bits(mem_uops_reg[1].bits.inst, 19, 15) node _T_239 = bits(mem_uops_reg[0].bits.inst, 11, 7) node _T_240 = eq(_T_238, _T_239) when _T_240 : connect mem_alu_uops_0.rs1_data, mem_uops_reg[0].bits.wdata.bits node _T_241 = bits(mem_uops_reg[1].bits.inst, 24, 20) node _T_242 = bits(mem_uops_reg[0].bits.inst, 11, 7) node _T_243 = eq(_T_241, _T_242) when _T_243 : connect mem_alu_uops_0.rs2_data, mem_uops_reg[0].bits.wdata.bits node _imm_sign_T_6 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h5)) node _imm_sign_T_7 = bits(mem_alu_uops_0.inst, 31, 31) node _imm_sign_T_8 = asSInt(_imm_sign_T_7) node imm_sign_2 = mux(_imm_sign_T_6, asSInt(UInt<1>(0h0)), _imm_sign_T_8) node _imm_b30_20_T_6 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b30_20_T_7 = bits(mem_alu_uops_0.inst, 30, 20) node _imm_b30_20_T_8 = asSInt(_imm_b30_20_T_7) node imm_b30_20_2 = mux(_imm_b30_20_T_6, _imm_b30_20_T_8, imm_sign_2) node _imm_b19_12_T_10 = neq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b19_12_T_11 = neq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b19_12_T_12 = and(_imm_b19_12_T_10, _imm_b19_12_T_11) node _imm_b19_12_T_13 = bits(mem_alu_uops_0.inst, 19, 12) node _imm_b19_12_T_14 = asSInt(_imm_b19_12_T_13) node imm_b19_12_2 = mux(_imm_b19_12_T_12, imm_sign_2, _imm_b19_12_T_14) node _imm_b11_T_22 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b11_T_23 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b11_T_24 = or(_imm_b11_T_22, _imm_b11_T_23) node _imm_b11_T_25 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h3)) node _imm_b11_T_26 = bits(mem_alu_uops_0.inst, 20, 20) node _imm_b11_T_27 = asSInt(_imm_b11_T_26) node _imm_b11_T_28 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b11_T_29 = bits(mem_alu_uops_0.inst, 7, 7) node _imm_b11_T_30 = asSInt(_imm_b11_T_29) node _imm_b11_T_31 = mux(_imm_b11_T_28, _imm_b11_T_30, imm_sign_2) node _imm_b11_T_32 = mux(_imm_b11_T_25, _imm_b11_T_27, _imm_b11_T_31) node imm_b11_2 = mux(_imm_b11_T_24, asSInt(UInt<1>(0h0)), _imm_b11_T_32) node _imm_b10_5_T_8 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b10_5_T_9 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b10_5_T_10 = or(_imm_b10_5_T_8, _imm_b10_5_T_9) node _imm_b10_5_T_11 = bits(mem_alu_uops_0.inst, 30, 25) node imm_b10_5_2 = mux(_imm_b10_5_T_10, UInt<1>(0h0), _imm_b10_5_T_11) node _imm_b4_1_T_20 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h2)) node _imm_b4_1_T_21 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b4_1_T_22 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h1)) node _imm_b4_1_T_23 = or(_imm_b4_1_T_21, _imm_b4_1_T_22) node _imm_b4_1_T_24 = bits(mem_alu_uops_0.inst, 11, 8) node _imm_b4_1_T_25 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b4_1_T_26 = bits(mem_alu_uops_0.inst, 19, 16) node _imm_b4_1_T_27 = bits(mem_alu_uops_0.inst, 24, 21) node _imm_b4_1_T_28 = mux(_imm_b4_1_T_25, _imm_b4_1_T_26, _imm_b4_1_T_27) node _imm_b4_1_T_29 = mux(_imm_b4_1_T_23, _imm_b4_1_T_24, _imm_b4_1_T_28) node imm_b4_1_2 = mux(_imm_b4_1_T_20, UInt<1>(0h0), _imm_b4_1_T_29) node _imm_b0_T_16 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h0)) node _imm_b0_T_17 = bits(mem_alu_uops_0.inst, 7, 7) node _imm_b0_T_18 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h4)) node _imm_b0_T_19 = bits(mem_alu_uops_0.inst, 20, 20) node _imm_b0_T_20 = eq(mem_alu_uops_0.ctrl.sel_imm, UInt<3>(0h5)) node _imm_b0_T_21 = bits(mem_alu_uops_0.inst, 15, 15) node _imm_b0_T_22 = mux(_imm_b0_T_20, _imm_b0_T_21, UInt<1>(0h0)) node _imm_b0_T_23 = mux(_imm_b0_T_18, _imm_b0_T_19, _imm_b0_T_22) node imm_b0_2 = mux(_imm_b0_T_16, _imm_b0_T_17, _imm_b0_T_23) node imm_lo_hi_2 = cat(imm_b10_5_2, imm_b4_1_2) node imm_lo_2 = cat(imm_lo_hi_2, imm_b0_2) node imm_hi_lo_lo_2 = asUInt(imm_b11_2) node imm_hi_lo_hi_2 = asUInt(imm_b19_12_2) node imm_hi_lo_2 = cat(imm_hi_lo_hi_2, imm_hi_lo_lo_2) node imm_hi_hi_lo_2 = asUInt(imm_b30_20_2) node imm_hi_hi_hi_2 = asUInt(imm_sign_2) node imm_hi_hi_2 = cat(imm_hi_hi_hi_2, imm_hi_hi_lo_2) node imm_hi_2 = cat(imm_hi_hi_2, imm_hi_lo_2) node _imm_T_2 = cat(imm_hi_2, imm_lo_2) node imm_2 = asSInt(_imm_T_2) wire sel_alu1_2 : UInt connect sel_alu1_2, mem_alu_uops_0.ctrl.sel_alu1 wire sel_alu2_2 : UInt connect sel_alu2_2, mem_alu_uops_0.ctrl.sel_alu2 node _ex_op1_T_26 = asSInt(mem_alu_uops_0.rs1_data) node _ex_op1_T_27 = asSInt(mem_alu_uops_0.pc) node _ex_op1_T_28 = bits(mem_alu_uops_0.inst, 3, 3) node _ex_op1_T_29 = bits(mem_alu_uops_0.rs1_data, 31, 0) node _ex_op1_T_30 = mux(_ex_op1_T_28, _ex_op1_T_29, mem_alu_uops_0.rs1_data) node _ex_op1_T_31 = bits(mem_alu_uops_0.inst, 14, 13) node _ex_op1_T_32 = dshl(_ex_op1_T_30, _ex_op1_T_31) node _ex_op1_T_33 = asSInt(_ex_op1_T_32) node _ex_op1_T_34 = eq(UInt<2>(0h1), sel_alu1_2) node _ex_op1_T_35 = mux(_ex_op1_T_34, _ex_op1_T_26, asSInt(UInt<1>(0h0))) node _ex_op1_T_36 = eq(UInt<2>(0h2), sel_alu1_2) node _ex_op1_T_37 = mux(_ex_op1_T_36, _ex_op1_T_27, _ex_op1_T_35) node _ex_op1_T_38 = eq(UInt<2>(0h3), sel_alu1_2) node ex_op1_2 = mux(_ex_op1_T_38, _ex_op1_T_33, _ex_op1_T_37) node _ex_op2_oh_T_10 = bits(mem_alu_uops_0.ctrl.sel_alu2, 0, 0) node _ex_op2_oh_T_11 = shr(mem_alu_uops_0.inst, 20) node _ex_op2_oh_T_12 = mux(_ex_op2_oh_T_10, _ex_op2_oh_T_11, mem_alu_uops_0.rs2_data) node _ex_op2_oh_T_13 = bits(_ex_op2_oh_T_12, 5, 0) node _ex_op2_oh_T_14 = dshl(UInt<1>(0h1), _ex_op2_oh_T_13) node ex_op2_oh_2 = asSInt(_ex_op2_oh_T_14) node _ex_op2_T_22 = asSInt(mem_alu_uops_0.rs2_data) node _ex_op2_T_23 = mux(mem_alu_uops_0.rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _ex_op2_T_24 = eq(UInt<3>(0h2), sel_alu2_2) node _ex_op2_T_25 = mux(_ex_op2_T_24, _ex_op2_T_22, asSInt(UInt<1>(0h0))) node _ex_op2_T_26 = eq(UInt<3>(0h3), sel_alu2_2) node _ex_op2_T_27 = mux(_ex_op2_T_26, imm_2, _ex_op2_T_25) node _ex_op2_T_28 = eq(UInt<3>(0h1), sel_alu2_2) node _ex_op2_T_29 = mux(_ex_op2_T_28, _ex_op2_T_23, _ex_op2_T_27) node _ex_op2_T_30 = eq(UInt<3>(0h4), sel_alu2_2) node _ex_op2_T_31 = mux(_ex_op2_T_30, ex_op2_oh_2, _ex_op2_T_29) node _ex_op2_T_32 = eq(UInt<3>(0h5), sel_alu2_2) node ex_op2_2 = mux(_ex_op2_T_32, ex_op2_oh_2, _ex_op2_T_31) connect mem_alus_0.io.dw, mem_alu_uops_0.ctrl.alu_dw connect mem_alus_0.io.fn, mem_alu_uops_0.ctrl.alu_fn node _mem_alus_0_io_in2_T = asUInt(ex_op2_2) connect mem_alus_0.io.in2, _mem_alus_0_io_in2_T node _mem_alus_0_io_in1_T = asUInt(ex_op1_2) connect mem_alus_0.io.in1, _mem_alus_0_io_in1_T when mem_alu_uops_0.uses_memalu : connect com_uops_reg[1].bits.wdata.valid, UInt<1>(0h1) connect com_uops_reg[1].bits.wdata.bits, mem_alus_0.io.out node _mem_bypasses_1_valid_T_3 = and(mem_uops_reg[1].bits.ctrl.wxd, mem_uops_reg[1].valid) connect mem_bypasses_1.valid, _mem_bypasses_1_valid_T_3 connect mem_bypasses_1.can_bypass, UInt<1>(0h1) connect mem_bypasses_1.data, mem_alus_0.io.out node _T_244 = and(mem_uops_reg[0].valid, mem_uops_reg[0].bits.ctrl.mem) node _T_245 = and(_T_244, kill_mem) reg REG_2 : UInt<1>, clock connect REG_2, _T_245 when REG_2 : connect io.dmem.s2_kill, UInt<1>(0h1) node _T_246 = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.mem) node _T_247 = or(com_uops[0].bits.needs_replay, com_uops_reg[0].bits.xcpt) node _T_248 = or(_T_247, kill_com[0]) node _T_249 = and(_T_246, _T_248) when _T_249 : connect io.dmem.s2_kill, UInt<1>(0h1) node _T_250 = and(mem_uops_reg[1].valid, mem_uops_reg[1].bits.ctrl.mem) node _T_251 = and(_T_250, kill_mem) reg REG_3 : UInt<1>, clock connect REG_3, _T_251 when REG_3 : connect io.dmem.s2_kill, UInt<1>(0h1) node _T_252 = and(com_uops_reg[1].valid, com_uops_reg[1].bits.ctrl.mem) node _T_253 = or(com_uops[1].bits.needs_replay, com_uops_reg[1].bits.xcpt) node _T_254 = or(_T_253, kill_com[1]) node _T_255 = and(_T_252, _T_254) when _T_255 : connect io.dmem.s2_kill, UInt<1>(0h1) connect fp_pipe.io.s2_kill, kill_com[0] node _com_fp_divsqrt_valid_T = and(com_uops_reg[0].bits.fp_ctrl.ldst, com_uops_reg[0].bits.fp_ctrl.wen) node _com_fp_divsqrt_valid_T_1 = eq(_com_fp_divsqrt_valid_T, UInt<1>(0h0)) node _com_fp_divsqrt_valid_T_2 = and(com_uops_reg[0].bits.ctrl.fp, _com_fp_divsqrt_valid_T_1) node _com_fp_divsqrt_valid_T_3 = or(com_uops_reg[0].bits.fp_ctrl.div, com_uops_reg[0].bits.fp_ctrl.sqrt) node com_fp_divsqrt_valid = and(_com_fp_divsqrt_valid_T_2, _com_fp_divsqrt_valid_T_3) regreset divSqrt_val : UInt<1>, clock, reset, UInt<1>(0h0) reg divSqrt_waddr : UInt<5>, clock reg divSqrt_typeTag : UInt<2>, clock reg divSqrt_wdata : { valid : UInt<1>, bits : UInt<65>}, clock reg divSqrt_flags : UInt<5>, clock node _T_256 = and(com_fp_divsqrt_valid, divSqrt_val) when _T_256 : connect com_uops[0].bits.needs_replay, UInt<1>(0h1) inst divSqrt of DivSqrtRecFM_small_e5_s11 connect divSqrt.clock, clock connect divSqrt.reset, reset node _divSqrt_io_inValid_T = eq(com_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _divSqrt_io_inValid_T_1 = and(com_uops_reg[0].valid, _divSqrt_io_inValid_T) node _divSqrt_io_inValid_T_2 = and(_divSqrt_io_inValid_T_1, com_fp_divsqrt_valid) node _divSqrt_io_inValid_T_3 = eq(divSqrt_val, UInt<1>(0h0)) node _divSqrt_io_inValid_T_4 = and(_divSqrt_io_inValid_T_2, _divSqrt_io_inValid_T_3) connect divSqrt.io.inValid, _divSqrt_io_inValid_T_4 connect divSqrt.io.sqrtOp, com_uops_reg[0].bits.fp_ctrl.sqrt node divSqrt_io_a_sign = bits(com_uops_reg[0].bits.fdivin.in1, 64, 64) node divSqrt_io_a_fractIn = bits(com_uops_reg[0].bits.fdivin.in1, 51, 0) node divSqrt_io_a_expIn = bits(com_uops_reg[0].bits.fdivin.in1, 63, 52) node _divSqrt_io_a_fractOut_T = shl(divSqrt_io_a_fractIn, 11) node divSqrt_io_a_fractOut = shr(_divSqrt_io_a_fractOut_T, 53) node divSqrt_io_a_expOut_expCode = bits(divSqrt_io_a_expIn, 11, 9) node _divSqrt_io_a_expOut_commonCase_T = add(divSqrt_io_a_expIn, UInt<6>(0h20)) node _divSqrt_io_a_expOut_commonCase_T_1 = tail(_divSqrt_io_a_expOut_commonCase_T, 1) node _divSqrt_io_a_expOut_commonCase_T_2 = sub(_divSqrt_io_a_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase = tail(_divSqrt_io_a_expOut_commonCase_T_2, 1) node _divSqrt_io_a_expOut_T = eq(divSqrt_io_a_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_1 = geq(divSqrt_io_a_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_2 = or(_divSqrt_io_a_expOut_T, _divSqrt_io_a_expOut_T_1) node _divSqrt_io_a_expOut_T_3 = bits(divSqrt_io_a_expOut_commonCase, 2, 0) node _divSqrt_io_a_expOut_T_4 = cat(divSqrt_io_a_expOut_expCode, _divSqrt_io_a_expOut_T_3) node _divSqrt_io_a_expOut_T_5 = bits(divSqrt_io_a_expOut_commonCase, 5, 0) node divSqrt_io_a_expOut = mux(_divSqrt_io_a_expOut_T_2, _divSqrt_io_a_expOut_T_4, _divSqrt_io_a_expOut_T_5) node divSqrt_io_a_hi = cat(divSqrt_io_a_sign, divSqrt_io_a_expOut) node _divSqrt_io_a_T = cat(divSqrt_io_a_hi, divSqrt_io_a_fractOut) connect divSqrt.io.a, _divSqrt_io_a_T node divSqrt_io_b_sign = bits(com_uops_reg[0].bits.fdivin.in2, 64, 64) node divSqrt_io_b_fractIn = bits(com_uops_reg[0].bits.fdivin.in2, 51, 0) node divSqrt_io_b_expIn = bits(com_uops_reg[0].bits.fdivin.in2, 63, 52) node _divSqrt_io_b_fractOut_T = shl(divSqrt_io_b_fractIn, 11) node divSqrt_io_b_fractOut = shr(_divSqrt_io_b_fractOut_T, 53) node divSqrt_io_b_expOut_expCode = bits(divSqrt_io_b_expIn, 11, 9) node _divSqrt_io_b_expOut_commonCase_T = add(divSqrt_io_b_expIn, UInt<6>(0h20)) node _divSqrt_io_b_expOut_commonCase_T_1 = tail(_divSqrt_io_b_expOut_commonCase_T, 1) node _divSqrt_io_b_expOut_commonCase_T_2 = sub(_divSqrt_io_b_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase = tail(_divSqrt_io_b_expOut_commonCase_T_2, 1) node _divSqrt_io_b_expOut_T = eq(divSqrt_io_b_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_1 = geq(divSqrt_io_b_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_2 = or(_divSqrt_io_b_expOut_T, _divSqrt_io_b_expOut_T_1) node _divSqrt_io_b_expOut_T_3 = bits(divSqrt_io_b_expOut_commonCase, 2, 0) node _divSqrt_io_b_expOut_T_4 = cat(divSqrt_io_b_expOut_expCode, _divSqrt_io_b_expOut_T_3) node _divSqrt_io_b_expOut_T_5 = bits(divSqrt_io_b_expOut_commonCase, 5, 0) node divSqrt_io_b_expOut = mux(_divSqrt_io_b_expOut_T_2, _divSqrt_io_b_expOut_T_4, _divSqrt_io_b_expOut_T_5) node divSqrt_io_b_hi = cat(divSqrt_io_b_sign, divSqrt_io_b_expOut) node _divSqrt_io_b_T = cat(divSqrt_io_b_hi, divSqrt_io_b_fractOut) connect divSqrt.io.b, _divSqrt_io_b_T connect divSqrt.io.roundingMode, com_uops_reg[0].bits.fdivin.rm connect divSqrt.io.detectTininess, UInt<1>(0h1) when divSqrt.io.inValid : node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(divSqrt.io.inReady, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:891 assert(divSqrt.io.inReady)\n") : printf_2 assert(clock, divSqrt.io.inReady, UInt<1>(0h1), "") : assert_2 node _divSqrt_waddr_T = bits(com_uops_reg[0].bits.inst, 11, 7) connect divSqrt_waddr, _divSqrt_waddr_T connect divSqrt_val, UInt<1>(0h1) connect divSqrt_wdata.valid, UInt<1>(0h0) node _T_260 = or(divSqrt.io.outValid_div, divSqrt.io.outValid_sqrt) when _T_260 : connect divSqrt_wdata.valid, UInt<1>(0h1) node _divSqrt_wdata_bits_bigger_swizzledNaN_T = andr(UInt<7>(0h7f)) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_1 = bits(divSqrt.io.out, 15, 15) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_2 = bits(divSqrt.io.out, 16, 16) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_3 = bits(divSqrt.io.out, 14, 0) node divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi = cat(UInt<7>(0h7f), _divSqrt_wdata_bits_bigger_swizzledNaN_T_2) node divSqrt_wdata_bits_bigger_swizzledNaN_lo = cat(divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi, _divSqrt_wdata_bits_bigger_swizzledNaN_T_3) node divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo = cat(UInt<4>(0hf), _divSqrt_wdata_bits_bigger_swizzledNaN_T_1) node divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _divSqrt_wdata_bits_bigger_swizzledNaN_T) node divSqrt_wdata_bits_bigger_swizzledNaN_hi = cat(divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi, divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo) node divSqrt_wdata_bits_bigger_swizzledNaN = cat(divSqrt_wdata_bits_bigger_swizzledNaN_hi, divSqrt_wdata_bits_bigger_swizzledNaN_lo) node _divSqrt_wdata_bits_bigger_T = andr(UInt<3>(0h7)) node divSqrt_wdata_bits_bigger = mux(_divSqrt_wdata_bits_bigger_T, divSqrt_wdata_bits_bigger_swizzledNaN, UInt<33>(0h1ffffffff)) node _divSqrt_wdata_bits_T = or(divSqrt_wdata_bits_bigger, UInt<65>(0h1fffffffe00000000)) connect divSqrt_wdata.bits, _divSqrt_wdata_bits_T connect divSqrt_flags, divSqrt.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h0) inst divSqrt_1 of DivSqrtRecFM_small_e8_s24 connect divSqrt_1.clock, clock connect divSqrt_1.reset, reset node _divSqrt_io_inValid_T_5 = eq(com_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<1>(0h1)) node _divSqrt_io_inValid_T_6 = and(com_uops_reg[0].valid, _divSqrt_io_inValid_T_5) node _divSqrt_io_inValid_T_7 = and(_divSqrt_io_inValid_T_6, com_fp_divsqrt_valid) node _divSqrt_io_inValid_T_8 = eq(divSqrt_val, UInt<1>(0h0)) node _divSqrt_io_inValid_T_9 = and(_divSqrt_io_inValid_T_7, _divSqrt_io_inValid_T_8) connect divSqrt_1.io.inValid, _divSqrt_io_inValid_T_9 connect divSqrt_1.io.sqrtOp, com_uops_reg[0].bits.fp_ctrl.sqrt node divSqrt_io_a_sign_1 = bits(com_uops_reg[0].bits.fdivin.in1, 64, 64) node divSqrt_io_a_fractIn_1 = bits(com_uops_reg[0].bits.fdivin.in1, 51, 0) node divSqrt_io_a_expIn_1 = bits(com_uops_reg[0].bits.fdivin.in1, 63, 52) node _divSqrt_io_a_fractOut_T_1 = shl(divSqrt_io_a_fractIn_1, 24) node divSqrt_io_a_fractOut_1 = shr(_divSqrt_io_a_fractOut_T_1, 53) node divSqrt_io_a_expOut_expCode_1 = bits(divSqrt_io_a_expIn_1, 11, 9) node _divSqrt_io_a_expOut_commonCase_T_3 = add(divSqrt_io_a_expIn_1, UInt<9>(0h100)) node _divSqrt_io_a_expOut_commonCase_T_4 = tail(_divSqrt_io_a_expOut_commonCase_T_3, 1) node _divSqrt_io_a_expOut_commonCase_T_5 = sub(_divSqrt_io_a_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase_1 = tail(_divSqrt_io_a_expOut_commonCase_T_5, 1) node _divSqrt_io_a_expOut_T_6 = eq(divSqrt_io_a_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_7 = geq(divSqrt_io_a_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_8 = or(_divSqrt_io_a_expOut_T_6, _divSqrt_io_a_expOut_T_7) node _divSqrt_io_a_expOut_T_9 = bits(divSqrt_io_a_expOut_commonCase_1, 5, 0) node _divSqrt_io_a_expOut_T_10 = cat(divSqrt_io_a_expOut_expCode_1, _divSqrt_io_a_expOut_T_9) node _divSqrt_io_a_expOut_T_11 = bits(divSqrt_io_a_expOut_commonCase_1, 8, 0) node divSqrt_io_a_expOut_1 = mux(_divSqrt_io_a_expOut_T_8, _divSqrt_io_a_expOut_T_10, _divSqrt_io_a_expOut_T_11) node divSqrt_io_a_hi_1 = cat(divSqrt_io_a_sign_1, divSqrt_io_a_expOut_1) node _divSqrt_io_a_T_1 = cat(divSqrt_io_a_hi_1, divSqrt_io_a_fractOut_1) connect divSqrt_1.io.a, _divSqrt_io_a_T_1 node divSqrt_io_b_sign_1 = bits(com_uops_reg[0].bits.fdivin.in2, 64, 64) node divSqrt_io_b_fractIn_1 = bits(com_uops_reg[0].bits.fdivin.in2, 51, 0) node divSqrt_io_b_expIn_1 = bits(com_uops_reg[0].bits.fdivin.in2, 63, 52) node _divSqrt_io_b_fractOut_T_1 = shl(divSqrt_io_b_fractIn_1, 24) node divSqrt_io_b_fractOut_1 = shr(_divSqrt_io_b_fractOut_T_1, 53) node divSqrt_io_b_expOut_expCode_1 = bits(divSqrt_io_b_expIn_1, 11, 9) node _divSqrt_io_b_expOut_commonCase_T_3 = add(divSqrt_io_b_expIn_1, UInt<9>(0h100)) node _divSqrt_io_b_expOut_commonCase_T_4 = tail(_divSqrt_io_b_expOut_commonCase_T_3, 1) node _divSqrt_io_b_expOut_commonCase_T_5 = sub(_divSqrt_io_b_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase_1 = tail(_divSqrt_io_b_expOut_commonCase_T_5, 1) node _divSqrt_io_b_expOut_T_6 = eq(divSqrt_io_b_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_7 = geq(divSqrt_io_b_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_8 = or(_divSqrt_io_b_expOut_T_6, _divSqrt_io_b_expOut_T_7) node _divSqrt_io_b_expOut_T_9 = bits(divSqrt_io_b_expOut_commonCase_1, 5, 0) node _divSqrt_io_b_expOut_T_10 = cat(divSqrt_io_b_expOut_expCode_1, _divSqrt_io_b_expOut_T_9) node _divSqrt_io_b_expOut_T_11 = bits(divSqrt_io_b_expOut_commonCase_1, 8, 0) node divSqrt_io_b_expOut_1 = mux(_divSqrt_io_b_expOut_T_8, _divSqrt_io_b_expOut_T_10, _divSqrt_io_b_expOut_T_11) node divSqrt_io_b_hi_1 = cat(divSqrt_io_b_sign_1, divSqrt_io_b_expOut_1) node _divSqrt_io_b_T_1 = cat(divSqrt_io_b_hi_1, divSqrt_io_b_fractOut_1) connect divSqrt_1.io.b, _divSqrt_io_b_T_1 connect divSqrt_1.io.roundingMode, com_uops_reg[0].bits.fdivin.rm connect divSqrt_1.io.detectTininess, UInt<1>(0h1) when divSqrt_1.io.inValid : node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(divSqrt_1.io.inReady, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:891 assert(divSqrt.io.inReady)\n") : printf_3 assert(clock, divSqrt_1.io.inReady, UInt<1>(0h1), "") : assert_3 node _divSqrt_waddr_T_1 = bits(com_uops_reg[0].bits.inst, 11, 7) connect divSqrt_waddr, _divSqrt_waddr_T_1 connect divSqrt_val, UInt<1>(0h1) connect divSqrt_wdata.valid, UInt<1>(0h0) node _T_264 = or(divSqrt_1.io.outValid_div, divSqrt_1.io.outValid_sqrt) when _T_264 : connect divSqrt_wdata.valid, UInt<1>(0h1) node _divSqrt_wdata_bits_maskedNaN_T = not(UInt<33>(0h10800000)) node divSqrt_wdata_bits_maskedNaN = and(divSqrt_1.io.out, _divSqrt_wdata_bits_maskedNaN_T) node _divSqrt_wdata_bits_T_1 = bits(divSqrt_1.io.out, 31, 29) node _divSqrt_wdata_bits_T_2 = andr(_divSqrt_wdata_bits_T_1) node _divSqrt_wdata_bits_T_3 = mux(_divSqrt_wdata_bits_T_2, divSqrt_wdata_bits_maskedNaN, divSqrt_1.io.out) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_5 = bits(_divSqrt_wdata_bits_T_3, 31, 31) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_6 = bits(_divSqrt_wdata_bits_T_3, 32, 32) node _divSqrt_wdata_bits_bigger_swizzledNaN_T_7 = bits(_divSqrt_wdata_bits_T_3, 30, 0) node divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _divSqrt_wdata_bits_bigger_swizzledNaN_T_6) node divSqrt_wdata_bits_bigger_swizzledNaN_lo_1 = cat(divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi_1, _divSqrt_wdata_bits_bigger_swizzledNaN_T_7) node divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _divSqrt_wdata_bits_bigger_swizzledNaN_T_5) node divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _divSqrt_wdata_bits_bigger_swizzledNaN_T_4) node divSqrt_wdata_bits_bigger_swizzledNaN_hi_1 = cat(divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi_1, divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo_1) node divSqrt_wdata_bits_bigger_swizzledNaN_1 = cat(divSqrt_wdata_bits_bigger_swizzledNaN_hi_1, divSqrt_wdata_bits_bigger_swizzledNaN_lo_1) node _divSqrt_wdata_bits_bigger_T_1 = andr(UInt<3>(0h7)) node divSqrt_wdata_bits_bigger_1 = mux(_divSqrt_wdata_bits_bigger_T_1, divSqrt_wdata_bits_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node _divSqrt_wdata_bits_T_4 = or(divSqrt_wdata_bits_bigger_1, UInt<1>(0h0)) connect divSqrt_wdata.bits, _divSqrt_wdata_bits_T_4 connect divSqrt_flags, divSqrt_1.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h1) inst divSqrt_2 of DivSqrtRecFM_small_e11_s53 connect divSqrt_2.clock, clock connect divSqrt_2.reset, reset node _divSqrt_io_inValid_T_10 = eq(com_uops_reg[0].bits.fp_ctrl.typeTagOut, UInt<2>(0h2)) node _divSqrt_io_inValid_T_11 = and(com_uops_reg[0].valid, _divSqrt_io_inValid_T_10) node _divSqrt_io_inValid_T_12 = and(_divSqrt_io_inValid_T_11, com_fp_divsqrt_valid) node _divSqrt_io_inValid_T_13 = eq(divSqrt_val, UInt<1>(0h0)) node _divSqrt_io_inValid_T_14 = and(_divSqrt_io_inValid_T_12, _divSqrt_io_inValid_T_13) connect divSqrt_2.io.inValid, _divSqrt_io_inValid_T_14 connect divSqrt_2.io.sqrtOp, com_uops_reg[0].bits.fp_ctrl.sqrt connect divSqrt_2.io.a, com_uops_reg[0].bits.fdivin.in1 connect divSqrt_2.io.b, com_uops_reg[0].bits.fdivin.in2 connect divSqrt_2.io.roundingMode, com_uops_reg[0].bits.fdivin.rm connect divSqrt_2.io.detectTininess, UInt<1>(0h1) when divSqrt_2.io.inValid : node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(divSqrt_2.io.inReady, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:891 assert(divSqrt.io.inReady)\n") : printf_4 assert(clock, divSqrt_2.io.inReady, UInt<1>(0h1), "") : assert_4 node _divSqrt_waddr_T_2 = bits(com_uops_reg[0].bits.inst, 11, 7) connect divSqrt_waddr, _divSqrt_waddr_T_2 connect divSqrt_val, UInt<1>(0h1) connect divSqrt_wdata.valid, UInt<1>(0h0) node _T_268 = or(divSqrt_2.io.outValid_div, divSqrt_2.io.outValid_sqrt) when _T_268 : connect divSqrt_wdata.valid, UInt<1>(0h1) node _divSqrt_wdata_bits_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000)) node divSqrt_wdata_bits_maskedNaN_1 = and(divSqrt_2.io.out, _divSqrt_wdata_bits_maskedNaN_T_1) node _divSqrt_wdata_bits_T_5 = bits(divSqrt_2.io.out, 63, 61) node _divSqrt_wdata_bits_T_6 = andr(_divSqrt_wdata_bits_T_5) node _divSqrt_wdata_bits_T_7 = mux(_divSqrt_wdata_bits_T_6, divSqrt_wdata_bits_maskedNaN_1, divSqrt_2.io.out) connect divSqrt_wdata.bits, _divSqrt_wdata_bits_T_7 connect divSqrt_flags, divSqrt_2.io.exceptionFlags connect divSqrt_typeTag, UInt<2>(0h2) inst div of MulDiv connect div.clock, clock connect div.reset, reset connect div.io.kill, UInt<1>(0h0) node _div_io_req_valid_T = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.div) node _div_io_req_valid_T_1 = eq(com_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _div_io_req_valid_T_2 = and(_div_io_req_valid_T, _div_io_req_valid_T_1) connect div.io.req.valid, _div_io_req_valid_T_2 connect div.io.req.bits.dw, com_uops_reg[0].bits.ctrl.alu_dw connect div.io.req.bits.fn, com_uops_reg[0].bits.ctrl.alu_fn connect div.io.req.bits.in1, com_uops_reg[0].bits.rs1_data connect div.io.req.bits.in2, com_uops_reg[0].bits.rs2_data node _div_io_req_bits_tag_T = bits(com_uops_reg[0].bits.inst, 11, 7) connect div.io.req.bits.tag, _div_io_req_bits_tag_T connect div.io.resp.ready, UInt<1>(0h0) node _T_269 = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.div) node _T_270 = eq(div.io.req.ready, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) when _T_271 : connect com_uops[0].bits.needs_replay, UInt<1>(0h1) when com_uops_reg[0].bits.ctrl.mul : connect com_uops[0].bits.wdata.valid, UInt<1>(0h1) connect com_uops[0].bits.wdata.bits, mul.io.resp.bits.data node com_rocc_valid = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.rocc) connect io.rocc.cmd.valid, UInt<1>(0h0) invalidate io.rocc.cmd.bits.status.uie invalidate io.rocc.cmd.bits.status.sie invalidate io.rocc.cmd.bits.status.hie invalidate io.rocc.cmd.bits.status.mie invalidate io.rocc.cmd.bits.status.upie invalidate io.rocc.cmd.bits.status.spie invalidate io.rocc.cmd.bits.status.ube invalidate io.rocc.cmd.bits.status.mpie invalidate io.rocc.cmd.bits.status.spp invalidate io.rocc.cmd.bits.status.vs invalidate io.rocc.cmd.bits.status.mpp invalidate io.rocc.cmd.bits.status.fs invalidate io.rocc.cmd.bits.status.xs invalidate io.rocc.cmd.bits.status.mprv invalidate io.rocc.cmd.bits.status.sum invalidate io.rocc.cmd.bits.status.mxr invalidate io.rocc.cmd.bits.status.tvm invalidate io.rocc.cmd.bits.status.tw invalidate io.rocc.cmd.bits.status.tsr invalidate io.rocc.cmd.bits.status.zero1 invalidate io.rocc.cmd.bits.status.sd_rv32 invalidate io.rocc.cmd.bits.status.uxl invalidate io.rocc.cmd.bits.status.sxl invalidate io.rocc.cmd.bits.status.sbe invalidate io.rocc.cmd.bits.status.mbe invalidate io.rocc.cmd.bits.status.gva invalidate io.rocc.cmd.bits.status.mpv invalidate io.rocc.cmd.bits.status.zero2 invalidate io.rocc.cmd.bits.status.sd invalidate io.rocc.cmd.bits.status.v invalidate io.rocc.cmd.bits.status.prv invalidate io.rocc.cmd.bits.status.dv invalidate io.rocc.cmd.bits.status.dprv invalidate io.rocc.cmd.bits.status.isa invalidate io.rocc.cmd.bits.status.wfi invalidate io.rocc.cmd.bits.status.cease invalidate io.rocc.cmd.bits.status.debug invalidate io.rocc.cmd.bits.rs2 invalidate io.rocc.cmd.bits.rs1 invalidate io.rocc.cmd.bits.inst.opcode invalidate io.rocc.cmd.bits.inst.rd invalidate io.rocc.cmd.bits.inst.xs2 invalidate io.rocc.cmd.bits.inst.xs1 invalidate io.rocc.cmd.bits.inst.xd invalidate io.rocc.cmd.bits.inst.rs1 invalidate io.rocc.cmd.bits.inst.rs2 invalidate io.rocc.cmd.bits.inst.funct invalidate io.rocc.mem.clock_enabled invalidate io.rocc.mem.keep_clock_enabled invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate io.rocc.mem.perf.canAcceptLoadThenLoad invalidate io.rocc.mem.perf.canAcceptStoreThenRMW invalidate io.rocc.mem.perf.canAcceptStoreThenLoad invalidate io.rocc.mem.perf.blocked invalidate io.rocc.mem.perf.tlbMiss invalidate io.rocc.mem.perf.grant invalidate io.rocc.mem.perf.release invalidate io.rocc.mem.perf.acquire invalidate io.rocc.mem.store_pending invalidate io.rocc.mem.ordered invalidate io.rocc.mem.s2_gpa_is_pte invalidate io.rocc.mem.s2_gpa invalidate io.rocc.mem.s2_xcpt.ae.st invalidate io.rocc.mem.s2_xcpt.ae.ld invalidate io.rocc.mem.s2_xcpt.gf.st invalidate io.rocc.mem.s2_xcpt.gf.ld invalidate io.rocc.mem.s2_xcpt.pf.st invalidate io.rocc.mem.s2_xcpt.pf.ld invalidate io.rocc.mem.s2_xcpt.ma.st invalidate io.rocc.mem.s2_xcpt.ma.ld invalidate io.rocc.mem.replay_next invalidate io.rocc.mem.resp.bits.store_data invalidate io.rocc.mem.resp.bits.data_raw invalidate io.rocc.mem.resp.bits.data_word_bypass invalidate io.rocc.mem.resp.bits.has_data invalidate io.rocc.mem.resp.bits.replay invalidate io.rocc.mem.resp.bits.mask invalidate io.rocc.mem.resp.bits.data invalidate io.rocc.mem.resp.bits.dv invalidate io.rocc.mem.resp.bits.dprv invalidate io.rocc.mem.resp.bits.signed invalidate io.rocc.mem.resp.bits.size invalidate io.rocc.mem.resp.bits.cmd invalidate io.rocc.mem.resp.bits.tag invalidate io.rocc.mem.resp.bits.addr invalidate io.rocc.mem.resp.valid invalidate io.rocc.mem.s2_paddr invalidate io.rocc.mem.s2_uncached invalidate io.rocc.mem.s2_kill invalidate io.rocc.mem.s2_nack_cause_raw invalidate io.rocc.mem.s2_nack invalidate io.rocc.mem.s1_data.mask invalidate io.rocc.mem.s1_data.data invalidate io.rocc.mem.s1_kill invalidate io.rocc.mem.req.bits.mask invalidate io.rocc.mem.req.bits.data invalidate io.rocc.mem.req.bits.no_xcpt invalidate io.rocc.mem.req.bits.no_alloc invalidate io.rocc.mem.req.bits.no_resp invalidate io.rocc.mem.req.bits.phys invalidate io.rocc.mem.req.bits.dv invalidate io.rocc.mem.req.bits.dprv invalidate io.rocc.mem.req.bits.signed invalidate io.rocc.mem.req.bits.size invalidate io.rocc.mem.req.bits.cmd invalidate io.rocc.mem.req.bits.tag invalidate io.rocc.mem.req.bits.addr invalidate io.rocc.mem.req.valid invalidate io.rocc.mem.req.ready connect io.rocc.exception, UInt<1>(0h0) node _com_retire_0_T = eq(com_uops[0].bits.xcpt, UInt<1>(0h0)) node _com_retire_0_T_1 = and(com_uops_reg[0].valid, _com_retire_0_T) node _com_retire_0_T_2 = eq(com_uops[0].bits.needs_replay, UInt<1>(0h0)) node _com_retire_0_T_3 = and(_com_retire_0_T_1, _com_retire_0_T_2) node _com_retire_0_T_4 = eq(kill_com[0], UInt<1>(0h0)) node _com_retire_0_T_5 = and(_com_retire_0_T_3, _com_retire_0_T_4) connect com_retire[0], _com_retire_0_T_5 node _com_retire_1_T = eq(com_uops[1].bits.xcpt, UInt<1>(0h0)) node _com_retire_1_T_1 = and(com_uops_reg[1].valid, _com_retire_1_T) node _com_retire_1_T_2 = eq(com_uops[1].bits.needs_replay, UInt<1>(0h0)) node _com_retire_1_T_3 = and(_com_retire_1_T_1, _com_retire_1_T_2) node _com_retire_1_T_4 = eq(kill_com[1], UInt<1>(0h0)) node _com_retire_1_T_5 = and(_com_retire_1_T_3, _com_retire_1_T_4) connect com_retire[1], _com_retire_1_T_5 node _csr_io_exception_T = eq(kill_com[0], UInt<1>(0h0)) node _csr_io_exception_T_1 = and(com_uops_reg[0].valid, _csr_io_exception_T) node _csr_io_exception_T_2 = and(_csr_io_exception_T_1, com_uops[0].bits.xcpt) node _csr_io_exception_T_3 = eq(com_uops[0].bits.needs_replay, UInt<1>(0h0)) node _csr_io_exception_T_4 = and(_csr_io_exception_T_2, _csr_io_exception_T_3) connect csr.io.exception, _csr_io_exception_T_4 connect csr.io.cause, com_uops[0].bits.xcpt_cause node _csr_io_retire_T = add(com_retire[0], com_retire[1]) node _csr_io_retire_T_1 = bits(_csr_io_retire_T, 1, 0) connect csr.io.retire, _csr_io_retire_T_1 node _debug_irt_reg_T = add(debug_irt_reg, csr.io.retire) node _debug_irt_reg_T_1 = tail(_debug_irt_reg_T, 1) connect debug_irt_reg, _debug_irt_reg_T_1 connect csr.io.pc, com_uops_reg[0].bits.pc node _T_272 = eq(com_uops_reg[0].valid, UInt<1>(0h0)) when _T_272 : connect csr.io.pc, com_uops_reg[1].bits.pc node _T_273 = or(com_uops_reg[0].valid, com_uops_reg[1].valid) connect csr.io.inst[0], com_uops_reg[0].bits.raw_inst connect csr.io.inst[1], com_uops_reg[1].bits.raw_inst connect csr.io.interrupts.seip, io.interrupts.seip connect csr.io.interrupts.meip, io.interrupts.meip connect csr.io.interrupts.msip, io.interrupts.msip connect csr.io.interrupts.mtip, io.interrupts.mtip connect csr.io.interrupts.debug, io.interrupts.debug connect csr.io.hartid, io.hartid connect csr.io.rocc_interrupt, io.rocc.interrupt node _tval_valid_T = eq(csr.io.cause, UInt<2>(0h2)) node _tval_valid_T_1 = eq(csr.io.cause, UInt<2>(0h3)) node _tval_valid_T_2 = eq(csr.io.cause, UInt<3>(0h4)) node _tval_valid_T_3 = eq(csr.io.cause, UInt<3>(0h6)) node _tval_valid_T_4 = eq(csr.io.cause, UInt<3>(0h5)) node _tval_valid_T_5 = eq(csr.io.cause, UInt<3>(0h7)) node _tval_valid_T_6 = eq(csr.io.cause, UInt<1>(0h1)) node _tval_valid_T_7 = eq(csr.io.cause, UInt<4>(0hd)) node _tval_valid_T_8 = eq(csr.io.cause, UInt<4>(0hf)) node _tval_valid_T_9 = eq(csr.io.cause, UInt<4>(0hc)) node _tval_valid_T_10 = or(_tval_valid_T, _tval_valid_T_1) node _tval_valid_T_11 = or(_tval_valid_T_10, _tval_valid_T_2) node _tval_valid_T_12 = or(_tval_valid_T_11, _tval_valid_T_3) node _tval_valid_T_13 = or(_tval_valid_T_12, _tval_valid_T_4) node _tval_valid_T_14 = or(_tval_valid_T_13, _tval_valid_T_5) node _tval_valid_T_15 = or(_tval_valid_T_14, _tval_valid_T_6) node _tval_valid_T_16 = or(_tval_valid_T_15, _tval_valid_T_7) node _tval_valid_T_17 = or(_tval_valid_T_16, _tval_valid_T_8) node _tval_valid_T_18 = or(_tval_valid_T_17, _tval_valid_T_9) node tval_valid = and(csr.io.exception, _tval_valid_T_18) node _csr_io_tval_a_T = asSInt(com_uops_reg[0].bits.wdata.bits) node csr_io_tval_a = shr(_csr_io_tval_a_T, 39) node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0))) node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1))) node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1) node _csr_io_tval_msb_T_3 = bits(com_uops_reg[0].bits.wdata.bits, 39, 39) node _csr_io_tval_msb_T_4 = bits(com_uops_reg[0].bits.wdata.bits, 38, 38) node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0)) node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5) node _csr_io_tval_T = bits(com_uops_reg[0].bits.wdata.bits, 38, 0) node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T) node _csr_io_tval_T_2 = mux(tval_valid, _csr_io_tval_T_1, UInt<1>(0h0)) connect csr.io.tval, _csr_io_tval_T_2 connect io.ptw.ptbr, csr.io.ptbr connect io.ptw.status, csr.io.status connect io.ptw.pmp, csr.io.pmp connect io.ptw.hstatus, csr.io.hstatus connect io.ptw.gstatus, csr.io.gstatus connect io.ptw.hgatp, csr.io.hgatp connect io.ptw.vsatp, csr.io.vsatp connect io.trace.time, csr.io.time connect io.trace.insns, csr.io.trace connect io.fcsr_rm, csr.io.fcsr_rm node _csr_io_rw_addr_T = bits(com_uops_reg[0].bits.inst, 31, 20) node _csr_io_rw_addr_T_1 = mux(com_uops_reg[0].valid, _csr_io_rw_addr_T, UInt<1>(0h0)) connect csr.io.rw.addr, _csr_io_rw_addr_T_1 node _csr_io_rw_cmd_T = eq(com_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _csr_io_rw_cmd_T_1 = and(com_uops_reg[0].valid, _csr_io_rw_cmd_T) node _csr_io_rw_cmd_T_2 = mux(_csr_io_rw_cmd_T_1, UInt<1>(0h0), UInt<3>(0h4)) node _csr_io_rw_cmd_T_3 = not(_csr_io_rw_cmd_T_2) node _csr_io_rw_cmd_T_4 = and(com_uops_reg[0].bits.ctrl.csr, _csr_io_rw_cmd_T_3) connect csr.io.rw.cmd, _csr_io_rw_cmd_T_4 connect csr.io.rw.wdata, com_uops_reg[0].bits.wdata.bits node _T_274 = neq(com_uops_reg[0].bits.ctrl.csr, UInt<3>(0h0)) when _T_274 : connect com_uops[0].bits.wdata.valid, UInt<1>(0h1) connect com_uops[0].bits.wdata.bits, csr.io.rw.rdata when csr.io.rw_stall : connect com_uops[0].bits.needs_replay, UInt<1>(0h1) node _T_275 = eq(com_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _T_276 = and(com_uops_reg[0].valid, _T_275) node _T_277 = eq(com_uops_reg[0].bits.needs_replay, UInt<1>(0h0)) node _T_278 = and(_T_276, _T_277) node _T_279 = and(_T_278, com_uops_reg[0].bits.ctrl.fence_i) when _T_279 : connect io.imem.flush_icache, UInt<1>(0h1) connect csr.io.fcsr_flags.valid, UInt<1>(0h0) connect csr.io.set_fs_dirty, UInt<1>(0h0) wire csr_fcsr_flags : UInt<5>[4] connect csr_fcsr_flags[0], UInt<1>(0h0) connect csr_fcsr_flags[1], UInt<1>(0h0) connect csr_fcsr_flags[2], UInt<1>(0h0) connect csr_fcsr_flags[3], UInt<1>(0h0) node _csr_io_fcsr_flags_bits_T = or(csr_fcsr_flags[0], csr_fcsr_flags[1]) node _csr_io_fcsr_flags_bits_T_1 = or(_csr_io_fcsr_flags_bits_T, csr_fcsr_flags[2]) node _csr_io_fcsr_flags_bits_T_2 = or(_csr_io_fcsr_flags_bits_T_1, csr_fcsr_flags[3]) connect csr.io.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T_2 node _com_uops_0_bits_xcpt_T = and(com_uops_reg[0].valid, com_uops_reg[0].bits.xcpt) connect com_uops[0].bits.xcpt, _com_uops_0_bits_xcpt_T connect com_uops[0].bits.xcpt_cause, com_uops_reg[0].bits.xcpt_cause node _T_280 = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.mem) node _T_281 = and(_T_280, io.dmem.s2_nack) when _T_281 : connect com_uops[0].bits.needs_replay, UInt<1>(0h1) node _T_282 = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.rocc) node _T_283 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) when _T_284 : connect com_uops[0].bits.needs_replay, UInt<1>(0h1) node _T_285 = and(com_uops_reg[1].valid, com_uops_reg[1].bits.ctrl.mem) node _T_286 = and(_T_285, io.dmem.s2_nack) when _T_286 : connect com_uops[1].bits.needs_replay, UInt<1>(0h1) node _T_287 = and(com_uops_reg[1].valid, com_uops_reg[1].bits.ctrl.rocc) node _T_288 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node _T_289 = and(_T_287, _T_288) when _T_289 : connect com_uops[1].bits.needs_replay, UInt<1>(0h1) node _T_290 = and(com_uops_reg[1].valid, com_uops_reg[1].bits.xcpt) when _T_290 : connect com_uops[1].bits.needs_replay, UInt<1>(0h1) node waddr = bits(com_uops[0].bits.inst, 11, 7) node _T_291 = and(com_uops[0].bits.ctrl.wxd, com_uops[0].bits.ctrl.mem) node _T_292 = and(_T_291, io.dmem.s2_hit) when _T_292 : connect com_uops[0].bits.wdata.valid, UInt<1>(0h1) connect com_uops[0].bits.wdata.bits, io.dmem.resp.bits.data node _com_bypasses_0_valid_T = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.wxd) connect com_bypasses_0.valid, _com_bypasses_0_valid_T node _com_bypasses_0_dst_T = bits(com_uops_reg[0].bits.inst, 11, 7) connect com_bypasses_0.dst, _com_bypasses_0_dst_T connect com_bypasses_0.can_bypass, com_uops[0].bits.wdata.valid connect com_bypasses_0.data, com_uops[0].bits.wdata.bits node _T_293 = and(com_retire[0], com_uops[0].bits.ctrl.wfd) when _T_293 : connect fsboard_clear[waddr], UInt<1>(0h1) node _fp_com_bypasses_0_valid_T = and(com_uops_reg[0].valid, com_uops_reg[0].bits.ctrl.wfd) connect fp_com_bypasses_0.valid, _fp_com_bypasses_0_valid_T node _fp_com_bypasses_0_dst_T = bits(com_uops_reg[0].bits.inst, 11, 7) connect fp_com_bypasses_0.dst, _fp_com_bypasses_0_dst_T connect fp_com_bypasses_0.can_bypass, UInt<1>(0h0) invalidate fp_com_bypasses_0.data node waddr_1 = bits(com_uops[1].bits.inst, 11, 7) node _T_294 = and(com_uops[1].bits.ctrl.wxd, com_uops[1].bits.ctrl.mem) node _T_295 = and(_T_294, io.dmem.s2_hit) when _T_295 : connect com_uops[1].bits.wdata.valid, UInt<1>(0h1) connect com_uops[1].bits.wdata.bits, io.dmem.resp.bits.data node _com_bypasses_1_valid_T = and(com_uops_reg[1].valid, com_uops_reg[1].bits.ctrl.wxd) connect com_bypasses_1.valid, _com_bypasses_1_valid_T node _com_bypasses_1_dst_T = bits(com_uops_reg[1].bits.inst, 11, 7) connect com_bypasses_1.dst, _com_bypasses_1_dst_T connect com_bypasses_1.can_bypass, com_uops[1].bits.wdata.valid connect com_bypasses_1.data, com_uops[1].bits.wdata.bits node _T_296 = and(com_retire[1], com_uops[1].bits.ctrl.wfd) when _T_296 : connect fsboard_clear[waddr_1], UInt<1>(0h1) node _fp_com_bypasses_1_valid_T = and(com_uops_reg[1].valid, com_uops_reg[1].bits.ctrl.wfd) connect fp_com_bypasses_1.valid, _fp_com_bypasses_1_valid_T node _fp_com_bypasses_1_dst_T = bits(com_uops_reg[1].bits.inst, 11, 7) connect fp_com_bypasses_1.dst, _fp_com_bypasses_1_dst_T connect fp_com_bypasses_1.can_bypass, UInt<1>(0h0) invalidate fp_com_bypasses_1.data node _T_297 = and(com_uops_reg[0].bits.fp_ctrl.ldst, com_uops_reg[0].bits.fp_ctrl.wen) node _T_298 = eq(_T_297, UInt<1>(0h0)) node _T_299 = and(com_uops_reg[0].bits.ctrl.fp, _T_298) node _T_300 = and(com_uops_reg[0].valid, _T_299) node _T_301 = and(_T_300, com_uops_reg[0].bits.fp_ctrl.toint) node _T_302 = eq(com_uops_reg[0].bits.xcpt, UInt<1>(0h0)) node _T_303 = and(_T_301, _T_302) when _T_303 : connect csr.io.fcsr_flags.valid, UInt<1>(0h1) connect csr_fcsr_flags[0], com_uops_reg[0].bits.fexc when UInt<1>(0h0) : connect csr.io.fcsr_flags.valid, UInt<1>(0h1) connect csr_fcsr_flags[3], UInt<1>(0h0) connect io.imem.sfence.valid, UInt<1>(0h0) connect io.ptw.sfence.bits.hg, io.imem.sfence.bits.hg connect io.ptw.sfence.bits.hv, io.imem.sfence.bits.hv connect io.ptw.sfence.bits.asid, io.imem.sfence.bits.asid connect io.ptw.sfence.bits.addr, io.imem.sfence.bits.addr connect io.ptw.sfence.bits.rs2, io.imem.sfence.bits.rs2 connect io.ptw.sfence.bits.rs1, io.imem.sfence.bits.rs1 connect io.ptw.sfence.valid, io.imem.sfence.valid node _io_imem_sfence_bits_rs1_T = bits(com_uops_reg[0].bits.mem_size, 0, 0) connect io.imem.sfence.bits.rs1, _io_imem_sfence_bits_rs1_T node _io_imem_sfence_bits_rs2_T = bits(com_uops_reg[0].bits.mem_size, 1, 1) connect io.imem.sfence.bits.rs2, _io_imem_sfence_bits_rs2_T connect io.imem.sfence.bits.addr, com_uops_reg[0].bits.wdata.bits connect io.imem.sfence.bits.asid, com_uops_reg[0].bits.rs2_data node _io_imem_sfence_bits_hv_T = eq(com_uops_reg[0].bits.ctrl.mem_cmd, UInt<5>(0h15)) connect io.imem.sfence.bits.hv, _io_imem_sfence_bits_hv_T node _io_imem_sfence_bits_hg_T = eq(com_uops_reg[0].bits.ctrl.mem_cmd, UInt<5>(0h16)) connect io.imem.sfence.bits.hg, _io_imem_sfence_bits_hg_T node _T_304 = eq(com_uops[0].bits.ctrl.mem_cmd, UInt<5>(0h14)) node _T_305 = and(com_uops[0].bits.ctrl.mem, _T_304) node _T_306 = and(com_uops[0].valid, _T_305) node _T_307 = eq(com_uops[0].bits.xcpt, UInt<1>(0h0)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(com_uops[0].bits.needs_replay, UInt<1>(0h0)) node _T_310 = and(_T_308, _T_309) when _T_310 : connect io.imem.sfence.valid, UInt<1>(0h1) node xcpt_4 = or(com_uops[1].bits.xcpt, csr.io.eret) node _flush_before_next_T = eq(com_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _flush_before_next_T_1 = eq(com_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _flush_before_next_T_2 = eq(com_uops[1].bits.ctrl.csr, UInt<3>(0h5)) node _flush_before_next_T_3 = or(_flush_before_next_T, _flush_before_next_T_1) node _flush_before_next_T_4 = or(_flush_before_next_T_3, _flush_before_next_T_2) node _flush_before_next_T_5 = eq(com_uops[1].bits.ctrl.csr, UInt<3>(0h6)) node _flush_before_next_T_6 = eq(com_uops[1].bits.ctrl.csr, UInt<3>(0h7)) node _flush_before_next_T_7 = or(_flush_before_next_T_5, _flush_before_next_T_6) node _flush_before_next_T_8 = bits(com_uops[1].bits.inst, 19, 15) node _flush_before_next_T_9 = eq(_flush_before_next_T_8, UInt<1>(0h0)) node _flush_before_next_T_10 = and(_flush_before_next_T_7, _flush_before_next_T_9) node _flush_before_next_T_11 = eq(_flush_before_next_T_10, UInt<1>(0h0)) node _flush_before_next_T_12 = and(_flush_before_next_T_4, _flush_before_next_T_11) node flush_before_next = or(_flush_before_next_T_12, com_uops[1].bits.flush_pipe) node _T_311 = or(com_uops[1].bits.needs_replay, xcpt_4) node _T_312 = or(_T_311, flush_before_next) node _T_313 = and(com_uops[1].valid, _T_312) when _T_313 : connect io.imem.redirect_val, UInt<1>(0h1) connect io.imem.redirect_flush, UInt<1>(0h1) node _io_imem_redirect_pc_T = mux(com_uops[1].bits.rvc, UInt<2>(0h2), UInt<3>(0h4)) node _io_imem_redirect_pc_T_1 = add(com_uops[1].bits.pc, _io_imem_redirect_pc_T) node _io_imem_redirect_pc_T_2 = tail(_io_imem_redirect_pc_T_1, 1) node _io_imem_redirect_pc_T_3 = mux(xcpt_4, csr.io.evec, _io_imem_redirect_pc_T_2) node _io_imem_redirect_pc_T_4 = mux(com_uops[1].bits.needs_replay, com_uops[1].bits.pc, _io_imem_redirect_pc_T_3) connect io.imem.redirect_pc, _io_imem_redirect_pc_T_4 connect io.imem.redirect_ras_head, com_uops[1].bits.ras_head connect kill_mem, UInt<1>(0h1) connect flush_rrd_ex, UInt<1>(0h1) node xcpt_5 = or(com_uops[0].bits.xcpt, csr.io.eret) node _flush_before_next_T_13 = eq(com_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _flush_before_next_T_14 = eq(com_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _flush_before_next_T_15 = eq(com_uops[0].bits.ctrl.csr, UInt<3>(0h5)) node _flush_before_next_T_16 = or(_flush_before_next_T_13, _flush_before_next_T_14) node _flush_before_next_T_17 = or(_flush_before_next_T_16, _flush_before_next_T_15) node _flush_before_next_T_18 = eq(com_uops[0].bits.ctrl.csr, UInt<3>(0h6)) node _flush_before_next_T_19 = eq(com_uops[0].bits.ctrl.csr, UInt<3>(0h7)) node _flush_before_next_T_20 = or(_flush_before_next_T_18, _flush_before_next_T_19) node _flush_before_next_T_21 = bits(com_uops[0].bits.inst, 19, 15) node _flush_before_next_T_22 = eq(_flush_before_next_T_21, UInt<1>(0h0)) node _flush_before_next_T_23 = and(_flush_before_next_T_20, _flush_before_next_T_22) node _flush_before_next_T_24 = eq(_flush_before_next_T_23, UInt<1>(0h0)) node _flush_before_next_T_25 = and(_flush_before_next_T_17, _flush_before_next_T_24) node flush_before_next_1 = or(_flush_before_next_T_25, com_uops[0].bits.flush_pipe) node _T_314 = or(com_uops[0].bits.needs_replay, xcpt_5) node _T_315 = or(_T_314, flush_before_next_1) node _T_316 = and(com_uops[0].valid, _T_315) when _T_316 : connect io.imem.redirect_val, UInt<1>(0h1) connect io.imem.redirect_flush, UInt<1>(0h1) node _io_imem_redirect_pc_T_5 = mux(com_uops[0].bits.rvc, UInt<2>(0h2), UInt<3>(0h4)) node _io_imem_redirect_pc_T_6 = add(com_uops[0].bits.pc, _io_imem_redirect_pc_T_5) node _io_imem_redirect_pc_T_7 = tail(_io_imem_redirect_pc_T_6, 1) node _io_imem_redirect_pc_T_8 = mux(xcpt_5, csr.io.evec, _io_imem_redirect_pc_T_7) node _io_imem_redirect_pc_T_9 = mux(com_uops[0].bits.needs_replay, com_uops[0].bits.pc, _io_imem_redirect_pc_T_8) connect io.imem.redirect_pc, _io_imem_redirect_pc_T_9 connect io.imem.redirect_ras_head, com_uops[0].bits.ras_head connect kill_mem, UInt<1>(0h1) connect flush_rrd_ex, UInt<1>(0h1) connect kill_com[1], UInt<1>(0h1) when com_uops_reg[1].bits.uses_latealu : node _T_317 = bits(com_uops_reg[1].bits.inst, 19, 15) node _T_318 = bits(com_uops_reg[0].bits.inst, 11, 7) node _T_319 = eq(_T_317, _T_318) when _T_319 : connect wb_uops_reg[1].bits.rs1_data, io.dmem.resp.bits.data node _T_320 = bits(com_uops_reg[1].bits.inst, 24, 20) node _T_321 = bits(com_uops_reg[0].bits.inst, 11, 7) node _T_322 = eq(_T_320, _T_321) when _T_322 : connect wb_uops_reg[1].bits.rs2_data, io.dmem.resp.bits.data node _T_323 = eq(io.dmem.s2_hit, UInt<1>(0h0)) when _T_323 : connect com_uops[1].bits.needs_replay, UInt<1>(0h1) node wen = and(wb_uops[0].valid, wb_uops[0].bits.ctrl.wxd) node _T_324 = eq(wb_uops[0].bits.wdata.valid, UInt<1>(0h0)) node _T_325 = and(wen, _T_324) when _T_325 : node _T_326 = bits(wb_uops[0].bits.inst, 11, 7) connect isboard_clear[_T_326], UInt<1>(0h1) node _T_327 = and(wen, wb_uops[0].bits.wdata.valid) when _T_327 : node _T_328 = bits(wb_uops[0].bits.inst, 11, 7) connect iregfile[_T_328], wb_uops[0].bits.wdata.bits node _T_329 = bits(wb_uops[0].bits.inst, 11, 7) connect isboard_set[_T_329], UInt<1>(0h1) node _T_330 = and(wen, wb_uops[0].bits.wdata.valid) node _T_331 = bits(wb_uops[0].bits.inst, 11, 7) inst debug_rob_push_wb of DebugROBPushWb connect debug_rob_push_wb.clock, clock connect debug_rob_push_wb.reset, reset connect debug_rob_push_wb.hartid, io.hartid connect debug_rob_push_wb.valid, _T_330 connect debug_rob_push_wb.wb_tag, _T_331 connect debug_rob_push_wb.wb_data, wb_uops[0].bits.wdata.bits node _wb_bypasses_0_valid_T = and(wb_uops[0].valid, wb_uops[0].bits.ctrl.wxd) connect wb_bypasses_0.valid, _wb_bypasses_0_valid_T node _wb_bypasses_0_dst_T = bits(wb_uops[0].bits.inst, 11, 7) connect wb_bypasses_0.dst, _wb_bypasses_0_dst_T connect wb_bypasses_0.can_bypass, wb_uops[0].bits.wdata.valid connect wb_bypasses_0.data, wb_uops[0].bits.wdata.bits node _T_332 = and(wb_uops_reg[1].valid, wb_uops_reg[1].bits.uses_latealu) when _T_332 : connect mem_alu_uops_0.flush_pipe, wb_uops_reg[1].bits.flush_pipe connect mem_alu_uops_0.mem_size, wb_uops_reg[1].bits.mem_size connect mem_alu_uops_0.fdivin, wb_uops_reg[1].bits.fdivin connect mem_alu_uops_0.fexc, wb_uops_reg[1].bits.fexc connect mem_alu_uops_0.fra3, wb_uops_reg[1].bits.fra3 connect mem_alu_uops_0.fra2, wb_uops_reg[1].bits.fra2 connect mem_alu_uops_0.fra1, wb_uops_reg[1].bits.fra1 connect mem_alu_uops_0.wdata, wb_uops_reg[1].bits.wdata connect mem_alu_uops_0.uses_latealu, wb_uops_reg[1].bits.uses_latealu connect mem_alu_uops_0.uses_memalu, wb_uops_reg[1].bits.uses_memalu connect mem_alu_uops_0.rs3_data, wb_uops_reg[1].bits.rs3_data connect mem_alu_uops_0.rs2_data, wb_uops_reg[1].bits.rs2_data connect mem_alu_uops_0.rs1_data, wb_uops_reg[1].bits.rs1_data connect mem_alu_uops_0.needs_replay, wb_uops_reg[1].bits.needs_replay connect mem_alu_uops_0.xcpt_cause, wb_uops_reg[1].bits.xcpt_cause connect mem_alu_uops_0.xcpt, wb_uops_reg[1].bits.xcpt connect mem_alu_uops_0.taken, wb_uops_reg[1].bits.taken connect mem_alu_uops_0.ras_head, wb_uops_reg[1].bits.ras_head connect mem_alu_uops_0.next_pc, wb_uops_reg[1].bits.next_pc connect mem_alu_uops_0.sfb_shadow, wb_uops_reg[1].bits.sfb_shadow connect mem_alu_uops_0.sfb_br, wb_uops_reg[1].bits.sfb_br connect mem_alu_uops_0.btb_resp, wb_uops_reg[1].bits.btb_resp connect mem_alu_uops_0.sets_vcfg, wb_uops_reg[1].bits.sets_vcfg connect mem_alu_uops_0.rvc, wb_uops_reg[1].bits.rvc connect mem_alu_uops_0.fp_ctrl, wb_uops_reg[1].bits.fp_ctrl connect mem_alu_uops_0.ctrl, wb_uops_reg[1].bits.ctrl connect mem_alu_uops_0.edge_inst, wb_uops_reg[1].bits.edge_inst connect mem_alu_uops_0.pc, wb_uops_reg[1].bits.pc connect mem_alu_uops_0.raw_inst, wb_uops_reg[1].bits.raw_inst connect mem_alu_uops_0.inst, wb_uops_reg[1].bits.inst connect wb_uops[1].bits.wdata.valid, UInt<1>(0h1) connect wb_uops[1].bits.wdata.bits, mem_alus_0.io.out node wen_1 = and(wb_uops[1].valid, wb_uops[1].bits.ctrl.wxd) node _T_333 = eq(wb_uops[1].bits.wdata.valid, UInt<1>(0h0)) node _T_334 = and(wen_1, _T_333) when _T_334 : node _T_335 = bits(wb_uops[1].bits.inst, 11, 7) connect isboard_clear[_T_335], UInt<1>(0h1) node _T_336 = and(wen_1, wb_uops[1].bits.wdata.valid) when _T_336 : node _T_337 = bits(wb_uops[1].bits.inst, 11, 7) connect iregfile[_T_337], wb_uops[1].bits.wdata.bits node _T_338 = bits(wb_uops[1].bits.inst, 11, 7) connect isboard_set[_T_338], UInt<1>(0h1) node _T_339 = and(wen_1, wb_uops[1].bits.wdata.valid) node _T_340 = bits(wb_uops[1].bits.inst, 11, 7) inst debug_rob_push_wb_1 of DebugROBPushWb_1 connect debug_rob_push_wb_1.clock, clock connect debug_rob_push_wb_1.reset, reset connect debug_rob_push_wb_1.hartid, io.hartid connect debug_rob_push_wb_1.valid, _T_339 connect debug_rob_push_wb_1.wb_tag, _T_340 connect debug_rob_push_wb_1.wb_data, wb_uops[1].bits.wdata.bits node _wb_bypasses_1_valid_T = and(wb_uops[1].valid, wb_uops[1].bits.ctrl.wxd) connect wb_bypasses_1.valid, _wb_bypasses_1_valid_T node _wb_bypasses_1_dst_T = bits(wb_uops[1].bits.inst, 11, 7) connect wb_bypasses_1.dst, _wb_bypasses_1_dst_T connect wb_bypasses_1.can_bypass, wb_uops[1].bits.wdata.valid connect wb_bypasses_1.data, wb_uops[1].bits.wdata.bits node _dmem_xpu_T = bits(io.dmem.resp.bits.tag, 0, 0) node dmem_xpu = eq(_dmem_xpu_T, UInt<1>(0h0)) node dmem_fpu = bits(io.dmem.resp.bits.tag, 0, 0) node dmem_waddr = bits(io.dmem.resp.bits.tag, 5, 1) inst ll_arb of Arbiter3_LLWB connect ll_arb.clock, clock connect ll_arb.reset, reset connect ll_arb.io.out.ready, UInt<1>(0h1) node _ll_arb_io_in_0_valid_T = eq(io.dmem.s2_hit, UInt<1>(0h0)) node _ll_arb_io_in_0_valid_T_1 = or(_ll_arb_io_in_0_valid_T, io.dmem.s2_kill) node _ll_arb_io_in_0_valid_T_2 = and(io.dmem.resp.valid, _ll_arb_io_in_0_valid_T_1) node _ll_arb_io_in_0_valid_T_3 = and(_ll_arb_io_in_0_valid_T_2, io.dmem.resp.bits.has_data) node _ll_arb_io_in_0_valid_T_4 = and(_ll_arb_io_in_0_valid_T_3, dmem_xpu) regreset ll_arb_io_in_0_valid_REG : UInt<1>, clock, reset, UInt<1>(0h0) connect ll_arb_io_in_0_valid_REG, _ll_arb_io_in_0_valid_T_4 connect ll_arb.io.in[0].valid, ll_arb_io_in_0_valid_REG reg ll_arb_io_in_0_bits_waddr_r : UInt<5>, clock when io.dmem.resp.valid : connect ll_arb_io_in_0_bits_waddr_r, dmem_waddr connect ll_arb.io.in[0].bits.waddr, ll_arb_io_in_0_bits_waddr_r reg ll_arb_io_in_0_bits_wdata_r : UInt<64>, clock when io.dmem.resp.valid : connect ll_arb_io_in_0_bits_wdata_r, io.dmem.resp.bits.data connect ll_arb.io.in[0].bits.wdata, ll_arb_io_in_0_bits_wdata_r connect ll_arb.io.in[1].valid, div.io.resp.valid connect div.io.resp.ready, ll_arb.io.in[1].ready connect ll_arb.io.in[1].bits.waddr, div.io.resp.bits.tag connect ll_arb.io.in[1].bits.wdata, div.io.resp.bits.data connect ll_arb.io.in[2].valid, io.rocc.resp.valid connect io.rocc.resp.ready, ll_arb.io.in[2].ready connect ll_arb.io.in[2].bits.waddr, io.rocc.resp.bits.rd connect ll_arb.io.in[2].bits.wdata, io.rocc.resp.bits.data connect ll_bypass_0.valid, ll_arb.io.out.valid connect ll_bypass_0.dst, ll_arb.io.out.bits.waddr connect ll_bypass_0.data, ll_arb.io.out.bits.wdata connect ll_bypass_0.can_bypass, UInt<1>(0h1) when ll_arb.io.out.valid : connect iregfile[ll_arb.io.out.bits.waddr], ll_arb.io.out.bits.wdata connect isboard_set[ll_arb.io.out.bits.waddr], UInt<1>(0h1) node _fp_load_val_T = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) node _fp_load_val_T_1 = and(_fp_load_val_T, dmem_fpu) regreset fp_load_val : UInt<1>, clock, reset, UInt<1>(0h0) connect fp_load_val, _fp_load_val_T_1 node _fp_load_type_T = sub(io.dmem.resp.bits.size, UInt<1>(0h1)) node _fp_load_type_T_1 = tail(_fp_load_type_T, 1) reg fp_load_type : UInt<2>, clock when io.dmem.resp.valid : connect fp_load_type, _fp_load_type_T_1 node _fp_load_addr_T = bits(io.dmem.resp.bits.tag, 5, 1) reg fp_load_addr : UInt<5>, clock when io.dmem.resp.valid : connect fp_load_addr, _fp_load_addr_T reg fp_load_data : UInt<64>, clock when io.dmem.resp.valid : connect fp_load_data, io.dmem.resp.bits.data wire ll_fp_wval : UInt<1> connect ll_fp_wval, fp_load_val wire ll_fp_wdata : UInt<65> connect ll_fp_wdata, UInt<65>(0h0) wire ll_fp_waddr : UInt connect ll_fp_waddr, fp_load_addr when fp_load_val : connect ll_fp_wval, UInt<1>(0h1) node _ll_fp_wdata_T = eq(fp_load_type, UInt<1>(0h1)) node _ll_fp_wdata_T_1 = mux(_ll_fp_wdata_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000)) node _ll_fp_wdata_T_2 = eq(fp_load_type, UInt<2>(0h2)) node _ll_fp_wdata_T_3 = mux(_ll_fp_wdata_T_2, UInt<1>(0h0), _ll_fp_wdata_T_1) node _ll_fp_wdata_T_4 = eq(fp_load_type, UInt<2>(0h3)) node _ll_fp_wdata_T_5 = mux(_ll_fp_wdata_T_4, UInt<1>(0h0), _ll_fp_wdata_T_3) node _ll_fp_wdata_T_6 = or(_ll_fp_wdata_T_5, fp_load_data) node ll_fp_wdata_rawIn_sign = bits(_ll_fp_wdata_T_6, 63, 63) node ll_fp_wdata_rawIn_expIn = bits(_ll_fp_wdata_T_6, 62, 52) node ll_fp_wdata_rawIn_fractIn = bits(_ll_fp_wdata_T_6, 51, 0) node ll_fp_wdata_rawIn_isZeroExpIn = eq(ll_fp_wdata_rawIn_expIn, UInt<1>(0h0)) node ll_fp_wdata_rawIn_isZeroFractIn = eq(ll_fp_wdata_rawIn_fractIn, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_normDist_T = bits(ll_fp_wdata_rawIn_fractIn, 0, 0) node _ll_fp_wdata_rawIn_normDist_T_1 = bits(ll_fp_wdata_rawIn_fractIn, 1, 1) node _ll_fp_wdata_rawIn_normDist_T_2 = bits(ll_fp_wdata_rawIn_fractIn, 2, 2) node _ll_fp_wdata_rawIn_normDist_T_3 = bits(ll_fp_wdata_rawIn_fractIn, 3, 3) node _ll_fp_wdata_rawIn_normDist_T_4 = bits(ll_fp_wdata_rawIn_fractIn, 4, 4) node _ll_fp_wdata_rawIn_normDist_T_5 = bits(ll_fp_wdata_rawIn_fractIn, 5, 5) node _ll_fp_wdata_rawIn_normDist_T_6 = bits(ll_fp_wdata_rawIn_fractIn, 6, 6) node _ll_fp_wdata_rawIn_normDist_T_7 = bits(ll_fp_wdata_rawIn_fractIn, 7, 7) node _ll_fp_wdata_rawIn_normDist_T_8 = bits(ll_fp_wdata_rawIn_fractIn, 8, 8) node _ll_fp_wdata_rawIn_normDist_T_9 = bits(ll_fp_wdata_rawIn_fractIn, 9, 9) node _ll_fp_wdata_rawIn_normDist_T_10 = bits(ll_fp_wdata_rawIn_fractIn, 10, 10) node _ll_fp_wdata_rawIn_normDist_T_11 = bits(ll_fp_wdata_rawIn_fractIn, 11, 11) node _ll_fp_wdata_rawIn_normDist_T_12 = bits(ll_fp_wdata_rawIn_fractIn, 12, 12) node _ll_fp_wdata_rawIn_normDist_T_13 = bits(ll_fp_wdata_rawIn_fractIn, 13, 13) node _ll_fp_wdata_rawIn_normDist_T_14 = bits(ll_fp_wdata_rawIn_fractIn, 14, 14) node _ll_fp_wdata_rawIn_normDist_T_15 = bits(ll_fp_wdata_rawIn_fractIn, 15, 15) node _ll_fp_wdata_rawIn_normDist_T_16 = bits(ll_fp_wdata_rawIn_fractIn, 16, 16) node _ll_fp_wdata_rawIn_normDist_T_17 = bits(ll_fp_wdata_rawIn_fractIn, 17, 17) node _ll_fp_wdata_rawIn_normDist_T_18 = bits(ll_fp_wdata_rawIn_fractIn, 18, 18) node _ll_fp_wdata_rawIn_normDist_T_19 = bits(ll_fp_wdata_rawIn_fractIn, 19, 19) node _ll_fp_wdata_rawIn_normDist_T_20 = bits(ll_fp_wdata_rawIn_fractIn, 20, 20) node _ll_fp_wdata_rawIn_normDist_T_21 = bits(ll_fp_wdata_rawIn_fractIn, 21, 21) node _ll_fp_wdata_rawIn_normDist_T_22 = bits(ll_fp_wdata_rawIn_fractIn, 22, 22) node _ll_fp_wdata_rawIn_normDist_T_23 = bits(ll_fp_wdata_rawIn_fractIn, 23, 23) node _ll_fp_wdata_rawIn_normDist_T_24 = bits(ll_fp_wdata_rawIn_fractIn, 24, 24) node _ll_fp_wdata_rawIn_normDist_T_25 = bits(ll_fp_wdata_rawIn_fractIn, 25, 25) node _ll_fp_wdata_rawIn_normDist_T_26 = bits(ll_fp_wdata_rawIn_fractIn, 26, 26) node _ll_fp_wdata_rawIn_normDist_T_27 = bits(ll_fp_wdata_rawIn_fractIn, 27, 27) node _ll_fp_wdata_rawIn_normDist_T_28 = bits(ll_fp_wdata_rawIn_fractIn, 28, 28) node _ll_fp_wdata_rawIn_normDist_T_29 = bits(ll_fp_wdata_rawIn_fractIn, 29, 29) node _ll_fp_wdata_rawIn_normDist_T_30 = bits(ll_fp_wdata_rawIn_fractIn, 30, 30) node _ll_fp_wdata_rawIn_normDist_T_31 = bits(ll_fp_wdata_rawIn_fractIn, 31, 31) node _ll_fp_wdata_rawIn_normDist_T_32 = bits(ll_fp_wdata_rawIn_fractIn, 32, 32) node _ll_fp_wdata_rawIn_normDist_T_33 = bits(ll_fp_wdata_rawIn_fractIn, 33, 33) node _ll_fp_wdata_rawIn_normDist_T_34 = bits(ll_fp_wdata_rawIn_fractIn, 34, 34) node _ll_fp_wdata_rawIn_normDist_T_35 = bits(ll_fp_wdata_rawIn_fractIn, 35, 35) node _ll_fp_wdata_rawIn_normDist_T_36 = bits(ll_fp_wdata_rawIn_fractIn, 36, 36) node _ll_fp_wdata_rawIn_normDist_T_37 = bits(ll_fp_wdata_rawIn_fractIn, 37, 37) node _ll_fp_wdata_rawIn_normDist_T_38 = bits(ll_fp_wdata_rawIn_fractIn, 38, 38) node _ll_fp_wdata_rawIn_normDist_T_39 = bits(ll_fp_wdata_rawIn_fractIn, 39, 39) node _ll_fp_wdata_rawIn_normDist_T_40 = bits(ll_fp_wdata_rawIn_fractIn, 40, 40) node _ll_fp_wdata_rawIn_normDist_T_41 = bits(ll_fp_wdata_rawIn_fractIn, 41, 41) node _ll_fp_wdata_rawIn_normDist_T_42 = bits(ll_fp_wdata_rawIn_fractIn, 42, 42) node _ll_fp_wdata_rawIn_normDist_T_43 = bits(ll_fp_wdata_rawIn_fractIn, 43, 43) node _ll_fp_wdata_rawIn_normDist_T_44 = bits(ll_fp_wdata_rawIn_fractIn, 44, 44) node _ll_fp_wdata_rawIn_normDist_T_45 = bits(ll_fp_wdata_rawIn_fractIn, 45, 45) node _ll_fp_wdata_rawIn_normDist_T_46 = bits(ll_fp_wdata_rawIn_fractIn, 46, 46) node _ll_fp_wdata_rawIn_normDist_T_47 = bits(ll_fp_wdata_rawIn_fractIn, 47, 47) node _ll_fp_wdata_rawIn_normDist_T_48 = bits(ll_fp_wdata_rawIn_fractIn, 48, 48) node _ll_fp_wdata_rawIn_normDist_T_49 = bits(ll_fp_wdata_rawIn_fractIn, 49, 49) node _ll_fp_wdata_rawIn_normDist_T_50 = bits(ll_fp_wdata_rawIn_fractIn, 50, 50) node _ll_fp_wdata_rawIn_normDist_T_51 = bits(ll_fp_wdata_rawIn_fractIn, 51, 51) node _ll_fp_wdata_rawIn_normDist_T_52 = mux(_ll_fp_wdata_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) node _ll_fp_wdata_rawIn_normDist_T_53 = mux(_ll_fp_wdata_rawIn_normDist_T_2, UInt<6>(0h31), _ll_fp_wdata_rawIn_normDist_T_52) node _ll_fp_wdata_rawIn_normDist_T_54 = mux(_ll_fp_wdata_rawIn_normDist_T_3, UInt<6>(0h30), _ll_fp_wdata_rawIn_normDist_T_53) node _ll_fp_wdata_rawIn_normDist_T_55 = mux(_ll_fp_wdata_rawIn_normDist_T_4, UInt<6>(0h2f), _ll_fp_wdata_rawIn_normDist_T_54) node _ll_fp_wdata_rawIn_normDist_T_56 = mux(_ll_fp_wdata_rawIn_normDist_T_5, UInt<6>(0h2e), _ll_fp_wdata_rawIn_normDist_T_55) node _ll_fp_wdata_rawIn_normDist_T_57 = mux(_ll_fp_wdata_rawIn_normDist_T_6, UInt<6>(0h2d), _ll_fp_wdata_rawIn_normDist_T_56) node _ll_fp_wdata_rawIn_normDist_T_58 = mux(_ll_fp_wdata_rawIn_normDist_T_7, UInt<6>(0h2c), _ll_fp_wdata_rawIn_normDist_T_57) node _ll_fp_wdata_rawIn_normDist_T_59 = mux(_ll_fp_wdata_rawIn_normDist_T_8, UInt<6>(0h2b), _ll_fp_wdata_rawIn_normDist_T_58) node _ll_fp_wdata_rawIn_normDist_T_60 = mux(_ll_fp_wdata_rawIn_normDist_T_9, UInt<6>(0h2a), _ll_fp_wdata_rawIn_normDist_T_59) node _ll_fp_wdata_rawIn_normDist_T_61 = mux(_ll_fp_wdata_rawIn_normDist_T_10, UInt<6>(0h29), _ll_fp_wdata_rawIn_normDist_T_60) node _ll_fp_wdata_rawIn_normDist_T_62 = mux(_ll_fp_wdata_rawIn_normDist_T_11, UInt<6>(0h28), _ll_fp_wdata_rawIn_normDist_T_61) node _ll_fp_wdata_rawIn_normDist_T_63 = mux(_ll_fp_wdata_rawIn_normDist_T_12, UInt<6>(0h27), _ll_fp_wdata_rawIn_normDist_T_62) node _ll_fp_wdata_rawIn_normDist_T_64 = mux(_ll_fp_wdata_rawIn_normDist_T_13, UInt<6>(0h26), _ll_fp_wdata_rawIn_normDist_T_63) node _ll_fp_wdata_rawIn_normDist_T_65 = mux(_ll_fp_wdata_rawIn_normDist_T_14, UInt<6>(0h25), _ll_fp_wdata_rawIn_normDist_T_64) node _ll_fp_wdata_rawIn_normDist_T_66 = mux(_ll_fp_wdata_rawIn_normDist_T_15, UInt<6>(0h24), _ll_fp_wdata_rawIn_normDist_T_65) node _ll_fp_wdata_rawIn_normDist_T_67 = mux(_ll_fp_wdata_rawIn_normDist_T_16, UInt<6>(0h23), _ll_fp_wdata_rawIn_normDist_T_66) node _ll_fp_wdata_rawIn_normDist_T_68 = mux(_ll_fp_wdata_rawIn_normDist_T_17, UInt<6>(0h22), _ll_fp_wdata_rawIn_normDist_T_67) node _ll_fp_wdata_rawIn_normDist_T_69 = mux(_ll_fp_wdata_rawIn_normDist_T_18, UInt<6>(0h21), _ll_fp_wdata_rawIn_normDist_T_68) node _ll_fp_wdata_rawIn_normDist_T_70 = mux(_ll_fp_wdata_rawIn_normDist_T_19, UInt<6>(0h20), _ll_fp_wdata_rawIn_normDist_T_69) node _ll_fp_wdata_rawIn_normDist_T_71 = mux(_ll_fp_wdata_rawIn_normDist_T_20, UInt<5>(0h1f), _ll_fp_wdata_rawIn_normDist_T_70) node _ll_fp_wdata_rawIn_normDist_T_72 = mux(_ll_fp_wdata_rawIn_normDist_T_21, UInt<5>(0h1e), _ll_fp_wdata_rawIn_normDist_T_71) node _ll_fp_wdata_rawIn_normDist_T_73 = mux(_ll_fp_wdata_rawIn_normDist_T_22, UInt<5>(0h1d), _ll_fp_wdata_rawIn_normDist_T_72) node _ll_fp_wdata_rawIn_normDist_T_74 = mux(_ll_fp_wdata_rawIn_normDist_T_23, UInt<5>(0h1c), _ll_fp_wdata_rawIn_normDist_T_73) node _ll_fp_wdata_rawIn_normDist_T_75 = mux(_ll_fp_wdata_rawIn_normDist_T_24, UInt<5>(0h1b), _ll_fp_wdata_rawIn_normDist_T_74) node _ll_fp_wdata_rawIn_normDist_T_76 = mux(_ll_fp_wdata_rawIn_normDist_T_25, UInt<5>(0h1a), _ll_fp_wdata_rawIn_normDist_T_75) node _ll_fp_wdata_rawIn_normDist_T_77 = mux(_ll_fp_wdata_rawIn_normDist_T_26, UInt<5>(0h19), _ll_fp_wdata_rawIn_normDist_T_76) node _ll_fp_wdata_rawIn_normDist_T_78 = mux(_ll_fp_wdata_rawIn_normDist_T_27, UInt<5>(0h18), _ll_fp_wdata_rawIn_normDist_T_77) node _ll_fp_wdata_rawIn_normDist_T_79 = mux(_ll_fp_wdata_rawIn_normDist_T_28, UInt<5>(0h17), _ll_fp_wdata_rawIn_normDist_T_78) node _ll_fp_wdata_rawIn_normDist_T_80 = mux(_ll_fp_wdata_rawIn_normDist_T_29, UInt<5>(0h16), _ll_fp_wdata_rawIn_normDist_T_79) node _ll_fp_wdata_rawIn_normDist_T_81 = mux(_ll_fp_wdata_rawIn_normDist_T_30, UInt<5>(0h15), _ll_fp_wdata_rawIn_normDist_T_80) node _ll_fp_wdata_rawIn_normDist_T_82 = mux(_ll_fp_wdata_rawIn_normDist_T_31, UInt<5>(0h14), _ll_fp_wdata_rawIn_normDist_T_81) node _ll_fp_wdata_rawIn_normDist_T_83 = mux(_ll_fp_wdata_rawIn_normDist_T_32, UInt<5>(0h13), _ll_fp_wdata_rawIn_normDist_T_82) node _ll_fp_wdata_rawIn_normDist_T_84 = mux(_ll_fp_wdata_rawIn_normDist_T_33, UInt<5>(0h12), _ll_fp_wdata_rawIn_normDist_T_83) node _ll_fp_wdata_rawIn_normDist_T_85 = mux(_ll_fp_wdata_rawIn_normDist_T_34, UInt<5>(0h11), _ll_fp_wdata_rawIn_normDist_T_84) node _ll_fp_wdata_rawIn_normDist_T_86 = mux(_ll_fp_wdata_rawIn_normDist_T_35, UInt<5>(0h10), _ll_fp_wdata_rawIn_normDist_T_85) node _ll_fp_wdata_rawIn_normDist_T_87 = mux(_ll_fp_wdata_rawIn_normDist_T_36, UInt<4>(0hf), _ll_fp_wdata_rawIn_normDist_T_86) node _ll_fp_wdata_rawIn_normDist_T_88 = mux(_ll_fp_wdata_rawIn_normDist_T_37, UInt<4>(0he), _ll_fp_wdata_rawIn_normDist_T_87) node _ll_fp_wdata_rawIn_normDist_T_89 = mux(_ll_fp_wdata_rawIn_normDist_T_38, UInt<4>(0hd), _ll_fp_wdata_rawIn_normDist_T_88) node _ll_fp_wdata_rawIn_normDist_T_90 = mux(_ll_fp_wdata_rawIn_normDist_T_39, UInt<4>(0hc), _ll_fp_wdata_rawIn_normDist_T_89) node _ll_fp_wdata_rawIn_normDist_T_91 = mux(_ll_fp_wdata_rawIn_normDist_T_40, UInt<4>(0hb), _ll_fp_wdata_rawIn_normDist_T_90) node _ll_fp_wdata_rawIn_normDist_T_92 = mux(_ll_fp_wdata_rawIn_normDist_T_41, UInt<4>(0ha), _ll_fp_wdata_rawIn_normDist_T_91) node _ll_fp_wdata_rawIn_normDist_T_93 = mux(_ll_fp_wdata_rawIn_normDist_T_42, UInt<4>(0h9), _ll_fp_wdata_rawIn_normDist_T_92) node _ll_fp_wdata_rawIn_normDist_T_94 = mux(_ll_fp_wdata_rawIn_normDist_T_43, UInt<4>(0h8), _ll_fp_wdata_rawIn_normDist_T_93) node _ll_fp_wdata_rawIn_normDist_T_95 = mux(_ll_fp_wdata_rawIn_normDist_T_44, UInt<3>(0h7), _ll_fp_wdata_rawIn_normDist_T_94) node _ll_fp_wdata_rawIn_normDist_T_96 = mux(_ll_fp_wdata_rawIn_normDist_T_45, UInt<3>(0h6), _ll_fp_wdata_rawIn_normDist_T_95) node _ll_fp_wdata_rawIn_normDist_T_97 = mux(_ll_fp_wdata_rawIn_normDist_T_46, UInt<3>(0h5), _ll_fp_wdata_rawIn_normDist_T_96) node _ll_fp_wdata_rawIn_normDist_T_98 = mux(_ll_fp_wdata_rawIn_normDist_T_47, UInt<3>(0h4), _ll_fp_wdata_rawIn_normDist_T_97) node _ll_fp_wdata_rawIn_normDist_T_99 = mux(_ll_fp_wdata_rawIn_normDist_T_48, UInt<2>(0h3), _ll_fp_wdata_rawIn_normDist_T_98) node _ll_fp_wdata_rawIn_normDist_T_100 = mux(_ll_fp_wdata_rawIn_normDist_T_49, UInt<2>(0h2), _ll_fp_wdata_rawIn_normDist_T_99) node _ll_fp_wdata_rawIn_normDist_T_101 = mux(_ll_fp_wdata_rawIn_normDist_T_50, UInt<1>(0h1), _ll_fp_wdata_rawIn_normDist_T_100) node ll_fp_wdata_rawIn_normDist = mux(_ll_fp_wdata_rawIn_normDist_T_51, UInt<1>(0h0), _ll_fp_wdata_rawIn_normDist_T_101) node _ll_fp_wdata_rawIn_subnormFract_T = dshl(ll_fp_wdata_rawIn_fractIn, ll_fp_wdata_rawIn_normDist) node _ll_fp_wdata_rawIn_subnormFract_T_1 = bits(_ll_fp_wdata_rawIn_subnormFract_T, 50, 0) node ll_fp_wdata_rawIn_subnormFract = shl(_ll_fp_wdata_rawIn_subnormFract_T_1, 1) node _ll_fp_wdata_rawIn_adjustedExp_T = xor(ll_fp_wdata_rawIn_normDist, UInt<12>(0hfff)) node _ll_fp_wdata_rawIn_adjustedExp_T_1 = mux(ll_fp_wdata_rawIn_isZeroExpIn, _ll_fp_wdata_rawIn_adjustedExp_T, ll_fp_wdata_rawIn_expIn) node _ll_fp_wdata_rawIn_adjustedExp_T_2 = mux(ll_fp_wdata_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _ll_fp_wdata_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _ll_fp_wdata_rawIn_adjustedExp_T_2) node _ll_fp_wdata_rawIn_adjustedExp_T_4 = add(_ll_fp_wdata_rawIn_adjustedExp_T_1, _ll_fp_wdata_rawIn_adjustedExp_T_3) node ll_fp_wdata_rawIn_adjustedExp = tail(_ll_fp_wdata_rawIn_adjustedExp_T_4, 1) node ll_fp_wdata_rawIn_isZero = and(ll_fp_wdata_rawIn_isZeroExpIn, ll_fp_wdata_rawIn_isZeroFractIn) node _ll_fp_wdata_rawIn_isSpecial_T = bits(ll_fp_wdata_rawIn_adjustedExp, 11, 10) node ll_fp_wdata_rawIn_isSpecial = eq(_ll_fp_wdata_rawIn_isSpecial_T, UInt<2>(0h3)) wire ll_fp_wdata_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _ll_fp_wdata_rawIn_out_isNaN_T = eq(ll_fp_wdata_rawIn_isZeroFractIn, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_isNaN_T_1 = and(ll_fp_wdata_rawIn_isSpecial, _ll_fp_wdata_rawIn_out_isNaN_T) connect ll_fp_wdata_rawIn.isNaN, _ll_fp_wdata_rawIn_out_isNaN_T_1 node _ll_fp_wdata_rawIn_out_isInf_T = and(ll_fp_wdata_rawIn_isSpecial, ll_fp_wdata_rawIn_isZeroFractIn) connect ll_fp_wdata_rawIn.isInf, _ll_fp_wdata_rawIn_out_isInf_T connect ll_fp_wdata_rawIn.isZero, ll_fp_wdata_rawIn_isZero connect ll_fp_wdata_rawIn.sign, ll_fp_wdata_rawIn_sign node _ll_fp_wdata_rawIn_out_sExp_T = bits(ll_fp_wdata_rawIn_adjustedExp, 11, 0) node _ll_fp_wdata_rawIn_out_sExp_T_1 = cvt(_ll_fp_wdata_rawIn_out_sExp_T) connect ll_fp_wdata_rawIn.sExp, _ll_fp_wdata_rawIn_out_sExp_T_1 node _ll_fp_wdata_rawIn_out_sig_T = eq(ll_fp_wdata_rawIn_isZero, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _ll_fp_wdata_rawIn_out_sig_T) node _ll_fp_wdata_rawIn_out_sig_T_2 = mux(ll_fp_wdata_rawIn_isZeroExpIn, ll_fp_wdata_rawIn_subnormFract, ll_fp_wdata_rawIn_fractIn) node _ll_fp_wdata_rawIn_out_sig_T_3 = cat(_ll_fp_wdata_rawIn_out_sig_T_1, _ll_fp_wdata_rawIn_out_sig_T_2) connect ll_fp_wdata_rawIn.sig, _ll_fp_wdata_rawIn_out_sig_T_3 node _ll_fp_wdata_T_7 = bits(ll_fp_wdata_rawIn.sExp, 11, 9) node _ll_fp_wdata_T_8 = mux(ll_fp_wdata_rawIn.isZero, UInt<3>(0h0), _ll_fp_wdata_T_7) node _ll_fp_wdata_T_9 = mux(ll_fp_wdata_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _ll_fp_wdata_T_10 = or(_ll_fp_wdata_T_8, _ll_fp_wdata_T_9) node _ll_fp_wdata_T_11 = cat(ll_fp_wdata_rawIn.sign, _ll_fp_wdata_T_10) node _ll_fp_wdata_T_12 = bits(ll_fp_wdata_rawIn.sExp, 8, 0) node _ll_fp_wdata_T_13 = cat(_ll_fp_wdata_T_11, _ll_fp_wdata_T_12) node _ll_fp_wdata_T_14 = bits(ll_fp_wdata_rawIn.sig, 51, 0) node _ll_fp_wdata_T_15 = cat(_ll_fp_wdata_T_13, _ll_fp_wdata_T_14) node ll_fp_wdata_rawIn_sign_1 = bits(_ll_fp_wdata_T_6, 31, 31) node ll_fp_wdata_rawIn_expIn_1 = bits(_ll_fp_wdata_T_6, 30, 23) node ll_fp_wdata_rawIn_fractIn_1 = bits(_ll_fp_wdata_T_6, 22, 0) node ll_fp_wdata_rawIn_isZeroExpIn_1 = eq(ll_fp_wdata_rawIn_expIn_1, UInt<1>(0h0)) node ll_fp_wdata_rawIn_isZeroFractIn_1 = eq(ll_fp_wdata_rawIn_fractIn_1, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_normDist_T_102 = bits(ll_fp_wdata_rawIn_fractIn_1, 0, 0) node _ll_fp_wdata_rawIn_normDist_T_103 = bits(ll_fp_wdata_rawIn_fractIn_1, 1, 1) node _ll_fp_wdata_rawIn_normDist_T_104 = bits(ll_fp_wdata_rawIn_fractIn_1, 2, 2) node _ll_fp_wdata_rawIn_normDist_T_105 = bits(ll_fp_wdata_rawIn_fractIn_1, 3, 3) node _ll_fp_wdata_rawIn_normDist_T_106 = bits(ll_fp_wdata_rawIn_fractIn_1, 4, 4) node _ll_fp_wdata_rawIn_normDist_T_107 = bits(ll_fp_wdata_rawIn_fractIn_1, 5, 5) node _ll_fp_wdata_rawIn_normDist_T_108 = bits(ll_fp_wdata_rawIn_fractIn_1, 6, 6) node _ll_fp_wdata_rawIn_normDist_T_109 = bits(ll_fp_wdata_rawIn_fractIn_1, 7, 7) node _ll_fp_wdata_rawIn_normDist_T_110 = bits(ll_fp_wdata_rawIn_fractIn_1, 8, 8) node _ll_fp_wdata_rawIn_normDist_T_111 = bits(ll_fp_wdata_rawIn_fractIn_1, 9, 9) node _ll_fp_wdata_rawIn_normDist_T_112 = bits(ll_fp_wdata_rawIn_fractIn_1, 10, 10) node _ll_fp_wdata_rawIn_normDist_T_113 = bits(ll_fp_wdata_rawIn_fractIn_1, 11, 11) node _ll_fp_wdata_rawIn_normDist_T_114 = bits(ll_fp_wdata_rawIn_fractIn_1, 12, 12) node _ll_fp_wdata_rawIn_normDist_T_115 = bits(ll_fp_wdata_rawIn_fractIn_1, 13, 13) node _ll_fp_wdata_rawIn_normDist_T_116 = bits(ll_fp_wdata_rawIn_fractIn_1, 14, 14) node _ll_fp_wdata_rawIn_normDist_T_117 = bits(ll_fp_wdata_rawIn_fractIn_1, 15, 15) node _ll_fp_wdata_rawIn_normDist_T_118 = bits(ll_fp_wdata_rawIn_fractIn_1, 16, 16) node _ll_fp_wdata_rawIn_normDist_T_119 = bits(ll_fp_wdata_rawIn_fractIn_1, 17, 17) node _ll_fp_wdata_rawIn_normDist_T_120 = bits(ll_fp_wdata_rawIn_fractIn_1, 18, 18) node _ll_fp_wdata_rawIn_normDist_T_121 = bits(ll_fp_wdata_rawIn_fractIn_1, 19, 19) node _ll_fp_wdata_rawIn_normDist_T_122 = bits(ll_fp_wdata_rawIn_fractIn_1, 20, 20) node _ll_fp_wdata_rawIn_normDist_T_123 = bits(ll_fp_wdata_rawIn_fractIn_1, 21, 21) node _ll_fp_wdata_rawIn_normDist_T_124 = bits(ll_fp_wdata_rawIn_fractIn_1, 22, 22) node _ll_fp_wdata_rawIn_normDist_T_125 = mux(_ll_fp_wdata_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) node _ll_fp_wdata_rawIn_normDist_T_126 = mux(_ll_fp_wdata_rawIn_normDist_T_104, UInt<5>(0h14), _ll_fp_wdata_rawIn_normDist_T_125) node _ll_fp_wdata_rawIn_normDist_T_127 = mux(_ll_fp_wdata_rawIn_normDist_T_105, UInt<5>(0h13), _ll_fp_wdata_rawIn_normDist_T_126) node _ll_fp_wdata_rawIn_normDist_T_128 = mux(_ll_fp_wdata_rawIn_normDist_T_106, UInt<5>(0h12), _ll_fp_wdata_rawIn_normDist_T_127) node _ll_fp_wdata_rawIn_normDist_T_129 = mux(_ll_fp_wdata_rawIn_normDist_T_107, UInt<5>(0h11), _ll_fp_wdata_rawIn_normDist_T_128) node _ll_fp_wdata_rawIn_normDist_T_130 = mux(_ll_fp_wdata_rawIn_normDist_T_108, UInt<5>(0h10), _ll_fp_wdata_rawIn_normDist_T_129) node _ll_fp_wdata_rawIn_normDist_T_131 = mux(_ll_fp_wdata_rawIn_normDist_T_109, UInt<4>(0hf), _ll_fp_wdata_rawIn_normDist_T_130) node _ll_fp_wdata_rawIn_normDist_T_132 = mux(_ll_fp_wdata_rawIn_normDist_T_110, UInt<4>(0he), _ll_fp_wdata_rawIn_normDist_T_131) node _ll_fp_wdata_rawIn_normDist_T_133 = mux(_ll_fp_wdata_rawIn_normDist_T_111, UInt<4>(0hd), _ll_fp_wdata_rawIn_normDist_T_132) node _ll_fp_wdata_rawIn_normDist_T_134 = mux(_ll_fp_wdata_rawIn_normDist_T_112, UInt<4>(0hc), _ll_fp_wdata_rawIn_normDist_T_133) node _ll_fp_wdata_rawIn_normDist_T_135 = mux(_ll_fp_wdata_rawIn_normDist_T_113, UInt<4>(0hb), _ll_fp_wdata_rawIn_normDist_T_134) node _ll_fp_wdata_rawIn_normDist_T_136 = mux(_ll_fp_wdata_rawIn_normDist_T_114, UInt<4>(0ha), _ll_fp_wdata_rawIn_normDist_T_135) node _ll_fp_wdata_rawIn_normDist_T_137 = mux(_ll_fp_wdata_rawIn_normDist_T_115, UInt<4>(0h9), _ll_fp_wdata_rawIn_normDist_T_136) node _ll_fp_wdata_rawIn_normDist_T_138 = mux(_ll_fp_wdata_rawIn_normDist_T_116, UInt<4>(0h8), _ll_fp_wdata_rawIn_normDist_T_137) node _ll_fp_wdata_rawIn_normDist_T_139 = mux(_ll_fp_wdata_rawIn_normDist_T_117, UInt<3>(0h7), _ll_fp_wdata_rawIn_normDist_T_138) node _ll_fp_wdata_rawIn_normDist_T_140 = mux(_ll_fp_wdata_rawIn_normDist_T_118, UInt<3>(0h6), _ll_fp_wdata_rawIn_normDist_T_139) node _ll_fp_wdata_rawIn_normDist_T_141 = mux(_ll_fp_wdata_rawIn_normDist_T_119, UInt<3>(0h5), _ll_fp_wdata_rawIn_normDist_T_140) node _ll_fp_wdata_rawIn_normDist_T_142 = mux(_ll_fp_wdata_rawIn_normDist_T_120, UInt<3>(0h4), _ll_fp_wdata_rawIn_normDist_T_141) node _ll_fp_wdata_rawIn_normDist_T_143 = mux(_ll_fp_wdata_rawIn_normDist_T_121, UInt<2>(0h3), _ll_fp_wdata_rawIn_normDist_T_142) node _ll_fp_wdata_rawIn_normDist_T_144 = mux(_ll_fp_wdata_rawIn_normDist_T_122, UInt<2>(0h2), _ll_fp_wdata_rawIn_normDist_T_143) node _ll_fp_wdata_rawIn_normDist_T_145 = mux(_ll_fp_wdata_rawIn_normDist_T_123, UInt<1>(0h1), _ll_fp_wdata_rawIn_normDist_T_144) node ll_fp_wdata_rawIn_normDist_1 = mux(_ll_fp_wdata_rawIn_normDist_T_124, UInt<1>(0h0), _ll_fp_wdata_rawIn_normDist_T_145) node _ll_fp_wdata_rawIn_subnormFract_T_2 = dshl(ll_fp_wdata_rawIn_fractIn_1, ll_fp_wdata_rawIn_normDist_1) node _ll_fp_wdata_rawIn_subnormFract_T_3 = bits(_ll_fp_wdata_rawIn_subnormFract_T_2, 21, 0) node ll_fp_wdata_rawIn_subnormFract_1 = shl(_ll_fp_wdata_rawIn_subnormFract_T_3, 1) node _ll_fp_wdata_rawIn_adjustedExp_T_5 = xor(ll_fp_wdata_rawIn_normDist_1, UInt<9>(0h1ff)) node _ll_fp_wdata_rawIn_adjustedExp_T_6 = mux(ll_fp_wdata_rawIn_isZeroExpIn_1, _ll_fp_wdata_rawIn_adjustedExp_T_5, ll_fp_wdata_rawIn_expIn_1) node _ll_fp_wdata_rawIn_adjustedExp_T_7 = mux(ll_fp_wdata_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _ll_fp_wdata_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _ll_fp_wdata_rawIn_adjustedExp_T_7) node _ll_fp_wdata_rawIn_adjustedExp_T_9 = add(_ll_fp_wdata_rawIn_adjustedExp_T_6, _ll_fp_wdata_rawIn_adjustedExp_T_8) node ll_fp_wdata_rawIn_adjustedExp_1 = tail(_ll_fp_wdata_rawIn_adjustedExp_T_9, 1) node ll_fp_wdata_rawIn_isZero_1 = and(ll_fp_wdata_rawIn_isZeroExpIn_1, ll_fp_wdata_rawIn_isZeroFractIn_1) node _ll_fp_wdata_rawIn_isSpecial_T_1 = bits(ll_fp_wdata_rawIn_adjustedExp_1, 8, 7) node ll_fp_wdata_rawIn_isSpecial_1 = eq(_ll_fp_wdata_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire ll_fp_wdata_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _ll_fp_wdata_rawIn_out_isNaN_T_2 = eq(ll_fp_wdata_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_isNaN_T_3 = and(ll_fp_wdata_rawIn_isSpecial_1, _ll_fp_wdata_rawIn_out_isNaN_T_2) connect ll_fp_wdata_rawIn_1.isNaN, _ll_fp_wdata_rawIn_out_isNaN_T_3 node _ll_fp_wdata_rawIn_out_isInf_T_1 = and(ll_fp_wdata_rawIn_isSpecial_1, ll_fp_wdata_rawIn_isZeroFractIn_1) connect ll_fp_wdata_rawIn_1.isInf, _ll_fp_wdata_rawIn_out_isInf_T_1 connect ll_fp_wdata_rawIn_1.isZero, ll_fp_wdata_rawIn_isZero_1 connect ll_fp_wdata_rawIn_1.sign, ll_fp_wdata_rawIn_sign_1 node _ll_fp_wdata_rawIn_out_sExp_T_2 = bits(ll_fp_wdata_rawIn_adjustedExp_1, 8, 0) node _ll_fp_wdata_rawIn_out_sExp_T_3 = cvt(_ll_fp_wdata_rawIn_out_sExp_T_2) connect ll_fp_wdata_rawIn_1.sExp, _ll_fp_wdata_rawIn_out_sExp_T_3 node _ll_fp_wdata_rawIn_out_sig_T_4 = eq(ll_fp_wdata_rawIn_isZero_1, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _ll_fp_wdata_rawIn_out_sig_T_4) node _ll_fp_wdata_rawIn_out_sig_T_6 = mux(ll_fp_wdata_rawIn_isZeroExpIn_1, ll_fp_wdata_rawIn_subnormFract_1, ll_fp_wdata_rawIn_fractIn_1) node _ll_fp_wdata_rawIn_out_sig_T_7 = cat(_ll_fp_wdata_rawIn_out_sig_T_5, _ll_fp_wdata_rawIn_out_sig_T_6) connect ll_fp_wdata_rawIn_1.sig, _ll_fp_wdata_rawIn_out_sig_T_7 node _ll_fp_wdata_T_16 = bits(ll_fp_wdata_rawIn_1.sExp, 8, 6) node _ll_fp_wdata_T_17 = mux(ll_fp_wdata_rawIn_1.isZero, UInt<3>(0h0), _ll_fp_wdata_T_16) node _ll_fp_wdata_T_18 = mux(ll_fp_wdata_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _ll_fp_wdata_T_19 = or(_ll_fp_wdata_T_17, _ll_fp_wdata_T_18) node _ll_fp_wdata_T_20 = cat(ll_fp_wdata_rawIn_1.sign, _ll_fp_wdata_T_19) node _ll_fp_wdata_T_21 = bits(ll_fp_wdata_rawIn_1.sExp, 5, 0) node _ll_fp_wdata_T_22 = cat(_ll_fp_wdata_T_20, _ll_fp_wdata_T_21) node _ll_fp_wdata_T_23 = bits(ll_fp_wdata_rawIn_1.sig, 22, 0) node _ll_fp_wdata_T_24 = cat(_ll_fp_wdata_T_22, _ll_fp_wdata_T_23) node ll_fp_wdata_rawIn_sign_2 = bits(_ll_fp_wdata_T_6, 15, 15) node ll_fp_wdata_rawIn_expIn_2 = bits(_ll_fp_wdata_T_6, 14, 10) node ll_fp_wdata_rawIn_fractIn_2 = bits(_ll_fp_wdata_T_6, 9, 0) node ll_fp_wdata_rawIn_isZeroExpIn_2 = eq(ll_fp_wdata_rawIn_expIn_2, UInt<1>(0h0)) node ll_fp_wdata_rawIn_isZeroFractIn_2 = eq(ll_fp_wdata_rawIn_fractIn_2, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_normDist_T_146 = bits(ll_fp_wdata_rawIn_fractIn_2, 0, 0) node _ll_fp_wdata_rawIn_normDist_T_147 = bits(ll_fp_wdata_rawIn_fractIn_2, 1, 1) node _ll_fp_wdata_rawIn_normDist_T_148 = bits(ll_fp_wdata_rawIn_fractIn_2, 2, 2) node _ll_fp_wdata_rawIn_normDist_T_149 = bits(ll_fp_wdata_rawIn_fractIn_2, 3, 3) node _ll_fp_wdata_rawIn_normDist_T_150 = bits(ll_fp_wdata_rawIn_fractIn_2, 4, 4) node _ll_fp_wdata_rawIn_normDist_T_151 = bits(ll_fp_wdata_rawIn_fractIn_2, 5, 5) node _ll_fp_wdata_rawIn_normDist_T_152 = bits(ll_fp_wdata_rawIn_fractIn_2, 6, 6) node _ll_fp_wdata_rawIn_normDist_T_153 = bits(ll_fp_wdata_rawIn_fractIn_2, 7, 7) node _ll_fp_wdata_rawIn_normDist_T_154 = bits(ll_fp_wdata_rawIn_fractIn_2, 8, 8) node _ll_fp_wdata_rawIn_normDist_T_155 = bits(ll_fp_wdata_rawIn_fractIn_2, 9, 9) node _ll_fp_wdata_rawIn_normDist_T_156 = mux(_ll_fp_wdata_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9)) node _ll_fp_wdata_rawIn_normDist_T_157 = mux(_ll_fp_wdata_rawIn_normDist_T_148, UInt<3>(0h7), _ll_fp_wdata_rawIn_normDist_T_156) node _ll_fp_wdata_rawIn_normDist_T_158 = mux(_ll_fp_wdata_rawIn_normDist_T_149, UInt<3>(0h6), _ll_fp_wdata_rawIn_normDist_T_157) node _ll_fp_wdata_rawIn_normDist_T_159 = mux(_ll_fp_wdata_rawIn_normDist_T_150, UInt<3>(0h5), _ll_fp_wdata_rawIn_normDist_T_158) node _ll_fp_wdata_rawIn_normDist_T_160 = mux(_ll_fp_wdata_rawIn_normDist_T_151, UInt<3>(0h4), _ll_fp_wdata_rawIn_normDist_T_159) node _ll_fp_wdata_rawIn_normDist_T_161 = mux(_ll_fp_wdata_rawIn_normDist_T_152, UInt<2>(0h3), _ll_fp_wdata_rawIn_normDist_T_160) node _ll_fp_wdata_rawIn_normDist_T_162 = mux(_ll_fp_wdata_rawIn_normDist_T_153, UInt<2>(0h2), _ll_fp_wdata_rawIn_normDist_T_161) node _ll_fp_wdata_rawIn_normDist_T_163 = mux(_ll_fp_wdata_rawIn_normDist_T_154, UInt<1>(0h1), _ll_fp_wdata_rawIn_normDist_T_162) node ll_fp_wdata_rawIn_normDist_2 = mux(_ll_fp_wdata_rawIn_normDist_T_155, UInt<1>(0h0), _ll_fp_wdata_rawIn_normDist_T_163) node _ll_fp_wdata_rawIn_subnormFract_T_4 = dshl(ll_fp_wdata_rawIn_fractIn_2, ll_fp_wdata_rawIn_normDist_2) node _ll_fp_wdata_rawIn_subnormFract_T_5 = bits(_ll_fp_wdata_rawIn_subnormFract_T_4, 8, 0) node ll_fp_wdata_rawIn_subnormFract_2 = shl(_ll_fp_wdata_rawIn_subnormFract_T_5, 1) node _ll_fp_wdata_rawIn_adjustedExp_T_10 = xor(ll_fp_wdata_rawIn_normDist_2, UInt<6>(0h3f)) node _ll_fp_wdata_rawIn_adjustedExp_T_11 = mux(ll_fp_wdata_rawIn_isZeroExpIn_2, _ll_fp_wdata_rawIn_adjustedExp_T_10, ll_fp_wdata_rawIn_expIn_2) node _ll_fp_wdata_rawIn_adjustedExp_T_12 = mux(ll_fp_wdata_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _ll_fp_wdata_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _ll_fp_wdata_rawIn_adjustedExp_T_12) node _ll_fp_wdata_rawIn_adjustedExp_T_14 = add(_ll_fp_wdata_rawIn_adjustedExp_T_11, _ll_fp_wdata_rawIn_adjustedExp_T_13) node ll_fp_wdata_rawIn_adjustedExp_2 = tail(_ll_fp_wdata_rawIn_adjustedExp_T_14, 1) node ll_fp_wdata_rawIn_isZero_2 = and(ll_fp_wdata_rawIn_isZeroExpIn_2, ll_fp_wdata_rawIn_isZeroFractIn_2) node _ll_fp_wdata_rawIn_isSpecial_T_2 = bits(ll_fp_wdata_rawIn_adjustedExp_2, 5, 4) node ll_fp_wdata_rawIn_isSpecial_2 = eq(_ll_fp_wdata_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire ll_fp_wdata_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _ll_fp_wdata_rawIn_out_isNaN_T_4 = eq(ll_fp_wdata_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_isNaN_T_5 = and(ll_fp_wdata_rawIn_isSpecial_2, _ll_fp_wdata_rawIn_out_isNaN_T_4) connect ll_fp_wdata_rawIn_2.isNaN, _ll_fp_wdata_rawIn_out_isNaN_T_5 node _ll_fp_wdata_rawIn_out_isInf_T_2 = and(ll_fp_wdata_rawIn_isSpecial_2, ll_fp_wdata_rawIn_isZeroFractIn_2) connect ll_fp_wdata_rawIn_2.isInf, _ll_fp_wdata_rawIn_out_isInf_T_2 connect ll_fp_wdata_rawIn_2.isZero, ll_fp_wdata_rawIn_isZero_2 connect ll_fp_wdata_rawIn_2.sign, ll_fp_wdata_rawIn_sign_2 node _ll_fp_wdata_rawIn_out_sExp_T_4 = bits(ll_fp_wdata_rawIn_adjustedExp_2, 5, 0) node _ll_fp_wdata_rawIn_out_sExp_T_5 = cvt(_ll_fp_wdata_rawIn_out_sExp_T_4) connect ll_fp_wdata_rawIn_2.sExp, _ll_fp_wdata_rawIn_out_sExp_T_5 node _ll_fp_wdata_rawIn_out_sig_T_8 = eq(ll_fp_wdata_rawIn_isZero_2, UInt<1>(0h0)) node _ll_fp_wdata_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _ll_fp_wdata_rawIn_out_sig_T_8) node _ll_fp_wdata_rawIn_out_sig_T_10 = mux(ll_fp_wdata_rawIn_isZeroExpIn_2, ll_fp_wdata_rawIn_subnormFract_2, ll_fp_wdata_rawIn_fractIn_2) node _ll_fp_wdata_rawIn_out_sig_T_11 = cat(_ll_fp_wdata_rawIn_out_sig_T_9, _ll_fp_wdata_rawIn_out_sig_T_10) connect ll_fp_wdata_rawIn_2.sig, _ll_fp_wdata_rawIn_out_sig_T_11 node _ll_fp_wdata_T_25 = bits(ll_fp_wdata_rawIn_2.sExp, 5, 3) node _ll_fp_wdata_T_26 = mux(ll_fp_wdata_rawIn_2.isZero, UInt<3>(0h0), _ll_fp_wdata_T_25) node _ll_fp_wdata_T_27 = mux(ll_fp_wdata_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _ll_fp_wdata_T_28 = or(_ll_fp_wdata_T_26, _ll_fp_wdata_T_27) node _ll_fp_wdata_T_29 = cat(ll_fp_wdata_rawIn_2.sign, _ll_fp_wdata_T_28) node _ll_fp_wdata_T_30 = bits(ll_fp_wdata_rawIn_2.sExp, 2, 0) node _ll_fp_wdata_T_31 = cat(_ll_fp_wdata_T_29, _ll_fp_wdata_T_30) node _ll_fp_wdata_T_32 = bits(ll_fp_wdata_rawIn_2.sig, 9, 0) node _ll_fp_wdata_T_33 = cat(_ll_fp_wdata_T_31, _ll_fp_wdata_T_32) node _ll_fp_wdata_swizzledNaN_T = bits(_ll_fp_wdata_T_24, 32, 29) node _ll_fp_wdata_swizzledNaN_T_1 = bits(_ll_fp_wdata_T_24, 22, 16) node _ll_fp_wdata_swizzledNaN_T_2 = andr(_ll_fp_wdata_swizzledNaN_T_1) node _ll_fp_wdata_swizzledNaN_T_3 = bits(_ll_fp_wdata_T_24, 27, 24) node _ll_fp_wdata_swizzledNaN_T_4 = bits(_ll_fp_wdata_T_33, 15, 15) node _ll_fp_wdata_swizzledNaN_T_5 = bits(_ll_fp_wdata_T_24, 22, 16) node _ll_fp_wdata_swizzledNaN_T_6 = bits(_ll_fp_wdata_T_33, 16, 16) node _ll_fp_wdata_swizzledNaN_T_7 = bits(_ll_fp_wdata_T_33, 14, 0) node ll_fp_wdata_swizzledNaN_lo_hi = cat(_ll_fp_wdata_swizzledNaN_T_5, _ll_fp_wdata_swizzledNaN_T_6) node ll_fp_wdata_swizzledNaN_lo = cat(ll_fp_wdata_swizzledNaN_lo_hi, _ll_fp_wdata_swizzledNaN_T_7) node ll_fp_wdata_swizzledNaN_hi_lo = cat(_ll_fp_wdata_swizzledNaN_T_3, _ll_fp_wdata_swizzledNaN_T_4) node ll_fp_wdata_swizzledNaN_hi_hi = cat(_ll_fp_wdata_swizzledNaN_T, _ll_fp_wdata_swizzledNaN_T_2) node ll_fp_wdata_swizzledNaN_hi = cat(ll_fp_wdata_swizzledNaN_hi_hi, ll_fp_wdata_swizzledNaN_hi_lo) node ll_fp_wdata_swizzledNaN = cat(ll_fp_wdata_swizzledNaN_hi, ll_fp_wdata_swizzledNaN_lo) node _ll_fp_wdata_T_34 = bits(_ll_fp_wdata_T_24, 31, 29) node _ll_fp_wdata_T_35 = andr(_ll_fp_wdata_T_34) node _ll_fp_wdata_T_36 = mux(_ll_fp_wdata_T_35, ll_fp_wdata_swizzledNaN, _ll_fp_wdata_T_24) node _ll_fp_wdata_swizzledNaN_T_8 = bits(_ll_fp_wdata_T_15, 64, 61) node _ll_fp_wdata_swizzledNaN_T_9 = bits(_ll_fp_wdata_T_15, 51, 32) node _ll_fp_wdata_swizzledNaN_T_10 = andr(_ll_fp_wdata_swizzledNaN_T_9) node _ll_fp_wdata_swizzledNaN_T_11 = bits(_ll_fp_wdata_T_15, 59, 53) node _ll_fp_wdata_swizzledNaN_T_12 = bits(_ll_fp_wdata_T_36, 31, 31) node _ll_fp_wdata_swizzledNaN_T_13 = bits(_ll_fp_wdata_T_15, 51, 32) node _ll_fp_wdata_swizzledNaN_T_14 = bits(_ll_fp_wdata_T_36, 32, 32) node _ll_fp_wdata_swizzledNaN_T_15 = bits(_ll_fp_wdata_T_36, 30, 0) node ll_fp_wdata_swizzledNaN_lo_hi_1 = cat(_ll_fp_wdata_swizzledNaN_T_13, _ll_fp_wdata_swizzledNaN_T_14) node ll_fp_wdata_swizzledNaN_lo_1 = cat(ll_fp_wdata_swizzledNaN_lo_hi_1, _ll_fp_wdata_swizzledNaN_T_15) node ll_fp_wdata_swizzledNaN_hi_lo_1 = cat(_ll_fp_wdata_swizzledNaN_T_11, _ll_fp_wdata_swizzledNaN_T_12) node ll_fp_wdata_swizzledNaN_hi_hi_1 = cat(_ll_fp_wdata_swizzledNaN_T_8, _ll_fp_wdata_swizzledNaN_T_10) node ll_fp_wdata_swizzledNaN_hi_1 = cat(ll_fp_wdata_swizzledNaN_hi_hi_1, ll_fp_wdata_swizzledNaN_hi_lo_1) node ll_fp_wdata_swizzledNaN_1 = cat(ll_fp_wdata_swizzledNaN_hi_1, ll_fp_wdata_swizzledNaN_lo_1) node _ll_fp_wdata_T_37 = bits(_ll_fp_wdata_T_15, 63, 61) node _ll_fp_wdata_T_38 = andr(_ll_fp_wdata_T_37) node _ll_fp_wdata_T_39 = mux(_ll_fp_wdata_T_38, ll_fp_wdata_swizzledNaN_1, _ll_fp_wdata_T_15) connect ll_fp_wdata, _ll_fp_wdata_T_39 connect ll_fp_waddr, fp_load_addr else : node _T_341 = and(divSqrt_val, divSqrt_wdata.valid) when _T_341 : connect ll_fp_wval, UInt<1>(0h1) connect ll_fp_wdata, divSqrt_wdata.bits connect ll_fp_waddr, divSqrt_waddr connect divSqrt_val, UInt<1>(0h0) connect csr.io.fcsr_flags.valid, UInt<1>(0h1) connect csr_fcsr_flags[1], divSqrt_flags when ll_fp_wval : node _T_342 = or(ll_fp_waddr, UInt<5>(0h0)) node _T_343 = bits(_T_342, 4, 0) connect fregfile[_T_343], ll_fp_wdata connect csr.io.set_fs_dirty, UInt<1>(0h1) node _T_344 = or(ll_fp_waddr, UInt<5>(0h0)) node _T_345 = bits(_T_344, 4, 0) connect fsboard_set[_T_345], UInt<1>(0h1) node _T_346 = or(ll_fp_waddr, UInt<5>(0h0)) node _T_347 = bits(_T_346, 4, 0) node _T_348 = eq(fsboard[_T_347], UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:1306 assert(!fsboard(ll_fp_waddr))\n") : printf_5 assert(clock, _T_348, UInt<1>(0h1), "") : assert_5 node _fp_wdata_opts_bigger_swizzledNaN_T = andr(UInt<7>(0h7f)) node _fp_wdata_opts_bigger_swizzledNaN_T_1 = bits(fp_pipe.io.out.bits.data, 15, 15) node _fp_wdata_opts_bigger_swizzledNaN_T_2 = bits(fp_pipe.io.out.bits.data, 16, 16) node _fp_wdata_opts_bigger_swizzledNaN_T_3 = bits(fp_pipe.io.out.bits.data, 14, 0) node fp_wdata_opts_bigger_swizzledNaN_lo_hi = cat(UInt<7>(0h7f), _fp_wdata_opts_bigger_swizzledNaN_T_2) node fp_wdata_opts_bigger_swizzledNaN_lo = cat(fp_wdata_opts_bigger_swizzledNaN_lo_hi, _fp_wdata_opts_bigger_swizzledNaN_T_3) node fp_wdata_opts_bigger_swizzledNaN_hi_lo = cat(UInt<4>(0hf), _fp_wdata_opts_bigger_swizzledNaN_T_1) node fp_wdata_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _fp_wdata_opts_bigger_swizzledNaN_T) node fp_wdata_opts_bigger_swizzledNaN_hi = cat(fp_wdata_opts_bigger_swizzledNaN_hi_hi, fp_wdata_opts_bigger_swizzledNaN_hi_lo) node fp_wdata_opts_bigger_swizzledNaN = cat(fp_wdata_opts_bigger_swizzledNaN_hi, fp_wdata_opts_bigger_swizzledNaN_lo) node _fp_wdata_opts_bigger_T = andr(UInt<3>(0h7)) node fp_wdata_opts_bigger = mux(_fp_wdata_opts_bigger_T, fp_wdata_opts_bigger_swizzledNaN, UInt<33>(0h1ffffffff)) node fp_wdata_opts_0 = or(fp_wdata_opts_bigger, UInt<65>(0h1fffffffe00000000)) node _fp_wdata_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _fp_wdata_opts_bigger_swizzledNaN_T_5 = bits(fp_pipe.io.out.bits.data, 31, 31) node _fp_wdata_opts_bigger_swizzledNaN_T_6 = bits(fp_pipe.io.out.bits.data, 32, 32) node _fp_wdata_opts_bigger_swizzledNaN_T_7 = bits(fp_pipe.io.out.bits.data, 30, 0) node fp_wdata_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _fp_wdata_opts_bigger_swizzledNaN_T_6) node fp_wdata_opts_bigger_swizzledNaN_lo_1 = cat(fp_wdata_opts_bigger_swizzledNaN_lo_hi_1, _fp_wdata_opts_bigger_swizzledNaN_T_7) node fp_wdata_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _fp_wdata_opts_bigger_swizzledNaN_T_5) node fp_wdata_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _fp_wdata_opts_bigger_swizzledNaN_T_4) node fp_wdata_opts_bigger_swizzledNaN_hi_1 = cat(fp_wdata_opts_bigger_swizzledNaN_hi_hi_1, fp_wdata_opts_bigger_swizzledNaN_hi_lo_1) node fp_wdata_opts_bigger_swizzledNaN_1 = cat(fp_wdata_opts_bigger_swizzledNaN_hi_1, fp_wdata_opts_bigger_swizzledNaN_lo_1) node _fp_wdata_opts_bigger_T_1 = andr(UInt<3>(0h7)) node fp_wdata_opts_bigger_1 = mux(_fp_wdata_opts_bigger_T_1, fp_wdata_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node fp_wdata_opts_1 = or(fp_wdata_opts_bigger_1, UInt<1>(0h0)) node _fp_wdata_T = eq(fp_pipe.io.out_tag, UInt<1>(0h1)) node _fp_wdata_T_1 = mux(_fp_wdata_T, fp_wdata_opts_1, fp_wdata_opts_0) node _fp_wdata_T_2 = eq(fp_pipe.io.out_tag, UInt<2>(0h2)) node _fp_wdata_T_3 = mux(_fp_wdata_T_2, fp_pipe.io.out.bits.data, _fp_wdata_T_1) node _fp_wdata_T_4 = eq(fp_pipe.io.out_tag, UInt<2>(0h3)) node fp_wdata = mux(_fp_wdata_T_4, fp_pipe.io.out.bits.data, _fp_wdata_T_3) node fp_ieee_wdata_unrecoded_rawIn_exp = bits(fp_wdata, 63, 52) node _fp_ieee_wdata_unrecoded_rawIn_isZero_T = bits(fp_ieee_wdata_unrecoded_rawIn_exp, 11, 9) node fp_ieee_wdata_unrecoded_rawIn_isZero = eq(_fp_ieee_wdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _fp_ieee_wdata_unrecoded_rawIn_isSpecial_T = bits(fp_ieee_wdata_unrecoded_rawIn_exp, 11, 10) node fp_ieee_wdata_unrecoded_rawIn_isSpecial = eq(_fp_ieee_wdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire fp_ieee_wdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T = bits(fp_ieee_wdata_unrecoded_rawIn_exp, 9, 9) node _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T_1 = and(fp_ieee_wdata_unrecoded_rawIn_isSpecial, _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T) connect fp_ieee_wdata_unrecoded_rawIn.isNaN, _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T_1 node _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T = bits(fp_ieee_wdata_unrecoded_rawIn_exp, 9, 9) node _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_1 = eq(_fp_ieee_wdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_2 = and(fp_ieee_wdata_unrecoded_rawIn_isSpecial, _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_1) connect fp_ieee_wdata_unrecoded_rawIn.isInf, _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_2 connect fp_ieee_wdata_unrecoded_rawIn.isZero, fp_ieee_wdata_unrecoded_rawIn_isZero node _fp_ieee_wdata_unrecoded_rawIn_out_sign_T = bits(fp_wdata, 64, 64) connect fp_ieee_wdata_unrecoded_rawIn.sign, _fp_ieee_wdata_unrecoded_rawIn_out_sign_T node _fp_ieee_wdata_unrecoded_rawIn_out_sExp_T = cvt(fp_ieee_wdata_unrecoded_rawIn_exp) connect fp_ieee_wdata_unrecoded_rawIn.sExp, _fp_ieee_wdata_unrecoded_rawIn_out_sExp_T node _fp_ieee_wdata_unrecoded_rawIn_out_sig_T = eq(fp_ieee_wdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _fp_ieee_wdata_unrecoded_rawIn_out_sig_T) node _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_2 = bits(fp_wdata, 51, 0) node _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_3 = cat(_fp_ieee_wdata_unrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_2) connect fp_ieee_wdata_unrecoded_rawIn.sig, _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_3 node fp_ieee_wdata_unrecoded_isSubnormal = lt(fp_ieee_wdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _fp_ieee_wdata_unrecoded_denormShiftDist_T = bits(fp_ieee_wdata_unrecoded_rawIn.sExp, 5, 0) node _fp_ieee_wdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _fp_ieee_wdata_unrecoded_denormShiftDist_T) node fp_ieee_wdata_unrecoded_denormShiftDist = tail(_fp_ieee_wdata_unrecoded_denormShiftDist_T_1, 1) node _fp_ieee_wdata_unrecoded_denormFract_T = shr(fp_ieee_wdata_unrecoded_rawIn.sig, 1) node _fp_ieee_wdata_unrecoded_denormFract_T_1 = dshr(_fp_ieee_wdata_unrecoded_denormFract_T, fp_ieee_wdata_unrecoded_denormShiftDist) node fp_ieee_wdata_unrecoded_denormFract = bits(_fp_ieee_wdata_unrecoded_denormFract_T_1, 51, 0) node _fp_ieee_wdata_unrecoded_expOut_T = bits(fp_ieee_wdata_unrecoded_rawIn.sExp, 10, 0) node _fp_ieee_wdata_unrecoded_expOut_T_1 = sub(_fp_ieee_wdata_unrecoded_expOut_T, UInt<11>(0h401)) node _fp_ieee_wdata_unrecoded_expOut_T_2 = tail(_fp_ieee_wdata_unrecoded_expOut_T_1, 1) node _fp_ieee_wdata_unrecoded_expOut_T_3 = mux(fp_ieee_wdata_unrecoded_isSubnormal, UInt<1>(0h0), _fp_ieee_wdata_unrecoded_expOut_T_2) node _fp_ieee_wdata_unrecoded_expOut_T_4 = or(fp_ieee_wdata_unrecoded_rawIn.isNaN, fp_ieee_wdata_unrecoded_rawIn.isInf) node _fp_ieee_wdata_unrecoded_expOut_T_5 = mux(_fp_ieee_wdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node fp_ieee_wdata_unrecoded_expOut = or(_fp_ieee_wdata_unrecoded_expOut_T_3, _fp_ieee_wdata_unrecoded_expOut_T_5) node _fp_ieee_wdata_unrecoded_fractOut_T = bits(fp_ieee_wdata_unrecoded_rawIn.sig, 51, 0) node _fp_ieee_wdata_unrecoded_fractOut_T_1 = mux(fp_ieee_wdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _fp_ieee_wdata_unrecoded_fractOut_T) node fp_ieee_wdata_unrecoded_fractOut = mux(fp_ieee_wdata_unrecoded_isSubnormal, fp_ieee_wdata_unrecoded_denormFract, _fp_ieee_wdata_unrecoded_fractOut_T_1) node fp_ieee_wdata_unrecoded_hi = cat(fp_ieee_wdata_unrecoded_rawIn.sign, fp_ieee_wdata_unrecoded_expOut) node fp_ieee_wdata_unrecoded = cat(fp_ieee_wdata_unrecoded_hi, fp_ieee_wdata_unrecoded_fractOut) node _fp_ieee_wdata_prevRecoded_T = bits(fp_wdata, 31, 31) node _fp_ieee_wdata_prevRecoded_T_1 = bits(fp_wdata, 52, 52) node _fp_ieee_wdata_prevRecoded_T_2 = bits(fp_wdata, 30, 0) node fp_ieee_wdata_prevRecoded_hi = cat(_fp_ieee_wdata_prevRecoded_T, _fp_ieee_wdata_prevRecoded_T_1) node fp_ieee_wdata_prevRecoded = cat(fp_ieee_wdata_prevRecoded_hi, _fp_ieee_wdata_prevRecoded_T_2) node fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp = bits(fp_ieee_wdata_prevRecoded, 31, 23) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero = eq(_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isNaN, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isInf, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isZero, fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(fp_ieee_wdata_prevRecoded, 32, 32) connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sign, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sign_T node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp) connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sExp, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(fp_ieee_wdata_prevRecoded, 22, 0) node _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sig, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal = lt(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T) node fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist = tail(_fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T = shr(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sig, 1) node _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T, fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist) node fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract = bits(_fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_1 = sub(_fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_2 = tail(_fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_1, 1) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_3 = mux(fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_2) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_4 = or(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isNaN, fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isInf) node _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_5 = mux(_fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node fp_ieee_wdata_prevUnrecoded_unrecoded_expOut = or(_fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_3, _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_5) node _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T = bits(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T_1 = mux(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T) node fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut = mux(fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal, fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract, _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T_1) node fp_ieee_wdata_prevUnrecoded_unrecoded_hi = cat(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn.sign, fp_ieee_wdata_prevUnrecoded_unrecoded_expOut) node fp_ieee_wdata_prevUnrecoded_unrecoded = cat(fp_ieee_wdata_prevUnrecoded_unrecoded_hi, fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut) node _fp_ieee_wdata_prevUnrecoded_prevRecoded_T = bits(fp_ieee_wdata_prevRecoded, 15, 15) node _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_1 = bits(fp_ieee_wdata_prevRecoded, 23, 23) node _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_2 = bits(fp_ieee_wdata_prevRecoded, 14, 0) node fp_ieee_wdata_prevUnrecoded_prevRecoded_hi = cat(_fp_ieee_wdata_prevUnrecoded_prevRecoded_T, _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_1) node fp_ieee_wdata_prevUnrecoded_prevRecoded = cat(fp_ieee_wdata_prevUnrecoded_prevRecoded_hi, _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_2) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(fp_ieee_wdata_prevUnrecoded_prevRecoded, 15, 10) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isZero, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(fp_ieee_wdata_prevUnrecoded_prevRecoded, 16, 16) connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sign, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp) connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(fp_ieee_wdata_prevUnrecoded_prevRecoded, 9, 0) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sig, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal = lt(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T = shr(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract = bits(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_2) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut = or(_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_3, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_5) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T = bits(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut = mux(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T_1) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded_hi = cat(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn.sign, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut) node fp_ieee_wdata_prevUnrecoded_prevUnrecoded = cat(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_hi, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut) node _fp_ieee_wdata_prevUnrecoded_T = shr(fp_ieee_wdata_prevUnrecoded_unrecoded, 16) node _fp_ieee_wdata_prevUnrecoded_T_1 = bits(fp_ieee_wdata_prevRecoded, 31, 29) node _fp_ieee_wdata_prevUnrecoded_T_2 = andr(_fp_ieee_wdata_prevUnrecoded_T_1) node _fp_ieee_wdata_prevUnrecoded_T_3 = bits(fp_ieee_wdata_prevUnrecoded_unrecoded, 15, 0) node _fp_ieee_wdata_prevUnrecoded_T_4 = mux(_fp_ieee_wdata_prevUnrecoded_T_2, fp_ieee_wdata_prevUnrecoded_prevUnrecoded, _fp_ieee_wdata_prevUnrecoded_T_3) node fp_ieee_wdata_prevUnrecoded = cat(_fp_ieee_wdata_prevUnrecoded_T, _fp_ieee_wdata_prevUnrecoded_T_4) node _fp_ieee_wdata_T = shr(fp_ieee_wdata_unrecoded, 32) node _fp_ieee_wdata_T_1 = bits(fp_wdata, 63, 61) node _fp_ieee_wdata_T_2 = andr(_fp_ieee_wdata_T_1) node _fp_ieee_wdata_T_3 = bits(fp_ieee_wdata_unrecoded, 31, 0) node _fp_ieee_wdata_T_4 = mux(_fp_ieee_wdata_T_2, fp_ieee_wdata_prevUnrecoded, _fp_ieee_wdata_T_3) node fp_ieee_wdata = cat(_fp_ieee_wdata_T, _fp_ieee_wdata_T_4) when fp_pipe.io.out.valid : connect fregfile[fp_pipe.io.out_rd], fp_wdata connect fsboard_set[fp_pipe.io.out_rd], UInt<1>(0h1) connect csr.io.fcsr_flags.valid, UInt<1>(0h1) connect csr.io.set_fs_dirty, UInt<1>(0h1) connect csr_fcsr_flags[2], fp_pipe.io.out.bits.exc node _T_352 = eq(fsboard[fp_pipe.io.out_rd], UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Core.scala:1320 assert(!fsboard(waddr))\n") : printf_6 assert(clock, _T_352, UInt<1>(0h1), "") : assert_6 node _T_356 = asUInt(reset) when _T_356 : connect ex_uops_reg[0].valid, UInt<1>(0h0) connect mem_uops_reg[0].valid, UInt<1>(0h0) connect com_uops_reg[0].valid, UInt<1>(0h0) connect ex_uops_reg[1].valid, UInt<1>(0h0) connect mem_uops_reg[1].valid, UInt<1>(0h0) connect com_uops_reg[1].valid, UInt<1>(0h0)
module ShuttleCore( // @[Core.scala:25:7] input clock, // @[Core.scala:25:7] input reset, // @[Core.scala:25:7] input io_hartid, // @[Core.scala:31:14] input io_interrupts_debug, // @[Core.scala:31:14] input io_interrupts_mtip, // @[Core.scala:31:14] input io_interrupts_msip, // @[Core.scala:31:14] input io_interrupts_meip, // @[Core.scala:31:14] input io_interrupts_seip, // @[Core.scala:31:14] output io_imem_redirect_flush, // @[Core.scala:31:14] output io_imem_redirect_val, // @[Core.scala:31:14] output [39:0] io_imem_redirect_pc, // @[Core.scala:31:14] output [2:0] io_imem_redirect_ras_head, // @[Core.scala:31:14] output io_imem_sfence_valid, // @[Core.scala:31:14] output io_imem_sfence_bits_rs1, // @[Core.scala:31:14] output io_imem_sfence_bits_rs2, // @[Core.scala:31:14] output [38:0] io_imem_sfence_bits_addr, // @[Core.scala:31:14] output io_imem_sfence_bits_asid, // @[Core.scala:31:14] output io_imem_sfence_bits_hv, // @[Core.scala:31:14] output io_imem_sfence_bits_hg, // @[Core.scala:31:14] output io_imem_flush_icache, // @[Core.scala:31:14] output io_imem_resp_0_ready, // @[Core.scala:31:14] input io_imem_resp_0_valid, // @[Core.scala:31:14] input [31:0] io_imem_resp_0_bits_inst, // @[Core.scala:31:14] input [31:0] io_imem_resp_0_bits_raw_inst, // @[Core.scala:31:14] input [39:0] io_imem_resp_0_bits_pc, // @[Core.scala:31:14] input io_imem_resp_0_bits_edge_inst, // @[Core.scala:31:14] input io_imem_resp_0_bits_rvc, // @[Core.scala:31:14] input io_imem_resp_0_bits_btb_resp_valid, // @[Core.scala:31:14] input [1:0] io_imem_resp_0_bits_btb_resp_bits_cfiType, // @[Core.scala:31:14] input io_imem_resp_0_bits_btb_resp_bits_taken, // @[Core.scala:31:14] input [3:0] io_imem_resp_0_bits_btb_resp_bits_mask, // @[Core.scala:31:14] input [1:0] io_imem_resp_0_bits_btb_resp_bits_bridx, // @[Core.scala:31:14] input [38:0] io_imem_resp_0_bits_btb_resp_bits_target, // @[Core.scala:31:14] input [5:0] io_imem_resp_0_bits_btb_resp_bits_entry, // @[Core.scala:31:14] input [7:0] io_imem_resp_0_bits_btb_resp_bits_bht_history, // @[Core.scala:31:14] input [1:0] io_imem_resp_0_bits_btb_resp_bits_bht_value, // @[Core.scala:31:14] input io_imem_resp_0_bits_sfb_br, // @[Core.scala:31:14] input io_imem_resp_0_bits_next_pc_valid, // @[Core.scala:31:14] input [39:0] io_imem_resp_0_bits_next_pc_bits, // @[Core.scala:31:14] input [2:0] io_imem_resp_0_bits_ras_head, // @[Core.scala:31:14] input io_imem_resp_0_bits_xcpt, // @[Core.scala:31:14] input [63:0] io_imem_resp_0_bits_xcpt_cause, // @[Core.scala:31:14] input [1:0] io_imem_resp_0_bits_mem_size, // @[Core.scala:31:14] output io_imem_resp_1_ready, // @[Core.scala:31:14] input io_imem_resp_1_valid, // @[Core.scala:31:14] input [31:0] io_imem_resp_1_bits_inst, // @[Core.scala:31:14] input [31:0] io_imem_resp_1_bits_raw_inst, // @[Core.scala:31:14] input [39:0] io_imem_resp_1_bits_pc, // @[Core.scala:31:14] input io_imem_resp_1_bits_edge_inst, // @[Core.scala:31:14] input io_imem_resp_1_bits_rvc, // @[Core.scala:31:14] input io_imem_resp_1_bits_btb_resp_valid, // @[Core.scala:31:14] input [1:0] io_imem_resp_1_bits_btb_resp_bits_cfiType, // @[Core.scala:31:14] input io_imem_resp_1_bits_btb_resp_bits_taken, // @[Core.scala:31:14] input [3:0] io_imem_resp_1_bits_btb_resp_bits_mask, // @[Core.scala:31:14] input [1:0] io_imem_resp_1_bits_btb_resp_bits_bridx, // @[Core.scala:31:14] input [38:0] io_imem_resp_1_bits_btb_resp_bits_target, // @[Core.scala:31:14] input [5:0] io_imem_resp_1_bits_btb_resp_bits_entry, // @[Core.scala:31:14] input [7:0] io_imem_resp_1_bits_btb_resp_bits_bht_history, // @[Core.scala:31:14] input [1:0] io_imem_resp_1_bits_btb_resp_bits_bht_value, // @[Core.scala:31:14] input io_imem_resp_1_bits_sfb_br, // @[Core.scala:31:14] input io_imem_resp_1_bits_next_pc_valid, // @[Core.scala:31:14] input [39:0] io_imem_resp_1_bits_next_pc_bits, // @[Core.scala:31:14] input [2:0] io_imem_resp_1_bits_ras_head, // @[Core.scala:31:14] input io_imem_resp_1_bits_xcpt, // @[Core.scala:31:14] input [63:0] io_imem_resp_1_bits_xcpt_cause, // @[Core.scala:31:14] input [1:0] io_imem_resp_1_bits_mem_size, // @[Core.scala:31:14] input io_imem_peek_0_valid, // @[Core.scala:31:14] input [31:0] io_imem_peek_0_bits_inst, // @[Core.scala:31:14] input [31:0] io_imem_peek_0_bits_raw_inst, // @[Core.scala:31:14] input [39:0] io_imem_peek_0_bits_pc, // @[Core.scala:31:14] input io_imem_peek_0_bits_edge_inst, // @[Core.scala:31:14] input io_imem_peek_0_bits_rvc, // @[Core.scala:31:14] input io_imem_peek_0_bits_btb_resp_valid, // @[Core.scala:31:14] input [1:0] io_imem_peek_0_bits_btb_resp_bits_cfiType, // @[Core.scala:31:14] input io_imem_peek_0_bits_btb_resp_bits_taken, // @[Core.scala:31:14] input [3:0] io_imem_peek_0_bits_btb_resp_bits_mask, // @[Core.scala:31:14] input [1:0] io_imem_peek_0_bits_btb_resp_bits_bridx, // @[Core.scala:31:14] input [38:0] io_imem_peek_0_bits_btb_resp_bits_target, // @[Core.scala:31:14] input [5:0] io_imem_peek_0_bits_btb_resp_bits_entry, // @[Core.scala:31:14] input [7:0] io_imem_peek_0_bits_btb_resp_bits_bht_history, // @[Core.scala:31:14] input [1:0] io_imem_peek_0_bits_btb_resp_bits_bht_value, // @[Core.scala:31:14] input io_imem_peek_0_bits_sfb_br, // @[Core.scala:31:14] input io_imem_peek_0_bits_next_pc_valid, // @[Core.scala:31:14] input [39:0] io_imem_peek_0_bits_next_pc_bits, // @[Core.scala:31:14] input [2:0] io_imem_peek_0_bits_ras_head, // @[Core.scala:31:14] input io_imem_peek_0_bits_xcpt, // @[Core.scala:31:14] input [63:0] io_imem_peek_0_bits_xcpt_cause, // @[Core.scala:31:14] input [1:0] io_imem_peek_0_bits_mem_size, // @[Core.scala:31:14] input io_imem_peek_1_valid, // @[Core.scala:31:14] input [31:0] io_imem_peek_1_bits_inst, // @[Core.scala:31:14] input [31:0] io_imem_peek_1_bits_raw_inst, // @[Core.scala:31:14] input [39:0] io_imem_peek_1_bits_pc, // @[Core.scala:31:14] input io_imem_peek_1_bits_edge_inst, // @[Core.scala:31:14] input io_imem_peek_1_bits_rvc, // @[Core.scala:31:14] input io_imem_peek_1_bits_btb_resp_valid, // @[Core.scala:31:14] input [1:0] io_imem_peek_1_bits_btb_resp_bits_cfiType, // @[Core.scala:31:14] input io_imem_peek_1_bits_btb_resp_bits_taken, // @[Core.scala:31:14] input [3:0] io_imem_peek_1_bits_btb_resp_bits_mask, // @[Core.scala:31:14] input [1:0] io_imem_peek_1_bits_btb_resp_bits_bridx, // @[Core.scala:31:14] input [38:0] io_imem_peek_1_bits_btb_resp_bits_target, // @[Core.scala:31:14] input [5:0] io_imem_peek_1_bits_btb_resp_bits_entry, // @[Core.scala:31:14] input [7:0] io_imem_peek_1_bits_btb_resp_bits_bht_history, // @[Core.scala:31:14] input [1:0] io_imem_peek_1_bits_btb_resp_bits_bht_value, // @[Core.scala:31:14] input io_imem_peek_1_bits_sfb_br, // @[Core.scala:31:14] input io_imem_peek_1_bits_next_pc_valid, // @[Core.scala:31:14] input [39:0] io_imem_peek_1_bits_next_pc_bits, // @[Core.scala:31:14] input [2:0] io_imem_peek_1_bits_ras_head, // @[Core.scala:31:14] input io_imem_peek_1_bits_xcpt, // @[Core.scala:31:14] input [63:0] io_imem_peek_1_bits_xcpt_cause, // @[Core.scala:31:14] input [1:0] io_imem_peek_1_bits_mem_size, // @[Core.scala:31:14] output io_imem_btb_update_valid, // @[Core.scala:31:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[Core.scala:31:14] output io_imem_btb_update_bits_prediction_taken, // @[Core.scala:31:14] output [3:0] io_imem_btb_update_bits_prediction_mask, // @[Core.scala:31:14] output [1:0] io_imem_btb_update_bits_prediction_bridx, // @[Core.scala:31:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[Core.scala:31:14] output [5:0] io_imem_btb_update_bits_prediction_entry, // @[Core.scala:31:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[Core.scala:31:14] output [1:0] io_imem_btb_update_bits_prediction_bht_value, // @[Core.scala:31:14] output [38:0] io_imem_btb_update_bits_pc, // @[Core.scala:31:14] output [38:0] io_imem_btb_update_bits_target, // @[Core.scala:31:14] output io_imem_btb_update_bits_isValid, // @[Core.scala:31:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[Core.scala:31:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[Core.scala:31:14] output io_imem_btb_update_bits_mispredict, // @[Core.scala:31:14] output io_imem_bht_update_valid, // @[Core.scala:31:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[Core.scala:31:14] output [1:0] io_imem_bht_update_bits_prediction_value, // @[Core.scala:31:14] output [38:0] io_imem_bht_update_bits_pc, // @[Core.scala:31:14] output io_imem_bht_update_bits_branch, // @[Core.scala:31:14] output io_imem_bht_update_bits_taken, // @[Core.scala:31:14] output io_imem_bht_update_bits_mispredict, // @[Core.scala:31:14] output io_imem_ras_update_valid, // @[Core.scala:31:14] output [2:0] io_imem_ras_update_bits_head, // @[Core.scala:31:14] output [39:0] io_imem_ras_update_bits_addr, // @[Core.scala:31:14] input io_dmem_req_ready, // @[Core.scala:31:14] output io_dmem_req_valid, // @[Core.scala:31:14] output [39:0] io_dmem_req_bits_addr, // @[Core.scala:31:14] output [6:0] io_dmem_req_bits_tag, // @[Core.scala:31:14] output [4:0] io_dmem_req_bits_cmd, // @[Core.scala:31:14] output [1:0] io_dmem_req_bits_size, // @[Core.scala:31:14] output io_dmem_req_bits_signed, // @[Core.scala:31:14] output [31:0] io_dmem_s1_paddr, // @[Core.scala:31:14] output io_dmem_s1_kill, // @[Core.scala:31:14] output [63:0] io_dmem_s1_data_data, // @[Core.scala:31:14] input io_dmem_s2_nack, // @[Core.scala:31:14] output io_dmem_s2_kill, // @[Core.scala:31:14] input io_dmem_resp_valid, // @[Core.scala:31:14] input io_dmem_resp_bits_has_data, // @[Core.scala:31:14] input [6:0] io_dmem_resp_bits_tag, // @[Core.scala:31:14] input [63:0] io_dmem_resp_bits_data, // @[Core.scala:31:14] input [1:0] io_dmem_resp_bits_size, // @[Core.scala:31:14] input io_dmem_s2_hit, // @[Core.scala:31:14] input io_dmem_ordered, // @[Core.scala:31:14] input io_dmem_store_pending, // @[Core.scala:31:14] input io_dmem_perf_acquire, // @[Core.scala:31:14] input io_dmem_perf_release, // @[Core.scala:31:14] input io_dmem_perf_grant, // @[Core.scala:31:14] output [3:0] io_ptw_ptbr_mode, // @[Core.scala:31:14] output [43:0] io_ptw_ptbr_ppn, // @[Core.scala:31:14] output io_ptw_sfence_valid, // @[Core.scala:31:14] output io_ptw_sfence_bits_rs1, // @[Core.scala:31:14] output io_ptw_sfence_bits_rs2, // @[Core.scala:31:14] output [38:0] io_ptw_sfence_bits_addr, // @[Core.scala:31:14] output io_ptw_sfence_bits_asid, // @[Core.scala:31:14] output io_ptw_sfence_bits_hv, // @[Core.scala:31:14] output io_ptw_sfence_bits_hg, // @[Core.scala:31:14] output io_ptw_status_debug, // @[Core.scala:31:14] output io_ptw_status_cease, // @[Core.scala:31:14] output io_ptw_status_wfi, // @[Core.scala:31:14] output [1:0] io_ptw_status_dprv, // @[Core.scala:31:14] output io_ptw_status_dv, // @[Core.scala:31:14] output [1:0] io_ptw_status_prv, // @[Core.scala:31:14] output io_ptw_status_v, // @[Core.scala:31:14] output io_ptw_status_sd, // @[Core.scala:31:14] output io_ptw_status_mpv, // @[Core.scala:31:14] output io_ptw_status_gva, // @[Core.scala:31:14] output io_ptw_status_tsr, // @[Core.scala:31:14] output io_ptw_status_tw, // @[Core.scala:31:14] output io_ptw_status_tvm, // @[Core.scala:31:14] output io_ptw_status_mxr, // @[Core.scala:31:14] output io_ptw_status_sum, // @[Core.scala:31:14] output io_ptw_status_mprv, // @[Core.scala:31:14] output [1:0] io_ptw_status_fs, // @[Core.scala:31:14] output [1:0] io_ptw_status_mpp, // @[Core.scala:31:14] output io_ptw_status_spp, // @[Core.scala:31:14] output io_ptw_status_mpie, // @[Core.scala:31:14] output io_ptw_status_spie, // @[Core.scala:31:14] output io_ptw_status_mie, // @[Core.scala:31:14] output io_ptw_status_sie, // @[Core.scala:31:14] output io_ptw_hstatus_spvp, // @[Core.scala:31:14] output io_ptw_hstatus_spv, // @[Core.scala:31:14] output io_ptw_hstatus_gva, // @[Core.scala:31:14] output io_ptw_gstatus_debug, // @[Core.scala:31:14] output io_ptw_gstatus_cease, // @[Core.scala:31:14] output io_ptw_gstatus_wfi, // @[Core.scala:31:14] output [31:0] io_ptw_gstatus_isa, // @[Core.scala:31:14] output [1:0] io_ptw_gstatus_dprv, // @[Core.scala:31:14] output io_ptw_gstatus_dv, // @[Core.scala:31:14] output [1:0] io_ptw_gstatus_prv, // @[Core.scala:31:14] output io_ptw_gstatus_v, // @[Core.scala:31:14] output [22:0] io_ptw_gstatus_zero2, // @[Core.scala:31:14] output io_ptw_gstatus_mpv, // @[Core.scala:31:14] output io_ptw_gstatus_gva, // @[Core.scala:31:14] output io_ptw_gstatus_mbe, // @[Core.scala:31:14] output io_ptw_gstatus_sbe, // @[Core.scala:31:14] output [1:0] io_ptw_gstatus_sxl, // @[Core.scala:31:14] output [7:0] io_ptw_gstatus_zero1, // @[Core.scala:31:14] output io_ptw_gstatus_tsr, // @[Core.scala:31:14] output io_ptw_gstatus_tw, // @[Core.scala:31:14] output io_ptw_gstatus_tvm, // @[Core.scala:31:14] output io_ptw_gstatus_mxr, // @[Core.scala:31:14] output io_ptw_gstatus_sum, // @[Core.scala:31:14] output io_ptw_gstatus_mprv, // @[Core.scala:31:14] output [1:0] io_ptw_gstatus_mpp, // @[Core.scala:31:14] output [1:0] io_ptw_gstatus_vs, // @[Core.scala:31:14] output io_ptw_gstatus_spp, // @[Core.scala:31:14] output io_ptw_gstatus_mpie, // @[Core.scala:31:14] output io_ptw_gstatus_ube, // @[Core.scala:31:14] output io_ptw_gstatus_spie, // @[Core.scala:31:14] output io_ptw_gstatus_upie, // @[Core.scala:31:14] output io_ptw_gstatus_mie, // @[Core.scala:31:14] output io_ptw_gstatus_hie, // @[Core.scala:31:14] output io_ptw_gstatus_sie, // @[Core.scala:31:14] output io_ptw_gstatus_uie, // @[Core.scala:31:14] input io_ptw_perf_l2miss, // @[Core.scala:31:14] input io_ptw_perf_l2hit, // @[Core.scala:31:14] input io_ptw_perf_pte_miss, // @[Core.scala:31:14] input io_ptw_clock_enabled, // @[Core.scala:31:14] input io_ptw_tlb_req_ready, // @[Core.scala:31:14] output io_ptw_tlb_req_valid, // @[Core.scala:31:14] output [26:0] io_ptw_tlb_req_bits_bits_addr, // @[Core.scala:31:14] input io_ptw_tlb_resp_valid, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_ae_ptw, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_ae_final, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pf, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_gf, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_hr, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_hw, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_hx, // @[Core.scala:31:14] input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[Core.scala:31:14] input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_d, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_a, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_g, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_u, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_x, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_w, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_r, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_pte_v, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_resp_bits_level, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_homogeneous, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_gpa_valid, // @[Core.scala:31:14] input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[Core.scala:31:14] input io_ptw_tlb_resp_bits_gpa_is_pte, // @[Core.scala:31:14] input [3:0] io_ptw_tlb_ptbr_mode, // @[Core.scala:31:14] input [43:0] io_ptw_tlb_ptbr_ppn, // @[Core.scala:31:14] input io_ptw_tlb_status_debug, // @[Core.scala:31:14] input io_ptw_tlb_status_cease, // @[Core.scala:31:14] input io_ptw_tlb_status_wfi, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_status_dprv, // @[Core.scala:31:14] input io_ptw_tlb_status_dv, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_status_prv, // @[Core.scala:31:14] input io_ptw_tlb_status_v, // @[Core.scala:31:14] input io_ptw_tlb_status_sd, // @[Core.scala:31:14] input io_ptw_tlb_status_mpv, // @[Core.scala:31:14] input io_ptw_tlb_status_gva, // @[Core.scala:31:14] input io_ptw_tlb_status_tsr, // @[Core.scala:31:14] input io_ptw_tlb_status_tw, // @[Core.scala:31:14] input io_ptw_tlb_status_tvm, // @[Core.scala:31:14] input io_ptw_tlb_status_mxr, // @[Core.scala:31:14] input io_ptw_tlb_status_sum, // @[Core.scala:31:14] input io_ptw_tlb_status_mprv, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_status_fs, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_status_mpp, // @[Core.scala:31:14] input io_ptw_tlb_status_spp, // @[Core.scala:31:14] input io_ptw_tlb_status_mpie, // @[Core.scala:31:14] input io_ptw_tlb_status_spie, // @[Core.scala:31:14] input io_ptw_tlb_status_mie, // @[Core.scala:31:14] input io_ptw_tlb_status_sie, // @[Core.scala:31:14] input io_ptw_tlb_hstatus_spvp, // @[Core.scala:31:14] input io_ptw_tlb_hstatus_spv, // @[Core.scala:31:14] input io_ptw_tlb_hstatus_gva, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_debug, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_cease, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_wfi, // @[Core.scala:31:14] input [31:0] io_ptw_tlb_gstatus_isa, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_gstatus_dprv, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_dv, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_gstatus_prv, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_v, // @[Core.scala:31:14] input [22:0] io_ptw_tlb_gstatus_zero2, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mpv, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_gva, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mbe, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_sbe, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_gstatus_sxl, // @[Core.scala:31:14] input [7:0] io_ptw_tlb_gstatus_zero1, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_tsr, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_tw, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_tvm, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mxr, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_sum, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mprv, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_gstatus_mpp, // @[Core.scala:31:14] input [1:0] io_ptw_tlb_gstatus_vs, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_spp, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mpie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_ube, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_spie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_upie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_mie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_hie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_sie, // @[Core.scala:31:14] input io_ptw_tlb_gstatus_uie, // @[Core.scala:31:14] output io_trace_insns_0_valid, // @[Core.scala:31:14] output [39:0] io_trace_insns_0_iaddr, // @[Core.scala:31:14] output [31:0] io_trace_insns_0_insn, // @[Core.scala:31:14] output [2:0] io_trace_insns_0_priv, // @[Core.scala:31:14] output io_trace_insns_0_exception, // @[Core.scala:31:14] output io_trace_insns_0_interrupt, // @[Core.scala:31:14] output [63:0] io_trace_insns_0_cause, // @[Core.scala:31:14] output [39:0] io_trace_insns_0_tval, // @[Core.scala:31:14] output io_trace_insns_1_valid, // @[Core.scala:31:14] output [39:0] io_trace_insns_1_iaddr, // @[Core.scala:31:14] output [31:0] io_trace_insns_1_insn, // @[Core.scala:31:14] output [2:0] io_trace_insns_1_priv, // @[Core.scala:31:14] output io_trace_insns_1_exception, // @[Core.scala:31:14] output io_trace_insns_1_interrupt, // @[Core.scala:31:14] output [63:0] io_trace_insns_1_cause, // @[Core.scala:31:14] output [39:0] io_trace_insns_1_tval, // @[Core.scala:31:14] output [63:0] io_trace_time // @[Core.scala:31:14] ); wire ll_fp_wdata_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire ll_fp_wdata_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire ll_fp_wdata_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [63:0] mem_alu_uops_0_rs2_data; // @[Core.scala:809:69] wire [63:0] mem_alu_uops_0_rs1_data; // @[Core.scala:809:69] wire [39:0] mem_alu_uops_0_pc; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_ctrl_sel_alu1; // @[Core.scala:809:69] wire [2:0] mem_alu_uops_0_ctrl_sel_alu2; // @[Core.scala:809:69] wire [63:0] _mem_brjmp_uop_WIRE_bits_wdata_bits; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_bits_pc; // @[Mux.scala:30:73] wire [63:0] wb_uops_1_bits_wdata_bits; // @[Core.scala:76:25] wire wb_uops_1_bits_wdata_valid; // @[Core.scala:76:25] wire [63:0] com_uops_1_bits_wdata_bits; // @[Core.scala:74:26] wire com_uops_1_bits_wdata_valid; // @[Core.scala:74:26] wire [63:0] com_uops_0_bits_wdata_bits; // @[Core.scala:74:26] wire com_uops_0_bits_wdata_valid; // @[Core.scala:74:26] wire rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire io_imem_sfence_bits_hg_0; // @[Core.scala:25:7] wire io_imem_sfence_bits_hv_0; // @[Core.scala:25:7] wire io_imem_sfence_bits_asid_0; // @[Core.scala:25:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[Core.scala:25:7] wire io_imem_sfence_bits_rs2_0; // @[Core.scala:25:7] wire io_imem_sfence_bits_rs1_0; // @[Core.scala:25:7] wire io_imem_sfence_valid_0; // @[Core.scala:25:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[Core.scala:25:7] wire _ll_arb_io_in_1_ready; // @[Core.scala:1228:22] wire _ll_arb_io_out_valid; // @[Core.scala:1228:22] wire [4:0] _ll_arb_io_out_bits_waddr; // @[Core.scala:1228:22] wire [63:0] _ll_arb_io_out_bits_wdata; // @[Core.scala:1228:22] wire _div_io_req_ready; // @[Core.scala:905:19] wire _div_io_resp_valid; // @[Core.scala:905:19] wire [63:0] _div_io_resp_bits_data; // @[Core.scala:905:19] wire [4:0] _div_io_resp_bits_tag; // @[Core.scala:905:19] wire _divSqrt_2_io_inReady; // @[Core.scala:882:25] wire _divSqrt_2_io_outValid_div; // @[Core.scala:882:25] wire _divSqrt_2_io_outValid_sqrt; // @[Core.scala:882:25] wire [64:0] _divSqrt_2_io_out; // @[Core.scala:882:25] wire [4:0] _divSqrt_2_io_exceptionFlags; // @[Core.scala:882:25] wire _divSqrt_1_io_inReady; // @[Core.scala:882:25] wire _divSqrt_1_io_outValid_div; // @[Core.scala:882:25] wire _divSqrt_1_io_outValid_sqrt; // @[Core.scala:882:25] wire [32:0] _divSqrt_1_io_out; // @[Core.scala:882:25] wire [4:0] _divSqrt_1_io_exceptionFlags; // @[Core.scala:882:25] wire _divSqrt_io_inReady; // @[Core.scala:882:25] wire _divSqrt_io_outValid_div; // @[Core.scala:882:25] wire _divSqrt_io_outValid_sqrt; // @[Core.scala:882:25] wire [16:0] _divSqrt_io_out; // @[Core.scala:882:25] wire [4:0] _divSqrt_io_exceptionFlags; // @[Core.scala:882:25] wire [63:0] _mem_alus_0_io_out; // @[Core.scala:810:67] wire _dtlb_io_req_0_ready; // @[Core.scala:634:20] wire _dtlb_io_resp_0_miss; // @[Core.scala:634:20] wire _dtlb_io_resp_0_pf_ld; // @[Core.scala:634:20] wire _dtlb_io_resp_0_pf_st; // @[Core.scala:634:20] wire _dtlb_io_resp_0_ae_ld; // @[Core.scala:634:20] wire _dtlb_io_resp_0_ae_st; // @[Core.scala:634:20] wire _dtlb_io_resp_0_ma_ld; // @[Core.scala:634:20] wire _dtlb_io_resp_0_ma_st; // @[Core.scala:634:20] wire [63:0] _alu_1_io_out; // @[Core.scala:579:21] wire [63:0] _alu_1_io_adder_out; // @[Core.scala:579:21] wire _alu_1_io_cmp_out; // @[Core.scala:579:21] wire [63:0] _alu_io_out; // @[Core.scala:579:21] wire [63:0] _alu_io_adder_out; // @[Core.scala:579:21] wire _alu_io_cmp_out; // @[Core.scala:579:21] wire [63:0] _mul_io_resp_bits_data; // @[Core.scala:535:19] wire [63:0] _fp_pipe_io_s1_store_data; // @[Core.scala:469:23] wire [63:0] _fp_pipe_io_s1_fpiu_toint; // @[Core.scala:469:23] wire [4:0] _fp_pipe_io_s1_fpiu_fexc; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_ldst; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_wen; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_ren1; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_ren2; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_ren3; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_swap12; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_swap23; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_s1_fpiu_fdiv_typeTagIn; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_s1_fpiu_fdiv_typeTagOut; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_fromint; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_toint; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_fastpipe; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_fma; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_div; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_sqrt; // @[Core.scala:469:23] wire _fp_pipe_io_s1_fpiu_fdiv_wflags; // @[Core.scala:469:23] wire [2:0] _fp_pipe_io_s1_fpiu_fdiv_rm; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_s1_fpiu_fdiv_fmaCmd; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_s1_fpiu_fdiv_typ; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_s1_fpiu_fdiv_fmt; // @[Core.scala:469:23] wire [64:0] _fp_pipe_io_s1_fpiu_fdiv_in1; // @[Core.scala:469:23] wire [64:0] _fp_pipe_io_s1_fpiu_fdiv_in2; // @[Core.scala:469:23] wire [64:0] _fp_pipe_io_s1_fpiu_fdiv_in3; // @[Core.scala:469:23] wire _fp_pipe_io_out_valid; // @[Core.scala:469:23] wire [64:0] _fp_pipe_io_out_bits_data; // @[Core.scala:469:23] wire [4:0] _fp_pipe_io_out_bits_exc; // @[Core.scala:469:23] wire [4:0] _fp_pipe_io_out_rd; // @[Core.scala:469:23] wire [1:0] _fp_pipe_io_out_tag; // @[Core.scala:469:23] wire [63:0] _csr_io_rw_rdata; // @[Core.scala:52:19] wire _csr_io_decode_0_fp_illegal; // @[Core.scala:52:19] wire _csr_io_decode_0_read_illegal; // @[Core.scala:52:19] wire _csr_io_decode_0_write_illegal; // @[Core.scala:52:19] wire _csr_io_decode_0_write_flush; // @[Core.scala:52:19] wire _csr_io_decode_0_system_illegal; // @[Core.scala:52:19] wire _csr_io_decode_1_fp_illegal; // @[Core.scala:52:19] wire _csr_io_decode_1_read_illegal; // @[Core.scala:52:19] wire _csr_io_decode_1_write_illegal; // @[Core.scala:52:19] wire _csr_io_decode_1_write_flush; // @[Core.scala:52:19] wire _csr_io_decode_1_system_illegal; // @[Core.scala:52:19] wire _csr_io_csr_stall; // @[Core.scala:52:19] wire _csr_io_eret; // @[Core.scala:52:19] wire _csr_io_status_debug; // @[Core.scala:52:19] wire [1:0] _csr_io_status_dprv; // @[Core.scala:52:19] wire [39:0] _csr_io_evec; // @[Core.scala:52:19] wire [2:0] _csr_io_fcsr_rm; // @[Core.scala:52:19] wire _csr_io_interrupt; // @[Core.scala:52:19] wire [63:0] _csr_io_interrupt_cause; // @[Core.scala:52:19] wire io_hartid_0 = io_hartid; // @[Core.scala:25:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[Core.scala:25:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[Core.scala:25:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[Core.scala:25:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[Core.scala:25:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[Core.scala:25:7] wire io_imem_resp_0_valid_0 = io_imem_resp_0_valid; // @[Core.scala:25:7] wire [31:0] io_imem_resp_0_bits_inst_0 = io_imem_resp_0_bits_inst; // @[Core.scala:25:7] wire [31:0] io_imem_resp_0_bits_raw_inst_0 = io_imem_resp_0_bits_raw_inst; // @[Core.scala:25:7] wire [39:0] io_imem_resp_0_bits_pc_0 = io_imem_resp_0_bits_pc; // @[Core.scala:25:7] wire io_imem_resp_0_bits_edge_inst_0 = io_imem_resp_0_bits_edge_inst; // @[Core.scala:25:7] wire io_imem_resp_0_bits_rvc_0 = io_imem_resp_0_bits_rvc; // @[Core.scala:25:7] wire io_imem_resp_0_bits_btb_resp_valid_0 = io_imem_resp_0_bits_btb_resp_valid; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_btb_resp_bits_cfiType_0 = io_imem_resp_0_bits_btb_resp_bits_cfiType; // @[Core.scala:25:7] wire io_imem_resp_0_bits_btb_resp_bits_taken_0 = io_imem_resp_0_bits_btb_resp_bits_taken; // @[Core.scala:25:7] wire [3:0] io_imem_resp_0_bits_btb_resp_bits_mask_0 = io_imem_resp_0_bits_btb_resp_bits_mask; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_btb_resp_bits_bridx_0 = io_imem_resp_0_bits_btb_resp_bits_bridx; // @[Core.scala:25:7] wire [38:0] io_imem_resp_0_bits_btb_resp_bits_target_0 = io_imem_resp_0_bits_btb_resp_bits_target; // @[Core.scala:25:7] wire [5:0] io_imem_resp_0_bits_btb_resp_bits_entry_0 = io_imem_resp_0_bits_btb_resp_bits_entry; // @[Core.scala:25:7] wire [7:0] io_imem_resp_0_bits_btb_resp_bits_bht_history_0 = io_imem_resp_0_bits_btb_resp_bits_bht_history; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_btb_resp_bits_bht_value_0 = io_imem_resp_0_bits_btb_resp_bits_bht_value; // @[Core.scala:25:7] wire io_imem_resp_0_bits_sfb_br_0 = io_imem_resp_0_bits_sfb_br; // @[Core.scala:25:7] wire io_imem_resp_0_bits_next_pc_valid_0 = io_imem_resp_0_bits_next_pc_valid; // @[Core.scala:25:7] wire [39:0] io_imem_resp_0_bits_next_pc_bits_0 = io_imem_resp_0_bits_next_pc_bits; // @[Core.scala:25:7] wire [2:0] io_imem_resp_0_bits_ras_head_0 = io_imem_resp_0_bits_ras_head; // @[Core.scala:25:7] wire io_imem_resp_0_bits_xcpt_0 = io_imem_resp_0_bits_xcpt; // @[Core.scala:25:7] wire [63:0] io_imem_resp_0_bits_xcpt_cause_0 = io_imem_resp_0_bits_xcpt_cause; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_mem_size_0 = io_imem_resp_0_bits_mem_size; // @[Core.scala:25:7] wire io_imem_resp_1_valid_0 = io_imem_resp_1_valid; // @[Core.scala:25:7] wire [31:0] io_imem_resp_1_bits_inst_0 = io_imem_resp_1_bits_inst; // @[Core.scala:25:7] wire [31:0] io_imem_resp_1_bits_raw_inst_0 = io_imem_resp_1_bits_raw_inst; // @[Core.scala:25:7] wire [39:0] io_imem_resp_1_bits_pc_0 = io_imem_resp_1_bits_pc; // @[Core.scala:25:7] wire io_imem_resp_1_bits_edge_inst_0 = io_imem_resp_1_bits_edge_inst; // @[Core.scala:25:7] wire io_imem_resp_1_bits_rvc_0 = io_imem_resp_1_bits_rvc; // @[Core.scala:25:7] wire io_imem_resp_1_bits_btb_resp_valid_0 = io_imem_resp_1_bits_btb_resp_valid; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_btb_resp_bits_cfiType_0 = io_imem_resp_1_bits_btb_resp_bits_cfiType; // @[Core.scala:25:7] wire io_imem_resp_1_bits_btb_resp_bits_taken_0 = io_imem_resp_1_bits_btb_resp_bits_taken; // @[Core.scala:25:7] wire [3:0] io_imem_resp_1_bits_btb_resp_bits_mask_0 = io_imem_resp_1_bits_btb_resp_bits_mask; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_btb_resp_bits_bridx_0 = io_imem_resp_1_bits_btb_resp_bits_bridx; // @[Core.scala:25:7] wire [38:0] io_imem_resp_1_bits_btb_resp_bits_target_0 = io_imem_resp_1_bits_btb_resp_bits_target; // @[Core.scala:25:7] wire [5:0] io_imem_resp_1_bits_btb_resp_bits_entry_0 = io_imem_resp_1_bits_btb_resp_bits_entry; // @[Core.scala:25:7] wire [7:0] io_imem_resp_1_bits_btb_resp_bits_bht_history_0 = io_imem_resp_1_bits_btb_resp_bits_bht_history; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_btb_resp_bits_bht_value_0 = io_imem_resp_1_bits_btb_resp_bits_bht_value; // @[Core.scala:25:7] wire io_imem_resp_1_bits_sfb_br_0 = io_imem_resp_1_bits_sfb_br; // @[Core.scala:25:7] wire io_imem_resp_1_bits_next_pc_valid_0 = io_imem_resp_1_bits_next_pc_valid; // @[Core.scala:25:7] wire [39:0] io_imem_resp_1_bits_next_pc_bits_0 = io_imem_resp_1_bits_next_pc_bits; // @[Core.scala:25:7] wire [2:0] io_imem_resp_1_bits_ras_head_0 = io_imem_resp_1_bits_ras_head; // @[Core.scala:25:7] wire io_imem_resp_1_bits_xcpt_0 = io_imem_resp_1_bits_xcpt; // @[Core.scala:25:7] wire [63:0] io_imem_resp_1_bits_xcpt_cause_0 = io_imem_resp_1_bits_xcpt_cause; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_mem_size_0 = io_imem_resp_1_bits_mem_size; // @[Core.scala:25:7] wire io_imem_peek_0_valid_0 = io_imem_peek_0_valid; // @[Core.scala:25:7] wire [31:0] io_imem_peek_0_bits_inst_0 = io_imem_peek_0_bits_inst; // @[Core.scala:25:7] wire [31:0] io_imem_peek_0_bits_raw_inst_0 = io_imem_peek_0_bits_raw_inst; // @[Core.scala:25:7] wire [39:0] io_imem_peek_0_bits_pc_0 = io_imem_peek_0_bits_pc; // @[Core.scala:25:7] wire io_imem_peek_0_bits_edge_inst_0 = io_imem_peek_0_bits_edge_inst; // @[Core.scala:25:7] wire io_imem_peek_0_bits_rvc_0 = io_imem_peek_0_bits_rvc; // @[Core.scala:25:7] wire io_imem_peek_0_bits_btb_resp_valid_0 = io_imem_peek_0_bits_btb_resp_valid; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_btb_resp_bits_cfiType_0 = io_imem_peek_0_bits_btb_resp_bits_cfiType; // @[Core.scala:25:7] wire io_imem_peek_0_bits_btb_resp_bits_taken_0 = io_imem_peek_0_bits_btb_resp_bits_taken; // @[Core.scala:25:7] wire [3:0] io_imem_peek_0_bits_btb_resp_bits_mask_0 = io_imem_peek_0_bits_btb_resp_bits_mask; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_btb_resp_bits_bridx_0 = io_imem_peek_0_bits_btb_resp_bits_bridx; // @[Core.scala:25:7] wire [38:0] io_imem_peek_0_bits_btb_resp_bits_target_0 = io_imem_peek_0_bits_btb_resp_bits_target; // @[Core.scala:25:7] wire [5:0] io_imem_peek_0_bits_btb_resp_bits_entry_0 = io_imem_peek_0_bits_btb_resp_bits_entry; // @[Core.scala:25:7] wire [7:0] io_imem_peek_0_bits_btb_resp_bits_bht_history_0 = io_imem_peek_0_bits_btb_resp_bits_bht_history; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_btb_resp_bits_bht_value_0 = io_imem_peek_0_bits_btb_resp_bits_bht_value; // @[Core.scala:25:7] wire io_imem_peek_0_bits_sfb_br_0 = io_imem_peek_0_bits_sfb_br; // @[Core.scala:25:7] wire io_imem_peek_0_bits_next_pc_valid_0 = io_imem_peek_0_bits_next_pc_valid; // @[Core.scala:25:7] wire [39:0] io_imem_peek_0_bits_next_pc_bits_0 = io_imem_peek_0_bits_next_pc_bits; // @[Core.scala:25:7] wire [2:0] io_imem_peek_0_bits_ras_head_0 = io_imem_peek_0_bits_ras_head; // @[Core.scala:25:7] wire io_imem_peek_0_bits_xcpt_0 = io_imem_peek_0_bits_xcpt; // @[Core.scala:25:7] wire [63:0] io_imem_peek_0_bits_xcpt_cause_0 = io_imem_peek_0_bits_xcpt_cause; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_mem_size_0 = io_imem_peek_0_bits_mem_size; // @[Core.scala:25:7] wire io_imem_peek_1_valid_0 = io_imem_peek_1_valid; // @[Core.scala:25:7] wire [31:0] io_imem_peek_1_bits_inst_0 = io_imem_peek_1_bits_inst; // @[Core.scala:25:7] wire [31:0] io_imem_peek_1_bits_raw_inst_0 = io_imem_peek_1_bits_raw_inst; // @[Core.scala:25:7] wire [39:0] io_imem_peek_1_bits_pc_0 = io_imem_peek_1_bits_pc; // @[Core.scala:25:7] wire io_imem_peek_1_bits_edge_inst_0 = io_imem_peek_1_bits_edge_inst; // @[Core.scala:25:7] wire io_imem_peek_1_bits_rvc_0 = io_imem_peek_1_bits_rvc; // @[Core.scala:25:7] wire io_imem_peek_1_bits_btb_resp_valid_0 = io_imem_peek_1_bits_btb_resp_valid; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_btb_resp_bits_cfiType_0 = io_imem_peek_1_bits_btb_resp_bits_cfiType; // @[Core.scala:25:7] wire io_imem_peek_1_bits_btb_resp_bits_taken_0 = io_imem_peek_1_bits_btb_resp_bits_taken; // @[Core.scala:25:7] wire [3:0] io_imem_peek_1_bits_btb_resp_bits_mask_0 = io_imem_peek_1_bits_btb_resp_bits_mask; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_btb_resp_bits_bridx_0 = io_imem_peek_1_bits_btb_resp_bits_bridx; // @[Core.scala:25:7] wire [38:0] io_imem_peek_1_bits_btb_resp_bits_target_0 = io_imem_peek_1_bits_btb_resp_bits_target; // @[Core.scala:25:7] wire [5:0] io_imem_peek_1_bits_btb_resp_bits_entry_0 = io_imem_peek_1_bits_btb_resp_bits_entry; // @[Core.scala:25:7] wire [7:0] io_imem_peek_1_bits_btb_resp_bits_bht_history_0 = io_imem_peek_1_bits_btb_resp_bits_bht_history; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_btb_resp_bits_bht_value_0 = io_imem_peek_1_bits_btb_resp_bits_bht_value; // @[Core.scala:25:7] wire io_imem_peek_1_bits_sfb_br_0 = io_imem_peek_1_bits_sfb_br; // @[Core.scala:25:7] wire io_imem_peek_1_bits_next_pc_valid_0 = io_imem_peek_1_bits_next_pc_valid; // @[Core.scala:25:7] wire [39:0] io_imem_peek_1_bits_next_pc_bits_0 = io_imem_peek_1_bits_next_pc_bits; // @[Core.scala:25:7] wire [2:0] io_imem_peek_1_bits_ras_head_0 = io_imem_peek_1_bits_ras_head; // @[Core.scala:25:7] wire io_imem_peek_1_bits_xcpt_0 = io_imem_peek_1_bits_xcpt; // @[Core.scala:25:7] wire [63:0] io_imem_peek_1_bits_xcpt_cause_0 = io_imem_peek_1_bits_xcpt_cause; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_mem_size_0 = io_imem_peek_1_bits_mem_size; // @[Core.scala:25:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[Core.scala:25:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[Core.scala:25:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[Core.scala:25:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[Core.scala:25:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[Core.scala:25:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[Core.scala:25:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[Core.scala:25:7] wire io_dmem_s2_hit_0 = io_dmem_s2_hit; // @[Core.scala:25:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[Core.scala:25:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[Core.scala:25:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[Core.scala:25:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[Core.scala:25:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[Core.scala:25:7] wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[Core.scala:25:7] wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[Core.scala:25:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[Core.scala:25:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[Core.scala:25:7] wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[Core.scala:25:7] wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[Core.scala:25:7] wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[Core.scala:25:7] wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[Core.scala:25:7] wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[Core.scala:25:7] wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[Core.scala:25:7] wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[Core.scala:25:7] wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[Core.scala:25:7] wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[Core.scala:25:7] wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[Core.scala:25:7] wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[Core.scala:25:7] wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[Core.scala:25:7] wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[Core.scala:25:7] wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[Core.scala:25:7] wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[Core.scala:25:7] wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[Core.scala:25:7] wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[Core.scala:25:7] wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[Core.scala:25:7] wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[Core.scala:25:7] wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[Core.scala:25:7] wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[Core.scala:25:7] wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[Core.scala:25:7] wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[Core.scala:25:7] wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[Core.scala:25:7] wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[Core.scala:25:7] wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_spvp_0 = io_ptw_tlb_hstatus_spvp; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_spv_0 = io_ptw_tlb_hstatus_spv; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_gva_0 = io_ptw_tlb_hstatus_gva; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_debug_0 = io_ptw_tlb_gstatus_debug; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_cease_0 = io_ptw_tlb_gstatus_cease; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_wfi_0 = io_ptw_tlb_gstatus_wfi; // @[Core.scala:25:7] wire [31:0] io_ptw_tlb_gstatus_isa_0 = io_ptw_tlb_gstatus_isa; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_dprv_0 = io_ptw_tlb_gstatus_dprv; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_dv_0 = io_ptw_tlb_gstatus_dv; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_prv_0 = io_ptw_tlb_gstatus_prv; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_v_0 = io_ptw_tlb_gstatus_v; // @[Core.scala:25:7] wire [22:0] io_ptw_tlb_gstatus_zero2_0 = io_ptw_tlb_gstatus_zero2; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mpv_0 = io_ptw_tlb_gstatus_mpv; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_gva_0 = io_ptw_tlb_gstatus_gva; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mbe_0 = io_ptw_tlb_gstatus_mbe; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_sbe_0 = io_ptw_tlb_gstatus_sbe; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_sxl_0 = io_ptw_tlb_gstatus_sxl; // @[Core.scala:25:7] wire [7:0] io_ptw_tlb_gstatus_zero1_0 = io_ptw_tlb_gstatus_zero1; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_tsr_0 = io_ptw_tlb_gstatus_tsr; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_tw_0 = io_ptw_tlb_gstatus_tw; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_tvm_0 = io_ptw_tlb_gstatus_tvm; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mxr_0 = io_ptw_tlb_gstatus_mxr; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_sum_0 = io_ptw_tlb_gstatus_sum; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mprv_0 = io_ptw_tlb_gstatus_mprv; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_mpp_0 = io_ptw_tlb_gstatus_mpp; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_vs_0 = io_ptw_tlb_gstatus_vs; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_spp_0 = io_ptw_tlb_gstatus_spp; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mpie_0 = io_ptw_tlb_gstatus_mpie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_ube_0 = io_ptw_tlb_gstatus_ube; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_spie_0 = io_ptw_tlb_gstatus_spie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_upie_0 = io_ptw_tlb_gstatus_upie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_mie_0 = io_ptw_tlb_gstatus_mie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_hie_0 = io_ptw_tlb_gstatus_hie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_sie_0 = io_ptw_tlb_gstatus_sie; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_uie_0 = io_ptw_tlb_gstatus_uie; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_legal = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_fp = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rocc = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_branch = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_jal = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_jalr = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rxs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rxs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_alu_dw = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_mem = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rfs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rfs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_rfs3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_wfd = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_mul = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_wxd = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_fence_i = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_fence = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_amo = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_dp = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fp_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_sets_vcfg = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_sfb_shadow = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_taken = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_needs_replay = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_uses_memalu = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_uses_latealu = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_wdata_valid = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_fdivin_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_0_bits_flush_pipe = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_legal = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_fp = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rocc = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_branch = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_jal = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_jalr = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rxs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rxs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_alu_dw = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_mem = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rfs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rfs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_rfs3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_wfd = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_mul = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_wxd = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_fence_i = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_fence = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_amo = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_dp = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fp_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_sets_vcfg = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_sfb_shadow = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_taken = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_needs_replay = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_uses_memalu = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_uses_latealu = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_wdata_valid = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_div = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_fdivin_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_resp_1_bits_flush_pipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_legal = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_fp = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rocc = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_branch = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_jal = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_jalr = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rxs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rxs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_alu_dw = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_mem = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rfs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rfs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_rfs3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_wfd = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_mul = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_wxd = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_fence_i = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_fence = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_amo = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_dp = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fp_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_sets_vcfg = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_sfb_shadow = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_taken = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_needs_replay = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_uses_memalu = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_uses_latealu = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_wdata_valid = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_fdivin_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_0_bits_flush_pipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_legal = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_fp = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rocc = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_branch = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_jal = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_jalr = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rxs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rxs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_alu_dw = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_mem = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rfs1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rfs2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_rfs3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_wfd = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_mul = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_wxd = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_fence_i = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_fence = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_amo = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_dp = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fp_ctrl_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_sets_vcfg = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_sfb_shadow = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_taken = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_needs_replay = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_uses_memalu = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_uses_latealu = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_wdata_valid = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_ldst = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_wen = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_ren1 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_ren2 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_ren3 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_swap12 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_swap23 = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_fromint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_toint = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_fma = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_div = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_sqrt = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_wflags = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_fdivin_vec = 1'h0; // @[Core.scala:25:7] wire io_imem_peek_1_bits_flush_pipe = 1'h0; // @[Core.scala:25:7] wire io_imem_btb_update_bits_taken = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_tlbMiss = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_blocked = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_canAcceptStoreThenLoad = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_canAcceptStoreThenRMW = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_canAcceptLoadThenLoad = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Core.scala:25:7] wire io_dmem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_mbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_sbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_ube = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_upie = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_hie = 1'h0; // @[Core.scala:25:7] wire io_ptw_status_uie = 1'h0; // @[Core.scala:25:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[Core.scala:25:7] wire io_ptw_hstatus_vtw = 1'h0; // @[Core.scala:25:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[Core.scala:25:7] wire io_ptw_hstatus_hu = 1'h0; // @[Core.scala:25:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Core.scala:25:7] wire io_ptw_perf_pte_hit = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_mbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_sbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_ube = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_upie = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_hie = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_status_uie = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_hu = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_ready = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_valid = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_debug = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_cease = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_dv = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_v = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_sd = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_gva = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_tw = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_sum = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_spp = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_spie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_mie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_sie = 1'h0; // @[Core.scala:25:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[Core.scala:25:7] wire io_rocc_resp_valid = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_ready = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_valid = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s1_kill = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_nack = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_kill = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_resp_valid = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_replay_next = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_ordered = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_store_pending = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_release = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_grant = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[Core.scala:25:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[Core.scala:25:7] wire io_rocc_busy = 1'h0; // @[Core.scala:25:7] wire io_rocc_interrupt = 1'h0; // @[Core.scala:25:7] wire io_rocc_exception = 1'h0; // @[Core.scala:25:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire rrd_uops_0_bits_ctrl_vec = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_sets_vcfg = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_sfb_shadow = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_taken = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_needs_replay = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_uses_memalu = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_uses_latealu = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_wdata_valid = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_ldst = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_wen = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_ren1 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_ren2 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_ren3 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_swap12 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_swap23 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_fromint = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_toint = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_fma = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_div = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_sqrt = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_wflags = 1'h0; // @[Core.scala:70:22] wire rrd_uops_0_bits_fdivin_vec = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_vec = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_sets_vcfg = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_taken = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_needs_replay = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_wdata_valid = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_ldst = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_wen = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_ren1 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_ren2 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_ren3 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_swap12 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_swap23 = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_fromint = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_toint = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_fastpipe = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_fma = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_div = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_sqrt = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_wflags = 1'h0; // @[Core.scala:70:22] wire rrd_uops_1_bits_fdivin_vec = 1'h0; // @[Core.scala:70:22] wire fp_mem_bypasses_0_can_bypass = 1'h0; // @[Core.scala:101:66] wire fp_mem_bypasses_1_can_bypass = 1'h0; // @[Core.scala:101:66] wire fp_com_bypasses_0_can_bypass = 1'h0; // @[Core.scala:102:66] wire fp_com_bypasses_1_can_bypass = 1'h0; // @[Core.scala:102:66] wire _kill_com_WIRE_0 = 1'h0; // @[Core.scala:112:34] wire _kill_com_WIRE_1 = 1'h0; // @[Core.scala:112:34] wire kill_com_0 = 1'h0; // @[Core.scala:112:26] wire _rrd_uops_0_bits_sets_vcfg_T_8 = 1'h0; // @[Core.scala:186:122] wire _rrd_uops_1_bits_sets_vcfg_T_8 = 1'h0; // @[Core.scala:186:122] wire _rrd_illegal_insn_0_T_6 = 1'h0; // @[Core.scala:247:17] wire _rrd_illegal_insn_1_T_6 = 1'h0; // @[Core.scala:247:17] wire _isboard_clear_WIRE_0 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_1 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_2 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_3 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_4 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_5 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_6 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_7 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_8 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_9 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_10 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_11 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_12 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_13 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_14 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_15 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_16 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_17 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_18 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_19 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_20 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_21 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_22 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_23 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_24 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_25 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_26 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_27 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_28 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_29 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_30 = 1'h0; // @[Core.scala:279:39] wire _isboard_clear_WIRE_31 = 1'h0; // @[Core.scala:279:39] wire _isboard_set_WIRE_0 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_1 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_2 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_3 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_4 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_5 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_6 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_7 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_8 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_9 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_10 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_11 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_12 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_13 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_14 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_15 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_16 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_17 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_18 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_19 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_20 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_21 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_22 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_23 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_24 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_25 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_26 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_27 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_28 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_29 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_30 = 1'h0; // @[Core.scala:280:37] wire _isboard_set_WIRE_31 = 1'h0; // @[Core.scala:280:37] wire sfb_shadow = 1'h0; // @[Core.scala:317:33] wire _rs1_can_forward_from_x_p0_T = 1'h0; // @[Core.scala:333:45] wire _rs1_can_forward_from_x_p0_T_1 = 1'h0; // @[Core.scala:333:74] wire _rs1_can_forward_from_x_p0_T_23 = 1'h0; // @[Core.scala:333:88] wire _rs1_can_forward_from_x_p0_T_27 = 1'h0; // @[Core.scala:333:117] wire _rs1_can_forward_from_x_p0_T_29 = 1'h0; // @[Core.scala:333:142] wire _rs1_can_forward_from_x_p0_T_31 = 1'h0; // @[Core.scala:333:173] wire rs1_can_forward_from_x_p0 = 1'h0; // @[Core.scala:333:188] wire _rs2_can_forward_from_x_p0_T = 1'h0; // @[Core.scala:334:45] wire _rs2_can_forward_from_x_p0_T_1 = 1'h0; // @[Core.scala:334:74] wire _rs2_can_forward_from_x_p0_T_23 = 1'h0; // @[Core.scala:334:88] wire _rs2_can_forward_from_x_p0_T_27 = 1'h0; // @[Core.scala:334:117] wire _rs2_can_forward_from_x_p0_T_29 = 1'h0; // @[Core.scala:334:142] wire _rs2_can_forward_from_x_p0_T_31 = 1'h0; // @[Core.scala:334:173] wire rs2_can_forward_from_x_p0 = 1'h0; // @[Core.scala:334:188] wire _rs1_can_forward_from_w_p0_T = 1'h0; // @[Core.scala:335:45] wire _rs1_can_forward_from_w_p0_T_1 = 1'h0; // @[Core.scala:335:74] wire _rs1_can_forward_from_w_p0_T_23 = 1'h0; // @[Core.scala:335:88] wire _rs1_can_forward_from_w_p0_T_27 = 1'h0; // @[Core.scala:335:117] wire _rs1_can_forward_from_w_p0_T_29 = 1'h0; // @[Core.scala:335:142] wire rs1_can_forward_from_w_p0 = 1'h0; // @[Core.scala:335:173] wire _rs2_can_forward_from_w_p0_T = 1'h0; // @[Core.scala:336:45] wire _rs2_can_forward_from_w_p0_T_1 = 1'h0; // @[Core.scala:336:74] wire _rs2_can_forward_from_w_p0_T_23 = 1'h0; // @[Core.scala:336:88] wire _rs2_can_forward_from_w_p0_T_27 = 1'h0; // @[Core.scala:336:117] wire _rs2_can_forward_from_w_p0_T_29 = 1'h0; // @[Core.scala:336:142] wire rs2_can_forward_from_w_p0 = 1'h0; // @[Core.scala:336:173] wire _frs1_same_hazard_T = 1'h0; // @[Core.scala:365:39] wire frs1_same_hazard = 1'h0; // @[Core.scala:365:124] wire _frs2_same_hazard_T = 1'h0; // @[Core.scala:366:39] wire frs2_same_hazard = 1'h0; // @[Core.scala:366:124] wire _frs3_same_hazard_T = 1'h0; // @[Core.scala:367:39] wire frs3_same_hazard = 1'h0; // @[Core.scala:367:124] wire _frd_same_hazard_T = 1'h0; // @[Core.scala:368:39] wire frd_same_hazard = 1'h0; // @[Core.scala:368:124] wire _rrd_uops_0_bits_uses_memalu_T_21 = 1'h0; // @[Core.scala:371:79] wire _rrd_uops_0_bits_uses_memalu_T_22 = 1'h0; // @[Core.scala:371:124] wire _rrd_uops_0_bits_uses_memalu_T_23 = 1'h0; // @[Core.scala:371:109] wire _rrd_uops_0_bits_uses_memalu_T_24 = 1'h0; // @[Core.scala:371:63] wire _rrd_uops_0_bits_uses_memalu_T_25 = 1'h0; // @[Core.scala:371:155] wire _rrd_uops_0_bits_uses_memalu_T_27 = 1'h0; // @[Core.scala:371:173] wire _rrd_uops_0_bits_uses_latealu_T_21 = 1'h0; // @[Core.scala:372:80] wire _rrd_uops_0_bits_uses_latealu_T_22 = 1'h0; // @[Core.scala:372:125] wire _rrd_uops_0_bits_uses_latealu_T_23 = 1'h0; // @[Core.scala:372:110] wire _rrd_uops_0_bits_uses_latealu_T_24 = 1'h0; // @[Core.scala:372:64] wire _rrd_uops_0_bits_uses_latealu_T_25 = 1'h0; // @[Core.scala:372:156] wire _rrd_uops_0_bits_uses_latealu_T_27 = 1'h0; // @[Core.scala:372:175] wire _frs1_same_hazard_T_5 = 1'h0; // @[Core.scala:365:39] wire frs1_same_hazard_1 = 1'h0; // @[Core.scala:365:124] wire _frs2_same_hazard_T_5 = 1'h0; // @[Core.scala:366:39] wire frs2_same_hazard_1 = 1'h0; // @[Core.scala:366:124] wire _frs3_same_hazard_T_5 = 1'h0; // @[Core.scala:367:39] wire frs3_same_hazard_1 = 1'h0; // @[Core.scala:367:124] wire _frd_same_hazard_T_5 = 1'h0; // @[Core.scala:368:39] wire frd_same_hazard_1 = 1'h0; // @[Core.scala:368:124] wire _is_pipe0_T_29 = 1'h0; // @[Core.scala:418:26] wire _is_pipe0_T_32 = 1'h0; // @[Core.scala:419:26] wire _is_pipe0_T_36 = 1'h0; // @[Core.scala:422:71] wire _rrd_stall_0_T_2 = 1'h0; // @[Core.scala:440:17] wire _rrd_stall_0_T_4 = 1'h0; // @[Core.scala:441:22] wire _rrd_stall_0_T_6 = 1'h0; // @[Core.scala:442:26] wire _rrd_stall_0_T_8 = 1'h0; // @[Core.scala:443:24] wire rrd_fence_stall_1 = 1'h0; // @[Core.scala:413:38] wire _rrd_rocc_stall_T_2 = 1'h0; // @[Core.scala:415:37] wire rrd_rocc_stall_1 = 1'h0; // @[Core.scala:415:50] wire _is_pipe0_T_95 = 1'h0; // @[Core.scala:422:71] wire _rrd_stall_1_T_6 = 1'h0; // @[Core.scala:442:26] wire _fsboard_set_WIRE_0 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_1 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_2 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_3 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_4 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_5 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_6 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_7 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_8 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_9 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_10 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_11 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_12 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_13 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_14 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_15 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_16 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_17 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_18 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_19 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_20 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_21 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_22 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_23 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_24 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_25 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_26 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_27 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_28 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_29 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_30 = 1'h0; // @[Core.scala:461:37] wire _fsboard_set_WIRE_31 = 1'h0; // @[Core.scala:461:37] wire _fsboard_clear_WIRE_0 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_1 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_2 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_3 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_4 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_5 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_6 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_7 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_8 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_9 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_10 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_11 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_12 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_13 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_14 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_15 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_16 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_17 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_18 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_19 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_20 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_21 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_22 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_23 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_24 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_25 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_26 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_27 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_28 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_29 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_30 = 1'h0; // @[Core.scala:462:39] wire _fsboard_clear_WIRE_31 = 1'h0; // @[Core.scala:462:39] wire frd_maybe_hazard_bypass_data = 1'h0; // @[Core.scala:293:31] wire frs1_hazard_bypass_data = 1'h0; // @[Core.scala:293:31] wire frs2_hazard_bypass_data = 1'h0; // @[Core.scala:293:31] wire frs3_hazard_bypass_data = 1'h0; // @[Core.scala:293:31] wire frd_maybe_hazard_bypass_data_1 = 1'h0; // @[Core.scala:293:31] wire ex_setvcfg_valid_0 = 1'h0; // @[Core.scala:509:55] wire ex_setvcfg_valid_1 = 1'h0; // @[Core.scala:509:55] wire _ex_setvcfg_uop_WIRE_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_edge_inst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_rvc = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_btb_resp_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_sfb_br = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_next_pc_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_xcpt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_bits_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_edge_inst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_legal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_fp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rocc = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_branch = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_jal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_jalr = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_mem = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_wfd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_mul = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_wxd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_fence = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_amo = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_dp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fp_ctrl_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_rvc = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_btb_resp_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_btb_resp_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_sfb_br = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_sfb_shadow = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_next_pc_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_xcpt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_needs_replay = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_uses_memalu = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_uses_latealu = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_wdata_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_fdivin_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_1_flush_pipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_4_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_27 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_28 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_29 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_30 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_31 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_32 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_33 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_34 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_35 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_14 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_36 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_37 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_38 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_15 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_39 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_40 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_41 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_16 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_42 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_43 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_44 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_17 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_45 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_46 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_47 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_18 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_48 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_49 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_50 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_19 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_57 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_58 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_59 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_22 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_60 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_61 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_62 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_63 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_64 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_65 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_24 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_66 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_67 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_68 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_25 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_69 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_70 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_71 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_26 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_72 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_73 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_74 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_27 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_75 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_76 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_77 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_28 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_33_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_93 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_94 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_95 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_35 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_97 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_98 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_36 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_100 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_101 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_37 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_111 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_112 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_113 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_41 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_117 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_118 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_119 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_43 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_120 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_121 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_122 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_44 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_46_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_129 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_130 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_131 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_48 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_132 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_133 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_134 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_49 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_135 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_136 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_137 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_50 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_51_valid = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_51_bits_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_52_taken = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_156 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_157 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_158 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_60 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_162 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_163 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_164 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_62 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_63 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_168 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_169 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_170 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_64 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_ldst = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_wen = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_ren1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_ren2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_ren3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_swap12 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_swap23 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_fromint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_toint = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_fastpipe = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_fma = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_sqrt = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_wflags = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_65_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_171 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_172 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_173 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_66 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_174 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_175 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_176 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_67 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_177 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_178 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_179 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_68 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_180 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_181 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_182 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_69 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_183 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_184 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_185 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_70 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_186 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_187 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_188 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_71 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_189 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_190 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_191 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_72 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_192 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_193 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_194 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_73 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_201 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_202 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_203 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_76 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_204 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_205 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_206 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_77 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_207 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_208 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_209 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_78 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_210 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_211 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_212 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_79 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_213 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_214 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_215 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_80 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_216 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_217 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_218 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_81 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_219 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_220 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_221 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_82 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_legal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_fp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rocc = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_branch = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_jal = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_jalr = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rxs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rxs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_alu_dw = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_mem = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rfs1 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rfs2 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_rfs3 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_wfd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_mul = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_div = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_wxd = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_fence_i = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_fence = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_amo = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_dp = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_83_vec = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_222 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_223 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_224 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_84 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_225 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_226 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_227 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_85 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_228 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_229 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_230 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_86 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_231 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_232 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_233 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_87 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_234 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_235 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_236 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_88 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_240 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_241 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_242 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_90 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_243 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_244 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_245 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_91 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_246 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_247 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_248 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_92 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_249 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_250 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_251 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_93 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_252 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_253 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_254 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_94 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_255 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_256 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_257 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_95 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_258 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_259 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_260 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_96 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_264 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_265 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_266 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_98 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_270 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_271 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_272 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_100 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_282 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_283 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_284 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_104 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_285 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_286 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_287 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_105 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_288 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_289 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_290 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_106 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_291 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_292 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_293 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_107 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_294 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_295 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_296 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_108 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_297 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_298 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_299 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_109 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_300 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_301 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_302 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_110 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_303 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_304 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_305 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_111 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_306 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_307 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_308 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_112 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_318 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_319 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_T_320 = 1'h0; // @[Mux.scala:30:73] wire _ex_setvcfg_uop_WIRE_116 = 1'h0; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_sets_vcfg = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_96 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_99 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_132 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_165 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_166 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_167 = 1'h0; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_62 = 1'h0; // @[Mux.scala:30:73] wire _mem_uops_reg_0_bits_wdata_bits_T_1 = 1'h0; // @[Core.scala:605:58] wire _mem_uops_reg_1_bits_wdata_bits_T_1 = 1'h0; // @[Core.scala:605:58] wire _mem_brjmp_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_brjmp_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_brjmp_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_brjmp_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_brjmp_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_brjmp_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_brjmp_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_brjmp_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_brjmp_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_brjmp_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_brjmp_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_brjmp_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_brjmp_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_brjmp_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_brjmp_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_brjmp_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_brjmp_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_brjmp_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_brjmp_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_brjmp_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_brjmp_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_brjmp_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_brjmp_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_brjmp_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_brjmp_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_brjmp_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_brjmp_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_brjmp_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_brjmp_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_brjmp_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_brjmp_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_brjmp_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_brjmp_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_brjmp_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_brjmp_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_brjmp_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_brjmp_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_brjmp_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_brjmp_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_brjmp_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire sfb_shadow_kill = 1'h0; // @[Core.scala:775:35] wire [2:0] io_imem_resp_0_bits_ctrl_sel_alu2 = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_0_bits_ctrl_sel_imm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_0_bits_ctrl_csr = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_0_bits_fdivin_rm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_1_bits_ctrl_sel_alu2 = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_1_bits_ctrl_sel_imm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_1_bits_ctrl_csr = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_resp_1_bits_fdivin_rm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_0_bits_ctrl_sel_alu2 = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_0_bits_ctrl_sel_imm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_0_bits_ctrl_csr = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_0_bits_fdivin_rm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_1_bits_ctrl_sel_alu2 = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_1_bits_ctrl_sel_imm = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_1_bits_ctrl_csr = 3'h0; // @[Core.scala:25:7] wire [2:0] io_imem_peek_1_bits_fdivin_rm = 3'h0; // @[Core.scala:25:7] wire [2:0] rrd_uops_0_bits_fdivin_rm = 3'h0; // @[Core.scala:70:22] wire [2:0] rrd_uops_1_bits_fdivin_rm = 3'h0; // @[Core.scala:70:22] wire [2:0] _ex_setvcfg_uop_WIRE_bits_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_bits_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_bits_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_bits_ras_head = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_bits_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_1_ctrl_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_1_ctrl_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_1_ctrl_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_1_ras_head = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_1_fdivin_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_4_rm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_24 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_25 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_26 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_11 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_123 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_124 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_125 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_45 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_83_sel_alu2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_83_sel_imm = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_83_csr = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_237 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_238 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_239 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_89 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_273 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_274 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_275 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_101 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_279 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_280 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_T_281 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_setvcfg_uop_WIRE_103 = 3'h0; // @[Mux.scala:30:73] wire [1:0] io_imem_resp_0_bits_ctrl_sel_alu1 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fdivin_typ = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_0_bits_fdivin_fmt = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_ctrl_sel_alu1 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fdivin_typ = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_resp_1_bits_fdivin_fmt = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_ctrl_sel_alu1 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fdivin_typ = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_0_bits_fdivin_fmt = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_ctrl_sel_alu1 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fdivin_typ = 2'h0; // @[Core.scala:25:7] wire [1:0] io_imem_peek_1_bits_fdivin_fmt = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[Core.scala:25:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[Core.scala:25:7] wire [1:0] rrd_uops_0_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fdivin_typ = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fdivin_fmt = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fdivin_typeTagIn = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fdivin_typeTagOut = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fdivin_fmaCmd = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fdivin_typ = 2'h0; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fdivin_fmt = 2'h0; // @[Core.scala:70:22] wire [1:0] _ex_setvcfg_uop_WIRE_bits_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_cfiType = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_bridx = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_bht_value = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_bits_mem_size = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_ctrl_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_cfiType = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_bridx = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_bht_value = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fdivin_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fdivin_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fdivin_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fdivin_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_fdivin_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_1_mem_size = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_3 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_4 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_5 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_3 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_4_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_4_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_4_fmaCmd = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_4_typ = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_4_fmt = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_15 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_16 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_17 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_8 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_18 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_19 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_9 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_22 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_23 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_10 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_51 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_52 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_53 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_20 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_55 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_56 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_21 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_51_bits_cfiType = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_51_bits_bridx = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_51_bits_bht_value = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_52_cfiType = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_52_bridx = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_52_bht_value = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_53_value = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_138 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_139 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_140 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_54 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_150 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_151 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_152 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_58 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_159 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_160 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_161 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_61 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_65_typeTagIn = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_65_typeTagOut = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_195 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_196 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_197 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_74 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_198 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_199 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_200 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_75 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_83_sel_alu1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_276 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_277 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_T_278 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_setvcfg_uop_WIRE_102 = 2'h0; // @[Mux.scala:30:73] wire [4:0] io_imem_resp_0_bits_ctrl_alu_fn = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_0_bits_ctrl_mem_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_0_bits_fra1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_0_bits_fra2 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_0_bits_fra3 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_0_bits_fexc = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_ctrl_alu_fn = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_ctrl_mem_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_fra1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_fra2 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_fra3 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_resp_1_bits_fexc = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_ctrl_alu_fn = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_ctrl_mem_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_fra1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_fra2 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_fra3 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_0_bits_fexc = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_ctrl_alu_fn = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_ctrl_mem_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_fra1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_fra2 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_fra3 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_imem_peek_1_bits_fexc = 5'h0; // @[Core.scala:25:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[Core.scala:25:7] wire [4:0] rrd_uops_0_bits_fexc = 5'h0; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_fexc = 5'h0; // @[Core.scala:70:22] wire [4:0] _ex_setvcfg_uop_WIRE_bits_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_bits_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_bits_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_bits_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_bits_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_bits_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_ctrl_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_ctrl_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_fra1 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_fra2 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_fra3 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_1_fexc = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_78 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_79 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_80 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_29 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_81 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_82 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_83 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_30 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_84 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_85 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_86 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_31 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_87 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_88 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_89 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_32 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_83_alu_fn = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_83_mem_cmd = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_261 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_262 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_263 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_97 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_267 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_268 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_T_269 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_setvcfg_uop_WIRE_99 = 5'h0; // @[Mux.scala:30:73] wire [4:0] csr_fcsr_flags_3 = 5'h0; // @[Core.scala:1045:28] wire [63:0] io_imem_resp_0_bits_rs1_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_0_bits_rs2_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_0_bits_rs3_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_0_bits_wdata_bits = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_1_bits_rs1_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_1_bits_rs2_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_1_bits_rs3_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_resp_1_bits_wdata_bits = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_0_bits_rs1_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_0_bits_rs2_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_0_bits_rs3_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_0_bits_wdata_bits = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_1_bits_rs1_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_1_bits_rs2_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_1_bits_rs3_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_imem_peek_1_bits_wdata_bits = 64'h0; // @[Core.scala:25:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[Core.scala:25:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[Core.scala:25:7] wire [63:0] rrd_uops_0_bits_rs3_data = 64'h0; // @[Core.scala:70:22] wire [63:0] rrd_uops_0_bits_wdata_bits = 64'h0; // @[Core.scala:70:22] wire [63:0] rrd_uops_1_bits_rs3_data = 64'h0; // @[Core.scala:70:22] wire [63:0] rrd_uops_1_bits_wdata_bits = 64'h0; // @[Core.scala:70:22] wire [63:0] fp_mem_bypasses_0_data = 64'h0; // @[Core.scala:101:66] wire [63:0] fp_mem_bypasses_1_data = 64'h0; // @[Core.scala:101:66] wire [63:0] fp_com_bypasses_0_data = 64'h0; // @[Core.scala:102:66] wire [63:0] fp_com_bypasses_1_data = 64'h0; // @[Core.scala:102:66] wire [63:0] _ex_setvcfg_uop_WIRE_bits_xcpt_cause = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_bits_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_bits_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_bits_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_bits_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_1_xcpt_cause = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_1_rs1_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_1_rs2_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_1_rs3_data = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_1_wdata_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_33_bits = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_90 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_91 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_92 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_34 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_102 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_103 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_104 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_38 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_105 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_106 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_107 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_39 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_108 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_109 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_110 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_40 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_114 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_115 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_T_116 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_setvcfg_uop_WIRE_42 = 64'h0; // @[Mux.scala:30:73] wire [64:0] io_imem_resp_0_bits_fdivin_in1 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_resp_0_bits_fdivin_in2 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_resp_0_bits_fdivin_in3 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_resp_1_bits_fdivin_in1 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_resp_1_bits_fdivin_in2 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_resp_1_bits_fdivin_in3 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_0_bits_fdivin_in1 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_0_bits_fdivin_in2 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_0_bits_fdivin_in3 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_1_bits_fdivin_in1 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_1_bits_fdivin_in2 = 65'h0; // @[Core.scala:25:7] wire [64:0] io_imem_peek_1_bits_fdivin_in3 = 65'h0; // @[Core.scala:25:7] wire [64:0] rrd_uops_0_bits_fdivin_in1 = 65'h0; // @[Core.scala:70:22] wire [64:0] rrd_uops_0_bits_fdivin_in2 = 65'h0; // @[Core.scala:70:22] wire [64:0] rrd_uops_0_bits_fdivin_in3 = 65'h0; // @[Core.scala:70:22] wire [64:0] rrd_uops_1_bits_fdivin_in1 = 65'h0; // @[Core.scala:70:22] wire [64:0] rrd_uops_1_bits_fdivin_in2 = 65'h0; // @[Core.scala:70:22] wire [64:0] rrd_uops_1_bits_fdivin_in3 = 65'h0; // @[Core.scala:70:22] wire [64:0] _ex_setvcfg_uop_WIRE_bits_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_bits_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_bits_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_1_fdivin_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_1_fdivin_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_1_fdivin_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_4_in1 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_4_in2 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_4_in3 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_7 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_8 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_5 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_9 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_10 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_11 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_6 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_12 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_13 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_T_14 = 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_setvcfg_uop_WIRE_7 = 65'h0; // @[Mux.scala:30:73] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Core.scala:25:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Core.scala:25:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Core.scala:25:7] wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[Core.scala:25:7] wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[Core.scala:25:7] wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[Core.scala:25:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Core.scala:25:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Core.scala:25:7] wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[Core.scala:25:7] wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[Core.scala:25:7] wire [3:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_mask = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_mask = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_WIRE_51_bits_mask = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_WIRE_52_mask = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_T_153 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_T_154 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_T_155 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_setvcfg_uop_WIRE_59 = 4'h0; // @[Mux.scala:30:73] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Core.scala:25:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Core.scala:25:7] wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[Core.scala:25:7] wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[Core.scala:25:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[Core.scala:25:7] wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[Core.scala:25:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Core.scala:25:7] wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[Core.scala:25:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[Core.scala:25:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[Core.scala:25:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[Core.scala:25:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Core.scala:25:7] wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[Core.scala:25:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[Core.scala:25:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[Core.scala:25:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[Core.scala:25:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[Core.scala:25:7] wire [7:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_bht_history = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_bht_history = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_WIRE_51_bits_bht_history = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_WIRE_52_bht_history = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_WIRE_53_history = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_T_141 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_T_142 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_T_143 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_setvcfg_uop_WIRE_55 = 8'h0; // @[Mux.scala:30:73] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Core.scala:25:7] wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[Core.scala:25:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Core.scala:25:7] wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[Core.scala:25:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Core.scala:25:7] wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[Core.scala:25:7] wire [5:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_entry = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_entry = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_WIRE_51_bits_entry = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_WIRE_52_entry = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_T_144 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_T_145 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_T_146 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_setvcfg_uop_WIRE_56 = 6'h0; // @[Mux.scala:30:73] wire io_dmem_keep_clock_enabled = 1'h1; // @[Core.scala:25:7] wire io_dmem_clock_enabled = 1'h1; // @[Core.scala:25:7] wire io_ptw_gstatus_sd = 1'h1; // @[Core.scala:25:7] wire io_ptw_tlb_req_bits_valid = 1'h1; // @[Core.scala:25:7] wire io_ptw_tlb_gstatus_sd = 1'h1; // @[Core.scala:25:7] wire ll_bypass_0_can_bypass = 1'h1; // @[Core.scala:96:40] wire _fp_illegal_T = 1'h1; // @[Core.scala:233:68] wire _rrd_illegal_insn_0_T_5 = 1'h1; // @[Core.scala:247:53] wire _fp_illegal_T_2 = 1'h1; // @[Core.scala:233:68] wire _rrd_illegal_insn_1_T_5 = 1'h1; // @[Core.scala:247:53] wire _rrd_p0_can_forward_x_to_m_T_19 = 1'h1; // @[MicroOp.scala:77:120] wire _rs1_can_forward_from_x_p0_T_21 = 1'h1; // @[MicroOp.scala:77:120] wire _rs1_can_forward_from_x_p0_T_28 = 1'h1; // @[Core.scala:333:145] wire _rs2_can_forward_from_x_p0_T_21 = 1'h1; // @[MicroOp.scala:77:120] wire _rs2_can_forward_from_x_p0_T_28 = 1'h1; // @[Core.scala:334:145] wire _rs1_can_forward_from_w_p0_T_21 = 1'h1; // @[MicroOp.scala:77:120] wire _rs1_can_forward_from_w_p0_T_28 = 1'h1; // @[Core.scala:335:145] wire _rs2_can_forward_from_w_p0_T_21 = 1'h1; // @[MicroOp.scala:77:120] wire _rs2_can_forward_from_w_p0_T_28 = 1'h1; // @[Core.scala:336:145] wire _rrd_uops_0_bits_uses_memalu_T_19 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_uops_0_bits_uses_memalu_T_26 = 1'h1; // @[Core.scala:371:176] wire _rrd_uops_0_bits_uses_latealu_T_19 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_uops_0_bits_uses_latealu_T_26 = 1'h1; // @[Core.scala:372:178] wire _rs1_can_forward_from_x_p0_T_54 = 1'h1; // @[MicroOp.scala:77:120] wire _rs1_can_forward_from_x_p0_T_61 = 1'h1; // @[Core.scala:333:145] wire _rs2_can_forward_from_x_p0_T_54 = 1'h1; // @[MicroOp.scala:77:120] wire _rs2_can_forward_from_x_p0_T_61 = 1'h1; // @[Core.scala:334:145] wire _rs1_can_forward_from_w_p0_T_52 = 1'h1; // @[MicroOp.scala:77:120] wire _rs1_can_forward_from_w_p0_T_59 = 1'h1; // @[Core.scala:335:145] wire _rs2_can_forward_from_w_p0_T_52 = 1'h1; // @[MicroOp.scala:77:120] wire _rs2_can_forward_from_w_p0_T_59 = 1'h1; // @[Core.scala:336:145] wire _rd_same_hazard_T_21 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_uops_1_bits_uses_memalu_T_19 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_uops_1_bits_uses_latealu_T_19 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_rocc_stall_T_1 = 1'h1; // @[Core.scala:415:53] wire _is_pipe0_T_20 = 1'h1; // @[MicroOp.scala:77:120] wire _rrd_rocc_stall_T_3 = 1'h1; // @[Core.scala:415:53] wire _is_pipe0_T_79 = 1'h1; // @[MicroOp.scala:77:120] wire _mem_uops_reg_0_bits_wdata_valid_T_21 = 1'h1; // @[Core.scala:604:57] wire _mem_uops_reg_0_bits_wdata_valid_T_23 = 1'h1; // @[Core.scala:604:77] wire _ex_bypasses_0_can_bypass_T_21 = 1'h1; // @[Core.scala:612:50] wire _ex_bypasses_0_can_bypass_T_23 = 1'h1; // @[Core.scala:612:70] wire _ex_bypasses_0_can_bypass_T_25 = 1'h1; // @[Core.scala:612:91] wire _mem_brjmp_target_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _mem_brjmp_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:1343:43] wire _mem_brjmp_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:1343:36] wire _mem_brjmp_target_b11_T_6 = 1'h1; // @[RocketCore.scala:1346:23] wire _mem_brjmp_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:1349:41] wire _mem_brjmp_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:1349:34] wire _mem_brjmp_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26] wire _mem_brjmp_target_b11_T_14 = 1'h1; // @[RocketCore.scala:1345:23] wire _mem_bypasses_0_valid_T_1 = 1'h1; // @[Core.scala:798:88] wire _fp_mem_bypasses_0_valid_T_1 = 1'h1; // @[Core.scala:803:91] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _divSqrt_wdata_bits_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _divSqrt_wdata_bits_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire _com_retire_0_T_4 = 1'h1; // @[Core.scala:941:107] wire _csr_io_exception_T = 1'h1; // @[Core.scala:943:48] wire _fp_wdata_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _fp_wdata_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _fp_wdata_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _fp_wdata_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire [1:0] io_ptw_gstatus_fs = 2'h3; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_fs = 2'h3; // @[Core.scala:25:7] wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[Core.scala:25:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[Core.scala:25:7] wire [31:0] _ex_setvcfg_uop_WIRE_bits_inst = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_WIRE_bits_raw_inst = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_WIRE_1_inst = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_WIRE_1_raw_inst = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_312 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_313 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_314 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_WIRE_114 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_315 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_316 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_T_317 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_setvcfg_uop_WIRE_115 = 32'h0; // @[Mux.scala:30:73] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[Core.scala:25:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[Core.scala:25:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[Core.scala:25:7] wire [39:0] _ex_setvcfg_uop_WIRE_bits_pc = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_bits_next_pc_bits = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_1_pc = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_1_next_pc_bits = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_46_bits = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_126 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_127 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_128 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_47 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_309 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_310 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_T_311 = 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_setvcfg_uop_WIRE_113 = 40'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_WIRE_bits_btb_resp_bits_target = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_WIRE_1_btb_resp_bits_target = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_WIRE_51_bits_target = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_WIRE_52_target = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_T_147 = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_T_148 = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_T_149 = 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_setvcfg_uop_WIRE_57 = 39'h0; // @[Mux.scala:30:73] wire [1:0] io_ptw_status_sxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h2; // @[Core.scala:25:7] wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h2; // @[Core.scala:25:7] wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[Core.scala:25:7] wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[Core.scala:25:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[Core.scala:25:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[Core.scala:25:7] wire [4:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fp_wdata_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fp_wdata_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [64:0] _divSqrt_wdata_bits_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire [32:0] _divSqrt_wdata_bits_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[Core.scala:25:7] wire _io_imem_sfence_bits_rs1_T; // @[Core.scala:1125:59] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[Core.scala:25:7] wire _io_imem_sfence_bits_rs2_T; // @[Core.scala:1126:59] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[Core.scala:25:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[Core.scala:25:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[Core.scala:25:7] wire _io_imem_sfence_bits_hv_T; // @[Core.scala:1129:63] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[Core.scala:25:7] wire _io_imem_sfence_bits_hg_T; // @[Core.scala:1130:63] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[Core.scala:25:7] wire _io_imem_resp_0_ready_T; // @[Core.scala:275:30] wire rrd_uops_0_valid = io_imem_resp_0_valid_0; // @[Core.scala:25:7, :70:22] wire [31:0] rrd_uops_0_bits_inst = io_imem_resp_0_bits_inst_0; // @[Core.scala:25:7, :70:22] wire [31:0] decoder_decoded_plaInput = io_imem_resp_0_bits_inst_0; // @[pla.scala:77:22] wire [31:0] rrd_uops_0_bits_raw_inst = io_imem_resp_0_bits_raw_inst_0; // @[Core.scala:25:7, :70:22] wire [39:0] rrd_uops_0_bits_pc = io_imem_resp_0_bits_pc_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_edge_inst = io_imem_resp_0_bits_edge_inst_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_rvc = io_imem_resp_0_bits_rvc_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_btb_resp_valid = io_imem_resp_0_bits_btb_resp_valid_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_0_bits_btb_resp_bits_cfiType = io_imem_resp_0_bits_btb_resp_bits_cfiType_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_btb_resp_bits_taken = io_imem_resp_0_bits_btb_resp_bits_taken_0; // @[Core.scala:25:7, :70:22] wire [3:0] rrd_uops_0_bits_btb_resp_bits_mask = io_imem_resp_0_bits_btb_resp_bits_mask_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_0_bits_btb_resp_bits_bridx = io_imem_resp_0_bits_btb_resp_bits_bridx_0; // @[Core.scala:25:7, :70:22] wire [38:0] rrd_uops_0_bits_btb_resp_bits_target = io_imem_resp_0_bits_btb_resp_bits_target_0; // @[Core.scala:25:7, :70:22] wire [5:0] rrd_uops_0_bits_btb_resp_bits_entry = io_imem_resp_0_bits_btb_resp_bits_entry_0; // @[Core.scala:25:7, :70:22] wire [7:0] rrd_uops_0_bits_btb_resp_bits_bht_history = io_imem_resp_0_bits_btb_resp_bits_bht_history_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_0_bits_btb_resp_bits_bht_value = io_imem_resp_0_bits_btb_resp_bits_bht_value_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_sfb_br = io_imem_resp_0_bits_sfb_br_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_0_bits_next_pc_valid = io_imem_resp_0_bits_next_pc_valid_0; // @[Core.scala:25:7, :70:22] wire [39:0] rrd_uops_0_bits_next_pc_bits = io_imem_resp_0_bits_next_pc_bits_0; // @[Core.scala:25:7, :70:22] wire [2:0] rrd_uops_0_bits_ras_head = io_imem_resp_0_bits_ras_head_0; // @[Core.scala:25:7, :70:22] wire _io_imem_resp_1_ready_T; // @[Core.scala:275:30] wire rrd_uops_1_valid = io_imem_resp_1_valid_0; // @[Core.scala:25:7, :70:22] wire [31:0] rrd_uops_1_bits_inst = io_imem_resp_1_bits_inst_0; // @[Core.scala:25:7, :70:22] wire [31:0] decoder_decoded_plaInput_1 = io_imem_resp_1_bits_inst_0; // @[pla.scala:77:22] wire [31:0] rrd_uops_1_bits_raw_inst = io_imem_resp_1_bits_raw_inst_0; // @[Core.scala:25:7, :70:22] wire [39:0] rrd_uops_1_bits_pc = io_imem_resp_1_bits_pc_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_edge_inst = io_imem_resp_1_bits_edge_inst_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_rvc = io_imem_resp_1_bits_rvc_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_btb_resp_valid = io_imem_resp_1_bits_btb_resp_valid_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_1_bits_btb_resp_bits_cfiType = io_imem_resp_1_bits_btb_resp_bits_cfiType_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_btb_resp_bits_taken = io_imem_resp_1_bits_btb_resp_bits_taken_0; // @[Core.scala:25:7, :70:22] wire [3:0] rrd_uops_1_bits_btb_resp_bits_mask = io_imem_resp_1_bits_btb_resp_bits_mask_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_1_bits_btb_resp_bits_bridx = io_imem_resp_1_bits_btb_resp_bits_bridx_0; // @[Core.scala:25:7, :70:22] wire [38:0] rrd_uops_1_bits_btb_resp_bits_target = io_imem_resp_1_bits_btb_resp_bits_target_0; // @[Core.scala:25:7, :70:22] wire [5:0] rrd_uops_1_bits_btb_resp_bits_entry = io_imem_resp_1_bits_btb_resp_bits_entry_0; // @[Core.scala:25:7, :70:22] wire [7:0] rrd_uops_1_bits_btb_resp_bits_bht_history = io_imem_resp_1_bits_btb_resp_bits_bht_history_0; // @[Core.scala:25:7, :70:22] wire [1:0] rrd_uops_1_bits_btb_resp_bits_bht_value = io_imem_resp_1_bits_btb_resp_bits_bht_value_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_sfb_br = io_imem_resp_1_bits_sfb_br_0; // @[Core.scala:25:7, :70:22] wire rrd_uops_1_bits_next_pc_valid = io_imem_resp_1_bits_next_pc_valid_0; // @[Core.scala:25:7, :70:22] wire [39:0] rrd_uops_1_bits_next_pc_bits = io_imem_resp_1_bits_next_pc_bits_0; // @[Core.scala:25:7, :70:22] wire [2:0] rrd_uops_1_bits_ras_head = io_imem_resp_1_bits_ras_head_0; // @[Core.scala:25:7, :70:22] wire _io_imem_btb_update_valid_T_1; // @[Core.scala:661:45] wire [1:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[Core.scala:674:34] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[Core.scala:25:7] wire mem_brjmp_val; // @[Core.scala:642:44] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[Core.scala:665:8] wire mem_brjmp_mispredict; // @[Core.scala:658:57] wire _io_imem_bht_update_valid_T_1; // @[Core.scala:681:45] wire _mem_brjmp_uop_WIRE_bits_ctrl_branch; // @[Mux.scala:30:73] wire mem_brjmp_taken; // @[Core.scala:655:95] wire _io_imem_ras_update_valid_T; // @[Core.scala:688:46] wire [2:0] _io_imem_ras_update_bits_head_T_3; // @[Core.scala:689:38] wire _io_dmem_req_valid_T_2; // @[Core.scala:546:48] wire [39:0] _io_dmem_req_bits_addr_WIRE; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_ctrl_mem_cmd; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_mem_size; // @[Mux.scala:30:73] wire _io_dmem_req_bits_signed_T_1; // @[Core.scala:551:30] wire io_imem_resp_0_ready_0; // @[Core.scala:25:7] wire io_imem_resp_1_ready_0; // @[Core.scala:25:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[Core.scala:25:7] wire [1:0] io_imem_btb_update_bits_prediction_bht_value_0; // @[Core.scala:25:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[Core.scala:25:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[Core.scala:25:7] wire [3:0] io_imem_btb_update_bits_prediction_mask_0; // @[Core.scala:25:7] wire [1:0] io_imem_btb_update_bits_prediction_bridx_0; // @[Core.scala:25:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[Core.scala:25:7] wire [5:0] io_imem_btb_update_bits_prediction_entry_0; // @[Core.scala:25:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[Core.scala:25:7] wire io_imem_btb_update_bits_isValid_0; // @[Core.scala:25:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[Core.scala:25:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[Core.scala:25:7] wire io_imem_btb_update_bits_mispredict_0; // @[Core.scala:25:7] wire io_imem_btb_update_valid_0; // @[Core.scala:25:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[Core.scala:25:7] wire [1:0] io_imem_bht_update_bits_prediction_value_0; // @[Core.scala:25:7] wire io_imem_bht_update_bits_branch_0; // @[Core.scala:25:7] wire io_imem_bht_update_bits_taken_0; // @[Core.scala:25:7] wire io_imem_bht_update_bits_mispredict_0; // @[Core.scala:25:7] wire io_imem_bht_update_valid_0; // @[Core.scala:25:7] wire [2:0] io_imem_ras_update_bits_head_0; // @[Core.scala:25:7] wire [39:0] io_imem_ras_update_bits_addr_0; // @[Core.scala:25:7] wire io_imem_ras_update_valid_0; // @[Core.scala:25:7] wire io_imem_redirect_flush_0; // @[Core.scala:25:7] wire io_imem_redirect_val_0; // @[Core.scala:25:7] wire [39:0] io_imem_redirect_pc_0; // @[Core.scala:25:7] wire [2:0] io_imem_redirect_ras_head_0; // @[Core.scala:25:7] wire io_imem_flush_icache_0; // @[Core.scala:25:7] wire [39:0] io_dmem_req_bits_addr_0; // @[Core.scala:25:7] wire [6:0] io_dmem_req_bits_tag_0; // @[Core.scala:25:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[Core.scala:25:7] wire [1:0] io_dmem_req_bits_size_0; // @[Core.scala:25:7] wire io_dmem_req_bits_signed_0; // @[Core.scala:25:7] wire io_dmem_req_valid_0; // @[Core.scala:25:7] wire [63:0] io_dmem_s1_data_data_0; // @[Core.scala:25:7] wire [31:0] io_dmem_s1_paddr_0; // @[Core.scala:25:7] wire io_dmem_s1_kill_0; // @[Core.scala:25:7] wire io_dmem_s2_kill_0; // @[Core.scala:25:7] wire [3:0] io_ptw_ptbr_mode_0; // @[Core.scala:25:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[Core.scala:25:7] wire io_ptw_status_debug_0; // @[Core.scala:25:7] wire io_ptw_status_cease_0; // @[Core.scala:25:7] wire io_ptw_status_wfi_0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_dprv_0; // @[Core.scala:25:7] wire io_ptw_status_dv_0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_prv_0; // @[Core.scala:25:7] wire io_ptw_status_v_0; // @[Core.scala:25:7] wire io_ptw_status_sd_0; // @[Core.scala:25:7] wire io_ptw_status_mpv_0; // @[Core.scala:25:7] wire io_ptw_status_gva_0; // @[Core.scala:25:7] wire io_ptw_status_tsr_0; // @[Core.scala:25:7] wire io_ptw_status_tw_0; // @[Core.scala:25:7] wire io_ptw_status_tvm_0; // @[Core.scala:25:7] wire io_ptw_status_mxr_0; // @[Core.scala:25:7] wire io_ptw_status_sum_0; // @[Core.scala:25:7] wire io_ptw_status_mprv_0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_fs_0; // @[Core.scala:25:7] wire [1:0] io_ptw_status_mpp_0; // @[Core.scala:25:7] wire io_ptw_status_spp_0; // @[Core.scala:25:7] wire io_ptw_status_mpie_0; // @[Core.scala:25:7] wire io_ptw_status_spie_0; // @[Core.scala:25:7] wire io_ptw_status_mie_0; // @[Core.scala:25:7] wire io_ptw_status_sie_0; // @[Core.scala:25:7] wire io_ptw_hstatus_spvp_0; // @[Core.scala:25:7] wire io_ptw_hstatus_spv_0; // @[Core.scala:25:7] wire io_ptw_hstatus_gva_0; // @[Core.scala:25:7] wire io_ptw_gstatus_debug_0; // @[Core.scala:25:7] wire io_ptw_gstatus_cease_0; // @[Core.scala:25:7] wire io_ptw_gstatus_wfi_0; // @[Core.scala:25:7] wire [31:0] io_ptw_gstatus_isa_0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[Core.scala:25:7] wire io_ptw_gstatus_dv_0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_prv_0; // @[Core.scala:25:7] wire io_ptw_gstatus_v_0; // @[Core.scala:25:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mpv_0; // @[Core.scala:25:7] wire io_ptw_gstatus_gva_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mbe_0; // @[Core.scala:25:7] wire io_ptw_gstatus_sbe_0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[Core.scala:25:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[Core.scala:25:7] wire io_ptw_gstatus_tsr_0; // @[Core.scala:25:7] wire io_ptw_gstatus_tw_0; // @[Core.scala:25:7] wire io_ptw_gstatus_tvm_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mxr_0; // @[Core.scala:25:7] wire io_ptw_gstatus_sum_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mprv_0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[Core.scala:25:7] wire [1:0] io_ptw_gstatus_vs_0; // @[Core.scala:25:7] wire io_ptw_gstatus_spp_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mpie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_ube_0; // @[Core.scala:25:7] wire io_ptw_gstatus_spie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_upie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_mie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_hie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_sie_0; // @[Core.scala:25:7] wire io_ptw_gstatus_uie_0; // @[Core.scala:25:7] wire [26:0] io_ptw_tlb_req_bits_bits_addr_0; // @[Core.scala:25:7] wire io_ptw_tlb_req_valid_0; // @[Core.scala:25:7] wire io_rocc_resp_ready; // @[Core.scala:25:7] wire io_trace_insns_0_valid_0; // @[Core.scala:25:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[Core.scala:25:7] wire [31:0] io_trace_insns_0_insn_0; // @[Core.scala:25:7] wire [2:0] io_trace_insns_0_priv_0; // @[Core.scala:25:7] wire io_trace_insns_0_exception_0; // @[Core.scala:25:7] wire io_trace_insns_0_interrupt_0; // @[Core.scala:25:7] wire [63:0] io_trace_insns_0_cause_0; // @[Core.scala:25:7] wire [39:0] io_trace_insns_0_tval_0; // @[Core.scala:25:7] wire io_trace_insns_1_valid_0; // @[Core.scala:25:7] wire [39:0] io_trace_insns_1_iaddr_0; // @[Core.scala:25:7] wire [31:0] io_trace_insns_1_insn_0; // @[Core.scala:25:7] wire [2:0] io_trace_insns_1_priv_0; // @[Core.scala:25:7] wire io_trace_insns_1_exception_0; // @[Core.scala:25:7] wire io_trace_insns_1_interrupt_0; // @[Core.scala:25:7] wire [63:0] io_trace_insns_1_cause_0; // @[Core.scala:25:7] wire [39:0] io_trace_insns_1_tval_0; // @[Core.scala:25:7] wire [63:0] io_trace_time_0; // @[Core.scala:25:7] wire [2:0] io_fcsr_rm; // @[Core.scala:25:7] reg [63:0] debug_tsc_reg; // @[Core.scala:44:30] wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[Core.scala:44:30, :45:34] wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[Core.scala:45:34] reg [63:0] debug_irt_reg; // @[Core.scala:47:30] wire decoder_0; // @[Decode.scala:50:77] wire decoder_1; // @[Decode.scala:50:77] wire decoder_2; // @[Decode.scala:50:77] wire decoder_3; // @[Decode.scala:50:77] wire _rrd_illegal_insn_0_T_3 = rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22, :246:18] wire _rrd_rocc_stall_T = rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22, :415:37] wire decoder_4; // @[Decode.scala:50:77] wire decoder_5; // @[Decode.scala:50:77] wire decoder_6; // @[Decode.scala:50:77] wire decoder_7; // @[Decode.scala:50:77] wire [2:0] decoder_10; // @[Decode.scala:50:77] wire decoder_13; // @[Decode.scala:50:77] wire [4:0] decoder_14; // @[Decode.scala:50:77] wire decoder_15; // @[Decode.scala:50:77] wire decoder_16; // @[Decode.scala:50:77] wire decoder_17; // @[Decode.scala:50:77] wire decoder_18; // @[Decode.scala:50:77] wire decoder_19; // @[Decode.scala:50:77] wire decoder_20; // @[Decode.scala:50:77] wire decoder_21; // @[Decode.scala:50:77] wire [2:0] decoder_22; // @[Decode.scala:50:77] wire decoder_23; // @[Decode.scala:50:77] wire decoder_24; // @[Decode.scala:50:77] wire decoder_25; // @[Decode.scala:50:77] wire decoder_26; // @[Decode.scala:50:77] wire sfb_shadow_1 = rrd_uops_0_bits_sfb_br; // @[Core.scala:70:22, :317:33] wire xcpt; // @[Core.scala:60:26] wire [63:0] cause; // @[Mux.scala:50:70] wire [63:0] _rrd_uops_0_bits_rs2_data_T_1; // @[Core.scala:326:37] wire _rrd_uops_0_bits_flush_pipe_T_2; // @[Core.scala:242:58] wire decoder_0_1; // @[Decode.scala:50:77] wire decoder_1_1; // @[Decode.scala:50:77] wire decoder_2_1; // @[Decode.scala:50:77] wire decoder_3_1; // @[Decode.scala:50:77] wire _rrd_illegal_insn_1_T_3 = rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22, :246:18] wire decoder_4_1; // @[Decode.scala:50:77] wire decoder_5_1; // @[Decode.scala:50:77] wire decoder_6_1; // @[Decode.scala:50:77] wire decoder_7_1; // @[Decode.scala:50:77] wire [2:0] decoder_10_1; // @[Decode.scala:50:77] wire decoder_13_1; // @[Decode.scala:50:77] wire [4:0] decoder_14_1; // @[Decode.scala:50:77] wire decoder_15_1; // @[Decode.scala:50:77] wire decoder_16_1; // @[Decode.scala:50:77] wire decoder_17_1; // @[Decode.scala:50:77] wire decoder_18_1; // @[Decode.scala:50:77] wire decoder_19_1; // @[Decode.scala:50:77] wire decoder_20_1; // @[Decode.scala:50:77] wire decoder_21_1; // @[Decode.scala:50:77] wire [2:0] decoder_22_1; // @[Decode.scala:50:77] wire decoder_23_1; // @[Decode.scala:50:77] wire decoder_24_1; // @[Decode.scala:50:77] wire decoder_25_1; // @[Decode.scala:50:77] wire decoder_26_1; // @[Decode.scala:50:77] wire xcpt_1; // @[Core.scala:60:26] wire [63:0] cause_1; // @[Mux.scala:50:70] wire [63:0] _rrd_uops_1_bits_rs2_data_T_1; // @[Core.scala:326:37] wire _rrd_uops_1_bits_uses_memalu_T_27; // @[Core.scala:371:173] wire _rrd_uops_1_bits_uses_latealu_T_27; // @[Core.scala:372:175] wire _rrd_uops_1_bits_flush_pipe_T_2; // @[Core.scala:242:58] wire rrd_uops_0_bits_ctrl_legal; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_branch; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_jal; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rxs2; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rxs1; // @[Core.scala:70:22] wire [2:0] rrd_uops_0_bits_ctrl_sel_alu2; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_ctrl_sel_alu1; // @[Core.scala:70:22] wire [2:0] rrd_uops_0_bits_ctrl_sel_imm; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_alu_dw; // @[Core.scala:70:22] wire [4:0] rrd_uops_0_bits_ctrl_alu_fn; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire [4:0] rrd_uops_0_bits_ctrl_mem_cmd; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rfs1; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rfs2; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_rfs3; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_wfd; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_wxd; // @[Core.scala:70:22] wire [2:0] rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_fence_i; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_fence; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_amo; // @[Core.scala:70:22] wire rrd_uops_0_bits_ctrl_dp; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_ldst; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_wen; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_ren1; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_ren2; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_ren3; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_swap12; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_swap23; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_fromint; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_toint; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_fastpipe; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_fma; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_div; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_sqrt; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_wflags; // @[Core.scala:70:22] wire rrd_uops_0_bits_fp_ctrl_vec; // @[Core.scala:70:22] wire rrd_uops_0_bits_xcpt; // @[Core.scala:70:22] wire [63:0] rrd_uops_0_bits_xcpt_cause; // @[Core.scala:70:22] wire [63:0] rrd_uops_0_bits_rs1_data; // @[Core.scala:70:22] wire [63:0] rrd_uops_0_bits_rs2_data; // @[Core.scala:70:22] wire [4:0] rrd_uops_0_bits_fra1; // @[Core.scala:70:22] wire [4:0] rrd_uops_0_bits_fra2; // @[Core.scala:70:22] wire [4:0] rrd_uops_0_bits_fra3; // @[Core.scala:70:22] wire [1:0] rrd_uops_0_bits_mem_size; // @[Core.scala:70:22] wire rrd_uops_0_bits_flush_pipe; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_legal; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_branch; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_jal; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_rxs2; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_rxs1; // @[Core.scala:70:22] wire [2:0] rrd_uops_1_bits_ctrl_sel_alu2; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_ctrl_sel_alu1; // @[Core.scala:70:22] wire [2:0] rrd_uops_1_bits_ctrl_sel_imm; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_alu_dw; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_ctrl_alu_fn; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_ctrl_mem_cmd; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_rfs1; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_rfs2; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_rfs3; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_wfd; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_wxd; // @[Core.scala:70:22] wire [2:0] rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_fence_i; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_fence; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_amo; // @[Core.scala:70:22] wire rrd_uops_1_bits_ctrl_dp; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_ldst; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_wen; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_ren1; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_ren2; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_ren3; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_swap12; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_swap23; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_fromint; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_toint; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_fastpipe; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_fma; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_div; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_sqrt; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_wflags; // @[Core.scala:70:22] wire rrd_uops_1_bits_fp_ctrl_vec; // @[Core.scala:70:22] wire rrd_uops_1_bits_sfb_shadow; // @[Core.scala:70:22] wire rrd_uops_1_bits_xcpt; // @[Core.scala:70:22] wire [63:0] rrd_uops_1_bits_xcpt_cause; // @[Core.scala:70:22] wire [63:0] rrd_uops_1_bits_rs1_data; // @[Core.scala:70:22] wire [63:0] rrd_uops_1_bits_rs2_data; // @[Core.scala:70:22] wire rrd_uops_1_bits_uses_memalu; // @[Core.scala:70:22] wire rrd_uops_1_bits_uses_latealu; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_fra1; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_fra2; // @[Core.scala:70:22] wire [4:0] rrd_uops_1_bits_fra3; // @[Core.scala:70:22] wire [1:0] rrd_uops_1_bits_mem_size; // @[Core.scala:70:22] wire rrd_uops_1_bits_flush_pipe; // @[Core.scala:70:22] reg ex_uops_reg_0_valid; // @[Core.scala:71:24] reg [31:0] ex_uops_reg_0_bits_inst; // @[Core.scala:71:24] reg [31:0] ex_uops_reg_0_bits_raw_inst; // @[Core.scala:71:24] reg [39:0] ex_uops_reg_0_bits_pc; // @[Core.scala:71:24] wire [39:0] _ex_op1_T_1 = ex_uops_reg_0_bits_pc; // @[Core.scala:71:24, :587:23] reg ex_uops_reg_0_bits_edge_inst; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_legal; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_fp; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_branch; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_jal; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:71:24] wire [2:0] sel_alu2 = ex_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:71:24, :584:28] reg [1:0] ex_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:71:24] wire [1:0] sel_alu1 = ex_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:71:24, :583:28] reg [2:0] ex_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_mem; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_mul; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_div; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_0_bits_ctrl_csr; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_fence; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_amo; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_dp; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_ctrl_vec; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_rvc; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:71:24] reg [3:0] ex_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:71:24] reg [38:0] ex_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:71:24] reg [5:0] ex_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:71:24] reg [7:0] ex_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_sfb_br; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_next_pc_valid; // @[Core.scala:71:24] reg [39:0] ex_uops_reg_0_bits_next_pc_bits; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_0_bits_ras_head; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_taken; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_xcpt; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_0_bits_xcpt_cause; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_needs_replay; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_0_bits_rs1_data; // @[Core.scala:71:24] wire [63:0] _ex_op1_T = ex_uops_reg_0_bits_rs1_data; // @[Core.scala:71:24, :586:30] wire [63:0] _ex_dmem_addrs_0_a_T = ex_uops_reg_0_bits_rs1_data; // @[Core.scala:65:16, :71:24] reg [63:0] ex_uops_reg_0_bits_rs2_data; // @[Core.scala:71:24] wire [63:0] _ex_op2_T = ex_uops_reg_0_bits_rs2_data; // @[Core.scala:71:24, :592:30] reg [63:0] ex_uops_reg_0_bits_rs3_data; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_wdata_valid; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_0_bits_wdata_bits; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_fra1; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_fra2; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_fra3; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_0_bits_fexc; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_wen; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_toint; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_fma; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_div; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_fdivin_vec; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_0_bits_fdivin_rm; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fdivin_typ; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_0_bits_fdivin_in1; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_0_bits_fdivin_in2; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_0_bits_fdivin_in3; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_0_bits_mem_size; // @[Core.scala:71:24] reg ex_uops_reg_0_bits_flush_pipe; // @[Core.scala:71:24] reg ex_uops_reg_1_valid; // @[Core.scala:71:24] reg [31:0] ex_uops_reg_1_bits_inst; // @[Core.scala:71:24] reg [31:0] ex_uops_reg_1_bits_raw_inst; // @[Core.scala:71:24] reg [39:0] ex_uops_reg_1_bits_pc; // @[Core.scala:71:24] wire [39:0] _ex_op1_T_14 = ex_uops_reg_1_bits_pc; // @[Core.scala:71:24, :587:23] reg ex_uops_reg_1_bits_edge_inst; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_legal; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_fp; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_branch; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_jal; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:71:24] wire [2:0] sel_alu2_1 = ex_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:71:24, :584:28] reg [1:0] ex_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:71:24] wire [1:0] sel_alu1_1 = ex_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:71:24, :583:28] reg [2:0] ex_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_mem; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_mul; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_div; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_1_bits_ctrl_csr; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_fence; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_amo; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_dp; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_ctrl_vec; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_rvc; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:71:24] reg [3:0] ex_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:71:24] reg [38:0] ex_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:71:24] reg [5:0] ex_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:71:24] reg [7:0] ex_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_sfb_br; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_sfb_shadow; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_next_pc_valid; // @[Core.scala:71:24] reg [39:0] ex_uops_reg_1_bits_next_pc_bits; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_1_bits_ras_head; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_taken; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_xcpt; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_1_bits_xcpt_cause; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_needs_replay; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_1_bits_rs1_data; // @[Core.scala:71:24] wire [63:0] _ex_op1_T_13 = ex_uops_reg_1_bits_rs1_data; // @[Core.scala:71:24, :586:30] wire [63:0] _ex_dmem_addrs_1_a_T = ex_uops_reg_1_bits_rs1_data; // @[Core.scala:65:16, :71:24] reg [63:0] ex_uops_reg_1_bits_rs2_data; // @[Core.scala:71:24] wire [63:0] _ex_op2_T_11 = ex_uops_reg_1_bits_rs2_data; // @[Core.scala:71:24, :592:30] reg [63:0] ex_uops_reg_1_bits_rs3_data; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_uses_memalu; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_uses_latealu; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_wdata_valid; // @[Core.scala:71:24] reg [63:0] ex_uops_reg_1_bits_wdata_bits; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_fra1; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_fra2; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_fra3; // @[Core.scala:71:24] reg [4:0] ex_uops_reg_1_bits_fexc; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_wen; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_toint; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_fma; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_div; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_fdivin_vec; // @[Core.scala:71:24] reg [2:0] ex_uops_reg_1_bits_fdivin_rm; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fdivin_typ; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_1_bits_fdivin_in1; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_1_bits_fdivin_in2; // @[Core.scala:71:24] reg [64:0] ex_uops_reg_1_bits_fdivin_in3; // @[Core.scala:71:24] reg [1:0] ex_uops_reg_1_bits_mem_size; // @[Core.scala:71:24] reg ex_uops_reg_1_bits_flush_pipe; // @[Core.scala:71:24] reg mem_uops_reg_0_valid; // @[Core.scala:72:25] reg [31:0] mem_uops_reg_0_bits_inst; // @[Core.scala:72:25] reg [31:0] mem_uops_reg_0_bits_raw_inst; // @[Core.scala:72:25] reg [39:0] mem_uops_reg_0_bits_pc; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_edge_inst; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_legal; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_fp; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_branch; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_jal; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_mem; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_mul; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_div; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_0_bits_ctrl_csr; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_fence; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_amo; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_dp; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_ctrl_vec; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_rvc; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_sets_vcfg; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:72:25] reg [3:0] mem_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:72:25] reg [38:0] mem_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:72:25] reg [5:0] mem_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:72:25] reg [7:0] mem_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_sfb_br; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_sfb_shadow; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_next_pc_valid; // @[Core.scala:72:25] reg [39:0] mem_uops_reg_0_bits_next_pc_bits; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_0_bits_ras_head; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_taken; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_xcpt; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_0_bits_xcpt_cause; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_needs_replay; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_0_bits_rs1_data; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_0_bits_rs2_data; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_0_bits_rs3_data; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_uses_memalu; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_uses_latealu; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_wdata_valid; // @[Core.scala:72:25] wire mem_bypasses_0_can_bypass = mem_uops_reg_0_bits_wdata_valid; // @[Core.scala:72:25, :93:63] reg [63:0] mem_uops_reg_0_bits_wdata_bits; // @[Core.scala:72:25] wire [63:0] mem_bypasses_0_data = mem_uops_reg_0_bits_wdata_bits; // @[Core.scala:72:25, :93:63] reg [4:0] mem_uops_reg_0_bits_fra1; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_0_bits_fra2; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_0_bits_fra3; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_0_bits_fexc; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_wen; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_toint; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_fma; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_div; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_fdivin_vec; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_0_bits_fdivin_rm; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fdivin_typ; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_0_bits_fdivin_in1; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_0_bits_fdivin_in2; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_0_bits_fdivin_in3; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_0_bits_mem_size; // @[Core.scala:72:25] reg mem_uops_reg_0_bits_flush_pipe; // @[Core.scala:72:25] reg mem_uops_reg_1_valid; // @[Core.scala:72:25] reg [31:0] mem_uops_reg_1_bits_inst; // @[Core.scala:72:25] reg [31:0] mem_uops_reg_1_bits_raw_inst; // @[Core.scala:72:25] reg [39:0] mem_uops_reg_1_bits_pc; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_edge_inst; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_legal; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_fp; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_branch; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_jal; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_mem; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_mul; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_div; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_1_bits_ctrl_csr; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_fence; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_amo; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_dp; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_ctrl_vec; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_rvc; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_sets_vcfg; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:72:25] reg [3:0] mem_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:72:25] reg [38:0] mem_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:72:25] reg [5:0] mem_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:72:25] reg [7:0] mem_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_sfb_br; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_sfb_shadow; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_next_pc_valid; // @[Core.scala:72:25] reg [39:0] mem_uops_reg_1_bits_next_pc_bits; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_1_bits_ras_head; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_taken; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_xcpt; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_1_bits_xcpt_cause; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_needs_replay; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_1_bits_rs1_data; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_1_bits_rs2_data; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_1_bits_rs3_data; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_uses_memalu; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_uses_latealu; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_wdata_valid; // @[Core.scala:72:25] reg [63:0] mem_uops_reg_1_bits_wdata_bits; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_fra1; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_fra2; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_fra3; // @[Core.scala:72:25] reg [4:0] mem_uops_reg_1_bits_fexc; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_wen; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_toint; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_fma; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_div; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_fdivin_vec; // @[Core.scala:72:25] reg [2:0] mem_uops_reg_1_bits_fdivin_rm; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fdivin_typ; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_1_bits_fdivin_in1; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_1_bits_fdivin_in2; // @[Core.scala:72:25] reg [64:0] mem_uops_reg_1_bits_fdivin_in3; // @[Core.scala:72:25] reg [1:0] mem_uops_reg_1_bits_mem_size; // @[Core.scala:72:25] reg mem_uops_reg_1_bits_flush_pipe; // @[Core.scala:72:25] reg com_uops_reg_0_valid; // @[Core.scala:73:25] wire com_uops_0_valid = com_uops_reg_0_valid; // @[Core.scala:73:25, :74:26] wire _csr_io_exception_T_1 = com_uops_reg_0_valid; // @[Core.scala:73:25, :943:45] reg [31:0] com_uops_reg_0_bits_inst; // @[Core.scala:73:25] wire [31:0] com_uops_0_bits_inst = com_uops_reg_0_bits_inst; // @[Core.scala:73:25, :74:26] reg [31:0] com_uops_reg_0_bits_raw_inst; // @[Core.scala:73:25] wire [31:0] com_uops_0_bits_raw_inst = com_uops_reg_0_bits_raw_inst; // @[Core.scala:73:25, :74:26] reg [39:0] com_uops_reg_0_bits_pc; // @[Core.scala:73:25] wire [39:0] com_uops_0_bits_pc = com_uops_reg_0_bits_pc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_edge_inst; // @[Core.scala:73:25] wire com_uops_0_bits_edge_inst = com_uops_reg_0_bits_edge_inst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_legal; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_legal = com_uops_reg_0_bits_ctrl_legal; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_fp; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_fp = com_uops_reg_0_bits_ctrl_fp; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rocc = com_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_branch; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_branch = com_uops_reg_0_bits_ctrl_branch; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_jal; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_jal = com_uops_reg_0_bits_ctrl_jal; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_jalr = com_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rxs2 = com_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rxs1 = com_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:73:25] wire [2:0] com_uops_0_bits_ctrl_sel_alu2 = com_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_ctrl_sel_alu1 = com_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:73:25] wire [2:0] com_uops_0_bits_ctrl_sel_imm = com_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_alu_dw = com_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_ctrl_alu_fn = com_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_mem; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_mem = com_uops_reg_0_bits_ctrl_mem; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_ctrl_mem_cmd = com_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rfs1 = com_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rfs2 = com_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_rfs3 = com_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_wfd = com_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_mul; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_mul = com_uops_reg_0_bits_ctrl_mul; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_div; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_div = com_uops_reg_0_bits_ctrl_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_wxd = com_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_0_bits_ctrl_csr; // @[Core.scala:73:25] wire [2:0] com_uops_0_bits_ctrl_csr = com_uops_reg_0_bits_ctrl_csr; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_fence_i = com_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_fence; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_fence = com_uops_reg_0_bits_ctrl_fence; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_amo; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_amo = com_uops_reg_0_bits_ctrl_amo; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_dp; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_dp = com_uops_reg_0_bits_ctrl_dp; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_ctrl_vec; // @[Core.scala:73:25] wire com_uops_0_bits_ctrl_vec = com_uops_reg_0_bits_ctrl_vec; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_ldst = com_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_wen = com_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_ren1 = com_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_ren2 = com_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_ren3 = com_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_swap12 = com_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_swap23 = com_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fp_ctrl_typeTagIn = com_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fp_ctrl_typeTagOut = com_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_fromint = com_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_toint = com_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_fastpipe = com_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_fma = com_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_div = com_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_sqrt = com_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_wflags = com_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:73:25] wire com_uops_0_bits_fp_ctrl_vec = com_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_rvc; // @[Core.scala:73:25] wire com_uops_0_bits_rvc = com_uops_reg_0_bits_rvc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_sets_vcfg; // @[Core.scala:73:25] wire com_uops_0_bits_sets_vcfg = com_uops_reg_0_bits_sets_vcfg; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:73:25] wire com_uops_0_bits_btb_resp_valid = com_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_btb_resp_bits_cfiType = com_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:73:25] wire com_uops_0_bits_btb_resp_bits_taken = com_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:73:25, :74:26] reg [3:0] com_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:73:25] wire [3:0] com_uops_0_bits_btb_resp_bits_mask = com_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_btb_resp_bits_bridx = com_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:73:25, :74:26] reg [38:0] com_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:73:25] wire [38:0] com_uops_0_bits_btb_resp_bits_target = com_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:73:25, :74:26] reg [5:0] com_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:73:25] wire [5:0] com_uops_0_bits_btb_resp_bits_entry = com_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:73:25, :74:26] reg [7:0] com_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:73:25] wire [7:0] com_uops_0_bits_btb_resp_bits_bht_history = com_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_btb_resp_bits_bht_value = com_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_sfb_br; // @[Core.scala:73:25] wire com_uops_0_bits_sfb_br = com_uops_reg_0_bits_sfb_br; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_sfb_shadow; // @[Core.scala:73:25] wire com_uops_0_bits_sfb_shadow = com_uops_reg_0_bits_sfb_shadow; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_next_pc_valid; // @[Core.scala:73:25] wire com_uops_0_bits_next_pc_valid = com_uops_reg_0_bits_next_pc_valid; // @[Core.scala:73:25, :74:26] reg [39:0] com_uops_reg_0_bits_next_pc_bits; // @[Core.scala:73:25] wire [39:0] com_uops_0_bits_next_pc_bits = com_uops_reg_0_bits_next_pc_bits; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_0_bits_ras_head; // @[Core.scala:73:25] wire [2:0] com_uops_0_bits_ras_head = com_uops_reg_0_bits_ras_head; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_taken; // @[Core.scala:73:25] wire com_uops_0_bits_taken = com_uops_reg_0_bits_taken; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_xcpt; // @[Core.scala:73:25] reg [63:0] com_uops_reg_0_bits_xcpt_cause; // @[Core.scala:73:25] wire [63:0] com_uops_0_bits_xcpt_cause = com_uops_reg_0_bits_xcpt_cause; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_needs_replay; // @[Core.scala:73:25] reg [63:0] com_uops_reg_0_bits_rs1_data; // @[Core.scala:73:25] wire [63:0] com_uops_0_bits_rs1_data = com_uops_reg_0_bits_rs1_data; // @[Core.scala:73:25, :74:26] reg [63:0] com_uops_reg_0_bits_rs2_data; // @[Core.scala:73:25] wire [63:0] com_uops_0_bits_rs2_data = com_uops_reg_0_bits_rs2_data; // @[Core.scala:73:25, :74:26] reg [63:0] com_uops_reg_0_bits_rs3_data; // @[Core.scala:73:25] wire [63:0] com_uops_0_bits_rs3_data = com_uops_reg_0_bits_rs3_data; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_uses_memalu; // @[Core.scala:73:25] wire com_uops_0_bits_uses_memalu = com_uops_reg_0_bits_uses_memalu; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_uses_latealu; // @[Core.scala:73:25] wire com_uops_0_bits_uses_latealu = com_uops_reg_0_bits_uses_latealu; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_wdata_valid; // @[Core.scala:73:25] reg [63:0] com_uops_reg_0_bits_wdata_bits; // @[Core.scala:73:25] wire [63:0] _csr_io_tval_a_T = com_uops_reg_0_bits_wdata_bits; // @[Core.scala:65:16, :73:25] reg [4:0] com_uops_reg_0_bits_fra1; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_fra1 = com_uops_reg_0_bits_fra1; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_0_bits_fra2; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_fra2 = com_uops_reg_0_bits_fra2; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_0_bits_fra3; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_fra3 = com_uops_reg_0_bits_fra3; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_0_bits_fexc; // @[Core.scala:73:25] wire [4:0] com_uops_0_bits_fexc = com_uops_reg_0_bits_fexc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_ldst = com_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_wen; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_wen = com_uops_reg_0_bits_fdivin_wen; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_ren1 = com_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_ren2 = com_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_ren3 = com_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_swap12 = com_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_swap23 = com_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fdivin_typeTagIn = com_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fdivin_typeTagOut = com_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_fromint = com_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_toint; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_toint = com_uops_reg_0_bits_fdivin_toint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_fastpipe = com_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_fma; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_fma = com_uops_reg_0_bits_fdivin_fma; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_div; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_div = com_uops_reg_0_bits_fdivin_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_sqrt = com_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_wflags = com_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_fdivin_vec; // @[Core.scala:73:25] wire com_uops_0_bits_fdivin_vec = com_uops_reg_0_bits_fdivin_vec; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_0_bits_fdivin_rm; // @[Core.scala:73:25] wire [2:0] com_uops_0_bits_fdivin_rm = com_uops_reg_0_bits_fdivin_rm; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fdivin_fmaCmd = com_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fdivin_typ; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fdivin_typ = com_uops_reg_0_bits_fdivin_typ; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_fdivin_fmt = com_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_0_bits_fdivin_in1; // @[Core.scala:73:25] wire [64:0] com_uops_0_bits_fdivin_in1 = com_uops_reg_0_bits_fdivin_in1; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_0_bits_fdivin_in2; // @[Core.scala:73:25] wire [64:0] com_uops_0_bits_fdivin_in2 = com_uops_reg_0_bits_fdivin_in2; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_0_bits_fdivin_in3; // @[Core.scala:73:25] wire [64:0] com_uops_0_bits_fdivin_in3 = com_uops_reg_0_bits_fdivin_in3; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_0_bits_mem_size; // @[Core.scala:73:25] wire [1:0] com_uops_0_bits_mem_size = com_uops_reg_0_bits_mem_size; // @[Core.scala:73:25, :74:26] reg com_uops_reg_0_bits_flush_pipe; // @[Core.scala:73:25] wire com_uops_0_bits_flush_pipe = com_uops_reg_0_bits_flush_pipe; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_valid; // @[Core.scala:73:25] wire com_uops_1_valid = com_uops_reg_1_valid; // @[Core.scala:73:25, :74:26] reg [31:0] com_uops_reg_1_bits_inst; // @[Core.scala:73:25] wire [31:0] com_uops_1_bits_inst = com_uops_reg_1_bits_inst; // @[Core.scala:73:25, :74:26] reg [31:0] com_uops_reg_1_bits_raw_inst; // @[Core.scala:73:25] wire [31:0] com_uops_1_bits_raw_inst = com_uops_reg_1_bits_raw_inst; // @[Core.scala:73:25, :74:26] reg [39:0] com_uops_reg_1_bits_pc; // @[Core.scala:73:25] wire [39:0] com_uops_1_bits_pc = com_uops_reg_1_bits_pc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_edge_inst; // @[Core.scala:73:25] wire com_uops_1_bits_edge_inst = com_uops_reg_1_bits_edge_inst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_legal; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_legal = com_uops_reg_1_bits_ctrl_legal; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_fp; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_fp = com_uops_reg_1_bits_ctrl_fp; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rocc = com_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_branch; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_branch = com_uops_reg_1_bits_ctrl_branch; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_jal; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_jal = com_uops_reg_1_bits_ctrl_jal; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_jalr = com_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rxs2 = com_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rxs1 = com_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:73:25] wire [2:0] com_uops_1_bits_ctrl_sel_alu2 = com_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_ctrl_sel_alu1 = com_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:73:25] wire [2:0] com_uops_1_bits_ctrl_sel_imm = com_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_alu_dw = com_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_ctrl_alu_fn = com_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_mem; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_mem = com_uops_reg_1_bits_ctrl_mem; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_ctrl_mem_cmd = com_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rfs1 = com_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rfs2 = com_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_rfs3 = com_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_wfd = com_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_mul; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_mul = com_uops_reg_1_bits_ctrl_mul; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_div; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_div = com_uops_reg_1_bits_ctrl_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_wxd = com_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_1_bits_ctrl_csr; // @[Core.scala:73:25] wire [2:0] com_uops_1_bits_ctrl_csr = com_uops_reg_1_bits_ctrl_csr; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_fence_i = com_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_fence; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_fence = com_uops_reg_1_bits_ctrl_fence; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_amo; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_amo = com_uops_reg_1_bits_ctrl_amo; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_dp; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_dp = com_uops_reg_1_bits_ctrl_dp; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_ctrl_vec; // @[Core.scala:73:25] wire com_uops_1_bits_ctrl_vec = com_uops_reg_1_bits_ctrl_vec; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_ldst = com_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_wen = com_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_ren1 = com_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_ren2 = com_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_ren3 = com_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_swap12 = com_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_swap23 = com_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fp_ctrl_typeTagIn = com_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fp_ctrl_typeTagOut = com_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_fromint = com_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_toint = com_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_fastpipe = com_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_fma = com_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_div = com_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_sqrt = com_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_wflags = com_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:73:25] wire com_uops_1_bits_fp_ctrl_vec = com_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_rvc; // @[Core.scala:73:25] wire com_uops_1_bits_rvc = com_uops_reg_1_bits_rvc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_sets_vcfg; // @[Core.scala:73:25] wire com_uops_1_bits_sets_vcfg = com_uops_reg_1_bits_sets_vcfg; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:73:25] wire com_uops_1_bits_btb_resp_valid = com_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_btb_resp_bits_cfiType = com_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:73:25] wire com_uops_1_bits_btb_resp_bits_taken = com_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:73:25, :74:26] reg [3:0] com_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:73:25] wire [3:0] com_uops_1_bits_btb_resp_bits_mask = com_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_btb_resp_bits_bridx = com_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:73:25, :74:26] reg [38:0] com_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:73:25] wire [38:0] com_uops_1_bits_btb_resp_bits_target = com_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:73:25, :74:26] reg [5:0] com_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:73:25] wire [5:0] com_uops_1_bits_btb_resp_bits_entry = com_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:73:25, :74:26] reg [7:0] com_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:73:25] wire [7:0] com_uops_1_bits_btb_resp_bits_bht_history = com_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_btb_resp_bits_bht_value = com_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_sfb_br; // @[Core.scala:73:25] wire com_uops_1_bits_sfb_br = com_uops_reg_1_bits_sfb_br; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_sfb_shadow; // @[Core.scala:73:25] wire com_uops_1_bits_sfb_shadow = com_uops_reg_1_bits_sfb_shadow; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_next_pc_valid; // @[Core.scala:73:25] wire com_uops_1_bits_next_pc_valid = com_uops_reg_1_bits_next_pc_valid; // @[Core.scala:73:25, :74:26] reg [39:0] com_uops_reg_1_bits_next_pc_bits; // @[Core.scala:73:25] wire [39:0] com_uops_1_bits_next_pc_bits = com_uops_reg_1_bits_next_pc_bits; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_1_bits_ras_head; // @[Core.scala:73:25] wire [2:0] com_uops_1_bits_ras_head = com_uops_reg_1_bits_ras_head; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_taken; // @[Core.scala:73:25] wire com_uops_1_bits_taken = com_uops_reg_1_bits_taken; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_xcpt; // @[Core.scala:73:25] wire com_uops_1_bits_xcpt = com_uops_reg_1_bits_xcpt; // @[Core.scala:73:25, :74:26] reg [63:0] com_uops_reg_1_bits_xcpt_cause; // @[Core.scala:73:25] wire [63:0] com_uops_1_bits_xcpt_cause = com_uops_reg_1_bits_xcpt_cause; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_needs_replay; // @[Core.scala:73:25] reg [63:0] com_uops_reg_1_bits_rs1_data; // @[Core.scala:73:25] wire [63:0] com_uops_1_bits_rs1_data = com_uops_reg_1_bits_rs1_data; // @[Core.scala:73:25, :74:26] reg [63:0] com_uops_reg_1_bits_rs2_data; // @[Core.scala:73:25] wire [63:0] com_uops_1_bits_rs2_data = com_uops_reg_1_bits_rs2_data; // @[Core.scala:73:25, :74:26] reg [63:0] com_uops_reg_1_bits_rs3_data; // @[Core.scala:73:25] wire [63:0] com_uops_1_bits_rs3_data = com_uops_reg_1_bits_rs3_data; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_uses_memalu; // @[Core.scala:73:25] wire com_uops_1_bits_uses_memalu = com_uops_reg_1_bits_uses_memalu; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_uses_latealu; // @[Core.scala:73:25] wire com_uops_1_bits_uses_latealu = com_uops_reg_1_bits_uses_latealu; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_wdata_valid; // @[Core.scala:73:25] reg [63:0] com_uops_reg_1_bits_wdata_bits; // @[Core.scala:73:25] reg [4:0] com_uops_reg_1_bits_fra1; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_fra1 = com_uops_reg_1_bits_fra1; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_1_bits_fra2; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_fra2 = com_uops_reg_1_bits_fra2; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_1_bits_fra3; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_fra3 = com_uops_reg_1_bits_fra3; // @[Core.scala:73:25, :74:26] reg [4:0] com_uops_reg_1_bits_fexc; // @[Core.scala:73:25] wire [4:0] com_uops_1_bits_fexc = com_uops_reg_1_bits_fexc; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_ldst = com_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_wen; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_wen = com_uops_reg_1_bits_fdivin_wen; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_ren1 = com_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_ren2 = com_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_ren3 = com_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_swap12 = com_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_swap23 = com_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fdivin_typeTagIn = com_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fdivin_typeTagOut = com_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_fromint = com_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_toint; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_toint = com_uops_reg_1_bits_fdivin_toint; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_fastpipe = com_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_fma; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_fma = com_uops_reg_1_bits_fdivin_fma; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_div; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_div = com_uops_reg_1_bits_fdivin_div; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_sqrt = com_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_wflags = com_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_fdivin_vec; // @[Core.scala:73:25] wire com_uops_1_bits_fdivin_vec = com_uops_reg_1_bits_fdivin_vec; // @[Core.scala:73:25, :74:26] reg [2:0] com_uops_reg_1_bits_fdivin_rm; // @[Core.scala:73:25] wire [2:0] com_uops_1_bits_fdivin_rm = com_uops_reg_1_bits_fdivin_rm; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fdivin_fmaCmd = com_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fdivin_typ; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fdivin_typ = com_uops_reg_1_bits_fdivin_typ; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_fdivin_fmt = com_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_1_bits_fdivin_in1; // @[Core.scala:73:25] wire [64:0] com_uops_1_bits_fdivin_in1 = com_uops_reg_1_bits_fdivin_in1; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_1_bits_fdivin_in2; // @[Core.scala:73:25] wire [64:0] com_uops_1_bits_fdivin_in2 = com_uops_reg_1_bits_fdivin_in2; // @[Core.scala:73:25, :74:26] reg [64:0] com_uops_reg_1_bits_fdivin_in3; // @[Core.scala:73:25] wire [64:0] com_uops_1_bits_fdivin_in3 = com_uops_reg_1_bits_fdivin_in3; // @[Core.scala:73:25, :74:26] reg [1:0] com_uops_reg_1_bits_mem_size; // @[Core.scala:73:25] wire [1:0] com_uops_1_bits_mem_size = com_uops_reg_1_bits_mem_size; // @[Core.scala:73:25, :74:26] reg com_uops_reg_1_bits_flush_pipe; // @[Core.scala:73:25] wire com_uops_1_bits_flush_pipe = com_uops_reg_1_bits_flush_pipe; // @[Core.scala:73:25, :74:26] wire _com_uops_0_bits_xcpt_T; // @[Core.scala:1049:50] wire com_bypasses_0_can_bypass = com_uops_0_bits_wdata_valid; // @[Core.scala:74:26, :94:63] wire [63:0] com_bypasses_0_data = com_uops_0_bits_wdata_bits; // @[Core.scala:74:26, :94:63] wire com_bypasses_1_can_bypass = com_uops_1_bits_wdata_valid; // @[Core.scala:74:26, :94:63] wire [63:0] com_bypasses_1_data = com_uops_1_bits_wdata_bits; // @[Core.scala:74:26, :94:63] wire com_uops_0_bits_xcpt; // @[Core.scala:74:26] wire com_uops_0_bits_needs_replay; // @[Core.scala:74:26] wire com_uops_1_bits_needs_replay; // @[Core.scala:74:26] reg wb_uops_reg_0_valid; // @[Core.scala:75:24] wire wb_uops_0_valid = wb_uops_reg_0_valid; // @[Core.scala:75:24, :76:25] reg [31:0] wb_uops_reg_0_bits_inst; // @[Core.scala:75:24] wire [31:0] wb_uops_0_bits_inst = wb_uops_reg_0_bits_inst; // @[Core.scala:75:24, :76:25] reg [31:0] wb_uops_reg_0_bits_raw_inst; // @[Core.scala:75:24] wire [31:0] wb_uops_0_bits_raw_inst = wb_uops_reg_0_bits_raw_inst; // @[Core.scala:75:24, :76:25] reg [39:0] wb_uops_reg_0_bits_pc; // @[Core.scala:75:24] wire [39:0] wb_uops_0_bits_pc = wb_uops_reg_0_bits_pc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_edge_inst; // @[Core.scala:75:24] wire wb_uops_0_bits_edge_inst = wb_uops_reg_0_bits_edge_inst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_legal; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_legal = wb_uops_reg_0_bits_ctrl_legal; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_fp; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_fp = wb_uops_reg_0_bits_ctrl_fp; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rocc = wb_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_branch; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_branch = wb_uops_reg_0_bits_ctrl_branch; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_jal; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_jal = wb_uops_reg_0_bits_ctrl_jal; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_jalr = wb_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rxs2 = wb_uops_reg_0_bits_ctrl_rxs2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rxs1 = wb_uops_reg_0_bits_ctrl_rxs1; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:75:24] wire [2:0] wb_uops_0_bits_ctrl_sel_alu2 = wb_uops_reg_0_bits_ctrl_sel_alu2; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_ctrl_sel_alu1 = wb_uops_reg_0_bits_ctrl_sel_alu1; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:75:24] wire [2:0] wb_uops_0_bits_ctrl_sel_imm = wb_uops_reg_0_bits_ctrl_sel_imm; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_alu_dw = wb_uops_reg_0_bits_ctrl_alu_dw; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_ctrl_alu_fn = wb_uops_reg_0_bits_ctrl_alu_fn; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_mem; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_mem = wb_uops_reg_0_bits_ctrl_mem; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_ctrl_mem_cmd = wb_uops_reg_0_bits_ctrl_mem_cmd; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rfs1 = wb_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rfs2 = wb_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_rfs3 = wb_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_wfd = wb_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_mul; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_mul = wb_uops_reg_0_bits_ctrl_mul; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_div; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_div = wb_uops_reg_0_bits_ctrl_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_wxd = wb_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_0_bits_ctrl_csr; // @[Core.scala:75:24] wire [2:0] wb_uops_0_bits_ctrl_csr = wb_uops_reg_0_bits_ctrl_csr; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_fence_i = wb_uops_reg_0_bits_ctrl_fence_i; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_fence; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_fence = wb_uops_reg_0_bits_ctrl_fence; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_amo; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_amo = wb_uops_reg_0_bits_ctrl_amo; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_dp; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_dp = wb_uops_reg_0_bits_ctrl_dp; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_ctrl_vec; // @[Core.scala:75:24] wire wb_uops_0_bits_ctrl_vec = wb_uops_reg_0_bits_ctrl_vec; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_ldst = wb_uops_reg_0_bits_fp_ctrl_ldst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_wen = wb_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_ren1 = wb_uops_reg_0_bits_fp_ctrl_ren1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_ren2 = wb_uops_reg_0_bits_fp_ctrl_ren2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_ren3 = wb_uops_reg_0_bits_fp_ctrl_ren3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_swap12 = wb_uops_reg_0_bits_fp_ctrl_swap12; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_swap23 = wb_uops_reg_0_bits_fp_ctrl_swap23; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fp_ctrl_typeTagIn = wb_uops_reg_0_bits_fp_ctrl_typeTagIn; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fp_ctrl_typeTagOut = wb_uops_reg_0_bits_fp_ctrl_typeTagOut; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_fromint = wb_uops_reg_0_bits_fp_ctrl_fromint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_toint = wb_uops_reg_0_bits_fp_ctrl_toint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_fastpipe = wb_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_fma = wb_uops_reg_0_bits_fp_ctrl_fma; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_div = wb_uops_reg_0_bits_fp_ctrl_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_sqrt = wb_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_wflags = wb_uops_reg_0_bits_fp_ctrl_wflags; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:75:24] wire wb_uops_0_bits_fp_ctrl_vec = wb_uops_reg_0_bits_fp_ctrl_vec; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_rvc; // @[Core.scala:75:24] wire wb_uops_0_bits_rvc = wb_uops_reg_0_bits_rvc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_sets_vcfg; // @[Core.scala:75:24] wire wb_uops_0_bits_sets_vcfg = wb_uops_reg_0_bits_sets_vcfg; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:75:24] wire wb_uops_0_bits_btb_resp_valid = wb_uops_reg_0_bits_btb_resp_valid; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_btb_resp_bits_cfiType = wb_uops_reg_0_bits_btb_resp_bits_cfiType; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:75:24] wire wb_uops_0_bits_btb_resp_bits_taken = wb_uops_reg_0_bits_btb_resp_bits_taken; // @[Core.scala:75:24, :76:25] reg [3:0] wb_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:75:24] wire [3:0] wb_uops_0_bits_btb_resp_bits_mask = wb_uops_reg_0_bits_btb_resp_bits_mask; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_btb_resp_bits_bridx = wb_uops_reg_0_bits_btb_resp_bits_bridx; // @[Core.scala:75:24, :76:25] reg [38:0] wb_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:75:24] wire [38:0] wb_uops_0_bits_btb_resp_bits_target = wb_uops_reg_0_bits_btb_resp_bits_target; // @[Core.scala:75:24, :76:25] reg [5:0] wb_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:75:24] wire [5:0] wb_uops_0_bits_btb_resp_bits_entry = wb_uops_reg_0_bits_btb_resp_bits_entry; // @[Core.scala:75:24, :76:25] reg [7:0] wb_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:75:24] wire [7:0] wb_uops_0_bits_btb_resp_bits_bht_history = wb_uops_reg_0_bits_btb_resp_bits_bht_history; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_btb_resp_bits_bht_value = wb_uops_reg_0_bits_btb_resp_bits_bht_value; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_sfb_br; // @[Core.scala:75:24] wire wb_uops_0_bits_sfb_br = wb_uops_reg_0_bits_sfb_br; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_sfb_shadow; // @[Core.scala:75:24] wire wb_uops_0_bits_sfb_shadow = wb_uops_reg_0_bits_sfb_shadow; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_next_pc_valid; // @[Core.scala:75:24] wire wb_uops_0_bits_next_pc_valid = wb_uops_reg_0_bits_next_pc_valid; // @[Core.scala:75:24, :76:25] reg [39:0] wb_uops_reg_0_bits_next_pc_bits; // @[Core.scala:75:24] wire [39:0] wb_uops_0_bits_next_pc_bits = wb_uops_reg_0_bits_next_pc_bits; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_0_bits_ras_head; // @[Core.scala:75:24] wire [2:0] wb_uops_0_bits_ras_head = wb_uops_reg_0_bits_ras_head; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_taken; // @[Core.scala:75:24] wire wb_uops_0_bits_taken = wb_uops_reg_0_bits_taken; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_xcpt; // @[Core.scala:75:24] wire wb_uops_0_bits_xcpt = wb_uops_reg_0_bits_xcpt; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_0_bits_xcpt_cause; // @[Core.scala:75:24] wire [63:0] wb_uops_0_bits_xcpt_cause = wb_uops_reg_0_bits_xcpt_cause; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_needs_replay; // @[Core.scala:75:24] wire wb_uops_0_bits_needs_replay = wb_uops_reg_0_bits_needs_replay; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_0_bits_rs1_data; // @[Core.scala:75:24] wire [63:0] wb_uops_0_bits_rs1_data = wb_uops_reg_0_bits_rs1_data; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_0_bits_rs2_data; // @[Core.scala:75:24] wire [63:0] wb_uops_0_bits_rs2_data = wb_uops_reg_0_bits_rs2_data; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_0_bits_rs3_data; // @[Core.scala:75:24] wire [63:0] wb_uops_0_bits_rs3_data = wb_uops_reg_0_bits_rs3_data; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_uses_memalu; // @[Core.scala:75:24] wire wb_uops_0_bits_uses_memalu = wb_uops_reg_0_bits_uses_memalu; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_uses_latealu; // @[Core.scala:75:24] wire wb_uops_0_bits_uses_latealu = wb_uops_reg_0_bits_uses_latealu; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_wdata_valid; // @[Core.scala:75:24] wire wb_uops_0_bits_wdata_valid = wb_uops_reg_0_bits_wdata_valid; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_0_bits_wdata_bits; // @[Core.scala:75:24] wire [63:0] wb_uops_0_bits_wdata_bits = wb_uops_reg_0_bits_wdata_bits; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_fra1; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_fra1 = wb_uops_reg_0_bits_fra1; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_fra2; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_fra2 = wb_uops_reg_0_bits_fra2; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_fra3; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_fra3 = wb_uops_reg_0_bits_fra3; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_0_bits_fexc; // @[Core.scala:75:24] wire [4:0] wb_uops_0_bits_fexc = wb_uops_reg_0_bits_fexc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_ldst = wb_uops_reg_0_bits_fdivin_ldst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_wen; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_wen = wb_uops_reg_0_bits_fdivin_wen; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_ren1 = wb_uops_reg_0_bits_fdivin_ren1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_ren2 = wb_uops_reg_0_bits_fdivin_ren2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_ren3 = wb_uops_reg_0_bits_fdivin_ren3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_swap12 = wb_uops_reg_0_bits_fdivin_swap12; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_swap23 = wb_uops_reg_0_bits_fdivin_swap23; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fdivin_typeTagIn = wb_uops_reg_0_bits_fdivin_typeTagIn; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fdivin_typeTagOut = wb_uops_reg_0_bits_fdivin_typeTagOut; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_fromint = wb_uops_reg_0_bits_fdivin_fromint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_toint; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_toint = wb_uops_reg_0_bits_fdivin_toint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_fastpipe = wb_uops_reg_0_bits_fdivin_fastpipe; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_fma; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_fma = wb_uops_reg_0_bits_fdivin_fma; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_div; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_div = wb_uops_reg_0_bits_fdivin_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_sqrt = wb_uops_reg_0_bits_fdivin_sqrt; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_wflags = wb_uops_reg_0_bits_fdivin_wflags; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_fdivin_vec; // @[Core.scala:75:24] wire wb_uops_0_bits_fdivin_vec = wb_uops_reg_0_bits_fdivin_vec; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_0_bits_fdivin_rm; // @[Core.scala:75:24] wire [2:0] wb_uops_0_bits_fdivin_rm = wb_uops_reg_0_bits_fdivin_rm; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fdivin_fmaCmd = wb_uops_reg_0_bits_fdivin_fmaCmd; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fdivin_typ; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fdivin_typ = wb_uops_reg_0_bits_fdivin_typ; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_fdivin_fmt = wb_uops_reg_0_bits_fdivin_fmt; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_0_bits_fdivin_in1; // @[Core.scala:75:24] wire [64:0] wb_uops_0_bits_fdivin_in1 = wb_uops_reg_0_bits_fdivin_in1; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_0_bits_fdivin_in2; // @[Core.scala:75:24] wire [64:0] wb_uops_0_bits_fdivin_in2 = wb_uops_reg_0_bits_fdivin_in2; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_0_bits_fdivin_in3; // @[Core.scala:75:24] wire [64:0] wb_uops_0_bits_fdivin_in3 = wb_uops_reg_0_bits_fdivin_in3; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_0_bits_mem_size; // @[Core.scala:75:24] wire [1:0] wb_uops_0_bits_mem_size = wb_uops_reg_0_bits_mem_size; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_0_bits_flush_pipe; // @[Core.scala:75:24] wire wb_uops_0_bits_flush_pipe = wb_uops_reg_0_bits_flush_pipe; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_valid; // @[Core.scala:75:24] wire wb_uops_1_valid = wb_uops_reg_1_valid; // @[Core.scala:75:24, :76:25] reg [31:0] wb_uops_reg_1_bits_inst; // @[Core.scala:75:24] wire [31:0] wb_uops_1_bits_inst = wb_uops_reg_1_bits_inst; // @[Core.scala:75:24, :76:25] reg [31:0] wb_uops_reg_1_bits_raw_inst; // @[Core.scala:75:24] wire [31:0] wb_uops_1_bits_raw_inst = wb_uops_reg_1_bits_raw_inst; // @[Core.scala:75:24, :76:25] reg [39:0] wb_uops_reg_1_bits_pc; // @[Core.scala:75:24] wire [39:0] wb_uops_1_bits_pc = wb_uops_reg_1_bits_pc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_edge_inst; // @[Core.scala:75:24] wire wb_uops_1_bits_edge_inst = wb_uops_reg_1_bits_edge_inst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_legal; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_legal = wb_uops_reg_1_bits_ctrl_legal; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_fp; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_fp = wb_uops_reg_1_bits_ctrl_fp; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rocc = wb_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_branch; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_branch = wb_uops_reg_1_bits_ctrl_branch; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_jal; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_jal = wb_uops_reg_1_bits_ctrl_jal; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_jalr = wb_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rxs2 = wb_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rxs1 = wb_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:75:24] wire [2:0] wb_uops_1_bits_ctrl_sel_alu2 = wb_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_ctrl_sel_alu1 = wb_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:75:24] wire [2:0] wb_uops_1_bits_ctrl_sel_imm = wb_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_alu_dw = wb_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_ctrl_alu_fn = wb_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_mem; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_mem = wb_uops_reg_1_bits_ctrl_mem; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_ctrl_mem_cmd = wb_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rfs1 = wb_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rfs2 = wb_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_rfs3 = wb_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_wfd = wb_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_mul; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_mul = wb_uops_reg_1_bits_ctrl_mul; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_div; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_div = wb_uops_reg_1_bits_ctrl_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_wxd = wb_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_1_bits_ctrl_csr; // @[Core.scala:75:24] wire [2:0] wb_uops_1_bits_ctrl_csr = wb_uops_reg_1_bits_ctrl_csr; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_fence_i = wb_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_fence; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_fence = wb_uops_reg_1_bits_ctrl_fence; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_amo; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_amo = wb_uops_reg_1_bits_ctrl_amo; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_dp; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_dp = wb_uops_reg_1_bits_ctrl_dp; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_ctrl_vec; // @[Core.scala:75:24] wire wb_uops_1_bits_ctrl_vec = wb_uops_reg_1_bits_ctrl_vec; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_ldst = wb_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_wen = wb_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_ren1 = wb_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_ren2 = wb_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_ren3 = wb_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_swap12 = wb_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_swap23 = wb_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fp_ctrl_typeTagIn = wb_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fp_ctrl_typeTagOut = wb_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_fromint = wb_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_toint = wb_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_fastpipe = wb_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_fma = wb_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_div = wb_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_sqrt = wb_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_wflags = wb_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:75:24] wire wb_uops_1_bits_fp_ctrl_vec = wb_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_rvc; // @[Core.scala:75:24] wire wb_uops_1_bits_rvc = wb_uops_reg_1_bits_rvc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_sets_vcfg; // @[Core.scala:75:24] wire wb_uops_1_bits_sets_vcfg = wb_uops_reg_1_bits_sets_vcfg; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:75:24] wire wb_uops_1_bits_btb_resp_valid = wb_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_btb_resp_bits_cfiType = wb_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:75:24] wire wb_uops_1_bits_btb_resp_bits_taken = wb_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:75:24, :76:25] reg [3:0] wb_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:75:24] wire [3:0] wb_uops_1_bits_btb_resp_bits_mask = wb_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_btb_resp_bits_bridx = wb_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:75:24, :76:25] reg [38:0] wb_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:75:24] wire [38:0] wb_uops_1_bits_btb_resp_bits_target = wb_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:75:24, :76:25] reg [5:0] wb_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:75:24] wire [5:0] wb_uops_1_bits_btb_resp_bits_entry = wb_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:75:24, :76:25] reg [7:0] wb_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:75:24] wire [7:0] wb_uops_1_bits_btb_resp_bits_bht_history = wb_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_btb_resp_bits_bht_value = wb_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_sfb_br; // @[Core.scala:75:24] wire wb_uops_1_bits_sfb_br = wb_uops_reg_1_bits_sfb_br; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_sfb_shadow; // @[Core.scala:75:24] wire wb_uops_1_bits_sfb_shadow = wb_uops_reg_1_bits_sfb_shadow; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_next_pc_valid; // @[Core.scala:75:24] wire wb_uops_1_bits_next_pc_valid = wb_uops_reg_1_bits_next_pc_valid; // @[Core.scala:75:24, :76:25] reg [39:0] wb_uops_reg_1_bits_next_pc_bits; // @[Core.scala:75:24] wire [39:0] wb_uops_1_bits_next_pc_bits = wb_uops_reg_1_bits_next_pc_bits; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_1_bits_ras_head; // @[Core.scala:75:24] wire [2:0] wb_uops_1_bits_ras_head = wb_uops_reg_1_bits_ras_head; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_taken; // @[Core.scala:75:24] wire wb_uops_1_bits_taken = wb_uops_reg_1_bits_taken; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_xcpt; // @[Core.scala:75:24] wire wb_uops_1_bits_xcpt = wb_uops_reg_1_bits_xcpt; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_1_bits_xcpt_cause; // @[Core.scala:75:24] wire [63:0] wb_uops_1_bits_xcpt_cause = wb_uops_reg_1_bits_xcpt_cause; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_needs_replay; // @[Core.scala:75:24] wire wb_uops_1_bits_needs_replay = wb_uops_reg_1_bits_needs_replay; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_1_bits_rs1_data; // @[Core.scala:75:24] wire [63:0] wb_uops_1_bits_rs1_data = wb_uops_reg_1_bits_rs1_data; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_1_bits_rs2_data; // @[Core.scala:75:24] wire [63:0] wb_uops_1_bits_rs2_data = wb_uops_reg_1_bits_rs2_data; // @[Core.scala:75:24, :76:25] reg [63:0] wb_uops_reg_1_bits_rs3_data; // @[Core.scala:75:24] wire [63:0] wb_uops_1_bits_rs3_data = wb_uops_reg_1_bits_rs3_data; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_uses_memalu; // @[Core.scala:75:24] wire wb_uops_1_bits_uses_memalu = wb_uops_reg_1_bits_uses_memalu; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_uses_latealu; // @[Core.scala:75:24] wire wb_uops_1_bits_uses_latealu = wb_uops_reg_1_bits_uses_latealu; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_wdata_valid; // @[Core.scala:75:24] reg [63:0] wb_uops_reg_1_bits_wdata_bits; // @[Core.scala:75:24] reg [4:0] wb_uops_reg_1_bits_fra1; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_fra1 = wb_uops_reg_1_bits_fra1; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_1_bits_fra2; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_fra2 = wb_uops_reg_1_bits_fra2; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_1_bits_fra3; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_fra3 = wb_uops_reg_1_bits_fra3; // @[Core.scala:75:24, :76:25] reg [4:0] wb_uops_reg_1_bits_fexc; // @[Core.scala:75:24] wire [4:0] wb_uops_1_bits_fexc = wb_uops_reg_1_bits_fexc; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_ldst = wb_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_wen; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_wen = wb_uops_reg_1_bits_fdivin_wen; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_ren1 = wb_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_ren2 = wb_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_ren3 = wb_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_swap12 = wb_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_swap23 = wb_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fdivin_typeTagIn = wb_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fdivin_typeTagOut = wb_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_fromint = wb_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_toint; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_toint = wb_uops_reg_1_bits_fdivin_toint; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_fastpipe = wb_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_fma; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_fma = wb_uops_reg_1_bits_fdivin_fma; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_div; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_div = wb_uops_reg_1_bits_fdivin_div; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_sqrt = wb_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_wflags = wb_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_fdivin_vec; // @[Core.scala:75:24] wire wb_uops_1_bits_fdivin_vec = wb_uops_reg_1_bits_fdivin_vec; // @[Core.scala:75:24, :76:25] reg [2:0] wb_uops_reg_1_bits_fdivin_rm; // @[Core.scala:75:24] wire [2:0] wb_uops_1_bits_fdivin_rm = wb_uops_reg_1_bits_fdivin_rm; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fdivin_fmaCmd = wb_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fdivin_typ; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fdivin_typ = wb_uops_reg_1_bits_fdivin_typ; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_fdivin_fmt = wb_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_1_bits_fdivin_in1; // @[Core.scala:75:24] wire [64:0] wb_uops_1_bits_fdivin_in1 = wb_uops_reg_1_bits_fdivin_in1; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_1_bits_fdivin_in2; // @[Core.scala:75:24] wire [64:0] wb_uops_1_bits_fdivin_in2 = wb_uops_reg_1_bits_fdivin_in2; // @[Core.scala:75:24, :76:25] reg [64:0] wb_uops_reg_1_bits_fdivin_in3; // @[Core.scala:75:24] wire [64:0] wb_uops_1_bits_fdivin_in3 = wb_uops_reg_1_bits_fdivin_in3; // @[Core.scala:75:24, :76:25] reg [1:0] wb_uops_reg_1_bits_mem_size; // @[Core.scala:75:24] wire [1:0] wb_uops_1_bits_mem_size = wb_uops_reg_1_bits_mem_size; // @[Core.scala:75:24, :76:25] reg wb_uops_reg_1_bits_flush_pipe; // @[Core.scala:75:24] wire wb_uops_1_bits_flush_pipe = wb_uops_reg_1_bits_flush_pipe; // @[Core.scala:75:24, :76:25] wire wb_bypasses_0_can_bypass = wb_uops_0_bits_wdata_valid; // @[Core.scala:76:25, :95:62] wire [63:0] wb_bypasses_0_data = wb_uops_0_bits_wdata_bits; // @[Core.scala:76:25, :95:62] wire wb_bypasses_1_can_bypass = wb_uops_1_bits_wdata_valid; // @[Core.scala:76:25, :95:62] wire [63:0] wb_bypasses_1_data = wb_uops_1_bits_wdata_bits; // @[Core.scala:76:25, :95:62] wire _ex_bypasses_0_valid_T; // @[Core.scala:610:50] wire [4:0] _ex_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire [63:0] _ex_bypasses_0_data_T; // @[Core.scala:613:31] wire _ex_bypasses_0_can_bypass_T_26; // @[Core.scala:612:88] wire ex_bypasses_0_valid; // @[Core.scala:92:62] wire [4:0] ex_bypasses_0_dst; // @[Core.scala:92:62] wire [63:0] ex_bypasses_0_data; // @[Core.scala:92:62] wire ex_bypasses_0_can_bypass; // @[Core.scala:92:62] wire _ex_bypasses_1_valid_T; // @[Core.scala:610:50] wire [4:0] _ex_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire [63:0] _ex_bypasses_1_data_T; // @[Core.scala:613:31] wire _ex_bypasses_1_can_bypass_T_26; // @[Core.scala:612:88] wire ex_bypasses_1_valid; // @[Core.scala:92:62] wire [4:0] ex_bypasses_1_dst; // @[Core.scala:92:62] wire [63:0] ex_bypasses_1_data; // @[Core.scala:92:62] wire ex_bypasses_1_can_bypass; // @[Core.scala:92:62] wire _mem_bypasses_0_valid_T_2; // @[Core.scala:798:85] wire [4:0] _mem_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire mem_bypasses_0_valid; // @[Core.scala:93:63] wire [4:0] mem_bypasses_0_dst; // @[Core.scala:93:63] wire [4:0] _mem_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire mem_bypasses_1_valid; // @[Core.scala:93:63] wire [4:0] mem_bypasses_1_dst; // @[Core.scala:93:63] wire [63:0] mem_bypasses_1_data; // @[Core.scala:93:63] wire mem_bypasses_1_can_bypass; // @[Core.scala:93:63] wire _com_bypasses_0_valid_T; // @[Core.scala:1098:52] wire [4:0] _com_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire com_bypasses_0_valid; // @[Core.scala:94:63] wire [4:0] com_bypasses_0_dst; // @[Core.scala:94:63] wire _com_bypasses_1_valid_T; // @[Core.scala:1098:52] wire [4:0] _com_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire com_bypasses_1_valid; // @[Core.scala:94:63] wire [4:0] com_bypasses_1_dst; // @[Core.scala:94:63] wire _wb_bypasses_0_valid_T; // @[Core.scala:1209:46] wire [4:0] _wb_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire wb_bypasses_0_valid; // @[Core.scala:95:62] wire [4:0] wb_bypasses_0_dst; // @[Core.scala:95:62] wire _wb_bypasses_1_valid_T; // @[Core.scala:1209:46] wire [4:0] _wb_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire wb_bypasses_1_valid; // @[Core.scala:95:62] wire [4:0] wb_bypasses_1_dst; // @[Core.scala:95:62] wire ll_bypass_0_valid; // @[Core.scala:96:40] wire [4:0] ll_bypass_0_dst; // @[Core.scala:96:40] wire [63:0] ll_bypass_0_data; // @[Core.scala:96:40] wire _fp_mem_bypasses_0_valid_T_2; // @[Core.scala:803:88] wire [4:0] _fp_mem_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire fp_mem_bypasses_0_valid; // @[Core.scala:101:66] wire [4:0] fp_mem_bypasses_0_dst; // @[Core.scala:101:66] wire _fp_mem_bypasses_1_valid_T_2; // @[Core.scala:803:88] wire [4:0] _fp_mem_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire fp_mem_bypasses_1_valid; // @[Core.scala:101:66] wire [4:0] fp_mem_bypasses_1_dst; // @[Core.scala:101:66] wire _fp_com_bypasses_0_valid_T; // @[Core.scala:1107:55] wire [4:0] _fp_com_bypasses_0_dst_T; // @[MicroOp.scala:55:16] wire fp_com_bypasses_0_valid; // @[Core.scala:102:66] wire [4:0] fp_com_bypasses_0_dst; // @[Core.scala:102:66] wire _fp_com_bypasses_1_valid_T; // @[Core.scala:1107:55] wire [4:0] _fp_com_bypasses_1_dst_T; // @[MicroOp.scala:55:16] wire fp_com_bypasses_1_valid; // @[Core.scala:102:66] wire [4:0] fp_com_bypasses_1_dst; // @[Core.scala:102:66] wire _rrd_stall_0_T_12; // @[Core.scala:445:48] wire _rrd_stall_1_T_12; // @[Core.scala:445:48] wire rrd_stall_0; // @[Core.scala:106:23] wire rrd_stall_1; // @[Core.scala:106:23] wire _ex_stall_T_5; // @[Core.scala:625:53] wire ex_stall; // @[Core.scala:107:26] wire flush_rrd_ex; // @[Core.scala:110:30] wire kill_mem; // @[Core.scala:111:26] wire kill_com_1; // @[Core.scala:112:26] wire _T_16 = ex_uops_reg_0_valid | ex_uops_reg_1_valid; // @[Core.scala:71:24, :114:49] wire ex_bsy; // @[Core.scala:114:49] assign ex_bsy = _T_16; // @[Core.scala:114:49] wire _ex_stall_T; // @[Core.scala:625:48] assign _ex_stall_T = _T_16; // @[Core.scala:114:49, :625:48] wire _dtlb_io_req_0_bits_vaddr_T; // @[package.scala:81:59] assign _dtlb_io_req_0_bits_vaddr_T = _T_16; // @[Core.scala:114:49] wire mem_bsy = mem_uops_reg_0_valid | mem_uops_reg_1_valid; // @[Core.scala:72:25, :115:51] wire com_bsy = com_uops_reg_0_valid | com_uops_reg_1_valid; // @[Core.scala:73:25, :116:51] wire _com_retire_0_T_5; // @[Core.scala:941:104] wire _com_retire_1_T_5; // @[Core.scala:941:104] wire com_retire_0; // @[Core.scala:118:24] wire com_retire_1; // @[Core.scala:118:24] wire _ex_uops_reg_0_valid_T = ~rrd_stall_0; // @[Core.scala:106:23, :124:52] wire _ex_uops_reg_0_valid_T_1 = rrd_uops_0_valid & _ex_uops_reg_0_valid_T; // @[Core.scala:70:22, :124:{49,52}] wire _mem_uops_reg_0_valid_T = ~flush_rrd_ex; // @[Core.scala:110:30, :129:54] wire _mem_uops_reg_0_valid_T_1 = ex_uops_reg_0_valid & _mem_uops_reg_0_valid_T; // @[Core.scala:71:24, :129:{51,54}] wire _mem_uops_reg_0_valid_T_2 = ~ex_stall; // @[Core.scala:107:26, :122:11, :129:71] wire _mem_uops_reg_0_valid_T_3 = _mem_uops_reg_0_valid_T_1 & _mem_uops_reg_0_valid_T_2; // @[Core.scala:129:{51,68,71}] wire _com_uops_reg_0_valid_T = ~kill_mem; // @[Core.scala:111:26, :132:55] wire _com_uops_reg_0_valid_T_1 = mem_uops_reg_0_valid & _com_uops_reg_0_valid_T; // @[Core.scala:72:25, :132:{52,55}] wire _ex_uops_reg_1_valid_T = ~rrd_stall_1; // @[Core.scala:106:23, :124:52] wire _ex_uops_reg_1_valid_T_1 = rrd_uops_1_valid & _ex_uops_reg_1_valid_T; // @[Core.scala:70:22, :124:{49,52}] wire _mem_uops_reg_1_valid_T = ~flush_rrd_ex; // @[Core.scala:110:30, :129:54] wire _mem_uops_reg_1_valid_T_1 = ex_uops_reg_1_valid & _mem_uops_reg_1_valid_T; // @[Core.scala:71:24, :129:{51,54}] wire _mem_uops_reg_1_valid_T_2 = ~ex_stall; // @[Core.scala:107:26, :122:11, :129:71] wire _mem_uops_reg_1_valid_T_3 = _mem_uops_reg_1_valid_T_1 & _mem_uops_reg_1_valid_T_2; // @[Core.scala:129:{51,68,71}] wire _com_uops_reg_1_valid_T = ~kill_mem; // @[Core.scala:111:26, :132:55] wire _com_uops_reg_1_valid_T_1 = mem_uops_reg_1_valid & _com_uops_reg_1_valid_T; // @[Core.scala:72:25, :132:{52,55}] wire [31:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] decoder_decoded; // @[pla.scala:81:23] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_98_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_101_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_9_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_29_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_139_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_117_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_4 = decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_95_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_7 = {decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_35_2 = &_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_8 = {decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_8 = {decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_182_2 = &_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_9 = {decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_9 = {decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_9 = {decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_128_2 = &_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_10 = {decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_10 = {decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_66_2 = &_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_78 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_31 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_7 = {decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_10, decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_11 = {decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_11 = {decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_10 = {decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_11 = {decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_77_2 = &_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_8 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_12 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_12 = {decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_11 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_12 = {decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_190_2 = &_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_9 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_13 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_13 = {decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_12 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_7_2 = &_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_10 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_14 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_14 = {decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_13 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_97_2 = &_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_11 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_14 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_15 = {decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_32_2 = &_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_12 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_16 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_16 = {decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_15 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_16 = {decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_70_2 = &_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_17 = {decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_181_2 = &_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_17 = decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_18 = {decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_18 = {decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_145_2 = &_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_19 = {decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_19 = {decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_143_2 = &_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_19 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_20 = {decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_16 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_20 = {decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_20_2 = &_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_20 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_17 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_21 = {decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_22_2 = &_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_22 = {decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_22 = {decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_96_2 = &_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_23 = {decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_23 = {decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_39_2 = &_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_24 = {decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_24 = {decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_131_2 = &_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_24 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_25 = {decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_25 = {decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_191_2 = &_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_64 = decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_26 = {decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_26 = {decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_165_2 = &_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_65 = decoder_decoded_andMatrixOutputs_165_2; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_119 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_25, decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_23, decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_21, decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_19 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_18, decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_16, decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_26 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_27 = {decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_23 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_27 = {decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_54_2 = &_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28, decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_20 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_27 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] decoder_decoded_andMatrixOutputs_lo_28 = {decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_24 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_89_2 = &_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_29 = {decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_29 = {decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_30_2 = &_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_30 = {decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_30 = {decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_26_2 = &_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_31 = {decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_176_2 = &_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_32 = {decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_76_2 = &_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_21_2 = &_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_5 = decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_25 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_30 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_34 = {decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_121_2 = &_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_26 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_34 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_35 = {decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_35 = {decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_60_2 = &_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_27 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_36 = {decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_32 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_36 = {decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_103_2 = &_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_28 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_37 = {decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_33 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_37 = {decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_24_2 = &_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_38 = {decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_38 = {decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_166_2 = &_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_39 = {decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_39 = {decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_160_2 = &_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_40 = {decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_40 = {decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_94_2 = &_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_41 = {decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_41 = {decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_55_2 = &_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_42 = {decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_42 = {decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_16_2 = &_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_43 = {decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_43 = {decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_185_2 = &_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_6 = decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_44 = {decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_44 = {decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_140_2 = &_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_45 = {decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_45 = {decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_52_2 = &_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_46 = {decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_46 = {decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_193_2 = &_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_47 = {decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_47 = {decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_91_2 = &_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_48 = {decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_48 = {decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_17_2 = &_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_49 = {decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_49 = {decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_129_2 = &_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_50 = {decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_177_2 = &_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_51 = {decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_51 = {decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_123_2 = &_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_51 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_52 = {decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_48 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_52 = {decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_14_2 = &_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_28 = decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_43 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_52 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_53 = {decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_132_2 = &_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_44 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_53 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_54 = {decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_50 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_54 = {decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_48_2 = &_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_55 = {decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_155_2 = &_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_7 = decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_56 = {decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_56 = {decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_184_2 = &_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_57 = {decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_57 = {decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_148_2 = &_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_58 = {decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_58 = {decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_115_2 = &_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_49 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_59 = {decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_59 = {decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_163_2 = &_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_60 = {decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_60 = {decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_45_2 = &_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_51 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_61 = {decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_61 = {decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_126_2 = &_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_52 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_62 = {decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_62 = {decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_150_2 = &_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_63 = {decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_63 = {decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_162_2 = &_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_64 = {decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_64 = {decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_133_2 = &_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_65 = {decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_65 = {decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_179_2 = &_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_66 = {decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_66 = {decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_67 = {decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_67 = {decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_87_2 = &_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_68 = {decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_68 = {decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_93_2 = &_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_69 = {decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_69 = {decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_65_2 = &_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_70 = {decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_70 = {decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_125_2 = &_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_71 = {decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_71 = {decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_90_2 = &_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_72 = {decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_72 = {decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_111_2 = &_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_72 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_73 = {decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_69 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_73 = {decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_172_2 = &_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_74 = {decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_74 = {decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_146_2 = &_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_75 = {decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_75 = {decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_170_2 = &_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_76 = {decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_76 = {decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_76 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_77 = {decoder_decoded_andMatrixOutputs_lo_hi_76, decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_77 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_77 = {decoder_decoded_andMatrixOutputs_hi_hi_77, decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_77 = {decoder_decoded_andMatrixOutputs_hi_77, decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_15_2 = &_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_68 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_26, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_77 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_78 = {decoder_decoded_andMatrixOutputs_lo_hi_77, decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_74 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_78 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_78 = {decoder_decoded_andMatrixOutputs_hi_hi_78, decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_78 = {decoder_decoded_andMatrixOutputs_hi_78, decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_167_2 = &_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_69 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_78 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_79 = {decoder_decoded_andMatrixOutputs_lo_hi_78, decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_75 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_79 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_79 = {decoder_decoded_andMatrixOutputs_hi_hi_79, decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_79 = {decoder_decoded_andMatrixOutputs_hi_79, decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_108_2 = &_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_80 = {decoder_decoded_andMatrixOutputs_lo_hi_79, decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_80 = {decoder_decoded_andMatrixOutputs_hi_hi_80, decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_80 = {decoder_decoded_andMatrixOutputs_hi_80, decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_75_2 = &_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_70 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_80 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_81 = {decoder_decoded_andMatrixOutputs_lo_hi_80, decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_77 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_81 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_81 = {decoder_decoded_andMatrixOutputs_hi_hi_81, decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_81 = {decoder_decoded_andMatrixOutputs_hi_81, decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_86_2 = &_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_71 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_81 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_82 = {decoder_decoded_andMatrixOutputs_lo_hi_81, decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_78 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_82 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_82 = {decoder_decoded_andMatrixOutputs_hi_hi_82, decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_82 = {decoder_decoded_andMatrixOutputs_hi_82, decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_144_2 = &_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_72 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_82 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_83 = {decoder_decoded_andMatrixOutputs_lo_hi_82, decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_79 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_83 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_83 = {decoder_decoded_andMatrixOutputs_hi_hi_83, decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_83 = {decoder_decoded_andMatrixOutputs_hi_83, decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_36_2 = &_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_73 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_83 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_84 = {decoder_decoded_andMatrixOutputs_lo_hi_83, decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_80 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_84 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_84 = {decoder_decoded_andMatrixOutputs_hi_hi_84, decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_84 = {decoder_decoded_andMatrixOutputs_hi_84, decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_41_2 = &_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_74 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_84 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_85 = {decoder_decoded_andMatrixOutputs_lo_hi_84, decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_81 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_85 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_85 = {decoder_decoded_andMatrixOutputs_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_85 = {decoder_decoded_andMatrixOutputs_hi_85, decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_8_2 = &_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_12 = decoder_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_75 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_85 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_86 = {decoder_decoded_andMatrixOutputs_lo_hi_85, decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_82 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_86 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_86 = {decoder_decoded_andMatrixOutputs_hi_hi_86, decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_86 = {decoder_decoded_andMatrixOutputs_hi_86, decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_102_2 = &_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_76 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_86 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_87 = {decoder_decoded_andMatrixOutputs_lo_hi_86, decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_83 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_87 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_87 = {decoder_decoded_andMatrixOutputs_hi_hi_87, decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_87 = {decoder_decoded_andMatrixOutputs_hi_87, decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_72_2 = &_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_7, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_77 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_87 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_88 = {decoder_decoded_andMatrixOutputs_lo_hi_87, decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_84 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_88 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_88 = {decoder_decoded_andMatrixOutputs_hi_hi_88, decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_88 = {decoder_decoded_andMatrixOutputs_hi_88, decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_189_2 = &_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_78 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_88 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_89 = {decoder_decoded_andMatrixOutputs_lo_hi_88, decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_85 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_89 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_89 = {decoder_decoded_andMatrixOutputs_hi_hi_89, decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_89 = {decoder_decoded_andMatrixOutputs_hi_89, decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_28_2 = &_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_79 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_89 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_90 = {decoder_decoded_andMatrixOutputs_lo_hi_89, decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_86 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_90 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_90 = {decoder_decoded_andMatrixOutputs_hi_hi_90, decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_90 = {decoder_decoded_andMatrixOutputs_hi_90, decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_80 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_27, decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_90 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_91 = {decoder_decoded_andMatrixOutputs_lo_hi_90, decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_87 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_91 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_91 = {decoder_decoded_andMatrixOutputs_hi_hi_91, decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_91 = {decoder_decoded_andMatrixOutputs_hi_91, decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_59_2 = &_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_81 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_91 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_92 = {decoder_decoded_andMatrixOutputs_lo_hi_91, decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_88 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_92 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_92 = {decoder_decoded_andMatrixOutputs_hi_hi_92, decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_92 = {decoder_decoded_andMatrixOutputs_hi_92, decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_43_2 = &_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_82 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_92 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_93 = {decoder_decoded_andMatrixOutputs_lo_hi_92, decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_89 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_93 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_93 = {decoder_decoded_andMatrixOutputs_hi_hi_93, decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_93 = {decoder_decoded_andMatrixOutputs_hi_93, decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_169_2 = &_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_83 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_93 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_94 = {decoder_decoded_andMatrixOutputs_lo_hi_93, decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_90 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_94 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_94 = {decoder_decoded_andMatrixOutputs_hi_hi_94, decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_94 = {decoder_decoded_andMatrixOutputs_hi_94, decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_164_2 = &_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_84 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_94 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_95 = {decoder_decoded_andMatrixOutputs_lo_hi_94, decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_91 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_95 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_95 = {decoder_decoded_andMatrixOutputs_hi_hi_95, decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_95 = {decoder_decoded_andMatrixOutputs_hi_95, decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_137_2 = &_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_13, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_85 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_95 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_96 = {decoder_decoded_andMatrixOutputs_lo_hi_95, decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_92 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_96 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_96 = {decoder_decoded_andMatrixOutputs_hi_hi_96, decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_96 = {decoder_decoded_andMatrixOutputs_hi_96, decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_73_2 = &_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_86 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_96 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_97 = {decoder_decoded_andMatrixOutputs_lo_hi_96, decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_93 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_97 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_97 = {decoder_decoded_andMatrixOutputs_hi_hi_97, decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_97 = {decoder_decoded_andMatrixOutputs_hi_97, decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_58_2 = &_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_87 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_97 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] decoder_decoded_andMatrixOutputs_lo_98 = {decoder_decoded_andMatrixOutputs_lo_hi_97, decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_94 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_98 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_98 = {decoder_decoded_andMatrixOutputs_hi_hi_98, decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _decoder_decoded_andMatrixOutputs_T_98 = {decoder_decoded_andMatrixOutputs_hi_98, decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_152_2 = &_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_88 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_98 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_99 = {decoder_decoded_andMatrixOutputs_lo_hi_98, decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_95 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_99 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_99 = {decoder_decoded_andMatrixOutputs_hi_hi_99, decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_99 = {decoder_decoded_andMatrixOutputs_hi_99, decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_161_2 = &_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_lo_89 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_99 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_lo_100 = {decoder_decoded_andMatrixOutputs_lo_hi_99, decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_96 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_100 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_100 = {decoder_decoded_andMatrixOutputs_hi_hi_100, decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [31:0] _decoder_decoded_andMatrixOutputs_T_100 = {decoder_decoded_andMatrixOutputs_hi_100, decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_112_2 = &_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_18, decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_90 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_100 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_101 = {decoder_decoded_andMatrixOutputs_lo_hi_100, decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_97 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_101 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_101 = {decoder_decoded_andMatrixOutputs_hi_hi_101, decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_101 = {decoder_decoded_andMatrixOutputs_hi_101, decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_82_2 = &_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_29 = decoder_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_38, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_91 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_101 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_102 = {decoder_decoded_andMatrixOutputs_lo_hi_101, decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_98 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_102 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_102 = {decoder_decoded_andMatrixOutputs_hi_hi_102, decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_102 = {decoder_decoded_andMatrixOutputs_hi_102, decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_31_2 = &_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_20, decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_92 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_102 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_103 = {decoder_decoded_andMatrixOutputs_lo_hi_102, decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_99 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_103 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_103 = {decoder_decoded_andMatrixOutputs_hi_hi_103, decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_103 = {decoder_decoded_andMatrixOutputs_hi_103, decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_13_2 = &_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_93 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_40, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_103 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_104 = {decoder_decoded_andMatrixOutputs_lo_hi_103, decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_100 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_104 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_104 = {decoder_decoded_andMatrixOutputs_hi_hi_104, decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_104 = {decoder_decoded_andMatrixOutputs_hi_104, decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_110_2 = &_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_94 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_104 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_105 = {decoder_decoded_andMatrixOutputs_lo_hi_104, decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_101 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_105 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_105 = {decoder_decoded_andMatrixOutputs_hi_hi_105, decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_105 = {decoder_decoded_andMatrixOutputs_hi_105, decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_64_2 = &_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_95 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_105 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_106 = {decoder_decoded_andMatrixOutputs_lo_hi_105, decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_102 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_106 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_106 = {decoder_decoded_andMatrixOutputs_hi_hi_106, decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_106 = {decoder_decoded_andMatrixOutputs_hi_106, decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_124_2 = &_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_96 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_106 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_107 = {decoder_decoded_andMatrixOutputs_lo_hi_106, decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_103 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_107 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_77, decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_107 = {decoder_decoded_andMatrixOutputs_hi_hi_107, decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_107 = {decoder_decoded_andMatrixOutputs_hi_107, decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_49_2 = &_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_97 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_107 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_108 = {decoder_decoded_andMatrixOutputs_lo_hi_107, decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_104 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_108 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_78, decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_108 = {decoder_decoded_andMatrixOutputs_hi_hi_108, decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_108 = {decoder_decoded_andMatrixOutputs_hi_108, decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_98 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_108 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_109 = {decoder_decoded_andMatrixOutputs_lo_hi_108, decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_105 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_109 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_79, decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_109 = {decoder_decoded_andMatrixOutputs_hi_hi_109, decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_109 = {decoder_decoded_andMatrixOutputs_hi_109, decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_134_2 = &_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_99 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_109 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_110 = {decoder_decoded_andMatrixOutputs_lo_hi_109, decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_106 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_110 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_80, decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_110 = {decoder_decoded_andMatrixOutputs_hi_hi_110, decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_110 = {decoder_decoded_andMatrixOutputs_hi_110, decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_153_2 = &_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_100 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_110 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_111 = {decoder_decoded_andMatrixOutputs_lo_hi_110, decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_107 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_111 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_81, decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_111 = {decoder_decoded_andMatrixOutputs_hi_hi_111, decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_111 = {decoder_decoded_andMatrixOutputs_hi_111, decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_107_2 = &_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_101 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_111 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_112 = {decoder_decoded_andMatrixOutputs_lo_hi_111, decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_108 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_112 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_82, decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_112 = {decoder_decoded_andMatrixOutputs_hi_hi_112, decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_112 = {decoder_decoded_andMatrixOutputs_hi_112, decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_187_2 = &_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_102 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_112 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_113 = {decoder_decoded_andMatrixOutputs_lo_hi_112, decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_109 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_113 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_83, decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_113 = {decoder_decoded_andMatrixOutputs_hi_hi_113, decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_113 = {decoder_decoded_andMatrixOutputs_hi_113, decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_46_2 = &_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_103 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_113 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_114 = {decoder_decoded_andMatrixOutputs_lo_hi_113, decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_110 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_114 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_84, decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_114 = {decoder_decoded_andMatrixOutputs_hi_hi_114, decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_114 = {decoder_decoded_andMatrixOutputs_hi_114, decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_78_2 = &_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_104 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_114 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_115 = {decoder_decoded_andMatrixOutputs_lo_hi_114, decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_111 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_115 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_115 = {decoder_decoded_andMatrixOutputs_hi_hi_115, decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_115 = {decoder_decoded_andMatrixOutputs_hi_115, decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_159_2 = &_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_105 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_115 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_116 = {decoder_decoded_andMatrixOutputs_lo_hi_115, decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_112 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_116 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_86, decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_116 = {decoder_decoded_andMatrixOutputs_hi_hi_116, decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_116 = {decoder_decoded_andMatrixOutputs_hi_116, decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_34_2 = &_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_106 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_116 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_117 = {decoder_decoded_andMatrixOutputs_lo_hi_116, decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_113 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_117 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_87, decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_117 = {decoder_decoded_andMatrixOutputs_hi_hi_117, decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_117 = {decoder_decoded_andMatrixOutputs_hi_117, decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_85_2 = &_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_107 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_117 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_68, decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_118 = {decoder_decoded_andMatrixOutputs_lo_hi_117, decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_114 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_118 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_88, decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_118 = {decoder_decoded_andMatrixOutputs_hi_hi_118, decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_118 = {decoder_decoded_andMatrixOutputs_hi_118, decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_10_2 = &_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_108 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_118 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_69, decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_119 = {decoder_decoded_andMatrixOutputs_lo_hi_118, decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_115 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_119 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_89, decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_119 = {decoder_decoded_andMatrixOutputs_hi_hi_119, decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_119 = {decoder_decoded_andMatrixOutputs_hi_119, decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_92_2 = &_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_109 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_14_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_119 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_70, decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_120 = {decoder_decoded_andMatrixOutputs_lo_hi_119, decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_116 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_120 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_90, decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_120 = {decoder_decoded_andMatrixOutputs_hi_hi_120, decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_120 = {decoder_decoded_andMatrixOutputs_hi_120, decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_180_2 = &_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_110 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_120 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_71, decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_121 = {decoder_decoded_andMatrixOutputs_lo_hi_120, decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_117 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_121 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_91, decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_121 = {decoder_decoded_andMatrixOutputs_hi_hi_121, decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_121 = {decoder_decoded_andMatrixOutputs_hi_121, decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_44_2 = &_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_50, decoder_decoded_andMatrixOutputs_andMatrixInput_15_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_111 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_121 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_72, decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_122 = {decoder_decoded_andMatrixOutputs_lo_hi_121, decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_118 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_122 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_92, decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_122 = {decoder_decoded_andMatrixOutputs_hi_hi_122, decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_122 = {decoder_decoded_andMatrixOutputs_hi_122, decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_135_2 = &_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, decoder_decoded_andMatrixOutputs_andMatrixInput_14_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_112 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_122 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_73, decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_123 = {decoder_decoded_andMatrixOutputs_lo_hi_122, decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_119 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_123 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_93, decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_123 = {decoder_decoded_andMatrixOutputs_hi_hi_123, decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_123 = {decoder_decoded_andMatrixOutputs_hi_123, decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_113 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_123 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_74, decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_124 = {decoder_decoded_andMatrixOutputs_lo_hi_123, decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_120 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_124 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_94, decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_124 = {decoder_decoded_andMatrixOutputs_hi_hi_124, decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_124 = {decoder_decoded_andMatrixOutputs_hi_124, decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_188_2 = &_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_114 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_124 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_75, decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_125 = {decoder_decoded_andMatrixOutputs_lo_hi_124, decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_121 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_125 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_95, decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_125 = {decoder_decoded_andMatrixOutputs_hi_hi_125, decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_125 = {decoder_decoded_andMatrixOutputs_hi_125, decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_54, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_115 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_125 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_76, decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_126 = {decoder_decoded_andMatrixOutputs_lo_hi_125, decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_122 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_126 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_96, decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_126 = {decoder_decoded_andMatrixOutputs_hi_hi_126, decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_126 = {decoder_decoded_andMatrixOutputs_hi_126, decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_25_2 = &_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_116 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_71, decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_126 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_127 = {decoder_decoded_andMatrixOutputs_lo_hi_126, decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_123 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_127 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_97, decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_127 = {decoder_decoded_andMatrixOutputs_hi_hi_127, decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_127 = {decoder_decoded_andMatrixOutputs_hi_127, decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_57_2 = &_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_117 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_72, decoder_decoded_andMatrixOutputs_andMatrixInput_14_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_127 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_78, decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_128 = {decoder_decoded_andMatrixOutputs_lo_hi_127, decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_124 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_128 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_98, decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_128 = {decoder_decoded_andMatrixOutputs_hi_hi_128, decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_128 = {decoder_decoded_andMatrixOutputs_hi_128, decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_147_2 = &_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_56, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_118 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_128 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_79, decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_129 = {decoder_decoded_andMatrixOutputs_lo_hi_128, decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_125 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_129 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_99, decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_129 = {decoder_decoded_andMatrixOutputs_hi_hi_129, decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_129 = {decoder_decoded_andMatrixOutputs_hi_129, decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_27_2 = &_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_119 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_129 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_80, decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_130 = {decoder_decoded_andMatrixOutputs_lo_hi_129, decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_126 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_77, decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_130 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_100, decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_130 = {decoder_decoded_andMatrixOutputs_hi_hi_130, decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_130 = {decoder_decoded_andMatrixOutputs_hi_130, decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_51_2 = &_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_120 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_75, decoder_decoded_andMatrixOutputs_andMatrixInput_14_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_130 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_81, decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_131 = {decoder_decoded_andMatrixOutputs_lo_hi_130, decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_127 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_78, decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_131 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_101, decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_131 = {decoder_decoded_andMatrixOutputs_hi_hi_131, decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_131 = {decoder_decoded_andMatrixOutputs_hi_131, decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_138_2 = &_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_59, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_121 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_76, decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_131 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_82, decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_132 = {decoder_decoded_andMatrixOutputs_lo_hi_131, decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_128 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_79, decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_132 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_102, decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_132 = {decoder_decoded_andMatrixOutputs_hi_hi_132, decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_132 = {decoder_decoded_andMatrixOutputs_hi_132, decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_178_2 = &_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_122 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_14_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_132 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_83, decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_133 = {decoder_decoded_andMatrixOutputs_lo_hi_132, decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_129 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_80, decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_133 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_103, decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_133 = {decoder_decoded_andMatrixOutputs_hi_hi_133, decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_133 = {decoder_decoded_andMatrixOutputs_hi_133, decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_174_2 = &_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_123 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_78, decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_133 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_84, decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_134 = {decoder_decoded_andMatrixOutputs_lo_hi_133, decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_130 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_81, decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_134 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_104, decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_134 = {decoder_decoded_andMatrixOutputs_hi_hi_134, decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_134 = {decoder_decoded_andMatrixOutputs_hi_134, decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_120_2 = &_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_124 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_79, decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_134 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_85, decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_135 = {decoder_decoded_andMatrixOutputs_lo_hi_134, decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_131 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_82, decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_135 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_105, decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_135 = {decoder_decoded_andMatrixOutputs_hi_hi_135, decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_135 = {decoder_decoded_andMatrixOutputs_hi_135, decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_19_2 = &_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_125 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_80, decoder_decoded_andMatrixOutputs_andMatrixInput_14_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_135 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_86, decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_136 = {decoder_decoded_andMatrixOutputs_lo_hi_135, decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_132 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_83, decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_136 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_106, decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_136 = {decoder_decoded_andMatrixOutputs_hi_hi_136, decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_136 = {decoder_decoded_andMatrixOutputs_hi_136, decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_63_2 = &_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_126 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_81, decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_136 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_87, decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_137 = {decoder_decoded_andMatrixOutputs_lo_hi_136, decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_133 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_84, decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_137 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_107, decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_137 = {decoder_decoded_andMatrixOutputs_hi_hi_137, decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_137 = {decoder_decoded_andMatrixOutputs_hi_137, decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_142_2 = &_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_65, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_127 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_82, decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_137 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_88, decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_138 = {decoder_decoded_andMatrixOutputs_lo_hi_137, decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_134 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_85, decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_138 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_108, decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_138 = {decoder_decoded_andMatrixOutputs_hi_hi_138, decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_138 = {decoder_decoded_andMatrixOutputs_hi_138, decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_11_2 = &_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_128 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_83, decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_138 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_89, decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_139 = {decoder_decoded_andMatrixOutputs_lo_hi_138, decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_135 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_86, decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_139 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_109, decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_139 = {decoder_decoded_andMatrixOutputs_hi_hi_139, decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_139 = {decoder_decoded_andMatrixOutputs_hi_139, decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_47_2 = &_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, decoder_decoded_andMatrixOutputs_andMatrixInput_14_67}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_129 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_84, decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_139 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_90, decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_140 = {decoder_decoded_andMatrixOutputs_lo_hi_139, decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_136 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_87, decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_140 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_110, decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_140 = {decoder_decoded_andMatrixOutputs_hi_hi_140, decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_140 = {decoder_decoded_andMatrixOutputs_hi_140, decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_141_2 = &_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, decoder_decoded_andMatrixOutputs_andMatrixInput_15_36}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_130 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_85, decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_140 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_91, decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_141 = {decoder_decoded_andMatrixOutputs_lo_hi_140, decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_137 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_88, decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_141 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_111, decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_141 = {decoder_decoded_andMatrixOutputs_hi_hi_141, decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_141 = {decoder_decoded_andMatrixOutputs_hi_141, decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_114_2 = &_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, decoder_decoded_andMatrixOutputs_andMatrixInput_14_69}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_131 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_86, decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_141 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_92, decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_142 = {decoder_decoded_andMatrixOutputs_lo_hi_141, decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_138 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_89, decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_142 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_112, decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_142 = {decoder_decoded_andMatrixOutputs_hi_hi_142, decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_142 = {decoder_decoded_andMatrixOutputs_hi_142, decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_69_2 = &_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_70, decoder_decoded_andMatrixOutputs_andMatrixInput_15_38}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_132 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_87, decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_142 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_93, decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_143 = {decoder_decoded_andMatrixOutputs_lo_hi_142, decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_139 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_90, decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_143 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_113, decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_143 = {decoder_decoded_andMatrixOutputs_hi_hi_143, decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_143 = {decoder_decoded_andMatrixOutputs_hi_143, decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_71_2 = &_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, decoder_decoded_andMatrixOutputs_andMatrixInput_14_71}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_133 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_88, decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_143 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_94, decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_144 = {decoder_decoded_andMatrixOutputs_lo_hi_143, decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_140 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_91, decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_144 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_114, decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_144 = {decoder_decoded_andMatrixOutputs_hi_hi_144, decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_144 = {decoder_decoded_andMatrixOutputs_hi_144, decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_175_2 = &_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_72, decoder_decoded_andMatrixOutputs_andMatrixInput_15_40}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_134 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_89, decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_144 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_95, decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_145 = {decoder_decoded_andMatrixOutputs_lo_hi_144, decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_141 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_92, decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_145 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_115, decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_145 = {decoder_decoded_andMatrixOutputs_hi_hi_145, decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_145 = {decoder_decoded_andMatrixOutputs_hi_145, decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_80_2 = &_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, decoder_decoded_andMatrixOutputs_andMatrixInput_14_73}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_135 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_90, decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_145 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_96, decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_146 = {decoder_decoded_andMatrixOutputs_lo_hi_145, decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_142 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_93, decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_146 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_116, decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_146 = {decoder_decoded_andMatrixOutputs_hi_hi_146, decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_146 = {decoder_decoded_andMatrixOutputs_hi_146, decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_130_2 = &_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_136 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_91, decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_146 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_97, decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_147 = {decoder_decoded_andMatrixOutputs_lo_hi_146, decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_143 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_94, decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_147 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_117, decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_147 = {decoder_decoded_andMatrixOutputs_hi_hi_147, decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_147 = {decoder_decoded_andMatrixOutputs_hi_147, decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_157_2 = &_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_137 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_92, decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_147 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_98, decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_148 = {decoder_decoded_andMatrixOutputs_lo_hi_147, decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_144 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_95, decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_148 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_118, decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_148 = {decoder_decoded_andMatrixOutputs_hi_hi_148, decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_148 = {decoder_decoded_andMatrixOutputs_hi_148, decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_67_2 = &_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_138 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_93, decoder_decoded_andMatrixOutputs_andMatrixInput_14_76}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_148 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_99, decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_149 = {decoder_decoded_andMatrixOutputs_lo_hi_148, decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_145 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_96, decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_149 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_119, decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_149 = {decoder_decoded_andMatrixOutputs_hi_hi_149, decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_149 = {decoder_decoded_andMatrixOutputs_hi_149, decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_42_2 = &_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_139 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_94, decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_149 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_100, decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_150 = {decoder_decoded_andMatrixOutputs_lo_hi_149, decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_146 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_97, decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_150 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_120, decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_150 = {decoder_decoded_andMatrixOutputs_hi_hi_150, decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_150 = {decoder_decoded_andMatrixOutputs_hi_150, decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_53_2 = &_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_140 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_95, decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_150 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_101, decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_151 = {decoder_decoded_andMatrixOutputs_lo_hi_150, decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_147 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_98, decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_151 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_121, decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_151 = {decoder_decoded_andMatrixOutputs_hi_hi_151, decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_151 = {decoder_decoded_andMatrixOutputs_hi_151, decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_62_2 = &_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_79, decoder_decoded_andMatrixOutputs_andMatrixInput_15_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_141 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_96, decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_151 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_102, decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_152 = {decoder_decoded_andMatrixOutputs_lo_hi_151, decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_148 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_99, decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_152 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_122, decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_152 = {decoder_decoded_andMatrixOutputs_hi_hi_152, decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_152 = {decoder_decoded_andMatrixOutputs_hi_152, decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_68_2 = &_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_46, decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, decoder_decoded_andMatrixOutputs_andMatrixInput_14_80}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_142 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_97, decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_152 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_103, decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_153 = {decoder_decoded_andMatrixOutputs_lo_hi_152, decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_149 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_100, decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_153 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_123, decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_153 = {decoder_decoded_andMatrixOutputs_hi_hi_153, decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_153 = {decoder_decoded_andMatrixOutputs_hi_153, decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_183_2 = &_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_143 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_98, decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_153 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_104, decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_154 = {decoder_decoded_andMatrixOutputs_lo_hi_153, decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_150 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_101, decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_154 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_124, decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_154 = {decoder_decoded_andMatrixOutputs_hi_hi_154, decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_154 = {decoder_decoded_andMatrixOutputs_hi_154, decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_50_2 = &_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, decoder_decoded_andMatrixOutputs_andMatrixInput_15_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_144 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_99, decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_154 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_105, decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_155 = {decoder_decoded_andMatrixOutputs_lo_hi_154, decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_151 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_102, decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_155 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_125, decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_155 = {decoder_decoded_andMatrixOutputs_hi_hi_155, decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_155 = {decoder_decoded_andMatrixOutputs_hi_155, decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_136_2 = &_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_145 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_100, decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_155 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_106, decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_156 = {decoder_decoded_andMatrixOutputs_lo_hi_155, decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_152 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_103, decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_156 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_126, decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_156 = {decoder_decoded_andMatrixOutputs_hi_hi_156, decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_156 = {decoder_decoded_andMatrixOutputs_hi_156, decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_127_2 = &_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_146 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_101, decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_156 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_107, decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_157 = {decoder_decoded_andMatrixOutputs_lo_hi_156, decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_153 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_104, decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_157 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_127, decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_157 = {decoder_decoded_andMatrixOutputs_hi_hi_157, decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_157 = {decoder_decoded_andMatrixOutputs_hi_157, decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_151_2 = &_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_147 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_102, decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_157 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_108, decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_158 = {decoder_decoded_andMatrixOutputs_lo_hi_157, decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_154 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_105, decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_158 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_128, decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_158 = {decoder_decoded_andMatrixOutputs_hi_hi_158, decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_158 = {decoder_decoded_andMatrixOutputs_hi_158, decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_148 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_103, decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_158 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_109, decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_159 = {decoder_decoded_andMatrixOutputs_lo_hi_158, decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_155 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_106, decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_159 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_129, decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_159 = {decoder_decoded_andMatrixOutputs_hi_hi_159, decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_159 = {decoder_decoded_andMatrixOutputs_hi_159, decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_99_2 = &_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_149 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_104, decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_159 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_110, decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_160 = {decoder_decoded_andMatrixOutputs_lo_hi_159, decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_156 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_107, decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_160 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_130, decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_160 = {decoder_decoded_andMatrixOutputs_hi_hi_160, decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_160 = {decoder_decoded_andMatrixOutputs_hi_160, decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_104_2 = &_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_54, decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_150 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_105, decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, decoder_decoded_andMatrixOutputs_andMatrixInput_14_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_160 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_111, decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_161 = {decoder_decoded_andMatrixOutputs_lo_hi_160, decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_157 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_108, decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_161 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_131, decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_161 = {decoder_decoded_andMatrixOutputs_hi_hi_161, decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_161 = {decoder_decoded_andMatrixOutputs_hi_161, decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_186_2 = &_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_151 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_106, decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_89, decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_161 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_112, decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_162 = {decoder_decoded_andMatrixOutputs_lo_hi_161, decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_158 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_109, decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_162 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_132, decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_162 = {decoder_decoded_andMatrixOutputs_hi_hi_162, decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_162 = {decoder_decoded_andMatrixOutputs_hi_162, decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_18_2 = &_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_56, decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_152 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_107, decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_162 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_113, decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_163 = {decoder_decoded_andMatrixOutputs_lo_hi_162, decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_159 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_110, decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_163 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_133, decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_163 = {decoder_decoded_andMatrixOutputs_hi_hi_163, decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_163 = {decoder_decoded_andMatrixOutputs_hi_163, decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_106_2 = &_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_153 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_108, decoder_decoded_andMatrixOutputs_andMatrixInput_14_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_163 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_114, decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_164 = {decoder_decoded_andMatrixOutputs_lo_hi_163, decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_160 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_111, decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_164 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_134, decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_164 = {decoder_decoded_andMatrixOutputs_hi_hi_164, decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_164 = {decoder_decoded_andMatrixOutputs_hi_164, decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_88_2 = &_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_154 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_109, decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_164 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_115, decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_165 = {decoder_decoded_andMatrixOutputs_lo_hi_164, decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_161 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_112, decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_165 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_135, decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_165 = {decoder_decoded_andMatrixOutputs_hi_hi_165, decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_165 = {decoder_decoded_andMatrixOutputs_hi_165, decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_61_2 = &_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_155 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_110, decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_165 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_116, decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_166 = {decoder_decoded_andMatrixOutputs_lo_hi_165, decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_162 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_113, decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_166 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_136, decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_166 = {decoder_decoded_andMatrixOutputs_hi_hi_166, decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_166 = {decoder_decoded_andMatrixOutputs_hi_166, decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_149_2 = &_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_156 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_111, decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_166 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_117, decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_167 = {decoder_decoded_andMatrixOutputs_lo_hi_166, decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_163 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_114, decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_167 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_137, decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_167 = {decoder_decoded_andMatrixOutputs_hi_hi_167, decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_167 = {decoder_decoded_andMatrixOutputs_hi_167, decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_173_2 = &_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_157 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_112, decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_167 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_118, decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_168 = {decoder_decoded_andMatrixOutputs_lo_hi_167, decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_164 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_115, decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_168 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_138, decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_168 = {decoder_decoded_andMatrixOutputs_hi_hi_168, decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_168 = {decoder_decoded_andMatrixOutputs_hi_168, decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_37_2 = &_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_158 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_113, decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_168 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_119, decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_169 = {decoder_decoded_andMatrixOutputs_lo_hi_168, decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_165 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_116, decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_169 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_139, decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_169 = {decoder_decoded_andMatrixOutputs_hi_hi_169, decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_169 = {decoder_decoded_andMatrixOutputs_hi_169, decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_122_2 = &_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_159 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_114, decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_169 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_120, decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_170 = {decoder_decoded_andMatrixOutputs_lo_hi_169, decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_166 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_117, decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_170 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_140, decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_170 = {decoder_decoded_andMatrixOutputs_hi_hi_170, decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_170 = {decoder_decoded_andMatrixOutputs_hi_170, decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_81_2 = &_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_lo_160 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_115, decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_170 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_121, decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_lo_171 = {decoder_decoded_andMatrixOutputs_lo_hi_170, decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_98, decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_167 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_118, decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_171 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_141, decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_171 = {decoder_decoded_andMatrixOutputs_hi_hi_171, decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _decoder_decoded_andMatrixOutputs_T_171 = {decoder_decoded_andMatrixOutputs_hi_171, decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_119_2 = &_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_161 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_116, decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_171 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_122, decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_172 = {decoder_decoded_andMatrixOutputs_lo_hi_171, decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_168 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_119, decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_172 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_142, decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_172 = {decoder_decoded_andMatrixOutputs_hi_hi_172, decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_172 = {decoder_decoded_andMatrixOutputs_hi_172, decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_171_2 = &_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_162 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_117, decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_172 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_123, decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_173 = {decoder_decoded_andMatrixOutputs_lo_hi_172, decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_169 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_120, decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_173 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_143, decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_173 = {decoder_decoded_andMatrixOutputs_hi_hi_173, decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_173 = {decoder_decoded_andMatrixOutputs_hi_173, decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_56_2 = &_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_163 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_118, decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_173 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_124, decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_174 = {decoder_decoded_andMatrixOutputs_lo_hi_173, decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_170 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_121, decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_174 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_144, decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_174 = {decoder_decoded_andMatrixOutputs_hi_hi_174, decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_174 = {decoder_decoded_andMatrixOutputs_hi_174, decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_79_2 = &_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_164 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_119, decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_174 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_125, decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_175 = {decoder_decoded_andMatrixOutputs_lo_hi_174, decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_171 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_122, decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_175 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_145, decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_175 = {decoder_decoded_andMatrixOutputs_hi_hi_175, decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_175 = {decoder_decoded_andMatrixOutputs_hi_175, decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_168_2 = &_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_165 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_120, decoder_decoded_andMatrixOutputs_andMatrixInput_14_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_175 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_126, decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_176 = {decoder_decoded_andMatrixOutputs_lo_hi_175, decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_172 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_123, decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_176 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_146, decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_176 = {decoder_decoded_andMatrixOutputs_hi_hi_176, decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_176 = {decoder_decoded_andMatrixOutputs_hi_176, decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_154_2 = &_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_166 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_121, decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_176 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_127, decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_177 = {decoder_decoded_andMatrixOutputs_lo_hi_176, decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_173 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_124, decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_177 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_147, decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_177 = {decoder_decoded_andMatrixOutputs_hi_hi_177, decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_177 = {decoder_decoded_andMatrixOutputs_hi_177, decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_192_2 = &_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_104, decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_167 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_122, decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_177 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_128, decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_178 = {decoder_decoded_andMatrixOutputs_lo_hi_177, decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_174 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_125, decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_178 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_148, decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_178 = {decoder_decoded_andMatrixOutputs_hi_hi_178, decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_178 = {decoder_decoded_andMatrixOutputs_hi_178, decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_38_2 = &_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_168 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_123, decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_178 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_129, decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_179 = {decoder_decoded_andMatrixOutputs_lo_hi_178, decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_175 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_126, decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_179 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_149, decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_179 = {decoder_decoded_andMatrixOutputs_hi_hi_179, decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_179 = {decoder_decoded_andMatrixOutputs_hi_179, decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_158_2 = &_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_169 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_124, decoder_decoded_andMatrixOutputs_andMatrixInput_14_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_179 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_130, decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_180 = {decoder_decoded_andMatrixOutputs_lo_hi_179, decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_176 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_127, decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_180 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_150, decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_180 = {decoder_decoded_andMatrixOutputs_hi_hi_180, decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_180 = {decoder_decoded_andMatrixOutputs_hi_180, decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_109_2 = &_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_170 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_125, decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_180 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_131, decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_181 = {decoder_decoded_andMatrixOutputs_lo_hi_180, decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_177 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_128, decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_181 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_151, decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_181 = {decoder_decoded_andMatrixOutputs_hi_hi_181, decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_181 = {decoder_decoded_andMatrixOutputs_hi_181, decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_23_2 = &_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_171 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_126, decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_181 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_132, decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_182 = {decoder_decoded_andMatrixOutputs_lo_hi_181, decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_178 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_129, decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_182 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_152, decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_182 = {decoder_decoded_andMatrixOutputs_hi_hi_182, decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_182 = {decoder_decoded_andMatrixOutputs_hi_182, decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_100_2 = &_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_172 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_127, decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_182 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_133, decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_183 = {decoder_decoded_andMatrixOutputs_lo_hi_182, decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_179 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_130, decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_183 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_153, decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_183 = {decoder_decoded_andMatrixOutputs_hi_hi_183, decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_183 = {decoder_decoded_andMatrixOutputs_hi_183, decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_118_2 = &_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_173 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_128, decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_183 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_134, decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_184 = {decoder_decoded_andMatrixOutputs_lo_hi_183, decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_180 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_131, decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_184 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_154, decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_184 = {decoder_decoded_andMatrixOutputs_hi_hi_184, decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_184 = {decoder_decoded_andMatrixOutputs_hi_184, decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_116_2 = &_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_111, decoder_decoded_andMatrixOutputs_andMatrixInput_15_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_174 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_129, decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_184 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_135, decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_185 = {decoder_decoded_andMatrixOutputs_lo_hi_184, decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_181 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_132, decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_185 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_155, decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_185 = {decoder_decoded_andMatrixOutputs_hi_hi_185, decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_185 = {decoder_decoded_andMatrixOutputs_hi_185, decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_156_2 = &_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_175 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_130, decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_185 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_136, decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_186 = {decoder_decoded_andMatrixOutputs_lo_hi_185, decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_182 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_133, decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_186 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_156, decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_186 = {decoder_decoded_andMatrixOutputs_hi_hi_186, decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_186 = {decoder_decoded_andMatrixOutputs_hi_186, decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_113_2 = &_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_176 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_131, decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_186 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_137, decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_187 = {decoder_decoded_andMatrixOutputs_lo_hi_186, decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_183 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_134, decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_187 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_157, decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_187 = {decoder_decoded_andMatrixOutputs_hi_hi_187, decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_187 = {decoder_decoded_andMatrixOutputs_hi_187, decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_105_2 = &_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_177 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_132, decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_187 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_138, decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_188 = {decoder_decoded_andMatrixOutputs_lo_hi_187, decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_184 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_135, decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_188 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_158, decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_188 = {decoder_decoded_andMatrixOutputs_hi_hi_188, decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_188 = {decoder_decoded_andMatrixOutputs_hi_188, decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_83_2 = &_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_74, decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_178 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_133, decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, decoder_decoded_andMatrixOutputs_andMatrixInput_14_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_188 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_139, decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_189 = {decoder_decoded_andMatrixOutputs_lo_hi_188, decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_185 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_136, decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_189 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_159, decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_189 = {decoder_decoded_andMatrixOutputs_hi_hi_189, decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_189 = {decoder_decoded_andMatrixOutputs_hi_189, decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_33_2 = &_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_179 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_134, decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_189 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_140, decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_190 = {decoder_decoded_andMatrixOutputs_lo_hi_189, decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_186 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_137, decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_190 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_160, decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_190 = {decoder_decoded_andMatrixOutputs_hi_hi_190, decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_190 = {decoder_decoded_andMatrixOutputs_hi_190, decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_84_2 = &_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_180 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_135, decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_190 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_141, decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_191 = {decoder_decoded_andMatrixOutputs_lo_hi_190, decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_187 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_138, decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_191 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_161, decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_191 = {decoder_decoded_andMatrixOutputs_hi_hi_191, decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_191 = {decoder_decoded_andMatrixOutputs_hi_191, decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_40_2 = &_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_181 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_136, decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_191 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_142, decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_192 = {decoder_decoded_andMatrixOutputs_lo_hi_191, decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_188 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_139, decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_192 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_162, decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_192 = {decoder_decoded_andMatrixOutputs_hi_hi_192, decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_192 = {decoder_decoded_andMatrixOutputs_hi_192, decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_12_2 = &_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_182 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_137, decoder_decoded_andMatrixOutputs_lo_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_119, decoder_decoded_andMatrixOutputs_andMatrixInput_15_78}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_192 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_143, decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_193 = {decoder_decoded_andMatrixOutputs_lo_hi_192, decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_189 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_140, decoder_decoded_andMatrixOutputs_hi_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_193 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_163, decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_193 = {decoder_decoded_andMatrixOutputs_hi_hi_193, decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_193 = {decoder_decoded_andMatrixOutputs_hi_193, decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_74_2 = &_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_118_2, decoder_decoded_andMatrixOutputs_84_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_114_2, decoder_decoded_andMatrixOutputs_175_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_85_2, decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo = {decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_148_2, decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_2 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_161_2, decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_1 = {decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_155_2, decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_54_2, decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _decoder_decoded_orMatrixOutputs_T_8 = {decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_9 = |_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {decoder_decoded_andMatrixOutputs_83_2, decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoder_decoded_andMatrixOutputs_154_2, decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoder_decoded_andMatrixOutputs_56_2, decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_168_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_99_2, decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_1 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {decoder_decoded_andMatrixOutputs_51_2, decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_23; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_23 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_137_2, decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] decoder_decoded_orMatrixOutputs_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_103_2, decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_2 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoder_decoded_andMatrixOutputs_191_2, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {decoder_decoded_andMatrixOutputs_98_2, decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_hi_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] decoder_decoded_orMatrixOutputs_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _decoder_decoded_orMatrixOutputs_T_10 = {decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_11 = |_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_167_2, decoder_decoded_andMatrixOutputs_108_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_14 = |_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_116_2, decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_2 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_3 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_3 = {decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {decoder_decoded_andMatrixOutputs_153_2, decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_76_2, decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {decoder_decoded_andMatrixOutputs_181_2, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_15 = {decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_16 = |_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_107_2, decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_3 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_4 = {decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_123_2, decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_22_2, decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _decoder_decoded_orMatrixOutputs_T_18 = {decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_19 = |_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_175_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_107_2, decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_124_2, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_20 = {decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_21 = |_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_64_2, decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_128_2, decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _decoder_decoded_orMatrixOutputs_T_22 = {decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_23 = |_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_137_2, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_24 = {decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_25 = |_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_82_2, decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_9 = _GEN_15; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_26 = {decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_27 = |_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_8 = {decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_6 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_101_2, decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _decoder_decoded_orMatrixOutputs_T_30 = {decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_31 = |_decoder_decoded_orMatrixOutputs_T_30; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_142_2, decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_6 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_169_2, decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_102_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_93_2, decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_55_2, decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _decoder_decoded_orMatrixOutputs_T_32 = {decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_33 = |_decoder_decoded_orMatrixOutputs_T_32; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_63_2, decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {decoder_decoded_andMatrixOutputs_138_2, decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_7 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_25_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_10 = {decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_170_2, decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_111_2, decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_39_2, decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _decoder_decoded_orMatrixOutputs_T_34 = {decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_35 = |_decoder_decoded_orMatrixOutputs_T_34; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_150_2, decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_13 = {decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _decoder_decoded_orMatrixOutputs_T_36 = {decoder_decoded_orMatrixOutputs_hi_13, decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_37 = |_decoder_decoded_orMatrixOutputs_T_36; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_9 = {decoder_decoded_andMatrixOutputs_53_2, decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_147_2, decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_10 = {decoder_decoded_andMatrixOutputs_43_2, decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_129_2, decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_14 = {decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _decoder_decoded_orMatrixOutputs_T_38 = {decoder_decoded_orMatrixOutputs_hi_14, decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_39 = |_decoder_decoded_orMatrixOutputs_T_38; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_173_2, decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {decoder_decoded_andMatrixOutputs_106_2, decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {decoder_decoded_andMatrixOutputs_104_2, decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_11 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_lo_13 = {decoder_decoded_orMatrixOutputs_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_11 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_15 = {decoder_decoded_orMatrixOutputs_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _decoder_decoded_orMatrixOutputs_T_40 = {decoder_decoded_orMatrixOutputs_hi_15, decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_41 = |_decoder_decoded_orMatrixOutputs_T_40; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_151_2, decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_135_2, decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_lo_11 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_82_2, decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_189_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_12 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_lo_14 = {decoder_decoded_orMatrixOutputs_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_162_2, decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_155_2, decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_121_2, decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_12 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_165_2, decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_7_2, decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_77_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_13 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_16 = {decoder_decoded_orMatrixOutputs_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _decoder_decoded_orMatrixOutputs_T_42 = {decoder_decoded_orMatrixOutputs_hi_16, decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_43 = |_decoder_decoded_orMatrixOutputs_T_42; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_44 = {decoder_decoded_orMatrixOutputs_hi_17, decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_45 = |_decoder_decoded_orMatrixOutputs_T_44; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_46 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_47 = |_decoder_decoded_orMatrixOutputs_T_46; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_99_2, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_42_2, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_12 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {decoder_decoded_andMatrixOutputs_188_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_13 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_16 = {decoder_decoded_orMatrixOutputs_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_90_2, decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_13 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_191_2, decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_14 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_18 = {decoder_decoded_orMatrixOutputs_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _decoder_decoded_orMatrixOutputs_T_48 = {decoder_decoded_orMatrixOutputs_hi_18, decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_49 = |_decoder_decoded_orMatrixOutputs_T_48; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {decoder_decoded_andMatrixOutputs_122_2, decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_13 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_14 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_lo_17 = {decoder_decoded_orMatrixOutputs_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {decoder_decoded_andMatrixOutputs_8_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {decoder_decoded_andMatrixOutputs_103_2, decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_14 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {decoder_decoded_andMatrixOutputs_97_2, decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {decoder_decoded_andMatrixOutputs_95_2, decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_15 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_hi_19 = {decoder_decoded_orMatrixOutputs_hi_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _decoder_decoded_orMatrixOutputs_T_50 = {decoder_decoded_orMatrixOutputs_hi_19, decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_51 = |_decoder_decoded_orMatrixOutputs_T_50; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_18 = {decoder_decoded_orMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_182_2, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_20 = {decoder_decoded_orMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _decoder_decoded_orMatrixOutputs_T_52 = {decoder_decoded_orMatrixOutputs_hi_20, decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_53 = |_decoder_decoded_orMatrixOutputs_T_52; // @[pla.scala:114:{19,36}] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_120_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_14 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_180_2, decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_16 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_lo_19 = {decoder_decoded_orMatrixOutputs_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {decoder_decoded_andMatrixOutputs_140_2, decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_15 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_hi_17 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] decoder_decoded_orMatrixOutputs_hi_21 = {decoder_decoded_orMatrixOutputs_hi_hi_17, decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _decoder_decoded_orMatrixOutputs_T_54 = {decoder_decoded_orMatrixOutputs_hi_21, decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_55 = |_decoder_decoded_orMatrixOutputs_T_54; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_88_2, decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_142_2, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_lo_15 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {decoder_decoded_andMatrixOutputs_159_2, decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_146_2, decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_17 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_20 = {decoder_decoded_orMatrixOutputs_lo_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_126_2, decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_16 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_190_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_18 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_15, decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_22 = {decoder_decoded_orMatrixOutputs_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _decoder_decoded_orMatrixOutputs_T_56 = {decoder_decoded_orMatrixOutputs_hi_22, decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_57 = |_decoder_decoded_orMatrixOutputs_T_56; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_67_2, decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_58 = {decoder_decoded_orMatrixOutputs_hi_23, decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_59 = |_decoder_decoded_orMatrixOutputs_T_58; // @[pla.scala:114:{19,36}] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_16 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_18 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_15, decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_lo_22 = {decoder_decoded_orMatrixOutputs_lo_hi_18, decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_17 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_19 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_16, decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_hi_24 = {decoder_decoded_orMatrixOutputs_hi_hi_19, decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _decoder_decoded_orMatrixOutputs_T_60 = {decoder_decoded_orMatrixOutputs_hi_24, decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_61 = |_decoder_decoded_orMatrixOutputs_T_60; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_17 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_19 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_23 = {decoder_decoded_orMatrixOutputs_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {decoder_decoded_andMatrixOutputs_162_2, decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_18 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_128_2, decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_20 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_17, decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_25 = {decoder_decoded_orMatrixOutputs_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _decoder_decoded_orMatrixOutputs_T_62 = {decoder_decoded_orMatrixOutputs_hi_25, decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_63 = |_decoder_decoded_orMatrixOutputs_T_62; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_66 = {decoder_decoded_andMatrixOutputs_96_2, decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_67 = |_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {decoder_decoded_andMatrixOutputs_158_2, decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_136_2, decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_18 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_130_2, decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_141_2, decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_175_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_20 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_17, decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_lo_24 = {decoder_decoded_orMatrixOutputs_lo_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_19 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_176_2, decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_21 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_26 = {decoder_decoded_orMatrixOutputs_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _decoder_decoded_orMatrixOutputs_T_68 = {decoder_decoded_orMatrixOutputs_hi_26, decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_69 = |_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoder_decoded_andMatrixOutputs_113_2, decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_122_2, decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_130_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_lo_19 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_174_2, decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_110_2, decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_hi_21 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] decoder_decoded_orMatrixOutputs_lo_25 = {decoder_decoded_orMatrixOutputs_lo_hi_21, decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoder_decoded_andMatrixOutputs_152_2, decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoder_decoded_andMatrixOutputs_28_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_94_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_hi_lo_20 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_17, decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoder_decoded_andMatrixOutputs_89_2, decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_131_2, decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoder_decoded_andMatrixOutputs_20_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoder_decoded_andMatrixOutputs_117_2, decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_hi_22 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_19, decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] decoder_decoded_orMatrixOutputs_hi_27 = {decoder_decoded_orMatrixOutputs_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _decoder_decoded_orMatrixOutputs_T_70 = {decoder_decoded_orMatrixOutputs_hi_27, decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_71 = |_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_decoder_decoded_orMatrixOutputs_T_6, _decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {_decoder_decoded_orMatrixOutputs_T_14, _decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] decoder_decoded_orMatrixOutputs_lo_lo_20 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_decoder_decoded_orMatrixOutputs_T_17, _decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_decoder_decoded_orMatrixOutputs_T_23, _decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_decoder_decoded_orMatrixOutputs_T_33, _decoder_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_22 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_19, decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] decoder_decoded_orMatrixOutputs_lo_26 = {decoder_decoded_orMatrixOutputs_lo_hi_22, decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_decoder_decoded_orMatrixOutputs_T_37, _decoder_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_decoder_decoded_orMatrixOutputs_T_43, _decoder_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_decoder_decoded_orMatrixOutputs_T_47, _decoder_decoded_orMatrixOutputs_T_45}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_decoder_decoded_orMatrixOutputs_T_53, _decoder_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _decoder_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] decoder_decoded_orMatrixOutputs_hi_lo_21 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_decoder_decoded_orMatrixOutputs_T_57, _decoder_decoded_orMatrixOutputs_T_55}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_decoder_decoded_orMatrixOutputs_T_63, _decoder_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _decoder_decoded_orMatrixOutputs_T_59}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_decoder_decoded_orMatrixOutputs_T_67, _decoder_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_decoder_decoded_orMatrixOutputs_T_71, _decoder_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_23 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] decoder_decoded_orMatrixOutputs_hi_28 = {decoder_decoded_orMatrixOutputs_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi_28, decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_16 = decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_17 = decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_18 = decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_19 = decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_20 = decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_21 = decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_22 = decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_23 = decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_24 = decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_25 = decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_26 = decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_27 = decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_28 = decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_29 = decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_30 = decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_31 = decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_32 = decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_33 = decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_34 = decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_35 = decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_36 = decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_37 = decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_38 = decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_39 = decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_40 = decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_41 = decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_4, _decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_6, _decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_9, _decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_11, _decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_14, _decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_decoder_decoded_invMatrixOutputs_T_17, _decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_20, _decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_22, _decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_25, _decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_27, _decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_30, _decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_32, _decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_35, _decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_decoder_decoded_invMatrixOutputs_T_38, _decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_41, _decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoder_0 = decoder_decoded[41]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_legal = decoder_0; // @[Core.scala:70:22] assign decoder_1 = decoder_decoded[40]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_fp = decoder_1; // @[Core.scala:70:22] assign decoder_2 = decoder_decoded[39]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rocc = decoder_2; // @[Core.scala:70:22] assign decoder_3 = decoder_decoded[38]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_branch = decoder_3; // @[Core.scala:70:22] assign decoder_4 = decoder_decoded[37]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_jal = decoder_4; // @[Core.scala:70:22] assign decoder_5 = decoder_decoded[36]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_jalr = decoder_5; // @[Core.scala:70:22] assign decoder_6 = decoder_decoded[35]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rxs2 = decoder_6; // @[Core.scala:70:22] assign decoder_7 = decoder_decoded[34]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rxs1 = decoder_7; // @[Core.scala:70:22] wire [2:0] decoder_8 = decoder_decoded[33:31]; // @[pla.scala:81:23] wire [1:0] decoder_9 = decoder_decoded[30:29]; // @[pla.scala:81:23] assign decoder_10 = decoder_decoded[28:26]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_sel_imm = decoder_10; // @[Core.scala:70:22] wire decoder_11 = decoder_decoded[25]; // @[pla.scala:81:23] wire [4:0] decoder_12 = decoder_decoded[24:20]; // @[pla.scala:81:23] assign decoder_13 = decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_mem = decoder_13; // @[Core.scala:70:22] assign decoder_14 = decoder_decoded[18:14]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_mem_cmd = decoder_14; // @[Core.scala:70:22] assign decoder_15 = decoder_decoded[13]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rfs1 = decoder_15; // @[Core.scala:70:22] assign decoder_16 = decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rfs2 = decoder_16; // @[Core.scala:70:22] assign decoder_17 = decoder_decoded[11]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_rfs3 = decoder_17; // @[Core.scala:70:22] assign decoder_18 = decoder_decoded[10]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_wfd = decoder_18; // @[Core.scala:70:22] assign decoder_19 = decoder_decoded[9]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_mul = decoder_19; // @[Core.scala:70:22] assign decoder_20 = decoder_decoded[8]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_div = decoder_20; // @[Core.scala:70:22] assign decoder_21 = decoder_decoded[7]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_wxd = decoder_21; // @[Core.scala:70:22] assign decoder_22 = decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_csr = decoder_22; // @[Core.scala:70:22] assign decoder_23 = decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_fence_i = decoder_23; // @[Core.scala:70:22] assign decoder_24 = decoder_decoded[2]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_fence = decoder_24; // @[Core.scala:70:22] assign decoder_25 = decoder_decoded[1]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_amo = decoder_25; // @[Core.scala:70:22] assign decoder_26 = decoder_decoded[0]; // @[pla.scala:81:23] assign rrd_uops_0_bits_ctrl_dp = decoder_26; // @[Core.scala:70:22] wire [31:0] _rrd_uops_0_bits_sets_vcfg_T = io_imem_resp_0_bits_inst_0 & 32'h8000707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_0_bits_sets_vcfg_T_1 = _rrd_uops_0_bits_sets_vcfg_T == 32'h7057; // @[Core.scala:186:101] wire [31:0] _rrd_uops_0_bits_sets_vcfg_T_2 = io_imem_resp_0_bits_inst_0 & 32'hC000707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_0_bits_sets_vcfg_T_3 = _rrd_uops_0_bits_sets_vcfg_T_2 == 32'hC0007057; // @[Core.scala:186:101] wire [31:0] _rrd_uops_0_bits_sets_vcfg_T_4 = io_imem_resp_0_bits_inst_0 & 32'hFE00707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_0_bits_sets_vcfg_T_5 = _rrd_uops_0_bits_sets_vcfg_T_4 == 32'h80007057; // @[Core.scala:186:101] wire _rrd_uops_0_bits_sets_vcfg_T_6 = _rrd_uops_0_bits_sets_vcfg_T_1 | _rrd_uops_0_bits_sets_vcfg_T_3; // @[Core.scala:186:101] wire _rrd_uops_0_bits_sets_vcfg_T_7 = _rrd_uops_0_bits_sets_vcfg_T_6 | _rrd_uops_0_bits_sets_vcfg_T_5; // @[Core.scala:186:101] wire [31:0] decoder_decoded_invInputs_1 = ~decoder_decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [41:0] decoder_decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [41:0] decoder_decoded_1; // @[pla.scala:81:23] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_194 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_195 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_196 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_197 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_198 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_199 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_200 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_201 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_202 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_203 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_204 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_205 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_206 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_207 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_208 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_209 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_210 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_211 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_212 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_213 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_214 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_215 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_216 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_217 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_218 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_219 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_220 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_221 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_222 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_223 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_224 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_225 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_226 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_227 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_228 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_229 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_230 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_231 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_232 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_233 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_234 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_235 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_236 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_237 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_238 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_239 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_240 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_241 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_242 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_243 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_244 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_245 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_246 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_247 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_248 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_249 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_250 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_251 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_252 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_253 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_254 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_255 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_256 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_257 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_258 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_259 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_260 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_261 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_262 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_263 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_264 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_265 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_266 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_267 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_268 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_269 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_270 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_271 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_272 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_273 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_274 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_275 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_276 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_277 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_278 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_279 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_280 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_281 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_282 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_283 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_284 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_285 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_286 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_287 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_288 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_289 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_290 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_291 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_292 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_294 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_295 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_296 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_297 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_298 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_299 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_300 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_301 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_302 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_303 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_304 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_305 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_306 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_307 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_308 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_309 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_310 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_311 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_312 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_313 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_314 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_315 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_316 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_317 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_318 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_319 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_320 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_321 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_322 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_323 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_324 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_325 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_326 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_327 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_328 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_329 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_330 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_331 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_332 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_333 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_334 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_335 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_336 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_337 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_338 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_339 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_340 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_341 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_342 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_343 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_344 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_345 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_346 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_347 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_348 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_349 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_350 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_351 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_352 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_353 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_354 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_355 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_356 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_357 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_358 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_359 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_360 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_361 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_362 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_363 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_365 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_366 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_367 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_368 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_369 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_370 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_371 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_372 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_373 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_374 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_375 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_376 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_377 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_378 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_379 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_380 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_381 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_382 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_383 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_384 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_385 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_386 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_387 = decoder_decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_194 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_195 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_196 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_197 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_198 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_199 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_200 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_201 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_202 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_203 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_204 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_205 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_206 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_207 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_208 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_209 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_210 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_211 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_212 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_213 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_214 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_215 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_216 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_217 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_218 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_219 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_220 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_222 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_223 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_224 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_225 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_226 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_227 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_228 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_229 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_230 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_231 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_232 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_233 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_234 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_235 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_236 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_237 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_238 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_239 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_240 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_241 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_242 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_243 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_244 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_245 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_246 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_247 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_248 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_249 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_250 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_251 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_252 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_253 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_254 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_255 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_256 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_257 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_258 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_259 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_260 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_261 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_262 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_263 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_264 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_265 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_266 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_267 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_268 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_269 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_270 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_271 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_272 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_273 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_274 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_275 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_276 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_277 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_278 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_279 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_280 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_281 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_282 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_283 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_284 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_285 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_286 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_287 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_288 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_289 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_290 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_292 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_294 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_295 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_296 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_297 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_298 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_299 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_300 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_301 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_302 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_303 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_304 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_305 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_306 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_307 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_308 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_309 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_310 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_311 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_312 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_313 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_314 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_315 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_316 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_317 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_318 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_319 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_320 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_321 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_322 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_323 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_324 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_325 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_326 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_327 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_328 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_329 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_330 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_331 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_332 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_333 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_334 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_335 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_336 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_337 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_338 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_339 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_340 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_341 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_342 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_343 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_344 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_345 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_346 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_347 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_348 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_349 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_350 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_351 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_352 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_353 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_354 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_355 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_356 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_357 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_358 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_359 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_360 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_361 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_362 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_363 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_365 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_366 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_367 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_368 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_369 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_370 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_371 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_372 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_373 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_374 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_375 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_376 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_377 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_378 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_379 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_380 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_381 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_382 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_383 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_384 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_385 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_386 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_387 = decoder_decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_194 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_195 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_196 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_197 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_198 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_200 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_203 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_204 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_205 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_206 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_207 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_208 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_209 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_210 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_214 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_215 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_216 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_217 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_222 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_228 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_229 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_230 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_231 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_234 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_235 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_236 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_237 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_242 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_243 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_247 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_248 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_249 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_250 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_252 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_253 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_254 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_255 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_256 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_257 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_258 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_259 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_260 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_261 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_262 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_263 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_264 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_265 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_266 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_267 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_268 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_269 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_270 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_271 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_272 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_273 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_275 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_276 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_277 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_278 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_279 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_280 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_281 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_282 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_283 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_285 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_286 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_287 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_288 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_292 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_294 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_295 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_296 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_297 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_298 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_300 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_301 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_302 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_303 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_304 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_305 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_306 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_307 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_309 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_310 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_311 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_312 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_313 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_314 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_315 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_316 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_317 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_318 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_319 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_320 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_322 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_323 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_324 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_325 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_326 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_327 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_328 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_329 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_330 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_331 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_332 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_333 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_334 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_335 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_336 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_337 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_338 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_339 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_340 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_341 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_342 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_343 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_344 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_345 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_346 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_347 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_348 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_349 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_350 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_351 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_352 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_353 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_354 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_355 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_356 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_357 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_358 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_359 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_360 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_361 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_362 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_363 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_365 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_367 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_368 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_369 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_370 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_371 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_372 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_373 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_374 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_375 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_376 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_377 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_378 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_379 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_380 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_381 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_382 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_383 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_384 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_385 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_386 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_387 = decoder_decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_194 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_195 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_196 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_197 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_198 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_201 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_202 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_203 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_204 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_205 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_207 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_214 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_215 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_216 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_217 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_218 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_219 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_222 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_223 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_224 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_225 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_226 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_228 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_229 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_232 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_233 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_234 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_235 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_236 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_237 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_238 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_239 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_240 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_241 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_242 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_243 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_244 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_245 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_247 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_248 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_249 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_250 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_251 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_252 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_253 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_254 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_255 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_256 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_257 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_258 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_262 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_263 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_264 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_265 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_266 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_267 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_268 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_269 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_270 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_271 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_272 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_275 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_276 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_277 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_278 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_286 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_287 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_288 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_292 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_294 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_295 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_296 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_297 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_298 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_300 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_301 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_302 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_303 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_304 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_305 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_306 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_307 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_311 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_312 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_313 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_314 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_315 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_316 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_317 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_318 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_319 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_322 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_323 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_324 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_325 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_326 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_331 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_332 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_333 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_334 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_335 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_336 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_337 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_338 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_339 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_340 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_341 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_342 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_343 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_344 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_345 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_346 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_347 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_348 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_349 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_350 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_351 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_354 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_356 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_359 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_361 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_363 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_365 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_367 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_368 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_369 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_370 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_371 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_372 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_373 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_374 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_375 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_376 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_377 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_378 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_379 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_380 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_381 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_382 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_383 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_384 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_385 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_386 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_387 = decoder_decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_194 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_194 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_195 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_197 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_198 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_200 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_201 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_211 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_212 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_213 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_212 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_213 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_224 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_224 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_225 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_227 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_229 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_239 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_239 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_240 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_241 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_250 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_252 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_264 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_269 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_274 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_273 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_281 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_298 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_299 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_300 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_301 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_302 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_303 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_304 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_305 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_309 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_310 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_311 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_312 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_313 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_316 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_322 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_323 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_324 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_326 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_332 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_333 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_334 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_335 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_336 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_337 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_338 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_339 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_340 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_341 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_342 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_346 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_347 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_348 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_349 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_352 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_353 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_352 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_355 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_354 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_357 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_359 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_361 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_365 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_366 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_367 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_368 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_369 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_370 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_371 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_372 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_373 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_374 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_375 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_376 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_377 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_378 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_379 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_380 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_381 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_382 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_383 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_384 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_385 = decoder_decoded_invInputs_1[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_193 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_191 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_192 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_196 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_194 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_195 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_199 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_200 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_197 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_198 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_200 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_205 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_202 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_207 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_208 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_205 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_223 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_222 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_223 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_218 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_219 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_226 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_221 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_228 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_223 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_230 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_225 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_238 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_237 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_238 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_233 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_234 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_235 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_242 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_237 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_238 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_239 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_240 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_249 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_244 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_245 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_246 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_247 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_248 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_256 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_257 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_258 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_259 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_254 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_258 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_259 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_263 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_264 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_271 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_268 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_269 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_270 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_277 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_278 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_279 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_274 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_275 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_276 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_277 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_278 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_279 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_280 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_281 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_282 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_291 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_300 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_307 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_308 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_306 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_307 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_308 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_309 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_310 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_311 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_318 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_313 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_314 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_315 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_316 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_317 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_318 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_325 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_320 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_327 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_328 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_323 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_324 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_325 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_334 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_335 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_336 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_337 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_338 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_339 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_343 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_350 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_351 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_346 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_353 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_348 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_355 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_356 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_351 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_358 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_353 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_360 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_355 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_358 = decoder_decoded_invInputs_1[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_190 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_183 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_196 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_190 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_201 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_203 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_195 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_210 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_201 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_153 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_141 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_233 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_265 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_260 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_263 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_191 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_175 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_233 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_177 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_191 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_181 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_278 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_280 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_284 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_285 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_301 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_302 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_289 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_297 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_312 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_301 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_311 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_304 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_246 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_345 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_347 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_358 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_359 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_362 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_364 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_365 = decoder_decoded_invInputs_1[12]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_194, decoder_decoded_andMatrixOutputs_andMatrixInput_5_193}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_194 = {decoder_decoded_andMatrixOutputs_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_6_190}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_194, decoder_decoded_andMatrixOutputs_andMatrixInput_3_194}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_194, decoder_decoded_andMatrixOutputs_andMatrixInput_1_194}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_194 = {decoder_decoded_andMatrixOutputs_hi_hi_194, decoder_decoded_andMatrixOutputs_hi_lo_190}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_194 = {decoder_decoded_andMatrixOutputs_hi_194, decoder_decoded_andMatrixOutputs_lo_194}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_98_2_1 = &_decoder_decoded_andMatrixOutputs_T_194; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_195 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_196 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_197 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_198 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_199 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_203 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_204 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_211 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_212 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_213 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_216 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_217 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_218 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_219 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_220 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_223 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_224 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_225 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_226 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_227 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_232 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_233 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_235 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_238 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_239 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_240 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_241 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_244 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_245 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_246 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_251 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_257 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_264 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_269 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_274 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_284 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_289 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_290 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_299 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_308 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_321 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_366 = decoder_decoded_invInputs_1[4]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_191, decoder_decoded_andMatrixOutputs_andMatrixInput_7_183}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_195, decoder_decoded_andMatrixOutputs_andMatrixInput_5_194}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_195 = {decoder_decoded_andMatrixOutputs_lo_hi_194, decoder_decoded_andMatrixOutputs_lo_lo_183}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_195, decoder_decoded_andMatrixOutputs_andMatrixInput_3_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_195, decoder_decoded_andMatrixOutputs_andMatrixInput_1_195}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_195 = {decoder_decoded_andMatrixOutputs_hi_hi_195, decoder_decoded_andMatrixOutputs_hi_lo_191}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_195 = {decoder_decoded_andMatrixOutputs_hi_195, decoder_decoded_andMatrixOutputs_lo_195}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_101_2_1 = &_decoder_decoded_andMatrixOutputs_T_195; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_184 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_186 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_187 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_199 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_166 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_191 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_193 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_204 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_171 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_198 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_199 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_200 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_176 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_149 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_138 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_180 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_208 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_182 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_210 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_184 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_214 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_186 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_216 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_237 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_238 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_239 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_240 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_252 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_222 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_223 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_225 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_265 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_185 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_171 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_193 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_173 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_185 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_177 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_279 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_281 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_282 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_283 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_290 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_291 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_254 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_255 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_256 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_257 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_258 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_259 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_298 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_264 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_265 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_266 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_305 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_268 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_307 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_308 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_271 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_282 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_283 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_284 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_285 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_286 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_287 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_294 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_333 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_296 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_335 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_336 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_299 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_338 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_301 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_340 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_303 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_264 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_242 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_346 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_348 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_320 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_321 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_360 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_361 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_324 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_363 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_326 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_327 = decoder_decoded_invInputs_1[13]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_192, decoder_decoded_andMatrixOutputs_andMatrixInput_7_184}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_196, decoder_decoded_andMatrixOutputs_andMatrixInput_5_195}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_196 = {decoder_decoded_andMatrixOutputs_lo_hi_195, decoder_decoded_andMatrixOutputs_lo_lo_184}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_196, decoder_decoded_andMatrixOutputs_andMatrixInput_3_196}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_196, decoder_decoded_andMatrixOutputs_andMatrixInput_1_196}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_196 = {decoder_decoded_andMatrixOutputs_hi_hi_196, decoder_decoded_andMatrixOutputs_hi_lo_192}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_196 = {decoder_decoded_andMatrixOutputs_hi_196, decoder_decoded_andMatrixOutputs_lo_196}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_9_2_1 = &_decoder_decoded_andMatrixOutputs_T_196; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_193 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_185 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_164 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_165 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_188 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_189 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_167 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_169 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_194 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_149 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_174 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_175 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_152 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_144 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_126 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_215 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_204 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_205 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_179 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_155 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_212 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_185 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_187 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_230 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_218 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_219 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_188 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_189 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_223 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_190 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_191 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_193 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_194 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_195 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_251 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_214 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_182 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_183 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_224 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_230 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_179 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_154 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_187 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_156 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_190 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_180 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_160 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_239 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_240 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_241 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_242 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_243 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_244 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_245 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_246 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_247 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_248 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_251 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_252 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_253 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_214 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_215 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_216 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_217 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_260 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_261 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_242 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_244 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_245 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_247 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_254 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_295 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_256 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_297 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_300 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_258 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_218 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_306 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_307 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_308 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_309 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_310 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_280 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_281 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_322 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_323 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_284 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_325 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_286 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_287 = decoder_decoded_invInputs_1[14]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_197, decoder_decoded_andMatrixOutputs_andMatrixInput_5_196}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_197 = {decoder_decoded_andMatrixOutputs_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_6_193}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_197, decoder_decoded_andMatrixOutputs_andMatrixInput_3_197}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_197, decoder_decoded_andMatrixOutputs_andMatrixInput_1_197}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_197 = {decoder_decoded_andMatrixOutputs_hi_hi_197, decoder_decoded_andMatrixOutputs_hi_lo_193}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_197 = {decoder_decoded_andMatrixOutputs_hi_197, decoder_decoded_andMatrixOutputs_lo_197}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_29_2_1 = &_decoder_decoded_andMatrixOutputs_T_197; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_185 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_194, decoder_decoded_andMatrixOutputs_andMatrixInput_7_185}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_198, decoder_decoded_andMatrixOutputs_andMatrixInput_5_197}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_198 = {decoder_decoded_andMatrixOutputs_lo_hi_197, decoder_decoded_andMatrixOutputs_lo_lo_185}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_198, decoder_decoded_andMatrixOutputs_andMatrixInput_3_198}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_198, decoder_decoded_andMatrixOutputs_andMatrixInput_1_198}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_198 = {decoder_decoded_andMatrixOutputs_hi_hi_198, decoder_decoded_andMatrixOutputs_hi_lo_194}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_198 = {decoder_decoded_andMatrixOutputs_hi_198, decoder_decoded_andMatrixOutputs_lo_198}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_139_2_1 = &_decoder_decoded_andMatrixOutputs_T_198; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_199 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_201 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_202 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_219 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_220 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_225 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_226 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_227 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_233 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_240 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_241 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_245 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_246 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_251 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_284 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_289 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_290 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_299 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_308 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_321 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_366 = decoder_decoded_plaInput_1[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_199 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_210 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_220 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_227 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_230 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_231 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_246 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_259 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_260 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_282 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_283 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_284 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_285 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_289 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_290 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_299 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_308 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_321 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_327 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_328 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_329 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_362 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_366 = decoder_decoded_plaInput_1[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_186, decoder_decoded_andMatrixOutputs_andMatrixInput_8_164}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_198, decoder_decoded_andMatrixOutputs_andMatrixInput_6_195}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_199 = {decoder_decoded_andMatrixOutputs_lo_hi_198, decoder_decoded_andMatrixOutputs_lo_lo_186}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_199, decoder_decoded_andMatrixOutputs_andMatrixInput_4_199}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_199, decoder_decoded_andMatrixOutputs_andMatrixInput_1_199}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_199 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_164, decoder_decoded_andMatrixOutputs_andMatrixInput_2_199}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_199 = {decoder_decoded_andMatrixOutputs_hi_hi_199, decoder_decoded_andMatrixOutputs_hi_lo_195}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_199 = {decoder_decoded_andMatrixOutputs_hi_199, decoder_decoded_andMatrixOutputs_lo_199}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_117_2_1 = &_decoder_decoded_andMatrixOutputs_T_199; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_76 = decoder_decoded_andMatrixOutputs_117_2_1; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_200 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_201 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_202 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_205 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_206 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_207 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_208 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_209 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_210 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_214 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_215 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_221 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_222 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_228 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_229 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_230 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_231 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_237 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_242 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_243 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_247 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_248 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_249 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_250 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_252 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_253 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_254 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_255 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_256 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_258 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_259 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_260 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_261 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_262 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_265 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_266 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_267 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_270 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_271 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_272 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_273 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_275 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_276 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_277 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_278 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_279 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_280 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_281 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_282 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_283 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_285 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_286 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_287 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_288 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_291 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_292 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_293 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_294 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_295 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_296 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_297 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_298 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_300 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_301 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_302 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_303 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_304 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_305 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_306 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_307 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_309 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_310 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_311 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_312 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_313 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_314 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_315 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_316 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_317 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_318 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_319 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_320 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_322 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_323 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_324 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_325 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_326 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_327 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_328 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_329 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_330 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_331 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_332 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_333 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_334 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_335 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_336 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_337 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_338 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_339 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_340 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_341 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_342 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_343 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_344 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_345 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_346 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_347 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_348 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_349 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_350 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_351 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_352 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_353 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_354 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_355 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_356 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_357 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_358 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_359 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_360 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_361 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_362 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_363 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_364 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_365 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_367 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_368 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_369 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_370 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_371 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_372 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_373 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_374 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_375 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_376 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_377 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_378 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_379 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_380 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_381 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_382 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_383 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_384 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_385 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_386 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_387 = decoder_decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_187, decoder_decoded_andMatrixOutputs_andMatrixInput_8_165}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_199, decoder_decoded_andMatrixOutputs_andMatrixInput_6_196}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_200 = {decoder_decoded_andMatrixOutputs_lo_hi_199, decoder_decoded_andMatrixOutputs_lo_lo_187}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_200, decoder_decoded_andMatrixOutputs_andMatrixInput_4_200}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_200, decoder_decoded_andMatrixOutputs_andMatrixInput_1_200}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_200 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_165, decoder_decoded_andMatrixOutputs_andMatrixInput_2_200}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_200 = {decoder_decoded_andMatrixOutputs_hi_hi_200, decoder_decoded_andMatrixOutputs_hi_lo_196}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_200 = {decoder_decoded_andMatrixOutputs_hi_200, decoder_decoded_andMatrixOutputs_lo_200}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_95_2_1 = &_decoder_decoded_andMatrixOutputs_T_200; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_201, decoder_decoded_andMatrixOutputs_andMatrixInput_4_201}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_201 = {decoder_decoded_andMatrixOutputs_lo_hi_200, decoder_decoded_andMatrixOutputs_andMatrixInput_5_200}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_201, decoder_decoded_andMatrixOutputs_andMatrixInput_1_201}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_201 = {decoder_decoded_andMatrixOutputs_hi_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_2_201}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_201 = {decoder_decoded_andMatrixOutputs_hi_201, decoder_decoded_andMatrixOutputs_lo_201}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_35_2_1 = &_decoder_decoded_andMatrixOutputs_T_201; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_202, decoder_decoded_andMatrixOutputs_andMatrixInput_5_201}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_202 = {decoder_decoded_andMatrixOutputs_lo_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_6_197}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_202, decoder_decoded_andMatrixOutputs_andMatrixInput_3_202}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_202, decoder_decoded_andMatrixOutputs_andMatrixInput_1_202}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_202 = {decoder_decoded_andMatrixOutputs_hi_hi_202, decoder_decoded_andMatrixOutputs_hi_lo_197}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_202 = {decoder_decoded_andMatrixOutputs_hi_202, decoder_decoded_andMatrixOutputs_lo_202}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_182_2_1 = &_decoder_decoded_andMatrixOutputs_T_202; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_202 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_203 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_204 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_206 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_206 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_208 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_209 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_209 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_214 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_215 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_218 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_217 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_218 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_221 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_220 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_232 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_231 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_234 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_233 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_236 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_235 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_244 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_243 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_244 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_245 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_246 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_247 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_248 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_251 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_253 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_254 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_255 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_261 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_260 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_263 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_262 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_263 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_265 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_268 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_267 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_268 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_270 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_273 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_274 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_275 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_276 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_279 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_280 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_281 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_280 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_282 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_283 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_284 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_285 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_286 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_287 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_288 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_291 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_290 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_293 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_292 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_293 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_294 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_295 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_296 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_297 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_306 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_309 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_310 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_314 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_315 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_317 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_320 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_319 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_320 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_321 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_330 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_329 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_330 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_331 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_343 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_344 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_345 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_358 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_357 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_360 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_364 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_363 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_364 = decoder_decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_198, decoder_decoded_andMatrixOutputs_andMatrixInput_7_188}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_203, decoder_decoded_andMatrixOutputs_andMatrixInput_5_202}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_203 = {decoder_decoded_andMatrixOutputs_lo_hi_202, decoder_decoded_andMatrixOutputs_lo_lo_188}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_203, decoder_decoded_andMatrixOutputs_andMatrixInput_3_203}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_203, decoder_decoded_andMatrixOutputs_andMatrixInput_1_203}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_203 = {decoder_decoded_andMatrixOutputs_hi_hi_203, decoder_decoded_andMatrixOutputs_hi_lo_198}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_203 = {decoder_decoded_andMatrixOutputs_hi_203, decoder_decoded_andMatrixOutputs_lo_203}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_128_2_1 = &_decoder_decoded_andMatrixOutputs_T_203; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_199, decoder_decoded_andMatrixOutputs_andMatrixInput_7_189}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_204, decoder_decoded_andMatrixOutputs_andMatrixInput_5_203}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_204 = {decoder_decoded_andMatrixOutputs_lo_hi_203, decoder_decoded_andMatrixOutputs_lo_lo_189}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_204, decoder_decoded_andMatrixOutputs_andMatrixInput_3_204}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_204, decoder_decoded_andMatrixOutputs_andMatrixInput_1_204}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_204 = {decoder_decoded_andMatrixOutputs_hi_hi_204, decoder_decoded_andMatrixOutputs_hi_lo_199}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_204 = {decoder_decoded_andMatrixOutputs_hi_204, decoder_decoded_andMatrixOutputs_lo_204}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_66_2_1 = &_decoder_decoded_andMatrixOutputs_T_204; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_170 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_146 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_210 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_196 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_12 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_9 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_183 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_159 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_192 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_162 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_199 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_167 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_168 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_169 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_176 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_88 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_10 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_11 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_17 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_13 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_200 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_201 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_204 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_206 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_249 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_250 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_210 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_211 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_104 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_219 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_220 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_262 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_223 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_227 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_222 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_229 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_230 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_225 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_232 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_227 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_215 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_216 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_228 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_229 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_239 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_246 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_241 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_229 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_245 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_246 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_247 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_231 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_232 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_209 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_234 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_298 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_259 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_260 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_262 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_267 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_268 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_251 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_267 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_269 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_272 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_150 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_234 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_156 = decoder_decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_192 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_147 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_148 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_143 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_211 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_197 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_8 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_9 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_181 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_157 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_158 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_154 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_161 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_157 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_163 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_164 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_200 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_166 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_162 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_163 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_164 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_170 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_171 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_173 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_168 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_266 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_215 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_176 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_177 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_178 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_219 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_180 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_181 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_170 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_177 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_50 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_186 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_181 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_182 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_10 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_11 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_12 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_13 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_183 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_179 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_159 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_60 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_202 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_203 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_205 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_207 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_209 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_210 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_205 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_206 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_207 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_208 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_209 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_204 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_205 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_62 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_213 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_214 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_222 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_217 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_218 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_219 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_220 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_221 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_216 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_223 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_224 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_219 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_226 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_221 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_217 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_218 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_219 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_220 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_236 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_243 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_238 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_233 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_240 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_235 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_230 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_227 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_239 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_240 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_241 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_207 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_208 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_134 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_210 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_258 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_253 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_254 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_255 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_256 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_83 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_14 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_15 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_269 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_270 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_252 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_268 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_270 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_265 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_273 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_151 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_235 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_90 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_155 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_157 = decoder_decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_138 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_139 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_168 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_144 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_145 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_8 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_9 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_156 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_152 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_153 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_149 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_160 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_156 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_151 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_158 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_159 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_165 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_161 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_156 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_157 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_158 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_165 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_166 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_167 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_162 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_170 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_171 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_179 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_174 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_175 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_172 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_152 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_10 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_11 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_12 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_13 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_178 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_175 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_99 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_44 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_194 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_195 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_196 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_197 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_200 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_201 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_208 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_203 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_204 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_199 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_200 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_207 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_208 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_221 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_216 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_211 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_212 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_214 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_215 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_209 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_217 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_218 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_220 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_214 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_211 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_212 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_213 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_214 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_215 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_216 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_217 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_218 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_232 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_233 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_234 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_132 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_133 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_81 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_135 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_252 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_247 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_248 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_249 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_250 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_266 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_261 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_262 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_263 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_264 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_247 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_248 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_261 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_262 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_263 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_264 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_257 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_266 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_267 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_86 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_87 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_152 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_153 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_64 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_91 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_92 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_93 = decoder_decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_134 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_135 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_146 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_141 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_142 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_139 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_8 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_9 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_151 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_147 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_148 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_145 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_155 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_150 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_147 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_152 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_153 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_160 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_155 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_152 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_153 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_154 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_159 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_160 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_161 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_158 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_164 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_165 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_172 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_173 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_168 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_169 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_162 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_166 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_29 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_174 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_170 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_171 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_188 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_189 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_190 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_191 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_198 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_199 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_194 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_195 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_202 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_197 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_198 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_193 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_194 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_201 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_196 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_197 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_194 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_195 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_37 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_201 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_202 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_215 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_210 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_204 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_205 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_213 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_207 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_208 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_205 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_210 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_211 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_212 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_213 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_210 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_187 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_188 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_189 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_190 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_191 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_192 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_193 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_194 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_223 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_231 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_225 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_222 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_227 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_224 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_228 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_229 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_230 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_79 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_80 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_55 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_82 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_246 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_240 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_241 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_242 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_243 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_43 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_260 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_255 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_256 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_257 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_258 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_255 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_256 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_88 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_89 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_65 = decoder_decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_132 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_133 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_143 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_137 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_138 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_136 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_172 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_173 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_8 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_4 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_146 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_143 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_144 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_142 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_146 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_144 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_148 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_149 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_154 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_151 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_149 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_150 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_151 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_155 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_156 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_157 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_155 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_175 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_159 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_160 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_166 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_167 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_163 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_164 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_145 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_163 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_178 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_27 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_169 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_166 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_167 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_151 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_52 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_12 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_6 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_157 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_98 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_43 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_33 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_187 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_197 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_198 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_203 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_200 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_206 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_203 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_206 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_208 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_209 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_186 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_114 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_115 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_116 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_117 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_118 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_119 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_120 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_121 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_224 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_221 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_223 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_200 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_126 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_127 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_75 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_253 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_254 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_251 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_252 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_253 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_254 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_255 = decoder_decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_120 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_121 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_136 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_122 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_123 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_79 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_147 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_148 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_8 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_4 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_139 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_127 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_128 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_82 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_130 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_83 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_132 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_146 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_147 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_133 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_134 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_84 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_136 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_137 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_138 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_139 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_85 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_163 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_141 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_142 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_158 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_159 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_143 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_144 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_49 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_87 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_167 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_14 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_148 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_89 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_90 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_51 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_30 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_10 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_5 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_12 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_31_2 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_57 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_42 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_32 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_19 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_178 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_183 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_184 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_161 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_162 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_163 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_164 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_167 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_168 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_101 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_102 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_61 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_20 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_105 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_106 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_175 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_107 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_177 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_178 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_108 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_180 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_109 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_110 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_183 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_111 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_112 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_63 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_46 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_47 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_48 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_49 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_195 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_196 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_122 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_123 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_124 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_72 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_50 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_51 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_38 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_76 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_77 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_78 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_35 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_36 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_26 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_38 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_211 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_136 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_137 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_138 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_139 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_21 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_14 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_31_3 = decoder_decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_138 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_134, decoder_decoded_andMatrixOutputs_andMatrixInput_13_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_190 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_138, decoder_decoded_andMatrixOutputs_andMatrixInput_14_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_132 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_141, decoder_decoded_andMatrixOutputs_andMatrixInput_11_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_166, decoder_decoded_andMatrixOutputs_andMatrixInput_9_144}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_204 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_144, decoder_decoded_andMatrixOutputs_lo_hi_lo_132}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_205 = {decoder_decoded_andMatrixOutputs_lo_hi_204, decoder_decoded_andMatrixOutputs_lo_lo_190}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_200, decoder_decoded_andMatrixOutputs_andMatrixInput_7_190}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_205, decoder_decoded_andMatrixOutputs_andMatrixInput_5_204}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_200 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_141, decoder_decoded_andMatrixOutputs_hi_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_205, decoder_decoded_andMatrixOutputs_andMatrixInput_3_205}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_205, decoder_decoded_andMatrixOutputs_andMatrixInput_1_205}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_205 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_166, decoder_decoded_andMatrixOutputs_hi_hi_lo_134}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_205 = {decoder_decoded_andMatrixOutputs_hi_hi_205, decoder_decoded_andMatrixOutputs_hi_lo_200}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_205 = {decoder_decoded_andMatrixOutputs_hi_205, decoder_decoded_andMatrixOutputs_lo_205}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_77_2_1 = &_decoder_decoded_andMatrixOutputs_T_205; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_139 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_135, decoder_decoded_andMatrixOutputs_andMatrixInput_13_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_191 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_139, decoder_decoded_andMatrixOutputs_andMatrixInput_14_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_133 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_142, decoder_decoded_andMatrixOutputs_andMatrixInput_11_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_167, decoder_decoded_andMatrixOutputs_andMatrixInput_9_145}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_205 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_145, decoder_decoded_andMatrixOutputs_lo_hi_lo_133}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_206 = {decoder_decoded_andMatrixOutputs_lo_hi_205, decoder_decoded_andMatrixOutputs_lo_lo_191}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_201, decoder_decoded_andMatrixOutputs_andMatrixInput_7_191}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_206, decoder_decoded_andMatrixOutputs_andMatrixInput_5_205}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_201 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_142, decoder_decoded_andMatrixOutputs_hi_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_206, decoder_decoded_andMatrixOutputs_andMatrixInput_3_206}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_206, decoder_decoded_andMatrixOutputs_andMatrixInput_1_206}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_206 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_167, decoder_decoded_andMatrixOutputs_hi_hi_lo_135}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_206 = {decoder_decoded_andMatrixOutputs_hi_hi_206, decoder_decoded_andMatrixOutputs_hi_lo_201}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_206 = {decoder_decoded_andMatrixOutputs_hi_206, decoder_decoded_andMatrixOutputs_lo_206}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_190_2_1 = &_decoder_decoded_andMatrixOutputs_T_206; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_140 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_134 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_135 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_124 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_150 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_151 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_8 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_4 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_142 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_140 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_141 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_129 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_143 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_131 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_145 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_150 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_148 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_135 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_152 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_153 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_154 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_140 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_169 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_156 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_157 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_161 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_162 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_160 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_161 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_86 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_146 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_172 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_19 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_165 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_149 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_150 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_91 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_37 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_10 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_5 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_12 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_6 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_97 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_58 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_35 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_24 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_182 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_179 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_180 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_181 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_182 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_187 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_188 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_185 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_186 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_187 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_188 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_165 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_166 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_191 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_169 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_103 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_25 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_243 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_244 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_245 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_246 = decoder_decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_140 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_143, decoder_decoded_andMatrixOutputs_andMatrixInput_11_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_192 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_140, decoder_decoded_andMatrixOutputs_andMatrixInput_12_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_192, decoder_decoded_andMatrixOutputs_andMatrixInput_8_168}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_206 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_146, decoder_decoded_andMatrixOutputs_andMatrixInput_9_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_207 = {decoder_decoded_andMatrixOutputs_lo_hi_206, decoder_decoded_andMatrixOutputs_lo_lo_192}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_207, decoder_decoded_andMatrixOutputs_andMatrixInput_5_206}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_202 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_143, decoder_decoded_andMatrixOutputs_andMatrixInput_6_202}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_136 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_207, decoder_decoded_andMatrixOutputs_andMatrixInput_3_207}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_207, decoder_decoded_andMatrixOutputs_andMatrixInput_1_207}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_207 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_168, decoder_decoded_andMatrixOutputs_hi_hi_lo_136}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_207 = {decoder_decoded_andMatrixOutputs_hi_hi_207, decoder_decoded_andMatrixOutputs_hi_lo_202}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_207 = {decoder_decoded_andMatrixOutputs_hi_207, decoder_decoded_andMatrixOutputs_lo_207}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_7_2_1 = &_decoder_decoded_andMatrixOutputs_T_207; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_141 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_137, decoder_decoded_andMatrixOutputs_andMatrixInput_13_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_193 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_141, decoder_decoded_andMatrixOutputs_andMatrixInput_14_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_144, decoder_decoded_andMatrixOutputs_andMatrixInput_11_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_169, decoder_decoded_andMatrixOutputs_andMatrixInput_9_147}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_207 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_147, decoder_decoded_andMatrixOutputs_lo_hi_lo_134}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_208 = {decoder_decoded_andMatrixOutputs_lo_hi_207, decoder_decoded_andMatrixOutputs_lo_lo_193}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_203, decoder_decoded_andMatrixOutputs_andMatrixInput_7_193}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_208, decoder_decoded_andMatrixOutputs_andMatrixInput_5_207}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_203 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_144, decoder_decoded_andMatrixOutputs_hi_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_137 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_208, decoder_decoded_andMatrixOutputs_andMatrixInput_3_208}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_208, decoder_decoded_andMatrixOutputs_andMatrixInput_1_208}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_208 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_169, decoder_decoded_andMatrixOutputs_hi_hi_lo_137}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_208 = {decoder_decoded_andMatrixOutputs_hi_hi_208, decoder_decoded_andMatrixOutputs_hi_lo_203}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_208 = {decoder_decoded_andMatrixOutputs_hi_208, decoder_decoded_andMatrixOutputs_lo_208}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_97_2_1 = &_decoder_decoded_andMatrixOutputs_T_208; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_138, decoder_decoded_andMatrixOutputs_andMatrixInput_13_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_194 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_142, decoder_decoded_andMatrixOutputs_andMatrixInput_14_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_145, decoder_decoded_andMatrixOutputs_andMatrixInput_11_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_170, decoder_decoded_andMatrixOutputs_andMatrixInput_9_148}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_208 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_148, decoder_decoded_andMatrixOutputs_lo_hi_lo_135}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_209 = {decoder_decoded_andMatrixOutputs_lo_hi_208, decoder_decoded_andMatrixOutputs_lo_lo_194}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_204, decoder_decoded_andMatrixOutputs_andMatrixInput_7_194}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_209, decoder_decoded_andMatrixOutputs_andMatrixInput_5_208}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_204 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_145, decoder_decoded_andMatrixOutputs_hi_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_138 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_209, decoder_decoded_andMatrixOutputs_andMatrixInput_3_209}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_209, decoder_decoded_andMatrixOutputs_andMatrixInput_1_209}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_209 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_170, decoder_decoded_andMatrixOutputs_hi_hi_lo_138}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_209 = {decoder_decoded_andMatrixOutputs_hi_hi_209, decoder_decoded_andMatrixOutputs_hi_lo_204}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_209 = {decoder_decoded_andMatrixOutputs_hi_209, decoder_decoded_andMatrixOutputs_lo_209}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_32_2_1 = &_decoder_decoded_andMatrixOutputs_T_209; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_124, decoder_decoded_andMatrixOutputs_andMatrixInput_15_79}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_139, decoder_decoded_andMatrixOutputs_andMatrixInput_13_136}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_195 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_143, decoder_decoded_andMatrixOutputs_lo_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_136 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_146, decoder_decoded_andMatrixOutputs_andMatrixInput_11_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_171, decoder_decoded_andMatrixOutputs_andMatrixInput_9_149}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_209 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_149, decoder_decoded_andMatrixOutputs_lo_hi_lo_136}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_210 = {decoder_decoded_andMatrixOutputs_lo_hi_209, decoder_decoded_andMatrixOutputs_lo_lo_195}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_205, decoder_decoded_andMatrixOutputs_andMatrixInput_7_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_210, decoder_decoded_andMatrixOutputs_andMatrixInput_5_209}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_205 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_146, decoder_decoded_andMatrixOutputs_hi_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_139 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_210, decoder_decoded_andMatrixOutputs_andMatrixInput_3_210}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_210, decoder_decoded_andMatrixOutputs_andMatrixInput_1_210}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_210 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_171, decoder_decoded_andMatrixOutputs_hi_hi_lo_139}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_210 = {decoder_decoded_andMatrixOutputs_hi_hi_210, decoder_decoded_andMatrixOutputs_hi_lo_205}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_210 = {decoder_decoded_andMatrixOutputs_hi_210, decoder_decoded_andMatrixOutputs_lo_210}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_70_2_1 = &_decoder_decoded_andMatrixOutputs_T_210; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_211 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_212 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_213 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_206 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_207 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_208 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_209 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_216 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_211 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_212 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_221 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_214 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_232 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_227 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_234 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_229 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_241 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_242 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_249 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_261 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_256 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_257 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_266 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_261 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_262 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_274 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_267 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_291 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_284 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_293 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_286 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_287 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_288 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_289 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_290 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_292 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_293 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_294 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_295 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_296 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_297 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_298 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_299 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_303 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_304 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_305 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_326 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_327 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_328 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_329 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_330 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_331 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_332 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_333 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_340 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_341 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_342 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_364 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_357 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_359 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_360 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_361 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_362 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_363 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_364 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_365 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_366 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_367 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_368 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_369 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_370 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_371 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_372 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_373 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_374 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_375 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_376 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_377 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_378 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_379 = decoder_decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_211, decoder_decoded_andMatrixOutputs_andMatrixInput_4_211}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_211, decoder_decoded_andMatrixOutputs_andMatrixInput_1_211}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_211 = {decoder_decoded_andMatrixOutputs_hi_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_2_211}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T_211 = {decoder_decoded_andMatrixOutputs_hi_211, decoder_decoded_andMatrixOutputs_lo_211}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_181_2_1 = &_decoder_decoded_andMatrixOutputs_T_211; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_89 = decoder_decoded_andMatrixOutputs_181_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_212, decoder_decoded_andMatrixOutputs_andMatrixInput_4_212}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_212 = {decoder_decoded_andMatrixOutputs_lo_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_5_210}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_212, decoder_decoded_andMatrixOutputs_andMatrixInput_1_212}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_212 = {decoder_decoded_andMatrixOutputs_hi_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_2_212}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_212 = {decoder_decoded_andMatrixOutputs_hi_212, decoder_decoded_andMatrixOutputs_lo_212}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_145_2_1 = &_decoder_decoded_andMatrixOutputs_T_212; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_213, decoder_decoded_andMatrixOutputs_andMatrixInput_4_213}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_213 = {decoder_decoded_andMatrixOutputs_lo_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_5_211}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_213, decoder_decoded_andMatrixOutputs_andMatrixInput_1_213}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_213 = {decoder_decoded_andMatrixOutputs_hi_hi_213, decoder_decoded_andMatrixOutputs_andMatrixInput_2_213}; // @[pla.scala:91:29, :98:53] wire [5:0] _decoder_decoded_andMatrixOutputs_T_213 = {decoder_decoded_andMatrixOutputs_hi_213, decoder_decoded_andMatrixOutputs_lo_213}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_143_2_1 = &_decoder_decoded_andMatrixOutputs_T_213; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_150, decoder_decoded_andMatrixOutputs_andMatrixInput_10_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_206, decoder_decoded_andMatrixOutputs_andMatrixInput_7_196}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_212 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_150, decoder_decoded_andMatrixOutputs_andMatrixInput_8_172}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_214 = {decoder_decoded_andMatrixOutputs_lo_hi_212, decoder_decoded_andMatrixOutputs_lo_lo_196}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_214, decoder_decoded_andMatrixOutputs_andMatrixInput_4_214}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_206 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_147, decoder_decoded_andMatrixOutputs_andMatrixInput_5_212}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_214, decoder_decoded_andMatrixOutputs_andMatrixInput_1_214}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_214 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_2_214}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_214 = {decoder_decoded_andMatrixOutputs_hi_hi_214, decoder_decoded_andMatrixOutputs_hi_lo_206}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_214 = {decoder_decoded_andMatrixOutputs_hi_214, decoder_decoded_andMatrixOutputs_lo_214}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_20_2_1 = &_decoder_decoded_andMatrixOutputs_T_214; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_151, decoder_decoded_andMatrixOutputs_andMatrixInput_10_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_207, decoder_decoded_andMatrixOutputs_andMatrixInput_7_197}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_213 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_151, decoder_decoded_andMatrixOutputs_andMatrixInput_8_173}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_215 = {decoder_decoded_andMatrixOutputs_lo_hi_213, decoder_decoded_andMatrixOutputs_lo_lo_197}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_215, decoder_decoded_andMatrixOutputs_andMatrixInput_4_215}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_207 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_148, decoder_decoded_andMatrixOutputs_andMatrixInput_5_213}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_173 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_215, decoder_decoded_andMatrixOutputs_andMatrixInput_1_215}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_215 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_173, decoder_decoded_andMatrixOutputs_andMatrixInput_2_215}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_215 = {decoder_decoded_andMatrixOutputs_hi_hi_215, decoder_decoded_andMatrixOutputs_hi_lo_207}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_215 = {decoder_decoded_andMatrixOutputs_hi_215, decoder_decoded_andMatrixOutputs_lo_215}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_22_2_1 = &_decoder_decoded_andMatrixOutputs_T_215; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_208, decoder_decoded_andMatrixOutputs_andMatrixInput_7_198}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_216, decoder_decoded_andMatrixOutputs_andMatrixInput_5_214}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_216 = {decoder_decoded_andMatrixOutputs_lo_hi_214, decoder_decoded_andMatrixOutputs_lo_lo_198}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_216, decoder_decoded_andMatrixOutputs_andMatrixInput_3_216}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_216, decoder_decoded_andMatrixOutputs_andMatrixInput_1_216}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_216 = {decoder_decoded_andMatrixOutputs_hi_hi_216, decoder_decoded_andMatrixOutputs_hi_lo_208}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_216 = {decoder_decoded_andMatrixOutputs_hi_216, decoder_decoded_andMatrixOutputs_lo_216}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_96_2_1 = &_decoder_decoded_andMatrixOutputs_T_216; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_199, decoder_decoded_andMatrixOutputs_andMatrixInput_8_174}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_215, decoder_decoded_andMatrixOutputs_andMatrixInput_6_209}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_217 = {decoder_decoded_andMatrixOutputs_lo_hi_215, decoder_decoded_andMatrixOutputs_lo_lo_199}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_217, decoder_decoded_andMatrixOutputs_andMatrixInput_4_217}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_217, decoder_decoded_andMatrixOutputs_andMatrixInput_1_217}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_217 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_174, decoder_decoded_andMatrixOutputs_andMatrixInput_2_217}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_217 = {decoder_decoded_andMatrixOutputs_hi_hi_217, decoder_decoded_andMatrixOutputs_hi_lo_209}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_217 = {decoder_decoded_andMatrixOutputs_hi_217, decoder_decoded_andMatrixOutputs_lo_217}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_39_2_1 = &_decoder_decoded_andMatrixOutputs_T_217; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_200, decoder_decoded_andMatrixOutputs_andMatrixInput_8_175}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_216, decoder_decoded_andMatrixOutputs_andMatrixInput_6_210}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_218 = {decoder_decoded_andMatrixOutputs_lo_hi_216, decoder_decoded_andMatrixOutputs_lo_lo_200}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_218, decoder_decoded_andMatrixOutputs_andMatrixInput_4_218}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_218, decoder_decoded_andMatrixOutputs_andMatrixInput_1_218}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_218 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_175, decoder_decoded_andMatrixOutputs_andMatrixInput_2_218}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_218 = {decoder_decoded_andMatrixOutputs_hi_hi_218, decoder_decoded_andMatrixOutputs_hi_lo_210}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_218 = {decoder_decoded_andMatrixOutputs_hi_218, decoder_decoded_andMatrixOutputs_lo_218}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_131_2_1 = &_decoder_decoded_andMatrixOutputs_T_218; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_176, decoder_decoded_andMatrixOutputs_andMatrixInput_9_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_217, decoder_decoded_andMatrixOutputs_andMatrixInput_6_211}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_217 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_152, decoder_decoded_andMatrixOutputs_andMatrixInput_7_201}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_219 = {decoder_decoded_andMatrixOutputs_lo_hi_217, decoder_decoded_andMatrixOutputs_lo_lo_201}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_219, decoder_decoded_andMatrixOutputs_andMatrixInput_4_219}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_219, decoder_decoded_andMatrixOutputs_andMatrixInput_1_219}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_219 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_176, decoder_decoded_andMatrixOutputs_andMatrixInput_2_219}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_219 = {decoder_decoded_andMatrixOutputs_hi_hi_219, decoder_decoded_andMatrixOutputs_hi_lo_211}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_219 = {decoder_decoded_andMatrixOutputs_hi_219, decoder_decoded_andMatrixOutputs_lo_219}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_191_2_1 = &_decoder_decoded_andMatrixOutputs_T_219; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_136 = decoder_decoded_andMatrixOutputs_191_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_220, decoder_decoded_andMatrixOutputs_andMatrixInput_5_218}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_220 = {decoder_decoded_andMatrixOutputs_lo_hi_218, decoder_decoded_andMatrixOutputs_andMatrixInput_6_212}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_220, decoder_decoded_andMatrixOutputs_andMatrixInput_3_220}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_220, decoder_decoded_andMatrixOutputs_andMatrixInput_1_220}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_220 = {decoder_decoded_andMatrixOutputs_hi_hi_220, decoder_decoded_andMatrixOutputs_hi_lo_212}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_220 = {decoder_decoded_andMatrixOutputs_hi_220, decoder_decoded_andMatrixOutputs_lo_220}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_165_2_1 = &_decoder_decoded_andMatrixOutputs_T_220; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_137 = decoder_decoded_andMatrixOutputs_165_2_1; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_221 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_203 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_291 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_270 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_293 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_272 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_273 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_274 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_275 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_276 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_364 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_343 = decoder_decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_219 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_178 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_289 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_232 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_293 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_234 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_235 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_236 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_237 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_238 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_364 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_305 = decoder_decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_213 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_154 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_283 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_192 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_291 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_194 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_195 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_196 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_197 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_198 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_362 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_265 = decoder_decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_202 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_150 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_269 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_186 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_285 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_188 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_192 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_356 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_259 = decoder_decoded_invInputs_1[10]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_177 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_145 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_231 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_180 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_271 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_182 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_186 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_342 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_253 = decoder_decoded_invInputs_1[11]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_140 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_81 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_174 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_94 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_181 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_96 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_252 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_142 = decoder_decoded_invInputs_1[15]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_137 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_48 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_170 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_54 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_176 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_56 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_245 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_85 = decoder_decoded_invInputs_1[16]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_125 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_35 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_153 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_39 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_172 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_41 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_241 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_59 = decoder_decoded_invInputs_1[17]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_80 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_28 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_93 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_32 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_155 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_34 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_217 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_45 = decoder_decoded_invInputs_1[18]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_47 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_26 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_53 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_29 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_95 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_31 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_141 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_41 = decoder_decoded_invInputs_1[19]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_34 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_18 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_173 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_229 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_184 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_40 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_18 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_274 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_275 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_318 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_319 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_288 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_289 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_290 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_329 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_345 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_248 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_257 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_251 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_311 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_312 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_268 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_269 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_276 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_277 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_272 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_279 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_274 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_275 = decoder_decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_27 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_13 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_168 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_189 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_178 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_28 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_11 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_234 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_235 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_236 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_237 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_278 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_279 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_280 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_281 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_248 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_249 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_250 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_330 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_331 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_249 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_244 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_251 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_244 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_44 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_15 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_271 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_272 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_351 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_352 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_353 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_354 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_355 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_356 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_357 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_260 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_261 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_270 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_271 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_264 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_273 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_266 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_267 = decoder_decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_25 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_9 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_164 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_183 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_173 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_20 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_11 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_30 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_13 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_196 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_228 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_229 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_230 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_231 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_238 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_239 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_240 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_241 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_242 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_243 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_244 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_291 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_292 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_293 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_242 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_243 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_237 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_245 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_40 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_15 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_265 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_266 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_313 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_314 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_315 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_316 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_317 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_318 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_319 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_256 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_257 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_262 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_263 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_260 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_265 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_262 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_263 = decoder_decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_17 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_9 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_147 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_177 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_169 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_15 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_11 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_22 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_13 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_172 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_222 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_223 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_224 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_225 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_232 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_233 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_234 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_235 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_236 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_237 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_238 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_251 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_252 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_253 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_235 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_236 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_233 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_238 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_259 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_260 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_273 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_274 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_275 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_276 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_277 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_278 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_279 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_232 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_233 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_258 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_259 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_236 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_261 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_238 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_239 = decoder_decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_8, decoder_decoded_andMatrixOutputs_andMatrixInput_26_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_80 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_27_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_8, decoder_decoded_andMatrixOutputs_andMatrixInput_24_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_12, decoder_decoded_andMatrixOutputs_andMatrixInput_22_8}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_144 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_202 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_144, decoder_decoded_andMatrixOutputs_lo_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_27, decoder_decoded_andMatrixOutputs_andMatrixInput_19_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_137 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_20_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_47, decoder_decoded_andMatrixOutputs_andMatrixInput_17_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_125, decoder_decoded_andMatrixOutputs_andMatrixInput_15_80}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_153 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_219 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_153, decoder_decoded_andMatrixOutputs_lo_hi_lo_137}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_221 = {decoder_decoded_andMatrixOutputs_lo_hi_219, decoder_decoded_andMatrixOutputs_lo_lo_202}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_144, decoder_decoded_andMatrixOutputs_andMatrixInput_12_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_125 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_153, decoder_decoded_andMatrixOutputs_andMatrixInput_10_149}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_202, decoder_decoded_andMatrixOutputs_andMatrixInput_8_177}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_149 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_213 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_149, decoder_decoded_andMatrixOutputs_hi_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_221, decoder_decoded_andMatrixOutputs_andMatrixInput_5_219}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_140 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_213}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_221, decoder_decoded_andMatrixOutputs_andMatrixInput_3_221}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_221, decoder_decoded_andMatrixOutputs_andMatrixInput_1_221}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_177 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_221 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_177, decoder_decoded_andMatrixOutputs_hi_hi_lo_140}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_221 = {decoder_decoded_andMatrixOutputs_hi_hi_221, decoder_decoded_andMatrixOutputs_hi_lo_213}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_221 = {decoder_decoded_andMatrixOutputs_hi_221, decoder_decoded_andMatrixOutputs_lo_221}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_54_2_1 = &_decoder_decoded_andMatrixOutputs_T_221; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_4, decoder_decoded_andMatrixOutputs_andMatrixInput_29_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_81 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_30_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_9, decoder_decoded_andMatrixOutputs_andMatrixInput_27_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_9, decoder_decoded_andMatrixOutputs_andMatrixInput_25_9}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_145 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_203 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_145, decoder_decoded_andMatrixOutputs_lo_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_9, decoder_decoded_andMatrixOutputs_andMatrixInput_23_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_18, decoder_decoded_andMatrixOutputs_andMatrixInput_21_13}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_138 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_28, decoder_decoded_andMatrixOutputs_andMatrixInput_19_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_48, decoder_decoded_andMatrixOutputs_andMatrixInput_17_35}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_154 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_220 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_154, decoder_decoded_andMatrixOutputs_lo_hi_lo_138}; // @[pla.scala:98:53] wire [14:0] decoder_decoded_andMatrixOutputs_lo_222 = {decoder_decoded_andMatrixOutputs_lo_hi_220, decoder_decoded_andMatrixOutputs_lo_lo_203}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_126, decoder_decoded_andMatrixOutputs_andMatrixInput_15_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_141, decoder_decoded_andMatrixOutputs_andMatrixInput_13_138}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_126 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_150, decoder_decoded_andMatrixOutputs_andMatrixInput_11_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_178, decoder_decoded_andMatrixOutputs_andMatrixInput_9_154}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_150 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_214 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_150, decoder_decoded_andMatrixOutputs_hi_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_214, decoder_decoded_andMatrixOutputs_andMatrixInput_7_203}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_222, decoder_decoded_andMatrixOutputs_andMatrixInput_5_220}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_141 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_222, decoder_decoded_andMatrixOutputs_andMatrixInput_3_222}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_222, decoder_decoded_andMatrixOutputs_andMatrixInput_1_222}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_178 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_222 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_178, decoder_decoded_andMatrixOutputs_hi_hi_lo_141}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_222 = {decoder_decoded_andMatrixOutputs_hi_hi_222, decoder_decoded_andMatrixOutputs_hi_lo_214}; // @[pla.scala:98:53] wire [30:0] _decoder_decoded_andMatrixOutputs_T_222 = {decoder_decoded_andMatrixOutputs_hi_222, decoder_decoded_andMatrixOutputs_lo_222}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_89_2_1 = &_decoder_decoded_andMatrixOutputs_T_222; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_221 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_216 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_217 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_206 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_207 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_220 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_209 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_222 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_211 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_224 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_213 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_226 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_215 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_228 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_217 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_243 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_231 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_232 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_250 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_251 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_252 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_253 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_241 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_255 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_243 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_244 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_250 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_254 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_272 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_261 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_266 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_292 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_293 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_294 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_295 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_296 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_302 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_303 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_304 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_319 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_306 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_321 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_322 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_309 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_320 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_321 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_322 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_323 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_324 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_325 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_332 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_347 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_334 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_349 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_350 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_337 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_352 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_339 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_354 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_341 = decoder_decoded_plaInput_1[12]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_223, decoder_decoded_andMatrixOutputs_andMatrixInput_5_221}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_223 = {decoder_decoded_andMatrixOutputs_lo_hi_221, decoder_decoded_andMatrixOutputs_andMatrixInput_6_215}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_223, decoder_decoded_andMatrixOutputs_andMatrixInput_3_223}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_223, decoder_decoded_andMatrixOutputs_andMatrixInput_1_223}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_223 = {decoder_decoded_andMatrixOutputs_hi_hi_223, decoder_decoded_andMatrixOutputs_hi_lo_215}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_223 = {decoder_decoded_andMatrixOutputs_hi_223, decoder_decoded_andMatrixOutputs_lo_223}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_30_2_1 = &_decoder_decoded_andMatrixOutputs_T_223; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_216, decoder_decoded_andMatrixOutputs_andMatrixInput_7_204}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_224, decoder_decoded_andMatrixOutputs_andMatrixInput_5_222}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_224 = {decoder_decoded_andMatrixOutputs_lo_hi_222, decoder_decoded_andMatrixOutputs_lo_lo_204}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_224, decoder_decoded_andMatrixOutputs_andMatrixInput_3_224}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_224, decoder_decoded_andMatrixOutputs_andMatrixInput_1_224}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_224 = {decoder_decoded_andMatrixOutputs_hi_hi_224, decoder_decoded_andMatrixOutputs_hi_lo_216}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_224 = {decoder_decoded_andMatrixOutputs_hi_224, decoder_decoded_andMatrixOutputs_lo_224}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_26_2_1 = &_decoder_decoded_andMatrixOutputs_T_224; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_217, decoder_decoded_andMatrixOutputs_andMatrixInput_7_205}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_225, decoder_decoded_andMatrixOutputs_andMatrixInput_5_223}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_225 = {decoder_decoded_andMatrixOutputs_lo_hi_223, decoder_decoded_andMatrixOutputs_lo_lo_205}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_225, decoder_decoded_andMatrixOutputs_andMatrixInput_3_225}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_225, decoder_decoded_andMatrixOutputs_andMatrixInput_1_225}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_225 = {decoder_decoded_andMatrixOutputs_hi_hi_225, decoder_decoded_andMatrixOutputs_hi_lo_217}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_225 = {decoder_decoded_andMatrixOutputs_hi_225, decoder_decoded_andMatrixOutputs_lo_225}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_176_2_1 = &_decoder_decoded_andMatrixOutputs_T_225; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_206, decoder_decoded_andMatrixOutputs_andMatrixInput_8_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_224, decoder_decoded_andMatrixOutputs_andMatrixInput_6_218}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_226 = {decoder_decoded_andMatrixOutputs_lo_hi_224, decoder_decoded_andMatrixOutputs_lo_lo_206}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_226, decoder_decoded_andMatrixOutputs_andMatrixInput_4_226}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_179 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_226, decoder_decoded_andMatrixOutputs_andMatrixInput_1_226}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_226 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_179, decoder_decoded_andMatrixOutputs_andMatrixInput_2_226}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_226 = {decoder_decoded_andMatrixOutputs_hi_hi_226, decoder_decoded_andMatrixOutputs_hi_lo_218}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_226 = {decoder_decoded_andMatrixOutputs_hi_226, decoder_decoded_andMatrixOutputs_lo_226}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_76_2_1 = &_decoder_decoded_andMatrixOutputs_T_226; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_180, decoder_decoded_andMatrixOutputs_andMatrixInput_9_155}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_225, decoder_decoded_andMatrixOutputs_andMatrixInput_6_219}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_225 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_7_207}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_227 = {decoder_decoded_andMatrixOutputs_lo_hi_225, decoder_decoded_andMatrixOutputs_lo_lo_207}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_227, decoder_decoded_andMatrixOutputs_andMatrixInput_4_227}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_227, decoder_decoded_andMatrixOutputs_andMatrixInput_1_227}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_227 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_180, decoder_decoded_andMatrixOutputs_andMatrixInput_2_227}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_227 = {decoder_decoded_andMatrixOutputs_hi_hi_227, decoder_decoded_andMatrixOutputs_hi_lo_219}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_227 = {decoder_decoded_andMatrixOutputs_hi_227, decoder_decoded_andMatrixOutputs_lo_227}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_21_2_1 = &_decoder_decoded_andMatrixOutputs_T_227; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_77 = decoder_decoded_andMatrixOutputs_21_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_146, decoder_decoded_andMatrixOutputs_andMatrixInput_12_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_208 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_146, decoder_decoded_andMatrixOutputs_andMatrixInput_13_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_139 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_156, decoder_decoded_andMatrixOutputs_andMatrixInput_10_151}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_208, decoder_decoded_andMatrixOutputs_andMatrixInput_8_181}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_226 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_156, decoder_decoded_andMatrixOutputs_lo_hi_lo_139}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_228 = {decoder_decoded_andMatrixOutputs_lo_hi_226, decoder_decoded_andMatrixOutputs_lo_lo_208}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_228, decoder_decoded_andMatrixOutputs_andMatrixInput_5_226}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_220 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_151, decoder_decoded_andMatrixOutputs_andMatrixInput_6_220}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_228, decoder_decoded_andMatrixOutputs_andMatrixInput_3_228}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_181 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_228, decoder_decoded_andMatrixOutputs_andMatrixInput_1_228}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_228 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_181, decoder_decoded_andMatrixOutputs_hi_hi_lo_142}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_228 = {decoder_decoded_andMatrixOutputs_hi_hi_228, decoder_decoded_andMatrixOutputs_hi_lo_220}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_228 = {decoder_decoded_andMatrixOutputs_hi_228, decoder_decoded_andMatrixOutputs_lo_228}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_121_2_1 = &_decoder_decoded_andMatrixOutputs_T_228; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_143, decoder_decoded_andMatrixOutputs_andMatrixInput_13_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_209 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_147, decoder_decoded_andMatrixOutputs_andMatrixInput_14_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_140 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_152, decoder_decoded_andMatrixOutputs_andMatrixInput_11_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_182, decoder_decoded_andMatrixOutputs_andMatrixInput_9_157}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_227 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_157, decoder_decoded_andMatrixOutputs_lo_hi_lo_140}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_229 = {decoder_decoded_andMatrixOutputs_lo_hi_227, decoder_decoded_andMatrixOutputs_lo_lo_209}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_221, decoder_decoded_andMatrixOutputs_andMatrixInput_7_209}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_229, decoder_decoded_andMatrixOutputs_andMatrixInput_5_227}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_221 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_152, decoder_decoded_andMatrixOutputs_hi_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_229, decoder_decoded_andMatrixOutputs_andMatrixInput_3_229}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_229, decoder_decoded_andMatrixOutputs_andMatrixInput_1_229}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_229 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_182, decoder_decoded_andMatrixOutputs_hi_hi_lo_143}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_229 = {decoder_decoded_andMatrixOutputs_hi_hi_229, decoder_decoded_andMatrixOutputs_hi_lo_221}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_229 = {decoder_decoded_andMatrixOutputs_hi_229, decoder_decoded_andMatrixOutputs_lo_229}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_60_2_1 = &_decoder_decoded_andMatrixOutputs_T_229; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_144, decoder_decoded_andMatrixOutputs_andMatrixInput_13_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_210 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_148, decoder_decoded_andMatrixOutputs_andMatrixInput_14_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_141 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_153, decoder_decoded_andMatrixOutputs_andMatrixInput_11_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_183, decoder_decoded_andMatrixOutputs_andMatrixInput_9_158}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_228 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_158, decoder_decoded_andMatrixOutputs_lo_hi_lo_141}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_230 = {decoder_decoded_andMatrixOutputs_lo_hi_228, decoder_decoded_andMatrixOutputs_lo_lo_210}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_222, decoder_decoded_andMatrixOutputs_andMatrixInput_7_210}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_230, decoder_decoded_andMatrixOutputs_andMatrixInput_5_228}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_222 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_153, decoder_decoded_andMatrixOutputs_hi_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_230, decoder_decoded_andMatrixOutputs_andMatrixInput_3_230}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_230, decoder_decoded_andMatrixOutputs_andMatrixInput_1_230}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_230 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_183, decoder_decoded_andMatrixOutputs_hi_hi_lo_144}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_230 = {decoder_decoded_andMatrixOutputs_hi_hi_230, decoder_decoded_andMatrixOutputs_hi_lo_222}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_230 = {decoder_decoded_andMatrixOutputs_hi_230, decoder_decoded_andMatrixOutputs_lo_230}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_103_2_1 = &_decoder_decoded_andMatrixOutputs_T_230; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_129, decoder_decoded_andMatrixOutputs_andMatrixInput_15_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_145, decoder_decoded_andMatrixOutputs_andMatrixInput_13_142}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_211 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_149, decoder_decoded_andMatrixOutputs_lo_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_154, decoder_decoded_andMatrixOutputs_andMatrixInput_11_149}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_184, decoder_decoded_andMatrixOutputs_andMatrixInput_9_159}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_229 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_159, decoder_decoded_andMatrixOutputs_lo_hi_lo_142}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_231 = {decoder_decoded_andMatrixOutputs_lo_hi_229, decoder_decoded_andMatrixOutputs_lo_lo_211}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_223, decoder_decoded_andMatrixOutputs_andMatrixInput_7_211}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_231, decoder_decoded_andMatrixOutputs_andMatrixInput_5_229}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_223 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_154, decoder_decoded_andMatrixOutputs_hi_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_231, decoder_decoded_andMatrixOutputs_andMatrixInput_3_231}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_231, decoder_decoded_andMatrixOutputs_andMatrixInput_1_231}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_231 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_184, decoder_decoded_andMatrixOutputs_hi_hi_lo_145}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_231 = {decoder_decoded_andMatrixOutputs_hi_hi_231, decoder_decoded_andMatrixOutputs_hi_lo_223}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_231 = {decoder_decoded_andMatrixOutputs_hi_231, decoder_decoded_andMatrixOutputs_lo_231}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_24_2_1 = &_decoder_decoded_andMatrixOutputs_T_231; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_224, decoder_decoded_andMatrixOutputs_andMatrixInput_7_212}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_232, decoder_decoded_andMatrixOutputs_andMatrixInput_5_230}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_232 = {decoder_decoded_andMatrixOutputs_lo_hi_230, decoder_decoded_andMatrixOutputs_lo_lo_212}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_232, decoder_decoded_andMatrixOutputs_andMatrixInput_3_232}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_232, decoder_decoded_andMatrixOutputs_andMatrixInput_1_232}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_232 = {decoder_decoded_andMatrixOutputs_hi_hi_232, decoder_decoded_andMatrixOutputs_hi_lo_224}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_232 = {decoder_decoded_andMatrixOutputs_hi_232, decoder_decoded_andMatrixOutputs_lo_232}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_166_2_1 = &_decoder_decoded_andMatrixOutputs_T_232; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_213, decoder_decoded_andMatrixOutputs_andMatrixInput_8_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_231, decoder_decoded_andMatrixOutputs_andMatrixInput_6_225}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_233 = {decoder_decoded_andMatrixOutputs_lo_hi_231, decoder_decoded_andMatrixOutputs_lo_lo_213}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_233, decoder_decoded_andMatrixOutputs_andMatrixInput_4_233}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_185 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_233, decoder_decoded_andMatrixOutputs_andMatrixInput_1_233}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_233 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_185, decoder_decoded_andMatrixOutputs_andMatrixInput_2_233}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_233 = {decoder_decoded_andMatrixOutputs_hi_hi_233, decoder_decoded_andMatrixOutputs_hi_lo_225}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_233 = {decoder_decoded_andMatrixOutputs_hi_233, decoder_decoded_andMatrixOutputs_lo_233}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_160_2_1 = &_decoder_decoded_andMatrixOutputs_T_233; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_226, decoder_decoded_andMatrixOutputs_andMatrixInput_7_214}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_234, decoder_decoded_andMatrixOutputs_andMatrixInput_5_232}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_234 = {decoder_decoded_andMatrixOutputs_lo_hi_232, decoder_decoded_andMatrixOutputs_lo_lo_214}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_234, decoder_decoded_andMatrixOutputs_andMatrixInput_3_234}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_234, decoder_decoded_andMatrixOutputs_andMatrixInput_1_234}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_234 = {decoder_decoded_andMatrixOutputs_hi_hi_234, decoder_decoded_andMatrixOutputs_hi_lo_226}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_234 = {decoder_decoded_andMatrixOutputs_hi_234, decoder_decoded_andMatrixOutputs_lo_234}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_94_2_1 = &_decoder_decoded_andMatrixOutputs_T_234; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_215, decoder_decoded_andMatrixOutputs_andMatrixInput_8_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_233, decoder_decoded_andMatrixOutputs_andMatrixInput_6_227}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_235 = {decoder_decoded_andMatrixOutputs_lo_hi_233, decoder_decoded_andMatrixOutputs_lo_lo_215}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_235, decoder_decoded_andMatrixOutputs_andMatrixInput_4_235}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_235, decoder_decoded_andMatrixOutputs_andMatrixInput_1_235}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_235 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_186, decoder_decoded_andMatrixOutputs_andMatrixInput_2_235}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_235 = {decoder_decoded_andMatrixOutputs_hi_hi_235, decoder_decoded_andMatrixOutputs_hi_lo_227}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_235 = {decoder_decoded_andMatrixOutputs_hi_235, decoder_decoded_andMatrixOutputs_lo_235}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_55_2_1 = &_decoder_decoded_andMatrixOutputs_T_235; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_216, decoder_decoded_andMatrixOutputs_andMatrixInput_8_187}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_234, decoder_decoded_andMatrixOutputs_andMatrixInput_6_228}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_236 = {decoder_decoded_andMatrixOutputs_lo_hi_234, decoder_decoded_andMatrixOutputs_lo_lo_216}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_236, decoder_decoded_andMatrixOutputs_andMatrixInput_4_236}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_236, decoder_decoded_andMatrixOutputs_andMatrixInput_1_236}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_236 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_187, decoder_decoded_andMatrixOutputs_andMatrixInput_2_236}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_236 = {decoder_decoded_andMatrixOutputs_hi_hi_236, decoder_decoded_andMatrixOutputs_hi_lo_228}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_236 = {decoder_decoded_andMatrixOutputs_hi_236, decoder_decoded_andMatrixOutputs_lo_236}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_16_2_1 = &_decoder_decoded_andMatrixOutputs_T_236; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_229, decoder_decoded_andMatrixOutputs_andMatrixInput_7_217}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_237, decoder_decoded_andMatrixOutputs_andMatrixInput_5_235}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_237 = {decoder_decoded_andMatrixOutputs_lo_hi_235, decoder_decoded_andMatrixOutputs_lo_lo_217}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_237, decoder_decoded_andMatrixOutputs_andMatrixInput_3_237}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_237, decoder_decoded_andMatrixOutputs_andMatrixInput_1_237}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_237 = {decoder_decoded_andMatrixOutputs_hi_hi_237, decoder_decoded_andMatrixOutputs_hi_lo_229}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_237 = {decoder_decoded_andMatrixOutputs_hi_237, decoder_decoded_andMatrixOutputs_lo_237}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_185_2_1 = &_decoder_decoded_andMatrixOutputs_T_237; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_78 = decoder_decoded_andMatrixOutputs_185_2_1; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_236 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_231 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_232 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_220 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_221 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_222 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_236 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_224 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_225 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_226 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_227 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_228 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_229 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_230 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_196 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_197 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_245 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_246 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_260 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_248 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_249 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_212 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_255 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_273 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_262 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_268 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_277 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_286 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_287 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_299 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_310 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_273 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_344 = decoder_decoded_plaInput_1[13]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_238, decoder_decoded_andMatrixOutputs_andMatrixInput_5_236}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_238 = {decoder_decoded_andMatrixOutputs_lo_hi_236, decoder_decoded_andMatrixOutputs_andMatrixInput_6_230}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_238, decoder_decoded_andMatrixOutputs_andMatrixInput_3_238}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_238, decoder_decoded_andMatrixOutputs_andMatrixInput_1_238}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_238 = {decoder_decoded_andMatrixOutputs_hi_hi_238, decoder_decoded_andMatrixOutputs_hi_lo_230}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_238 = {decoder_decoded_andMatrixOutputs_hi_238, decoder_decoded_andMatrixOutputs_lo_238}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_140_2_1 = &_decoder_decoded_andMatrixOutputs_T_238; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_231, decoder_decoded_andMatrixOutputs_andMatrixInput_7_218}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_239, decoder_decoded_andMatrixOutputs_andMatrixInput_5_237}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_239 = {decoder_decoded_andMatrixOutputs_lo_hi_237, decoder_decoded_andMatrixOutputs_lo_lo_218}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_239, decoder_decoded_andMatrixOutputs_andMatrixInput_3_239}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_239, decoder_decoded_andMatrixOutputs_andMatrixInput_1_239}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_239 = {decoder_decoded_andMatrixOutputs_hi_hi_239, decoder_decoded_andMatrixOutputs_hi_lo_231}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_239 = {decoder_decoded_andMatrixOutputs_hi_239, decoder_decoded_andMatrixOutputs_lo_239}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_52_2_1 = &_decoder_decoded_andMatrixOutputs_T_239; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_232, decoder_decoded_andMatrixOutputs_andMatrixInput_7_219}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_240, decoder_decoded_andMatrixOutputs_andMatrixInput_5_238}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_240 = {decoder_decoded_andMatrixOutputs_lo_hi_238, decoder_decoded_andMatrixOutputs_lo_lo_219}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_240, decoder_decoded_andMatrixOutputs_andMatrixInput_3_240}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_240, decoder_decoded_andMatrixOutputs_andMatrixInput_1_240}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_240 = {decoder_decoded_andMatrixOutputs_hi_hi_240, decoder_decoded_andMatrixOutputs_hi_lo_232}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_240 = {decoder_decoded_andMatrixOutputs_hi_240, decoder_decoded_andMatrixOutputs_lo_240}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_193_2_1 = &_decoder_decoded_andMatrixOutputs_T_240; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_220, decoder_decoded_andMatrixOutputs_andMatrixInput_8_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_239, decoder_decoded_andMatrixOutputs_andMatrixInput_6_233}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_241 = {decoder_decoded_andMatrixOutputs_lo_hi_239, decoder_decoded_andMatrixOutputs_lo_lo_220}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_241, decoder_decoded_andMatrixOutputs_andMatrixInput_4_241}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_241, decoder_decoded_andMatrixOutputs_andMatrixInput_1_241}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_241 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_188, decoder_decoded_andMatrixOutputs_andMatrixInput_2_241}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_241 = {decoder_decoded_andMatrixOutputs_hi_hi_241, decoder_decoded_andMatrixOutputs_hi_lo_233}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_241 = {decoder_decoded_andMatrixOutputs_hi_241, decoder_decoded_andMatrixOutputs_lo_241}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_91_2_1 = &_decoder_decoded_andMatrixOutputs_T_241; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_234, decoder_decoded_andMatrixOutputs_andMatrixInput_7_221}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_242, decoder_decoded_andMatrixOutputs_andMatrixInput_5_240}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_242 = {decoder_decoded_andMatrixOutputs_lo_hi_240, decoder_decoded_andMatrixOutputs_lo_lo_221}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_242, decoder_decoded_andMatrixOutputs_andMatrixInput_3_242}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_242, decoder_decoded_andMatrixOutputs_andMatrixInput_1_242}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_242 = {decoder_decoded_andMatrixOutputs_hi_hi_242, decoder_decoded_andMatrixOutputs_hi_lo_234}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_242 = {decoder_decoded_andMatrixOutputs_hi_242, decoder_decoded_andMatrixOutputs_lo_242}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_17_2_1 = &_decoder_decoded_andMatrixOutputs_T_242; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_222, decoder_decoded_andMatrixOutputs_andMatrixInput_8_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_241, decoder_decoded_andMatrixOutputs_andMatrixInput_6_235}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_243 = {decoder_decoded_andMatrixOutputs_lo_hi_241, decoder_decoded_andMatrixOutputs_lo_lo_222}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_243, decoder_decoded_andMatrixOutputs_andMatrixInput_4_243}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_243, decoder_decoded_andMatrixOutputs_andMatrixInput_1_243}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_243 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_189, decoder_decoded_andMatrixOutputs_andMatrixInput_2_243}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_243 = {decoder_decoded_andMatrixOutputs_hi_hi_243, decoder_decoded_andMatrixOutputs_hi_lo_235}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_243 = {decoder_decoded_andMatrixOutputs_hi_243, decoder_decoded_andMatrixOutputs_lo_243}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_129_2_1 = &_decoder_decoded_andMatrixOutputs_T_243; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_236, decoder_decoded_andMatrixOutputs_andMatrixInput_7_223}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_244, decoder_decoded_andMatrixOutputs_andMatrixInput_5_242}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_244 = {decoder_decoded_andMatrixOutputs_lo_hi_242, decoder_decoded_andMatrixOutputs_lo_lo_223}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_244, decoder_decoded_andMatrixOutputs_andMatrixInput_3_244}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_244, decoder_decoded_andMatrixOutputs_andMatrixInput_1_244}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_244 = {decoder_decoded_andMatrixOutputs_hi_hi_244, decoder_decoded_andMatrixOutputs_hi_lo_236}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_244 = {decoder_decoded_andMatrixOutputs_hi_244, decoder_decoded_andMatrixOutputs_lo_244}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_177_2_1 = &_decoder_decoded_andMatrixOutputs_T_244; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_224, decoder_decoded_andMatrixOutputs_andMatrixInput_8_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_243, decoder_decoded_andMatrixOutputs_andMatrixInput_6_237}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_245 = {decoder_decoded_andMatrixOutputs_lo_hi_243, decoder_decoded_andMatrixOutputs_lo_lo_224}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_245, decoder_decoded_andMatrixOutputs_andMatrixInput_4_245}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_245, decoder_decoded_andMatrixOutputs_andMatrixInput_1_245}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_245 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_190, decoder_decoded_andMatrixOutputs_andMatrixInput_2_245}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_245 = {decoder_decoded_andMatrixOutputs_hi_hi_245, decoder_decoded_andMatrixOutputs_hi_lo_237}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_245 = {decoder_decoded_andMatrixOutputs_hi_245, decoder_decoded_andMatrixOutputs_lo_245}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_123_2_1 = &_decoder_decoded_andMatrixOutputs_T_245; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_160, decoder_decoded_andMatrixOutputs_andMatrixInput_10_155}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_238, decoder_decoded_andMatrixOutputs_andMatrixInput_7_225}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_244 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_8_191}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_246 = {decoder_decoded_andMatrixOutputs_lo_hi_244, decoder_decoded_andMatrixOutputs_lo_lo_225}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_246, decoder_decoded_andMatrixOutputs_andMatrixInput_4_246}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_238 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_5_244}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_246, decoder_decoded_andMatrixOutputs_andMatrixInput_1_246}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_246 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_191, decoder_decoded_andMatrixOutputs_andMatrixInput_2_246}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_246 = {decoder_decoded_andMatrixOutputs_hi_hi_246, decoder_decoded_andMatrixOutputs_hi_lo_238}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_246 = {decoder_decoded_andMatrixOutputs_hi_246, decoder_decoded_andMatrixOutputs_lo_246}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_14_2_1 = &_decoder_decoded_andMatrixOutputs_T_246; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_100 = decoder_decoded_andMatrixOutputs_14_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_146, decoder_decoded_andMatrixOutputs_andMatrixInput_13_143}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_226 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_150, decoder_decoded_andMatrixOutputs_andMatrixInput_14_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_156, decoder_decoded_andMatrixOutputs_andMatrixInput_11_150}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_192, decoder_decoded_andMatrixOutputs_andMatrixInput_9_161}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_245 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_161, decoder_decoded_andMatrixOutputs_lo_hi_lo_143}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_247 = {decoder_decoded_andMatrixOutputs_lo_hi_245, decoder_decoded_andMatrixOutputs_lo_lo_226}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_130 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_239, decoder_decoded_andMatrixOutputs_andMatrixInput_7_226}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_247, decoder_decoded_andMatrixOutputs_andMatrixInput_5_245}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_239 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_156, decoder_decoded_andMatrixOutputs_hi_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_247, decoder_decoded_andMatrixOutputs_andMatrixInput_3_247}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_247, decoder_decoded_andMatrixOutputs_andMatrixInput_1_247}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_247 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_192, decoder_decoded_andMatrixOutputs_hi_hi_lo_146}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_247 = {decoder_decoded_andMatrixOutputs_hi_hi_247, decoder_decoded_andMatrixOutputs_hi_lo_239}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_247 = {decoder_decoded_andMatrixOutputs_hi_247, decoder_decoded_andMatrixOutputs_lo_247}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_132_2_1 = &_decoder_decoded_andMatrixOutputs_T_247; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_131, decoder_decoded_andMatrixOutputs_andMatrixInput_15_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_147, decoder_decoded_andMatrixOutputs_andMatrixInput_13_144}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_227 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_151, decoder_decoded_andMatrixOutputs_lo_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_157, decoder_decoded_andMatrixOutputs_andMatrixInput_11_151}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_193, decoder_decoded_andMatrixOutputs_andMatrixInput_9_162}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_246 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_162, decoder_decoded_andMatrixOutputs_lo_hi_lo_144}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_248 = {decoder_decoded_andMatrixOutputs_lo_hi_246, decoder_decoded_andMatrixOutputs_lo_lo_227}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_131 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_240, decoder_decoded_andMatrixOutputs_andMatrixInput_7_227}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_248, decoder_decoded_andMatrixOutputs_andMatrixInput_5_246}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_240 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_157, decoder_decoded_andMatrixOutputs_hi_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_248, decoder_decoded_andMatrixOutputs_andMatrixInput_3_248}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_248, decoder_decoded_andMatrixOutputs_andMatrixInput_1_248}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_248 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_193, decoder_decoded_andMatrixOutputs_hi_hi_lo_147}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_248 = {decoder_decoded_andMatrixOutputs_hi_hi_248, decoder_decoded_andMatrixOutputs_hi_lo_240}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_248 = {decoder_decoded_andMatrixOutputs_hi_248, decoder_decoded_andMatrixOutputs_lo_248}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_48_2_1 = &_decoder_decoded_andMatrixOutputs_T_248; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_241, decoder_decoded_andMatrixOutputs_andMatrixInput_7_228}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_249, decoder_decoded_andMatrixOutputs_andMatrixInput_5_247}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_249 = {decoder_decoded_andMatrixOutputs_lo_hi_247, decoder_decoded_andMatrixOutputs_lo_lo_228}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_249, decoder_decoded_andMatrixOutputs_andMatrixInput_3_249}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_249, decoder_decoded_andMatrixOutputs_andMatrixInput_1_249}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_249 = {decoder_decoded_andMatrixOutputs_hi_hi_249, decoder_decoded_andMatrixOutputs_hi_lo_241}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_249 = {decoder_decoded_andMatrixOutputs_hi_249, decoder_decoded_andMatrixOutputs_lo_249}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_155_2_1 = &_decoder_decoded_andMatrixOutputs_T_249; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_79 = decoder_decoded_andMatrixOutputs_155_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_229, decoder_decoded_andMatrixOutputs_andMatrixInput_8_194}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_248, decoder_decoded_andMatrixOutputs_andMatrixInput_6_242}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_250 = {decoder_decoded_andMatrixOutputs_lo_hi_248, decoder_decoded_andMatrixOutputs_lo_lo_229}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_250, decoder_decoded_andMatrixOutputs_andMatrixInput_4_250}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_250, decoder_decoded_andMatrixOutputs_andMatrixInput_1_250}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_250 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_2_250}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_250 = {decoder_decoded_andMatrixOutputs_hi_hi_250, decoder_decoded_andMatrixOutputs_hi_lo_242}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_250 = {decoder_decoded_andMatrixOutputs_hi_250, decoder_decoded_andMatrixOutputs_lo_250}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_184_2_1 = &_decoder_decoded_andMatrixOutputs_T_250; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_230, decoder_decoded_andMatrixOutputs_andMatrixInput_8_195}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_249, decoder_decoded_andMatrixOutputs_andMatrixInput_6_243}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_251 = {decoder_decoded_andMatrixOutputs_lo_hi_249, decoder_decoded_andMatrixOutputs_lo_lo_230}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_251, decoder_decoded_andMatrixOutputs_andMatrixInput_4_251}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_251, decoder_decoded_andMatrixOutputs_andMatrixInput_1_251}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_251 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_2_251}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_251 = {decoder_decoded_andMatrixOutputs_hi_hi_251, decoder_decoded_andMatrixOutputs_hi_lo_243}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_251 = {decoder_decoded_andMatrixOutputs_hi_251, decoder_decoded_andMatrixOutputs_lo_251}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_148_2_1 = &_decoder_decoded_andMatrixOutputs_T_251; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_231, decoder_decoded_andMatrixOutputs_andMatrixInput_8_196}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_250, decoder_decoded_andMatrixOutputs_andMatrixInput_6_244}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_252 = {decoder_decoded_andMatrixOutputs_lo_hi_250, decoder_decoded_andMatrixOutputs_lo_lo_231}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_252, decoder_decoded_andMatrixOutputs_andMatrixInput_4_252}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_252, decoder_decoded_andMatrixOutputs_andMatrixInput_1_252}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_252 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_2_252}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_252 = {decoder_decoded_andMatrixOutputs_hi_hi_252, decoder_decoded_andMatrixOutputs_hi_lo_244}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_252 = {decoder_decoded_andMatrixOutputs_hi_252, decoder_decoded_andMatrixOutputs_lo_252}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_115_2_1 = &_decoder_decoded_andMatrixOutputs_T_252; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_148, decoder_decoded_andMatrixOutputs_andMatrixInput_13_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_232 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_152, decoder_decoded_andMatrixOutputs_andMatrixInput_14_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_158, decoder_decoded_andMatrixOutputs_andMatrixInput_11_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_197, decoder_decoded_andMatrixOutputs_andMatrixInput_9_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_251 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_163, decoder_decoded_andMatrixOutputs_lo_hi_lo_145}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_253 = {decoder_decoded_andMatrixOutputs_lo_hi_251, decoder_decoded_andMatrixOutputs_lo_lo_232}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_132 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_245, decoder_decoded_andMatrixOutputs_andMatrixInput_7_232}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_253, decoder_decoded_andMatrixOutputs_andMatrixInput_5_251}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_245 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_158, decoder_decoded_andMatrixOutputs_hi_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_253, decoder_decoded_andMatrixOutputs_andMatrixInput_3_253}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_253, decoder_decoded_andMatrixOutputs_andMatrixInput_1_253}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_253 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_197, decoder_decoded_andMatrixOutputs_hi_hi_lo_148}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_253 = {decoder_decoded_andMatrixOutputs_hi_hi_253, decoder_decoded_andMatrixOutputs_hi_lo_245}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_253 = {decoder_decoded_andMatrixOutputs_hi_253, decoder_decoded_andMatrixOutputs_lo_253}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_163_2_1 = &_decoder_decoded_andMatrixOutputs_T_253; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_198 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_234 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_235 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_236 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_201 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_202 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_203 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_204 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_205 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_242 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_206 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_207 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_208 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_209 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_247 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_210 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_211 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_172 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_256 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_271 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_258 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_259 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_185 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_264 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_227 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_228 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_288 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_218 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_300 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_263 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_224 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_225 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_226 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_267 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_228 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_269 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_270 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_231 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_272 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_233 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_261 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_302 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_263 = decoder_decoded_plaInput_1[14]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_233, decoder_decoded_andMatrixOutputs_andMatrixInput_8_198}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_252, decoder_decoded_andMatrixOutputs_andMatrixInput_6_246}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_254 = {decoder_decoded_andMatrixOutputs_lo_hi_252, decoder_decoded_andMatrixOutputs_lo_lo_233}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_254, decoder_decoded_andMatrixOutputs_andMatrixInput_4_254}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_254, decoder_decoded_andMatrixOutputs_andMatrixInput_1_254}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_254 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_2_254}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_254 = {decoder_decoded_andMatrixOutputs_hi_hi_254, decoder_decoded_andMatrixOutputs_hi_lo_246}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_254 = {decoder_decoded_andMatrixOutputs_hi_254, decoder_decoded_andMatrixOutputs_lo_254}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_45_2_1 = &_decoder_decoded_andMatrixOutputs_T_254; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_153, decoder_decoded_andMatrixOutputs_andMatrixInput_12_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_234 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_153, decoder_decoded_andMatrixOutputs_andMatrixInput_13_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_164, decoder_decoded_andMatrixOutputs_andMatrixInput_10_159}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_234, decoder_decoded_andMatrixOutputs_andMatrixInput_8_199}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_253 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_164, decoder_decoded_andMatrixOutputs_lo_hi_lo_146}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_255 = {decoder_decoded_andMatrixOutputs_lo_hi_253, decoder_decoded_andMatrixOutputs_lo_lo_234}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_255, decoder_decoded_andMatrixOutputs_andMatrixInput_5_253}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_247 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_159, decoder_decoded_andMatrixOutputs_andMatrixInput_6_247}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_255, decoder_decoded_andMatrixOutputs_andMatrixInput_3_255}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_255, decoder_decoded_andMatrixOutputs_andMatrixInput_1_255}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_255 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_199, decoder_decoded_andMatrixOutputs_hi_hi_lo_149}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_255 = {decoder_decoded_andMatrixOutputs_hi_hi_255, decoder_decoded_andMatrixOutputs_hi_lo_247}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_255 = {decoder_decoded_andMatrixOutputs_hi_255, decoder_decoded_andMatrixOutputs_lo_255}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_126_2_1 = &_decoder_decoded_andMatrixOutputs_T_255; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_154, decoder_decoded_andMatrixOutputs_andMatrixInput_12_150}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_235 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_154, decoder_decoded_andMatrixOutputs_andMatrixInput_13_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_165, decoder_decoded_andMatrixOutputs_andMatrixInput_10_160}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_235, decoder_decoded_andMatrixOutputs_andMatrixInput_8_200}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_254 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_165, decoder_decoded_andMatrixOutputs_lo_hi_lo_147}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_256 = {decoder_decoded_andMatrixOutputs_lo_hi_254, decoder_decoded_andMatrixOutputs_lo_lo_235}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_256, decoder_decoded_andMatrixOutputs_andMatrixInput_5_254}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_248 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_6_248}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_256, decoder_decoded_andMatrixOutputs_andMatrixInput_3_256}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_256, decoder_decoded_andMatrixOutputs_andMatrixInput_1_256}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_256 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_200, decoder_decoded_andMatrixOutputs_hi_hi_lo_150}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_256 = {decoder_decoded_andMatrixOutputs_hi_hi_256, decoder_decoded_andMatrixOutputs_hi_lo_248}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_256 = {decoder_decoded_andMatrixOutputs_hi_256, decoder_decoded_andMatrixOutputs_lo_256}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_150_2_1 = &_decoder_decoded_andMatrixOutputs_T_256; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_249, decoder_decoded_andMatrixOutputs_andMatrixInput_7_236}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_257, decoder_decoded_andMatrixOutputs_andMatrixInput_5_255}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_257 = {decoder_decoded_andMatrixOutputs_lo_hi_255, decoder_decoded_andMatrixOutputs_lo_lo_236}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_257, decoder_decoded_andMatrixOutputs_andMatrixInput_3_257}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_257 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_257, decoder_decoded_andMatrixOutputs_andMatrixInput_1_257}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_257 = {decoder_decoded_andMatrixOutputs_hi_hi_257, decoder_decoded_andMatrixOutputs_hi_lo_249}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_257 = {decoder_decoded_andMatrixOutputs_hi_257, decoder_decoded_andMatrixOutputs_lo_257}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_162_2_1 = &_decoder_decoded_andMatrixOutputs_T_257; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_151, decoder_decoded_andMatrixOutputs_andMatrixInput_13_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_237 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_155, decoder_decoded_andMatrixOutputs_andMatrixInput_14_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_161, decoder_decoded_andMatrixOutputs_andMatrixInput_11_155}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_201, decoder_decoded_andMatrixOutputs_andMatrixInput_9_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_256 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_166, decoder_decoded_andMatrixOutputs_lo_hi_lo_148}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_258 = {decoder_decoded_andMatrixOutputs_lo_hi_256, decoder_decoded_andMatrixOutputs_lo_lo_237}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_133 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_250, decoder_decoded_andMatrixOutputs_andMatrixInput_7_237}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_258, decoder_decoded_andMatrixOutputs_andMatrixInput_5_256}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_250 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_161, decoder_decoded_andMatrixOutputs_hi_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_258, decoder_decoded_andMatrixOutputs_andMatrixInput_3_258}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_258, decoder_decoded_andMatrixOutputs_andMatrixInput_1_258}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_258 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_201, decoder_decoded_andMatrixOutputs_hi_hi_lo_151}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_258 = {decoder_decoded_andMatrixOutputs_hi_hi_258, decoder_decoded_andMatrixOutputs_hi_lo_250}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_258 = {decoder_decoded_andMatrixOutputs_hi_258, decoder_decoded_andMatrixOutputs_lo_258}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_133_2_1 = &_decoder_decoded_andMatrixOutputs_T_258; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_152, decoder_decoded_andMatrixOutputs_andMatrixInput_13_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_238 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_156, decoder_decoded_andMatrixOutputs_andMatrixInput_14_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_162, decoder_decoded_andMatrixOutputs_andMatrixInput_11_156}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_202, decoder_decoded_andMatrixOutputs_andMatrixInput_9_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_257 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_167, decoder_decoded_andMatrixOutputs_lo_hi_lo_149}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_259 = {decoder_decoded_andMatrixOutputs_lo_hi_257, decoder_decoded_andMatrixOutputs_lo_lo_238}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_251, decoder_decoded_andMatrixOutputs_andMatrixInput_7_238}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_259, decoder_decoded_andMatrixOutputs_andMatrixInput_5_257}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_251 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_162, decoder_decoded_andMatrixOutputs_hi_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_259, decoder_decoded_andMatrixOutputs_andMatrixInput_3_259}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_259, decoder_decoded_andMatrixOutputs_andMatrixInput_1_259}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_259 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_202, decoder_decoded_andMatrixOutputs_hi_hi_lo_152}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_259 = {decoder_decoded_andMatrixOutputs_hi_hi_259, decoder_decoded_andMatrixOutputs_hi_lo_251}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_259 = {decoder_decoded_andMatrixOutputs_hi_259, decoder_decoded_andMatrixOutputs_lo_259}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_179_2_1 = &_decoder_decoded_andMatrixOutputs_T_259; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_135, decoder_decoded_andMatrixOutputs_andMatrixInput_15_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_153, decoder_decoded_andMatrixOutputs_andMatrixInput_13_150}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_239 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_157, decoder_decoded_andMatrixOutputs_lo_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_163, decoder_decoded_andMatrixOutputs_andMatrixInput_11_157}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_203, decoder_decoded_andMatrixOutputs_andMatrixInput_9_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_258 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_168, decoder_decoded_andMatrixOutputs_lo_hi_lo_150}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_260 = {decoder_decoded_andMatrixOutputs_lo_hi_258, decoder_decoded_andMatrixOutputs_lo_lo_239}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_252, decoder_decoded_andMatrixOutputs_andMatrixInput_7_239}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_260, decoder_decoded_andMatrixOutputs_andMatrixInput_5_258}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_252 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_163, decoder_decoded_andMatrixOutputs_hi_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_260, decoder_decoded_andMatrixOutputs_andMatrixInput_3_260}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_260, decoder_decoded_andMatrixOutputs_andMatrixInput_1_260}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_260 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_203, decoder_decoded_andMatrixOutputs_hi_hi_lo_153}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_260 = {decoder_decoded_andMatrixOutputs_hi_hi_260, decoder_decoded_andMatrixOutputs_hi_lo_252}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_260 = {decoder_decoded_andMatrixOutputs_hi_260, decoder_decoded_andMatrixOutputs_lo_260}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_5_2_1 = &_decoder_decoded_andMatrixOutputs_T_260; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_154, decoder_decoded_andMatrixOutputs_andMatrixInput_13_151}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_240 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_158, decoder_decoded_andMatrixOutputs_andMatrixInput_14_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_164, decoder_decoded_andMatrixOutputs_andMatrixInput_11_158}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_204, decoder_decoded_andMatrixOutputs_andMatrixInput_9_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_259 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_169, decoder_decoded_andMatrixOutputs_lo_hi_lo_151}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_261 = {decoder_decoded_andMatrixOutputs_lo_hi_259, decoder_decoded_andMatrixOutputs_lo_lo_240}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_136 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_253, decoder_decoded_andMatrixOutputs_andMatrixInput_7_240}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_261, decoder_decoded_andMatrixOutputs_andMatrixInput_5_259}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_253 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_164, decoder_decoded_andMatrixOutputs_hi_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_261, decoder_decoded_andMatrixOutputs_andMatrixInput_3_261}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_261, decoder_decoded_andMatrixOutputs_andMatrixInput_1_261}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_261 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_204, decoder_decoded_andMatrixOutputs_hi_hi_lo_154}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_261 = {decoder_decoded_andMatrixOutputs_hi_hi_261, decoder_decoded_andMatrixOutputs_hi_lo_253}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_261 = {decoder_decoded_andMatrixOutputs_hi_261, decoder_decoded_andMatrixOutputs_lo_261}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_87_2_1 = &_decoder_decoded_andMatrixOutputs_T_261; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_155, decoder_decoded_andMatrixOutputs_andMatrixInput_13_152}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_241 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_159, decoder_decoded_andMatrixOutputs_andMatrixInput_14_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_165, decoder_decoded_andMatrixOutputs_andMatrixInput_11_159}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_205, decoder_decoded_andMatrixOutputs_andMatrixInput_9_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_260 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_170, decoder_decoded_andMatrixOutputs_lo_hi_lo_152}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_262 = {decoder_decoded_andMatrixOutputs_lo_hi_260, decoder_decoded_andMatrixOutputs_lo_lo_241}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_137 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_254, decoder_decoded_andMatrixOutputs_andMatrixInput_7_241}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_262, decoder_decoded_andMatrixOutputs_andMatrixInput_5_260}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_254 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_165, decoder_decoded_andMatrixOutputs_hi_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_262, decoder_decoded_andMatrixOutputs_andMatrixInput_3_262}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_262, decoder_decoded_andMatrixOutputs_andMatrixInput_1_262}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_262 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_205, decoder_decoded_andMatrixOutputs_hi_hi_lo_155}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_262 = {decoder_decoded_andMatrixOutputs_hi_hi_262, decoder_decoded_andMatrixOutputs_hi_lo_254}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_262 = {decoder_decoded_andMatrixOutputs_hi_262, decoder_decoded_andMatrixOutputs_lo_262}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_93_2_1 = &_decoder_decoded_andMatrixOutputs_T_262; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_255, decoder_decoded_andMatrixOutputs_andMatrixInput_7_242}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_263, decoder_decoded_andMatrixOutputs_andMatrixInput_5_261}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_263 = {decoder_decoded_andMatrixOutputs_lo_hi_261, decoder_decoded_andMatrixOutputs_lo_lo_242}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_263, decoder_decoded_andMatrixOutputs_andMatrixInput_3_263}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_263, decoder_decoded_andMatrixOutputs_andMatrixInput_1_263}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_263 = {decoder_decoded_andMatrixOutputs_hi_hi_263, decoder_decoded_andMatrixOutputs_hi_lo_255}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_263 = {decoder_decoded_andMatrixOutputs_hi_263, decoder_decoded_andMatrixOutputs_lo_263}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_65_2_1 = &_decoder_decoded_andMatrixOutputs_T_263; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_243, decoder_decoded_andMatrixOutputs_andMatrixInput_8_206}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_262, decoder_decoded_andMatrixOutputs_andMatrixInput_6_256}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_264 = {decoder_decoded_andMatrixOutputs_lo_hi_262, decoder_decoded_andMatrixOutputs_lo_lo_243}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_264, decoder_decoded_andMatrixOutputs_andMatrixInput_4_264}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_264, decoder_decoded_andMatrixOutputs_andMatrixInput_1_264}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_264 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_206, decoder_decoded_andMatrixOutputs_andMatrixInput_2_264}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_264 = {decoder_decoded_andMatrixOutputs_hi_hi_264, decoder_decoded_andMatrixOutputs_hi_lo_256}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_264 = {decoder_decoded_andMatrixOutputs_hi_264, decoder_decoded_andMatrixOutputs_lo_264}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_125_2_1 = &_decoder_decoded_andMatrixOutputs_T_264; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_244, decoder_decoded_andMatrixOutputs_andMatrixInput_8_207}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_263, decoder_decoded_andMatrixOutputs_andMatrixInput_6_257}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_265 = {decoder_decoded_andMatrixOutputs_lo_hi_263, decoder_decoded_andMatrixOutputs_lo_lo_244}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_257 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_265, decoder_decoded_andMatrixOutputs_andMatrixInput_4_265}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_265, decoder_decoded_andMatrixOutputs_andMatrixInput_1_265}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_265 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_207, decoder_decoded_andMatrixOutputs_andMatrixInput_2_265}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_265 = {decoder_decoded_andMatrixOutputs_hi_hi_265, decoder_decoded_andMatrixOutputs_hi_lo_257}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_265 = {decoder_decoded_andMatrixOutputs_hi_265, decoder_decoded_andMatrixOutputs_lo_265}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_90_2_1 = &_decoder_decoded_andMatrixOutputs_T_265; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_245 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_245, decoder_decoded_andMatrixOutputs_andMatrixInput_8_208}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_264 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_264, decoder_decoded_andMatrixOutputs_andMatrixInput_6_258}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_266 = {decoder_decoded_andMatrixOutputs_lo_hi_264, decoder_decoded_andMatrixOutputs_lo_lo_245}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_258 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_266, decoder_decoded_andMatrixOutputs_andMatrixInput_4_266}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_266, decoder_decoded_andMatrixOutputs_andMatrixInput_1_266}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_266 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_208, decoder_decoded_andMatrixOutputs_andMatrixInput_2_266}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_266 = {decoder_decoded_andMatrixOutputs_hi_hi_266, decoder_decoded_andMatrixOutputs_hi_lo_258}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_266 = {decoder_decoded_andMatrixOutputs_hi_266, decoder_decoded_andMatrixOutputs_lo_266}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_111_2_1 = &_decoder_decoded_andMatrixOutputs_T_266; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_156, decoder_decoded_andMatrixOutputs_andMatrixInput_13_153}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_246 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_160, decoder_decoded_andMatrixOutputs_andMatrixInput_14_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_166, decoder_decoded_andMatrixOutputs_andMatrixInput_11_160}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_209, decoder_decoded_andMatrixOutputs_andMatrixInput_9_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_265 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_171, decoder_decoded_andMatrixOutputs_lo_hi_lo_153}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_267 = {decoder_decoded_andMatrixOutputs_lo_hi_265, decoder_decoded_andMatrixOutputs_lo_lo_246}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_138 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_259, decoder_decoded_andMatrixOutputs_andMatrixInput_7_246}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_267, decoder_decoded_andMatrixOutputs_andMatrixInput_5_265}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_259 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_166, decoder_decoded_andMatrixOutputs_hi_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_267, decoder_decoded_andMatrixOutputs_andMatrixInput_3_267}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_267, decoder_decoded_andMatrixOutputs_andMatrixInput_1_267}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_267 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_209, decoder_decoded_andMatrixOutputs_hi_hi_lo_156}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_267 = {decoder_decoded_andMatrixOutputs_hi_hi_267, decoder_decoded_andMatrixOutputs_hi_lo_259}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_267 = {decoder_decoded_andMatrixOutputs_hi_267, decoder_decoded_andMatrixOutputs_lo_267}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_172_2_1 = &_decoder_decoded_andMatrixOutputs_T_267; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_260, decoder_decoded_andMatrixOutputs_andMatrixInput_7_247}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_268, decoder_decoded_andMatrixOutputs_andMatrixInput_5_266}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_268 = {decoder_decoded_andMatrixOutputs_lo_hi_266, decoder_decoded_andMatrixOutputs_lo_lo_247}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_268, decoder_decoded_andMatrixOutputs_andMatrixInput_3_268}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_268 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_268, decoder_decoded_andMatrixOutputs_andMatrixInput_1_268}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_268 = {decoder_decoded_andMatrixOutputs_hi_hi_268, decoder_decoded_andMatrixOutputs_hi_lo_260}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_268 = {decoder_decoded_andMatrixOutputs_hi_268, decoder_decoded_andMatrixOutputs_lo_268}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_146_2_1 = &_decoder_decoded_andMatrixOutputs_T_268; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_248, decoder_decoded_andMatrixOutputs_andMatrixInput_8_210}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_267 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_267, decoder_decoded_andMatrixOutputs_andMatrixInput_6_261}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_269 = {decoder_decoded_andMatrixOutputs_lo_hi_267, decoder_decoded_andMatrixOutputs_lo_lo_248}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_269, decoder_decoded_andMatrixOutputs_andMatrixInput_4_269}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_269, decoder_decoded_andMatrixOutputs_andMatrixInput_1_269}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_269 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_2_269}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_269 = {decoder_decoded_andMatrixOutputs_hi_hi_269, decoder_decoded_andMatrixOutputs_hi_lo_261}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_269 = {decoder_decoded_andMatrixOutputs_hi_269, decoder_decoded_andMatrixOutputs_lo_269}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_170_2_1 = &_decoder_decoded_andMatrixOutputs_T_269; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_249, decoder_decoded_andMatrixOutputs_andMatrixInput_8_211}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_268 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_268, decoder_decoded_andMatrixOutputs_andMatrixInput_6_262}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_270 = {decoder_decoded_andMatrixOutputs_lo_hi_268, decoder_decoded_andMatrixOutputs_lo_lo_249}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_270, decoder_decoded_andMatrixOutputs_andMatrixInput_4_270}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_270, decoder_decoded_andMatrixOutputs_andMatrixInput_1_270}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_270 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_211, decoder_decoded_andMatrixOutputs_andMatrixInput_2_270}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_270 = {decoder_decoded_andMatrixOutputs_hi_hi_270, decoder_decoded_andMatrixOutputs_hi_lo_262}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_270 = {decoder_decoded_andMatrixOutputs_hi_270, decoder_decoded_andMatrixOutputs_lo_270}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_2_2_1 = &_decoder_decoded_andMatrixOutputs_T_270; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_212, decoder_decoded_andMatrixOutputs_andMatrixInput_9_172}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_269, decoder_decoded_andMatrixOutputs_andMatrixInput_6_263}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_269 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_7_250}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_271 = {decoder_decoded_andMatrixOutputs_lo_hi_269, decoder_decoded_andMatrixOutputs_lo_lo_250}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_271, decoder_decoded_andMatrixOutputs_andMatrixInput_4_271}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_271, decoder_decoded_andMatrixOutputs_andMatrixInput_1_271}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_271 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_2_271}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_271 = {decoder_decoded_andMatrixOutputs_hi_hi_271, decoder_decoded_andMatrixOutputs_hi_lo_263}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_271 = {decoder_decoded_andMatrixOutputs_hi_271, decoder_decoded_andMatrixOutputs_lo_271}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_15_2_1 = &_decoder_decoded_andMatrixOutputs_T_271; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_213 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_174 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_272 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_253 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_216 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_217 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_218 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_257 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_220 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_221 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_226 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_187 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_188 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_189 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_184 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_176 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_100 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_211 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_212 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_213 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_226 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_227 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_231 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_140 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_22 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_15 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_271 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_154 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_237 = decoder_decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_157, decoder_decoded_andMatrixOutputs_andMatrixInput_13_154}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_251 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_161, decoder_decoded_andMatrixOutputs_andMatrixInput_14_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_167, decoder_decoded_andMatrixOutputs_andMatrixInput_11_161}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_173 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_213, decoder_decoded_andMatrixOutputs_andMatrixInput_9_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_270 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_173, decoder_decoded_andMatrixOutputs_lo_hi_lo_154}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_272 = {decoder_decoded_andMatrixOutputs_lo_hi_270, decoder_decoded_andMatrixOutputs_lo_lo_251}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_139 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_264, decoder_decoded_andMatrixOutputs_andMatrixInput_7_251}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_272, decoder_decoded_andMatrixOutputs_andMatrixInput_5_270}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_264 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_167, decoder_decoded_andMatrixOutputs_hi_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_272, decoder_decoded_andMatrixOutputs_andMatrixInput_3_272}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_272, decoder_decoded_andMatrixOutputs_andMatrixInput_1_272}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_272 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_213, decoder_decoded_andMatrixOutputs_hi_hi_lo_157}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_272 = {decoder_decoded_andMatrixOutputs_hi_hi_272, decoder_decoded_andMatrixOutputs_hi_lo_264}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_272 = {decoder_decoded_andMatrixOutputs_hi_272, decoder_decoded_andMatrixOutputs_lo_272}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_167_2_1 = &_decoder_decoded_andMatrixOutputs_T_272; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_140, decoder_decoded_andMatrixOutputs_andMatrixInput_15_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_158, decoder_decoded_andMatrixOutputs_andMatrixInput_13_155}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_252 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_162, decoder_decoded_andMatrixOutputs_lo_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_168, decoder_decoded_andMatrixOutputs_andMatrixInput_11_162}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_214, decoder_decoded_andMatrixOutputs_andMatrixInput_9_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_271 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_174, decoder_decoded_andMatrixOutputs_lo_hi_lo_155}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_273 = {decoder_decoded_andMatrixOutputs_lo_hi_271, decoder_decoded_andMatrixOutputs_lo_lo_252}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_140 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_265, decoder_decoded_andMatrixOutputs_andMatrixInput_7_252}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_273, decoder_decoded_andMatrixOutputs_andMatrixInput_5_271}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_265 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_168, decoder_decoded_andMatrixOutputs_hi_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_273, decoder_decoded_andMatrixOutputs_andMatrixInput_3_273}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_273, decoder_decoded_andMatrixOutputs_andMatrixInput_1_273}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_273 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_214, decoder_decoded_andMatrixOutputs_hi_hi_lo_158}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_273 = {decoder_decoded_andMatrixOutputs_hi_hi_273, decoder_decoded_andMatrixOutputs_hi_lo_265}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_273 = {decoder_decoded_andMatrixOutputs_hi_273, decoder_decoded_andMatrixOutputs_lo_273}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_108_2_1 = &_decoder_decoded_andMatrixOutputs_T_273; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_272 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_274, decoder_decoded_andMatrixOutputs_andMatrixInput_5_272}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_274 = {decoder_decoded_andMatrixOutputs_lo_hi_272, decoder_decoded_andMatrixOutputs_andMatrixInput_6_266}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_274, decoder_decoded_andMatrixOutputs_andMatrixInput_3_274}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_274 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_274, decoder_decoded_andMatrixOutputs_andMatrixInput_1_274}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_274 = {decoder_decoded_andMatrixOutputs_hi_hi_274, decoder_decoded_andMatrixOutputs_hi_lo_266}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_274 = {decoder_decoded_andMatrixOutputs_hi_274, decoder_decoded_andMatrixOutputs_lo_274}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_75_2_1 = &_decoder_decoded_andMatrixOutputs_T_274; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_175, decoder_decoded_andMatrixOutputs_andMatrixInput_10_169}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_253 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_163, decoder_decoded_andMatrixOutputs_andMatrixInput_11_163}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_267, decoder_decoded_andMatrixOutputs_andMatrixInput_7_253}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_273 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_175, decoder_decoded_andMatrixOutputs_andMatrixInput_8_215}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_275 = {decoder_decoded_andMatrixOutputs_lo_hi_273, decoder_decoded_andMatrixOutputs_lo_lo_253}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_275, decoder_decoded_andMatrixOutputs_andMatrixInput_4_275}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_267 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_169, decoder_decoded_andMatrixOutputs_andMatrixInput_5_273}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_275, decoder_decoded_andMatrixOutputs_andMatrixInput_1_275}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_275 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_2_275}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_275 = {decoder_decoded_andMatrixOutputs_hi_hi_275, decoder_decoded_andMatrixOutputs_hi_lo_267}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_275 = {decoder_decoded_andMatrixOutputs_hi_275, decoder_decoded_andMatrixOutputs_lo_275}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_86_2_1 = &_decoder_decoded_andMatrixOutputs_T_275; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_159, decoder_decoded_andMatrixOutputs_andMatrixInput_13_156}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_254 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_164, decoder_decoded_andMatrixOutputs_andMatrixInput_14_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_170, decoder_decoded_andMatrixOutputs_andMatrixInput_11_164}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_216, decoder_decoded_andMatrixOutputs_andMatrixInput_9_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_274 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_176, decoder_decoded_andMatrixOutputs_lo_hi_lo_156}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_276 = {decoder_decoded_andMatrixOutputs_lo_hi_274, decoder_decoded_andMatrixOutputs_lo_lo_254}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_141 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_268, decoder_decoded_andMatrixOutputs_andMatrixInput_7_254}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_276, decoder_decoded_andMatrixOutputs_andMatrixInput_5_274}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_268 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_170, decoder_decoded_andMatrixOutputs_hi_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_276, decoder_decoded_andMatrixOutputs_andMatrixInput_3_276}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_276, decoder_decoded_andMatrixOutputs_andMatrixInput_1_276}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_276 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_216, decoder_decoded_andMatrixOutputs_hi_hi_lo_159}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_276 = {decoder_decoded_andMatrixOutputs_hi_hi_276, decoder_decoded_andMatrixOutputs_hi_lo_268}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_276 = {decoder_decoded_andMatrixOutputs_hi_276, decoder_decoded_andMatrixOutputs_lo_276}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_144_2_1 = &_decoder_decoded_andMatrixOutputs_T_276; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_160, decoder_decoded_andMatrixOutputs_andMatrixInput_13_157}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_255 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_165, decoder_decoded_andMatrixOutputs_andMatrixInput_14_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_171, decoder_decoded_andMatrixOutputs_andMatrixInput_11_165}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_177 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_217, decoder_decoded_andMatrixOutputs_andMatrixInput_9_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_275 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_177, decoder_decoded_andMatrixOutputs_lo_hi_lo_157}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_277 = {decoder_decoded_andMatrixOutputs_lo_hi_275, decoder_decoded_andMatrixOutputs_lo_lo_255}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_142 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_269, decoder_decoded_andMatrixOutputs_andMatrixInput_7_255}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_277, decoder_decoded_andMatrixOutputs_andMatrixInput_5_275}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_269 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_171, decoder_decoded_andMatrixOutputs_hi_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_277, decoder_decoded_andMatrixOutputs_andMatrixInput_3_277}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_277, decoder_decoded_andMatrixOutputs_andMatrixInput_1_277}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_277 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_217, decoder_decoded_andMatrixOutputs_hi_hi_lo_160}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_277 = {decoder_decoded_andMatrixOutputs_hi_hi_277, decoder_decoded_andMatrixOutputs_hi_lo_269}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_277 = {decoder_decoded_andMatrixOutputs_hi_277, decoder_decoded_andMatrixOutputs_lo_277}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_36_2_1 = &_decoder_decoded_andMatrixOutputs_T_277; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_166, decoder_decoded_andMatrixOutputs_andMatrixInput_12_161}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_256 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_166, decoder_decoded_andMatrixOutputs_andMatrixInput_13_158}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_178, decoder_decoded_andMatrixOutputs_andMatrixInput_10_172}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_256, decoder_decoded_andMatrixOutputs_andMatrixInput_8_218}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_276 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_178, decoder_decoded_andMatrixOutputs_lo_hi_lo_158}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_278 = {decoder_decoded_andMatrixOutputs_lo_hi_276, decoder_decoded_andMatrixOutputs_lo_lo_256}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_278, decoder_decoded_andMatrixOutputs_andMatrixInput_5_276}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_270 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_6_270}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_278, decoder_decoded_andMatrixOutputs_andMatrixInput_3_278}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_278, decoder_decoded_andMatrixOutputs_andMatrixInput_1_278}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_278 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_218, decoder_decoded_andMatrixOutputs_hi_hi_lo_161}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_278 = {decoder_decoded_andMatrixOutputs_hi_hi_278, decoder_decoded_andMatrixOutputs_hi_lo_270}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_278 = {decoder_decoded_andMatrixOutputs_hi_278, decoder_decoded_andMatrixOutputs_lo_278}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_41_2_1 = &_decoder_decoded_andMatrixOutputs_T_278; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_167, decoder_decoded_andMatrixOutputs_andMatrixInput_12_162}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_257 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_167, decoder_decoded_andMatrixOutputs_andMatrixInput_13_159}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_179, decoder_decoded_andMatrixOutputs_andMatrixInput_10_173}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_179 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_257, decoder_decoded_andMatrixOutputs_andMatrixInput_8_219}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_277 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_179, decoder_decoded_andMatrixOutputs_lo_hi_lo_159}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_279 = {decoder_decoded_andMatrixOutputs_lo_hi_277, decoder_decoded_andMatrixOutputs_lo_lo_257}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_173 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_279, decoder_decoded_andMatrixOutputs_andMatrixInput_5_277}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_271 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_173, decoder_decoded_andMatrixOutputs_andMatrixInput_6_271}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_279, decoder_decoded_andMatrixOutputs_andMatrixInput_3_279}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_279, decoder_decoded_andMatrixOutputs_andMatrixInput_1_279}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_279 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_219, decoder_decoded_andMatrixOutputs_hi_hi_lo_162}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_279 = {decoder_decoded_andMatrixOutputs_hi_hi_279, decoder_decoded_andMatrixOutputs_hi_lo_271}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_279 = {decoder_decoded_andMatrixOutputs_hi_279, decoder_decoded_andMatrixOutputs_lo_279}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_8_2_1 = &_decoder_decoded_andMatrixOutputs_T_279; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_84 = decoder_decoded_andMatrixOutputs_8_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_163, decoder_decoded_andMatrixOutputs_andMatrixInput_13_160}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_258 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_168, decoder_decoded_andMatrixOutputs_andMatrixInput_14_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_174, decoder_decoded_andMatrixOutputs_andMatrixInput_11_168}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_220, decoder_decoded_andMatrixOutputs_andMatrixInput_9_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_278 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_180, decoder_decoded_andMatrixOutputs_lo_hi_lo_160}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_280 = {decoder_decoded_andMatrixOutputs_lo_hi_278, decoder_decoded_andMatrixOutputs_lo_lo_258}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_272, decoder_decoded_andMatrixOutputs_andMatrixInput_7_258}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_280, decoder_decoded_andMatrixOutputs_andMatrixInput_5_278}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_272 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_174, decoder_decoded_andMatrixOutputs_hi_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_280, decoder_decoded_andMatrixOutputs_andMatrixInput_3_280}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_280, decoder_decoded_andMatrixOutputs_andMatrixInput_1_280}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_280 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_220, decoder_decoded_andMatrixOutputs_hi_hi_lo_163}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_280 = {decoder_decoded_andMatrixOutputs_hi_hi_280, decoder_decoded_andMatrixOutputs_hi_lo_272}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_280 = {decoder_decoded_andMatrixOutputs_hi_280, decoder_decoded_andMatrixOutputs_lo_280}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_102_2_1 = &_decoder_decoded_andMatrixOutputs_T_280; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_164, decoder_decoded_andMatrixOutputs_andMatrixInput_13_161}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_259 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_169, decoder_decoded_andMatrixOutputs_andMatrixInput_14_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_175, decoder_decoded_andMatrixOutputs_andMatrixInput_11_169}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_181 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_221, decoder_decoded_andMatrixOutputs_andMatrixInput_9_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_279 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_181, decoder_decoded_andMatrixOutputs_lo_hi_lo_161}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_281 = {decoder_decoded_andMatrixOutputs_lo_hi_279, decoder_decoded_andMatrixOutputs_lo_lo_259}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_273, decoder_decoded_andMatrixOutputs_andMatrixInput_7_259}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_281, decoder_decoded_andMatrixOutputs_andMatrixInput_5_279}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_273 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_175, decoder_decoded_andMatrixOutputs_hi_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_281, decoder_decoded_andMatrixOutputs_andMatrixInput_3_281}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_281, decoder_decoded_andMatrixOutputs_andMatrixInput_1_281}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_281 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_221, decoder_decoded_andMatrixOutputs_hi_hi_lo_164}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_281 = {decoder_decoded_andMatrixOutputs_hi_hi_281, decoder_decoded_andMatrixOutputs_hi_lo_273}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_281 = {decoder_decoded_andMatrixOutputs_hi_281, decoder_decoded_andMatrixOutputs_lo_281}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_72_2_1 = &_decoder_decoded_andMatrixOutputs_T_281; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_165 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_171 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_184 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_36 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_180 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_175 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_176 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_199 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_202 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_203 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_198 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_199 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_45 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_230 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_237 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_232 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_226 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_234 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_228 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_225 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_226 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_203 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_57 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_23_14 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_27_15 = decoder_decoded_plaInput_1[27]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_86, decoder_decoded_andMatrixOutputs_andMatrixInput_16_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_162, decoder_decoded_andMatrixOutputs_andMatrixInput_14_145}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_260 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_170, decoder_decoded_andMatrixOutputs_lo_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_170, decoder_decoded_andMatrixOutputs_andMatrixInput_12_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_182, decoder_decoded_andMatrixOutputs_andMatrixInput_10_176}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_280 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_182, decoder_decoded_andMatrixOutputs_lo_hi_lo_162}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_282 = {decoder_decoded_andMatrixOutputs_lo_hi_280, decoder_decoded_andMatrixOutputs_lo_lo_260}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_260, decoder_decoded_andMatrixOutputs_andMatrixInput_8_222}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_280, decoder_decoded_andMatrixOutputs_andMatrixInput_6_274}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_274 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_176, decoder_decoded_andMatrixOutputs_hi_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_282, decoder_decoded_andMatrixOutputs_andMatrixInput_4_282}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_282, decoder_decoded_andMatrixOutputs_andMatrixInput_1_282}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_222 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_2_282}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_282 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_222, decoder_decoded_andMatrixOutputs_hi_hi_lo_165}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_282 = {decoder_decoded_andMatrixOutputs_hi_hi_282, decoder_decoded_andMatrixOutputs_hi_lo_274}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_282 = {decoder_decoded_andMatrixOutputs_hi_282, decoder_decoded_andMatrixOutputs_lo_282}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_189_2_1 = &_decoder_decoded_andMatrixOutputs_T_282; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_146, decoder_decoded_andMatrixOutputs_andMatrixInput_15_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_166, decoder_decoded_andMatrixOutputs_andMatrixInput_13_163}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_261 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_171, decoder_decoded_andMatrixOutputs_lo_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_177, decoder_decoded_andMatrixOutputs_andMatrixInput_11_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_223, decoder_decoded_andMatrixOutputs_andMatrixInput_9_183}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_281 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_183, decoder_decoded_andMatrixOutputs_lo_hi_lo_163}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_283 = {decoder_decoded_andMatrixOutputs_lo_hi_281, decoder_decoded_andMatrixOutputs_lo_lo_261}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_275, decoder_decoded_andMatrixOutputs_andMatrixInput_7_261}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_177 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_283, decoder_decoded_andMatrixOutputs_andMatrixInput_5_281}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_275 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_177, decoder_decoded_andMatrixOutputs_hi_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_283, decoder_decoded_andMatrixOutputs_andMatrixInput_3_283}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_283, decoder_decoded_andMatrixOutputs_andMatrixInput_1_283}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_283 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_223, decoder_decoded_andMatrixOutputs_hi_hi_lo_166}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_283 = {decoder_decoded_andMatrixOutputs_hi_hi_283, decoder_decoded_andMatrixOutputs_hi_lo_275}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_283 = {decoder_decoded_andMatrixOutputs_hi_283, decoder_decoded_andMatrixOutputs_lo_283}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_28_2_1 = &_decoder_decoded_andMatrixOutputs_T_283; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_178, decoder_decoded_andMatrixOutputs_andMatrixInput_11_172}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_262 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_172, decoder_decoded_andMatrixOutputs_andMatrixInput_12_167}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_262, decoder_decoded_andMatrixOutputs_andMatrixInput_8_224}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_282 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_184, decoder_decoded_andMatrixOutputs_andMatrixInput_9_184}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_284 = {decoder_decoded_andMatrixOutputs_lo_hi_282, decoder_decoded_andMatrixOutputs_lo_lo_262}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_284, decoder_decoded_andMatrixOutputs_andMatrixInput_5_282}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_276 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_178, decoder_decoded_andMatrixOutputs_andMatrixInput_6_276}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_284, decoder_decoded_andMatrixOutputs_andMatrixInput_3_284}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_284, decoder_decoded_andMatrixOutputs_andMatrixInput_1_284}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_284 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_224, decoder_decoded_andMatrixOutputs_hi_hi_lo_167}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_284 = {decoder_decoded_andMatrixOutputs_hi_hi_284, decoder_decoded_andMatrixOutputs_hi_lo_276}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_284 = {decoder_decoded_andMatrixOutputs_hi_284, decoder_decoded_andMatrixOutputs_lo_284}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_0_2_1 = &_decoder_decoded_andMatrixOutputs_T_284; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_179 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_267 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_190 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_38 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_21 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_314 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_315 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_316 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_317 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_326 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_327 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_328 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_344 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_255 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_250 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_257 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_84 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_29 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_349 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_350 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_274 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_275 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_282 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_283 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_278 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_285 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_280 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_281 = decoder_decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_19, decoder_decoded_andMatrixOutputs_andMatrixInput_21_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_36, decoder_decoded_andMatrixOutputs_andMatrixInput_18_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_173 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_19_27}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_263 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_173, decoder_decoded_andMatrixOutputs_lo_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_147, decoder_decoded_andMatrixOutputs_andMatrixInput_15_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_164 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_173, decoder_decoded_andMatrixOutputs_andMatrixInput_12_168}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_185 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_164}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_283 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_185, decoder_decoded_andMatrixOutputs_lo_hi_lo_164}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_285 = {decoder_decoded_andMatrixOutputs_lo_hi_283, decoder_decoded_andMatrixOutputs_lo_lo_263}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_185, decoder_decoded_andMatrixOutputs_andMatrixInput_10_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_277, decoder_decoded_andMatrixOutputs_andMatrixInput_7_263}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_179 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_andMatrixInput_8_225}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_277 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_179, decoder_decoded_andMatrixOutputs_hi_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_285, decoder_decoded_andMatrixOutputs_andMatrixInput_4_285}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_168 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_283}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_285, decoder_decoded_andMatrixOutputs_andMatrixInput_1_285}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_225 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_2_285}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_285 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_225, decoder_decoded_andMatrixOutputs_hi_hi_lo_168}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_285 = {decoder_decoded_andMatrixOutputs_hi_hi_285, decoder_decoded_andMatrixOutputs_hi_lo_277}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_285 = {decoder_decoded_andMatrixOutputs_hi_285, decoder_decoded_andMatrixOutputs_lo_285}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_59_2_1 = &_decoder_decoded_andMatrixOutputs_T_285; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_169, decoder_decoded_andMatrixOutputs_andMatrixInput_13_165}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_264 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_174, decoder_decoded_andMatrixOutputs_andMatrixInput_14_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_180, decoder_decoded_andMatrixOutputs_andMatrixInput_11_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_226, decoder_decoded_andMatrixOutputs_andMatrixInput_9_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_284 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_186, decoder_decoded_andMatrixOutputs_lo_hi_lo_165}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_286 = {decoder_decoded_andMatrixOutputs_lo_hi_284, decoder_decoded_andMatrixOutputs_lo_lo_264}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_278, decoder_decoded_andMatrixOutputs_andMatrixInput_7_264}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_286, decoder_decoded_andMatrixOutputs_andMatrixInput_5_284}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_278 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_180, decoder_decoded_andMatrixOutputs_hi_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_286, decoder_decoded_andMatrixOutputs_andMatrixInput_3_286}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_286, decoder_decoded_andMatrixOutputs_andMatrixInput_1_286}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_286 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_226, decoder_decoded_andMatrixOutputs_hi_hi_lo_169}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_286 = {decoder_decoded_andMatrixOutputs_hi_hi_286, decoder_decoded_andMatrixOutputs_hi_lo_278}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_286 = {decoder_decoded_andMatrixOutputs_hi_286, decoder_decoded_andMatrixOutputs_lo_286}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_43_2_1 = &_decoder_decoded_andMatrixOutputs_T_286; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_149, decoder_decoded_andMatrixOutputs_andMatrixInput_15_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_170, decoder_decoded_andMatrixOutputs_andMatrixInput_13_166}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_265 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_175, decoder_decoded_andMatrixOutputs_lo_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_181, decoder_decoded_andMatrixOutputs_andMatrixInput_11_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_227, decoder_decoded_andMatrixOutputs_andMatrixInput_9_187}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_285 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_187, decoder_decoded_andMatrixOutputs_lo_hi_lo_166}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_287 = {decoder_decoded_andMatrixOutputs_lo_hi_285, decoder_decoded_andMatrixOutputs_lo_lo_265}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_279, decoder_decoded_andMatrixOutputs_andMatrixInput_7_265}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_181 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_287, decoder_decoded_andMatrixOutputs_andMatrixInput_5_285}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_279 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_181, decoder_decoded_andMatrixOutputs_hi_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_287, decoder_decoded_andMatrixOutputs_andMatrixInput_3_287}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_287, decoder_decoded_andMatrixOutputs_andMatrixInput_1_287}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_287 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_227, decoder_decoded_andMatrixOutputs_hi_hi_lo_170}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_287 = {decoder_decoded_andMatrixOutputs_hi_hi_287, decoder_decoded_andMatrixOutputs_hi_lo_279}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_287 = {decoder_decoded_andMatrixOutputs_hi_287, decoder_decoded_andMatrixOutputs_lo_287}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_169_2_1 = &_decoder_decoded_andMatrixOutputs_T_287; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_150, decoder_decoded_andMatrixOutputs_andMatrixInput_15_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_171, decoder_decoded_andMatrixOutputs_andMatrixInput_13_167}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_266 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_176, decoder_decoded_andMatrixOutputs_lo_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_182, decoder_decoded_andMatrixOutputs_andMatrixInput_11_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_228, decoder_decoded_andMatrixOutputs_andMatrixInput_9_188}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_286 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_188, decoder_decoded_andMatrixOutputs_lo_hi_lo_167}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_288 = {decoder_decoded_andMatrixOutputs_lo_hi_286, decoder_decoded_andMatrixOutputs_lo_lo_266}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_280, decoder_decoded_andMatrixOutputs_andMatrixInput_7_266}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_288, decoder_decoded_andMatrixOutputs_andMatrixInput_5_286}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_280 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_182, decoder_decoded_andMatrixOutputs_hi_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_288, decoder_decoded_andMatrixOutputs_andMatrixInput_3_288}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_288, decoder_decoded_andMatrixOutputs_andMatrixInput_1_288}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_288 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_228, decoder_decoded_andMatrixOutputs_hi_hi_lo_171}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_288 = {decoder_decoded_andMatrixOutputs_hi_hi_288, decoder_decoded_andMatrixOutputs_hi_lo_280}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_288 = {decoder_decoded_andMatrixOutputs_hi_288, decoder_decoded_andMatrixOutputs_lo_288}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_164_2_1 = &_decoder_decoded_andMatrixOutputs_T_288; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_168 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_92 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_10 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_5 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_12 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_6 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_174 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_158 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_59 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_36 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_193 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_201 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_202 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_128 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_14 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_28_7 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_258 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_259 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_66 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_67 = decoder_decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_91, decoder_decoded_andMatrixOutputs_andMatrixInput_16_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_177 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_168, decoder_decoded_andMatrixOutputs_andMatrixInput_14_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_267 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_177, decoder_decoded_andMatrixOutputs_lo_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_177, decoder_decoded_andMatrixOutputs_andMatrixInput_12_172}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_189, decoder_decoded_andMatrixOutputs_andMatrixInput_10_183}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_287 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_189, decoder_decoded_andMatrixOutputs_lo_hi_lo_168}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_289 = {decoder_decoded_andMatrixOutputs_lo_hi_287, decoder_decoded_andMatrixOutputs_lo_lo_267}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_267, decoder_decoded_andMatrixOutputs_andMatrixInput_8_229}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_287, decoder_decoded_andMatrixOutputs_andMatrixInput_6_281}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_281 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_183, decoder_decoded_andMatrixOutputs_hi_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_289, decoder_decoded_andMatrixOutputs_andMatrixInput_4_289}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_289, decoder_decoded_andMatrixOutputs_andMatrixInput_1_289}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_229 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_2_289}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_289 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_229, decoder_decoded_andMatrixOutputs_hi_hi_lo_172}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_289 = {decoder_decoded_andMatrixOutputs_hi_hi_289, decoder_decoded_andMatrixOutputs_hi_lo_281}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_289 = {decoder_decoded_andMatrixOutputs_hi_289, decoder_decoded_andMatrixOutputs_lo_289}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_137_2_1 = &_decoder_decoded_andMatrixOutputs_T_289; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_37, decoder_decoded_andMatrixOutputs_andMatrixInput_18_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_92, decoder_decoded_andMatrixOutputs_andMatrixInput_16_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_268 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_178, decoder_decoded_andMatrixOutputs_lo_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_169, decoder_decoded_andMatrixOutputs_andMatrixInput_14_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_184, decoder_decoded_andMatrixOutputs_andMatrixInput_11_178}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_190 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_12_173}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_288 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_190, decoder_decoded_andMatrixOutputs_lo_hi_lo_169}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_290 = {decoder_decoded_andMatrixOutputs_lo_hi_288, decoder_decoded_andMatrixOutputs_lo_lo_268}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_230, decoder_decoded_andMatrixOutputs_andMatrixInput_9_190}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_288, decoder_decoded_andMatrixOutputs_andMatrixInput_6_282}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_184 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_268}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_282 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_184, decoder_decoded_andMatrixOutputs_hi_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_173 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_290, decoder_decoded_andMatrixOutputs_andMatrixInput_4_290}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_290, decoder_decoded_andMatrixOutputs_andMatrixInput_1_290}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_230 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_2_290}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_290 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_230, decoder_decoded_andMatrixOutputs_hi_hi_lo_173}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_290 = {decoder_decoded_andMatrixOutputs_hi_hi_290, decoder_decoded_andMatrixOutputs_hi_lo_282}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_290 = {decoder_decoded_andMatrixOutputs_hi_290, decoder_decoded_andMatrixOutputs_lo_290}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_73_2_1 = &_decoder_decoded_andMatrixOutputs_T_290; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_31 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_16 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_206 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_276 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_277 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_58 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_23 = decoder_decoded_plaInput_1[21]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_10, decoder_decoded_andMatrixOutputs_andMatrixInput_26_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_93 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_27_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_10, decoder_decoded_andMatrixOutputs_andMatrixInput_24_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_15, decoder_decoded_andMatrixOutputs_andMatrixInput_22_10}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_179 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_269 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_179, decoder_decoded_andMatrixOutputs_lo_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_31, decoder_decoded_andMatrixOutputs_andMatrixInput_19_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_170 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_20_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_53, decoder_decoded_andMatrixOutputs_andMatrixInput_17_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_153, decoder_decoded_andMatrixOutputs_andMatrixInput_15_93}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_191 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_289 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_191, decoder_decoded_andMatrixOutputs_lo_hi_lo_170}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_291 = {decoder_decoded_andMatrixOutputs_lo_hi_289, decoder_decoded_andMatrixOutputs_lo_lo_269}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_179, decoder_decoded_andMatrixOutputs_andMatrixInput_12_174}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_153 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_170}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_191, decoder_decoded_andMatrixOutputs_andMatrixInput_10_185}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_269, decoder_decoded_andMatrixOutputs_andMatrixInput_8_231}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_185 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_283 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_185, decoder_decoded_andMatrixOutputs_hi_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_291, decoder_decoded_andMatrixOutputs_andMatrixInput_5_289}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_174 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_6_283}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_291, decoder_decoded_andMatrixOutputs_andMatrixInput_3_291}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_291, decoder_decoded_andMatrixOutputs_andMatrixInput_1_291}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_231 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_291 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_231, decoder_decoded_andMatrixOutputs_hi_hi_lo_174}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_291 = {decoder_decoded_andMatrixOutputs_hi_hi_291, decoder_decoded_andMatrixOutputs_hi_lo_283}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_291 = {decoder_decoded_andMatrixOutputs_hi_291, decoder_decoded_andMatrixOutputs_lo_291}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_58_2_1 = &_decoder_decoded_andMatrixOutputs_T_291; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_5, decoder_decoded_andMatrixOutputs_andMatrixInput_29_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_94 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_30_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_11, decoder_decoded_andMatrixOutputs_andMatrixInput_27_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_11, decoder_decoded_andMatrixOutputs_andMatrixInput_25_11}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_180 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_270 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_180, decoder_decoded_andMatrixOutputs_lo_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_11, decoder_decoded_andMatrixOutputs_andMatrixInput_23_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_21, decoder_decoded_andMatrixOutputs_andMatrixInput_21_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_171 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_32, decoder_decoded_andMatrixOutputs_andMatrixInput_19_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_54, decoder_decoded_andMatrixOutputs_andMatrixInput_17_39}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_192 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_290 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_192, decoder_decoded_andMatrixOutputs_lo_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] decoder_decoded_andMatrixOutputs_lo_292 = {decoder_decoded_andMatrixOutputs_lo_hi_290, decoder_decoded_andMatrixOutputs_lo_lo_270}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_154, decoder_decoded_andMatrixOutputs_andMatrixInput_15_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_175, decoder_decoded_andMatrixOutputs_andMatrixInput_13_171}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_154 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_186, decoder_decoded_andMatrixOutputs_andMatrixInput_11_180}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_232, decoder_decoded_andMatrixOutputs_andMatrixInput_9_192}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_186 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_284 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_186, decoder_decoded_andMatrixOutputs_hi_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_284, decoder_decoded_andMatrixOutputs_andMatrixInput_7_270}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_292, decoder_decoded_andMatrixOutputs_andMatrixInput_5_290}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_175 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_292, decoder_decoded_andMatrixOutputs_andMatrixInput_3_292}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_292, decoder_decoded_andMatrixOutputs_andMatrixInput_1_292}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_232 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_292 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_232, decoder_decoded_andMatrixOutputs_hi_hi_lo_175}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_292 = {decoder_decoded_andMatrixOutputs_hi_hi_292, decoder_decoded_andMatrixOutputs_hi_lo_284}; // @[pla.scala:98:53] wire [30:0] _decoder_decoded_andMatrixOutputs_T_292 = {decoder_decoded_andMatrixOutputs_hi_292, decoder_decoded_andMatrixOutputs_lo_292}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_152_2_1 = &_decoder_decoded_andMatrixOutputs_T_292; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_55 = decoder_decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_23 = decoder_decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_212 = decoder_decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_312 = decoder_decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_313 = decoder_decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_33 = decoder_decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_22_13 = decoder_decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_200 = decoder_decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_12, decoder_decoded_andMatrixOutputs_andMatrixInput_26_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_95 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_27_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_12, decoder_decoded_andMatrixOutputs_andMatrixInput_24_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_17, decoder_decoded_andMatrixOutputs_andMatrixInput_22_12}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_181 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_271 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_181, decoder_decoded_andMatrixOutputs_lo_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_33, decoder_decoded_andMatrixOutputs_andMatrixInput_19_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_172 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_20_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_55, decoder_decoded_andMatrixOutputs_andMatrixInput_17_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_155, decoder_decoded_andMatrixOutputs_andMatrixInput_15_95}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_193 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_291 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_193, decoder_decoded_andMatrixOutputs_lo_hi_lo_172}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_293 = {decoder_decoded_andMatrixOutputs_lo_hi_291, decoder_decoded_andMatrixOutputs_lo_lo_271}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_181, decoder_decoded_andMatrixOutputs_andMatrixInput_12_176}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_155 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_172}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_193, decoder_decoded_andMatrixOutputs_andMatrixInput_10_187}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_271, decoder_decoded_andMatrixOutputs_andMatrixInput_8_233}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_187 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_285 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_187, decoder_decoded_andMatrixOutputs_hi_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_293, decoder_decoded_andMatrixOutputs_andMatrixInput_5_291}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_176 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_6_285}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_293, decoder_decoded_andMatrixOutputs_andMatrixInput_3_293}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_293, decoder_decoded_andMatrixOutputs_andMatrixInput_1_293}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_233 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_293 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_233, decoder_decoded_andMatrixOutputs_hi_hi_lo_176}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_293 = {decoder_decoded_andMatrixOutputs_hi_hi_293, decoder_decoded_andMatrixOutputs_hi_lo_285}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_293 = {decoder_decoded_andMatrixOutputs_hi_293, decoder_decoded_andMatrixOutputs_lo_293}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_161_2_1 = &_decoder_decoded_andMatrixOutputs_T_293; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_30_6, decoder_decoded_andMatrixOutputs_andMatrixInput_31_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_6, decoder_decoded_andMatrixOutputs_andMatrixInput_29_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_96 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_13, decoder_decoded_andMatrixOutputs_andMatrixInput_27_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_13, decoder_decoded_andMatrixOutputs_andMatrixInput_25_13}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_182 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_lo_272 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_182, decoder_decoded_andMatrixOutputs_lo_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_13, decoder_decoded_andMatrixOutputs_andMatrixInput_23_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_23, decoder_decoded_andMatrixOutputs_andMatrixInput_21_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_173 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_34, decoder_decoded_andMatrixOutputs_andMatrixInput_19_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_56, decoder_decoded_andMatrixOutputs_andMatrixInput_17_41}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_194 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_292 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_194, decoder_decoded_andMatrixOutputs_lo_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_lo_294 = {decoder_decoded_andMatrixOutputs_lo_hi_292, decoder_decoded_andMatrixOutputs_lo_lo_272}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_156, decoder_decoded_andMatrixOutputs_andMatrixInput_15_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_177, decoder_decoded_andMatrixOutputs_andMatrixInput_13_173}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_156 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_188, decoder_decoded_andMatrixOutputs_andMatrixInput_11_182}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_234, decoder_decoded_andMatrixOutputs_andMatrixInput_9_194}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_188 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_286 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_188, decoder_decoded_andMatrixOutputs_hi_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_286, decoder_decoded_andMatrixOutputs_andMatrixInput_7_272}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_294, decoder_decoded_andMatrixOutputs_andMatrixInput_5_292}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_177 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_294, decoder_decoded_andMatrixOutputs_andMatrixInput_3_294}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_294, decoder_decoded_andMatrixOutputs_andMatrixInput_1_294}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_234 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_294 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_234, decoder_decoded_andMatrixOutputs_hi_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_294 = {decoder_decoded_andMatrixOutputs_hi_hi_294, decoder_decoded_andMatrixOutputs_hi_lo_286}; // @[pla.scala:98:53] wire [31:0] _decoder_decoded_andMatrixOutputs_T_294 = {decoder_decoded_andMatrixOutputs_hi_294, decoder_decoded_andMatrixOutputs_lo_294}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_112_2_1 = &_decoder_decoded_andMatrixOutputs_T_294; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_97 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_97, decoder_decoded_andMatrixOutputs_andMatrixInput_16_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_174, decoder_decoded_andMatrixOutputs_andMatrixInput_14_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_273 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_183, decoder_decoded_andMatrixOutputs_lo_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_183, decoder_decoded_andMatrixOutputs_andMatrixInput_12_178}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_195, decoder_decoded_andMatrixOutputs_andMatrixInput_10_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_293 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_195, decoder_decoded_andMatrixOutputs_lo_hi_lo_174}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_295 = {decoder_decoded_andMatrixOutputs_lo_hi_293, decoder_decoded_andMatrixOutputs_lo_lo_273}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_273, decoder_decoded_andMatrixOutputs_andMatrixInput_8_235}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_293, decoder_decoded_andMatrixOutputs_andMatrixInput_6_287}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_287 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_189, decoder_decoded_andMatrixOutputs_hi_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_295, decoder_decoded_andMatrixOutputs_andMatrixInput_4_295}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_295, decoder_decoded_andMatrixOutputs_andMatrixInput_1_295}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_235 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_2_295}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_295 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_235, decoder_decoded_andMatrixOutputs_hi_hi_lo_178}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_295 = {decoder_decoded_andMatrixOutputs_hi_hi_295, decoder_decoded_andMatrixOutputs_hi_lo_287}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_295 = {decoder_decoded_andMatrixOutputs_hi_295, decoder_decoded_andMatrixOutputs_lo_295}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_82_2_1 = &_decoder_decoded_andMatrixOutputs_T_295; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_101 = decoder_decoded_andMatrixOutputs_82_2_1; // @[pla.scala:98:70, :114:36] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_98 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_58, decoder_decoded_andMatrixOutputs_andMatrixInput_17_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_158, decoder_decoded_andMatrixOutputs_andMatrixInput_15_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_274 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_184, decoder_decoded_andMatrixOutputs_lo_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_179, decoder_decoded_andMatrixOutputs_andMatrixInput_13_175}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_196, decoder_decoded_andMatrixOutputs_andMatrixInput_10_190}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_196 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_184}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_294 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_196, decoder_decoded_andMatrixOutputs_lo_hi_lo_175}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_296 = {decoder_decoded_andMatrixOutputs_lo_hi_294, decoder_decoded_andMatrixOutputs_lo_lo_274}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_158 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_274, decoder_decoded_andMatrixOutputs_andMatrixInput_8_236}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_294, decoder_decoded_andMatrixOutputs_andMatrixInput_6_288}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_288 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_190, decoder_decoded_andMatrixOutputs_hi_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_179 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_296, decoder_decoded_andMatrixOutputs_andMatrixInput_4_296}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_296, decoder_decoded_andMatrixOutputs_andMatrixInput_1_296}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_236 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_andMatrixInput_2_296}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_296 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_236, decoder_decoded_andMatrixOutputs_hi_hi_lo_179}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_296 = {decoder_decoded_andMatrixOutputs_hi_hi_296, decoder_decoded_andMatrixOutputs_hi_lo_288}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_296 = {decoder_decoded_andMatrixOutputs_hi_296, decoder_decoded_andMatrixOutputs_lo_296}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_31_2_1 = &_decoder_decoded_andMatrixOutputs_T_296; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_99 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_35, decoder_decoded_andMatrixOutputs_andMatrixInput_19_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_99, decoder_decoded_andMatrixOutputs_andMatrixInput_16_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_185 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_17_43}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_275 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_185, decoder_decoded_andMatrixOutputs_lo_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_176, decoder_decoded_andMatrixOutputs_andMatrixInput_14_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_191, decoder_decoded_andMatrixOutputs_andMatrixInput_11_185}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_197 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_12_180}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_295 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_197, decoder_decoded_andMatrixOutputs_lo_hi_lo_176}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_297 = {decoder_decoded_andMatrixOutputs_lo_hi_295, decoder_decoded_andMatrixOutputs_lo_lo_275}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_159 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_237, decoder_decoded_andMatrixOutputs_andMatrixInput_9_197}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_295, decoder_decoded_andMatrixOutputs_andMatrixInput_6_289}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_191 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_275}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_289 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_191, decoder_decoded_andMatrixOutputs_hi_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_297, decoder_decoded_andMatrixOutputs_andMatrixInput_4_297}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_297, decoder_decoded_andMatrixOutputs_andMatrixInput_1_297}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_237 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_andMatrixInput_2_297}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_297 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_237, decoder_decoded_andMatrixOutputs_hi_hi_lo_180}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_297 = {decoder_decoded_andMatrixOutputs_hi_hi_297, decoder_decoded_andMatrixOutputs_hi_lo_289}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_297 = {decoder_decoded_andMatrixOutputs_hi_297, decoder_decoded_andMatrixOutputs_lo_297}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_13_2_1 = &_decoder_decoded_andMatrixOutputs_T_297; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_100 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_24, decoder_decoded_andMatrixOutputs_andMatrixInput_21_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_44, decoder_decoded_andMatrixOutputs_andMatrixInput_18_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_186 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_19_33}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_276 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_186, decoder_decoded_andMatrixOutputs_lo_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_160, decoder_decoded_andMatrixOutputs_andMatrixInput_15_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_177 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_16_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_186, decoder_decoded_andMatrixOutputs_andMatrixInput_12_181}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_198 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_177}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_296 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_198, decoder_decoded_andMatrixOutputs_lo_hi_lo_177}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_298 = {decoder_decoded_andMatrixOutputs_lo_hi_296, decoder_decoded_andMatrixOutputs_lo_lo_276}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_160 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_198, decoder_decoded_andMatrixOutputs_andMatrixInput_10_192}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_290, decoder_decoded_andMatrixOutputs_andMatrixInput_7_276}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_192 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_8_238}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_290 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_192, decoder_decoded_andMatrixOutputs_hi_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_298, decoder_decoded_andMatrixOutputs_andMatrixInput_4_298}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_181 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_296}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_298, decoder_decoded_andMatrixOutputs_andMatrixInput_1_298}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_238 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_2_298}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_298 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_238, decoder_decoded_andMatrixOutputs_hi_hi_lo_181}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_298 = {decoder_decoded_andMatrixOutputs_hi_hi_298, decoder_decoded_andMatrixOutputs_hi_lo_290}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_298 = {decoder_decoded_andMatrixOutputs_hi_298, decoder_decoded_andMatrixOutputs_lo_298}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_110_2_1 = &_decoder_decoded_andMatrixOutputs_T_298; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_187, decoder_decoded_andMatrixOutputs_andMatrixInput_12_182}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_277 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_187, decoder_decoded_andMatrixOutputs_andMatrixInput_13_178}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_199, decoder_decoded_andMatrixOutputs_andMatrixInput_10_193}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_277, decoder_decoded_andMatrixOutputs_andMatrixInput_8_239}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_297 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_199, decoder_decoded_andMatrixOutputs_lo_hi_lo_178}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_299 = {decoder_decoded_andMatrixOutputs_lo_hi_297, decoder_decoded_andMatrixOutputs_lo_lo_277}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_299, decoder_decoded_andMatrixOutputs_andMatrixInput_5_297}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_291 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_6_291}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_299, decoder_decoded_andMatrixOutputs_andMatrixInput_3_299}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_299, decoder_decoded_andMatrixOutputs_andMatrixInput_1_299}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_299 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_239, decoder_decoded_andMatrixOutputs_hi_hi_lo_182}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_299 = {decoder_decoded_andMatrixOutputs_hi_hi_299, decoder_decoded_andMatrixOutputs_hi_lo_291}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_299 = {decoder_decoded_andMatrixOutputs_hi_299, decoder_decoded_andMatrixOutputs_lo_299}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_64_2_1 = &_decoder_decoded_andMatrixOutputs_T_299; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_183 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_184 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_185 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_186 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_192 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_193 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_189 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_190 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_196 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_191 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_192 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_189 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_190 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_195 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_192 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_193 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_170 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_171 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_34 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_204 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_205 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_206 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_53 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_54 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_41 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_56 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_239 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_236 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_237 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_238 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_239 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_39 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_25_14 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_29_7 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_247 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_248 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_249 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_250 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_60 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_61 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_62 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_63 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_50 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_51 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_52 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_53 = decoder_decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_188, decoder_decoded_andMatrixOutputs_andMatrixInput_12_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_278 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_188, decoder_decoded_andMatrixOutputs_andMatrixInput_13_179}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_179 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_200, decoder_decoded_andMatrixOutputs_andMatrixInput_10_194}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_278, decoder_decoded_andMatrixOutputs_andMatrixInput_8_240}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_298 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_200, decoder_decoded_andMatrixOutputs_lo_hi_lo_179}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_300 = {decoder_decoded_andMatrixOutputs_lo_hi_298, decoder_decoded_andMatrixOutputs_lo_lo_278}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_300, decoder_decoded_andMatrixOutputs_andMatrixInput_5_298}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_292 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_6_292}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_300, decoder_decoded_andMatrixOutputs_andMatrixInput_3_300}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_300, decoder_decoded_andMatrixOutputs_andMatrixInput_1_300}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_300 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_240, decoder_decoded_andMatrixOutputs_hi_hi_lo_183}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_300 = {decoder_decoded_andMatrixOutputs_hi_hi_300, decoder_decoded_andMatrixOutputs_hi_lo_292}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_300 = {decoder_decoded_andMatrixOutputs_hi_300, decoder_decoded_andMatrixOutputs_lo_300}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_124_2_1 = &_decoder_decoded_andMatrixOutputs_T_300; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_189, decoder_decoded_andMatrixOutputs_andMatrixInput_12_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_279 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_189, decoder_decoded_andMatrixOutputs_andMatrixInput_13_180}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_201, decoder_decoded_andMatrixOutputs_andMatrixInput_10_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_279, decoder_decoded_andMatrixOutputs_andMatrixInput_8_241}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_299 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_201, decoder_decoded_andMatrixOutputs_lo_hi_lo_180}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_301 = {decoder_decoded_andMatrixOutputs_lo_hi_299, decoder_decoded_andMatrixOutputs_lo_lo_279}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_301, decoder_decoded_andMatrixOutputs_andMatrixInput_5_299}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_293 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_6_293}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_301, decoder_decoded_andMatrixOutputs_andMatrixInput_3_301}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_301, decoder_decoded_andMatrixOutputs_andMatrixInput_1_301}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_301 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_241, decoder_decoded_andMatrixOutputs_hi_hi_lo_184}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_301 = {decoder_decoded_andMatrixOutputs_hi_hi_301, decoder_decoded_andMatrixOutputs_hi_lo_293}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_301 = {decoder_decoded_andMatrixOutputs_hi_301, decoder_decoded_andMatrixOutputs_lo_301}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_49_2_1 = &_decoder_decoded_andMatrixOutputs_T_301; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_190, decoder_decoded_andMatrixOutputs_andMatrixInput_12_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_280 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_190, decoder_decoded_andMatrixOutputs_andMatrixInput_13_181}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_181 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_202, decoder_decoded_andMatrixOutputs_andMatrixInput_10_196}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_280, decoder_decoded_andMatrixOutputs_andMatrixInput_8_242}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_300 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_202, decoder_decoded_andMatrixOutputs_lo_hi_lo_181}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_302 = {decoder_decoded_andMatrixOutputs_lo_hi_300, decoder_decoded_andMatrixOutputs_lo_lo_280}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_302, decoder_decoded_andMatrixOutputs_andMatrixInput_5_300}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_294 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_6_294}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_185 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_302, decoder_decoded_andMatrixOutputs_andMatrixInput_3_302}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_302, decoder_decoded_andMatrixOutputs_andMatrixInput_1_302}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_302 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_242, decoder_decoded_andMatrixOutputs_hi_hi_lo_185}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_302 = {decoder_decoded_andMatrixOutputs_hi_hi_302, decoder_decoded_andMatrixOutputs_hi_lo_294}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_302 = {decoder_decoded_andMatrixOutputs_hi_302, decoder_decoded_andMatrixOutputs_lo_302}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_6_2_1 = &_decoder_decoded_andMatrixOutputs_T_302; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_191, decoder_decoded_andMatrixOutputs_andMatrixInput_12_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_281 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_191, decoder_decoded_andMatrixOutputs_andMatrixInput_13_182}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_203, decoder_decoded_andMatrixOutputs_andMatrixInput_10_197}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_281, decoder_decoded_andMatrixOutputs_andMatrixInput_8_243}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_301 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_203, decoder_decoded_andMatrixOutputs_lo_hi_lo_182}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_303 = {decoder_decoded_andMatrixOutputs_lo_hi_301, decoder_decoded_andMatrixOutputs_lo_lo_281}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_303, decoder_decoded_andMatrixOutputs_andMatrixInput_5_301}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_295 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_197, decoder_decoded_andMatrixOutputs_andMatrixInput_6_295}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_303, decoder_decoded_andMatrixOutputs_andMatrixInput_3_303}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_303, decoder_decoded_andMatrixOutputs_andMatrixInput_1_303}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_303 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_243, decoder_decoded_andMatrixOutputs_hi_hi_lo_186}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_303 = {decoder_decoded_andMatrixOutputs_hi_hi_303, decoder_decoded_andMatrixOutputs_hi_lo_295}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_303 = {decoder_decoded_andMatrixOutputs_hi_303, decoder_decoded_andMatrixOutputs_lo_303}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_134_2_1 = &_decoder_decoded_andMatrixOutputs_T_303; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_192, decoder_decoded_andMatrixOutputs_andMatrixInput_12_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_282 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_192, decoder_decoded_andMatrixOutputs_andMatrixInput_13_183}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_204, decoder_decoded_andMatrixOutputs_andMatrixInput_10_198}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_282, decoder_decoded_andMatrixOutputs_andMatrixInput_8_244}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_302 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_204, decoder_decoded_andMatrixOutputs_lo_hi_lo_183}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_304 = {decoder_decoded_andMatrixOutputs_lo_hi_302, decoder_decoded_andMatrixOutputs_lo_lo_282}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_304, decoder_decoded_andMatrixOutputs_andMatrixInput_5_302}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_296 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_6_296}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_304, decoder_decoded_andMatrixOutputs_andMatrixInput_3_304}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_304, decoder_decoded_andMatrixOutputs_andMatrixInput_1_304}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_304 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_244, decoder_decoded_andMatrixOutputs_hi_hi_lo_187}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_304 = {decoder_decoded_andMatrixOutputs_hi_hi_304, decoder_decoded_andMatrixOutputs_hi_lo_296}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_304 = {decoder_decoded_andMatrixOutputs_hi_304, decoder_decoded_andMatrixOutputs_lo_304}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_153_2_1 = &_decoder_decoded_andMatrixOutputs_T_304; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_193, decoder_decoded_andMatrixOutputs_andMatrixInput_12_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_283 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_193, decoder_decoded_andMatrixOutputs_andMatrixInput_13_184}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_205, decoder_decoded_andMatrixOutputs_andMatrixInput_10_199}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_283, decoder_decoded_andMatrixOutputs_andMatrixInput_8_245}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_303 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_205, decoder_decoded_andMatrixOutputs_lo_hi_lo_184}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_305 = {decoder_decoded_andMatrixOutputs_lo_hi_303, decoder_decoded_andMatrixOutputs_lo_lo_283}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_305, decoder_decoded_andMatrixOutputs_andMatrixInput_5_303}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_297 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_199, decoder_decoded_andMatrixOutputs_andMatrixInput_6_297}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_305, decoder_decoded_andMatrixOutputs_andMatrixInput_3_305}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_245 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_305, decoder_decoded_andMatrixOutputs_andMatrixInput_1_305}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_305 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_245, decoder_decoded_andMatrixOutputs_hi_hi_lo_188}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_305 = {decoder_decoded_andMatrixOutputs_hi_hi_305, decoder_decoded_andMatrixOutputs_hi_lo_297}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_305 = {decoder_decoded_andMatrixOutputs_hi_305, decoder_decoded_andMatrixOutputs_lo_305}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_107_2_1 = &_decoder_decoded_andMatrixOutputs_T_305; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_189, decoder_decoded_andMatrixOutputs_andMatrixInput_13_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_284 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_194, decoder_decoded_andMatrixOutputs_andMatrixInput_14_161}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_185 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_200, decoder_decoded_andMatrixOutputs_andMatrixInput_11_194}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_246, decoder_decoded_andMatrixOutputs_andMatrixInput_9_206}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_304 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_206, decoder_decoded_andMatrixOutputs_lo_hi_lo_185}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_306 = {decoder_decoded_andMatrixOutputs_lo_hi_304, decoder_decoded_andMatrixOutputs_lo_lo_284}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_161 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_298, decoder_decoded_andMatrixOutputs_andMatrixInput_7_284}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_306, decoder_decoded_andMatrixOutputs_andMatrixInput_5_304}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_298 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_200, decoder_decoded_andMatrixOutputs_hi_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_306, decoder_decoded_andMatrixOutputs_andMatrixInput_3_306}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_306, decoder_decoded_andMatrixOutputs_andMatrixInput_1_306}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_306 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_246, decoder_decoded_andMatrixOutputs_hi_hi_lo_189}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_306 = {decoder_decoded_andMatrixOutputs_hi_hi_306, decoder_decoded_andMatrixOutputs_hi_lo_298}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_306 = {decoder_decoded_andMatrixOutputs_hi_306, decoder_decoded_andMatrixOutputs_lo_306}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_187_2_1 = &_decoder_decoded_andMatrixOutputs_T_306; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_190, decoder_decoded_andMatrixOutputs_andMatrixInput_13_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_285 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_195, decoder_decoded_andMatrixOutputs_andMatrixInput_14_162}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_201, decoder_decoded_andMatrixOutputs_andMatrixInput_11_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_247, decoder_decoded_andMatrixOutputs_andMatrixInput_9_207}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_305 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_207, decoder_decoded_andMatrixOutputs_lo_hi_lo_186}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_307 = {decoder_decoded_andMatrixOutputs_lo_hi_305, decoder_decoded_andMatrixOutputs_lo_lo_285}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_162 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_299, decoder_decoded_andMatrixOutputs_andMatrixInput_7_285}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_307, decoder_decoded_andMatrixOutputs_andMatrixInput_5_305}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_299 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_201, decoder_decoded_andMatrixOutputs_hi_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_307, decoder_decoded_andMatrixOutputs_andMatrixInput_3_307}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_307, decoder_decoded_andMatrixOutputs_andMatrixInput_1_307}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_307 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_247, decoder_decoded_andMatrixOutputs_hi_hi_lo_190}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_307 = {decoder_decoded_andMatrixOutputs_hi_hi_307, decoder_decoded_andMatrixOutputs_hi_lo_299}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_307 = {decoder_decoded_andMatrixOutputs_hi_307, decoder_decoded_andMatrixOutputs_lo_307}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_46_2_1 = &_decoder_decoded_andMatrixOutputs_T_307; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_208, decoder_decoded_andMatrixOutputs_andMatrixInput_10_202}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_286 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_196, decoder_decoded_andMatrixOutputs_andMatrixInput_11_196}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_300, decoder_decoded_andMatrixOutputs_andMatrixInput_7_286}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_306 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_208, decoder_decoded_andMatrixOutputs_andMatrixInput_8_248}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_308 = {decoder_decoded_andMatrixOutputs_lo_hi_306, decoder_decoded_andMatrixOutputs_lo_lo_286}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_308, decoder_decoded_andMatrixOutputs_andMatrixInput_4_308}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_300 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_202, decoder_decoded_andMatrixOutputs_andMatrixInput_5_306}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_308, decoder_decoded_andMatrixOutputs_andMatrixInput_1_308}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_308 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_248, decoder_decoded_andMatrixOutputs_andMatrixInput_2_308}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_308 = {decoder_decoded_andMatrixOutputs_hi_hi_308, decoder_decoded_andMatrixOutputs_hi_lo_300}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_308 = {decoder_decoded_andMatrixOutputs_hi_308, decoder_decoded_andMatrixOutputs_lo_308}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_78_2_1 = &_decoder_decoded_andMatrixOutputs_T_308; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_191, decoder_decoded_andMatrixOutputs_andMatrixInput_13_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_287 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_197, decoder_decoded_andMatrixOutputs_andMatrixInput_14_163}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_203, decoder_decoded_andMatrixOutputs_andMatrixInput_11_197}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_249, decoder_decoded_andMatrixOutputs_andMatrixInput_9_209}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_307 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_209, decoder_decoded_andMatrixOutputs_lo_hi_lo_187}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_309 = {decoder_decoded_andMatrixOutputs_lo_hi_307, decoder_decoded_andMatrixOutputs_lo_lo_287}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_163 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_301, decoder_decoded_andMatrixOutputs_andMatrixInput_7_287}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_309, decoder_decoded_andMatrixOutputs_andMatrixInput_5_307}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_301 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_203, decoder_decoded_andMatrixOutputs_hi_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_309, decoder_decoded_andMatrixOutputs_andMatrixInput_3_309}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_309, decoder_decoded_andMatrixOutputs_andMatrixInput_1_309}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_309 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_249, decoder_decoded_andMatrixOutputs_hi_hi_lo_191}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_309 = {decoder_decoded_andMatrixOutputs_hi_hi_309, decoder_decoded_andMatrixOutputs_hi_lo_301}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_309 = {decoder_decoded_andMatrixOutputs_hi_309, decoder_decoded_andMatrixOutputs_lo_309}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_159_2_1 = &_decoder_decoded_andMatrixOutputs_T_309; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_192, decoder_decoded_andMatrixOutputs_andMatrixInput_13_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_288 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_198, decoder_decoded_andMatrixOutputs_andMatrixInput_14_164}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_204, decoder_decoded_andMatrixOutputs_andMatrixInput_11_198}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_250, decoder_decoded_andMatrixOutputs_andMatrixInput_9_210}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_308 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_210, decoder_decoded_andMatrixOutputs_lo_hi_lo_188}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_310 = {decoder_decoded_andMatrixOutputs_lo_hi_308, decoder_decoded_andMatrixOutputs_lo_lo_288}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_164 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_302, decoder_decoded_andMatrixOutputs_andMatrixInput_7_288}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_310, decoder_decoded_andMatrixOutputs_andMatrixInput_5_308}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_302 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_204, decoder_decoded_andMatrixOutputs_hi_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_310, decoder_decoded_andMatrixOutputs_andMatrixInput_3_310}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_310, decoder_decoded_andMatrixOutputs_andMatrixInput_1_310}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_310 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_250, decoder_decoded_andMatrixOutputs_hi_hi_lo_192}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_310 = {decoder_decoded_andMatrixOutputs_hi_hi_310, decoder_decoded_andMatrixOutputs_hi_lo_302}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_310 = {decoder_decoded_andMatrixOutputs_hi_310, decoder_decoded_andMatrixOutputs_lo_310}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_34_2_1 = &_decoder_decoded_andMatrixOutputs_T_310; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_193, decoder_decoded_andMatrixOutputs_andMatrixInput_13_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_289 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_199, decoder_decoded_andMatrixOutputs_andMatrixInput_14_165}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_205, decoder_decoded_andMatrixOutputs_andMatrixInput_11_199}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_251, decoder_decoded_andMatrixOutputs_andMatrixInput_9_211}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_309 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_211, decoder_decoded_andMatrixOutputs_lo_hi_lo_189}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_311 = {decoder_decoded_andMatrixOutputs_lo_hi_309, decoder_decoded_andMatrixOutputs_lo_lo_289}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_165 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_303, decoder_decoded_andMatrixOutputs_andMatrixInput_7_289}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_311, decoder_decoded_andMatrixOutputs_andMatrixInput_5_309}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_303 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_205, decoder_decoded_andMatrixOutputs_hi_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_311, decoder_decoded_andMatrixOutputs_andMatrixInput_3_311}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_251 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_311, decoder_decoded_andMatrixOutputs_andMatrixInput_1_311}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_311 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_251, decoder_decoded_andMatrixOutputs_hi_hi_lo_193}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_311 = {decoder_decoded_andMatrixOutputs_hi_hi_311, decoder_decoded_andMatrixOutputs_hi_lo_303}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_311 = {decoder_decoded_andMatrixOutputs_hi_311, decoder_decoded_andMatrixOutputs_lo_311}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_85_2_1 = &_decoder_decoded_andMatrixOutputs_T_311; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_194, decoder_decoded_andMatrixOutputs_andMatrixInput_13_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_290 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_200, decoder_decoded_andMatrixOutputs_andMatrixInput_14_166}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_206, decoder_decoded_andMatrixOutputs_andMatrixInput_11_200}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_252, decoder_decoded_andMatrixOutputs_andMatrixInput_9_212}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_310 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_212, decoder_decoded_andMatrixOutputs_lo_hi_lo_190}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_312 = {decoder_decoded_andMatrixOutputs_lo_hi_310, decoder_decoded_andMatrixOutputs_lo_lo_290}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_166 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_304, decoder_decoded_andMatrixOutputs_andMatrixInput_7_290}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_312, decoder_decoded_andMatrixOutputs_andMatrixInput_5_310}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_304 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_206, decoder_decoded_andMatrixOutputs_hi_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_312, decoder_decoded_andMatrixOutputs_andMatrixInput_3_312}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_312, decoder_decoded_andMatrixOutputs_andMatrixInput_1_312}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_312 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_252, decoder_decoded_andMatrixOutputs_hi_hi_lo_194}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_312 = {decoder_decoded_andMatrixOutputs_hi_hi_312, decoder_decoded_andMatrixOutputs_hi_lo_304}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_312 = {decoder_decoded_andMatrixOutputs_hi_312, decoder_decoded_andMatrixOutputs_lo_312}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_10_2_1 = &_decoder_decoded_andMatrixOutputs_T_312; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_195, decoder_decoded_andMatrixOutputs_andMatrixInput_13_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_291 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_201, decoder_decoded_andMatrixOutputs_andMatrixInput_14_167}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_207, decoder_decoded_andMatrixOutputs_andMatrixInput_11_201}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_253, decoder_decoded_andMatrixOutputs_andMatrixInput_9_213}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_311 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_213, decoder_decoded_andMatrixOutputs_lo_hi_lo_191}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_313 = {decoder_decoded_andMatrixOutputs_lo_hi_311, decoder_decoded_andMatrixOutputs_lo_lo_291}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_167 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_305, decoder_decoded_andMatrixOutputs_andMatrixInput_7_291}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_313, decoder_decoded_andMatrixOutputs_andMatrixInput_5_311}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_305 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_207, decoder_decoded_andMatrixOutputs_hi_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_313, decoder_decoded_andMatrixOutputs_andMatrixInput_3_313}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_253 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_313, decoder_decoded_andMatrixOutputs_andMatrixInput_1_313}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_313 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_253, decoder_decoded_andMatrixOutputs_hi_hi_lo_195}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_313 = {decoder_decoded_andMatrixOutputs_hi_hi_313, decoder_decoded_andMatrixOutputs_hi_lo_305}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_313 = {decoder_decoded_andMatrixOutputs_hi_313, decoder_decoded_andMatrixOutputs_lo_313}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_92_2_1 = &_decoder_decoded_andMatrixOutputs_T_313; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_196, decoder_decoded_andMatrixOutputs_andMatrixInput_13_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_292 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_202, decoder_decoded_andMatrixOutputs_andMatrixInput_14_168}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_208, decoder_decoded_andMatrixOutputs_andMatrixInput_11_202}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_254, decoder_decoded_andMatrixOutputs_andMatrixInput_9_214}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_312 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_214, decoder_decoded_andMatrixOutputs_lo_hi_lo_192}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_314 = {decoder_decoded_andMatrixOutputs_lo_hi_312, decoder_decoded_andMatrixOutputs_lo_lo_292}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_168 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_306, decoder_decoded_andMatrixOutputs_andMatrixInput_7_292}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_314, decoder_decoded_andMatrixOutputs_andMatrixInput_5_312}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_306 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_208, decoder_decoded_andMatrixOutputs_hi_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_314, decoder_decoded_andMatrixOutputs_andMatrixInput_3_314}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_254 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_314, decoder_decoded_andMatrixOutputs_andMatrixInput_1_314}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_314 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_254, decoder_decoded_andMatrixOutputs_hi_hi_lo_196}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_314 = {decoder_decoded_andMatrixOutputs_hi_hi_314, decoder_decoded_andMatrixOutputs_hi_lo_306}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_314 = {decoder_decoded_andMatrixOutputs_hi_314, decoder_decoded_andMatrixOutputs_lo_314}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_180_2_1 = &_decoder_decoded_andMatrixOutputs_T_314; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_101 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_169, decoder_decoded_andMatrixOutputs_andMatrixInput_15_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_197, decoder_decoded_andMatrixOutputs_andMatrixInput_13_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_293 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_203, decoder_decoded_andMatrixOutputs_lo_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_209, decoder_decoded_andMatrixOutputs_andMatrixInput_11_203}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_255, decoder_decoded_andMatrixOutputs_andMatrixInput_9_215}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_313 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_215, decoder_decoded_andMatrixOutputs_lo_hi_lo_193}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_315 = {decoder_decoded_andMatrixOutputs_lo_hi_313, decoder_decoded_andMatrixOutputs_lo_lo_293}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_169 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_307, decoder_decoded_andMatrixOutputs_andMatrixInput_7_293}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_315, decoder_decoded_andMatrixOutputs_andMatrixInput_5_313}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_307 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_209, decoder_decoded_andMatrixOutputs_hi_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_315, decoder_decoded_andMatrixOutputs_andMatrixInput_3_315}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_315, decoder_decoded_andMatrixOutputs_andMatrixInput_1_315}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_315 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_255, decoder_decoded_andMatrixOutputs_hi_hi_lo_197}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_315 = {decoder_decoded_andMatrixOutputs_hi_hi_315, decoder_decoded_andMatrixOutputs_hi_lo_307}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_315 = {decoder_decoded_andMatrixOutputs_hi_315, decoder_decoded_andMatrixOutputs_lo_315}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_44_2_1 = &_decoder_decoded_andMatrixOutputs_T_315; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_102 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_170, decoder_decoded_andMatrixOutputs_andMatrixInput_15_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_198, decoder_decoded_andMatrixOutputs_andMatrixInput_13_194}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_294 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_204, decoder_decoded_andMatrixOutputs_lo_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_210, decoder_decoded_andMatrixOutputs_andMatrixInput_11_204}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_256, decoder_decoded_andMatrixOutputs_andMatrixInput_9_216}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_314 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_216, decoder_decoded_andMatrixOutputs_lo_hi_lo_194}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_316 = {decoder_decoded_andMatrixOutputs_lo_hi_314, decoder_decoded_andMatrixOutputs_lo_lo_294}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_170 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_308, decoder_decoded_andMatrixOutputs_andMatrixInput_7_294}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_316, decoder_decoded_andMatrixOutputs_andMatrixInput_5_314}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_308 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_210, decoder_decoded_andMatrixOutputs_hi_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_316, decoder_decoded_andMatrixOutputs_andMatrixInput_3_316}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_316, decoder_decoded_andMatrixOutputs_andMatrixInput_1_316}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_316 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_256, decoder_decoded_andMatrixOutputs_hi_hi_lo_198}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_316 = {decoder_decoded_andMatrixOutputs_hi_hi_316, decoder_decoded_andMatrixOutputs_hi_lo_308}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_316 = {decoder_decoded_andMatrixOutputs_hi_316, decoder_decoded_andMatrixOutputs_lo_316}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_135_2_1 = &_decoder_decoded_andMatrixOutputs_T_316; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_103 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_103, decoder_decoded_andMatrixOutputs_andMatrixInput_16_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_195, decoder_decoded_andMatrixOutputs_andMatrixInput_14_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_295 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_205, decoder_decoded_andMatrixOutputs_lo_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_205, decoder_decoded_andMatrixOutputs_andMatrixInput_12_199}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_217, decoder_decoded_andMatrixOutputs_andMatrixInput_10_211}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_315 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_217, decoder_decoded_andMatrixOutputs_lo_hi_lo_195}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_317 = {decoder_decoded_andMatrixOutputs_lo_hi_315, decoder_decoded_andMatrixOutputs_lo_lo_295}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_171 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_295, decoder_decoded_andMatrixOutputs_andMatrixInput_8_257}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_315, decoder_decoded_andMatrixOutputs_andMatrixInput_6_309}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_309 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_211, decoder_decoded_andMatrixOutputs_hi_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_317, decoder_decoded_andMatrixOutputs_andMatrixInput_4_317}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_317, decoder_decoded_andMatrixOutputs_andMatrixInput_1_317}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_257 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_2_317}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_317 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_257, decoder_decoded_andMatrixOutputs_hi_hi_lo_199}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_317 = {decoder_decoded_andMatrixOutputs_hi_hi_317, decoder_decoded_andMatrixOutputs_hi_lo_309}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_317 = {decoder_decoded_andMatrixOutputs_hi_317, decoder_decoded_andMatrixOutputs_lo_317}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_3_2_1 = &_decoder_decoded_andMatrixOutputs_T_317; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_104 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_25, decoder_decoded_andMatrixOutputs_andMatrixInput_21_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_45, decoder_decoded_andMatrixOutputs_andMatrixInput_18_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_206 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_andMatrixInput_19_34}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_296 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_206, decoder_decoded_andMatrixOutputs_lo_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_172, decoder_decoded_andMatrixOutputs_andMatrixInput_15_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_196 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_16_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_206, decoder_decoded_andMatrixOutputs_andMatrixInput_12_200}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_218 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_196}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_316 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_218, decoder_decoded_andMatrixOutputs_lo_hi_lo_196}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_318 = {decoder_decoded_andMatrixOutputs_lo_hi_316, decoder_decoded_andMatrixOutputs_lo_lo_296}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_172 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_218, decoder_decoded_andMatrixOutputs_andMatrixInput_10_212}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_310, decoder_decoded_andMatrixOutputs_andMatrixInput_7_296}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_212 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_258}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_310 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_212, decoder_decoded_andMatrixOutputs_hi_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_318, decoder_decoded_andMatrixOutputs_andMatrixInput_4_318}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_200 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_316}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_318, decoder_decoded_andMatrixOutputs_andMatrixInput_1_318}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_258 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_2_318}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_318 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_258, decoder_decoded_andMatrixOutputs_hi_hi_lo_200}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_318 = {decoder_decoded_andMatrixOutputs_hi_hi_318, decoder_decoded_andMatrixOutputs_hi_lo_310}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_318 = {decoder_decoded_andMatrixOutputs_hi_318, decoder_decoded_andMatrixOutputs_lo_318}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_188_2_1 = &_decoder_decoded_andMatrixOutputs_T_318; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_173 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_174 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_209 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_199 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_176 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_201 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_202 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_179 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_204 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_181 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_182 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_207 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_184 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_185 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_113 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_64 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_65 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_66 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_67 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_68 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_69 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_70 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_71 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_219 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_220 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_197 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_198 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_199 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_125 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_73 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_74 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_52 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_129 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_130 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_131 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_39 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_40 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_37 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_42 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_235 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_212 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_213 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_214 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_215 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_27 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_26_14 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_30_7 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_223 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_224 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_249 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_250 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_227 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_228 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_229 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_230 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_231 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_46 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_47 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_48 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_49 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_46 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_47 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_48 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_49 = decoder_decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_105 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_173, decoder_decoded_andMatrixOutputs_andMatrixInput_15_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_201, decoder_decoded_andMatrixOutputs_andMatrixInput_13_197}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_297 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_207, decoder_decoded_andMatrixOutputs_lo_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_213, decoder_decoded_andMatrixOutputs_andMatrixInput_11_207}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_259, decoder_decoded_andMatrixOutputs_andMatrixInput_9_219}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_317 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_219, decoder_decoded_andMatrixOutputs_lo_hi_lo_197}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_319 = {decoder_decoded_andMatrixOutputs_lo_hi_317, decoder_decoded_andMatrixOutputs_lo_lo_297}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_173 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_311, decoder_decoded_andMatrixOutputs_andMatrixInput_7_297}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_319, decoder_decoded_andMatrixOutputs_andMatrixInput_5_317}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_311 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_213, decoder_decoded_andMatrixOutputs_hi_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_319, decoder_decoded_andMatrixOutputs_andMatrixInput_3_319}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_259 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_319, decoder_decoded_andMatrixOutputs_andMatrixInput_1_319}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_319 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_259, decoder_decoded_andMatrixOutputs_hi_hi_lo_201}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_319 = {decoder_decoded_andMatrixOutputs_hi_hi_319, decoder_decoded_andMatrixOutputs_hi_lo_311}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_319 = {decoder_decoded_andMatrixOutputs_hi_319, decoder_decoded_andMatrixOutputs_lo_319}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_4_2_1 = &_decoder_decoded_andMatrixOutputs_T_319; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_106 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_174, decoder_decoded_andMatrixOutputs_andMatrixInput_15_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_202, decoder_decoded_andMatrixOutputs_andMatrixInput_13_198}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_298 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_208, decoder_decoded_andMatrixOutputs_lo_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_214, decoder_decoded_andMatrixOutputs_andMatrixInput_11_208}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_260, decoder_decoded_andMatrixOutputs_andMatrixInput_9_220}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_318 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_220, decoder_decoded_andMatrixOutputs_lo_hi_lo_198}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_320 = {decoder_decoded_andMatrixOutputs_lo_hi_318, decoder_decoded_andMatrixOutputs_lo_lo_298}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_174 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_312, decoder_decoded_andMatrixOutputs_andMatrixInput_7_298}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_320, decoder_decoded_andMatrixOutputs_andMatrixInput_5_318}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_312 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_214, decoder_decoded_andMatrixOutputs_hi_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_320, decoder_decoded_andMatrixOutputs_andMatrixInput_3_320}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_320, decoder_decoded_andMatrixOutputs_andMatrixInput_1_320}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_320 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_260, decoder_decoded_andMatrixOutputs_hi_hi_lo_202}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_320 = {decoder_decoded_andMatrixOutputs_hi_hi_320, decoder_decoded_andMatrixOutputs_hi_lo_312}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_320 = {decoder_decoded_andMatrixOutputs_hi_320, decoder_decoded_andMatrixOutputs_lo_320}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_25_2_1 = &_decoder_decoded_andMatrixOutputs_T_320; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_221, decoder_decoded_andMatrixOutputs_andMatrixInput_10_215}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_299 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_209, decoder_decoded_andMatrixOutputs_andMatrixInput_11_209}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_313, decoder_decoded_andMatrixOutputs_andMatrixInput_7_299}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_319 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_221, decoder_decoded_andMatrixOutputs_andMatrixInput_8_261}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_321 = {decoder_decoded_andMatrixOutputs_lo_hi_319, decoder_decoded_andMatrixOutputs_lo_lo_299}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_321, decoder_decoded_andMatrixOutputs_andMatrixInput_4_321}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_313 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_5_319}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_321, decoder_decoded_andMatrixOutputs_andMatrixInput_1_321}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_321 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_261, decoder_decoded_andMatrixOutputs_andMatrixInput_2_321}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_321 = {decoder_decoded_andMatrixOutputs_hi_hi_321, decoder_decoded_andMatrixOutputs_hi_lo_313}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_321 = {decoder_decoded_andMatrixOutputs_hi_321, decoder_decoded_andMatrixOutputs_lo_321}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_57_2_1 = &_decoder_decoded_andMatrixOutputs_T_321; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_203, decoder_decoded_andMatrixOutputs_andMatrixInput_13_199}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_300 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_210, decoder_decoded_andMatrixOutputs_andMatrixInput_14_175}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_216, decoder_decoded_andMatrixOutputs_andMatrixInput_11_210}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_262, decoder_decoded_andMatrixOutputs_andMatrixInput_9_222}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_320 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_222, decoder_decoded_andMatrixOutputs_lo_hi_lo_199}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_322 = {decoder_decoded_andMatrixOutputs_lo_hi_320, decoder_decoded_andMatrixOutputs_lo_lo_300}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_175 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_314, decoder_decoded_andMatrixOutputs_andMatrixInput_7_300}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_322, decoder_decoded_andMatrixOutputs_andMatrixInput_5_320}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_314 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_216, decoder_decoded_andMatrixOutputs_hi_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_322, decoder_decoded_andMatrixOutputs_andMatrixInput_3_322}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_322, decoder_decoded_andMatrixOutputs_andMatrixInput_1_322}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_322 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_262, decoder_decoded_andMatrixOutputs_hi_hi_lo_203}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_322 = {decoder_decoded_andMatrixOutputs_hi_hi_322, decoder_decoded_andMatrixOutputs_hi_lo_314}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_322 = {decoder_decoded_andMatrixOutputs_hi_322, decoder_decoded_andMatrixOutputs_lo_322}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_147_2_1 = &_decoder_decoded_andMatrixOutputs_T_322; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_107 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_176, decoder_decoded_andMatrixOutputs_andMatrixInput_15_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_204, decoder_decoded_andMatrixOutputs_andMatrixInput_13_200}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_301 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_211, decoder_decoded_andMatrixOutputs_lo_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_217, decoder_decoded_andMatrixOutputs_andMatrixInput_11_211}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_263, decoder_decoded_andMatrixOutputs_andMatrixInput_9_223}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_321 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_223, decoder_decoded_andMatrixOutputs_lo_hi_lo_200}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_323 = {decoder_decoded_andMatrixOutputs_lo_hi_321, decoder_decoded_andMatrixOutputs_lo_lo_301}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_176 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_315, decoder_decoded_andMatrixOutputs_andMatrixInput_7_301}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_323, decoder_decoded_andMatrixOutputs_andMatrixInput_5_321}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_315 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_217, decoder_decoded_andMatrixOutputs_hi_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_323, decoder_decoded_andMatrixOutputs_andMatrixInput_3_323}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_323, decoder_decoded_andMatrixOutputs_andMatrixInput_1_323}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_323 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_263, decoder_decoded_andMatrixOutputs_hi_hi_lo_204}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_323 = {decoder_decoded_andMatrixOutputs_hi_hi_323, decoder_decoded_andMatrixOutputs_hi_lo_315}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_323 = {decoder_decoded_andMatrixOutputs_hi_323, decoder_decoded_andMatrixOutputs_lo_323}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_27_2_1 = &_decoder_decoded_andMatrixOutputs_T_323; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_205, decoder_decoded_andMatrixOutputs_andMatrixInput_13_201}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_302 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_212, decoder_decoded_andMatrixOutputs_andMatrixInput_14_177}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_218, decoder_decoded_andMatrixOutputs_andMatrixInput_11_212}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_264, decoder_decoded_andMatrixOutputs_andMatrixInput_9_224}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_322 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_224, decoder_decoded_andMatrixOutputs_lo_hi_lo_201}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_324 = {decoder_decoded_andMatrixOutputs_lo_hi_322, decoder_decoded_andMatrixOutputs_lo_lo_302}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_177 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_316, decoder_decoded_andMatrixOutputs_andMatrixInput_7_302}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_324, decoder_decoded_andMatrixOutputs_andMatrixInput_5_322}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_316 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_218, decoder_decoded_andMatrixOutputs_hi_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_324, decoder_decoded_andMatrixOutputs_andMatrixInput_3_324}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_264 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_324, decoder_decoded_andMatrixOutputs_andMatrixInput_1_324}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_324 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_264, decoder_decoded_andMatrixOutputs_hi_hi_lo_205}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_324 = {decoder_decoded_andMatrixOutputs_hi_hi_324, decoder_decoded_andMatrixOutputs_hi_lo_316}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_324 = {decoder_decoded_andMatrixOutputs_hi_324, decoder_decoded_andMatrixOutputs_lo_324}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_51_2_1 = &_decoder_decoded_andMatrixOutputs_T_324; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_206, decoder_decoded_andMatrixOutputs_andMatrixInput_13_202}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_303 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_213, decoder_decoded_andMatrixOutputs_andMatrixInput_14_178}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_219, decoder_decoded_andMatrixOutputs_andMatrixInput_11_213}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_265, decoder_decoded_andMatrixOutputs_andMatrixInput_9_225}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_323 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_225, decoder_decoded_andMatrixOutputs_lo_hi_lo_202}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_325 = {decoder_decoded_andMatrixOutputs_lo_hi_323, decoder_decoded_andMatrixOutputs_lo_lo_303}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_178 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_317, decoder_decoded_andMatrixOutputs_andMatrixInput_7_303}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_325, decoder_decoded_andMatrixOutputs_andMatrixInput_5_323}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_317 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_219, decoder_decoded_andMatrixOutputs_hi_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_325, decoder_decoded_andMatrixOutputs_andMatrixInput_3_325}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_265 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_325, decoder_decoded_andMatrixOutputs_andMatrixInput_1_325}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_325 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_265, decoder_decoded_andMatrixOutputs_hi_hi_lo_206}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_325 = {decoder_decoded_andMatrixOutputs_hi_hi_325, decoder_decoded_andMatrixOutputs_hi_lo_317}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_325 = {decoder_decoded_andMatrixOutputs_hi_325, decoder_decoded_andMatrixOutputs_lo_325}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_138_2_1 = &_decoder_decoded_andMatrixOutputs_T_325; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_108 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_179, decoder_decoded_andMatrixOutputs_andMatrixInput_15_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_207, decoder_decoded_andMatrixOutputs_andMatrixInput_13_203}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_304 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_214, decoder_decoded_andMatrixOutputs_lo_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_220, decoder_decoded_andMatrixOutputs_andMatrixInput_11_214}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_266, decoder_decoded_andMatrixOutputs_andMatrixInput_9_226}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_324 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_226, decoder_decoded_andMatrixOutputs_lo_hi_lo_203}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_326 = {decoder_decoded_andMatrixOutputs_lo_hi_324, decoder_decoded_andMatrixOutputs_lo_lo_304}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_179 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_318, decoder_decoded_andMatrixOutputs_andMatrixInput_7_304}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_326, decoder_decoded_andMatrixOutputs_andMatrixInput_5_324}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_318 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_220, decoder_decoded_andMatrixOutputs_hi_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_326, decoder_decoded_andMatrixOutputs_andMatrixInput_3_326}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_326, decoder_decoded_andMatrixOutputs_andMatrixInput_1_326}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_326 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_266, decoder_decoded_andMatrixOutputs_hi_hi_lo_207}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_326 = {decoder_decoded_andMatrixOutputs_hi_hi_326, decoder_decoded_andMatrixOutputs_hi_lo_318}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_326 = {decoder_decoded_andMatrixOutputs_hi_326, decoder_decoded_andMatrixOutputs_lo_326}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_178_2_1 = &_decoder_decoded_andMatrixOutputs_T_326; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_208, decoder_decoded_andMatrixOutputs_andMatrixInput_13_204}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_305 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_215, decoder_decoded_andMatrixOutputs_andMatrixInput_14_180}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_221, decoder_decoded_andMatrixOutputs_andMatrixInput_11_215}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_267, decoder_decoded_andMatrixOutputs_andMatrixInput_9_227}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_325 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_227, decoder_decoded_andMatrixOutputs_lo_hi_lo_204}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_327 = {decoder_decoded_andMatrixOutputs_lo_hi_325, decoder_decoded_andMatrixOutputs_lo_lo_305}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_180 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_319, decoder_decoded_andMatrixOutputs_andMatrixInput_7_305}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_327, decoder_decoded_andMatrixOutputs_andMatrixInput_5_325}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_319 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_221, decoder_decoded_andMatrixOutputs_hi_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_327, decoder_decoded_andMatrixOutputs_andMatrixInput_3_327}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_267 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_327, decoder_decoded_andMatrixOutputs_andMatrixInput_1_327}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_327 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_267, decoder_decoded_andMatrixOutputs_hi_hi_lo_208}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_327 = {decoder_decoded_andMatrixOutputs_hi_hi_327, decoder_decoded_andMatrixOutputs_hi_lo_319}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_327 = {decoder_decoded_andMatrixOutputs_hi_327, decoder_decoded_andMatrixOutputs_lo_327}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_174_2_1 = &_decoder_decoded_andMatrixOutputs_T_327; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_109 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_181, decoder_decoded_andMatrixOutputs_andMatrixInput_15_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_209, decoder_decoded_andMatrixOutputs_andMatrixInput_13_205}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_306 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_216, decoder_decoded_andMatrixOutputs_lo_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_222, decoder_decoded_andMatrixOutputs_andMatrixInput_11_216}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_268, decoder_decoded_andMatrixOutputs_andMatrixInput_9_228}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_326 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_228, decoder_decoded_andMatrixOutputs_lo_hi_lo_205}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_328 = {decoder_decoded_andMatrixOutputs_lo_hi_326, decoder_decoded_andMatrixOutputs_lo_lo_306}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_181 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_320, decoder_decoded_andMatrixOutputs_andMatrixInput_7_306}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_328, decoder_decoded_andMatrixOutputs_andMatrixInput_5_326}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_320 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_222, decoder_decoded_andMatrixOutputs_hi_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_328, decoder_decoded_andMatrixOutputs_andMatrixInput_3_328}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_268 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_328, decoder_decoded_andMatrixOutputs_andMatrixInput_1_328}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_328 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_268, decoder_decoded_andMatrixOutputs_hi_hi_lo_209}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_328 = {decoder_decoded_andMatrixOutputs_hi_hi_328, decoder_decoded_andMatrixOutputs_hi_lo_320}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_328 = {decoder_decoded_andMatrixOutputs_hi_328, decoder_decoded_andMatrixOutputs_lo_328}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_120_2_1 = &_decoder_decoded_andMatrixOutputs_T_328; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_110 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_182, decoder_decoded_andMatrixOutputs_andMatrixInput_15_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_210, decoder_decoded_andMatrixOutputs_andMatrixInput_13_206}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_307 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_217, decoder_decoded_andMatrixOutputs_lo_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_223, decoder_decoded_andMatrixOutputs_andMatrixInput_11_217}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_269, decoder_decoded_andMatrixOutputs_andMatrixInput_9_229}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_327 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_229, decoder_decoded_andMatrixOutputs_lo_hi_lo_206}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_329 = {decoder_decoded_andMatrixOutputs_lo_hi_327, decoder_decoded_andMatrixOutputs_lo_lo_307}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_182 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_321, decoder_decoded_andMatrixOutputs_andMatrixInput_7_307}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_329, decoder_decoded_andMatrixOutputs_andMatrixInput_5_327}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_321 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_223, decoder_decoded_andMatrixOutputs_hi_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_329, decoder_decoded_andMatrixOutputs_andMatrixInput_3_329}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_269 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_329, decoder_decoded_andMatrixOutputs_andMatrixInput_1_329}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_329 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_269, decoder_decoded_andMatrixOutputs_hi_hi_lo_210}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_329 = {decoder_decoded_andMatrixOutputs_hi_hi_329, decoder_decoded_andMatrixOutputs_hi_lo_321}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_329 = {decoder_decoded_andMatrixOutputs_hi_329, decoder_decoded_andMatrixOutputs_lo_329}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_19_2_1 = &_decoder_decoded_andMatrixOutputs_T_329; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_211, decoder_decoded_andMatrixOutputs_andMatrixInput_13_207}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_308 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_218, decoder_decoded_andMatrixOutputs_andMatrixInput_14_183}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_224, decoder_decoded_andMatrixOutputs_andMatrixInput_11_218}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_270, decoder_decoded_andMatrixOutputs_andMatrixInput_9_230}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_328 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_230, decoder_decoded_andMatrixOutputs_lo_hi_lo_207}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_330 = {decoder_decoded_andMatrixOutputs_lo_hi_328, decoder_decoded_andMatrixOutputs_lo_lo_308}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_183 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_322, decoder_decoded_andMatrixOutputs_andMatrixInput_7_308}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_330, decoder_decoded_andMatrixOutputs_andMatrixInput_5_328}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_322 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_224, decoder_decoded_andMatrixOutputs_hi_lo_lo_183}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_330, decoder_decoded_andMatrixOutputs_andMatrixInput_3_330}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_270 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_330, decoder_decoded_andMatrixOutputs_andMatrixInput_1_330}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_330 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_270, decoder_decoded_andMatrixOutputs_hi_hi_lo_211}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_330 = {decoder_decoded_andMatrixOutputs_hi_hi_330, decoder_decoded_andMatrixOutputs_hi_lo_322}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_330 = {decoder_decoded_andMatrixOutputs_hi_330, decoder_decoded_andMatrixOutputs_lo_330}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_63_2_1 = &_decoder_decoded_andMatrixOutputs_T_330; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_111 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_184, decoder_decoded_andMatrixOutputs_andMatrixInput_15_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_212, decoder_decoded_andMatrixOutputs_andMatrixInput_13_208}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_309 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_219, decoder_decoded_andMatrixOutputs_lo_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_225, decoder_decoded_andMatrixOutputs_andMatrixInput_11_219}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_271, decoder_decoded_andMatrixOutputs_andMatrixInput_9_231}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_329 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_231, decoder_decoded_andMatrixOutputs_lo_hi_lo_208}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_331 = {decoder_decoded_andMatrixOutputs_lo_hi_329, decoder_decoded_andMatrixOutputs_lo_lo_309}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_184 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_323, decoder_decoded_andMatrixOutputs_andMatrixInput_7_309}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_331, decoder_decoded_andMatrixOutputs_andMatrixInput_5_329}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_323 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_225, decoder_decoded_andMatrixOutputs_hi_lo_lo_184}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_331, decoder_decoded_andMatrixOutputs_andMatrixInput_3_331}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_271 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_331, decoder_decoded_andMatrixOutputs_andMatrixInput_1_331}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_331 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_271, decoder_decoded_andMatrixOutputs_hi_hi_lo_212}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_331 = {decoder_decoded_andMatrixOutputs_hi_hi_331, decoder_decoded_andMatrixOutputs_hi_lo_323}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_331 = {decoder_decoded_andMatrixOutputs_hi_331, decoder_decoded_andMatrixOutputs_lo_331}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_142_2_1 = &_decoder_decoded_andMatrixOutputs_T_331; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_112 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_185, decoder_decoded_andMatrixOutputs_andMatrixInput_15_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_213, decoder_decoded_andMatrixOutputs_andMatrixInput_13_209}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_310 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_220, decoder_decoded_andMatrixOutputs_lo_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_226, decoder_decoded_andMatrixOutputs_andMatrixInput_11_220}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_272, decoder_decoded_andMatrixOutputs_andMatrixInput_9_232}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_330 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_232, decoder_decoded_andMatrixOutputs_lo_hi_lo_209}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_332 = {decoder_decoded_andMatrixOutputs_lo_hi_330, decoder_decoded_andMatrixOutputs_lo_lo_310}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_185 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_324, decoder_decoded_andMatrixOutputs_andMatrixInput_7_310}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_332, decoder_decoded_andMatrixOutputs_andMatrixInput_5_330}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_324 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_226, decoder_decoded_andMatrixOutputs_hi_lo_lo_185}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_332, decoder_decoded_andMatrixOutputs_andMatrixInput_3_332}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_272 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_332, decoder_decoded_andMatrixOutputs_andMatrixInput_1_332}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_332 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_272, decoder_decoded_andMatrixOutputs_hi_hi_lo_213}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_332 = {decoder_decoded_andMatrixOutputs_hi_hi_332, decoder_decoded_andMatrixOutputs_hi_lo_324}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_332 = {decoder_decoded_andMatrixOutputs_hi_332, decoder_decoded_andMatrixOutputs_lo_332}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_11_2_1 = &_decoder_decoded_andMatrixOutputs_T_332; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_113 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_113, decoder_decoded_andMatrixOutputs_andMatrixInput_16_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_210, decoder_decoded_andMatrixOutputs_andMatrixInput_14_186}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_311 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_221, decoder_decoded_andMatrixOutputs_lo_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_221, decoder_decoded_andMatrixOutputs_andMatrixInput_12_214}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_233, decoder_decoded_andMatrixOutputs_andMatrixInput_10_227}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_331 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_233, decoder_decoded_andMatrixOutputs_lo_hi_lo_210}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_333 = {decoder_decoded_andMatrixOutputs_lo_hi_331, decoder_decoded_andMatrixOutputs_lo_lo_311}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_186 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_311, decoder_decoded_andMatrixOutputs_andMatrixInput_8_273}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_331, decoder_decoded_andMatrixOutputs_andMatrixInput_6_325}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_325 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_227, decoder_decoded_andMatrixOutputs_hi_lo_lo_186}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_333, decoder_decoded_andMatrixOutputs_andMatrixInput_4_333}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_333, decoder_decoded_andMatrixOutputs_andMatrixInput_1_333}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_273 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_2_333}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_333 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_273, decoder_decoded_andMatrixOutputs_hi_hi_lo_214}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_333 = {decoder_decoded_andMatrixOutputs_hi_hi_333, decoder_decoded_andMatrixOutputs_hi_lo_325}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_333 = {decoder_decoded_andMatrixOutputs_hi_333, decoder_decoded_andMatrixOutputs_lo_333}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_47_2_1 = &_decoder_decoded_andMatrixOutputs_T_333; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_114 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_114, decoder_decoded_andMatrixOutputs_andMatrixInput_16_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_211, decoder_decoded_andMatrixOutputs_andMatrixInput_14_187}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_312 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_222, decoder_decoded_andMatrixOutputs_lo_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_222, decoder_decoded_andMatrixOutputs_andMatrixInput_12_215}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_234, decoder_decoded_andMatrixOutputs_andMatrixInput_10_228}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_332 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_234, decoder_decoded_andMatrixOutputs_lo_hi_lo_211}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_334 = {decoder_decoded_andMatrixOutputs_lo_hi_332, decoder_decoded_andMatrixOutputs_lo_lo_312}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_187 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_312, decoder_decoded_andMatrixOutputs_andMatrixInput_8_274}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_332, decoder_decoded_andMatrixOutputs_andMatrixInput_6_326}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_326 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_228, decoder_decoded_andMatrixOutputs_hi_lo_lo_187}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_334, decoder_decoded_andMatrixOutputs_andMatrixInput_4_334}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_334, decoder_decoded_andMatrixOutputs_andMatrixInput_1_334}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_274 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_2_334}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_334 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_274, decoder_decoded_andMatrixOutputs_hi_hi_lo_215}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_334 = {decoder_decoded_andMatrixOutputs_hi_hi_334, decoder_decoded_andMatrixOutputs_hi_lo_326}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_334 = {decoder_decoded_andMatrixOutputs_hi_334, decoder_decoded_andMatrixOutputs_lo_334}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_141_2_1 = &_decoder_decoded_andMatrixOutputs_T_334; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_115 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_65, decoder_decoded_andMatrixOutputs_andMatrixInput_17_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_188, decoder_decoded_andMatrixOutputs_andMatrixInput_15_115}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_313 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_223, decoder_decoded_andMatrixOutputs_lo_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_216, decoder_decoded_andMatrixOutputs_andMatrixInput_13_212}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_235, decoder_decoded_andMatrixOutputs_andMatrixInput_10_229}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_235 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_223}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_333 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_235, decoder_decoded_andMatrixOutputs_lo_hi_lo_212}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_335 = {decoder_decoded_andMatrixOutputs_lo_hi_333, decoder_decoded_andMatrixOutputs_lo_lo_313}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_188 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_313, decoder_decoded_andMatrixOutputs_andMatrixInput_8_275}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_333, decoder_decoded_andMatrixOutputs_andMatrixInput_6_327}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_327 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_229, decoder_decoded_andMatrixOutputs_hi_lo_lo_188}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_335, decoder_decoded_andMatrixOutputs_andMatrixInput_4_335}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_335, decoder_decoded_andMatrixOutputs_andMatrixInput_1_335}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_275 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_andMatrixInput_2_335}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_335 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_275, decoder_decoded_andMatrixOutputs_hi_hi_lo_216}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_335 = {decoder_decoded_andMatrixOutputs_hi_hi_335, decoder_decoded_andMatrixOutputs_hi_lo_327}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_335 = {decoder_decoded_andMatrixOutputs_hi_335, decoder_decoded_andMatrixOutputs_lo_335}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_114_2_1 = &_decoder_decoded_andMatrixOutputs_T_335; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_116 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_116, decoder_decoded_andMatrixOutputs_andMatrixInput_16_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_213, decoder_decoded_andMatrixOutputs_andMatrixInput_14_189}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_314 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_224, decoder_decoded_andMatrixOutputs_lo_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_224, decoder_decoded_andMatrixOutputs_andMatrixInput_12_217}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_236, decoder_decoded_andMatrixOutputs_andMatrixInput_10_230}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_334 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_236, decoder_decoded_andMatrixOutputs_lo_hi_lo_213}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_336 = {decoder_decoded_andMatrixOutputs_lo_hi_334, decoder_decoded_andMatrixOutputs_lo_lo_314}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_189 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_314, decoder_decoded_andMatrixOutputs_andMatrixInput_8_276}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_334, decoder_decoded_andMatrixOutputs_andMatrixInput_6_328}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_328 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_230, decoder_decoded_andMatrixOutputs_hi_lo_lo_189}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_336, decoder_decoded_andMatrixOutputs_andMatrixInput_4_336}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_336, decoder_decoded_andMatrixOutputs_andMatrixInput_1_336}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_276 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_andMatrixInput_2_336}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_336 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_276, decoder_decoded_andMatrixOutputs_hi_hi_lo_217}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_336 = {decoder_decoded_andMatrixOutputs_hi_hi_336, decoder_decoded_andMatrixOutputs_hi_lo_328}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_336 = {decoder_decoded_andMatrixOutputs_hi_336, decoder_decoded_andMatrixOutputs_lo_336}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_69_2_1 = &_decoder_decoded_andMatrixOutputs_T_336; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_117 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_67, decoder_decoded_andMatrixOutputs_andMatrixInput_17_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_190, decoder_decoded_andMatrixOutputs_andMatrixInput_15_117}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_315 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_225, decoder_decoded_andMatrixOutputs_lo_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_218, decoder_decoded_andMatrixOutputs_andMatrixInput_13_214}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_237, decoder_decoded_andMatrixOutputs_andMatrixInput_10_231}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_237 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_225}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_335 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_237, decoder_decoded_andMatrixOutputs_lo_hi_lo_214}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_337 = {decoder_decoded_andMatrixOutputs_lo_hi_335, decoder_decoded_andMatrixOutputs_lo_lo_315}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_190 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_315, decoder_decoded_andMatrixOutputs_andMatrixInput_8_277}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_335, decoder_decoded_andMatrixOutputs_andMatrixInput_6_329}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_329 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_231, decoder_decoded_andMatrixOutputs_hi_lo_lo_190}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_337, decoder_decoded_andMatrixOutputs_andMatrixInput_4_337}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_337, decoder_decoded_andMatrixOutputs_andMatrixInput_1_337}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_277 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_andMatrixInput_2_337}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_337 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_277, decoder_decoded_andMatrixOutputs_hi_hi_lo_218}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_337 = {decoder_decoded_andMatrixOutputs_hi_hi_337, decoder_decoded_andMatrixOutputs_hi_lo_329}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_337 = {decoder_decoded_andMatrixOutputs_hi_337, decoder_decoded_andMatrixOutputs_lo_337}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_71_2_1 = &_decoder_decoded_andMatrixOutputs_T_337; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_118 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_118, decoder_decoded_andMatrixOutputs_andMatrixInput_16_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_215, decoder_decoded_andMatrixOutputs_andMatrixInput_14_191}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_316 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_226, decoder_decoded_andMatrixOutputs_lo_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_226, decoder_decoded_andMatrixOutputs_andMatrixInput_12_219}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_238, decoder_decoded_andMatrixOutputs_andMatrixInput_10_232}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_336 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_238, decoder_decoded_andMatrixOutputs_lo_hi_lo_215}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_338 = {decoder_decoded_andMatrixOutputs_lo_hi_336, decoder_decoded_andMatrixOutputs_lo_lo_316}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_191 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_316, decoder_decoded_andMatrixOutputs_andMatrixInput_8_278}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_336, decoder_decoded_andMatrixOutputs_andMatrixInput_6_330}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_330 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_232, decoder_decoded_andMatrixOutputs_hi_lo_lo_191}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_338, decoder_decoded_andMatrixOutputs_andMatrixInput_4_338}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_68 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_338, decoder_decoded_andMatrixOutputs_andMatrixInput_1_338}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_278 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_andMatrixInput_2_338}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_338 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_278, decoder_decoded_andMatrixOutputs_hi_hi_lo_219}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_338 = {decoder_decoded_andMatrixOutputs_hi_hi_338, decoder_decoded_andMatrixOutputs_hi_lo_330}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_338 = {decoder_decoded_andMatrixOutputs_hi_338, decoder_decoded_andMatrixOutputs_lo_338}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_175_2_1 = &_decoder_decoded_andMatrixOutputs_T_338; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_119 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_69, decoder_decoded_andMatrixOutputs_andMatrixInput_17_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_192, decoder_decoded_andMatrixOutputs_andMatrixInput_15_119}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_317 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_227, decoder_decoded_andMatrixOutputs_lo_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_220, decoder_decoded_andMatrixOutputs_andMatrixInput_13_216}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_239, decoder_decoded_andMatrixOutputs_andMatrixInput_10_233}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_239 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_227}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_337 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_239, decoder_decoded_andMatrixOutputs_lo_hi_lo_216}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_339 = {decoder_decoded_andMatrixOutputs_lo_hi_337, decoder_decoded_andMatrixOutputs_lo_lo_317}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_192 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_317, decoder_decoded_andMatrixOutputs_andMatrixInput_8_279}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_337, decoder_decoded_andMatrixOutputs_andMatrixInput_6_331}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_331 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_233, decoder_decoded_andMatrixOutputs_hi_lo_lo_192}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_339, decoder_decoded_andMatrixOutputs_andMatrixInput_4_339}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_69 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_339, decoder_decoded_andMatrixOutputs_andMatrixInput_1_339}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_279 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_andMatrixInput_2_339}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_339 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_279, decoder_decoded_andMatrixOutputs_hi_hi_lo_220}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_339 = {decoder_decoded_andMatrixOutputs_hi_hi_339, decoder_decoded_andMatrixOutputs_hi_lo_331}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_339 = {decoder_decoded_andMatrixOutputs_hi_339, decoder_decoded_andMatrixOutputs_lo_339}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_80_2_1 = &_decoder_decoded_andMatrixOutputs_T_339; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_221 = decoder_decoded_plaInput_1[26]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_222 = decoder_decoded_plaInput_1[26]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_120 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_120, decoder_decoded_andMatrixOutputs_andMatrixInput_16_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_217, decoder_decoded_andMatrixOutputs_andMatrixInput_14_193}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_318 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_228, decoder_decoded_andMatrixOutputs_lo_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_217 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_228, decoder_decoded_andMatrixOutputs_andMatrixInput_12_221}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_240, decoder_decoded_andMatrixOutputs_andMatrixInput_10_234}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_338 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_240, decoder_decoded_andMatrixOutputs_lo_hi_lo_217}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_340 = {decoder_decoded_andMatrixOutputs_lo_hi_338, decoder_decoded_andMatrixOutputs_lo_lo_318}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_193 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_318, decoder_decoded_andMatrixOutputs_andMatrixInput_8_280}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_338, decoder_decoded_andMatrixOutputs_andMatrixInput_6_332}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_332 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_234, decoder_decoded_andMatrixOutputs_hi_lo_lo_193}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_340, decoder_decoded_andMatrixOutputs_andMatrixInput_4_340}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_70 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_340, decoder_decoded_andMatrixOutputs_andMatrixInput_1_340}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_280 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_andMatrixInput_2_340}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_340 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_280, decoder_decoded_andMatrixOutputs_hi_hi_lo_221}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_340 = {decoder_decoded_andMatrixOutputs_hi_hi_340, decoder_decoded_andMatrixOutputs_hi_lo_332}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_340 = {decoder_decoded_andMatrixOutputs_hi_340, decoder_decoded_andMatrixOutputs_lo_340}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_130_2_1 = &_decoder_decoded_andMatrixOutputs_T_340; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_121 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_71, decoder_decoded_andMatrixOutputs_andMatrixInput_17_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_194, decoder_decoded_andMatrixOutputs_andMatrixInput_15_121}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_319 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_229, decoder_decoded_andMatrixOutputs_lo_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_218 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_222, decoder_decoded_andMatrixOutputs_andMatrixInput_13_218}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_241, decoder_decoded_andMatrixOutputs_andMatrixInput_10_235}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_241 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_229}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_339 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_241, decoder_decoded_andMatrixOutputs_lo_hi_lo_218}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_341 = {decoder_decoded_andMatrixOutputs_lo_hi_339, decoder_decoded_andMatrixOutputs_lo_lo_319}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_194 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_319, decoder_decoded_andMatrixOutputs_andMatrixInput_8_281}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_339, decoder_decoded_andMatrixOutputs_andMatrixInput_6_333}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_333 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_235, decoder_decoded_andMatrixOutputs_hi_lo_lo_194}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_341, decoder_decoded_andMatrixOutputs_andMatrixInput_4_341}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_71 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_341, decoder_decoded_andMatrixOutputs_andMatrixInput_1_341}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_281 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_andMatrixInput_2_341}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_341 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_281, decoder_decoded_andMatrixOutputs_hi_hi_lo_222}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_341 = {decoder_decoded_andMatrixOutputs_hi_hi_341, decoder_decoded_andMatrixOutputs_hi_lo_333}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_341 = {decoder_decoded_andMatrixOutputs_hi_341, decoder_decoded_andMatrixOutputs_lo_341}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_157_2_1 = &_decoder_decoded_andMatrixOutputs_T_341; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_223, decoder_decoded_andMatrixOutputs_andMatrixInput_13_219}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_320 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_230, decoder_decoded_andMatrixOutputs_andMatrixInput_14_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_236, decoder_decoded_andMatrixOutputs_andMatrixInput_11_230}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_282, decoder_decoded_andMatrixOutputs_andMatrixInput_9_242}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_340 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_242, decoder_decoded_andMatrixOutputs_lo_hi_lo_219}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_342 = {decoder_decoded_andMatrixOutputs_lo_hi_340, decoder_decoded_andMatrixOutputs_lo_lo_320}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_195 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_334, decoder_decoded_andMatrixOutputs_andMatrixInput_7_320}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_342, decoder_decoded_andMatrixOutputs_andMatrixInput_5_340}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_334 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_236, decoder_decoded_andMatrixOutputs_hi_lo_lo_195}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_342, decoder_decoded_andMatrixOutputs_andMatrixInput_3_342}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_282 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_342, decoder_decoded_andMatrixOutputs_andMatrixInput_1_342}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_342 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_282, decoder_decoded_andMatrixOutputs_hi_hi_lo_223}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_342 = {decoder_decoded_andMatrixOutputs_hi_hi_342, decoder_decoded_andMatrixOutputs_hi_lo_334}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_342 = {decoder_decoded_andMatrixOutputs_hi_342, decoder_decoded_andMatrixOutputs_lo_342}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_67_2_1 = &_decoder_decoded_andMatrixOutputs_T_342; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_224, decoder_decoded_andMatrixOutputs_andMatrixInput_13_220}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_321 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_231, decoder_decoded_andMatrixOutputs_andMatrixInput_14_196}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_237, decoder_decoded_andMatrixOutputs_andMatrixInput_11_231}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_283, decoder_decoded_andMatrixOutputs_andMatrixInput_9_243}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_341 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_243, decoder_decoded_andMatrixOutputs_lo_hi_lo_220}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_343 = {decoder_decoded_andMatrixOutputs_lo_hi_341, decoder_decoded_andMatrixOutputs_lo_lo_321}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_196 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_335, decoder_decoded_andMatrixOutputs_andMatrixInput_7_321}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_343, decoder_decoded_andMatrixOutputs_andMatrixInput_5_341}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_335 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_237, decoder_decoded_andMatrixOutputs_hi_lo_lo_196}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_343, decoder_decoded_andMatrixOutputs_andMatrixInput_3_343}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_283 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_343, decoder_decoded_andMatrixOutputs_andMatrixInput_1_343}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_343 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_283, decoder_decoded_andMatrixOutputs_hi_hi_lo_224}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_343 = {decoder_decoded_andMatrixOutputs_hi_hi_343, decoder_decoded_andMatrixOutputs_hi_lo_335}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_343 = {decoder_decoded_andMatrixOutputs_hi_343, decoder_decoded_andMatrixOutputs_lo_343}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_42_2_1 = &_decoder_decoded_andMatrixOutputs_T_343; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_122 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_197, decoder_decoded_andMatrixOutputs_andMatrixInput_15_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_225, decoder_decoded_andMatrixOutputs_andMatrixInput_13_221}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_322 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_232, decoder_decoded_andMatrixOutputs_lo_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_238, decoder_decoded_andMatrixOutputs_andMatrixInput_11_232}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_284, decoder_decoded_andMatrixOutputs_andMatrixInput_9_244}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_342 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_244, decoder_decoded_andMatrixOutputs_lo_hi_lo_221}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_344 = {decoder_decoded_andMatrixOutputs_lo_hi_342, decoder_decoded_andMatrixOutputs_lo_lo_322}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_197 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_336, decoder_decoded_andMatrixOutputs_andMatrixInput_7_322}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_344, decoder_decoded_andMatrixOutputs_andMatrixInput_5_342}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_336 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_238, decoder_decoded_andMatrixOutputs_hi_lo_lo_197}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_344, decoder_decoded_andMatrixOutputs_andMatrixInput_3_344}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_284 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_344, decoder_decoded_andMatrixOutputs_andMatrixInput_1_344}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_344 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_284, decoder_decoded_andMatrixOutputs_hi_hi_lo_225}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_344 = {decoder_decoded_andMatrixOutputs_hi_hi_344, decoder_decoded_andMatrixOutputs_hi_lo_336}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_344 = {decoder_decoded_andMatrixOutputs_hi_344, decoder_decoded_andMatrixOutputs_lo_344}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_53_2_1 = &_decoder_decoded_andMatrixOutputs_T_344; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_123 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_198, decoder_decoded_andMatrixOutputs_andMatrixInput_15_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_226, decoder_decoded_andMatrixOutputs_andMatrixInput_13_222}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_323 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_233, decoder_decoded_andMatrixOutputs_lo_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_239, decoder_decoded_andMatrixOutputs_andMatrixInput_11_233}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_245 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_285, decoder_decoded_andMatrixOutputs_andMatrixInput_9_245}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_343 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_245, decoder_decoded_andMatrixOutputs_lo_hi_lo_222}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_345 = {decoder_decoded_andMatrixOutputs_lo_hi_343, decoder_decoded_andMatrixOutputs_lo_lo_323}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_198 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_337, decoder_decoded_andMatrixOutputs_andMatrixInput_7_323}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_345, decoder_decoded_andMatrixOutputs_andMatrixInput_5_343}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_337 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_239, decoder_decoded_andMatrixOutputs_hi_lo_lo_198}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_345, decoder_decoded_andMatrixOutputs_andMatrixInput_3_345}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_285 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_345, decoder_decoded_andMatrixOutputs_andMatrixInput_1_345}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_345 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_285, decoder_decoded_andMatrixOutputs_hi_hi_lo_226}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_345 = {decoder_decoded_andMatrixOutputs_hi_hi_345, decoder_decoded_andMatrixOutputs_hi_lo_337}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_345 = {decoder_decoded_andMatrixOutputs_hi_345, decoder_decoded_andMatrixOutputs_lo_345}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_62_2_1 = &_decoder_decoded_andMatrixOutputs_T_345; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_124 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_199, decoder_decoded_andMatrixOutputs_andMatrixInput_15_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_227, decoder_decoded_andMatrixOutputs_andMatrixInput_13_223}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_324 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_234, decoder_decoded_andMatrixOutputs_lo_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_240, decoder_decoded_andMatrixOutputs_andMatrixInput_11_234}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_286, decoder_decoded_andMatrixOutputs_andMatrixInput_9_246}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_344 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_246, decoder_decoded_andMatrixOutputs_lo_hi_lo_223}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_346 = {decoder_decoded_andMatrixOutputs_lo_hi_344, decoder_decoded_andMatrixOutputs_lo_lo_324}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_199 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_338, decoder_decoded_andMatrixOutputs_andMatrixInput_7_324}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_346, decoder_decoded_andMatrixOutputs_andMatrixInput_5_344}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_338 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_240, decoder_decoded_andMatrixOutputs_hi_lo_lo_199}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_346, decoder_decoded_andMatrixOutputs_andMatrixInput_3_346}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_286 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_346, decoder_decoded_andMatrixOutputs_andMatrixInput_1_346}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_346 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_286, decoder_decoded_andMatrixOutputs_hi_hi_lo_227}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_346 = {decoder_decoded_andMatrixOutputs_hi_hi_346, decoder_decoded_andMatrixOutputs_hi_lo_338}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_346 = {decoder_decoded_andMatrixOutputs_hi_346, decoder_decoded_andMatrixOutputs_lo_346}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_68_2_1 = &_decoder_decoded_andMatrixOutputs_T_346; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_125 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_125, decoder_decoded_andMatrixOutputs_andMatrixInput_16_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_224, decoder_decoded_andMatrixOutputs_andMatrixInput_14_200}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_325 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_235, decoder_decoded_andMatrixOutputs_lo_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_235, decoder_decoded_andMatrixOutputs_andMatrixInput_12_228}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_247, decoder_decoded_andMatrixOutputs_andMatrixInput_10_241}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_345 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_247, decoder_decoded_andMatrixOutputs_lo_hi_lo_224}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_347 = {decoder_decoded_andMatrixOutputs_lo_hi_345, decoder_decoded_andMatrixOutputs_lo_lo_325}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_200 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_325, decoder_decoded_andMatrixOutputs_andMatrixInput_8_287}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_345, decoder_decoded_andMatrixOutputs_andMatrixInput_6_339}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_339 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_241, decoder_decoded_andMatrixOutputs_hi_lo_lo_200}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_347, decoder_decoded_andMatrixOutputs_andMatrixInput_4_347}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_72 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_347, decoder_decoded_andMatrixOutputs_andMatrixInput_1_347}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_287 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_72, decoder_decoded_andMatrixOutputs_andMatrixInput_2_347}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_347 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_287, decoder_decoded_andMatrixOutputs_hi_hi_lo_228}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_347 = {decoder_decoded_andMatrixOutputs_hi_hi_347, decoder_decoded_andMatrixOutputs_hi_lo_339}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_347 = {decoder_decoded_andMatrixOutputs_hi_347, decoder_decoded_andMatrixOutputs_lo_347}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_183_2_1 = &_decoder_decoded_andMatrixOutputs_T_347; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_126 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_73, decoder_decoded_andMatrixOutputs_andMatrixInput_17_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_201, decoder_decoded_andMatrixOutputs_andMatrixInput_15_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_326 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_236, decoder_decoded_andMatrixOutputs_lo_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_229, decoder_decoded_andMatrixOutputs_andMatrixInput_13_225}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_248, decoder_decoded_andMatrixOutputs_andMatrixInput_10_242}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_248 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_236}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_346 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_248, decoder_decoded_andMatrixOutputs_lo_hi_lo_225}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_348 = {decoder_decoded_andMatrixOutputs_lo_hi_346, decoder_decoded_andMatrixOutputs_lo_lo_326}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_201 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_326, decoder_decoded_andMatrixOutputs_andMatrixInput_8_288}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_346, decoder_decoded_andMatrixOutputs_andMatrixInput_6_340}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_340 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_242, decoder_decoded_andMatrixOutputs_hi_lo_lo_201}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_348, decoder_decoded_andMatrixOutputs_andMatrixInput_4_348}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_73 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_348, decoder_decoded_andMatrixOutputs_andMatrixInput_1_348}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_288 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_73, decoder_decoded_andMatrixOutputs_andMatrixInput_2_348}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_348 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_288, decoder_decoded_andMatrixOutputs_hi_hi_lo_229}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_348 = {decoder_decoded_andMatrixOutputs_hi_hi_348, decoder_decoded_andMatrixOutputs_hi_lo_340}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_348 = {decoder_decoded_andMatrixOutputs_hi_348, decoder_decoded_andMatrixOutputs_lo_348}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_50_2_1 = &_decoder_decoded_andMatrixOutputs_T_348; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_127 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_74, decoder_decoded_andMatrixOutputs_andMatrixInput_17_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_202, decoder_decoded_andMatrixOutputs_andMatrixInput_15_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_327 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_237, decoder_decoded_andMatrixOutputs_lo_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_230, decoder_decoded_andMatrixOutputs_andMatrixInput_13_226}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_249, decoder_decoded_andMatrixOutputs_andMatrixInput_10_243}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_249 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_237}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_347 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_249, decoder_decoded_andMatrixOutputs_lo_hi_lo_226}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_349 = {decoder_decoded_andMatrixOutputs_lo_hi_347, decoder_decoded_andMatrixOutputs_lo_lo_327}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_202 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_327, decoder_decoded_andMatrixOutputs_andMatrixInput_8_289}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_347, decoder_decoded_andMatrixOutputs_andMatrixInput_6_341}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_341 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_243, decoder_decoded_andMatrixOutputs_hi_lo_lo_202}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_349, decoder_decoded_andMatrixOutputs_andMatrixInput_4_349}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_74 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_349, decoder_decoded_andMatrixOutputs_andMatrixInput_1_349}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_289 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_74, decoder_decoded_andMatrixOutputs_andMatrixInput_2_349}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_349 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_289, decoder_decoded_andMatrixOutputs_hi_hi_lo_230}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_349 = {decoder_decoded_andMatrixOutputs_hi_hi_349, decoder_decoded_andMatrixOutputs_hi_lo_341}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_349 = {decoder_decoded_andMatrixOutputs_hi_349, decoder_decoded_andMatrixOutputs_lo_349}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_136_2_1 = &_decoder_decoded_andMatrixOutputs_T_349; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_128 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_52, decoder_decoded_andMatrixOutputs_andMatrixInput_18_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_128, decoder_decoded_andMatrixOutputs_andMatrixInput_16_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_328 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_238, decoder_decoded_andMatrixOutputs_lo_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_227, decoder_decoded_andMatrixOutputs_andMatrixInput_14_203}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_244, decoder_decoded_andMatrixOutputs_andMatrixInput_11_238}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_250 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_231}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_348 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_250, decoder_decoded_andMatrixOutputs_lo_hi_lo_227}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_350 = {decoder_decoded_andMatrixOutputs_lo_hi_348, decoder_decoded_andMatrixOutputs_lo_lo_328}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_203 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_290, decoder_decoded_andMatrixOutputs_andMatrixInput_9_250}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_348, decoder_decoded_andMatrixOutputs_andMatrixInput_6_342}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_244 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_andMatrixInput_7_328}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_342 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_244, decoder_decoded_andMatrixOutputs_hi_lo_lo_203}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_350, decoder_decoded_andMatrixOutputs_andMatrixInput_4_350}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_75 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_350, decoder_decoded_andMatrixOutputs_andMatrixInput_1_350}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_290 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_75, decoder_decoded_andMatrixOutputs_andMatrixInput_2_350}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_350 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_290, decoder_decoded_andMatrixOutputs_hi_hi_lo_231}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_350 = {decoder_decoded_andMatrixOutputs_hi_hi_350, decoder_decoded_andMatrixOutputs_hi_lo_342}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_350 = {decoder_decoded_andMatrixOutputs_hi_350, decoder_decoded_andMatrixOutputs_lo_350}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_127_2_1 = &_decoder_decoded_andMatrixOutputs_T_350; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_129 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_129, decoder_decoded_andMatrixOutputs_andMatrixInput_16_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_228, decoder_decoded_andMatrixOutputs_andMatrixInput_14_204}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_329 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_239, decoder_decoded_andMatrixOutputs_lo_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_239, decoder_decoded_andMatrixOutputs_andMatrixInput_12_232}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_251 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_251, decoder_decoded_andMatrixOutputs_andMatrixInput_10_245}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_349 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_251, decoder_decoded_andMatrixOutputs_lo_hi_lo_228}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_351 = {decoder_decoded_andMatrixOutputs_lo_hi_349, decoder_decoded_andMatrixOutputs_lo_lo_329}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_204 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_329, decoder_decoded_andMatrixOutputs_andMatrixInput_8_291}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_245 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_349, decoder_decoded_andMatrixOutputs_andMatrixInput_6_343}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_343 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_245, decoder_decoded_andMatrixOutputs_hi_lo_lo_204}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_351, decoder_decoded_andMatrixOutputs_andMatrixInput_4_351}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_76 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_351, decoder_decoded_andMatrixOutputs_andMatrixInput_1_351}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_291 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_76, decoder_decoded_andMatrixOutputs_andMatrixInput_2_351}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_351 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_291, decoder_decoded_andMatrixOutputs_hi_hi_lo_232}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_351 = {decoder_decoded_andMatrixOutputs_hi_hi_351, decoder_decoded_andMatrixOutputs_hi_lo_343}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_351 = {decoder_decoded_andMatrixOutputs_hi_351, decoder_decoded_andMatrixOutputs_lo_351}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_151_2_1 = &_decoder_decoded_andMatrixOutputs_T_351; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_130 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_130, decoder_decoded_andMatrixOutputs_andMatrixInput_16_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_229, decoder_decoded_andMatrixOutputs_andMatrixInput_14_205}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_330 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_240, decoder_decoded_andMatrixOutputs_lo_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_240, decoder_decoded_andMatrixOutputs_andMatrixInput_12_233}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_252, decoder_decoded_andMatrixOutputs_andMatrixInput_10_246}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_350 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_252, decoder_decoded_andMatrixOutputs_lo_hi_lo_229}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_352 = {decoder_decoded_andMatrixOutputs_lo_hi_350, decoder_decoded_andMatrixOutputs_lo_lo_330}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_205 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_330, decoder_decoded_andMatrixOutputs_andMatrixInput_8_292}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_350, decoder_decoded_andMatrixOutputs_andMatrixInput_6_344}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_344 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_246, decoder_decoded_andMatrixOutputs_hi_lo_lo_205}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_352, decoder_decoded_andMatrixOutputs_andMatrixInput_4_352}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_77 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_352, decoder_decoded_andMatrixOutputs_andMatrixInput_1_352}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_292 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_77, decoder_decoded_andMatrixOutputs_andMatrixInput_2_352}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_352 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_292, decoder_decoded_andMatrixOutputs_hi_hi_lo_233}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_352 = {decoder_decoded_andMatrixOutputs_hi_hi_352, decoder_decoded_andMatrixOutputs_hi_lo_344}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_352 = {decoder_decoded_andMatrixOutputs_hi_352, decoder_decoded_andMatrixOutputs_lo_352}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_1_2_1 = &_decoder_decoded_andMatrixOutputs_T_352; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_131 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_131, decoder_decoded_andMatrixOutputs_andMatrixInput_16_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_230, decoder_decoded_andMatrixOutputs_andMatrixInput_14_206}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_331 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_241, decoder_decoded_andMatrixOutputs_lo_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_241, decoder_decoded_andMatrixOutputs_andMatrixInput_12_234}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_253 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_253, decoder_decoded_andMatrixOutputs_andMatrixInput_10_247}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_351 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_253, decoder_decoded_andMatrixOutputs_lo_hi_lo_230}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_353 = {decoder_decoded_andMatrixOutputs_lo_hi_351, decoder_decoded_andMatrixOutputs_lo_lo_331}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_206 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_331, decoder_decoded_andMatrixOutputs_andMatrixInput_8_293}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_351, decoder_decoded_andMatrixOutputs_andMatrixInput_6_345}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_345 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_247, decoder_decoded_andMatrixOutputs_hi_lo_lo_206}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_353, decoder_decoded_andMatrixOutputs_andMatrixInput_4_353}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_78 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_353, decoder_decoded_andMatrixOutputs_andMatrixInput_1_353}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_293 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_78, decoder_decoded_andMatrixOutputs_andMatrixInput_2_353}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_353 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_293, decoder_decoded_andMatrixOutputs_hi_hi_lo_234}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_353 = {decoder_decoded_andMatrixOutputs_hi_hi_353, decoder_decoded_andMatrixOutputs_hi_lo_345}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_353 = {decoder_decoded_andMatrixOutputs_hi_353, decoder_decoded_andMatrixOutputs_lo_353}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_99_2_1 = &_decoder_decoded_andMatrixOutputs_T_353; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_132 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_39, decoder_decoded_andMatrixOutputs_andMatrixInput_19_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_132, decoder_decoded_andMatrixOutputs_andMatrixInput_16_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_242 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_andMatrixInput_17_53}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_332 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_242, decoder_decoded_andMatrixOutputs_lo_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_231, decoder_decoded_andMatrixOutputs_andMatrixInput_14_207}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_248, decoder_decoded_andMatrixOutputs_andMatrixInput_11_242}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_254 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_235}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_352 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_254, decoder_decoded_andMatrixOutputs_lo_hi_lo_231}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_354 = {decoder_decoded_andMatrixOutputs_lo_hi_352, decoder_decoded_andMatrixOutputs_lo_lo_332}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_207 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_294, decoder_decoded_andMatrixOutputs_andMatrixInput_9_254}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_352, decoder_decoded_andMatrixOutputs_andMatrixInput_6_346}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_248 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_7_332}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_346 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_248, decoder_decoded_andMatrixOutputs_hi_lo_lo_207}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_354, decoder_decoded_andMatrixOutputs_andMatrixInput_4_354}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_79 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_354, decoder_decoded_andMatrixOutputs_andMatrixInput_1_354}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_294 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_79, decoder_decoded_andMatrixOutputs_andMatrixInput_2_354}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_354 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_294, decoder_decoded_andMatrixOutputs_hi_hi_lo_235}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_354 = {decoder_decoded_andMatrixOutputs_hi_hi_354, decoder_decoded_andMatrixOutputs_hi_lo_346}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_354 = {decoder_decoded_andMatrixOutputs_hi_354, decoder_decoded_andMatrixOutputs_lo_354}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_104_2_1 = &_decoder_decoded_andMatrixOutputs_T_354; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_133 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_40, decoder_decoded_andMatrixOutputs_andMatrixInput_19_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_133, decoder_decoded_andMatrixOutputs_andMatrixInput_16_80}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_243 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_andMatrixInput_17_54}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_333 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_243, decoder_decoded_andMatrixOutputs_lo_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_232, decoder_decoded_andMatrixOutputs_andMatrixInput_14_208}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_249, decoder_decoded_andMatrixOutputs_andMatrixInput_11_243}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_255 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_andMatrixInput_12_236}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_353 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_255, decoder_decoded_andMatrixOutputs_lo_hi_lo_232}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_355 = {decoder_decoded_andMatrixOutputs_lo_hi_353, decoder_decoded_andMatrixOutputs_lo_lo_333}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_208 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_295, decoder_decoded_andMatrixOutputs_andMatrixInput_9_255}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_353, decoder_decoded_andMatrixOutputs_andMatrixInput_6_347}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_249 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_7_333}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_347 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_249, decoder_decoded_andMatrixOutputs_hi_lo_lo_208}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_355, decoder_decoded_andMatrixOutputs_andMatrixInput_4_355}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_80 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_355, decoder_decoded_andMatrixOutputs_andMatrixInput_1_355}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_295 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_80, decoder_decoded_andMatrixOutputs_andMatrixInput_2_355}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_355 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_295, decoder_decoded_andMatrixOutputs_hi_hi_lo_236}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_355 = {decoder_decoded_andMatrixOutputs_hi_hi_355, decoder_decoded_andMatrixOutputs_hi_lo_347}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_355 = {decoder_decoded_andMatrixOutputs_hi_355, decoder_decoded_andMatrixOutputs_lo_355}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_186_2_1 = &_decoder_decoded_andMatrixOutputs_T_355; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_134 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_37, decoder_decoded_andMatrixOutputs_andMatrixInput_20_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_81, decoder_decoded_andMatrixOutputs_andMatrixInput_17_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_244 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_andMatrixInput_18_41}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_334 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_244, decoder_decoded_andMatrixOutputs_lo_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_209, decoder_decoded_andMatrixOutputs_andMatrixInput_15_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_244, decoder_decoded_andMatrixOutputs_andMatrixInput_12_237}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_256 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_andMatrixInput_13_233}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_354 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_256, decoder_decoded_andMatrixOutputs_lo_hi_lo_233}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_356 = {decoder_decoded_andMatrixOutputs_lo_hi_354, decoder_decoded_andMatrixOutputs_lo_lo_334}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_209 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_256, decoder_decoded_andMatrixOutputs_andMatrixInput_10_250}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_348, decoder_decoded_andMatrixOutputs_andMatrixInput_7_334}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_250 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_296}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_348 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_250, decoder_decoded_andMatrixOutputs_hi_lo_lo_209}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_356, decoder_decoded_andMatrixOutputs_andMatrixInput_4_356}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_237 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_354}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_81 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_356, decoder_decoded_andMatrixOutputs_andMatrixInput_1_356}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_296 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_81, decoder_decoded_andMatrixOutputs_andMatrixInput_2_356}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_356 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_296, decoder_decoded_andMatrixOutputs_hi_hi_lo_237}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_356 = {decoder_decoded_andMatrixOutputs_hi_hi_356, decoder_decoded_andMatrixOutputs_hi_lo_348}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_356 = {decoder_decoded_andMatrixOutputs_hi_356, decoder_decoded_andMatrixOutputs_lo_356}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_18_2_1 = &_decoder_decoded_andMatrixOutputs_T_356; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_135 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_42, decoder_decoded_andMatrixOutputs_andMatrixInput_19_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_135, decoder_decoded_andMatrixOutputs_andMatrixInput_16_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_245 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_andMatrixInput_17_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_335 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_245, decoder_decoded_andMatrixOutputs_lo_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_234, decoder_decoded_andMatrixOutputs_andMatrixInput_14_210}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_251, decoder_decoded_andMatrixOutputs_andMatrixInput_11_245}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_257 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_andMatrixInput_12_238}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_355 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_257, decoder_decoded_andMatrixOutputs_lo_hi_lo_234}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_357 = {decoder_decoded_andMatrixOutputs_lo_hi_355, decoder_decoded_andMatrixOutputs_lo_lo_335}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_210 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_297, decoder_decoded_andMatrixOutputs_andMatrixInput_9_257}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_355, decoder_decoded_andMatrixOutputs_andMatrixInput_6_349}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_251 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_7_335}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_349 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_251, decoder_decoded_andMatrixOutputs_hi_lo_lo_210}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_357, decoder_decoded_andMatrixOutputs_andMatrixInput_4_357}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_82 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_357, decoder_decoded_andMatrixOutputs_andMatrixInput_1_357}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_297 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_82, decoder_decoded_andMatrixOutputs_andMatrixInput_2_357}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_357 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_297, decoder_decoded_andMatrixOutputs_hi_hi_lo_238}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_357 = {decoder_decoded_andMatrixOutputs_hi_hi_357, decoder_decoded_andMatrixOutputs_hi_lo_349}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_357 = {decoder_decoded_andMatrixOutputs_hi_357, decoder_decoded_andMatrixOutputs_lo_357}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_106_2_1 = &_decoder_decoded_andMatrixOutputs_T_357; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_239, decoder_decoded_andMatrixOutputs_andMatrixInput_13_235}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_336 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_246, decoder_decoded_andMatrixOutputs_andMatrixInput_14_211}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_252, decoder_decoded_andMatrixOutputs_andMatrixInput_11_246}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_258 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_298, decoder_decoded_andMatrixOutputs_andMatrixInput_9_258}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_356 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_258, decoder_decoded_andMatrixOutputs_lo_hi_lo_235}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_358 = {decoder_decoded_andMatrixOutputs_lo_hi_356, decoder_decoded_andMatrixOutputs_lo_lo_336}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_211 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_350, decoder_decoded_andMatrixOutputs_andMatrixInput_7_336}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_358, decoder_decoded_andMatrixOutputs_andMatrixInput_5_356}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_350 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_252, decoder_decoded_andMatrixOutputs_hi_lo_lo_211}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_358, decoder_decoded_andMatrixOutputs_andMatrixInput_3_358}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_298 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_358, decoder_decoded_andMatrixOutputs_andMatrixInput_1_358}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_358 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_298, decoder_decoded_andMatrixOutputs_hi_hi_lo_239}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_358 = {decoder_decoded_andMatrixOutputs_hi_hi_358, decoder_decoded_andMatrixOutputs_hi_lo_350}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_358 = {decoder_decoded_andMatrixOutputs_hi_358, decoder_decoded_andMatrixOutputs_lo_358}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_88_2_1 = &_decoder_decoded_andMatrixOutputs_T_358; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_136 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_212, decoder_decoded_andMatrixOutputs_andMatrixInput_15_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_240, decoder_decoded_andMatrixOutputs_andMatrixInput_13_236}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_337 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_247, decoder_decoded_andMatrixOutputs_lo_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_253, decoder_decoded_andMatrixOutputs_andMatrixInput_11_247}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_259 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_299, decoder_decoded_andMatrixOutputs_andMatrixInput_9_259}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_357 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_259, decoder_decoded_andMatrixOutputs_lo_hi_lo_236}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_359 = {decoder_decoded_andMatrixOutputs_lo_hi_357, decoder_decoded_andMatrixOutputs_lo_lo_337}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_212 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_351, decoder_decoded_andMatrixOutputs_andMatrixInput_7_337}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_253 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_359, decoder_decoded_andMatrixOutputs_andMatrixInput_5_357}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_351 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_253, decoder_decoded_andMatrixOutputs_hi_lo_lo_212}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_240 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_359, decoder_decoded_andMatrixOutputs_andMatrixInput_3_359}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_299 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_359, decoder_decoded_andMatrixOutputs_andMatrixInput_1_359}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_359 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_299, decoder_decoded_andMatrixOutputs_hi_hi_lo_240}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_359 = {decoder_decoded_andMatrixOutputs_hi_hi_359, decoder_decoded_andMatrixOutputs_hi_lo_351}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_359 = {decoder_decoded_andMatrixOutputs_hi_359, decoder_decoded_andMatrixOutputs_lo_359}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_61_2_1 = &_decoder_decoded_andMatrixOutputs_T_359; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_137 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_213, decoder_decoded_andMatrixOutputs_andMatrixInput_15_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_241, decoder_decoded_andMatrixOutputs_andMatrixInput_13_237}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_338 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_248, decoder_decoded_andMatrixOutputs_lo_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_254, decoder_decoded_andMatrixOutputs_andMatrixInput_11_248}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_300, decoder_decoded_andMatrixOutputs_andMatrixInput_9_260}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_358 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_260, decoder_decoded_andMatrixOutputs_lo_hi_lo_237}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_360 = {decoder_decoded_andMatrixOutputs_lo_hi_358, decoder_decoded_andMatrixOutputs_lo_lo_338}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_213 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_352, decoder_decoded_andMatrixOutputs_andMatrixInput_7_338}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_254 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_360, decoder_decoded_andMatrixOutputs_andMatrixInput_5_358}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_352 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_254, decoder_decoded_andMatrixOutputs_hi_lo_lo_213}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_241 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_360, decoder_decoded_andMatrixOutputs_andMatrixInput_3_360}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_300 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_360, decoder_decoded_andMatrixOutputs_andMatrixInput_1_360}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_360 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_300, decoder_decoded_andMatrixOutputs_hi_hi_lo_241}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_360 = {decoder_decoded_andMatrixOutputs_hi_hi_360, decoder_decoded_andMatrixOutputs_hi_lo_352}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_360 = {decoder_decoded_andMatrixOutputs_hi_360, decoder_decoded_andMatrixOutputs_lo_360}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_149_2_1 = &_decoder_decoded_andMatrixOutputs_T_360; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_138 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_214, decoder_decoded_andMatrixOutputs_andMatrixInput_15_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_242, decoder_decoded_andMatrixOutputs_andMatrixInput_13_238}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_339 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_249, decoder_decoded_andMatrixOutputs_lo_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_255, decoder_decoded_andMatrixOutputs_andMatrixInput_11_249}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_301, decoder_decoded_andMatrixOutputs_andMatrixInput_9_261}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_359 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_261, decoder_decoded_andMatrixOutputs_lo_hi_lo_238}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_361 = {decoder_decoded_andMatrixOutputs_lo_hi_359, decoder_decoded_andMatrixOutputs_lo_lo_339}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_214 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_353, decoder_decoded_andMatrixOutputs_andMatrixInput_7_339}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_361, decoder_decoded_andMatrixOutputs_andMatrixInput_5_359}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_353 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_255, decoder_decoded_andMatrixOutputs_hi_lo_lo_214}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_242 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_361, decoder_decoded_andMatrixOutputs_andMatrixInput_3_361}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_301 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_361, decoder_decoded_andMatrixOutputs_andMatrixInput_1_361}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_361 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_301, decoder_decoded_andMatrixOutputs_hi_hi_lo_242}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_361 = {decoder_decoded_andMatrixOutputs_hi_hi_361, decoder_decoded_andMatrixOutputs_hi_lo_353}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_361 = {decoder_decoded_andMatrixOutputs_hi_361, decoder_decoded_andMatrixOutputs_lo_361}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_173_2_1 = &_decoder_decoded_andMatrixOutputs_T_361; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_139 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_215, decoder_decoded_andMatrixOutputs_andMatrixInput_15_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_243, decoder_decoded_andMatrixOutputs_andMatrixInput_13_239}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_340 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_250, decoder_decoded_andMatrixOutputs_lo_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_256, decoder_decoded_andMatrixOutputs_andMatrixInput_11_250}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_302, decoder_decoded_andMatrixOutputs_andMatrixInput_9_262}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_360 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_262, decoder_decoded_andMatrixOutputs_lo_hi_lo_239}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_362 = {decoder_decoded_andMatrixOutputs_lo_hi_360, decoder_decoded_andMatrixOutputs_lo_lo_340}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_215 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_354, decoder_decoded_andMatrixOutputs_andMatrixInput_7_340}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_362, decoder_decoded_andMatrixOutputs_andMatrixInput_5_360}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_354 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_256, decoder_decoded_andMatrixOutputs_hi_lo_lo_215}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_362, decoder_decoded_andMatrixOutputs_andMatrixInput_3_362}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_302 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_362, decoder_decoded_andMatrixOutputs_andMatrixInput_1_362}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_362 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_302, decoder_decoded_andMatrixOutputs_hi_hi_lo_243}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_362 = {decoder_decoded_andMatrixOutputs_hi_hi_362, decoder_decoded_andMatrixOutputs_hi_lo_354}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_362 = {decoder_decoded_andMatrixOutputs_hi_362, decoder_decoded_andMatrixOutputs_lo_362}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_37_2_1 = &_decoder_decoded_andMatrixOutputs_T_362; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_240 = decoder_decoded_plaInput_1[23]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_216 = decoder_decoded_plaInput_1[24]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_28 = decoder_decoded_plaInput_1[24]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_24_15 = decoder_decoded_plaInput_1[24]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_140 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_27, decoder_decoded_andMatrixOutputs_andMatrixInput_21_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_57, decoder_decoded_andMatrixOutputs_andMatrixInput_18_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_251 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_andMatrixInput_19_39}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_341 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_251, decoder_decoded_andMatrixOutputs_lo_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_216, decoder_decoded_andMatrixOutputs_andMatrixInput_15_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_240 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_16_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_251, decoder_decoded_andMatrixOutputs_andMatrixInput_12_244}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_263 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_andMatrixInput_13_240}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_361 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_263, decoder_decoded_andMatrixOutputs_lo_hi_lo_240}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_363 = {decoder_decoded_andMatrixOutputs_lo_hi_361, decoder_decoded_andMatrixOutputs_lo_lo_341}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_216 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_263, decoder_decoded_andMatrixOutputs_andMatrixInput_10_257}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_355, decoder_decoded_andMatrixOutputs_andMatrixInput_7_341}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_257 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_303}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_355 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_257, decoder_decoded_andMatrixOutputs_hi_lo_lo_216}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_363, decoder_decoded_andMatrixOutputs_andMatrixInput_4_363}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_244 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_361}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_83 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_363, decoder_decoded_andMatrixOutputs_andMatrixInput_1_363}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_303 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_83, decoder_decoded_andMatrixOutputs_andMatrixInput_2_363}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_363 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_303, decoder_decoded_andMatrixOutputs_hi_hi_lo_244}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_363 = {decoder_decoded_andMatrixOutputs_hi_hi_363, decoder_decoded_andMatrixOutputs_hi_lo_355}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_363 = {decoder_decoded_andMatrixOutputs_hi_363, decoder_decoded_andMatrixOutputs_lo_363}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_122_2_1 = &_decoder_decoded_andMatrixOutputs_T_363; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_25_14, decoder_decoded_andMatrixOutputs_andMatrixInput_26_14}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_141 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_27_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_23_14, decoder_decoded_andMatrixOutputs_andMatrixInput_24_14}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_21_22, decoder_decoded_andMatrixOutputs_andMatrixInput_22_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_252 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_lo_342 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_252, decoder_decoded_andMatrixOutputs_lo_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_44, decoder_decoded_andMatrixOutputs_andMatrixInput_19_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_241 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_20_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_84, decoder_decoded_andMatrixOutputs_andMatrixInput_17_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_217, decoder_decoded_andMatrixOutputs_andMatrixInput_15_141}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_264 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_hi_362 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_264, decoder_decoded_andMatrixOutputs_lo_hi_lo_241}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_lo_364 = {decoder_decoded_andMatrixOutputs_lo_hi_362, decoder_decoded_andMatrixOutputs_lo_lo_342}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_252, decoder_decoded_andMatrixOutputs_andMatrixInput_12_245}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_217 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_241}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_264, decoder_decoded_andMatrixOutputs_andMatrixInput_10_258}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_342, decoder_decoded_andMatrixOutputs_andMatrixInput_8_304}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_258 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_lo_356 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_258, decoder_decoded_andMatrixOutputs_hi_lo_lo_217}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_364, decoder_decoded_andMatrixOutputs_andMatrixInput_5_362}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_245 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_andMatrixInput_6_356}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_364, decoder_decoded_andMatrixOutputs_andMatrixInput_3_364}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_84 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_364, decoder_decoded_andMatrixOutputs_andMatrixInput_1_364}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_304 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_84, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_hi_364 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_304, decoder_decoded_andMatrixOutputs_hi_hi_lo_245}; // @[pla.scala:98:53] wire [13:0] decoder_decoded_andMatrixOutputs_hi_364 = {decoder_decoded_andMatrixOutputs_hi_hi_364, decoder_decoded_andMatrixOutputs_hi_lo_356}; // @[pla.scala:98:53] wire [27:0] _decoder_decoded_andMatrixOutputs_T_364 = {decoder_decoded_andMatrixOutputs_hi_364, decoder_decoded_andMatrixOutputs_lo_364}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_81_2_1 = &_decoder_decoded_andMatrixOutputs_T_364; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_30_7, decoder_decoded_andMatrixOutputs_andMatrixInput_31_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_28_7, decoder_decoded_andMatrixOutputs_andMatrixInput_29_7}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_142 = {decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_26_15, decoder_decoded_andMatrixOutputs_andMatrixInput_27_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_24_15, decoder_decoded_andMatrixOutputs_andMatrixInput_25_15}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_253 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_lo_343 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_253, decoder_decoded_andMatrixOutputs_lo_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_22_15, decoder_decoded_andMatrixOutputs_andMatrixInput_23_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_29, decoder_decoded_andMatrixOutputs_andMatrixInput_21_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_242 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_45, decoder_decoded_andMatrixOutputs_andMatrixInput_19_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_85, decoder_decoded_andMatrixOutputs_andMatrixInput_17_59}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_265 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_hi_363 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_265, decoder_decoded_andMatrixOutputs_lo_hi_lo_242}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_lo_365 = {decoder_decoded_andMatrixOutputs_lo_hi_363, decoder_decoded_andMatrixOutputs_lo_lo_343}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_218, decoder_decoded_andMatrixOutputs_andMatrixInput_15_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_246, decoder_decoded_andMatrixOutputs_andMatrixInput_13_242}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_218 = {decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_259, decoder_decoded_andMatrixOutputs_andMatrixInput_11_253}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_305, decoder_decoded_andMatrixOutputs_andMatrixInput_9_265}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_259 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_lo_357 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_259, decoder_decoded_andMatrixOutputs_hi_lo_lo_218}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_357, decoder_decoded_andMatrixOutputs_andMatrixInput_7_343}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_365, decoder_decoded_andMatrixOutputs_andMatrixInput_5_363}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_246 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_365, decoder_decoded_andMatrixOutputs_andMatrixInput_3_365}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_85 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_365, decoder_decoded_andMatrixOutputs_andMatrixInput_1_365}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_305 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_85, decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_hi_365 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_305, decoder_decoded_andMatrixOutputs_hi_hi_lo_246}; // @[pla.scala:98:53] wire [15:0] decoder_decoded_andMatrixOutputs_hi_365 = {decoder_decoded_andMatrixOutputs_hi_hi_365, decoder_decoded_andMatrixOutputs_hi_lo_357}; // @[pla.scala:98:53] wire [31:0] _decoder_decoded_andMatrixOutputs_T_365 = {decoder_decoded_andMatrixOutputs_hi_365, decoder_decoded_andMatrixOutputs_lo_365}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_119_2_1 = &_decoder_decoded_andMatrixOutputs_T_365; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_254 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_219 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_220 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_221 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_222 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_143 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_144 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_225 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_226 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_145 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_146 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_147 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_148 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_149 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_42 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_43 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_44 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_45 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_30 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_31 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_32 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_33 = decoder_decoded_plaInput_1[31]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_254 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_266, decoder_decoded_andMatrixOutputs_andMatrixInput_10_260}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_344 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_254, decoder_decoded_andMatrixOutputs_andMatrixInput_11_254}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_358, decoder_decoded_andMatrixOutputs_andMatrixInput_7_344}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_364 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_266, decoder_decoded_andMatrixOutputs_andMatrixInput_8_306}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_366 = {decoder_decoded_andMatrixOutputs_lo_hi_364, decoder_decoded_andMatrixOutputs_lo_lo_344}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_366, decoder_decoded_andMatrixOutputs_andMatrixInput_4_366}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_358 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_260, decoder_decoded_andMatrixOutputs_andMatrixInput_5_364}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_306 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_366, decoder_decoded_andMatrixOutputs_andMatrixInput_1_366}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_366 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_306, decoder_decoded_andMatrixOutputs_andMatrixInput_2_366}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_366 = {decoder_decoded_andMatrixOutputs_hi_hi_366, decoder_decoded_andMatrixOutputs_hi_lo_358}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_366 = {decoder_decoded_andMatrixOutputs_hi_366, decoder_decoded_andMatrixOutputs_lo_366}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_171_2_1 = &_decoder_decoded_andMatrixOutputs_T_366; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_247, decoder_decoded_andMatrixOutputs_andMatrixInput_13_243}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_345 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_255, decoder_decoded_andMatrixOutputs_andMatrixInput_14_219}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_243 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_261, decoder_decoded_andMatrixOutputs_andMatrixInput_11_255}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_267 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_307, decoder_decoded_andMatrixOutputs_andMatrixInput_9_267}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_365 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_267, decoder_decoded_andMatrixOutputs_lo_hi_lo_243}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_367 = {decoder_decoded_andMatrixOutputs_lo_hi_365, decoder_decoded_andMatrixOutputs_lo_lo_345}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_219 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_359, decoder_decoded_andMatrixOutputs_andMatrixInput_7_345}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_367, decoder_decoded_andMatrixOutputs_andMatrixInput_5_365}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_359 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_261, decoder_decoded_andMatrixOutputs_hi_lo_lo_219}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_367, decoder_decoded_andMatrixOutputs_andMatrixInput_3_367}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_307 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_367, decoder_decoded_andMatrixOutputs_andMatrixInput_1_367}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_367 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_307, decoder_decoded_andMatrixOutputs_hi_hi_lo_247}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_367 = {decoder_decoded_andMatrixOutputs_hi_hi_367, decoder_decoded_andMatrixOutputs_hi_lo_359}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_367 = {decoder_decoded_andMatrixOutputs_hi_367, decoder_decoded_andMatrixOutputs_lo_367}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_56_2_1 = &_decoder_decoded_andMatrixOutputs_T_367; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_248, decoder_decoded_andMatrixOutputs_andMatrixInput_13_244}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_346 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_256, decoder_decoded_andMatrixOutputs_andMatrixInput_14_220}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_244 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_262, decoder_decoded_andMatrixOutputs_andMatrixInput_11_256}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_268 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_308, decoder_decoded_andMatrixOutputs_andMatrixInput_9_268}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_366 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_268, decoder_decoded_andMatrixOutputs_lo_hi_lo_244}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_368 = {decoder_decoded_andMatrixOutputs_lo_hi_366, decoder_decoded_andMatrixOutputs_lo_lo_346}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_220 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_360, decoder_decoded_andMatrixOutputs_andMatrixInput_7_346}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_368, decoder_decoded_andMatrixOutputs_andMatrixInput_5_366}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_360 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_262, decoder_decoded_andMatrixOutputs_hi_lo_lo_220}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_368, decoder_decoded_andMatrixOutputs_andMatrixInput_3_368}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_308 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_368, decoder_decoded_andMatrixOutputs_andMatrixInput_1_368}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_368 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_308, decoder_decoded_andMatrixOutputs_hi_hi_lo_248}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_368 = {decoder_decoded_andMatrixOutputs_hi_hi_368, decoder_decoded_andMatrixOutputs_hi_lo_360}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_368 = {decoder_decoded_andMatrixOutputs_hi_368, decoder_decoded_andMatrixOutputs_lo_368}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_79_2_1 = &_decoder_decoded_andMatrixOutputs_T_368; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_257 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_249, decoder_decoded_andMatrixOutputs_andMatrixInput_13_245}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_347 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_257, decoder_decoded_andMatrixOutputs_andMatrixInput_14_221}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_245 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_263, decoder_decoded_andMatrixOutputs_andMatrixInput_11_257}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_269 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_309, decoder_decoded_andMatrixOutputs_andMatrixInput_9_269}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_367 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_269, decoder_decoded_andMatrixOutputs_lo_hi_lo_245}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_369 = {decoder_decoded_andMatrixOutputs_lo_hi_367, decoder_decoded_andMatrixOutputs_lo_lo_347}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_221 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_361, decoder_decoded_andMatrixOutputs_andMatrixInput_7_347}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_369, decoder_decoded_andMatrixOutputs_andMatrixInput_5_367}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_361 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_263, decoder_decoded_andMatrixOutputs_hi_lo_lo_221}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_369, decoder_decoded_andMatrixOutputs_andMatrixInput_3_369}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_309 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_369, decoder_decoded_andMatrixOutputs_andMatrixInput_1_369}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_369 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_309, decoder_decoded_andMatrixOutputs_hi_hi_lo_249}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_369 = {decoder_decoded_andMatrixOutputs_hi_hi_369, decoder_decoded_andMatrixOutputs_hi_lo_361}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_369 = {decoder_decoded_andMatrixOutputs_hi_369, decoder_decoded_andMatrixOutputs_lo_369}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_168_2_1 = &_decoder_decoded_andMatrixOutputs_T_369; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_258 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_250, decoder_decoded_andMatrixOutputs_andMatrixInput_13_246}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_348 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_258, decoder_decoded_andMatrixOutputs_andMatrixInput_14_222}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_246 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_264, decoder_decoded_andMatrixOutputs_andMatrixInput_11_258}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_270 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_310, decoder_decoded_andMatrixOutputs_andMatrixInput_9_270}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_368 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_270, decoder_decoded_andMatrixOutputs_lo_hi_lo_246}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_370 = {decoder_decoded_andMatrixOutputs_lo_hi_368, decoder_decoded_andMatrixOutputs_lo_lo_348}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_222 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_362, decoder_decoded_andMatrixOutputs_andMatrixInput_7_348}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_264 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_370, decoder_decoded_andMatrixOutputs_andMatrixInput_5_368}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_362 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_264, decoder_decoded_andMatrixOutputs_hi_lo_lo_222}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_370, decoder_decoded_andMatrixOutputs_andMatrixInput_3_370}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_310 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_370, decoder_decoded_andMatrixOutputs_andMatrixInput_1_370}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_370 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_310, decoder_decoded_andMatrixOutputs_hi_hi_lo_250}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_370 = {decoder_decoded_andMatrixOutputs_hi_hi_370, decoder_decoded_andMatrixOutputs_hi_lo_362}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_370 = {decoder_decoded_andMatrixOutputs_hi_370, decoder_decoded_andMatrixOutputs_lo_370}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_154_2_1 = &_decoder_decoded_andMatrixOutputs_T_370; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_143 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_223, decoder_decoded_andMatrixOutputs_andMatrixInput_15_143}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_259 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_251, decoder_decoded_andMatrixOutputs_andMatrixInput_13_247}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_349 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_259, decoder_decoded_andMatrixOutputs_lo_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_247 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_265, decoder_decoded_andMatrixOutputs_andMatrixInput_11_259}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_271 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_311, decoder_decoded_andMatrixOutputs_andMatrixInput_9_271}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_369 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_271, decoder_decoded_andMatrixOutputs_lo_hi_lo_247}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_371 = {decoder_decoded_andMatrixOutputs_lo_hi_369, decoder_decoded_andMatrixOutputs_lo_lo_349}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_223 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_363, decoder_decoded_andMatrixOutputs_andMatrixInput_7_349}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_265 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_371, decoder_decoded_andMatrixOutputs_andMatrixInput_5_369}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_363 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_265, decoder_decoded_andMatrixOutputs_hi_lo_lo_223}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_251 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_371, decoder_decoded_andMatrixOutputs_andMatrixInput_3_371}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_311 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_371, decoder_decoded_andMatrixOutputs_andMatrixInput_1_371}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_371 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_311, decoder_decoded_andMatrixOutputs_hi_hi_lo_251}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_371 = {decoder_decoded_andMatrixOutputs_hi_hi_371, decoder_decoded_andMatrixOutputs_hi_lo_363}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_371 = {decoder_decoded_andMatrixOutputs_hi_371, decoder_decoded_andMatrixOutputs_lo_371}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_192_2_1 = &_decoder_decoded_andMatrixOutputs_T_371; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_144 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_224, decoder_decoded_andMatrixOutputs_andMatrixInput_15_144}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_252, decoder_decoded_andMatrixOutputs_andMatrixInput_13_248}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_350 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_260, decoder_decoded_andMatrixOutputs_lo_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_248 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_266, decoder_decoded_andMatrixOutputs_andMatrixInput_11_260}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_272 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_312, decoder_decoded_andMatrixOutputs_andMatrixInput_9_272}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_370 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_272, decoder_decoded_andMatrixOutputs_lo_hi_lo_248}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_372 = {decoder_decoded_andMatrixOutputs_lo_hi_370, decoder_decoded_andMatrixOutputs_lo_lo_350}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_224 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_364, decoder_decoded_andMatrixOutputs_andMatrixInput_7_350}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_372, decoder_decoded_andMatrixOutputs_andMatrixInput_5_370}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_364 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_266, decoder_decoded_andMatrixOutputs_hi_lo_lo_224}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_372, decoder_decoded_andMatrixOutputs_andMatrixInput_3_372}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_312 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_372, decoder_decoded_andMatrixOutputs_andMatrixInput_1_372}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_372 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_312, decoder_decoded_andMatrixOutputs_hi_hi_lo_252}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_372 = {decoder_decoded_andMatrixOutputs_hi_hi_372, decoder_decoded_andMatrixOutputs_hi_lo_364}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_372 = {decoder_decoded_andMatrixOutputs_hi_372, decoder_decoded_andMatrixOutputs_lo_372}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_38_2_1 = &_decoder_decoded_andMatrixOutputs_T_372; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_253, decoder_decoded_andMatrixOutputs_andMatrixInput_13_249}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_351 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_261, decoder_decoded_andMatrixOutputs_andMatrixInput_14_225}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_249 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_267, decoder_decoded_andMatrixOutputs_andMatrixInput_11_261}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_273 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_313, decoder_decoded_andMatrixOutputs_andMatrixInput_9_273}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_371 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_273, decoder_decoded_andMatrixOutputs_lo_hi_lo_249}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_373 = {decoder_decoded_andMatrixOutputs_lo_hi_371, decoder_decoded_andMatrixOutputs_lo_lo_351}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_225 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_365, decoder_decoded_andMatrixOutputs_andMatrixInput_7_351}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_267 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_373, decoder_decoded_andMatrixOutputs_andMatrixInput_5_371}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_365 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_267, decoder_decoded_andMatrixOutputs_hi_lo_lo_225}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_253 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_373, decoder_decoded_andMatrixOutputs_andMatrixInput_3_373}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_313 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_373, decoder_decoded_andMatrixOutputs_andMatrixInput_1_373}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_373 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_313, decoder_decoded_andMatrixOutputs_hi_hi_lo_253}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_373 = {decoder_decoded_andMatrixOutputs_hi_hi_373, decoder_decoded_andMatrixOutputs_hi_lo_365}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_373 = {decoder_decoded_andMatrixOutputs_hi_373, decoder_decoded_andMatrixOutputs_lo_373}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_158_2_1 = &_decoder_decoded_andMatrixOutputs_T_373; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_254, decoder_decoded_andMatrixOutputs_andMatrixInput_13_250}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_352 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_262, decoder_decoded_andMatrixOutputs_andMatrixInput_14_226}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_250 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_268, decoder_decoded_andMatrixOutputs_andMatrixInput_11_262}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_274 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_314, decoder_decoded_andMatrixOutputs_andMatrixInput_9_274}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_372 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_274, decoder_decoded_andMatrixOutputs_lo_hi_lo_250}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_374 = {decoder_decoded_andMatrixOutputs_lo_hi_372, decoder_decoded_andMatrixOutputs_lo_lo_352}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_226 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_366, decoder_decoded_andMatrixOutputs_andMatrixInput_7_352}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_268 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_374, decoder_decoded_andMatrixOutputs_andMatrixInput_5_372}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_366 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_268, decoder_decoded_andMatrixOutputs_hi_lo_lo_226}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_254 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_374, decoder_decoded_andMatrixOutputs_andMatrixInput_3_374}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_314 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_374, decoder_decoded_andMatrixOutputs_andMatrixInput_1_374}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_374 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_314, decoder_decoded_andMatrixOutputs_hi_hi_lo_254}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_374 = {decoder_decoded_andMatrixOutputs_hi_hi_374, decoder_decoded_andMatrixOutputs_hi_lo_366}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_374 = {decoder_decoded_andMatrixOutputs_hi_374, decoder_decoded_andMatrixOutputs_lo_374}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_109_2_1 = &_decoder_decoded_andMatrixOutputs_T_374; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_145 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_227, decoder_decoded_andMatrixOutputs_andMatrixInput_15_145}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_255, decoder_decoded_andMatrixOutputs_andMatrixInput_13_251}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_353 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_263, decoder_decoded_andMatrixOutputs_lo_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_251 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_269, decoder_decoded_andMatrixOutputs_andMatrixInput_11_263}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_275 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_315, decoder_decoded_andMatrixOutputs_andMatrixInput_9_275}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_373 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_275, decoder_decoded_andMatrixOutputs_lo_hi_lo_251}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_375 = {decoder_decoded_andMatrixOutputs_lo_hi_373, decoder_decoded_andMatrixOutputs_lo_lo_353}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_227 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_367, decoder_decoded_andMatrixOutputs_andMatrixInput_7_353}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_269 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_375, decoder_decoded_andMatrixOutputs_andMatrixInput_5_373}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_367 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_269, decoder_decoded_andMatrixOutputs_hi_lo_lo_227}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_375, decoder_decoded_andMatrixOutputs_andMatrixInput_3_375}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_315 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_375, decoder_decoded_andMatrixOutputs_andMatrixInput_1_375}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_375 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_315, decoder_decoded_andMatrixOutputs_hi_hi_lo_255}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_375 = {decoder_decoded_andMatrixOutputs_hi_hi_375, decoder_decoded_andMatrixOutputs_hi_lo_367}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_375 = {decoder_decoded_andMatrixOutputs_hi_375, decoder_decoded_andMatrixOutputs_lo_375}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_23_2_1 = &_decoder_decoded_andMatrixOutputs_T_375; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_146 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_228, decoder_decoded_andMatrixOutputs_andMatrixInput_15_146}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_264 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_256, decoder_decoded_andMatrixOutputs_andMatrixInput_13_252}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_354 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_264, decoder_decoded_andMatrixOutputs_lo_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_252 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_270, decoder_decoded_andMatrixOutputs_andMatrixInput_11_264}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_276 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_316, decoder_decoded_andMatrixOutputs_andMatrixInput_9_276}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_374 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_276, decoder_decoded_andMatrixOutputs_lo_hi_lo_252}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_376 = {decoder_decoded_andMatrixOutputs_lo_hi_374, decoder_decoded_andMatrixOutputs_lo_lo_354}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_228 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_368, decoder_decoded_andMatrixOutputs_andMatrixInput_7_354}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_270 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_376, decoder_decoded_andMatrixOutputs_andMatrixInput_5_374}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_368 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_270, decoder_decoded_andMatrixOutputs_hi_lo_lo_228}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_376, decoder_decoded_andMatrixOutputs_andMatrixInput_3_376}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_316 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_376, decoder_decoded_andMatrixOutputs_andMatrixInput_1_376}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_376 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_316, decoder_decoded_andMatrixOutputs_hi_hi_lo_256}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_376 = {decoder_decoded_andMatrixOutputs_hi_hi_376, decoder_decoded_andMatrixOutputs_hi_lo_368}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_376 = {decoder_decoded_andMatrixOutputs_hi_376, decoder_decoded_andMatrixOutputs_lo_376}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_100_2_1 = &_decoder_decoded_andMatrixOutputs_T_376; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_147 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_229, decoder_decoded_andMatrixOutputs_andMatrixInput_15_147}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_265 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_257, decoder_decoded_andMatrixOutputs_andMatrixInput_13_253}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_355 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_265, decoder_decoded_andMatrixOutputs_lo_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_253 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_271, decoder_decoded_andMatrixOutputs_andMatrixInput_11_265}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_277 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_317, decoder_decoded_andMatrixOutputs_andMatrixInput_9_277}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_375 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_277, decoder_decoded_andMatrixOutputs_lo_hi_lo_253}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_377 = {decoder_decoded_andMatrixOutputs_lo_hi_375, decoder_decoded_andMatrixOutputs_lo_lo_355}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_229 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_369, decoder_decoded_andMatrixOutputs_andMatrixInput_7_355}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_271 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_377, decoder_decoded_andMatrixOutputs_andMatrixInput_5_375}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_369 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_271, decoder_decoded_andMatrixOutputs_hi_lo_lo_229}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_257 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_377, decoder_decoded_andMatrixOutputs_andMatrixInput_3_377}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_317 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_377, decoder_decoded_andMatrixOutputs_andMatrixInput_1_377}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_377 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_317, decoder_decoded_andMatrixOutputs_hi_hi_lo_257}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_377 = {decoder_decoded_andMatrixOutputs_hi_hi_377, decoder_decoded_andMatrixOutputs_hi_lo_369}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_377 = {decoder_decoded_andMatrixOutputs_hi_377, decoder_decoded_andMatrixOutputs_lo_377}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_118_2_1 = &_decoder_decoded_andMatrixOutputs_T_377; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_148 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_230, decoder_decoded_andMatrixOutputs_andMatrixInput_15_148}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_266 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_258, decoder_decoded_andMatrixOutputs_andMatrixInput_13_254}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_356 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_266, decoder_decoded_andMatrixOutputs_lo_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_254 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_272, decoder_decoded_andMatrixOutputs_andMatrixInput_11_266}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_278 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_318, decoder_decoded_andMatrixOutputs_andMatrixInput_9_278}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_376 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_278, decoder_decoded_andMatrixOutputs_lo_hi_lo_254}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_378 = {decoder_decoded_andMatrixOutputs_lo_hi_376, decoder_decoded_andMatrixOutputs_lo_lo_356}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_230 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_370, decoder_decoded_andMatrixOutputs_andMatrixInput_7_356}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_272 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_378, decoder_decoded_andMatrixOutputs_andMatrixInput_5_376}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_370 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_272, decoder_decoded_andMatrixOutputs_hi_lo_lo_230}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_258 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_378, decoder_decoded_andMatrixOutputs_andMatrixInput_3_378}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_318 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_378, decoder_decoded_andMatrixOutputs_andMatrixInput_1_378}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_378 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_318, decoder_decoded_andMatrixOutputs_hi_hi_lo_258}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_378 = {decoder_decoded_andMatrixOutputs_hi_hi_378, decoder_decoded_andMatrixOutputs_hi_lo_370}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_378 = {decoder_decoded_andMatrixOutputs_hi_378, decoder_decoded_andMatrixOutputs_lo_378}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_116_2_1 = &_decoder_decoded_andMatrixOutputs_T_378; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_149 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_231, decoder_decoded_andMatrixOutputs_andMatrixInput_15_149}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_267 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_259, decoder_decoded_andMatrixOutputs_andMatrixInput_13_255}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_357 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_267, decoder_decoded_andMatrixOutputs_lo_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_255 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_273, decoder_decoded_andMatrixOutputs_andMatrixInput_11_267}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_279 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_319, decoder_decoded_andMatrixOutputs_andMatrixInput_9_279}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_377 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_279, decoder_decoded_andMatrixOutputs_lo_hi_lo_255}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_379 = {decoder_decoded_andMatrixOutputs_lo_hi_377, decoder_decoded_andMatrixOutputs_lo_lo_357}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_231 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_371, decoder_decoded_andMatrixOutputs_andMatrixInput_7_357}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_273 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_379, decoder_decoded_andMatrixOutputs_andMatrixInput_5_377}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_371 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_273, decoder_decoded_andMatrixOutputs_hi_lo_lo_231}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_259 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_379, decoder_decoded_andMatrixOutputs_andMatrixInput_3_379}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_319 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_379, decoder_decoded_andMatrixOutputs_andMatrixInput_1_379}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_379 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_319, decoder_decoded_andMatrixOutputs_hi_hi_lo_259}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_379 = {decoder_decoded_andMatrixOutputs_hi_hi_379, decoder_decoded_andMatrixOutputs_hi_lo_371}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_379 = {decoder_decoded_andMatrixOutputs_hi_379, decoder_decoded_andMatrixOutputs_lo_379}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_156_2_1 = &_decoder_decoded_andMatrixOutputs_T_379; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_150 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_46, decoder_decoded_andMatrixOutputs_andMatrixInput_19_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_150, decoder_decoded_andMatrixOutputs_andMatrixInput_16_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_268 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_17_60}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_358 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_268, decoder_decoded_andMatrixOutputs_lo_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_256 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_256, decoder_decoded_andMatrixOutputs_andMatrixInput_14_232}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_274, decoder_decoded_andMatrixOutputs_andMatrixInput_11_268}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_280 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_260}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_378 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_280, decoder_decoded_andMatrixOutputs_lo_hi_lo_256}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_380 = {decoder_decoded_andMatrixOutputs_lo_hi_378, decoder_decoded_andMatrixOutputs_lo_lo_358}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_232 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_320, decoder_decoded_andMatrixOutputs_andMatrixInput_9_280}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_378, decoder_decoded_andMatrixOutputs_andMatrixInput_6_372}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_274 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_7_358}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_372 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_274, decoder_decoded_andMatrixOutputs_hi_lo_lo_232}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_380, decoder_decoded_andMatrixOutputs_andMatrixInput_4_380}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_86 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_380, decoder_decoded_andMatrixOutputs_andMatrixInput_1_380}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_320 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_86, decoder_decoded_andMatrixOutputs_andMatrixInput_2_380}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_380 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_320, decoder_decoded_andMatrixOutputs_hi_hi_lo_260}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_380 = {decoder_decoded_andMatrixOutputs_hi_hi_380, decoder_decoded_andMatrixOutputs_hi_lo_372}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_380 = {decoder_decoded_andMatrixOutputs_hi_380, decoder_decoded_andMatrixOutputs_lo_380}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_113_2_1 = &_decoder_decoded_andMatrixOutputs_T_380; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_151 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_47, decoder_decoded_andMatrixOutputs_andMatrixInput_19_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_151, decoder_decoded_andMatrixOutputs_andMatrixInput_16_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_269 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_17_61}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_359 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_269, decoder_decoded_andMatrixOutputs_lo_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_257 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_257, decoder_decoded_andMatrixOutputs_andMatrixInput_14_233}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_275, decoder_decoded_andMatrixOutputs_andMatrixInput_11_269}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_281 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_261}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_379 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_281, decoder_decoded_andMatrixOutputs_lo_hi_lo_257}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_381 = {decoder_decoded_andMatrixOutputs_lo_hi_379, decoder_decoded_andMatrixOutputs_lo_lo_359}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_233 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_321, decoder_decoded_andMatrixOutputs_andMatrixInput_9_281}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_379, decoder_decoded_andMatrixOutputs_andMatrixInput_6_373}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_275 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_7_359}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_373 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_275, decoder_decoded_andMatrixOutputs_hi_lo_lo_233}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_381, decoder_decoded_andMatrixOutputs_andMatrixInput_4_381}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_87 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_381, decoder_decoded_andMatrixOutputs_andMatrixInput_1_381}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_321 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_87, decoder_decoded_andMatrixOutputs_andMatrixInput_2_381}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_381 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_321, decoder_decoded_andMatrixOutputs_hi_hi_lo_261}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_381 = {decoder_decoded_andMatrixOutputs_hi_hi_381, decoder_decoded_andMatrixOutputs_hi_lo_373}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_381 = {decoder_decoded_andMatrixOutputs_hi_381, decoder_decoded_andMatrixOutputs_lo_381}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_105_2_1 = &_decoder_decoded_andMatrixOutputs_T_381; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_152 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_48, decoder_decoded_andMatrixOutputs_andMatrixInput_19_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_152, decoder_decoded_andMatrixOutputs_andMatrixInput_16_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_270 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_17_62}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_360 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_270, decoder_decoded_andMatrixOutputs_lo_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_258 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_258, decoder_decoded_andMatrixOutputs_andMatrixInput_14_234}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_276, decoder_decoded_andMatrixOutputs_andMatrixInput_11_270}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_282 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_262}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_380 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_282, decoder_decoded_andMatrixOutputs_lo_hi_lo_258}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_382 = {decoder_decoded_andMatrixOutputs_lo_hi_380, decoder_decoded_andMatrixOutputs_lo_lo_360}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_234 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_322, decoder_decoded_andMatrixOutputs_andMatrixInput_9_282}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_380, decoder_decoded_andMatrixOutputs_andMatrixInput_6_374}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_276 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_7_360}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_374 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_276, decoder_decoded_andMatrixOutputs_hi_lo_lo_234}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_382, decoder_decoded_andMatrixOutputs_andMatrixInput_4_382}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_88 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_382, decoder_decoded_andMatrixOutputs_andMatrixInput_1_382}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_322 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_88, decoder_decoded_andMatrixOutputs_andMatrixInput_2_382}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_382 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_322, decoder_decoded_andMatrixOutputs_hi_hi_lo_262}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_382 = {decoder_decoded_andMatrixOutputs_hi_hi_382, decoder_decoded_andMatrixOutputs_hi_lo_374}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_382 = {decoder_decoded_andMatrixOutputs_hi_382, decoder_decoded_andMatrixOutputs_lo_382}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_83_2_1 = &_decoder_decoded_andMatrixOutputs_T_382; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_153 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_49, decoder_decoded_andMatrixOutputs_andMatrixInput_19_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_153, decoder_decoded_andMatrixOutputs_andMatrixInput_16_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_271 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_17_63}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_361 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_271, decoder_decoded_andMatrixOutputs_lo_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_259 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_259, decoder_decoded_andMatrixOutputs_andMatrixInput_14_235}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_277, decoder_decoded_andMatrixOutputs_andMatrixInput_11_271}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_283 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_263}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_381 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_283, decoder_decoded_andMatrixOutputs_lo_hi_lo_259}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_383 = {decoder_decoded_andMatrixOutputs_lo_hi_381, decoder_decoded_andMatrixOutputs_lo_lo_361}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_235 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_323, decoder_decoded_andMatrixOutputs_andMatrixInput_9_283}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_381, decoder_decoded_andMatrixOutputs_andMatrixInput_6_375}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_277 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_7_361}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_375 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_277, decoder_decoded_andMatrixOutputs_hi_lo_lo_235}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_383, decoder_decoded_andMatrixOutputs_andMatrixInput_4_383}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_89 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_383, decoder_decoded_andMatrixOutputs_andMatrixInput_1_383}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_323 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_89, decoder_decoded_andMatrixOutputs_andMatrixInput_2_383}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_383 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_323, decoder_decoded_andMatrixOutputs_hi_hi_lo_263}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_383 = {decoder_decoded_andMatrixOutputs_hi_hi_383, decoder_decoded_andMatrixOutputs_hi_lo_375}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_383 = {decoder_decoded_andMatrixOutputs_hi_383, decoder_decoded_andMatrixOutputs_lo_383}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_33_2_1 = &_decoder_decoded_andMatrixOutputs_T_383; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_154 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_46, decoder_decoded_andMatrixOutputs_andMatrixInput_20_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_90, decoder_decoded_andMatrixOutputs_andMatrixInput_17_64}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_272 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_andMatrixInput_18_50}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_362 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_272, decoder_decoded_andMatrixOutputs_lo_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_260 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_236, decoder_decoded_andMatrixOutputs_andMatrixInput_15_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_272, decoder_decoded_andMatrixOutputs_andMatrixInput_12_264}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_284 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_andMatrixInput_13_260}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_382 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_284, decoder_decoded_andMatrixOutputs_lo_hi_lo_260}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_384 = {decoder_decoded_andMatrixOutputs_lo_hi_382, decoder_decoded_andMatrixOutputs_lo_lo_362}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_236 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_284, decoder_decoded_andMatrixOutputs_andMatrixInput_10_278}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_376, decoder_decoded_andMatrixOutputs_andMatrixInput_7_362}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_278 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_andMatrixInput_8_324}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_376 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_278, decoder_decoded_andMatrixOutputs_hi_lo_lo_236}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_384, decoder_decoded_andMatrixOutputs_andMatrixInput_4_384}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_264 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_382}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_90 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_384, decoder_decoded_andMatrixOutputs_andMatrixInput_1_384}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_324 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_90, decoder_decoded_andMatrixOutputs_andMatrixInput_2_384}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_384 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_324, decoder_decoded_andMatrixOutputs_hi_hi_lo_264}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_384 = {decoder_decoded_andMatrixOutputs_hi_hi_384, decoder_decoded_andMatrixOutputs_hi_lo_376}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_384 = {decoder_decoded_andMatrixOutputs_hi_384, decoder_decoded_andMatrixOutputs_lo_384}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_84_2_1 = &_decoder_decoded_andMatrixOutputs_T_384; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_155 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_47, decoder_decoded_andMatrixOutputs_andMatrixInput_20_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_91, decoder_decoded_andMatrixOutputs_andMatrixInput_17_65}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_273 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_andMatrixInput_18_51}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_363 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_273, decoder_decoded_andMatrixOutputs_lo_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_261 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_237, decoder_decoded_andMatrixOutputs_andMatrixInput_15_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_273, decoder_decoded_andMatrixOutputs_andMatrixInput_12_265}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_285 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_andMatrixInput_13_261}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_383 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_285, decoder_decoded_andMatrixOutputs_lo_hi_lo_261}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_385 = {decoder_decoded_andMatrixOutputs_lo_hi_383, decoder_decoded_andMatrixOutputs_lo_lo_363}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_237 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_285, decoder_decoded_andMatrixOutputs_andMatrixInput_10_279}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_377, decoder_decoded_andMatrixOutputs_andMatrixInput_7_363}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_279 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_andMatrixInput_8_325}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_377 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_279, decoder_decoded_andMatrixOutputs_hi_lo_lo_237}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_385, decoder_decoded_andMatrixOutputs_andMatrixInput_4_385}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_265 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_383}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_91 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_385, decoder_decoded_andMatrixOutputs_andMatrixInput_1_385}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_325 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_91, decoder_decoded_andMatrixOutputs_andMatrixInput_2_385}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_385 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_325, decoder_decoded_andMatrixOutputs_hi_hi_lo_265}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_385 = {decoder_decoded_andMatrixOutputs_hi_hi_385, decoder_decoded_andMatrixOutputs_hi_lo_377}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_385 = {decoder_decoded_andMatrixOutputs_hi_385, decoder_decoded_andMatrixOutputs_lo_385}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_40_2_1 = &_decoder_decoded_andMatrixOutputs_T_385; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_156 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_48, decoder_decoded_andMatrixOutputs_andMatrixInput_20_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_92, decoder_decoded_andMatrixOutputs_andMatrixInput_17_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_274 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_andMatrixInput_18_52}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_364 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_274, decoder_decoded_andMatrixOutputs_lo_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_262 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_238, decoder_decoded_andMatrixOutputs_andMatrixInput_15_156}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_274, decoder_decoded_andMatrixOutputs_andMatrixInput_12_266}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_286 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_andMatrixInput_13_262}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_384 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_286, decoder_decoded_andMatrixOutputs_lo_hi_lo_262}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_386 = {decoder_decoded_andMatrixOutputs_lo_hi_384, decoder_decoded_andMatrixOutputs_lo_lo_364}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_238 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_286, decoder_decoded_andMatrixOutputs_andMatrixInput_10_280}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_378, decoder_decoded_andMatrixOutputs_andMatrixInput_7_364}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_280 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_andMatrixInput_8_326}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_378 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_280, decoder_decoded_andMatrixOutputs_hi_lo_lo_238}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_386, decoder_decoded_andMatrixOutputs_andMatrixInput_4_386}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_266 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_384}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_92 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_386, decoder_decoded_andMatrixOutputs_andMatrixInput_1_386}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_326 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_92, decoder_decoded_andMatrixOutputs_andMatrixInput_2_386}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_386 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_326, decoder_decoded_andMatrixOutputs_hi_hi_lo_266}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_386 = {decoder_decoded_andMatrixOutputs_hi_hi_386, decoder_decoded_andMatrixOutputs_hi_lo_378}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_386 = {decoder_decoded_andMatrixOutputs_hi_386, decoder_decoded_andMatrixOutputs_lo_386}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_12_2_1 = &_decoder_decoded_andMatrixOutputs_T_386; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_157 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_49, decoder_decoded_andMatrixOutputs_andMatrixInput_20_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_93, decoder_decoded_andMatrixOutputs_andMatrixInput_17_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_275 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_andMatrixInput_18_53}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_365 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_275, decoder_decoded_andMatrixOutputs_lo_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_263 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_239, decoder_decoded_andMatrixOutputs_andMatrixInput_15_157}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_275, decoder_decoded_andMatrixOutputs_andMatrixInput_12_267}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_287 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_andMatrixInput_13_263}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_385 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_287, decoder_decoded_andMatrixOutputs_lo_hi_lo_263}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_387 = {decoder_decoded_andMatrixOutputs_lo_hi_385, decoder_decoded_andMatrixOutputs_lo_lo_365}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_239 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_287, decoder_decoded_andMatrixOutputs_andMatrixInput_10_281}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_379, decoder_decoded_andMatrixOutputs_andMatrixInput_7_365}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_281 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_andMatrixInput_8_327}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_379 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_281, decoder_decoded_andMatrixOutputs_hi_lo_lo_239}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_387, decoder_decoded_andMatrixOutputs_andMatrixInput_4_387}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_267 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_385}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_93 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_387, decoder_decoded_andMatrixOutputs_andMatrixInput_1_387}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_327 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_93, decoder_decoded_andMatrixOutputs_andMatrixInput_2_387}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_387 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_327, decoder_decoded_andMatrixOutputs_hi_hi_lo_267}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_387 = {decoder_decoded_andMatrixOutputs_hi_hi_387, decoder_decoded_andMatrixOutputs_hi_lo_379}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_387 = {decoder_decoded_andMatrixOutputs_hi_387, decoder_decoded_andMatrixOutputs_lo_387}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_74_2_1 = &_decoder_decoded_andMatrixOutputs_T_387; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_18 = {decoder_decoded_andMatrixOutputs_118_2_1, decoder_decoded_andMatrixOutputs_84_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_21 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_40_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_114_2_1, decoder_decoded_andMatrixOutputs_175_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_23 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_127_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_27 = {decoder_decoded_orMatrixOutputs_lo_hi_23, decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_85_2_1, decoder_decoded_andMatrixOutputs_10_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_22 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_92_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_148_2_1, decoder_decoded_andMatrixOutputs_75_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_24 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_86_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_29 = {decoder_decoded_orMatrixOutputs_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19] wire [11:0] _decoder_decoded_orMatrixOutputs_T_72 = {decoder_decoded_orMatrixOutputs_hi_29, decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_73 = |_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_36 = {decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_0_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_30; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_30 = _GEN_36; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_29; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_29 = _GEN_36; // @[pla.scala:114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_74 = {decoder_decoded_orMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_137_2_1}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_75 = |_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_24 = {decoder_decoded_andMatrixOutputs_161_2_1, decoder_decoded_andMatrixOutputs_82_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_28 = {decoder_decoded_orMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_81_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_23 = {decoder_decoded_andMatrixOutputs_155_2_1, decoder_decoded_andMatrixOutputs_58_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_54_2_1, decoder_decoded_andMatrixOutputs_185_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_31 = {decoder_decoded_orMatrixOutputs_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19] wire [6:0] _decoder_decoded_orMatrixOutputs_T_80 = {decoder_decoded_orMatrixOutputs_hi_31, decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_81 = |_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_37 = {decoder_decoded_andMatrixOutputs_83_2_1, decoder_decoded_andMatrixOutputs_33_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_7 = _GEN_37; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_16; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_16 = _GEN_37; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_1 = _GEN_37; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_154_2_1, decoder_decoded_andMatrixOutputs_23_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_100_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_14 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_56_2_1, decoder_decoded_andMatrixOutputs_79_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_168_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_99_2_1, decoder_decoded_andMatrixOutputs_88_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_11 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_19 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_11, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_22 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_68_2_1, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_1_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_38 = {decoder_decoded_andMatrixOutputs_51_2_1, decoder_decoded_andMatrixOutputs_174_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_5 = _GEN_38; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_9 = _GEN_38; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_11 = _GEN_38; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_42_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_16 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_39 = {decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_135_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_5 = _GEN_39; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_29; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_29 = _GEN_39; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_6 = _GEN_39; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_52; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_52 = _GEN_39; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_7 = _GEN_39; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_8 = _GEN_39; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_188_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_137_2_1, decoder_decoded_andMatrixOutputs_159_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_14 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_34_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_lo_hi_25 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:114:19] wire [22:0] decoder_decoded_orMatrixOutputs_lo_29 = {decoder_decoded_orMatrixOutputs_lo_hi_25, decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:114:19] wire [1:0] _GEN_40 = {decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_59_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_7 = _GEN_40; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_9 = _GEN_40; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_11 = _GEN_40; // @[pla.scala:114:19] wire [1:0] _GEN_41 = {decoder_decoded_andMatrixOutputs_41_2_1, decoder_decoded_andMatrixOutputs_8_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_5 = _GEN_41; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_24; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_24 = _GEN_41; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_8 = _GEN_41; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_15 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_42 = {decoder_decoded_andMatrixOutputs_14_2_1, decoder_decoded_andMatrixOutputs_155_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_4 = _GEN_42; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_7 = _GEN_42; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_126_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_103_2_1, decoder_decoded_andMatrixOutputs_185_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_13 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_17_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_24 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_191_2_1, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_7 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_121_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_43 = {decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_97_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_5 = _GEN_43; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_18; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_18 = _GEN_43; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1 = _GEN_43; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_70_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_17 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_44 = {decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_35_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_5 = _GEN_44; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_12; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_12 = _GEN_44; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_190_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_45 = {decoder_decoded_andMatrixOutputs_98_2_1, decoder_decoded_andMatrixOutputs_9_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_7 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_8 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_19; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_19 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_9 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_21; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_21 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_10 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_11 = _GEN_45; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_1 = _GEN_45; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_14 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_139_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_8}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_hi_hi_26 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:114:19] wire [22:0] decoder_decoded_orMatrixOutputs_hi_32 = {decoder_decoded_orMatrixOutputs_hi_hi_26, decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19] wire [45:0] _decoder_decoded_orMatrixOutputs_T_82 = {decoder_decoded_orMatrixOutputs_hi_32, decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_83 = |_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_85 = {decoder_decoded_andMatrixOutputs_167_2_1, decoder_decoded_andMatrixOutputs_108_2_1}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_86 = |_decoder_decoded_orMatrixOutputs_T_85; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_46 = {decoder_decoded_andMatrixOutputs_12_2_1, decoder_decoded_andMatrixOutputs_74_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_15; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_15 = _GEN_46; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_9 = _GEN_46; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_11 = _GEN_46; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_20 = {decoder_decoded_andMatrixOutputs_116_2_1, decoder_decoded_andMatrixOutputs_156_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_23 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] _GEN_47 = {decoder_decoded_andMatrixOutputs_50_2_1, decoder_decoded_andMatrixOutputs_136_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_17; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_17 = _GEN_47; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_18; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_18 = _GEN_47; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1 = _GEN_47; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_71_2_1, decoder_decoded_andMatrixOutputs_80_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_22 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_157_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_26 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_22, decoder_decoded_orMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_30 = {decoder_decoded_orMatrixOutputs_lo_hi_26, decoder_decoded_orMatrixOutputs_lo_lo_23}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_16 = {decoder_decoded_andMatrixOutputs_46_2_1, decoder_decoded_andMatrixOutputs_114_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_48 = {decoder_decoded_andMatrixOutputs_153_2_1, decoder_decoded_andMatrixOutputs_107_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_14; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_14 = _GEN_48; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_27; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_27 = _GEN_48; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_8 = _GEN_48; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_21 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_187_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_25 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_18 = {decoder_decoded_andMatrixOutputs_76_2_1, decoder_decoded_andMatrixOutputs_91_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_49 = {decoder_decoded_andMatrixOutputs_181_2_1, decoder_decoded_andMatrixOutputs_20_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_15; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_15 = _GEN_49; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_24; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_24 = _GEN_49; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_16; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_16 = _GEN_49; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_25; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_25 = _GEN_49; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_22_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_27 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_33 = {decoder_decoded_orMatrixOutputs_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_87 = {decoder_decoded_orMatrixOutputs_hi_33, decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_88 = |_decoder_decoded_orMatrixOutputs_T_87; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_21 = {decoder_decoded_andMatrixOutputs_107_2_1, decoder_decoded_andMatrixOutputs_50_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_24 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_136_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_50 = {decoder_decoded_andMatrixOutputs_6_2_1, decoder_decoded_andMatrixOutputs_134_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_23; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_23 = _GEN_50; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_15; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_15 = _GEN_50; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1 = _GEN_50; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_27 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_153_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_31 = {decoder_decoded_orMatrixOutputs_lo_hi_27, decoder_decoded_orMatrixOutputs_lo_lo_24}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_123_2_1, decoder_decoded_andMatrixOutputs_124_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_26 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_49_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_19 = {decoder_decoded_andMatrixOutputs_22_2_1, decoder_decoded_andMatrixOutputs_160_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_28 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_34 = {decoder_decoded_orMatrixOutputs_hi_hi_28, decoder_decoded_orMatrixOutputs_hi_lo_26}; // @[pla.scala:114:19] wire [12:0] _decoder_decoded_orMatrixOutputs_T_90 = {decoder_decoded_orMatrixOutputs_hi_34, decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_91 = |_decoder_decoded_orMatrixOutputs_T_90; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_22 = {decoder_decoded_andMatrixOutputs_23_2_1, decoder_decoded_andMatrixOutputs_100_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_25 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_22, decoder_decoded_orMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:114:19] wire [1:0] _GEN_51 = {decoder_decoded_andMatrixOutputs_69_2_1, decoder_decoded_andMatrixOutputs_175_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_16; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_16 = _GEN_51; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_1 = _GEN_51; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_24 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_130_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_28 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_24, decoder_decoded_orMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_32 = {decoder_decoded_orMatrixOutputs_lo_hi_28, decoder_decoded_orMatrixOutputs_lo_lo_25}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_17 = {decoder_decoded_andMatrixOutputs_107_2_1, decoder_decoded_andMatrixOutputs_141_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_23 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_153_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_27 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_23, decoder_decoded_orMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_20 = {decoder_decoded_andMatrixOutputs_124_2_1, decoder_decoded_andMatrixOutputs_49_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_25 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_22_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_29 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_35 = {decoder_decoded_orMatrixOutputs_hi_hi_29, decoder_decoded_orMatrixOutputs_hi_lo_27}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_92 = {decoder_decoded_orMatrixOutputs_hi_35, decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_93 = |_decoder_decoded_orMatrixOutputs_T_92; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_64_2_1, decoder_decoded_andMatrixOutputs_78_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_30 = {decoder_decoded_andMatrixOutputs_128_2_1, decoder_decoded_andMatrixOutputs_166_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_36 = {decoder_decoded_orMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_177_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] _decoder_decoded_orMatrixOutputs_T_94 = {decoder_decoded_orMatrixOutputs_hi_36, decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_95 = |_decoder_decoded_orMatrixOutputs_T_94; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_hi_37 = {decoder_decoded_andMatrixOutputs_137_2_1, decoder_decoded_andMatrixOutputs_64_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] _decoder_decoded_orMatrixOutputs_T_96 = {decoder_decoded_orMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_57_2_1}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_97 = |_decoder_decoded_orMatrixOutputs_T_96; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_82_2_1, decoder_decoded_andMatrixOutputs_171_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_52 = {decoder_decoded_andMatrixOutputs_0_2_1, decoder_decoded_andMatrixOutputs_137_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_38; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_38 = _GEN_52; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_17; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_17 = _GEN_52; // @[pla.scala:114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_98 = {decoder_decoded_orMatrixOutputs_hi_38, decoder_decoded_orMatrixOutputs_lo_34}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_99 = |_decoder_decoded_orMatrixOutputs_T_98; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_26 = {decoder_decoded_andMatrixOutputs_73_2_1, decoder_decoded_andMatrixOutputs_110_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_35 = {decoder_decoded_orMatrixOutputs_lo_hi_29, decoder_decoded_orMatrixOutputs_lo_lo_26}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_28 = {decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_140_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_101_2_1, decoder_decoded_andMatrixOutputs_9_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_31 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_39 = {decoder_decoded_orMatrixOutputs_hi_hi_31, decoder_decoded_orMatrixOutputs_hi_lo_28}; // @[pla.scala:114:19] wire [8:0] _decoder_decoded_orMatrixOutputs_T_102 = {decoder_decoded_orMatrixOutputs_hi_39, decoder_decoded_orMatrixOutputs_lo_35}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_103 = |_decoder_decoded_orMatrixOutputs_T_102; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_23 = {decoder_decoded_andMatrixOutputs_142_2_1, decoder_decoded_andMatrixOutputs_47_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_27 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_149_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_19 = {decoder_decoded_andMatrixOutputs_169_2_1, decoder_decoded_andMatrixOutputs_138_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_102_2_1, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_30 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_25, decoder_decoded_orMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_lo_36 = {decoder_decoded_orMatrixOutputs_lo_hi_30, decoder_decoded_orMatrixOutputs_lo_lo_27}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_18 = {decoder_decoded_andMatrixOutputs_15_2_1, decoder_decoded_andMatrixOutputs_144_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_93_2_1, decoder_decoded_andMatrixOutputs_125_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_29 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_21 = {decoder_decoded_andMatrixOutputs_55_2_1, decoder_decoded_andMatrixOutputs_179_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_53 = {decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_103_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_27; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_27 = _GEN_53; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_10 = _GEN_53; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_1 = _GEN_53; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_32 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_hi_40 = {decoder_decoded_orMatrixOutputs_hi_hi_32, decoder_decoded_orMatrixOutputs_hi_lo_29}; // @[pla.scala:114:19] wire [14:0] _decoder_decoded_orMatrixOutputs_T_104 = {decoder_decoded_orMatrixOutputs_hi_40, decoder_decoded_orMatrixOutputs_lo_36}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_105 = |_decoder_decoded_orMatrixOutputs_T_104; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_17 = {decoder_decoded_andMatrixOutputs_63_2_1, decoder_decoded_andMatrixOutputs_142_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_54 = {decoder_decoded_andMatrixOutputs_138_2_1, decoder_decoded_andMatrixOutputs_174_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_24; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_24 = _GEN_54; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_16; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_16 = _GEN_54; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_28 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_24, decoder_decoded_orMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_20 = {decoder_decoded_andMatrixOutputs_25_2_1, decoder_decoded_andMatrixOutputs_51_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_44_2_1, decoder_decoded_andMatrixOutputs_3_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_26 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_4_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_31 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_26, decoder_decoded_orMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_37 = {decoder_decoded_orMatrixOutputs_lo_hi_31, decoder_decoded_orMatrixOutputs_lo_lo_28}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_19 = {decoder_decoded_andMatrixOutputs_72_2_1, decoder_decoded_andMatrixOutputs_164_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_170_2_1, decoder_decoded_andMatrixOutputs_36_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_30 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_22 = {decoder_decoded_andMatrixOutputs_111_2_1, decoder_decoded_andMatrixOutputs_172_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_39_2_1, decoder_decoded_andMatrixOutputs_115_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_28 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_163_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_33 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_28, decoder_decoded_orMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_41 = {decoder_decoded_orMatrixOutputs_hi_hi_33, decoder_decoded_orMatrixOutputs_hi_lo_30}; // @[pla.scala:114:19] wire [17:0] _decoder_decoded_orMatrixOutputs_T_106 = {decoder_decoded_orMatrixOutputs_hi_41, decoder_decoded_orMatrixOutputs_lo_37}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_107 = |_decoder_decoded_orMatrixOutputs_T_106; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_5_2_1, decoder_decoded_andMatrixOutputs_41_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_32 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_8_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_38 = {decoder_decoded_orMatrixOutputs_lo_hi_32, decoder_decoded_orMatrixOutputs_lo_lo_29}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_150_2_1, decoder_decoded_andMatrixOutputs_162_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_31 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_133_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_132_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_34 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_45_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_42 = {decoder_decoded_orMatrixOutputs_hi_hi_34, decoder_decoded_orMatrixOutputs_hi_lo_31}; // @[pla.scala:114:19] wire [10:0] _decoder_decoded_orMatrixOutputs_T_108 = {decoder_decoded_orMatrixOutputs_hi_42, decoder_decoded_orMatrixOutputs_lo_38}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_109 = |_decoder_decoded_orMatrixOutputs_T_108; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_30 = {decoder_decoded_andMatrixOutputs_53_2_1, decoder_decoded_andMatrixOutputs_183_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_147_2_1, decoder_decoded_andMatrixOutputs_178_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_33 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_19_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_39 = {decoder_decoded_orMatrixOutputs_lo_hi_33, decoder_decoded_orMatrixOutputs_lo_lo_30}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_32 = {decoder_decoded_andMatrixOutputs_43_2_1, decoder_decoded_andMatrixOutputs_25_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_129_2_1, decoder_decoded_andMatrixOutputs_48_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_35 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_162_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_43 = {decoder_decoded_orMatrixOutputs_hi_hi_35, decoder_decoded_orMatrixOutputs_hi_lo_32}; // @[pla.scala:114:19] wire [9:0] _decoder_decoded_orMatrixOutputs_T_110 = {decoder_decoded_orMatrixOutputs_hi_43, decoder_decoded_orMatrixOutputs_lo_39}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_111 = |_decoder_decoded_orMatrixOutputs_T_110; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_25 = {decoder_decoded_andMatrixOutputs_173_2_1, decoder_decoded_andMatrixOutputs_37_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_31 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_55 = {decoder_decoded_andMatrixOutputs_106_2_1, decoder_decoded_andMatrixOutputs_88_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_21; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_21 = _GEN_55; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_1 = _GEN_55; // @[pla.scala:114:19] wire [1:0] _GEN_56 = {decoder_decoded_andMatrixOutputs_104_2_1, decoder_decoded_andMatrixOutputs_186_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_29; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_29 = _GEN_56; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_7 = _GEN_56; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_34 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_29, decoder_decoded_orMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_lo_40 = {decoder_decoded_orMatrixOutputs_lo_hi_34, decoder_decoded_orMatrixOutputs_lo_lo_31}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_11_2_1, decoder_decoded_andMatrixOutputs_42_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_33 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_68_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_23 = {decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_27_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_43_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_36 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_31, decoder_decoded_orMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_44 = {decoder_decoded_orMatrixOutputs_hi_hi_36, decoder_decoded_orMatrixOutputs_hi_lo_33}; // @[pla.scala:114:19] wire [13:0] _decoder_decoded_orMatrixOutputs_T_112 = {decoder_decoded_orMatrixOutputs_hi_44, decoder_decoded_orMatrixOutputs_lo_40}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_113 = |_decoder_decoded_orMatrixOutputs_T_112; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_61_2_1, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_151_2_1, decoder_decoded_andMatrixOutputs_18_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_18 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_57 = {decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_68_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_8 = _GEN_57; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_8 = _GEN_57; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_9 = _GEN_57; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_135_2_1, decoder_decoded_andMatrixOutputs_188_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_12 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_51_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_26 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_8}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_lo_32 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_26, decoder_decoded_orMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_34_2_1, decoder_decoded_andMatrixOutputs_180_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_82_2_1, decoder_decoded_andMatrixOutputs_159_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_22 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_11, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_137_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_189_2_1, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_18 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_0_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_30 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_8}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_35 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_30, decoder_decoded_orMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_lo_41 = {decoder_decoded_orMatrixOutputs_lo_hi_35, decoder_decoded_orMatrixOutputs_lo_lo_32}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_162_2_1, decoder_decoded_andMatrixOutputs_41_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_155_2_1, decoder_decoded_andMatrixOutputs_126_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_20 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_58 = {decoder_decoded_andMatrixOutputs_17_2_1, decoder_decoded_andMatrixOutputs_14_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_8; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_8 = _GEN_58; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_5 = _GEN_58; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_6 = _GEN_58; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_121_2_1, decoder_decoded_andMatrixOutputs_94_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_16 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_140_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_28 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_8}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_34 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_28, decoder_decoded_orMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_165_2_1, decoder_decoded_andMatrixOutputs_30_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_7_2_1, decoder_decoded_andMatrixOutputs_131_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_24 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_77_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_18 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_32 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_9}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_37 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_32, decoder_decoded_orMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_45 = {decoder_decoded_orMatrixOutputs_hi_hi_37, decoder_decoded_orMatrixOutputs_hi_lo_34}; // @[pla.scala:114:19] wire [35:0] _decoder_decoded_orMatrixOutputs_T_114 = {decoder_decoded_orMatrixOutputs_hi_45, decoder_decoded_orMatrixOutputs_lo_41}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_115 = |_decoder_decoded_orMatrixOutputs_T_114; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_42 = {decoder_decoded_andMatrixOutputs_65_2_1, decoder_decoded_andMatrixOutputs_146_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_46 = {decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_116 = {decoder_decoded_orMatrixOutputs_hi_46, decoder_decoded_orMatrixOutputs_lo_42}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_117 = |_decoder_decoded_orMatrixOutputs_T_116; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_118 = {decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_119 = |_decoder_decoded_orMatrixOutputs_T_118; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_19 = {decoder_decoded_andMatrixOutputs_99_2_1, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_42_2_1, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_27 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_1_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_33 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_27, decoder_decoded_orMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] _GEN_59 = {decoder_decoded_andMatrixOutputs_188_2_1, decoder_decoded_andMatrixOutputs_51_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_12; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_12 = _GEN_59; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_10 = _GEN_59; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1 = _GEN_59; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_23 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_120_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_60 = {decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_59_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_19; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_19 = _GEN_60; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_10 = _GEN_60; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_31 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_180_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_36 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_31, decoder_decoded_orMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_43 = {decoder_decoded_orMatrixOutputs_lo_hi_36, decoder_decoded_orMatrixOutputs_lo_lo_33}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_21 = {decoder_decoded_andMatrixOutputs_90_2_1, decoder_decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_24_2_1, decoder_decoded_andMatrixOutputs_52_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_29 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_17_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_35 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_29, decoder_decoded_orMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_191_2_1, decoder_decoded_andMatrixOutputs_26_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_25 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_60_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_33 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_95_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_38 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_33, decoder_decoded_orMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_47 = {decoder_decoded_orMatrixOutputs_hi_hi_38, decoder_decoded_orMatrixOutputs_hi_lo_35}; // @[pla.scala:114:19] wire [21:0] _decoder_decoded_orMatrixOutputs_T_120 = {decoder_decoded_orMatrixOutputs_hi_47, decoder_decoded_orMatrixOutputs_lo_43}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_121 = |_decoder_decoded_orMatrixOutputs_T_120; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_61 = {decoder_decoded_andMatrixOutputs_122_2_1, decoder_decoded_andMatrixOutputs_116_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_6 = _GEN_61; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_7 = _GEN_61; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_156_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_20 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] _GEN_62 = {decoder_decoded_andMatrixOutputs_1_2_1, decoder_decoded_andMatrixOutputs_99_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_5 = _GEN_62; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_11 = _GEN_62; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_12; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_12 = _GEN_62; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_6 = _GEN_62; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_88_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_14 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_28 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_34 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_28, decoder_decoded_orMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_13 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_188_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_24 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] _GEN_63 = {decoder_decoded_andMatrixOutputs_31_2_1, decoder_decoded_andMatrixOutputs_159_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_6 = _GEN_63; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_7 = _GEN_63; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_34_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_20 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_137_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_32 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_37 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_32, decoder_decoded_orMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_lo_44 = {decoder_decoded_orMatrixOutputs_lo_hi_37, decoder_decoded_orMatrixOutputs_lo_lo_34}; // @[pla.scala:114:19] wire [1:0] _GEN_64 = {decoder_decoded_andMatrixOutputs_8_2_1, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_9 = _GEN_64; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_11 = _GEN_64; // @[pla.scala:114:19] wire [1:0] _GEN_65 = {decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_162_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_6 = _GEN_65; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_7 = _GEN_65; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_1 = _GEN_65; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_10 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_41_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_22 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_184_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_66 = {decoder_decoded_andMatrixOutputs_103_2_1, decoder_decoded_andMatrixOutputs_16_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_9 = _GEN_66; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_11 = _GEN_66; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_18 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_140_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_30 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_18, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_36 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_30, decoder_decoded_orMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:114:19] wire [1:0] _GEN_67 = {decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_121_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_9; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_9 = _GEN_67; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_11 = _GEN_67; // @[pla.scala:114:19] wire [1:0] _GEN_68 = {decoder_decoded_andMatrixOutputs_97_2_1, decoder_decoded_andMatrixOutputs_70_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_6 = _GEN_68; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_10; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_10 = _GEN_68; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_7 = _GEN_68; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_14 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_131_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_26 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] _GEN_69 = {decoder_decoded_andMatrixOutputs_95_2_1, decoder_decoded_andMatrixOutputs_190_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_6 = _GEN_69; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_7 = _GEN_69; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_10 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_7_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_20 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_34 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_10}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_39 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_34, decoder_decoded_orMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_hi_48 = {decoder_decoded_orMatrixOutputs_hi_hi_39, decoder_decoded_orMatrixOutputs_hi_lo_36}; // @[pla.scala:114:19] wire [43:0] _decoder_decoded_orMatrixOutputs_T_122 = {decoder_decoded_orMatrixOutputs_hi_48, decoder_decoded_orMatrixOutputs_lo_44}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_123 = |_decoder_decoded_orMatrixOutputs_T_122; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_38 = {decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_159_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_45 = {decoder_decoded_orMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_34_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_40 = {decoder_decoded_andMatrixOutputs_182_2_1, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_49 = {decoder_decoded_orMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_189_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] _decoder_decoded_orMatrixOutputs_T_124 = {decoder_decoded_orMatrixOutputs_hi_49, decoder_decoded_orMatrixOutputs_lo_45}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_125 = |_decoder_decoded_orMatrixOutputs_T_124; // @[pla.scala:114:{19,36}] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_21 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_120_2_1, decoder_decoded_andMatrixOutputs_42_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_29 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_35 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_29, decoder_decoded_orMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_180_2_1, decoder_decoded_andMatrixOutputs_188_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_25 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_51_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_2_2_1, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_33 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_59_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_39 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_33, decoder_decoded_orMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:114:19] wire [11:0] decoder_decoded_orMatrixOutputs_lo_46 = {decoder_decoded_orMatrixOutputs_lo_hi_39, decoder_decoded_orMatrixOutputs_lo_lo_35}; // @[pla.scala:114:19] wire [1:0] _GEN_70 = {decoder_decoded_andMatrixOutputs_140_2_1, decoder_decoded_andMatrixOutputs_17_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_11; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_11 = _GEN_70; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_12; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_12 = _GEN_70; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1 = _GEN_70; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_23 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_90_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_30_2_1, decoder_decoded_andMatrixOutputs_60_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_31 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_24_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_37 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_31, decoder_decoded_orMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_191_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_27 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_29_2_1, decoder_decoded_andMatrixOutputs_95_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_35 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_11}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_hi_41 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_35, decoder_decoded_orMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:114:19] wire [12:0] decoder_decoded_orMatrixOutputs_hi_50 = {decoder_decoded_orMatrixOutputs_hi_hi_41, decoder_decoded_orMatrixOutputs_hi_lo_37}; // @[pla.scala:114:19] wire [24:0] _decoder_decoded_orMatrixOutputs_T_126 = {decoder_decoded_orMatrixOutputs_hi_50, decoder_decoded_orMatrixOutputs_lo_46}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_127 = |_decoder_decoded_orMatrixOutputs_T_126; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_88_2_1, decoder_decoded_andMatrixOutputs_122_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_22 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_142_2_1, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_30 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_16, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_10}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_lo_36 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_30, decoder_decoded_orMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:114:19] wire [1:0] _GEN_71 = {decoder_decoded_andMatrixOutputs_159_2_1, decoder_decoded_andMatrixOutputs_34_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_15; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_15 = _GEN_71; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_18; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_18 = _GEN_71; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_1 = _GEN_71; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_26 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_146_2_1, decoder_decoded_andMatrixOutputs_41_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_22 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_8_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_34 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_40 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_34, decoder_decoded_orMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_47 = {decoder_decoded_orMatrixOutputs_lo_hi_40, decoder_decoded_orMatrixOutputs_lo_lo_36}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_126_2_1, decoder_decoded_andMatrixOutputs_65_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_24 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_131_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_20 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_30_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_32 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_20, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_10}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_38 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_32, decoder_decoded_orMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_190_2_1, decoder_decoded_andMatrixOutputs_7_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_28 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_22 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_36 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_12}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_42 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_36, decoder_decoded_orMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_51 = {decoder_decoded_orMatrixOutputs_hi_hi_42, decoder_decoded_orMatrixOutputs_hi_lo_38}; // @[pla.scala:114:19] wire [34:0] _decoder_decoded_orMatrixOutputs_T_128 = {decoder_decoded_orMatrixOutputs_hi_51, decoder_decoded_orMatrixOutputs_lo_47}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_129 = |_decoder_decoded_orMatrixOutputs_T_128; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_48 = {decoder_decoded_andMatrixOutputs_67_2_1, decoder_decoded_andMatrixOutputs_62_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_130 = {decoder_decoded_orMatrixOutputs_hi_52, decoder_decoded_orMatrixOutputs_lo_48}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_131 = |_decoder_decoded_orMatrixOutputs_T_130; // @[pla.scala:114:{19,36}] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_13 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_156_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_23 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_11 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_88_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_17 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_151_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_31 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_17, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_lo_37 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_31, decoder_decoded_orMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_16 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_188_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_27 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_16, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_34_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_23 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_137_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_35 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_41 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_35, decoder_decoded_orMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_lo_49 = {decoder_decoded_orMatrixOutputs_lo_hi_41, decoder_decoded_orMatrixOutputs_lo_lo_37}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_13 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_41_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_25 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_13, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_11 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_184_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_21 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_140_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_33 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_11}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_lo_39 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_33, decoder_decoded_orMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_17 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_131_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_29 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_17, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_13 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_7_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_23 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_37 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_43 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_37, decoder_decoded_orMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:114:19] wire [21:0] decoder_decoded_orMatrixOutputs_hi_53 = {decoder_decoded_orMatrixOutputs_hi_hi_43, decoder_decoded_orMatrixOutputs_hi_lo_39}; // @[pla.scala:114:19] wire [43:0] _decoder_decoded_orMatrixOutputs_T_132 = {decoder_decoded_orMatrixOutputs_hi_53, decoder_decoded_orMatrixOutputs_lo_49}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_133 = |_decoder_decoded_orMatrixOutputs_T_132; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_24 = {decoder_decoded_andMatrixOutputs_68_2_1, decoder_decoded_andMatrixOutputs_88_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_32 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_135_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_38 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_32, decoder_decoded_orMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_28 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_13_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_36 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_28_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_42 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_36, decoder_decoded_orMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_lo_50 = {decoder_decoded_orMatrixOutputs_lo_hi_42, decoder_decoded_orMatrixOutputs_lo_lo_38}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_26 = {decoder_decoded_andMatrixOutputs_162_2_1, decoder_decoded_andMatrixOutputs_87_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_70_2_1, decoder_decoded_andMatrixOutputs_14_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_34 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_126_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_40 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_34, decoder_decoded_orMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_30 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_32_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_128_2_1, decoder_decoded_andMatrixOutputs_66_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_38 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_190_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_44 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_38, decoder_decoded_orMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_54 = {decoder_decoded_orMatrixOutputs_hi_hi_44, decoder_decoded_orMatrixOutputs_hi_lo_40}; // @[pla.scala:114:19] wire [21:0] _decoder_decoded_orMatrixOutputs_T_134 = {decoder_decoded_orMatrixOutputs_hi_54, decoder_decoded_orMatrixOutputs_lo_50}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_135 = |_decoder_decoded_orMatrixOutputs_T_134; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_138 = {decoder_decoded_andMatrixOutputs_96_2_1, decoder_decoded_andMatrixOutputs_162_2_1}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_139 = |_decoder_decoded_orMatrixOutputs_T_138; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_72 = {decoder_decoded_andMatrixOutputs_158_2_1, decoder_decoded_andMatrixOutputs_109_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_25; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_25 = _GEN_72; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1 = _GEN_72; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_136_2_1, decoder_decoded_andMatrixOutputs_192_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_33 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_38_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_39 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_33, decoder_decoded_orMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_29 = {decoder_decoded_andMatrixOutputs_130_2_1, decoder_decoded_andMatrixOutputs_50_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_141_2_1, decoder_decoded_andMatrixOutputs_69_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_37 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_175_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_43 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_37, decoder_decoded_orMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_lo_51 = {decoder_decoded_orMatrixOutputs_lo_hi_43, decoder_decoded_orMatrixOutputs_lo_lo_39}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_49_2_1, decoder_decoded_andMatrixOutputs_6_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_35 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_134_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_41 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_35, decoder_decoded_orMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_176_2_1, decoder_decoded_andMatrixOutputs_193_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_31 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_124_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_39 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_22_2_1}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_45 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_39, decoder_decoded_orMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:114:19] wire [10:0] decoder_decoded_orMatrixOutputs_hi_55 = {decoder_decoded_orMatrixOutputs_hi_hi_45, decoder_decoded_orMatrixOutputs_hi_lo_41}; // @[pla.scala:114:19] wire [20:0] _decoder_decoded_orMatrixOutputs_T_140 = {decoder_decoded_orMatrixOutputs_hi_55, decoder_decoded_orMatrixOutputs_lo_51}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_141 = |_decoder_decoded_orMatrixOutputs_T_140; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_113_2_1, decoder_decoded_andMatrixOutputs_105_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_12 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_122_2_1, decoder_decoded_andMatrixOutputs_119_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_14 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_26 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_12}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_12 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_130_2_1, decoder_decoded_andMatrixOutputs_42_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_68_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_20 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_34 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_20, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_12}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_lo_40 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_34, decoder_decoded_orMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_174_2_1, decoder_decoded_andMatrixOutputs_141_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_18 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_30 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_18, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_12}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_110_2_1, decoder_decoded_andMatrixOutputs_124_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_49_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_26 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_38 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_26, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_12}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_lo_hi_44 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_38, decoder_decoded_orMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:114:19] wire [33:0] decoder_decoded_orMatrixOutputs_lo_52 = {decoder_decoded_orMatrixOutputs_lo_hi_44, decoder_decoded_orMatrixOutputs_lo_lo_40}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_152_2_1, decoder_decoded_andMatrixOutputs_112_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_59_2_1, decoder_decoded_andMatrixOutputs_73_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_12 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_1, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_28_2_1, decoder_decoded_andMatrixOutputs_0_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_14 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_28 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_14, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_12}; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_12 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_94_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_24 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_36 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_24, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_12}; // @[pla.scala:114:19] wire [16:0] decoder_decoded_orMatrixOutputs_hi_lo_42 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_36, decoder_decoded_orMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_89_2_1, decoder_decoded_andMatrixOutputs_30_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_131_2_1, decoder_decoded_andMatrixOutputs_165_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_12 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_20_2_1, decoder_decoded_andMatrixOutputs_22_2_1}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_70_2_1, decoder_decoded_andMatrixOutputs_145_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_143_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_20 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_32 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_20, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_35_2_1, decoder_decoded_andMatrixOutputs_190_2_1}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_14 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_117_2_1, decoder_decoded_andMatrixOutputs_95_2_1}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_29_2_1}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_26 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_12, decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_40 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_14}; // @[pla.scala:114:19] wire [17:0] decoder_decoded_orMatrixOutputs_hi_hi_46 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_40, decoder_decoded_orMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:114:19] wire [34:0] decoder_decoded_orMatrixOutputs_hi_56 = {decoder_decoded_orMatrixOutputs_hi_hi_46, decoder_decoded_orMatrixOutputs_hi_lo_42}; // @[pla.scala:114:19] wire [68:0] _decoder_decoded_orMatrixOutputs_T_142 = {decoder_decoded_orMatrixOutputs_hi_56, decoder_decoded_orMatrixOutputs_lo_52}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_143 = |_decoder_decoded_orMatrixOutputs_T_142; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_13 = {_decoder_decoded_orMatrixOutputs_T_75, _decoder_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_9 = {_decoder_decoded_orMatrixOutputs_T_78, _decoder_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_15 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_76}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_27 = {decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_13 = {_decoder_decoded_orMatrixOutputs_T_81, _decoder_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_11 = {_decoder_decoded_orMatrixOutputs_T_86, _decoder_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_21 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_11, _decoder_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_35 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_21, decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_13}; // @[pla.scala:102:36] wire [9:0] decoder_decoded_orMatrixOutputs_lo_lo_41 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_35, decoder_decoded_orMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_13 = {_decoder_decoded_orMatrixOutputs_T_89, _decoder_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_9 = {_decoder_decoded_orMatrixOutputs_T_95, _decoder_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_19 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_31 = {decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_19, decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_9 = {_decoder_decoded_orMatrixOutputs_T_100, _decoder_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_13 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_9, _decoder_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_13 = {_decoder_decoded_orMatrixOutputs_T_105, _decoder_decoded_orMatrixOutputs_T_103}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_27 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_13, _decoder_decoded_orMatrixOutputs_T_101}; // @[pla.scala:102:36, :114:36] wire [5:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_39 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_13}; // @[pla.scala:102:36] wire [10:0] decoder_decoded_orMatrixOutputs_lo_hi_45 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_39, decoder_decoded_orMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:102:36] wire [20:0] decoder_decoded_orMatrixOutputs_lo_53 = {decoder_decoded_orMatrixOutputs_lo_hi_45, decoder_decoded_orMatrixOutputs_lo_lo_41}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_13 = {_decoder_decoded_orMatrixOutputs_T_109, _decoder_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_9 = {_decoder_decoded_orMatrixOutputs_T_115, _decoder_decoded_orMatrixOutputs_T_113}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_15 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_111}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_29 = {decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_15, decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_13 = {_decoder_decoded_orMatrixOutputs_T_119, _decoder_decoded_orMatrixOutputs_T_117}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_13 = {_decoder_decoded_orMatrixOutputs_T_125, _decoder_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_25 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_13, _decoder_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_37 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_25, decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_13}; // @[pla.scala:102:36] wire [9:0] decoder_decoded_orMatrixOutputs_hi_lo_43 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_37, decoder_decoded_orMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_13 = {_decoder_decoded_orMatrixOutputs_T_129, _decoder_decoded_orMatrixOutputs_T_127}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_9 = {_decoder_decoded_orMatrixOutputs_T_135, _decoder_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_21 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_9, _decoder_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_33 = {decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_21, decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_9 = {_decoder_decoded_orMatrixOutputs_T_139, _decoder_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_15 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_9, _decoder_decoded_orMatrixOutputs_T_136}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_13 = {_decoder_decoded_orMatrixOutputs_T_143, _decoder_decoded_orMatrixOutputs_T_141}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_27 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_13, 1'h0}; // @[pla.scala:102:36] wire [5:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_41 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_15}; // @[pla.scala:102:36] wire [10:0] decoder_decoded_orMatrixOutputs_hi_hi_47 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_41, decoder_decoded_orMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:102:36] wire [20:0] decoder_decoded_orMatrixOutputs_hi_57 = {decoder_decoded_orMatrixOutputs_hi_hi_47, decoder_decoded_orMatrixOutputs_hi_lo_43}; // @[pla.scala:102:36] wire [41:0] decoder_decoded_orMatrixOutputs_1 = {decoder_decoded_orMatrixOutputs_hi_57, decoder_decoded_orMatrixOutputs_lo_53}; // @[pla.scala:102:36] wire _decoder_decoded_invMatrixOutputs_T_42 = decoder_decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_43 = decoder_decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_44 = decoder_decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_45 = decoder_decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_46 = decoder_decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_47 = decoder_decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_48 = decoder_decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_49 = decoder_decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_50 = decoder_decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_51 = decoder_decoded_orMatrixOutputs_1[9]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_52 = decoder_decoded_orMatrixOutputs_1[10]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_53 = decoder_decoded_orMatrixOutputs_1[11]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_54 = decoder_decoded_orMatrixOutputs_1[12]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_55 = decoder_decoded_orMatrixOutputs_1[13]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_56 = decoder_decoded_orMatrixOutputs_1[14]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_57 = decoder_decoded_orMatrixOutputs_1[15]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_58 = decoder_decoded_orMatrixOutputs_1[16]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_59 = decoder_decoded_orMatrixOutputs_1[17]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_60 = decoder_decoded_orMatrixOutputs_1[18]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_61 = decoder_decoded_orMatrixOutputs_1[19]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_62 = decoder_decoded_orMatrixOutputs_1[20]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_63 = decoder_decoded_orMatrixOutputs_1[21]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_64 = decoder_decoded_orMatrixOutputs_1[22]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_65 = decoder_decoded_orMatrixOutputs_1[23]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_66 = decoder_decoded_orMatrixOutputs_1[24]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_67 = decoder_decoded_orMatrixOutputs_1[25]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_68 = decoder_decoded_orMatrixOutputs_1[26]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_69 = decoder_decoded_orMatrixOutputs_1[27]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_70 = decoder_decoded_orMatrixOutputs_1[28]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_71 = decoder_decoded_orMatrixOutputs_1[29]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_72 = decoder_decoded_orMatrixOutputs_1[30]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_73 = decoder_decoded_orMatrixOutputs_1[31]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_74 = decoder_decoded_orMatrixOutputs_1[32]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_75 = decoder_decoded_orMatrixOutputs_1[33]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_76 = decoder_decoded_orMatrixOutputs_1[34]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_77 = decoder_decoded_orMatrixOutputs_1[35]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_78 = decoder_decoded_orMatrixOutputs_1[36]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_79 = decoder_decoded_orMatrixOutputs_1[37]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_80 = decoder_decoded_orMatrixOutputs_1[38]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_81 = decoder_decoded_orMatrixOutputs_1[39]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_82 = decoder_decoded_orMatrixOutputs_1[40]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_83 = decoder_decoded_orMatrixOutputs_1[41]; // @[pla.scala:102:36, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_1 = {_decoder_decoded_invMatrixOutputs_T_43, _decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_46, _decoder_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_1 = {decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_lo_lo_1 = {decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_1 = {_decoder_decoded_invMatrixOutputs_T_48, _decoder_decoded_invMatrixOutputs_T_47}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_51, _decoder_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:120:37] wire [9:0] decoder_decoded_invMatrixOutputs_lo_lo_1 = {decoder_decoded_invMatrixOutputs_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_1 = {_decoder_decoded_invMatrixOutputs_T_53, _decoder_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_56, _decoder_decoded_invMatrixOutputs_T_55}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_hi_lo_1 = {decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_1 = {_decoder_decoded_invMatrixOutputs_T_59, _decoder_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_1 = {decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_1, _decoder_decoded_invMatrixOutputs_T_57}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_62, _decoder_decoded_invMatrixOutputs_T_61}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [5:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:120:37] wire [10:0] decoder_decoded_invMatrixOutputs_lo_hi_1 = {decoder_decoded_invMatrixOutputs_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:120:37] wire [20:0] decoder_decoded_invMatrixOutputs_lo_1 = {decoder_decoded_invMatrixOutputs_lo_hi_1, decoder_decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_1 = {_decoder_decoded_invMatrixOutputs_T_64, _decoder_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_67, _decoder_decoded_invMatrixOutputs_T_66}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_1 = {decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_1 = {_decoder_decoded_invMatrixOutputs_T_69, _decoder_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_72, _decoder_decoded_invMatrixOutputs_T_71}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_1 = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:120:37] wire [9:0] decoder_decoded_invMatrixOutputs_hi_lo_1 = {decoder_decoded_invMatrixOutputs_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_1 = {_decoder_decoded_invMatrixOutputs_T_74, _decoder_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_77, _decoder_decoded_invMatrixOutputs_T_76}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_1 = {_decoder_decoded_invMatrixOutputs_T_80, _decoder_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_1 = {decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_1, _decoder_decoded_invMatrixOutputs_T_78}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1 = {_decoder_decoded_invMatrixOutputs_T_83, _decoder_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_1 = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1, _decoder_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [5:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:120:37] wire [10:0] decoder_decoded_invMatrixOutputs_hi_hi_1 = {decoder_decoded_invMatrixOutputs_hi_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:120:37] wire [20:0] decoder_decoded_invMatrixOutputs_hi_1 = {decoder_decoded_invMatrixOutputs_hi_hi_1, decoder_decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoder_decoded_invMatrixOutputs_1 = {decoder_decoded_invMatrixOutputs_hi_1, decoder_decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoder_decoded_1 = decoder_decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] assign decoder_0_1 = decoder_decoded_1[41]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_legal = decoder_0_1; // @[Core.scala:70:22] assign decoder_1_1 = decoder_decoded_1[40]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_fp = decoder_1_1; // @[Core.scala:70:22] assign decoder_2_1 = decoder_decoded_1[39]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rocc = decoder_2_1; // @[Core.scala:70:22] assign decoder_3_1 = decoder_decoded_1[38]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_branch = decoder_3_1; // @[Core.scala:70:22] assign decoder_4_1 = decoder_decoded_1[37]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_jal = decoder_4_1; // @[Core.scala:70:22] assign decoder_5_1 = decoder_decoded_1[36]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_jalr = decoder_5_1; // @[Core.scala:70:22] assign decoder_6_1 = decoder_decoded_1[35]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rxs2 = decoder_6_1; // @[Core.scala:70:22] assign decoder_7_1 = decoder_decoded_1[34]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rxs1 = decoder_7_1; // @[Core.scala:70:22] wire [2:0] decoder_8_1 = decoder_decoded_1[33:31]; // @[pla.scala:81:23] wire [1:0] decoder_9_1 = decoder_decoded_1[30:29]; // @[pla.scala:81:23] assign decoder_10_1 = decoder_decoded_1[28:26]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_sel_imm = decoder_10_1; // @[Core.scala:70:22] wire decoder_11_1 = decoder_decoded_1[25]; // @[pla.scala:81:23] wire [4:0] decoder_12_1 = decoder_decoded_1[24:20]; // @[pla.scala:81:23] assign decoder_13_1 = decoder_decoded_1[19]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_mem = decoder_13_1; // @[Core.scala:70:22] assign decoder_14_1 = decoder_decoded_1[18:14]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_mem_cmd = decoder_14_1; // @[Core.scala:70:22] assign decoder_15_1 = decoder_decoded_1[13]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rfs1 = decoder_15_1; // @[Core.scala:70:22] assign decoder_16_1 = decoder_decoded_1[12]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rfs2 = decoder_16_1; // @[Core.scala:70:22] assign decoder_17_1 = decoder_decoded_1[11]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_rfs3 = decoder_17_1; // @[Core.scala:70:22] assign decoder_18_1 = decoder_decoded_1[10]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_wfd = decoder_18_1; // @[Core.scala:70:22] assign decoder_19_1 = decoder_decoded_1[9]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_mul = decoder_19_1; // @[Core.scala:70:22] assign decoder_20_1 = decoder_decoded_1[8]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_div = decoder_20_1; // @[Core.scala:70:22] assign decoder_21_1 = decoder_decoded_1[7]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_wxd = decoder_21_1; // @[Core.scala:70:22] assign decoder_22_1 = decoder_decoded_1[6:4]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_csr = decoder_22_1; // @[Core.scala:70:22] assign decoder_23_1 = decoder_decoded_1[3]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_fence_i = decoder_23_1; // @[Core.scala:70:22] assign decoder_24_1 = decoder_decoded_1[2]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_fence = decoder_24_1; // @[Core.scala:70:22] assign decoder_25_1 = decoder_decoded_1[1]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_amo = decoder_25_1; // @[Core.scala:70:22] assign decoder_26_1 = decoder_decoded_1[0]; // @[pla.scala:81:23] assign rrd_uops_1_bits_ctrl_dp = decoder_26_1; // @[Core.scala:70:22] wire [31:0] _rrd_uops_1_bits_sets_vcfg_T = io_imem_resp_1_bits_inst_0 & 32'h8000707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_1_bits_sets_vcfg_T_1 = _rrd_uops_1_bits_sets_vcfg_T == 32'h7057; // @[Core.scala:186:101] wire [31:0] _rrd_uops_1_bits_sets_vcfg_T_2 = io_imem_resp_1_bits_inst_0 & 32'hC000707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_1_bits_sets_vcfg_T_3 = _rrd_uops_1_bits_sets_vcfg_T_2 == 32'hC0007057; // @[Core.scala:186:101] wire [31:0] _rrd_uops_1_bits_sets_vcfg_T_4 = io_imem_resp_1_bits_inst_0 & 32'hFE00707F; // @[Core.scala:25:7, :186:101] wire _rrd_uops_1_bits_sets_vcfg_T_5 = _rrd_uops_1_bits_sets_vcfg_T_4 == 32'h80007057; // @[Core.scala:186:101] wire _rrd_uops_1_bits_sets_vcfg_T_6 = _rrd_uops_1_bits_sets_vcfg_T_1 | _rrd_uops_1_bits_sets_vcfg_T_3; // @[Core.scala:186:101] wire _rrd_uops_1_bits_sets_vcfg_T_7 = _rrd_uops_1_bits_sets_vcfg_T_6 | _rrd_uops_1_bits_sets_vcfg_T_5; // @[Core.scala:186:101] wire _rrd_illegal_insn_0_T_15; // @[Core.scala:248:56] wire _rrd_illegal_insn_1_T_15; // @[Core.scala:248:56] wire rrd_illegal_insn_0; // @[Core.scala:227:30] wire rrd_illegal_insn_1; // @[Core.scala:227:30] wire [2:0] _illegal_rm_T = rrd_uops_0_bits_inst[14:12]; // @[Core.scala:70:22, :232:26] wire [2:0] _illegal_rm_T_4 = rrd_uops_0_bits_inst[14:12]; // @[Core.scala:70:22, :232:{26,59}] wire _illegal_rm_T_1 = _illegal_rm_T == 3'h5; // @[Core.scala:232:26] wire _illegal_rm_T_2 = _illegal_rm_T == 3'h6; // @[Core.scala:232:26] wire _illegal_rm_T_3 = _illegal_rm_T_1 | _illegal_rm_T_2; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_5 = &_illegal_rm_T_4; // @[Core.scala:232:{59,67}] wire _GEN_73 = _csr_io_fcsr_rm > 3'h4; // @[Core.scala:52:19, :232:93] wire _illegal_rm_T_6; // @[Core.scala:232:93] assign _illegal_rm_T_6 = _GEN_73; // @[Core.scala:232:93] wire _illegal_rm_T_14; // @[Core.scala:232:93] assign _illegal_rm_T_14 = _GEN_73; // @[Core.scala:232:93] wire _illegal_rm_T_7 = _illegal_rm_T_5 & _illegal_rm_T_6; // @[Core.scala:232:{67,75,93}] wire illegal_rm = _illegal_rm_T_3 | _illegal_rm_T_7; // @[Core.scala:232:{52,75}] wire _fp_illegal_T_1 = illegal_rm; // @[Core.scala:232:52, :233:65] wire fp_illegal = _csr_io_decode_0_fp_illegal | _fp_illegal_T_1; // @[Core.scala:52:19, :233:{50,65}] wire _GEN_74 = rrd_uops_0_bits_ctrl_csr == 3'h6; // @[Core.scala:70:22] wire _csr_en_T; // @[package.scala:16:47] assign _csr_en_T = _GEN_74; // @[package.scala:16:47] wire _csr_ren_T; // @[package.scala:16:47] assign _csr_ren_T = _GEN_74; // @[package.scala:16:47] wire _csr_wen_T; // @[package.scala:16:47] assign _csr_wen_T = _GEN_74; // @[package.scala:16:47] wire _csr_wen_T_5; // @[package.scala:16:47] assign _csr_wen_T_5 = _GEN_74; // @[package.scala:16:47] wire _rrd_p0_can_forward_x_to_m_T_6; // @[package.scala:16:47] assign _rrd_p0_can_forward_x_to_m_T_6 = _GEN_74; // @[package.scala:16:47] wire _rs1_can_forward_from_x_p0_T_8; // @[package.scala:16:47] assign _rs1_can_forward_from_x_p0_T_8 = _GEN_74; // @[package.scala:16:47] wire _rs2_can_forward_from_x_p0_T_8; // @[package.scala:16:47] assign _rs2_can_forward_from_x_p0_T_8 = _GEN_74; // @[package.scala:16:47] wire _rs1_can_forward_from_w_p0_T_8; // @[package.scala:16:47] assign _rs1_can_forward_from_w_p0_T_8 = _GEN_74; // @[package.scala:16:47] wire _rs2_can_forward_from_w_p0_T_8; // @[package.scala:16:47] assign _rs2_can_forward_from_w_p0_T_8 = _GEN_74; // @[package.scala:16:47] wire _rrd_uops_0_bits_uses_memalu_T_6; // @[package.scala:16:47] assign _rrd_uops_0_bits_uses_memalu_T_6 = _GEN_74; // @[package.scala:16:47] wire _rrd_uops_0_bits_uses_latealu_T_6; // @[package.scala:16:47] assign _rrd_uops_0_bits_uses_latealu_T_6 = _GEN_74; // @[package.scala:16:47] wire _rd_same_hazard_T_8; // @[package.scala:16:47] assign _rd_same_hazard_T_8 = _GEN_74; // @[package.scala:16:47] wire _is_pipe0_T_7; // @[package.scala:16:47] assign _is_pipe0_T_7 = _GEN_74; // @[package.scala:16:47] wire _is_pipe0_T_41; // @[package.scala:16:47] assign _is_pipe0_T_41 = _GEN_74; // @[package.scala:16:47] wire _is_youngest_T; // @[package.scala:16:47] assign _is_youngest_T = _GEN_74; // @[package.scala:16:47] wire _io_imem_redirect_flush_T_2; // @[package.scala:16:47] assign _io_imem_redirect_flush_T_2 = _GEN_74; // @[package.scala:16:47] wire _io_imem_redirect_flush_T_7; // @[package.scala:16:47] assign _io_imem_redirect_flush_T_7 = _GEN_74; // @[package.scala:16:47] wire _csr_en_T_1 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _GEN_75 = rrd_uops_0_bits_ctrl_csr == 3'h5; // @[Core.scala:70:22] wire _csr_en_T_2; // @[package.scala:16:47] assign _csr_en_T_2 = _GEN_75; // @[package.scala:16:47] wire _csr_wen_T_2; // @[package.scala:16:47] assign _csr_wen_T_2 = _GEN_75; // @[package.scala:16:47] wire _rrd_p0_can_forward_x_to_m_T_8; // @[package.scala:16:47] assign _rrd_p0_can_forward_x_to_m_T_8 = _GEN_75; // @[package.scala:16:47] wire _rs1_can_forward_from_x_p0_T_10; // @[package.scala:16:47] assign _rs1_can_forward_from_x_p0_T_10 = _GEN_75; // @[package.scala:16:47] wire _rs2_can_forward_from_x_p0_T_10; // @[package.scala:16:47] assign _rs2_can_forward_from_x_p0_T_10 = _GEN_75; // @[package.scala:16:47] wire _rs1_can_forward_from_w_p0_T_10; // @[package.scala:16:47] assign _rs1_can_forward_from_w_p0_T_10 = _GEN_75; // @[package.scala:16:47] wire _rs2_can_forward_from_w_p0_T_10; // @[package.scala:16:47] assign _rs2_can_forward_from_w_p0_T_10 = _GEN_75; // @[package.scala:16:47] wire _rrd_uops_0_bits_uses_memalu_T_8; // @[package.scala:16:47] assign _rrd_uops_0_bits_uses_memalu_T_8 = _GEN_75; // @[package.scala:16:47] wire _rrd_uops_0_bits_uses_latealu_T_8; // @[package.scala:16:47] assign _rrd_uops_0_bits_uses_latealu_T_8 = _GEN_75; // @[package.scala:16:47] wire _rd_same_hazard_T_10; // @[package.scala:16:47] assign _rd_same_hazard_T_10 = _GEN_75; // @[package.scala:16:47] wire _is_pipe0_T_9; // @[package.scala:16:47] assign _is_pipe0_T_9 = _GEN_75; // @[package.scala:16:47] wire _is_pipe0_T_43; // @[package.scala:16:47] assign _is_pipe0_T_43 = _GEN_75; // @[package.scala:16:47] wire _is_youngest_T_2; // @[package.scala:16:47] assign _is_youngest_T_2 = _GEN_75; // @[package.scala:16:47] wire _io_imem_redirect_flush_T_4; // @[package.scala:16:47] assign _io_imem_redirect_flush_T_4 = _GEN_75; // @[package.scala:16:47] wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59] wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59] wire _csr_ren_T_1 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59] wire [4:0] _csr_ren_T_3 = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _csr_wen_T_8 = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] rs1 = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra1_T = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra2_T = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _io_imem_redirect_flush_T_10 = rrd_uops_0_bits_inst[19:15]; // @[Core.scala:70:22] wire _csr_ren_T_4 = _csr_ren_T_3 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_4; // @[MicroOp.scala:69:{48,55}] wire _csr_wen_T_1 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_wen_T_3 = _csr_wen_T | _csr_wen_T_1; // @[package.scala:16:47, :81:59] wire _csr_wen_T_4 = _csr_wen_T_3 | _csr_wen_T_2; // @[package.scala:16:47, :81:59] wire _csr_wen_T_6 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_wen_T_7 = _csr_wen_T_5 | _csr_wen_T_6; // @[package.scala:16:47, :81:59] wire _csr_wen_T_9 = _csr_wen_T_8 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire _csr_wen_T_10 = _csr_wen_T_7 & _csr_wen_T_9; // @[MicroOp.scala:69:{48,55}] wire _csr_wen_T_11 = ~_csr_wen_T_10; // @[MicroOp.scala:69:48, :70:27] wire csr_wen = _csr_wen_T_4 & _csr_wen_T_11; // @[MicroOp.scala:70:{24,27}] wire csr_wen_illegal = csr_wen & _csr_io_decode_0_write_illegal; // @[Core.scala:52:19, :238:35] wire _T_67 = rrd_uops_0_bits_ctrl_mem_cmd == 5'h14; // @[Core.scala:70:22, :239:43] wire _sfence_T; // @[Core.scala:239:43] assign _sfence_T = _T_67; // @[Core.scala:239:43] wire _rrd_fence_stall_T_2; // @[MicroOp.scala:72:41] assign _rrd_fence_stall_T_2 = _T_67; // @[Core.scala:239:43] wire _brjmp_T_2; // @[MicroOp.scala:72:41] assign _brjmp_T_2 = _T_67; // @[Core.scala:239:43] wire _is_pipe0_T_25; // @[MicroOp.scala:72:41] assign _is_pipe0_T_25 = _T_67; // @[Core.scala:239:43] wire _is_pipe0_T_47; // @[MicroOp.scala:72:41] assign _is_pipe0_T_47 = _T_67; // @[Core.scala:239:43] wire sfence = rrd_uops_0_bits_ctrl_mem & _sfence_T; // @[Core.scala:70:22, :239:{27,43}] wire _GEN_76 = rrd_uops_0_bits_ctrl_csr == 3'h4; // @[Core.scala:70:22] wire system_insn; // @[MicroOp.scala:71:30] assign system_insn = _GEN_76; // @[MicroOp.scala:71:30] wire _rrd_fence_stall_T; // @[MicroOp.scala:71:30] assign _rrd_fence_stall_T = _GEN_76; // @[MicroOp.scala:71:30] wire _is_pipe0_T; // @[MicroOp.scala:71:30] assign _is_pipe0_T = _GEN_76; // @[MicroOp.scala:71:30] wire _is_youngest_T_6; // @[MicroOp.scala:71:30] assign _is_youngest_T_6 = _GEN_76; // @[MicroOp.scala:71:30] wire _GEN_77 = sfence | system_insn; // @[Core.scala:239:27, :242:43] wire _rrd_uops_0_bits_flush_pipe_T; // @[Core.scala:242:43] assign _rrd_uops_0_bits_flush_pipe_T = _GEN_77; // @[Core.scala:242:43] wire _rrd_illegal_insn_0_T_12; // @[Core.scala:249:29] assign _rrd_illegal_insn_0_T_12 = _GEN_77; // @[Core.scala:242:43, :249:29] wire _rrd_uops_0_bits_flush_pipe_T_1 = csr_wen & _csr_io_decode_0_write_flush; // @[Core.scala:52:19, :242:70] assign _rrd_uops_0_bits_flush_pipe_T_2 = _rrd_uops_0_bits_flush_pipe_T | _rrd_uops_0_bits_flush_pipe_T_1; // @[Core.scala:242:{43,58,70}] assign rrd_uops_0_bits_flush_pipe = _rrd_uops_0_bits_flush_pipe_T_2; // @[Core.scala:70:22, :242:58] wire _rrd_illegal_insn_0_T = ~rrd_uops_0_bits_ctrl_legal; // @[Core.scala:70:22, :244:29] wire _rrd_illegal_insn_0_T_1 = rrd_uops_0_bits_ctrl_fp & fp_illegal; // @[Core.scala:70:22, :233:50, :245:16] wire _rrd_illegal_insn_0_T_2 = _rrd_illegal_insn_0_T | _rrd_illegal_insn_0_T_1; // @[Core.scala:244:{29,41}, :245:16] wire _rrd_illegal_insn_0_T_4 = _rrd_illegal_insn_0_T_2 | _rrd_illegal_insn_0_T_3; // @[Core.scala:244:41, :245:31, :246:18] wire _rrd_illegal_insn_0_T_7 = _rrd_illegal_insn_0_T_4; // @[Core.scala:245:31, :246:52] wire _rrd_illegal_insn_0_T_8 = _csr_io_decode_0_read_illegal | csr_wen_illegal; // @[Core.scala:52:19, :238:35, :248:35] wire _rrd_illegal_insn_0_T_9 = csr_en & _rrd_illegal_insn_0_T_8; // @[Core.scala:248:{15,35}] wire _rrd_illegal_insn_0_T_10 = _rrd_illegal_insn_0_T_7 | _rrd_illegal_insn_0_T_9; // @[Core.scala:246:52, :247:103, :248:15] wire _rrd_illegal_insn_0_T_11 = ~rrd_uops_0_bits_rvc; // @[Core.scala:70:22, :249:8] wire _rrd_illegal_insn_0_T_13 = _rrd_illegal_insn_0_T_12 & _csr_io_decode_0_system_illegal; // @[Core.scala:52:19, :249:{29,45}] wire _rrd_illegal_insn_0_T_14 = _rrd_illegal_insn_0_T_11 & _rrd_illegal_insn_0_T_13; // @[Core.scala:249:{8,17,45}] assign _rrd_illegal_insn_0_T_15 = _rrd_illegal_insn_0_T_10 | _rrd_illegal_insn_0_T_14; // @[Core.scala:247:103, :248:56, :249:17] assign rrd_illegal_insn_0 = _rrd_illegal_insn_0_T_15; // @[Core.scala:227:30, :248:56] wire [2:0] _illegal_rm_T_8 = rrd_uops_1_bits_inst[14:12]; // @[Core.scala:70:22, :232:26] wire [2:0] _illegal_rm_T_12 = rrd_uops_1_bits_inst[14:12]; // @[Core.scala:70:22, :232:{26,59}] wire _illegal_rm_T_9 = _illegal_rm_T_8 == 3'h5; // @[Core.scala:232:26] wire _illegal_rm_T_10 = _illegal_rm_T_8 == 3'h6; // @[Core.scala:232:26] wire _illegal_rm_T_11 = _illegal_rm_T_9 | _illegal_rm_T_10; // @[package.scala:16:47, :81:59] wire _illegal_rm_T_13 = &_illegal_rm_T_12; // @[Core.scala:232:{59,67}] wire _illegal_rm_T_15 = _illegal_rm_T_13 & _illegal_rm_T_14; // @[Core.scala:232:{67,75,93}] wire illegal_rm_1 = _illegal_rm_T_11 | _illegal_rm_T_15; // @[Core.scala:232:{52,75}] wire _fp_illegal_T_3 = illegal_rm_1; // @[Core.scala:232:52, :233:65] wire fp_illegal_1 = _csr_io_decode_1_fp_illegal | _fp_illegal_T_3; // @[Core.scala:52:19, :233:{50,65}] wire _GEN_78 = rrd_uops_1_bits_ctrl_csr == 3'h6; // @[Core.scala:70:22] wire _csr_en_T_4; // @[package.scala:16:47] assign _csr_en_T_4 = _GEN_78; // @[package.scala:16:47] wire _csr_ren_T_5; // @[package.scala:16:47] assign _csr_ren_T_5 = _GEN_78; // @[package.scala:16:47] wire _csr_wen_T_12; // @[package.scala:16:47] assign _csr_wen_T_12 = _GEN_78; // @[package.scala:16:47] wire _csr_wen_T_17; // @[package.scala:16:47] assign _csr_wen_T_17 = _GEN_78; // @[package.scala:16:47] wire _rs1_can_forward_from_x_p0_T_41; // @[package.scala:16:47] assign _rs1_can_forward_from_x_p0_T_41 = _GEN_78; // @[package.scala:16:47] wire _rs2_can_forward_from_x_p0_T_41; // @[package.scala:16:47] assign _rs2_can_forward_from_x_p0_T_41 = _GEN_78; // @[package.scala:16:47] wire _rs1_can_forward_from_w_p0_T_39; // @[package.scala:16:47] assign _rs1_can_forward_from_w_p0_T_39 = _GEN_78; // @[package.scala:16:47] wire _rs2_can_forward_from_w_p0_T_39; // @[package.scala:16:47] assign _rs2_can_forward_from_w_p0_T_39 = _GEN_78; // @[package.scala:16:47] wire _rrd_uops_1_bits_uses_memalu_T_6; // @[package.scala:16:47] assign _rrd_uops_1_bits_uses_memalu_T_6 = _GEN_78; // @[package.scala:16:47] wire _rrd_uops_1_bits_uses_latealu_T_6; // @[package.scala:16:47] assign _rrd_uops_1_bits_uses_latealu_T_6 = _GEN_78; // @[package.scala:16:47] wire _is_pipe0_T_66; // @[package.scala:16:47] assign _is_pipe0_T_66 = _GEN_78; // @[package.scala:16:47] wire _is_pipe0_T_100; // @[package.scala:16:47] assign _is_pipe0_T_100 = _GEN_78; // @[package.scala:16:47] wire _is_youngest_T_7; // @[package.scala:16:47] assign _is_youngest_T_7 = _GEN_78; // @[package.scala:16:47] wire _csr_en_T_5 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _GEN_79 = rrd_uops_1_bits_ctrl_csr == 3'h5; // @[Core.scala:70:22] wire _csr_en_T_6; // @[package.scala:16:47] assign _csr_en_T_6 = _GEN_79; // @[package.scala:16:47] wire _csr_wen_T_14; // @[package.scala:16:47] assign _csr_wen_T_14 = _GEN_79; // @[package.scala:16:47] wire _rs1_can_forward_from_x_p0_T_43; // @[package.scala:16:47] assign _rs1_can_forward_from_x_p0_T_43 = _GEN_79; // @[package.scala:16:47] wire _rs2_can_forward_from_x_p0_T_43; // @[package.scala:16:47] assign _rs2_can_forward_from_x_p0_T_43 = _GEN_79; // @[package.scala:16:47] wire _rs1_can_forward_from_w_p0_T_41; // @[package.scala:16:47] assign _rs1_can_forward_from_w_p0_T_41 = _GEN_79; // @[package.scala:16:47] wire _rs2_can_forward_from_w_p0_T_41; // @[package.scala:16:47] assign _rs2_can_forward_from_w_p0_T_41 = _GEN_79; // @[package.scala:16:47] wire _rrd_uops_1_bits_uses_memalu_T_8; // @[package.scala:16:47] assign _rrd_uops_1_bits_uses_memalu_T_8 = _GEN_79; // @[package.scala:16:47] wire _rrd_uops_1_bits_uses_latealu_T_8; // @[package.scala:16:47] assign _rrd_uops_1_bits_uses_latealu_T_8 = _GEN_79; // @[package.scala:16:47] wire _is_pipe0_T_68; // @[package.scala:16:47] assign _is_pipe0_T_68 = _GEN_79; // @[package.scala:16:47] wire _is_pipe0_T_102; // @[package.scala:16:47] assign _is_pipe0_T_102 = _GEN_79; // @[package.scala:16:47] wire _is_youngest_T_9; // @[package.scala:16:47] assign _is_youngest_T_9 = _GEN_79; // @[package.scala:16:47] wire _csr_en_T_7 = _csr_en_T_4 | _csr_en_T_5; // @[package.scala:16:47, :81:59] wire csr_en_1 = _csr_en_T_7 | _csr_en_T_6; // @[package.scala:16:47, :81:59] wire _csr_ren_T_6 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_ren_T_7 = _csr_ren_T_5 | _csr_ren_T_6; // @[package.scala:16:47, :81:59] wire [4:0] _csr_ren_T_8 = rrd_uops_1_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _csr_wen_T_20 = rrd_uops_1_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] rs1_1 = rrd_uops_1_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra1_T = rrd_uops_1_bits_inst[19:15]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra2_T = rrd_uops_1_bits_inst[19:15]; // @[Core.scala:70:22] wire _csr_ren_T_9 = _csr_ren_T_8 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire csr_ren_1 = _csr_ren_T_7 & _csr_ren_T_9; // @[MicroOp.scala:69:{48,55}] wire _csr_wen_T_13 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_wen_T_15 = _csr_wen_T_12 | _csr_wen_T_13; // @[package.scala:16:47, :81:59] wire _csr_wen_T_16 = _csr_wen_T_15 | _csr_wen_T_14; // @[package.scala:16:47, :81:59] wire _csr_wen_T_18 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _csr_wen_T_19 = _csr_wen_T_17 | _csr_wen_T_18; // @[package.scala:16:47, :81:59] wire _csr_wen_T_21 = _csr_wen_T_20 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire _csr_wen_T_22 = _csr_wen_T_19 & _csr_wen_T_21; // @[MicroOp.scala:69:{48,55}] wire _csr_wen_T_23 = ~_csr_wen_T_22; // @[MicroOp.scala:69:48, :70:27] wire csr_wen_1 = _csr_wen_T_16 & _csr_wen_T_23; // @[MicroOp.scala:70:{24,27}] wire csr_wen_illegal_1 = csr_wen_1 & _csr_io_decode_1_write_illegal; // @[Core.scala:52:19, :238:35] wire _T_113 = rrd_uops_1_bits_ctrl_mem_cmd == 5'h14; // @[Core.scala:70:22, :239:43] wire _sfence_T_1; // @[Core.scala:239:43] assign _sfence_T_1 = _T_113; // @[Core.scala:239:43] wire _rrd_fence_stall_T_18; // @[MicroOp.scala:72:41] assign _rrd_fence_stall_T_18 = _T_113; // @[Core.scala:239:43] wire _brjmp_T_7; // @[MicroOp.scala:72:41] assign _brjmp_T_7 = _T_113; // @[Core.scala:239:43] wire _is_pipe0_T_84; // @[MicroOp.scala:72:41] assign _is_pipe0_T_84 = _T_113; // @[Core.scala:239:43] wire _is_pipe0_T_106; // @[MicroOp.scala:72:41] assign _is_pipe0_T_106 = _T_113; // @[Core.scala:239:43] wire sfence_1 = rrd_uops_1_bits_ctrl_mem & _sfence_T_1; // @[Core.scala:70:22, :239:{27,43}] wire _GEN_80 = rrd_uops_1_bits_ctrl_csr == 3'h4; // @[Core.scala:70:22] wire system_insn_1; // @[MicroOp.scala:71:30] assign system_insn_1 = _GEN_80; // @[MicroOp.scala:71:30] wire _rrd_fence_stall_T_16; // @[MicroOp.scala:71:30] assign _rrd_fence_stall_T_16 = _GEN_80; // @[MicroOp.scala:71:30] wire _is_pipe0_T_59; // @[MicroOp.scala:71:30] assign _is_pipe0_T_59 = _GEN_80; // @[MicroOp.scala:71:30] wire _is_youngest_T_13; // @[MicroOp.scala:71:30] assign _is_youngest_T_13 = _GEN_80; // @[MicroOp.scala:71:30] wire _GEN_81 = sfence_1 | system_insn_1; // @[Core.scala:239:27, :242:43] wire _rrd_uops_1_bits_flush_pipe_T; // @[Core.scala:242:43] assign _rrd_uops_1_bits_flush_pipe_T = _GEN_81; // @[Core.scala:242:43] wire _rrd_illegal_insn_1_T_12; // @[Core.scala:249:29] assign _rrd_illegal_insn_1_T_12 = _GEN_81; // @[Core.scala:242:43, :249:29] wire _rrd_uops_1_bits_flush_pipe_T_1 = csr_wen_1 & _csr_io_decode_1_write_flush; // @[Core.scala:52:19, :242:70] assign _rrd_uops_1_bits_flush_pipe_T_2 = _rrd_uops_1_bits_flush_pipe_T | _rrd_uops_1_bits_flush_pipe_T_1; // @[Core.scala:242:{43,58,70}] assign rrd_uops_1_bits_flush_pipe = _rrd_uops_1_bits_flush_pipe_T_2; // @[Core.scala:70:22, :242:58] wire _rrd_illegal_insn_1_T = ~rrd_uops_1_bits_ctrl_legal; // @[Core.scala:70:22, :244:29] wire _rrd_illegal_insn_1_T_1 = rrd_uops_1_bits_ctrl_fp & fp_illegal_1; // @[Core.scala:70:22, :233:50, :245:16] wire _rrd_illegal_insn_1_T_2 = _rrd_illegal_insn_1_T | _rrd_illegal_insn_1_T_1; // @[Core.scala:244:{29,41}, :245:16] wire _rrd_illegal_insn_1_T_4 = _rrd_illegal_insn_1_T_2 | _rrd_illegal_insn_1_T_3; // @[Core.scala:244:41, :245:31, :246:18] wire _rrd_illegal_insn_1_T_7 = _rrd_illegal_insn_1_T_4; // @[Core.scala:245:31, :246:52] wire _rrd_illegal_insn_1_T_8 = _csr_io_decode_1_read_illegal | csr_wen_illegal_1; // @[Core.scala:52:19, :238:35, :248:35] wire _rrd_illegal_insn_1_T_9 = csr_en_1 & _rrd_illegal_insn_1_T_8; // @[Core.scala:248:{15,35}] wire _rrd_illegal_insn_1_T_10 = _rrd_illegal_insn_1_T_7 | _rrd_illegal_insn_1_T_9; // @[Core.scala:246:52, :247:103, :248:15] wire _rrd_illegal_insn_1_T_11 = ~rrd_uops_1_bits_rvc; // @[Core.scala:70:22, :249:8] wire _rrd_illegal_insn_1_T_13 = _rrd_illegal_insn_1_T_12 & _csr_io_decode_1_system_illegal; // @[Core.scala:52:19, :249:{29,45}] wire _rrd_illegal_insn_1_T_14 = _rrd_illegal_insn_1_T_11 & _rrd_illegal_insn_1_T_13; // @[Core.scala:249:{8,17,45}] assign _rrd_illegal_insn_1_T_15 = _rrd_illegal_insn_1_T_10 | _rrd_illegal_insn_1_T_14; // @[Core.scala:247:103, :248:56, :249:17] assign rrd_illegal_insn_1 = _rrd_illegal_insn_1_T_15; // @[Core.scala:227:30, :248:56] assign xcpt = _csr_io_interrupt | io_imem_resp_0_bits_xcpt_0 | rrd_illegal_insn_0; // @[Core.scala:25:7, :52:19, :60:26, :227:30] assign rrd_uops_0_bits_xcpt = xcpt; // @[Core.scala:60:26, :70:22] assign cause = _csr_io_interrupt ? _csr_io_interrupt_cause : io_imem_resp_0_bits_xcpt_0 ? io_imem_resp_0_bits_xcpt_cause_0 : 64'h2; // @[Mux.scala:50:70] assign rrd_uops_0_bits_xcpt_cause = cause; // @[Mux.scala:50:70] assign rrd_uops_0_bits_ctrl_alu_fn = xcpt ? 5'h0 : decoder_12; // @[Core.scala:60:26, :70:22, :261:17, :262:36] assign rrd_uops_0_bits_ctrl_alu_dw = xcpt | decoder_11; // @[Core.scala:60:26, :70:22, :261:17, :263:36] assign rrd_uops_0_bits_ctrl_sel_alu1 = xcpt ? (io_imem_resp_0_bits_xcpt_0 ? 2'h2 : 2'h1) : decoder_9; // @[Core.scala:25:7, :60:26, :70:22, :261:17, :264:38, :266:40, :267:40] wire [2:0] _rrd_uops_0_bits_ctrl_sel_alu2_T = {2'h0, io_imem_resp_0_bits_edge_inst_0}; // @[Core.scala:25:7, :268:46] assign rrd_uops_0_bits_ctrl_sel_alu2 = xcpt ? (io_imem_resp_0_bits_xcpt_0 ? _rrd_uops_0_bits_ctrl_sel_alu2_T : 3'h0) : decoder_8; // @[Core.scala:25:7, :60:26, :70:22, :261:17, :265:38, :266:40, :268:{40,46}] assign xcpt_1 = _csr_io_interrupt | io_imem_resp_1_bits_xcpt_0 | rrd_illegal_insn_1; // @[Core.scala:25:7, :52:19, :60:26, :227:30] assign rrd_uops_1_bits_xcpt = xcpt_1; // @[Core.scala:60:26, :70:22] assign cause_1 = _csr_io_interrupt ? _csr_io_interrupt_cause : io_imem_resp_1_bits_xcpt_0 ? io_imem_resp_1_bits_xcpt_cause_0 : 64'h2; // @[Mux.scala:50:70] assign rrd_uops_1_bits_xcpt_cause = cause_1; // @[Mux.scala:50:70] assign rrd_uops_1_bits_ctrl_alu_fn = xcpt_1 ? 5'h0 : decoder_12_1; // @[Core.scala:60:26, :70:22, :261:17, :262:36] assign rrd_uops_1_bits_ctrl_alu_dw = xcpt_1 | decoder_11_1; // @[Core.scala:60:26, :70:22, :261:17, :263:36] assign rrd_uops_1_bits_ctrl_sel_alu1 = xcpt_1 ? (io_imem_resp_1_bits_xcpt_0 ? 2'h2 : 2'h1) : decoder_9_1; // @[Core.scala:25:7, :60:26, :70:22, :261:17, :264:38, :266:40, :267:40] wire [2:0] _rrd_uops_1_bits_ctrl_sel_alu2_T = {2'h0, io_imem_resp_1_bits_edge_inst_0}; // @[Core.scala:25:7, :268:46] assign rrd_uops_1_bits_ctrl_sel_alu2 = xcpt_1 ? (io_imem_resp_1_bits_xcpt_0 ? _rrd_uops_1_bits_ctrl_sel_alu2_T : 3'h0) : decoder_8_1; // @[Core.scala:25:7, :60:26, :70:22, :261:17, :265:38, :266:40, :268:{40,46}] assign _io_imem_resp_0_ready_T = ~rrd_stall_0; // @[Core.scala:106:23, :124:52, :275:30] assign io_imem_resp_0_ready_0 = _io_imem_resp_0_ready_T; // @[Core.scala:25:7, :275:30] assign _io_imem_resp_1_ready_T = ~rrd_stall_1; // @[Core.scala:106:23, :124:52, :275:30] assign io_imem_resp_1_ready_0 = _io_imem_resp_1_ready_T; // @[Core.scala:25:7, :275:30] reg [63:0] iregfile_0; // @[Core.scala:277:21] reg [63:0] iregfile_1; // @[Core.scala:277:21] reg [63:0] iregfile_2; // @[Core.scala:277:21] reg [63:0] iregfile_3; // @[Core.scala:277:21] reg [63:0] iregfile_4; // @[Core.scala:277:21] reg [63:0] iregfile_5; // @[Core.scala:277:21] reg [63:0] iregfile_6; // @[Core.scala:277:21] reg [63:0] iregfile_7; // @[Core.scala:277:21] reg [63:0] iregfile_8; // @[Core.scala:277:21] reg [63:0] iregfile_9; // @[Core.scala:277:21] reg [63:0] iregfile_10; // @[Core.scala:277:21] reg [63:0] iregfile_11; // @[Core.scala:277:21] reg [63:0] iregfile_12; // @[Core.scala:277:21] reg [63:0] iregfile_13; // @[Core.scala:277:21] reg [63:0] iregfile_14; // @[Core.scala:277:21] reg [63:0] iregfile_15; // @[Core.scala:277:21] reg [63:0] iregfile_16; // @[Core.scala:277:21] reg [63:0] iregfile_17; // @[Core.scala:277:21] reg [63:0] iregfile_18; // @[Core.scala:277:21] reg [63:0] iregfile_19; // @[Core.scala:277:21] reg [63:0] iregfile_20; // @[Core.scala:277:21] reg [63:0] iregfile_21; // @[Core.scala:277:21] reg [63:0] iregfile_22; // @[Core.scala:277:21] reg [63:0] iregfile_23; // @[Core.scala:277:21] reg [63:0] iregfile_24; // @[Core.scala:277:21] reg [63:0] iregfile_25; // @[Core.scala:277:21] reg [63:0] iregfile_26; // @[Core.scala:277:21] reg [63:0] iregfile_27; // @[Core.scala:277:21] reg [63:0] iregfile_28; // @[Core.scala:277:21] reg [63:0] iregfile_29; // @[Core.scala:277:21] reg [63:0] iregfile_30; // @[Core.scala:277:21] reg [63:0] iregfile_31; // @[Core.scala:277:21] reg isboard_1; // @[Core.scala:278:20] wire _isboard_bsy_T = isboard_1; // @[Core.scala:278:20, :285:38] reg isboard_2; // @[Core.scala:278:20] reg isboard_3; // @[Core.scala:278:20] reg isboard_4; // @[Core.scala:278:20] reg isboard_5; // @[Core.scala:278:20] reg isboard_6; // @[Core.scala:278:20] reg isboard_7; // @[Core.scala:278:20] reg isboard_8; // @[Core.scala:278:20] reg isboard_9; // @[Core.scala:278:20] reg isboard_10; // @[Core.scala:278:20] reg isboard_11; // @[Core.scala:278:20] reg isboard_12; // @[Core.scala:278:20] reg isboard_13; // @[Core.scala:278:20] reg isboard_14; // @[Core.scala:278:20] reg isboard_15; // @[Core.scala:278:20] reg isboard_16; // @[Core.scala:278:20] reg isboard_17; // @[Core.scala:278:20] reg isboard_18; // @[Core.scala:278:20] reg isboard_19; // @[Core.scala:278:20] reg isboard_20; // @[Core.scala:278:20] reg isboard_21; // @[Core.scala:278:20] reg isboard_22; // @[Core.scala:278:20] reg isboard_23; // @[Core.scala:278:20] reg isboard_24; // @[Core.scala:278:20] reg isboard_25; // @[Core.scala:278:20] reg isboard_26; // @[Core.scala:278:20] reg isboard_27; // @[Core.scala:278:20] reg isboard_28; // @[Core.scala:278:20] reg isboard_29; // @[Core.scala:278:20] reg isboard_30; // @[Core.scala:278:20] reg isboard_31; // @[Core.scala:278:20] wire isboard_clear_0; // @[Core.scala:279:31] wire isboard_clear_1; // @[Core.scala:279:31] wire isboard_clear_2; // @[Core.scala:279:31] wire isboard_clear_3; // @[Core.scala:279:31] wire isboard_clear_4; // @[Core.scala:279:31] wire isboard_clear_5; // @[Core.scala:279:31] wire isboard_clear_6; // @[Core.scala:279:31] wire isboard_clear_7; // @[Core.scala:279:31] wire isboard_clear_8; // @[Core.scala:279:31] wire isboard_clear_9; // @[Core.scala:279:31] wire isboard_clear_10; // @[Core.scala:279:31] wire isboard_clear_11; // @[Core.scala:279:31] wire isboard_clear_12; // @[Core.scala:279:31] wire isboard_clear_13; // @[Core.scala:279:31] wire isboard_clear_14; // @[Core.scala:279:31] wire isboard_clear_15; // @[Core.scala:279:31] wire isboard_clear_16; // @[Core.scala:279:31] wire isboard_clear_17; // @[Core.scala:279:31] wire isboard_clear_18; // @[Core.scala:279:31] wire isboard_clear_19; // @[Core.scala:279:31] wire isboard_clear_20; // @[Core.scala:279:31] wire isboard_clear_21; // @[Core.scala:279:31] wire isboard_clear_22; // @[Core.scala:279:31] wire isboard_clear_23; // @[Core.scala:279:31] wire isboard_clear_24; // @[Core.scala:279:31] wire isboard_clear_25; // @[Core.scala:279:31] wire isboard_clear_26; // @[Core.scala:279:31] wire isboard_clear_27; // @[Core.scala:279:31] wire isboard_clear_28; // @[Core.scala:279:31] wire isboard_clear_29; // @[Core.scala:279:31] wire isboard_clear_30; // @[Core.scala:279:31] wire isboard_clear_31; // @[Core.scala:279:31] wire isboard_set_0; // @[Core.scala:280:29] wire isboard_set_1; // @[Core.scala:280:29] wire isboard_set_2; // @[Core.scala:280:29] wire isboard_set_3; // @[Core.scala:280:29] wire isboard_set_4; // @[Core.scala:280:29] wire isboard_set_5; // @[Core.scala:280:29] wire isboard_set_6; // @[Core.scala:280:29] wire isboard_set_7; // @[Core.scala:280:29] wire isboard_set_8; // @[Core.scala:280:29] wire isboard_set_9; // @[Core.scala:280:29] wire isboard_set_10; // @[Core.scala:280:29] wire isboard_set_11; // @[Core.scala:280:29] wire isboard_set_12; // @[Core.scala:280:29] wire isboard_set_13; // @[Core.scala:280:29] wire isboard_set_14; // @[Core.scala:280:29] wire isboard_set_15; // @[Core.scala:280:29] wire isboard_set_16; // @[Core.scala:280:29] wire isboard_set_17; // @[Core.scala:280:29] wire isboard_set_18; // @[Core.scala:280:29] wire isboard_set_19; // @[Core.scala:280:29] wire isboard_set_20; // @[Core.scala:280:29] wire isboard_set_21; // @[Core.scala:280:29] wire isboard_set_22; // @[Core.scala:280:29] wire isboard_set_23; // @[Core.scala:280:29] wire isboard_set_24; // @[Core.scala:280:29] wire isboard_set_25; // @[Core.scala:280:29] wire isboard_set_26; // @[Core.scala:280:29] wire isboard_set_27; // @[Core.scala:280:29] wire isboard_set_28; // @[Core.scala:280:29] wire isboard_set_29; // @[Core.scala:280:29] wire isboard_set_30; // @[Core.scala:280:29] wire isboard_set_31; // @[Core.scala:280:29] wire _isboard_0_T = ~isboard_clear_0; // @[Core.scala:279:31, :282:34] wire _isboard_0_T_1 = _isboard_0_T; // @[Core.scala:282:{31,34}] wire _isboard_0_T_2 = _isboard_0_T_1 | isboard_set_0; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_1_T = ~isboard_clear_1; // @[Core.scala:279:31, :282:34] wire _isboard_1_T_1 = isboard_1 & _isboard_1_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_1_T_2 = _isboard_1_T_1 | isboard_set_1; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_2_T = ~isboard_clear_2; // @[Core.scala:279:31, :282:34] wire _isboard_2_T_1 = isboard_2 & _isboard_2_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_2_T_2 = _isboard_2_T_1 | isboard_set_2; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_3_T = ~isboard_clear_3; // @[Core.scala:279:31, :282:34] wire _isboard_3_T_1 = isboard_3 & _isboard_3_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_3_T_2 = _isboard_3_T_1 | isboard_set_3; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_4_T = ~isboard_clear_4; // @[Core.scala:279:31, :282:34] wire _isboard_4_T_1 = isboard_4 & _isboard_4_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_4_T_2 = _isboard_4_T_1 | isboard_set_4; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_5_T = ~isboard_clear_5; // @[Core.scala:279:31, :282:34] wire _isboard_5_T_1 = isboard_5 & _isboard_5_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_5_T_2 = _isboard_5_T_1 | isboard_set_5; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_6_T = ~isboard_clear_6; // @[Core.scala:279:31, :282:34] wire _isboard_6_T_1 = isboard_6 & _isboard_6_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_6_T_2 = _isboard_6_T_1 | isboard_set_6; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_7_T = ~isboard_clear_7; // @[Core.scala:279:31, :282:34] wire _isboard_7_T_1 = isboard_7 & _isboard_7_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_7_T_2 = _isboard_7_T_1 | isboard_set_7; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_8_T = ~isboard_clear_8; // @[Core.scala:279:31, :282:34] wire _isboard_8_T_1 = isboard_8 & _isboard_8_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_8_T_2 = _isboard_8_T_1 | isboard_set_8; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_9_T = ~isboard_clear_9; // @[Core.scala:279:31, :282:34] wire _isboard_9_T_1 = isboard_9 & _isboard_9_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_9_T_2 = _isboard_9_T_1 | isboard_set_9; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_10_T = ~isboard_clear_10; // @[Core.scala:279:31, :282:34] wire _isboard_10_T_1 = isboard_10 & _isboard_10_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_10_T_2 = _isboard_10_T_1 | isboard_set_10; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_11_T = ~isboard_clear_11; // @[Core.scala:279:31, :282:34] wire _isboard_11_T_1 = isboard_11 & _isboard_11_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_11_T_2 = _isboard_11_T_1 | isboard_set_11; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_12_T = ~isboard_clear_12; // @[Core.scala:279:31, :282:34] wire _isboard_12_T_1 = isboard_12 & _isboard_12_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_12_T_2 = _isboard_12_T_1 | isboard_set_12; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_13_T = ~isboard_clear_13; // @[Core.scala:279:31, :282:34] wire _isboard_13_T_1 = isboard_13 & _isboard_13_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_13_T_2 = _isboard_13_T_1 | isboard_set_13; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_14_T = ~isboard_clear_14; // @[Core.scala:279:31, :282:34] wire _isboard_14_T_1 = isboard_14 & _isboard_14_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_14_T_2 = _isboard_14_T_1 | isboard_set_14; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_15_T = ~isboard_clear_15; // @[Core.scala:279:31, :282:34] wire _isboard_15_T_1 = isboard_15 & _isboard_15_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_15_T_2 = _isboard_15_T_1 | isboard_set_15; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_16_T = ~isboard_clear_16; // @[Core.scala:279:31, :282:34] wire _isboard_16_T_1 = isboard_16 & _isboard_16_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_16_T_2 = _isboard_16_T_1 | isboard_set_16; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_17_T = ~isboard_clear_17; // @[Core.scala:279:31, :282:34] wire _isboard_17_T_1 = isboard_17 & _isboard_17_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_17_T_2 = _isboard_17_T_1 | isboard_set_17; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_18_T = ~isboard_clear_18; // @[Core.scala:279:31, :282:34] wire _isboard_18_T_1 = isboard_18 & _isboard_18_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_18_T_2 = _isboard_18_T_1 | isboard_set_18; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_19_T = ~isboard_clear_19; // @[Core.scala:279:31, :282:34] wire _isboard_19_T_1 = isboard_19 & _isboard_19_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_19_T_2 = _isboard_19_T_1 | isboard_set_19; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_20_T = ~isboard_clear_20; // @[Core.scala:279:31, :282:34] wire _isboard_20_T_1 = isboard_20 & _isboard_20_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_20_T_2 = _isboard_20_T_1 | isboard_set_20; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_21_T = ~isboard_clear_21; // @[Core.scala:279:31, :282:34] wire _isboard_21_T_1 = isboard_21 & _isboard_21_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_21_T_2 = _isboard_21_T_1 | isboard_set_21; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_22_T = ~isboard_clear_22; // @[Core.scala:279:31, :282:34] wire _isboard_22_T_1 = isboard_22 & _isboard_22_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_22_T_2 = _isboard_22_T_1 | isboard_set_22; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_23_T = ~isboard_clear_23; // @[Core.scala:279:31, :282:34] wire _isboard_23_T_1 = isboard_23 & _isboard_23_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_23_T_2 = _isboard_23_T_1 | isboard_set_23; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_24_T = ~isboard_clear_24; // @[Core.scala:279:31, :282:34] wire _isboard_24_T_1 = isboard_24 & _isboard_24_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_24_T_2 = _isboard_24_T_1 | isboard_set_24; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_25_T = ~isboard_clear_25; // @[Core.scala:279:31, :282:34] wire _isboard_25_T_1 = isboard_25 & _isboard_25_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_25_T_2 = _isboard_25_T_1 | isboard_set_25; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_26_T = ~isboard_clear_26; // @[Core.scala:279:31, :282:34] wire _isboard_26_T_1 = isboard_26 & _isboard_26_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_26_T_2 = _isboard_26_T_1 | isboard_set_26; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_27_T = ~isboard_clear_27; // @[Core.scala:279:31, :282:34] wire _isboard_27_T_1 = isboard_27 & _isboard_27_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_27_T_2 = _isboard_27_T_1 | isboard_set_27; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_28_T = ~isboard_clear_28; // @[Core.scala:279:31, :282:34] wire _isboard_28_T_1 = isboard_28 & _isboard_28_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_28_T_2 = _isboard_28_T_1 | isboard_set_28; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_29_T = ~isboard_clear_29; // @[Core.scala:279:31, :282:34] wire _isboard_29_T_1 = isboard_29 & _isboard_29_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_29_T_2 = _isboard_29_T_1 | isboard_set_29; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_30_T = ~isboard_clear_30; // @[Core.scala:279:31, :282:34] wire _isboard_30_T_1 = isboard_30 & _isboard_30_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_30_T_2 = _isboard_30_T_1 | isboard_set_30; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_31_T = ~isboard_clear_31; // @[Core.scala:279:31, :282:34] wire _isboard_31_T_1 = isboard_31 & _isboard_31_T; // @[Core.scala:278:20, :282:{31,34}] wire _isboard_31_T_2 = _isboard_31_T_1 | isboard_set_31; // @[Core.scala:280:29, :282:{31,53}] wire _isboard_bsy_T_1 = _isboard_bsy_T & isboard_2; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_2 = _isboard_bsy_T_1 & isboard_3; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_3 = _isboard_bsy_T_2 & isboard_4; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_4 = _isboard_bsy_T_3 & isboard_5; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_5 = _isboard_bsy_T_4 & isboard_6; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_6 = _isboard_bsy_T_5 & isboard_7; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_7 = _isboard_bsy_T_6 & isboard_8; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_8 = _isboard_bsy_T_7 & isboard_9; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_9 = _isboard_bsy_T_8 & isboard_10; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_10 = _isboard_bsy_T_9 & isboard_11; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_11 = _isboard_bsy_T_10 & isboard_12; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_12 = _isboard_bsy_T_11 & isboard_13; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_13 = _isboard_bsy_T_12 & isboard_14; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_14 = _isboard_bsy_T_13 & isboard_15; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_15 = _isboard_bsy_T_14 & isboard_16; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_16 = _isboard_bsy_T_15 & isboard_17; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_17 = _isboard_bsy_T_16 & isboard_18; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_18 = _isboard_bsy_T_17 & isboard_19; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_19 = _isboard_bsy_T_18 & isboard_20; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_20 = _isboard_bsy_T_19 & isboard_21; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_21 = _isboard_bsy_T_20 & isboard_22; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_22 = _isboard_bsy_T_21 & isboard_23; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_23 = _isboard_bsy_T_22 & isboard_24; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_24 = _isboard_bsy_T_23 & isboard_25; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_25 = _isboard_bsy_T_24 & isboard_26; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_26 = _isboard_bsy_T_25 & isboard_27; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_27 = _isboard_bsy_T_26 & isboard_28; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_28 = _isboard_bsy_T_27 & isboard_29; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_29 = _isboard_bsy_T_28 & isboard_30; // @[Core.scala:278:20, :285:38] wire _isboard_bsy_T_30 = _isboard_bsy_T_29 & isboard_31; // @[Core.scala:278:20, :285:38] wire isboard_bsy = ~_isboard_bsy_T_30; // @[Core.scala:285:{21,38}] wire _rrd_stall_data_0_T_5; // @[Core.scala:370:140] wire _rrd_stall_data_1_T_5; // @[Core.scala:370:140] wire rrd_stall_data_0; // @[Core.scala:303:28] wire rrd_stall_data_1; // @[Core.scala:303:28] wire _rrd_stall_1_T = rrd_stall_data_1; // @[Core.scala:303:28, :437:48] wire _rrd_irf_writes_0_valid_T; // @[Core.scala:380:50] wire [4:0] _rrd_irf_writes_0_bits_T; // @[MicroOp.scala:55:16] wire _rrd_irf_writes_1_valid_T; // @[Core.scala:380:50] wire [4:0] _rrd_irf_writes_1_bits_T; // @[MicroOp.scala:55:16] wire rrd_irf_writes_0_valid; // @[Core.scala:304:28] wire [4:0] rrd_irf_writes_0_bits; // @[Core.scala:304:28] wire rrd_irf_writes_1_valid; // @[Core.scala:304:28] wire [4:0] rrd_irf_writes_1_bits; // @[Core.scala:304:28] wire _rrd_p0_can_forward_x_to_m_T = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_1 = rrd_uops_0_bits_ctrl_wxd & _rrd_p0_can_forward_x_to_m_T; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_2 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_3 = _rrd_p0_can_forward_x_to_m_T_1 & _rrd_p0_can_forward_x_to_m_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _rrd_p0_can_forward_x_to_m_T_4 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_5 = _rrd_p0_can_forward_x_to_m_T_3 & _rrd_p0_can_forward_x_to_m_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _rrd_p0_can_forward_x_to_m_T_7 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_9 = _rrd_p0_can_forward_x_to_m_T_6 | _rrd_p0_can_forward_x_to_m_T_7; // @[package.scala:16:47, :81:59] wire _rrd_p0_can_forward_x_to_m_T_10 = _rrd_p0_can_forward_x_to_m_T_9 | _rrd_p0_can_forward_x_to_m_T_8; // @[package.scala:16:47, :81:59] wire _rrd_p0_can_forward_x_to_m_T_11 = ~_rrd_p0_can_forward_x_to_m_T_10; // @[MicroOp.scala:77:69] wire _rrd_p0_can_forward_x_to_m_T_12 = _rrd_p0_can_forward_x_to_m_T_5 & _rrd_p0_can_forward_x_to_m_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _rrd_p0_can_forward_x_to_m_T_13 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_14 = _rrd_p0_can_forward_x_to_m_T_12 & _rrd_p0_can_forward_x_to_m_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _rrd_p0_can_forward_x_to_m_T_15 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_16 = _rrd_p0_can_forward_x_to_m_T_14 & _rrd_p0_can_forward_x_to_m_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _rrd_p0_can_forward_x_to_m_T_17 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rrd_p0_can_forward_x_to_m_T_18 = _rrd_p0_can_forward_x_to_m_T_16 & _rrd_p0_can_forward_x_to_m_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _rrd_p0_can_forward_x_to_m_T_20 = _rrd_p0_can_forward_x_to_m_T_18; // @[MicroOp.scala:77:{103,117}] wire _rrd_p0_can_forward_x_to_m_T_21 = rrd_uops_0_bits_ctrl_wxd & _rrd_p0_can_forward_x_to_m_T_20; // @[Core.scala:70:22, :308:61] wire rrd_p0_can_forward_x_to_m = _rrd_p0_can_forward_x_to_m_T_21; // @[Core.scala:308:{61,90}] wire _rs1_can_forward_from_x_p0_T_33 = rrd_p0_can_forward_x_to_m; // @[Core.scala:308:90, :333:45] wire _rs2_can_forward_from_x_p0_T_33 = rrd_p0_can_forward_x_to_m; // @[Core.scala:308:90, :334:45] wire _rrd_p0_can_forward_w_to_l_T = rrd_uops_0_bits_ctrl_wxd & rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22, :309:61] wire rrd_p0_can_forward_w_to_l = _rrd_p0_can_forward_w_to_l_T; // @[Core.scala:309:{61,90}] wire _rs1_can_forward_from_w_p0_T_31 = rrd_p0_can_forward_w_to_l; // @[Core.scala:309:90, :335:45] wire _rs2_can_forward_from_w_p0_T_31 = rrd_p0_can_forward_w_to_l; // @[Core.scala:309:90, :336:45] wire [4:0] rs2 = rrd_uops_0_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra1_T_1 = rrd_uops_0_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra3_T = rrd_uops_0_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra2_T_1 = rrd_uops_0_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] rs3 = rrd_uops_0_bits_inst[31:27]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_0_bits_fra3_T_1 = rrd_uops_0_bits_inst[31:27]; // @[Core.scala:70:22] wire [4:0] rd = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] assign _rrd_irf_writes_0_bits_T = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] wire [4:0] _frs1_same_hazard_T_2 = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] wire [4:0] _frs2_same_hazard_T_2 = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] wire [4:0] _frs3_same_hazard_T_2 = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] wire [4:0] _frd_same_hazard_T_2 = rrd_uops_0_bits_inst[11:7]; // @[Core.scala:70:22] wire bypass_hit; // @[Core.scala:292:30] wire [31:0] _GEN_82 = {{isboard_31}, {isboard_30}, {isboard_29}, {isboard_28}, {isboard_27}, {isboard_26}, {isboard_25}, {isboard_24}, {isboard_23}, {isboard_22}, {isboard_21}, {isboard_20}, {isboard_19}, {isboard_18}, {isboard_17}, {isboard_16}, {isboard_15}, {isboard_14}, {isboard_13}, {isboard_12}, {isboard_11}, {isboard_10}, {isboard_9}, {isboard_8}, {isboard_7}, {isboard_6}, {isboard_5}, {isboard_4}, {isboard_3}, {isboard_2}, {isboard_1}, {1'h1}}; // @[Core.scala:278:20, :292:30] wire [63:0] rs1_data; // @[Core.scala:293:31] wire [31:0][63:0] _GEN_83 = {{iregfile_31}, {iregfile_30}, {iregfile_29}, {iregfile_28}, {iregfile_27}, {iregfile_26}, {iregfile_25}, {iregfile_24}, {iregfile_23}, {iregfile_22}, {iregfile_21}, {iregfile_20}, {iregfile_19}, {iregfile_18}, {iregfile_17}, {iregfile_16}, {iregfile_15}, {iregfile_14}, {iregfile_13}, {iregfile_12}, {iregfile_11}, {iregfile_10}, {iregfile_9}, {iregfile_8}, {iregfile_7}, {iregfile_6}, {iregfile_5}, {iregfile_4}, {iregfile_3}, {iregfile_2}, {iregfile_1}, {iregfile_0}}; // @[Core.scala:277:21, :293:31] wire _T_25 = ll_bypass_0_valid & ll_bypass_0_dst == rs1; // @[Core.scala:96:40, :295:{21,30}] wire _T_27 = wb_bypasses_0_valid & wb_bypasses_0_dst == rs1; // @[Core.scala:95:62, :295:{21,30}] wire _T_29 = wb_bypasses_1_valid & wb_bypasses_1_dst == rs1; // @[Core.scala:95:62, :295:{21,30}] wire _T_31 = com_bypasses_0_valid & com_bypasses_0_dst == rs1; // @[Core.scala:94:63, :295:{21,30}] wire _T_33 = com_bypasses_1_valid & com_bypasses_1_dst == rs1; // @[Core.scala:94:63, :295:{21,30}] wire _T_35 = mem_bypasses_0_valid & mem_bypasses_0_dst == rs1; // @[Core.scala:93:63, :295:{21,30}] wire _T_37 = mem_bypasses_1_valid & mem_bypasses_1_dst == rs1; // @[Core.scala:93:63, :295:{21,30}] wire _T_39 = ex_bypasses_0_valid & ex_bypasses_0_dst == rs1; // @[Core.scala:92:62, :295:{21,30}] wire _T_41 = ex_bypasses_1_valid & ex_bypasses_1_dst == rs1; // @[Core.scala:92:62, :295:{21,30}] assign bypass_hit = _T_41 ? ex_bypasses_1_can_bypass : _T_39 ? ex_bypasses_0_can_bypass : _T_37 ? mem_bypasses_1_can_bypass : _T_35 ? mem_bypasses_0_can_bypass : _T_33 ? com_bypasses_1_can_bypass : _T_31 ? com_bypasses_0_can_bypass : _T_29 ? wb_bypasses_1_can_bypass : _T_27 ? wb_bypasses_0_can_bypass : _T_25 ? ll_bypass_0_can_bypass : _GEN_82[rs1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rs1_data = _T_41 ? ex_bypasses_1_data : _T_39 ? ex_bypasses_0_data : _T_37 ? mem_bypasses_1_data : _T_35 ? mem_bypasses_0_data : _T_33 ? com_bypasses_1_data : _T_31 ? com_bypasses_0_data : _T_29 ? wb_bypasses_1_data : _T_27 ? wb_bypasses_0_data : _T_25 ? ll_bypass_0_data : _GEN_83[rs1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rs1_older_hazard = ~bypass_hit; // @[Core.scala:292:30, :300:6] wire _rs1_data_hazard_T = rs1_older_hazard; // @[Core.scala:300:6, :360:45] wire bypass_hit_1; // @[Core.scala:292:30] wire [63:0] rs2_data; // @[Core.scala:293:31] wire _T_43 = ll_bypass_0_valid & ll_bypass_0_dst == rs2; // @[Core.scala:96:40, :295:{21,30}] wire _T_45 = wb_bypasses_0_valid & wb_bypasses_0_dst == rs2; // @[Core.scala:95:62, :295:{21,30}] wire _T_47 = wb_bypasses_1_valid & wb_bypasses_1_dst == rs2; // @[Core.scala:95:62, :295:{21,30}] wire _T_49 = com_bypasses_0_valid & com_bypasses_0_dst == rs2; // @[Core.scala:94:63, :295:{21,30}] wire _T_51 = com_bypasses_1_valid & com_bypasses_1_dst == rs2; // @[Core.scala:94:63, :295:{21,30}] wire _T_53 = mem_bypasses_0_valid & mem_bypasses_0_dst == rs2; // @[Core.scala:93:63, :295:{21,30}] wire _T_55 = mem_bypasses_1_valid & mem_bypasses_1_dst == rs2; // @[Core.scala:93:63, :295:{21,30}] wire _T_57 = ex_bypasses_0_valid & ex_bypasses_0_dst == rs2; // @[Core.scala:92:62, :295:{21,30}] wire _T_59 = ex_bypasses_1_valid & ex_bypasses_1_dst == rs2; // @[Core.scala:92:62, :295:{21,30}] assign bypass_hit_1 = _T_59 ? ex_bypasses_1_can_bypass : _T_57 ? ex_bypasses_0_can_bypass : _T_55 ? mem_bypasses_1_can_bypass : _T_53 ? mem_bypasses_0_can_bypass : _T_51 ? com_bypasses_1_can_bypass : _T_49 ? com_bypasses_0_can_bypass : _T_47 ? wb_bypasses_1_can_bypass : _T_45 ? wb_bypasses_0_can_bypass : _T_43 ? ll_bypass_0_can_bypass : _GEN_82[rs2]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rs2_data = _T_59 ? ex_bypasses_1_data : _T_57 ? ex_bypasses_0_data : _T_55 ? mem_bypasses_1_data : _T_53 ? mem_bypasses_0_data : _T_51 ? com_bypasses_1_data : _T_49 ? com_bypasses_0_data : _T_47 ? wb_bypasses_1_data : _T_45 ? wb_bypasses_0_data : _T_43 ? ll_bypass_0_data : _GEN_83[rs2]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rs2_older_hazard = ~bypass_hit_1; // @[Core.scala:292:30, :300:6] wire _rs2_data_hazard_T = rs2_older_hazard; // @[Core.scala:300:6, :361:45] wire rd_older_hazard_bypass_hit; // @[Core.scala:292:30] wire rd_older_hazard_bypass_data; // @[Core.scala:293:31] wire _rd_older_hazard_T = ll_bypass_0_dst == rd; // @[Core.scala:96:40, :295:30] wire _rd_older_hazard_T_1 = ll_bypass_0_valid & _rd_older_hazard_T; // @[Core.scala:96:40, :295:{21,30}] wire _rd_older_hazard_T_2 = wb_bypasses_0_dst == rd; // @[Core.scala:95:62, :295:30] wire _rd_older_hazard_T_3 = wb_bypasses_0_valid & _rd_older_hazard_T_2; // @[Core.scala:95:62, :295:{21,30}] wire _rd_older_hazard_T_4 = wb_bypasses_1_dst == rd; // @[Core.scala:95:62, :295:30] wire _rd_older_hazard_T_5 = wb_bypasses_1_valid & _rd_older_hazard_T_4; // @[Core.scala:95:62, :295:{21,30}] wire _rd_older_hazard_T_6 = com_bypasses_0_dst == rd; // @[Core.scala:94:63, :295:30] wire _rd_older_hazard_T_7 = com_bypasses_0_valid & _rd_older_hazard_T_6; // @[Core.scala:94:63, :295:{21,30}] wire _rd_older_hazard_T_8 = com_bypasses_1_dst == rd; // @[Core.scala:94:63, :295:30] wire _rd_older_hazard_T_9 = com_bypasses_1_valid & _rd_older_hazard_T_8; // @[Core.scala:94:63, :295:{21,30}] wire _rd_older_hazard_T_10 = mem_bypasses_0_dst == rd; // @[Core.scala:93:63, :295:30] wire _rd_older_hazard_T_11 = mem_bypasses_0_valid & _rd_older_hazard_T_10; // @[Core.scala:93:63, :295:{21,30}] wire _rd_older_hazard_T_12 = mem_bypasses_1_dst == rd; // @[Core.scala:93:63, :295:30] wire _rd_older_hazard_T_13 = mem_bypasses_1_valid & _rd_older_hazard_T_12; // @[Core.scala:93:63, :295:{21,30}] wire _rd_older_hazard_T_14 = ex_bypasses_0_dst == rd; // @[Core.scala:92:62, :295:30] wire _rd_older_hazard_T_15 = ex_bypasses_0_valid & _rd_older_hazard_T_14; // @[Core.scala:92:62, :295:{21,30}] wire _rd_older_hazard_T_16 = ex_bypasses_1_dst == rd; // @[Core.scala:92:62, :295:30] wire _rd_older_hazard_T_17 = ex_bypasses_1_valid & _rd_older_hazard_T_16; // @[Core.scala:92:62, :295:{21,30}] assign rd_older_hazard_bypass_hit = _rd_older_hazard_T_17 ? ex_bypasses_1_can_bypass : _rd_older_hazard_T_15 ? ex_bypasses_0_can_bypass : _rd_older_hazard_T_13 ? mem_bypasses_1_can_bypass : _rd_older_hazard_T_11 ? mem_bypasses_0_can_bypass : _rd_older_hazard_T_9 ? com_bypasses_1_can_bypass : _rd_older_hazard_T_7 ? com_bypasses_0_can_bypass : _rd_older_hazard_T_5 ? wb_bypasses_1_can_bypass : _rd_older_hazard_T_3 ? wb_bypasses_0_can_bypass : _rd_older_hazard_T_1 ? ll_bypass_0_can_bypass : _GEN_82[rd]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rd_older_hazard_bypass_data = _rd_older_hazard_T_17 ? ex_bypasses_1_data[0] : _rd_older_hazard_T_15 ? ex_bypasses_0_data[0] : _rd_older_hazard_T_13 ? mem_bypasses_1_data[0] : _rd_older_hazard_T_11 ? mem_bypasses_0_data[0] : _rd_older_hazard_T_9 ? com_bypasses_1_data[0] : _rd_older_hazard_T_7 ? com_bypasses_0_data[0] : _rd_older_hazard_T_5 ? wb_bypasses_1_data[0] : _rd_older_hazard_T_3 ? wb_bypasses_0_data[0] : _rd_older_hazard_T_1 & ll_bypass_0_data[0]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rd_older_hazard = ~rd_older_hazard_bypass_hit; // @[Core.scala:292:30, :300:6] wire _rd_data_hazard_T = rd_older_hazard; // @[Core.scala:300:6, :362:44] wire _rrd_uops_0_bits_rs1_data_T = ~(|rs1); // @[Core.scala:322:42] wire [63:0] _rrd_uops_0_bits_rs1_data_T_1 = _rrd_uops_0_bits_rs1_data_T ? 64'h0 : rs1_data; // @[Core.scala:293:31, :322:{37,42}] assign rrd_uops_0_bits_rs1_data = rrd_uops_0_bits_xcpt & rrd_uops_0_bits_xcpt_cause == 64'h2 ? {32'h0, io_imem_resp_0_bits_raw_inst_0} : _rrd_uops_0_bits_rs1_data_T_1; // @[Core.scala:25:7, :70:22, :322:{31,37}, :323:{33,64,98}, :324:33] wire _rrd_uops_0_bits_rs2_data_T = ~(|rs2); // @[Core.scala:326:42] assign _rrd_uops_0_bits_rs2_data_T_1 = _rrd_uops_0_bits_rs2_data_T ? 64'h0 : rs2_data; // @[Core.scala:293:31, :326:{37,42}] assign rrd_uops_0_bits_rs2_data = _rrd_uops_0_bits_rs2_data_T_1; // @[Core.scala:70:22, :326:37] wire _rs1_w0_hit_T = rrd_irf_writes_0_bits == rs1; // @[Core.scala:304:28, :328:72] wire rs1_w0_hit = rrd_irf_writes_0_valid & _rs1_w0_hit_T; // @[Core.scala:304:28, :328:{46,72}] wire _rs2_w0_hit_T = rrd_irf_writes_0_bits == rs2; // @[Core.scala:304:28, :329:72] wire rs2_w0_hit = rrd_irf_writes_0_valid & _rs2_w0_hit_T; // @[Core.scala:304:28, :329:{46,72}] wire memalu_will_be_latealu = mem_uops_reg_0_valid & mem_uops_reg_0_bits_uses_latealu; // @[Core.scala:72:25, :331:56] wire _rs1_can_forward_from_x_p0_T_2 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_3 = rrd_uops_0_bits_ctrl_wxd & _rs1_can_forward_from_x_p0_T_2; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_4 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_5 = _rs1_can_forward_from_x_p0_T_3 & _rs1_can_forward_from_x_p0_T_4; // @[MicroOp.scala:77:{27,40,43}] wire _rs1_can_forward_from_x_p0_T_6 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_7 = _rs1_can_forward_from_x_p0_T_5 & _rs1_can_forward_from_x_p0_T_6; // @[MicroOp.scala:77:{40,53,56}] wire _rs1_can_forward_from_x_p0_T_9 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_11 = _rs1_can_forward_from_x_p0_T_8 | _rs1_can_forward_from_x_p0_T_9; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_x_p0_T_12 = _rs1_can_forward_from_x_p0_T_11 | _rs1_can_forward_from_x_p0_T_10; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_x_p0_T_13 = ~_rs1_can_forward_from_x_p0_T_12; // @[MicroOp.scala:77:69] wire _rs1_can_forward_from_x_p0_T_14 = _rs1_can_forward_from_x_p0_T_7 & _rs1_can_forward_from_x_p0_T_13; // @[MicroOp.scala:77:{53,66,69}] wire _rs1_can_forward_from_x_p0_T_15 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_16 = _rs1_can_forward_from_x_p0_T_14 & _rs1_can_forward_from_x_p0_T_15; // @[MicroOp.scala:77:{66,77,80}] wire _rs1_can_forward_from_x_p0_T_17 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_18 = _rs1_can_forward_from_x_p0_T_16 & _rs1_can_forward_from_x_p0_T_17; // @[MicroOp.scala:77:{77,89,92}] wire _rs1_can_forward_from_x_p0_T_19 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_20 = _rs1_can_forward_from_x_p0_T_18 & _rs1_can_forward_from_x_p0_T_19; // @[MicroOp.scala:77:{89,103,106}] wire _rs1_can_forward_from_x_p0_T_22 = _rs1_can_forward_from_x_p0_T_20; // @[MicroOp.scala:77:{103,117}] wire _GEN_84 = rrd_uops_0_bits_ctrl_branch | rrd_uops_0_bits_ctrl_jal; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_24; // @[MicroOp.scala:74:25] assign _rs1_can_forward_from_x_p0_T_24 = _GEN_84; // @[MicroOp.scala:74:25] wire _rs2_can_forward_from_x_p0_T_24; // @[MicroOp.scala:74:25] assign _rs2_can_forward_from_x_p0_T_24 = _GEN_84; // @[MicroOp.scala:74:25] wire _rs1_can_forward_from_w_p0_T_24; // @[MicroOp.scala:74:25] assign _rs1_can_forward_from_w_p0_T_24 = _GEN_84; // @[MicroOp.scala:74:25] wire _rs2_can_forward_from_w_p0_T_24; // @[MicroOp.scala:74:25] assign _rs2_can_forward_from_w_p0_T_24 = _GEN_84; // @[MicroOp.scala:74:25] wire _brjmp_T; // @[MicroOp.scala:74:25] assign _brjmp_T = _GEN_84; // @[MicroOp.scala:74:25] wire _is_pipe0_T_23; // @[MicroOp.scala:74:25] assign _is_pipe0_T_23 = _GEN_84; // @[MicroOp.scala:74:25] wire _rs1_can_forward_from_x_p0_T_25 = _rs1_can_forward_from_x_p0_T_24 | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_26 = ~_rs1_can_forward_from_x_p0_T_25; // @[Core.scala:333:120] wire _rs1_can_forward_from_x_p0_T_30 = |rs1; // @[Core.scala:322:42, :333:180] wire _rs1_can_forward_from_x_p0_T_32 = ~memalu_will_be_latealu; // @[Core.scala:331:56, :333:191] wire _rs2_can_forward_from_x_p0_T_2 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_3 = rrd_uops_0_bits_ctrl_wxd & _rs2_can_forward_from_x_p0_T_2; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_4 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_5 = _rs2_can_forward_from_x_p0_T_3 & _rs2_can_forward_from_x_p0_T_4; // @[MicroOp.scala:77:{27,40,43}] wire _rs2_can_forward_from_x_p0_T_6 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_7 = _rs2_can_forward_from_x_p0_T_5 & _rs2_can_forward_from_x_p0_T_6; // @[MicroOp.scala:77:{40,53,56}] wire _rs2_can_forward_from_x_p0_T_9 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_11 = _rs2_can_forward_from_x_p0_T_8 | _rs2_can_forward_from_x_p0_T_9; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_x_p0_T_12 = _rs2_can_forward_from_x_p0_T_11 | _rs2_can_forward_from_x_p0_T_10; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_x_p0_T_13 = ~_rs2_can_forward_from_x_p0_T_12; // @[MicroOp.scala:77:69] wire _rs2_can_forward_from_x_p0_T_14 = _rs2_can_forward_from_x_p0_T_7 & _rs2_can_forward_from_x_p0_T_13; // @[MicroOp.scala:77:{53,66,69}] wire _rs2_can_forward_from_x_p0_T_15 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_16 = _rs2_can_forward_from_x_p0_T_14 & _rs2_can_forward_from_x_p0_T_15; // @[MicroOp.scala:77:{66,77,80}] wire _rs2_can_forward_from_x_p0_T_17 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_18 = _rs2_can_forward_from_x_p0_T_16 & _rs2_can_forward_from_x_p0_T_17; // @[MicroOp.scala:77:{77,89,92}] wire _rs2_can_forward_from_x_p0_T_19 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_20 = _rs2_can_forward_from_x_p0_T_18 & _rs2_can_forward_from_x_p0_T_19; // @[MicroOp.scala:77:{89,103,106}] wire _rs2_can_forward_from_x_p0_T_22 = _rs2_can_forward_from_x_p0_T_20; // @[MicroOp.scala:77:{103,117}] wire _rs2_can_forward_from_x_p0_T_25 = _rs2_can_forward_from_x_p0_T_24 | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_26 = ~_rs2_can_forward_from_x_p0_T_25; // @[Core.scala:334:120] wire _rs2_can_forward_from_x_p0_T_30 = |rs2; // @[Core.scala:326:42, :334:180] wire _rs2_can_forward_from_x_p0_T_32 = ~memalu_will_be_latealu; // @[Core.scala:331:56, :333:191, :334:191] wire _rs1_can_forward_from_w_p0_T_2 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_3 = rrd_uops_0_bits_ctrl_wxd & _rs1_can_forward_from_w_p0_T_2; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_4 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_5 = _rs1_can_forward_from_w_p0_T_3 & _rs1_can_forward_from_w_p0_T_4; // @[MicroOp.scala:77:{27,40,43}] wire _rs1_can_forward_from_w_p0_T_6 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_7 = _rs1_can_forward_from_w_p0_T_5 & _rs1_can_forward_from_w_p0_T_6; // @[MicroOp.scala:77:{40,53,56}] wire _rs1_can_forward_from_w_p0_T_9 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_11 = _rs1_can_forward_from_w_p0_T_8 | _rs1_can_forward_from_w_p0_T_9; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_w_p0_T_12 = _rs1_can_forward_from_w_p0_T_11 | _rs1_can_forward_from_w_p0_T_10; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_w_p0_T_13 = ~_rs1_can_forward_from_w_p0_T_12; // @[MicroOp.scala:77:69] wire _rs1_can_forward_from_w_p0_T_14 = _rs1_can_forward_from_w_p0_T_7 & _rs1_can_forward_from_w_p0_T_13; // @[MicroOp.scala:77:{53,66,69}] wire _rs1_can_forward_from_w_p0_T_15 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_16 = _rs1_can_forward_from_w_p0_T_14 & _rs1_can_forward_from_w_p0_T_15; // @[MicroOp.scala:77:{66,77,80}] wire _rs1_can_forward_from_w_p0_T_17 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_18 = _rs1_can_forward_from_w_p0_T_16 & _rs1_can_forward_from_w_p0_T_17; // @[MicroOp.scala:77:{77,89,92}] wire _rs1_can_forward_from_w_p0_T_19 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_20 = _rs1_can_forward_from_w_p0_T_18 & _rs1_can_forward_from_w_p0_T_19; // @[MicroOp.scala:77:{89,103,106}] wire _rs1_can_forward_from_w_p0_T_22 = _rs1_can_forward_from_w_p0_T_20; // @[MicroOp.scala:77:{103,117}] wire _rs1_can_forward_from_w_p0_T_25 = _rs1_can_forward_from_w_p0_T_24 | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_26 = ~_rs1_can_forward_from_w_p0_T_25; // @[Core.scala:335:120] wire _rs1_can_forward_from_w_p0_T_30 = |rs1; // @[Core.scala:322:42, :335:180] wire _rs2_can_forward_from_w_p0_T_2 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_3 = rrd_uops_0_bits_ctrl_wxd & _rs2_can_forward_from_w_p0_T_2; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_4 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_5 = _rs2_can_forward_from_w_p0_T_3 & _rs2_can_forward_from_w_p0_T_4; // @[MicroOp.scala:77:{27,40,43}] wire _rs2_can_forward_from_w_p0_T_6 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_7 = _rs2_can_forward_from_w_p0_T_5 & _rs2_can_forward_from_w_p0_T_6; // @[MicroOp.scala:77:{40,53,56}] wire _rs2_can_forward_from_w_p0_T_9 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_11 = _rs2_can_forward_from_w_p0_T_8 | _rs2_can_forward_from_w_p0_T_9; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_w_p0_T_12 = _rs2_can_forward_from_w_p0_T_11 | _rs2_can_forward_from_w_p0_T_10; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_w_p0_T_13 = ~_rs2_can_forward_from_w_p0_T_12; // @[MicroOp.scala:77:69] wire _rs2_can_forward_from_w_p0_T_14 = _rs2_can_forward_from_w_p0_T_7 & _rs2_can_forward_from_w_p0_T_13; // @[MicroOp.scala:77:{53,66,69}] wire _rs2_can_forward_from_w_p0_T_15 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_16 = _rs2_can_forward_from_w_p0_T_14 & _rs2_can_forward_from_w_p0_T_15; // @[MicroOp.scala:77:{66,77,80}] wire _rs2_can_forward_from_w_p0_T_17 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_18 = _rs2_can_forward_from_w_p0_T_16 & _rs2_can_forward_from_w_p0_T_17; // @[MicroOp.scala:77:{77,89,92}] wire _rs2_can_forward_from_w_p0_T_19 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_20 = _rs2_can_forward_from_w_p0_T_18 & _rs2_can_forward_from_w_p0_T_19; // @[MicroOp.scala:77:{89,103,106}] wire _rs2_can_forward_from_w_p0_T_22 = _rs2_can_forward_from_w_p0_T_20; // @[MicroOp.scala:77:{103,117}] wire _rs2_can_forward_from_w_p0_T_25 = _rs2_can_forward_from_w_p0_T_24 | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_26 = ~_rs2_can_forward_from_w_p0_T_25; // @[Core.scala:336:120] wire _rs2_can_forward_from_w_p0_T_30 = |rs2; // @[Core.scala:326:42, :336:180] wire _rs1_data_hazard_T_1 = _rs1_data_hazard_T & rrd_uops_0_bits_ctrl_rxs1; // @[Core.scala:70:22, :360:{45,65}] wire _rs1_data_hazard_T_2 = |rs1; // @[Core.scala:322:42, :360:85] wire rs1_data_hazard = _rs1_data_hazard_T_1 & _rs1_data_hazard_T_2; // @[Core.scala:360:{65,78,85}] wire _rs2_data_hazard_T_1 = _rs2_data_hazard_T & rrd_uops_0_bits_ctrl_rxs2; // @[Core.scala:70:22, :361:{45,65}] wire _rs2_data_hazard_T_2 = |rs2; // @[Core.scala:326:42, :361:85] wire rs2_data_hazard = _rs2_data_hazard_T_1 & _rs2_data_hazard_T_2; // @[Core.scala:361:{65,78,85}] wire _rd_data_hazard_T_1 = _rd_data_hazard_T & rrd_uops_0_bits_ctrl_wxd; // @[Core.scala:70:22, :362:{44,63}] wire _rd_data_hazard_T_2 = |rd; // @[Core.scala:362:81] wire rd_data_hazard = _rd_data_hazard_T_1 & _rd_data_hazard_T_2; // @[Core.scala:362:{63,75,81}] wire _rrd_stall_data_0_T = rs1_data_hazard | rs2_data_hazard; // @[Core.scala:360:78, :361:78, :370:43] wire _rrd_stall_data_0_T_1 = _rrd_stall_data_0_T | rd_data_hazard; // @[Core.scala:362:75, :370:{43,62}] wire _rrd_stall_data_0_T_2 = _rrd_stall_data_0_T_1; // @[Core.scala:370:{62,80}] wire _rrd_stall_data_0_T_3 = _rrd_stall_data_0_T_2; // @[Core.scala:370:{80,100}] wire _rrd_stall_data_0_T_4 = _rrd_stall_data_0_T_3; // @[Core.scala:370:{100,120}] assign _rrd_stall_data_0_T_5 = _rrd_stall_data_0_T_4; // @[Core.scala:370:{120,140}] assign rrd_stall_data_0 = _rrd_stall_data_0_T_5; // @[Core.scala:303:28, :370:140] wire _rrd_uops_0_bits_uses_memalu_T = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_1 = rrd_uops_0_bits_ctrl_wxd & _rrd_uops_0_bits_uses_memalu_T; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_2 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_3 = _rrd_uops_0_bits_uses_memalu_T_1 & _rrd_uops_0_bits_uses_memalu_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _rrd_uops_0_bits_uses_memalu_T_4 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_5 = _rrd_uops_0_bits_uses_memalu_T_3 & _rrd_uops_0_bits_uses_memalu_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _rrd_uops_0_bits_uses_memalu_T_7 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_9 = _rrd_uops_0_bits_uses_memalu_T_6 | _rrd_uops_0_bits_uses_memalu_T_7; // @[package.scala:16:47, :81:59] wire _rrd_uops_0_bits_uses_memalu_T_10 = _rrd_uops_0_bits_uses_memalu_T_9 | _rrd_uops_0_bits_uses_memalu_T_8; // @[package.scala:16:47, :81:59] wire _rrd_uops_0_bits_uses_memalu_T_11 = ~_rrd_uops_0_bits_uses_memalu_T_10; // @[MicroOp.scala:77:69] wire _rrd_uops_0_bits_uses_memalu_T_12 = _rrd_uops_0_bits_uses_memalu_T_5 & _rrd_uops_0_bits_uses_memalu_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _rrd_uops_0_bits_uses_memalu_T_13 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_14 = _rrd_uops_0_bits_uses_memalu_T_12 & _rrd_uops_0_bits_uses_memalu_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _rrd_uops_0_bits_uses_memalu_T_15 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_16 = _rrd_uops_0_bits_uses_memalu_T_14 & _rrd_uops_0_bits_uses_memalu_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _rrd_uops_0_bits_uses_memalu_T_17 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_memalu_T_18 = _rrd_uops_0_bits_uses_memalu_T_16 & _rrd_uops_0_bits_uses_memalu_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _rrd_uops_0_bits_uses_memalu_T_20 = _rrd_uops_0_bits_uses_memalu_T_18; // @[MicroOp.scala:77:{103,117}] wire _rrd_uops_0_bits_uses_latealu_T = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_1 = rrd_uops_0_bits_ctrl_wxd & _rrd_uops_0_bits_uses_latealu_T; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_2 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_3 = _rrd_uops_0_bits_uses_latealu_T_1 & _rrd_uops_0_bits_uses_latealu_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _rrd_uops_0_bits_uses_latealu_T_4 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_5 = _rrd_uops_0_bits_uses_latealu_T_3 & _rrd_uops_0_bits_uses_latealu_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _rrd_uops_0_bits_uses_latealu_T_7 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_9 = _rrd_uops_0_bits_uses_latealu_T_6 | _rrd_uops_0_bits_uses_latealu_T_7; // @[package.scala:16:47, :81:59] wire _rrd_uops_0_bits_uses_latealu_T_10 = _rrd_uops_0_bits_uses_latealu_T_9 | _rrd_uops_0_bits_uses_latealu_T_8; // @[package.scala:16:47, :81:59] wire _rrd_uops_0_bits_uses_latealu_T_11 = ~_rrd_uops_0_bits_uses_latealu_T_10; // @[MicroOp.scala:77:69] wire _rrd_uops_0_bits_uses_latealu_T_12 = _rrd_uops_0_bits_uses_latealu_T_5 & _rrd_uops_0_bits_uses_latealu_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _rrd_uops_0_bits_uses_latealu_T_13 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_14 = _rrd_uops_0_bits_uses_latealu_T_12 & _rrd_uops_0_bits_uses_latealu_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _rrd_uops_0_bits_uses_latealu_T_15 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_16 = _rrd_uops_0_bits_uses_latealu_T_14 & _rrd_uops_0_bits_uses_latealu_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _rrd_uops_0_bits_uses_latealu_T_17 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rrd_uops_0_bits_uses_latealu_T_18 = _rrd_uops_0_bits_uses_latealu_T_16 & _rrd_uops_0_bits_uses_latealu_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _rrd_uops_0_bits_uses_latealu_T_20 = _rrd_uops_0_bits_uses_latealu_T_18; // @[MicroOp.scala:77:{103,117}] assign _rrd_irf_writes_0_valid_T = rrd_uops_0_valid & rrd_uops_0_bits_ctrl_wxd; // @[Core.scala:70:22, :380:50] assign rrd_irf_writes_0_valid = _rrd_irf_writes_0_valid_T; // @[Core.scala:304:28, :380:50] assign rrd_irf_writes_0_bits = _rrd_irf_writes_0_bits_T; // @[Core.scala:304:28] wire _T_62 = rrd_uops_0_valid & rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22, :383:29] assign rrd_uops_0_bits_fra1 = _T_62 ? (rrd_uops_0_bits_fp_ctrl_ren2 & rrd_uops_0_bits_fp_ctrl_swap12 ? _rrd_uops_0_bits_fra1_T_1 : rrd_uops_0_bits_fp_ctrl_ren1 & ~rrd_uops_0_bits_fp_ctrl_swap12 ? _rrd_uops_0_bits_fra1_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :384:27, :385:{15,32,56}, :388:27, :389:{32,56}] assign rrd_uops_0_bits_fra2 = _T_62 ? (rrd_uops_0_bits_fp_ctrl_ren2 & ~rrd_uops_0_bits_fp_ctrl_swap12 & ~rrd_uops_0_bits_fp_ctrl_swap23 ? _rrd_uops_0_bits_fra2_T_1 : rrd_uops_0_bits_fp_ctrl_ren1 & rrd_uops_0_bits_fp_ctrl_swap12 ? _rrd_uops_0_bits_fra2_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :384:27, :386:{32,56}, :388:27, :391:{15,31,34,51,75}] assign rrd_uops_0_bits_fra3 = _T_62 ? (rrd_uops_0_bits_fp_ctrl_ren3 ? _rrd_uops_0_bits_fra3_T_1 : rrd_uops_0_bits_fp_ctrl_ren2 & rrd_uops_0_bits_fp_ctrl_swap23 ? _rrd_uops_0_bits_fra3_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :388:27, :390:{32,56}, :393:27, :394:31] wire _rrd_uops_0_bits_mem_size_T = |rs2; // @[Core.scala:326:42, :399:44] wire _rrd_uops_0_bits_mem_size_T_1 = |rs1; // @[Core.scala:322:42, :399:57] wire [1:0] _rrd_uops_0_bits_mem_size_T_2 = {_rrd_uops_0_bits_mem_size_T, _rrd_uops_0_bits_mem_size_T_1}; // @[Core.scala:399:{39,44,57}] assign rrd_uops_0_bits_mem_size = _T_67 | rrd_uops_0_bits_ctrl_mem_cmd == 5'h5 ? _rrd_uops_0_bits_mem_size_T_2 : io_imem_resp_0_bits_mem_size_0; // @[Core.scala:25:7, :70:22, :157:12, :239:43, :398:56, :399:{33,39}] wire [4:0] rs2_1 = rrd_uops_1_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra1_T_1 = rrd_uops_1_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra3_T = rrd_uops_1_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra2_T_1 = rrd_uops_1_bits_inst[24:20]; // @[Core.scala:70:22] wire [4:0] rs3_1 = rrd_uops_1_bits_inst[31:27]; // @[Core.scala:70:22] wire [4:0] _rrd_uops_1_bits_fra3_T_1 = rrd_uops_1_bits_inst[31:27]; // @[Core.scala:70:22] wire [4:0] rd_1 = rrd_uops_1_bits_inst[11:7]; // @[Core.scala:70:22] assign _rrd_irf_writes_1_bits_T = rrd_uops_1_bits_inst[11:7]; // @[Core.scala:70:22] assign rrd_uops_1_bits_sfb_shadow = sfb_shadow_1; // @[Core.scala:70:22, :317:33] wire bypass_hit_2; // @[Core.scala:292:30] wire [63:0] rs1_data_1; // @[Core.scala:293:31] wire _T_71 = ll_bypass_0_valid & ll_bypass_0_dst == rs1_1; // @[Core.scala:96:40, :295:{21,30}] wire _T_73 = wb_bypasses_0_valid & wb_bypasses_0_dst == rs1_1; // @[Core.scala:95:62, :295:{21,30}] wire _T_75 = wb_bypasses_1_valid & wb_bypasses_1_dst == rs1_1; // @[Core.scala:95:62, :295:{21,30}] wire _T_77 = com_bypasses_0_valid & com_bypasses_0_dst == rs1_1; // @[Core.scala:94:63, :295:{21,30}] wire _T_79 = com_bypasses_1_valid & com_bypasses_1_dst == rs1_1; // @[Core.scala:94:63, :295:{21,30}] wire _T_81 = mem_bypasses_0_valid & mem_bypasses_0_dst == rs1_1; // @[Core.scala:93:63, :295:{21,30}] wire _T_83 = mem_bypasses_1_valid & mem_bypasses_1_dst == rs1_1; // @[Core.scala:93:63, :295:{21,30}] wire _T_85 = ex_bypasses_0_valid & ex_bypasses_0_dst == rs1_1; // @[Core.scala:92:62, :295:{21,30}] wire _T_87 = ex_bypasses_1_valid & ex_bypasses_1_dst == rs1_1; // @[Core.scala:92:62, :295:{21,30}] assign bypass_hit_2 = _T_87 ? ex_bypasses_1_can_bypass : _T_85 ? ex_bypasses_0_can_bypass : _T_83 ? mem_bypasses_1_can_bypass : _T_81 ? mem_bypasses_0_can_bypass : _T_79 ? com_bypasses_1_can_bypass : _T_77 ? com_bypasses_0_can_bypass : _T_75 ? wb_bypasses_1_can_bypass : _T_73 ? wb_bypasses_0_can_bypass : _T_71 ? ll_bypass_0_can_bypass : _GEN_82[rs1_1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rs1_data_1 = _T_87 ? ex_bypasses_1_data : _T_85 ? ex_bypasses_0_data : _T_83 ? mem_bypasses_1_data : _T_81 ? mem_bypasses_0_data : _T_79 ? com_bypasses_1_data : _T_77 ? com_bypasses_0_data : _T_75 ? wb_bypasses_1_data : _T_73 ? wb_bypasses_0_data : _T_71 ? ll_bypass_0_data : _GEN_83[rs1_1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rs1_older_hazard_1 = ~bypass_hit_2; // @[Core.scala:292:30, :300:6] wire bypass_hit_3; // @[Core.scala:292:30] wire [63:0] rs2_data_1; // @[Core.scala:293:31] wire _T_89 = ll_bypass_0_valid & ll_bypass_0_dst == rs2_1; // @[Core.scala:96:40, :295:{21,30}] wire _T_91 = wb_bypasses_0_valid & wb_bypasses_0_dst == rs2_1; // @[Core.scala:95:62, :295:{21,30}] wire _T_93 = wb_bypasses_1_valid & wb_bypasses_1_dst == rs2_1; // @[Core.scala:95:62, :295:{21,30}] wire _T_95 = com_bypasses_0_valid & com_bypasses_0_dst == rs2_1; // @[Core.scala:94:63, :295:{21,30}] wire _T_97 = com_bypasses_1_valid & com_bypasses_1_dst == rs2_1; // @[Core.scala:94:63, :295:{21,30}] wire _T_99 = mem_bypasses_0_valid & mem_bypasses_0_dst == rs2_1; // @[Core.scala:93:63, :295:{21,30}] wire _T_101 = mem_bypasses_1_valid & mem_bypasses_1_dst == rs2_1; // @[Core.scala:93:63, :295:{21,30}] wire _T_103 = ex_bypasses_0_valid & ex_bypasses_0_dst == rs2_1; // @[Core.scala:92:62, :295:{21,30}] wire _T_105 = ex_bypasses_1_valid & ex_bypasses_1_dst == rs2_1; // @[Core.scala:92:62, :295:{21,30}] assign bypass_hit_3 = _T_105 ? ex_bypasses_1_can_bypass : _T_103 ? ex_bypasses_0_can_bypass : _T_101 ? mem_bypasses_1_can_bypass : _T_99 ? mem_bypasses_0_can_bypass : _T_97 ? com_bypasses_1_can_bypass : _T_95 ? com_bypasses_0_can_bypass : _T_93 ? wb_bypasses_1_can_bypass : _T_91 ? wb_bypasses_0_can_bypass : _T_89 ? ll_bypass_0_can_bypass : _GEN_82[rs2_1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rs2_data_1 = _T_105 ? ex_bypasses_1_data : _T_103 ? ex_bypasses_0_data : _T_101 ? mem_bypasses_1_data : _T_99 ? mem_bypasses_0_data : _T_97 ? com_bypasses_1_data : _T_95 ? com_bypasses_0_data : _T_93 ? wb_bypasses_1_data : _T_91 ? wb_bypasses_0_data : _T_89 ? ll_bypass_0_data : _GEN_83[rs2_1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rs2_older_hazard_1 = ~bypass_hit_3; // @[Core.scala:292:30, :300:6] wire rd_older_hazard_bypass_hit_1; // @[Core.scala:292:30] wire rd_older_hazard_bypass_data_1; // @[Core.scala:293:31] wire _rd_older_hazard_T_18 = ll_bypass_0_dst == rd_1; // @[Core.scala:96:40, :295:30] wire _rd_older_hazard_T_19 = ll_bypass_0_valid & _rd_older_hazard_T_18; // @[Core.scala:96:40, :295:{21,30}] wire _rd_older_hazard_T_20 = wb_bypasses_0_dst == rd_1; // @[Core.scala:95:62, :295:30] wire _rd_older_hazard_T_21 = wb_bypasses_0_valid & _rd_older_hazard_T_20; // @[Core.scala:95:62, :295:{21,30}] wire _rd_older_hazard_T_22 = wb_bypasses_1_dst == rd_1; // @[Core.scala:95:62, :295:30] wire _rd_older_hazard_T_23 = wb_bypasses_1_valid & _rd_older_hazard_T_22; // @[Core.scala:95:62, :295:{21,30}] wire _rd_older_hazard_T_24 = com_bypasses_0_dst == rd_1; // @[Core.scala:94:63, :295:30] wire _rd_older_hazard_T_25 = com_bypasses_0_valid & _rd_older_hazard_T_24; // @[Core.scala:94:63, :295:{21,30}] wire _rd_older_hazard_T_26 = com_bypasses_1_dst == rd_1; // @[Core.scala:94:63, :295:30] wire _rd_older_hazard_T_27 = com_bypasses_1_valid & _rd_older_hazard_T_26; // @[Core.scala:94:63, :295:{21,30}] wire _rd_older_hazard_T_28 = mem_bypasses_0_dst == rd_1; // @[Core.scala:93:63, :295:30] wire _rd_older_hazard_T_29 = mem_bypasses_0_valid & _rd_older_hazard_T_28; // @[Core.scala:93:63, :295:{21,30}] wire _rd_older_hazard_T_30 = mem_bypasses_1_dst == rd_1; // @[Core.scala:93:63, :295:30] wire _rd_older_hazard_T_31 = mem_bypasses_1_valid & _rd_older_hazard_T_30; // @[Core.scala:93:63, :295:{21,30}] wire _rd_older_hazard_T_32 = ex_bypasses_0_dst == rd_1; // @[Core.scala:92:62, :295:30] wire _rd_older_hazard_T_33 = ex_bypasses_0_valid & _rd_older_hazard_T_32; // @[Core.scala:92:62, :295:{21,30}] wire _rd_older_hazard_T_34 = ex_bypasses_1_dst == rd_1; // @[Core.scala:92:62, :295:30] wire _rd_older_hazard_T_35 = ex_bypasses_1_valid & _rd_older_hazard_T_34; // @[Core.scala:92:62, :295:{21,30}] assign rd_older_hazard_bypass_hit_1 = _rd_older_hazard_T_35 ? ex_bypasses_1_can_bypass : _rd_older_hazard_T_33 ? ex_bypasses_0_can_bypass : _rd_older_hazard_T_31 ? mem_bypasses_1_can_bypass : _rd_older_hazard_T_29 ? mem_bypasses_0_can_bypass : _rd_older_hazard_T_27 ? com_bypasses_1_can_bypass : _rd_older_hazard_T_25 ? com_bypasses_0_can_bypass : _rd_older_hazard_T_23 ? wb_bypasses_1_can_bypass : _rd_older_hazard_T_21 ? wb_bypasses_0_can_bypass : _rd_older_hazard_T_19 ? ll_bypass_0_can_bypass : _GEN_82[rd_1]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :292:30, :295:{21,38}, :296:20] assign rd_older_hazard_bypass_data_1 = _rd_older_hazard_T_35 ? ex_bypasses_1_data[0] : _rd_older_hazard_T_33 ? ex_bypasses_0_data[0] : _rd_older_hazard_T_31 ? mem_bypasses_1_data[0] : _rd_older_hazard_T_29 ? mem_bypasses_0_data[0] : _rd_older_hazard_T_27 ? com_bypasses_1_data[0] : _rd_older_hazard_T_25 ? com_bypasses_0_data[0] : _rd_older_hazard_T_23 ? wb_bypasses_1_data[0] : _rd_older_hazard_T_21 ? wb_bypasses_0_data[0] : _rd_older_hazard_T_19 & ll_bypass_0_data[0]; // @[Core.scala:92:62, :93:63, :94:63, :95:62, :96:40, :293:31, :295:{21,38}, :297:21] wire rd_older_hazard_1 = ~rd_older_hazard_bypass_hit_1; // @[Core.scala:292:30, :300:6] wire _rrd_uops_1_bits_rs1_data_T = ~(|rs1_1); // @[Core.scala:322:42] wire [63:0] _rrd_uops_1_bits_rs1_data_T_1 = _rrd_uops_1_bits_rs1_data_T ? 64'h0 : rs1_data_1; // @[Core.scala:293:31, :322:{37,42}] assign rrd_uops_1_bits_rs1_data = rrd_uops_1_bits_xcpt & rrd_uops_1_bits_xcpt_cause == 64'h2 ? {32'h0, io_imem_resp_1_bits_raw_inst_0} : _rrd_uops_1_bits_rs1_data_T_1; // @[Core.scala:25:7, :70:22, :322:{31,37}, :323:{33,64,98}, :324:33] wire _rrd_uops_1_bits_rs2_data_T = ~(|rs2_1); // @[Core.scala:326:42] assign _rrd_uops_1_bits_rs2_data_T_1 = _rrd_uops_1_bits_rs2_data_T ? 64'h0 : rs2_data_1; // @[Core.scala:293:31, :326:{37,42}] assign rrd_uops_1_bits_rs2_data = _rrd_uops_1_bits_rs2_data_T_1; // @[Core.scala:70:22, :326:37] wire _rs1_w0_hit_T_1 = rrd_irf_writes_0_bits == rs1_1; // @[Core.scala:304:28, :328:72] wire rs1_w0_hit_1 = rrd_irf_writes_0_valid & _rs1_w0_hit_T_1; // @[Core.scala:304:28, :328:{46,72}] wire _rs2_w0_hit_T_1 = rrd_irf_writes_0_bits == rs2_1; // @[Core.scala:304:28, :329:72] wire rs2_w0_hit_1 = rrd_irf_writes_0_valid & _rs2_w0_hit_T_1; // @[Core.scala:304:28, :329:{46,72}] wire memalu_will_be_latealu_1 = mem_uops_reg_1_valid & mem_uops_reg_1_bits_uses_latealu; // @[Core.scala:72:25, :331:56] wire _rs1_can_forward_from_x_p0_T_34 = _rs1_can_forward_from_x_p0_T_33 & rs1_w0_hit_1; // @[Core.scala:328:46, :333:{45,74}] wire _rs1_can_forward_from_x_p0_T_35 = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_36 = rrd_uops_1_bits_ctrl_wxd & _rs1_can_forward_from_x_p0_T_35; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_37 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_38 = _rs1_can_forward_from_x_p0_T_36 & _rs1_can_forward_from_x_p0_T_37; // @[MicroOp.scala:77:{27,40,43}] wire _rs1_can_forward_from_x_p0_T_39 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_40 = _rs1_can_forward_from_x_p0_T_38 & _rs1_can_forward_from_x_p0_T_39; // @[MicroOp.scala:77:{40,53,56}] wire _rs1_can_forward_from_x_p0_T_42 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_44 = _rs1_can_forward_from_x_p0_T_41 | _rs1_can_forward_from_x_p0_T_42; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_x_p0_T_45 = _rs1_can_forward_from_x_p0_T_44 | _rs1_can_forward_from_x_p0_T_43; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_x_p0_T_46 = ~_rs1_can_forward_from_x_p0_T_45; // @[MicroOp.scala:77:69] wire _rs1_can_forward_from_x_p0_T_47 = _rs1_can_forward_from_x_p0_T_40 & _rs1_can_forward_from_x_p0_T_46; // @[MicroOp.scala:77:{53,66,69}] wire _rs1_can_forward_from_x_p0_T_48 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_49 = _rs1_can_forward_from_x_p0_T_47 & _rs1_can_forward_from_x_p0_T_48; // @[MicroOp.scala:77:{66,77,80}] wire _rs1_can_forward_from_x_p0_T_50 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_51 = _rs1_can_forward_from_x_p0_T_49 & _rs1_can_forward_from_x_p0_T_50; // @[MicroOp.scala:77:{77,89,92}] wire _rs1_can_forward_from_x_p0_T_52 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_53 = _rs1_can_forward_from_x_p0_T_51 & _rs1_can_forward_from_x_p0_T_52; // @[MicroOp.scala:77:{89,103,106}] wire _rs1_can_forward_from_x_p0_T_55 = _rs1_can_forward_from_x_p0_T_53; // @[MicroOp.scala:77:{103,117}] wire _rs1_can_forward_from_x_p0_T_56 = _rs1_can_forward_from_x_p0_T_34 & _rs1_can_forward_from_x_p0_T_55; // @[Core.scala:333:{74,88}] wire _GEN_85 = rrd_uops_1_bits_ctrl_branch | rrd_uops_1_bits_ctrl_jal; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_57; // @[MicroOp.scala:74:25] assign _rs1_can_forward_from_x_p0_T_57 = _GEN_85; // @[MicroOp.scala:74:25] wire _rs2_can_forward_from_x_p0_T_57; // @[MicroOp.scala:74:25] assign _rs2_can_forward_from_x_p0_T_57 = _GEN_85; // @[MicroOp.scala:74:25] wire _rs1_can_forward_from_w_p0_T_55; // @[MicroOp.scala:74:25] assign _rs1_can_forward_from_w_p0_T_55 = _GEN_85; // @[MicroOp.scala:74:25] wire _rs2_can_forward_from_w_p0_T_55; // @[MicroOp.scala:74:25] assign _rs2_can_forward_from_w_p0_T_55 = _GEN_85; // @[MicroOp.scala:74:25] wire _brjmp_T_5; // @[MicroOp.scala:74:25] assign _brjmp_T_5 = _GEN_85; // @[MicroOp.scala:74:25] wire _is_pipe0_T_82; // @[MicroOp.scala:74:25] assign _is_pipe0_T_82 = _GEN_85; // @[MicroOp.scala:74:25] wire _rs1_can_forward_from_x_p0_T_58 = _rs1_can_forward_from_x_p0_T_57 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_x_p0_T_59 = ~_rs1_can_forward_from_x_p0_T_58; // @[Core.scala:333:120] wire _rs1_can_forward_from_x_p0_T_60 = _rs1_can_forward_from_x_p0_T_56 & _rs1_can_forward_from_x_p0_T_59; // @[Core.scala:333:{88,117,120}] wire _rs1_can_forward_from_x_p0_T_62 = _rs1_can_forward_from_x_p0_T_60; // @[Core.scala:333:{117,142}] wire _rs1_can_forward_from_x_p0_T_63 = |rs1_1; // @[Core.scala:322:42, :333:180] wire _rs1_can_forward_from_x_p0_T_64 = _rs1_can_forward_from_x_p0_T_62 & _rs1_can_forward_from_x_p0_T_63; // @[Core.scala:333:{142,173,180}] wire _rs1_can_forward_from_x_p0_T_65 = ~memalu_will_be_latealu_1; // @[Core.scala:331:56, :333:191] wire rs1_can_forward_from_x_p0_1 = _rs1_can_forward_from_x_p0_T_64 & _rs1_can_forward_from_x_p0_T_65; // @[Core.scala:333:{173,188,191}] wire _rs2_can_forward_from_x_p0_T_34 = _rs2_can_forward_from_x_p0_T_33 & rs2_w0_hit_1; // @[Core.scala:329:46, :334:{45,74}] wire _rs2_can_forward_from_x_p0_T_35 = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_36 = rrd_uops_1_bits_ctrl_wxd & _rs2_can_forward_from_x_p0_T_35; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_37 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_38 = _rs2_can_forward_from_x_p0_T_36 & _rs2_can_forward_from_x_p0_T_37; // @[MicroOp.scala:77:{27,40,43}] wire _rs2_can_forward_from_x_p0_T_39 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_40 = _rs2_can_forward_from_x_p0_T_38 & _rs2_can_forward_from_x_p0_T_39; // @[MicroOp.scala:77:{40,53,56}] wire _rs2_can_forward_from_x_p0_T_42 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_44 = _rs2_can_forward_from_x_p0_T_41 | _rs2_can_forward_from_x_p0_T_42; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_x_p0_T_45 = _rs2_can_forward_from_x_p0_T_44 | _rs2_can_forward_from_x_p0_T_43; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_x_p0_T_46 = ~_rs2_can_forward_from_x_p0_T_45; // @[MicroOp.scala:77:69] wire _rs2_can_forward_from_x_p0_T_47 = _rs2_can_forward_from_x_p0_T_40 & _rs2_can_forward_from_x_p0_T_46; // @[MicroOp.scala:77:{53,66,69}] wire _rs2_can_forward_from_x_p0_T_48 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_49 = _rs2_can_forward_from_x_p0_T_47 & _rs2_can_forward_from_x_p0_T_48; // @[MicroOp.scala:77:{66,77,80}] wire _rs2_can_forward_from_x_p0_T_50 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_51 = _rs2_can_forward_from_x_p0_T_49 & _rs2_can_forward_from_x_p0_T_50; // @[MicroOp.scala:77:{77,89,92}] wire _rs2_can_forward_from_x_p0_T_52 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_53 = _rs2_can_forward_from_x_p0_T_51 & _rs2_can_forward_from_x_p0_T_52; // @[MicroOp.scala:77:{89,103,106}] wire _rs2_can_forward_from_x_p0_T_55 = _rs2_can_forward_from_x_p0_T_53; // @[MicroOp.scala:77:{103,117}] wire _rs2_can_forward_from_x_p0_T_56 = _rs2_can_forward_from_x_p0_T_34 & _rs2_can_forward_from_x_p0_T_55; // @[Core.scala:334:{74,88}] wire _rs2_can_forward_from_x_p0_T_58 = _rs2_can_forward_from_x_p0_T_57 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_x_p0_T_59 = ~_rs2_can_forward_from_x_p0_T_58; // @[Core.scala:334:120] wire _rs2_can_forward_from_x_p0_T_60 = _rs2_can_forward_from_x_p0_T_56 & _rs2_can_forward_from_x_p0_T_59; // @[Core.scala:334:{88,117,120}] wire _rs2_can_forward_from_x_p0_T_62 = _rs2_can_forward_from_x_p0_T_60; // @[Core.scala:334:{117,142}] wire _rs2_can_forward_from_x_p0_T_63 = |rs2_1; // @[Core.scala:326:42, :334:180] wire _rs2_can_forward_from_x_p0_T_64 = _rs2_can_forward_from_x_p0_T_62 & _rs2_can_forward_from_x_p0_T_63; // @[Core.scala:334:{142,173,180}] wire _rs2_can_forward_from_x_p0_T_65 = ~memalu_will_be_latealu_1; // @[Core.scala:331:56, :333:191, :334:191] wire rs2_can_forward_from_x_p0_1 = _rs2_can_forward_from_x_p0_T_64 & _rs2_can_forward_from_x_p0_T_65; // @[Core.scala:334:{173,188,191}] wire _rs1_can_forward_from_w_p0_T_32 = _rs1_can_forward_from_w_p0_T_31 & rs1_w0_hit_1; // @[Core.scala:328:46, :335:{45,74}] wire _rs1_can_forward_from_w_p0_T_33 = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_34 = rrd_uops_1_bits_ctrl_wxd & _rs1_can_forward_from_w_p0_T_33; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_35 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_36 = _rs1_can_forward_from_w_p0_T_34 & _rs1_can_forward_from_w_p0_T_35; // @[MicroOp.scala:77:{27,40,43}] wire _rs1_can_forward_from_w_p0_T_37 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_38 = _rs1_can_forward_from_w_p0_T_36 & _rs1_can_forward_from_w_p0_T_37; // @[MicroOp.scala:77:{40,53,56}] wire _rs1_can_forward_from_w_p0_T_40 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_42 = _rs1_can_forward_from_w_p0_T_39 | _rs1_can_forward_from_w_p0_T_40; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_w_p0_T_43 = _rs1_can_forward_from_w_p0_T_42 | _rs1_can_forward_from_w_p0_T_41; // @[package.scala:16:47, :81:59] wire _rs1_can_forward_from_w_p0_T_44 = ~_rs1_can_forward_from_w_p0_T_43; // @[MicroOp.scala:77:69] wire _rs1_can_forward_from_w_p0_T_45 = _rs1_can_forward_from_w_p0_T_38 & _rs1_can_forward_from_w_p0_T_44; // @[MicroOp.scala:77:{53,66,69}] wire _rs1_can_forward_from_w_p0_T_46 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_47 = _rs1_can_forward_from_w_p0_T_45 & _rs1_can_forward_from_w_p0_T_46; // @[MicroOp.scala:77:{66,77,80}] wire _rs1_can_forward_from_w_p0_T_48 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_49 = _rs1_can_forward_from_w_p0_T_47 & _rs1_can_forward_from_w_p0_T_48; // @[MicroOp.scala:77:{77,89,92}] wire _rs1_can_forward_from_w_p0_T_50 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_51 = _rs1_can_forward_from_w_p0_T_49 & _rs1_can_forward_from_w_p0_T_50; // @[MicroOp.scala:77:{89,103,106}] wire _rs1_can_forward_from_w_p0_T_53 = _rs1_can_forward_from_w_p0_T_51; // @[MicroOp.scala:77:{103,117}] wire _rs1_can_forward_from_w_p0_T_54 = _rs1_can_forward_from_w_p0_T_32 & _rs1_can_forward_from_w_p0_T_53; // @[Core.scala:335:{74,88}] wire _rs1_can_forward_from_w_p0_T_56 = _rs1_can_forward_from_w_p0_T_55 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs1_can_forward_from_w_p0_T_57 = ~_rs1_can_forward_from_w_p0_T_56; // @[Core.scala:335:120] wire _rs1_can_forward_from_w_p0_T_58 = _rs1_can_forward_from_w_p0_T_54 & _rs1_can_forward_from_w_p0_T_57; // @[Core.scala:335:{88,117,120}] wire _rs1_can_forward_from_w_p0_T_60 = _rs1_can_forward_from_w_p0_T_58; // @[Core.scala:335:{117,142}] wire _rs1_can_forward_from_w_p0_T_61 = |rs1_1; // @[Core.scala:322:42, :335:180] wire rs1_can_forward_from_w_p0_1 = _rs1_can_forward_from_w_p0_T_60 & _rs1_can_forward_from_w_p0_T_61; // @[Core.scala:335:{142,173,180}] wire _rs2_can_forward_from_w_p0_T_32 = _rs2_can_forward_from_w_p0_T_31 & rs2_w0_hit_1; // @[Core.scala:329:46, :336:{45,74}] wire _rs2_can_forward_from_w_p0_T_33 = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_34 = rrd_uops_1_bits_ctrl_wxd & _rs2_can_forward_from_w_p0_T_33; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_35 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_36 = _rs2_can_forward_from_w_p0_T_34 & _rs2_can_forward_from_w_p0_T_35; // @[MicroOp.scala:77:{27,40,43}] wire _rs2_can_forward_from_w_p0_T_37 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_38 = _rs2_can_forward_from_w_p0_T_36 & _rs2_can_forward_from_w_p0_T_37; // @[MicroOp.scala:77:{40,53,56}] wire _rs2_can_forward_from_w_p0_T_40 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_42 = _rs2_can_forward_from_w_p0_T_39 | _rs2_can_forward_from_w_p0_T_40; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_w_p0_T_43 = _rs2_can_forward_from_w_p0_T_42 | _rs2_can_forward_from_w_p0_T_41; // @[package.scala:16:47, :81:59] wire _rs2_can_forward_from_w_p0_T_44 = ~_rs2_can_forward_from_w_p0_T_43; // @[MicroOp.scala:77:69] wire _rs2_can_forward_from_w_p0_T_45 = _rs2_can_forward_from_w_p0_T_38 & _rs2_can_forward_from_w_p0_T_44; // @[MicroOp.scala:77:{53,66,69}] wire _rs2_can_forward_from_w_p0_T_46 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_47 = _rs2_can_forward_from_w_p0_T_45 & _rs2_can_forward_from_w_p0_T_46; // @[MicroOp.scala:77:{66,77,80}] wire _rs2_can_forward_from_w_p0_T_48 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_49 = _rs2_can_forward_from_w_p0_T_47 & _rs2_can_forward_from_w_p0_T_48; // @[MicroOp.scala:77:{77,89,92}] wire _rs2_can_forward_from_w_p0_T_50 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_51 = _rs2_can_forward_from_w_p0_T_49 & _rs2_can_forward_from_w_p0_T_50; // @[MicroOp.scala:77:{89,103,106}] wire _rs2_can_forward_from_w_p0_T_53 = _rs2_can_forward_from_w_p0_T_51; // @[MicroOp.scala:77:{103,117}] wire _rs2_can_forward_from_w_p0_T_54 = _rs2_can_forward_from_w_p0_T_32 & _rs2_can_forward_from_w_p0_T_53; // @[Core.scala:336:{74,88}] wire _rs2_can_forward_from_w_p0_T_56 = _rs2_can_forward_from_w_p0_T_55 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rs2_can_forward_from_w_p0_T_57 = ~_rs2_can_forward_from_w_p0_T_56; // @[Core.scala:336:120] wire _rs2_can_forward_from_w_p0_T_58 = _rs2_can_forward_from_w_p0_T_54 & _rs2_can_forward_from_w_p0_T_57; // @[Core.scala:336:{88,117,120}] wire _rs2_can_forward_from_w_p0_T_60 = _rs2_can_forward_from_w_p0_T_58; // @[Core.scala:336:{117,142}] wire _rs2_can_forward_from_w_p0_T_61 = |rs2_1; // @[Core.scala:326:42, :336:180] wire rs2_can_forward_from_w_p0_1 = _rs2_can_forward_from_w_p0_T_60 & _rs2_can_forward_from_w_p0_T_61; // @[Core.scala:336:{142,173,180}] wire _rs1_same_hazard_T = ~rs1_can_forward_from_x_p0_1; // @[Core.scala:333:188, :340:23] wire _rs1_same_hazard_T_1 = rs1_w0_hit_1 & _rs1_same_hazard_T; // @[Core.scala:328:46, :340:{20,23}] wire _rs1_same_hazard_T_2 = ~rs1_can_forward_from_w_p0_1; // @[Core.scala:335:173, :340:53] wire rs1_same_hazard = _rs1_same_hazard_T_1 & _rs1_same_hazard_T_2; // @[Core.scala:340:{20,50,53}] wire _rs2_same_hazard_T = ~rs2_can_forward_from_x_p0_1; // @[Core.scala:334:188, :347:23] wire _rs2_same_hazard_T_1 = rs2_w0_hit_1 & _rs2_same_hazard_T; // @[Core.scala:329:46, :347:{20,23}] wire _rs2_same_hazard_T_2 = ~rs2_can_forward_from_w_p0_1; // @[Core.scala:336:173, :347:53] wire rs2_same_hazard = _rs2_same_hazard_T_1 & _rs2_same_hazard_T_2; // @[Core.scala:347:{20,50,53}] wire _rd_same_hazard_T = rrd_irf_writes_0_bits == rd_1; // @[Core.scala:304:28, :354:27] wire _rd_same_hazard_T_1 = rrd_irf_writes_0_valid & _rd_same_hazard_T; // @[Core.scala:304:28, :354:{17,27}] wire _rd_same_hazard_T_2 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _rd_same_hazard_T_3 = rrd_uops_0_bits_ctrl_wxd & _rd_same_hazard_T_2; // @[Core.scala:70:22] wire _rd_same_hazard_T_4 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _rd_same_hazard_T_5 = _rd_same_hazard_T_3 & _rd_same_hazard_T_4; // @[MicroOp.scala:77:{27,40,43}] wire _rd_same_hazard_T_6 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _rd_same_hazard_T_7 = _rd_same_hazard_T_5 & _rd_same_hazard_T_6; // @[MicroOp.scala:77:{40,53,56}] wire _rd_same_hazard_T_9 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _rd_same_hazard_T_11 = _rd_same_hazard_T_8 | _rd_same_hazard_T_9; // @[package.scala:16:47, :81:59] wire _rd_same_hazard_T_12 = _rd_same_hazard_T_11 | _rd_same_hazard_T_10; // @[package.scala:16:47, :81:59] wire _rd_same_hazard_T_13 = ~_rd_same_hazard_T_12; // @[MicroOp.scala:77:69] wire _rd_same_hazard_T_14 = _rd_same_hazard_T_7 & _rd_same_hazard_T_13; // @[MicroOp.scala:77:{53,66,69}] wire _rd_same_hazard_T_15 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _rd_same_hazard_T_16 = _rd_same_hazard_T_14 & _rd_same_hazard_T_15; // @[MicroOp.scala:77:{66,77,80}] wire _rd_same_hazard_T_17 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rd_same_hazard_T_18 = _rd_same_hazard_T_16 & _rd_same_hazard_T_17; // @[MicroOp.scala:77:{77,89,92}] wire _rd_same_hazard_T_19 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rd_same_hazard_T_20 = _rd_same_hazard_T_18 & _rd_same_hazard_T_19; // @[MicroOp.scala:77:{89,103,106}] wire _rd_same_hazard_T_22 = _rd_same_hazard_T_20; // @[MicroOp.scala:77:{103,117}] wire _rd_same_hazard_T_23 = ~_rd_same_hazard_T_22; // @[Core.scala:354:37] wire _rd_same_hazard_T_24 = _rd_same_hazard_T_1 & _rd_same_hazard_T_23; // @[Core.scala:354:{17,34,37}] wire _rd_same_hazard_T_25 = ~rrd_uops_1_bits_uses_latealu; // @[Core.scala:70:22, :354:67] wire rd_same_hazard = _rd_same_hazard_T_24 & _rd_same_hazard_T_25; // @[Core.scala:354:{34,64,67}] wire _rs1_data_hazard_T_3 = rs1_older_hazard_1 | rs1_same_hazard; // @[Core.scala:300:6, :340:50, :360:45] wire _rs1_data_hazard_T_4 = _rs1_data_hazard_T_3 & rrd_uops_1_bits_ctrl_rxs1; // @[Core.scala:70:22, :360:{45,65}] wire _rs1_data_hazard_T_5 = |rs1_1; // @[Core.scala:322:42, :360:85] wire rs1_data_hazard_1 = _rs1_data_hazard_T_4 & _rs1_data_hazard_T_5; // @[Core.scala:360:{65,78,85}] wire _rs2_data_hazard_T_3 = rs2_older_hazard_1 | rs2_same_hazard; // @[Core.scala:300:6, :347:50, :361:45] wire _rs2_data_hazard_T_4 = _rs2_data_hazard_T_3 & rrd_uops_1_bits_ctrl_rxs2; // @[Core.scala:70:22, :361:{45,65}] wire _rs2_data_hazard_T_5 = |rs2_1; // @[Core.scala:326:42, :361:85] wire rs2_data_hazard_1 = _rs2_data_hazard_T_4 & _rs2_data_hazard_T_5; // @[Core.scala:361:{65,78,85}] wire _rd_data_hazard_T_3 = rd_older_hazard_1 | rd_same_hazard; // @[Core.scala:300:6, :354:64, :362:44] wire _rd_data_hazard_T_4 = _rd_data_hazard_T_3 & rrd_uops_1_bits_ctrl_wxd; // @[Core.scala:70:22, :362:{44,63}] wire _rd_data_hazard_T_5 = |rd_1; // @[Core.scala:362:81] wire rd_data_hazard_1 = _rd_data_hazard_T_4 & _rd_data_hazard_T_5; // @[Core.scala:362:{63,75,81}] wire _GEN_86 = rrd_uops_0_valid & rrd_uops_0_bits_ctrl_wfd; // @[Core.scala:70:22, :365:78] wire _frs1_same_hazard_T_1; // @[Core.scala:365:78] assign _frs1_same_hazard_T_1 = _GEN_86; // @[Core.scala:365:78] wire _frs2_same_hazard_T_1; // @[Core.scala:366:78] assign _frs2_same_hazard_T_1 = _GEN_86; // @[Core.scala:365:78, :366:78] wire _frs3_same_hazard_T_1; // @[Core.scala:367:78] assign _frs3_same_hazard_T_1 = _GEN_86; // @[Core.scala:365:78, :367:78] wire _frd_same_hazard_T_1; // @[Core.scala:368:78] assign _frd_same_hazard_T_1 = _GEN_86; // @[Core.scala:365:78, :368:78] wire _frs1_same_hazard_T_3 = _frs1_same_hazard_T_2 == rs1_1; // @[Core.scala:365:110] wire _frs1_same_hazard_T_4 = _frs1_same_hazard_T_1 & _frs1_same_hazard_T_3; // @[Core.scala:365:{78,97,110}] wire _frs2_same_hazard_T_3 = _frs2_same_hazard_T_2 == rs2_1; // @[Core.scala:366:110] wire _frs2_same_hazard_T_4 = _frs2_same_hazard_T_1 & _frs2_same_hazard_T_3; // @[Core.scala:366:{78,97,110}] wire _frs3_same_hazard_T_3 = _frs3_same_hazard_T_2 == rs3_1; // @[Core.scala:367:110] wire _frs3_same_hazard_T_4 = _frs3_same_hazard_T_1 & _frs3_same_hazard_T_3; // @[Core.scala:367:{78,97,110}] wire _frd_same_hazard_T_3 = _frd_same_hazard_T_2 == rd_1; // @[Core.scala:368:110] wire _frd_same_hazard_T_4 = _frd_same_hazard_T_1 & _frd_same_hazard_T_3; // @[Core.scala:368:{78,97,110}] wire _rrd_stall_data_1_T = rs1_data_hazard_1 | rs2_data_hazard_1; // @[Core.scala:360:78, :361:78, :370:43] wire _rrd_stall_data_1_T_1 = _rrd_stall_data_1_T | rd_data_hazard_1; // @[Core.scala:362:75, :370:{43,62}] wire _rrd_stall_data_1_T_2 = _rrd_stall_data_1_T_1; // @[Core.scala:370:{62,80}] wire _rrd_stall_data_1_T_3 = _rrd_stall_data_1_T_2; // @[Core.scala:370:{80,100}] wire _rrd_stall_data_1_T_4 = _rrd_stall_data_1_T_3; // @[Core.scala:370:{100,120}] assign _rrd_stall_data_1_T_5 = _rrd_stall_data_1_T_4; // @[Core.scala:370:{120,140}] assign rrd_stall_data_1 = _rrd_stall_data_1_T_5; // @[Core.scala:303:28, :370:140] wire _rrd_uops_1_bits_uses_memalu_T = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_1 = rrd_uops_1_bits_ctrl_wxd & _rrd_uops_1_bits_uses_memalu_T; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_2 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_3 = _rrd_uops_1_bits_uses_memalu_T_1 & _rrd_uops_1_bits_uses_memalu_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _rrd_uops_1_bits_uses_memalu_T_4 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_5 = _rrd_uops_1_bits_uses_memalu_T_3 & _rrd_uops_1_bits_uses_memalu_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _rrd_uops_1_bits_uses_memalu_T_7 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_9 = _rrd_uops_1_bits_uses_memalu_T_6 | _rrd_uops_1_bits_uses_memalu_T_7; // @[package.scala:16:47, :81:59] wire _rrd_uops_1_bits_uses_memalu_T_10 = _rrd_uops_1_bits_uses_memalu_T_9 | _rrd_uops_1_bits_uses_memalu_T_8; // @[package.scala:16:47, :81:59] wire _rrd_uops_1_bits_uses_memalu_T_11 = ~_rrd_uops_1_bits_uses_memalu_T_10; // @[MicroOp.scala:77:69] wire _rrd_uops_1_bits_uses_memalu_T_12 = _rrd_uops_1_bits_uses_memalu_T_5 & _rrd_uops_1_bits_uses_memalu_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _rrd_uops_1_bits_uses_memalu_T_13 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_14 = _rrd_uops_1_bits_uses_memalu_T_12 & _rrd_uops_1_bits_uses_memalu_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _rrd_uops_1_bits_uses_memalu_T_15 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_16 = _rrd_uops_1_bits_uses_memalu_T_14 & _rrd_uops_1_bits_uses_memalu_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _rrd_uops_1_bits_uses_memalu_T_17 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_memalu_T_18 = _rrd_uops_1_bits_uses_memalu_T_16 & _rrd_uops_1_bits_uses_memalu_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _rrd_uops_1_bits_uses_memalu_T_20 = _rrd_uops_1_bits_uses_memalu_T_18; // @[MicroOp.scala:77:{103,117}] wire _rrd_uops_1_bits_uses_memalu_T_21 = rs1_w0_hit_1 & rs1_can_forward_from_x_p0_1; // @[Core.scala:328:46, :333:188, :371:79] wire _rrd_uops_1_bits_uses_memalu_T_22 = rs2_w0_hit_1 & rs2_can_forward_from_x_p0_1; // @[Core.scala:329:46, :334:188, :371:124] wire _rrd_uops_1_bits_uses_memalu_T_23 = _rrd_uops_1_bits_uses_memalu_T_21 | _rrd_uops_1_bits_uses_memalu_T_22; // @[Core.scala:371:{79,109,124}] wire _rrd_uops_1_bits_uses_memalu_T_24 = _rrd_uops_1_bits_uses_memalu_T_20 & _rrd_uops_1_bits_uses_memalu_T_23; // @[Core.scala:371:{63,109}] wire _rrd_uops_1_bits_uses_memalu_T_25 = _rrd_uops_1_bits_uses_memalu_T_24; // @[Core.scala:371:{63,155}] wire _rrd_uops_1_bits_uses_memalu_T_26 = ~sfb_shadow_1; // @[Core.scala:317:33, :371:176] assign _rrd_uops_1_bits_uses_memalu_T_27 = _rrd_uops_1_bits_uses_memalu_T_25 & _rrd_uops_1_bits_uses_memalu_T_26; // @[Core.scala:371:{155,173,176}] assign rrd_uops_1_bits_uses_memalu = _rrd_uops_1_bits_uses_memalu_T_27; // @[Core.scala:70:22, :371:173] wire _rrd_uops_1_bits_uses_latealu_T = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_1 = rrd_uops_1_bits_ctrl_wxd & _rrd_uops_1_bits_uses_latealu_T; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_2 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_3 = _rrd_uops_1_bits_uses_latealu_T_1 & _rrd_uops_1_bits_uses_latealu_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _rrd_uops_1_bits_uses_latealu_T_4 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_5 = _rrd_uops_1_bits_uses_latealu_T_3 & _rrd_uops_1_bits_uses_latealu_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _rrd_uops_1_bits_uses_latealu_T_7 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_9 = _rrd_uops_1_bits_uses_latealu_T_6 | _rrd_uops_1_bits_uses_latealu_T_7; // @[package.scala:16:47, :81:59] wire _rrd_uops_1_bits_uses_latealu_T_10 = _rrd_uops_1_bits_uses_latealu_T_9 | _rrd_uops_1_bits_uses_latealu_T_8; // @[package.scala:16:47, :81:59] wire _rrd_uops_1_bits_uses_latealu_T_11 = ~_rrd_uops_1_bits_uses_latealu_T_10; // @[MicroOp.scala:77:69] wire _rrd_uops_1_bits_uses_latealu_T_12 = _rrd_uops_1_bits_uses_latealu_T_5 & _rrd_uops_1_bits_uses_latealu_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _rrd_uops_1_bits_uses_latealu_T_13 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_14 = _rrd_uops_1_bits_uses_latealu_T_12 & _rrd_uops_1_bits_uses_latealu_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _rrd_uops_1_bits_uses_latealu_T_15 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_16 = _rrd_uops_1_bits_uses_latealu_T_14 & _rrd_uops_1_bits_uses_latealu_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _rrd_uops_1_bits_uses_latealu_T_17 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _rrd_uops_1_bits_uses_latealu_T_18 = _rrd_uops_1_bits_uses_latealu_T_16 & _rrd_uops_1_bits_uses_latealu_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _rrd_uops_1_bits_uses_latealu_T_20 = _rrd_uops_1_bits_uses_latealu_T_18; // @[MicroOp.scala:77:{103,117}] wire _rrd_uops_1_bits_uses_latealu_T_21 = rs1_w0_hit_1 & rs1_can_forward_from_w_p0_1; // @[Core.scala:328:46, :335:173, :372:80] wire _rrd_uops_1_bits_uses_latealu_T_22 = rs2_w0_hit_1 & rs2_can_forward_from_w_p0_1; // @[Core.scala:329:46, :336:173, :372:125] wire _rrd_uops_1_bits_uses_latealu_T_23 = _rrd_uops_1_bits_uses_latealu_T_21 | _rrd_uops_1_bits_uses_latealu_T_22; // @[Core.scala:372:{80,110,125}] wire _rrd_uops_1_bits_uses_latealu_T_24 = _rrd_uops_1_bits_uses_latealu_T_20 & _rrd_uops_1_bits_uses_latealu_T_23; // @[Core.scala:372:{64,110}] wire _rrd_uops_1_bits_uses_latealu_T_25 = _rrd_uops_1_bits_uses_latealu_T_24; // @[Core.scala:372:{64,156}] wire _rrd_uops_1_bits_uses_latealu_T_26 = ~sfb_shadow_1; // @[Core.scala:317:33, :371:176, :372:178] assign _rrd_uops_1_bits_uses_latealu_T_27 = _rrd_uops_1_bits_uses_latealu_T_25 & _rrd_uops_1_bits_uses_latealu_T_26; // @[Core.scala:372:{156,175,178}] assign rrd_uops_1_bits_uses_latealu = _rrd_uops_1_bits_uses_latealu_T_27; // @[Core.scala:70:22, :372:175] assign _rrd_irf_writes_1_valid_T = rrd_uops_1_valid & rrd_uops_1_bits_ctrl_wxd; // @[Core.scala:70:22, :380:50] assign rrd_irf_writes_1_valid = _rrd_irf_writes_1_valid_T; // @[Core.scala:304:28, :380:50] assign rrd_irf_writes_1_bits = _rrd_irf_writes_1_bits_T; // @[Core.scala:304:28] wire _T_108 = rrd_uops_1_valid & rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22, :383:29] assign rrd_uops_1_bits_fra1 = _T_108 ? (rrd_uops_1_bits_fp_ctrl_ren2 & rrd_uops_1_bits_fp_ctrl_swap12 ? _rrd_uops_1_bits_fra1_T_1 : rrd_uops_1_bits_fp_ctrl_ren1 & ~rrd_uops_1_bits_fp_ctrl_swap12 ? _rrd_uops_1_bits_fra1_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :384:27, :385:{15,32,56}, :388:27, :389:{32,56}] assign rrd_uops_1_bits_fra2 = _T_108 ? (rrd_uops_1_bits_fp_ctrl_ren2 & ~rrd_uops_1_bits_fp_ctrl_swap12 & ~rrd_uops_1_bits_fp_ctrl_swap23 ? _rrd_uops_1_bits_fra2_T_1 : rrd_uops_1_bits_fp_ctrl_ren1 & rrd_uops_1_bits_fp_ctrl_swap12 ? _rrd_uops_1_bits_fra2_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :384:27, :386:{32,56}, :388:27, :391:{15,31,34,51,75}] assign rrd_uops_1_bits_fra3 = _T_108 ? (rrd_uops_1_bits_fp_ctrl_ren3 ? _rrd_uops_1_bits_fra3_T_1 : rrd_uops_1_bits_fp_ctrl_ren2 & rrd_uops_1_bits_fp_ctrl_swap23 ? _rrd_uops_1_bits_fra3_T : 5'h0) : 5'h0; // @[Core.scala:70:22, :157:12, :383:{29,41}, :388:27, :390:{32,56}, :393:27, :394:31] wire _rrd_uops_1_bits_mem_size_T = |rs2_1; // @[Core.scala:326:42, :399:44] wire _rrd_uops_1_bits_mem_size_T_1 = |rs1_1; // @[Core.scala:322:42, :399:57] wire [1:0] _rrd_uops_1_bits_mem_size_T_2 = {_rrd_uops_1_bits_mem_size_T, _rrd_uops_1_bits_mem_size_T_1}; // @[Core.scala:399:{39,44,57}] assign rrd_uops_1_bits_mem_size = _T_113 | rrd_uops_1_bits_ctrl_mem_cmd == 5'h5 ? _rrd_uops_1_bits_mem_size_T_2 : io_imem_resp_1_bits_mem_size_0; // @[Core.scala:25:7, :70:22, :157:12, :239:43, :398:56, :399:{33,39}] wire _fsboard_bsy_T_31; // @[Core.scala:460:18] wire fsboard_bsy; // @[Core.scala:403:25] wire [1:0] _amo_fence_T = rrd_uops_0_bits_inst[26:25]; // @[Core.scala:70:22, :412:41] wire _amo_fence_T_1 = |_amo_fence_T; // @[Core.scala:412:{41,49}] wire amo_fence = rrd_uops_0_bits_ctrl_amo & _amo_fence_T_1; // @[Core.scala:70:22, :412:{30,49}] wire _rrd_fence_stall_T_1 = _rrd_fence_stall_T | rrd_uops_0_bits_ctrl_fence; // @[Core.scala:70:22, :413:59] wire _rrd_fence_stall_T_3 = rrd_uops_0_bits_ctrl_mem & _rrd_fence_stall_T_2; // @[Core.scala:70:22] wire _rrd_fence_stall_T_4 = _rrd_fence_stall_T_1 | _rrd_fence_stall_T_3; // @[Core.scala:413:{59,73}] wire _rrd_fence_stall_T_5 = _rrd_fence_stall_T_4 | rrd_uops_0_bits_ctrl_fence_i; // @[Core.scala:70:22, :413:{73,87}] wire _rrd_fence_stall_T_6 = _rrd_fence_stall_T_5 | amo_fence; // @[Core.scala:412:30, :413:{87,103}] wire _GEN_87 = ex_bsy | mem_bsy; // @[Core.scala:114:49, :115:51, :414:15] wire _rrd_fence_stall_T_7; // @[Core.scala:414:15] assign _rrd_fence_stall_T_7 = _GEN_87; // @[Core.scala:414:15] wire _rrd_fence_stall_T_23; // @[Core.scala:414:15] assign _rrd_fence_stall_T_23 = _GEN_87; // @[Core.scala:414:15] wire _rrd_fence_stall_T_8 = _rrd_fence_stall_T_7 | com_bsy; // @[Core.scala:116:51, :414:{15,26}] wire _rrd_fence_stall_T_9 = _rrd_fence_stall_T_8 | isboard_bsy; // @[Core.scala:285:21, :414:{26,37}] wire _rrd_fence_stall_T_10 = _rrd_fence_stall_T_9 | fsboard_bsy; // @[Core.scala:403:25, :414:{37,52}] wire _rrd_fence_stall_T_11 = ~io_dmem_ordered_0; // @[Core.scala:25:7, :414:70] wire _rrd_fence_stall_T_12 = _rrd_fence_stall_T_10 | _rrd_fence_stall_T_11; // @[Core.scala:414:{52,67,70}] wire _rrd_fence_stall_T_13 = _rrd_fence_stall_T_12; // @[Core.scala:414:{67,87}] wire _rrd_fence_stall_T_14 = _rrd_fence_stall_T_13; // @[Core.scala:414:{87,103}] wire _rrd_fence_stall_T_15 = _rrd_fence_stall_T_6 & _rrd_fence_stall_T_14; // @[Core.scala:413:{103,117}, :414:103] wire rrd_fence_stall = _rrd_fence_stall_T_15; // @[Core.scala:413:{38,117}] wire rrd_rocc_stall = _rrd_rocc_stall_T; // @[Core.scala:415:{37,50}] wire _brjmp_T_1 = _brjmp_T | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _brjmp_T_3 = rrd_uops_0_bits_ctrl_mem & _brjmp_T_2; // @[Core.scala:70:22] wire _brjmp_T_4 = _brjmp_T_1 | _brjmp_T_3; // @[MicroOp.scala:72:25, :74:37, :76:24] wire brjmp = _brjmp_T_4 | rrd_uops_0_bits_next_pc_valid; // @[Core.scala:70:22, :416:32] wire _is_pipe0_T_30 = _is_pipe0_T; // @[Core.scala:418:7] wire _is_pipe0_T_1 = ~rrd_uops_0_bits_ctrl_mem; // @[Core.scala:70:22] wire _is_pipe0_T_2 = rrd_uops_0_bits_ctrl_wxd & _is_pipe0_T_1; // @[Core.scala:70:22] wire _is_pipe0_T_3 = ~rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22] wire _is_pipe0_T_4 = _is_pipe0_T_2 & _is_pipe0_T_3; // @[MicroOp.scala:77:{27,40,43}] wire _is_pipe0_T_5 = ~rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22] wire _is_pipe0_T_6 = _is_pipe0_T_4 & _is_pipe0_T_5; // @[MicroOp.scala:77:{40,53,56}] wire _is_pipe0_T_8 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_pipe0_T_10 = _is_pipe0_T_7 | _is_pipe0_T_8; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_11 = _is_pipe0_T_10 | _is_pipe0_T_9; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_12 = ~_is_pipe0_T_11; // @[MicroOp.scala:77:69] wire _is_pipe0_T_13 = _is_pipe0_T_6 & _is_pipe0_T_12; // @[MicroOp.scala:77:{53,66,69}] wire _is_pipe0_T_14 = ~rrd_uops_0_bits_ctrl_fp; // @[Core.scala:70:22] wire _is_pipe0_T_15 = _is_pipe0_T_13 & _is_pipe0_T_14; // @[MicroOp.scala:77:{66,77,80}] wire _is_pipe0_T_16 = ~rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22] wire _is_pipe0_T_17 = _is_pipe0_T_15 & _is_pipe0_T_16; // @[MicroOp.scala:77:{77,89,92}] wire _is_pipe0_T_18 = ~rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _is_pipe0_T_19 = _is_pipe0_T_17 & _is_pipe0_T_18; // @[MicroOp.scala:77:{89,103,106}] wire _is_pipe0_T_21 = _is_pipe0_T_19; // @[MicroOp.scala:77:{103,117}] wire _is_pipe0_T_22 = ~_is_pipe0_T_21; // @[Core.scala:418:30] wire _is_pipe0_T_24 = _is_pipe0_T_23 | rrd_uops_0_bits_ctrl_jalr; // @[Core.scala:70:22] wire _is_pipe0_T_26 = rrd_uops_0_bits_ctrl_mem & _is_pipe0_T_25; // @[Core.scala:70:22] wire _is_pipe0_T_27 = _is_pipe0_T_24 | _is_pipe0_T_26; // @[MicroOp.scala:72:25, :74:37, :76:24] wire _is_pipe0_T_28 = _is_pipe0_T_22 | _is_pipe0_T_27; // @[Core.scala:418:{30,44}] wire _is_pipe0_T_33 = _is_pipe0_T_30; // @[Core.scala:418:7, :419:7] wire _is_pipe0_T_31 = ~rrd_uops_0_bits_rvc; // @[Core.scala:70:22, :249:8, :419:29] wire _is_pipe0_T_34 = _is_pipe0_T_33 | rrd_uops_0_bits_sfb_br; // @[Core.scala:70:22, :419:7, :420:7] wire _is_pipe0_T_35 = _is_pipe0_T_34; // @[Core.scala:420:7, :421:7] wire _is_pipe0_T_37 = _is_pipe0_T_35; // @[Core.scala:421:7, :422:7] wire _is_pipe0_T_38 = _is_pipe0_T_37 | rrd_uops_0_bits_ctrl_fence; // @[Core.scala:70:22, :422:7, :423:7] wire _is_pipe0_T_39 = _is_pipe0_T_38 | rrd_uops_0_bits_ctrl_amo; // @[Core.scala:70:22, :423:7, :424:7] wire _is_pipe0_T_40 = _is_pipe0_T_39 | rrd_uops_0_bits_ctrl_fence_i; // @[Core.scala:70:22, :424:7, :425:7] wire _is_pipe0_T_42 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_pipe0_T_44 = _is_pipe0_T_41 | _is_pipe0_T_42; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_45 = _is_pipe0_T_44 | _is_pipe0_T_43; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_46 = _is_pipe0_T_40 | _is_pipe0_T_45; // @[Core.scala:425:7, :426:7] wire _is_pipe0_T_48 = rrd_uops_0_bits_ctrl_mem & _is_pipe0_T_47; // @[Core.scala:70:22] wire _is_pipe0_T_49 = _is_pipe0_T_46 | _is_pipe0_T_48; // @[Core.scala:426:7, :427:7] wire _is_pipe0_T_50 = |rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22, :428:19] wire _is_pipe0_T_51 = _is_pipe0_T_49 | _is_pipe0_T_50; // @[Core.scala:427:7, :428:{7,19}] wire _is_pipe0_T_52 = _is_pipe0_T_51 | rrd_uops_0_bits_xcpt; // @[Core.scala:70:22, :428:7, :429:7] wire _is_pipe0_T_53 = _is_pipe0_T_52 | rrd_uops_0_bits_ctrl_mul; // @[Core.scala:70:22, :429:7, :430:7] wire _is_pipe0_T_54 = _is_pipe0_T_53 | rrd_uops_0_bits_ctrl_div; // @[Core.scala:70:22, :430:7, :431:7] wire _is_pipe0_T_55 = _is_pipe0_T_54 | rrd_uops_0_bits_ctrl_rocc; // @[Core.scala:70:22, :431:7, :432:7] wire _is_pipe0_T_56 = rrd_uops_0_bits_fp_ctrl_ldst & rrd_uops_0_bits_fp_ctrl_wen; // @[Core.scala:70:22] wire _is_pipe0_T_57 = ~_is_pipe0_T_56; // @[MicroOp.scala:78:{28,43}] wire _is_pipe0_T_58 = rrd_uops_0_bits_ctrl_fp & _is_pipe0_T_57; // @[Core.scala:70:22] wire is_pipe0 = _is_pipe0_T_55 | _is_pipe0_T_58; // @[Core.scala:432:7, :433:7] wire _is_youngest_T_1 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_youngest_T_3 = _is_youngest_T | _is_youngest_T_1; // @[package.scala:16:47, :81:59] wire _is_youngest_T_4 = _is_youngest_T_3 | _is_youngest_T_2; // @[package.scala:16:47, :81:59] wire _is_youngest_T_5 = rrd_uops_0_bits_xcpt | _is_youngest_T_4; // @[Core.scala:70:22, :435:32] wire is_youngest = _is_youngest_T_5 | _is_youngest_T_6; // @[Core.scala:435:{32,46}] wire _rrd_stall_0_T = rrd_stall_data_0 | rrd_fence_stall; // @[Core.scala:303:28, :413:38, :437:48] wire _rrd_stall_0_T_1 = _rrd_stall_0_T | rrd_rocc_stall; // @[Core.scala:415:50, :437:48, :438:48] wire _rrd_stall_0_T_3 = _rrd_stall_0_T_1; // @[Core.scala:438:48, :439:48] wire _rrd_stall_0_T_5 = _rrd_stall_0_T_3; // @[Core.scala:439:48, :440:48] wire _rrd_stall_0_T_7 = _rrd_stall_0_T_5; // @[Core.scala:440:48, :441:48] wire _rrd_stall_0_T_9 = _rrd_stall_0_T_7; // @[Core.scala:441:48, :442:48] wire _rrd_stall_0_T_10 = _rrd_stall_0_T_9; // @[Core.scala:442:48, :443:48] wire _rrd_stall_0_T_11 = _rrd_stall_0_T_10 | _csr_io_csr_stall; // @[Core.scala:52:19, :443:48, :444:48] assign _rrd_stall_0_T_12 = _rrd_stall_0_T_11 | ex_stall; // @[Core.scala:107:26, :444:48, :445:48] assign rrd_stall_0 = _rrd_stall_0_T_12; // @[Core.scala:106:23, :445:48] wire [1:0] _amo_fence_T_2 = rrd_uops_1_bits_inst[26:25]; // @[Core.scala:70:22, :412:41] wire _amo_fence_T_3 = |_amo_fence_T_2; // @[Core.scala:412:{41,49}] wire amo_fence_1 = rrd_uops_1_bits_ctrl_amo & _amo_fence_T_3; // @[Core.scala:70:22, :412:{30,49}] wire _rrd_fence_stall_T_17 = _rrd_fence_stall_T_16 | rrd_uops_1_bits_ctrl_fence; // @[Core.scala:70:22, :413:59] wire _rrd_fence_stall_T_19 = rrd_uops_1_bits_ctrl_mem & _rrd_fence_stall_T_18; // @[Core.scala:70:22] wire _rrd_fence_stall_T_20 = _rrd_fence_stall_T_17 | _rrd_fence_stall_T_19; // @[Core.scala:413:{59,73}] wire _rrd_fence_stall_T_21 = _rrd_fence_stall_T_20 | rrd_uops_1_bits_ctrl_fence_i; // @[Core.scala:70:22, :413:{73,87}] wire _rrd_fence_stall_T_22 = _rrd_fence_stall_T_21 | amo_fence_1; // @[Core.scala:412:30, :413:{87,103}] wire _rrd_fence_stall_T_24 = _rrd_fence_stall_T_23 | com_bsy; // @[Core.scala:116:51, :414:{15,26}] wire _rrd_fence_stall_T_25 = _rrd_fence_stall_T_24 | isboard_bsy; // @[Core.scala:285:21, :414:{26,37}] wire _rrd_fence_stall_T_26 = _rrd_fence_stall_T_25 | fsboard_bsy; // @[Core.scala:403:25, :414:{37,52}] wire _rrd_fence_stall_T_27 = ~io_dmem_ordered_0; // @[Core.scala:25:7, :414:70] wire _rrd_fence_stall_T_28 = _rrd_fence_stall_T_26 | _rrd_fence_stall_T_27; // @[Core.scala:414:{52,67,70}] wire _rrd_fence_stall_T_29 = _rrd_fence_stall_T_28; // @[Core.scala:414:{67,87}] wire _rrd_fence_stall_T_30 = _rrd_fence_stall_T_29; // @[Core.scala:414:{87,103}] wire _rrd_fence_stall_T_31 = _rrd_fence_stall_T_22 & _rrd_fence_stall_T_30; // @[Core.scala:413:{103,117}, :414:103] wire _brjmp_T_6 = _brjmp_T_5 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _brjmp_T_8 = rrd_uops_1_bits_ctrl_mem & _brjmp_T_7; // @[Core.scala:70:22] wire _brjmp_T_9 = _brjmp_T_6 | _brjmp_T_8; // @[MicroOp.scala:72:25, :74:37, :76:24] wire brjmp_1 = _brjmp_T_9 | rrd_uops_1_bits_next_pc_valid; // @[Core.scala:70:22, :416:32] wire _is_pipe0_T_60 = ~rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22] wire _is_pipe0_T_61 = rrd_uops_1_bits_ctrl_wxd & _is_pipe0_T_60; // @[Core.scala:70:22] wire _is_pipe0_T_62 = ~rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22] wire _is_pipe0_T_63 = _is_pipe0_T_61 & _is_pipe0_T_62; // @[MicroOp.scala:77:{27,40,43}] wire _is_pipe0_T_64 = ~rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22] wire _is_pipe0_T_65 = _is_pipe0_T_63 & _is_pipe0_T_64; // @[MicroOp.scala:77:{40,53,56}] wire _is_pipe0_T_67 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_pipe0_T_69 = _is_pipe0_T_66 | _is_pipe0_T_67; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_70 = _is_pipe0_T_69 | _is_pipe0_T_68; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_71 = ~_is_pipe0_T_70; // @[MicroOp.scala:77:69] wire _is_pipe0_T_72 = _is_pipe0_T_65 & _is_pipe0_T_71; // @[MicroOp.scala:77:{53,66,69}] wire _is_pipe0_T_73 = ~rrd_uops_1_bits_ctrl_fp; // @[Core.scala:70:22] wire _is_pipe0_T_74 = _is_pipe0_T_72 & _is_pipe0_T_73; // @[MicroOp.scala:77:{66,77,80}] wire _is_pipe0_T_75 = ~rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22] wire _is_pipe0_T_76 = _is_pipe0_T_74 & _is_pipe0_T_75; // @[MicroOp.scala:77:{77,89,92}] wire _is_pipe0_T_77 = ~rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _is_pipe0_T_78 = _is_pipe0_T_76 & _is_pipe0_T_77; // @[MicroOp.scala:77:{89,103,106}] wire _is_pipe0_T_80 = _is_pipe0_T_78; // @[MicroOp.scala:77:{103,117}] wire _is_pipe0_T_81 = ~_is_pipe0_T_80; // @[Core.scala:418:30] wire _is_pipe0_T_83 = _is_pipe0_T_82 | rrd_uops_1_bits_ctrl_jalr; // @[Core.scala:70:22] wire _is_pipe0_T_85 = rrd_uops_1_bits_ctrl_mem & _is_pipe0_T_84; // @[Core.scala:70:22] wire _is_pipe0_T_86 = _is_pipe0_T_83 | _is_pipe0_T_85; // @[MicroOp.scala:72:25, :74:37, :76:24] wire _is_pipe0_T_87 = _is_pipe0_T_81 | _is_pipe0_T_86; // @[Core.scala:418:{30,44}] wire _is_pipe0_T_88 = rrd_uops_1_bits_sfb_shadow & _is_pipe0_T_87; // @[Core.scala:70:22, :418:{26,44}] wire _is_pipe0_T_89 = _is_pipe0_T_59 | _is_pipe0_T_88; // @[Core.scala:418:{7,26}] wire _is_pipe0_T_90 = ~rrd_uops_1_bits_rvc; // @[Core.scala:70:22, :249:8, :419:29] wire _is_pipe0_T_91 = rrd_uops_1_bits_sfb_shadow & _is_pipe0_T_90; // @[Core.scala:70:22, :419:{26,29}] wire _is_pipe0_T_92 = _is_pipe0_T_89 | _is_pipe0_T_91; // @[Core.scala:418:7, :419:{7,26}] wire _is_pipe0_T_93 = _is_pipe0_T_92 | rrd_uops_1_bits_sfb_br; // @[Core.scala:70:22, :419:7, :420:7] wire _is_pipe0_T_94 = _is_pipe0_T_93; // @[Core.scala:420:7, :421:7] wire _is_pipe0_T_96 = _is_pipe0_T_94; // @[Core.scala:421:7, :422:7] wire _is_pipe0_T_97 = _is_pipe0_T_96 | rrd_uops_1_bits_ctrl_fence; // @[Core.scala:70:22, :422:7, :423:7] wire _is_pipe0_T_98 = _is_pipe0_T_97 | rrd_uops_1_bits_ctrl_amo; // @[Core.scala:70:22, :423:7, :424:7] wire _is_pipe0_T_99 = _is_pipe0_T_98 | rrd_uops_1_bits_ctrl_fence_i; // @[Core.scala:70:22, :424:7, :425:7] wire _is_pipe0_T_101 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_pipe0_T_103 = _is_pipe0_T_100 | _is_pipe0_T_101; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_104 = _is_pipe0_T_103 | _is_pipe0_T_102; // @[package.scala:16:47, :81:59] wire _is_pipe0_T_105 = _is_pipe0_T_99 | _is_pipe0_T_104; // @[Core.scala:425:7, :426:7] wire _is_pipe0_T_107 = rrd_uops_1_bits_ctrl_mem & _is_pipe0_T_106; // @[Core.scala:70:22] wire _is_pipe0_T_108 = _is_pipe0_T_105 | _is_pipe0_T_107; // @[Core.scala:426:7, :427:7] wire _is_pipe0_T_109 = |rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22, :428:19] wire _is_pipe0_T_110 = _is_pipe0_T_108 | _is_pipe0_T_109; // @[Core.scala:427:7, :428:{7,19}] wire _is_pipe0_T_111 = _is_pipe0_T_110 | rrd_uops_1_bits_xcpt; // @[Core.scala:70:22, :428:7, :429:7] wire _is_pipe0_T_112 = _is_pipe0_T_111 | rrd_uops_1_bits_ctrl_mul; // @[Core.scala:70:22, :429:7, :430:7] wire _is_pipe0_T_113 = _is_pipe0_T_112 | rrd_uops_1_bits_ctrl_div; // @[Core.scala:70:22, :430:7, :431:7] wire _is_pipe0_T_114 = _is_pipe0_T_113 | rrd_uops_1_bits_ctrl_rocc; // @[Core.scala:70:22, :431:7, :432:7] wire _is_pipe0_T_115 = rrd_uops_1_bits_fp_ctrl_ldst & rrd_uops_1_bits_fp_ctrl_wen; // @[Core.scala:70:22] wire _is_pipe0_T_116 = ~_is_pipe0_T_115; // @[MicroOp.scala:78:{28,43}] wire _is_pipe0_T_117 = rrd_uops_1_bits_ctrl_fp & _is_pipe0_T_116; // @[Core.scala:70:22] wire is_pipe0_1 = _is_pipe0_T_114 | _is_pipe0_T_117; // @[Core.scala:432:7, :433:7] wire _rrd_stall_1_T_2 = is_pipe0_1; // @[Core.scala:433:7, :440:17] wire _is_youngest_T_8 = &rrd_uops_1_bits_ctrl_csr; // @[Core.scala:70:22] wire _is_youngest_T_10 = _is_youngest_T_7 | _is_youngest_T_8; // @[package.scala:16:47, :81:59] wire _is_youngest_T_11 = _is_youngest_T_10 | _is_youngest_T_9; // @[package.scala:16:47, :81:59] wire _is_youngest_T_12 = rrd_uops_1_bits_xcpt | _is_youngest_T_11; // @[Core.scala:70:22, :435:32] wire is_youngest_1 = _is_youngest_T_12 | _is_youngest_T_13; // @[Core.scala:435:{32,46}] wire _rrd_stall_1_T_1 = _rrd_stall_1_T; // @[Core.scala:437:48, :438:48] wire _rrd_stall_1_T_3 = _rrd_stall_1_T_1 | _rrd_stall_1_T_2; // @[Core.scala:438:48, :439:48, :440:17] wire _rrd_stall_1_T_4 = rrd_uops_0_bits_ctrl_mem & rrd_uops_1_bits_ctrl_mem; // @[Core.scala:70:22, :441:22] wire _rrd_stall_1_T_5 = _rrd_stall_1_T_3 | _rrd_stall_1_T_4; // @[Core.scala:439:48, :440:48, :441:22] wire _rrd_stall_1_T_7 = _rrd_stall_1_T_5; // @[Core.scala:440:48, :441:48] wire _rrd_stall_1_T_8 = brjmp & brjmp_1; // @[Core.scala:416:32, :443:24] wire _rrd_stall_1_T_9 = _rrd_stall_1_T_7 | _rrd_stall_1_T_8; // @[Core.scala:441:48, :442:48, :443:24] wire _rrd_stall_1_T_10 = _rrd_stall_1_T_9 | rrd_stall_0 | is_youngest; // @[Core.scala:106:23, :435:46, :442:48, :443:48, :449:39] wire _rrd_stall_1_T_11 = _rrd_stall_1_T_10 | _csr_io_csr_stall; // @[Core.scala:52:19, :443:48, :444:48] assign _rrd_stall_1_T_12 = _rrd_stall_1_T_11 | ex_stall; // @[Core.scala:107:26, :444:48, :445:48] assign rrd_stall_1 = _rrd_stall_1_T_12; // @[Core.scala:106:23, :445:48] wire _io_imem_redirect_flush_T = ~rrd_stall_0; // @[Core.scala:106:23, :124:52, :455:50] wire _io_imem_redirect_flush_T_1 = rrd_uops_0_valid & _io_imem_redirect_flush_T; // @[Core.scala:70:22, :455:{47,50}] wire _io_imem_redirect_flush_T_3 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _io_imem_redirect_flush_T_5 = _io_imem_redirect_flush_T_2 | _io_imem_redirect_flush_T_3; // @[package.scala:16:47, :81:59] wire _io_imem_redirect_flush_T_6 = _io_imem_redirect_flush_T_5 | _io_imem_redirect_flush_T_4; // @[package.scala:16:47, :81:59] wire _io_imem_redirect_flush_T_8 = &rrd_uops_0_bits_ctrl_csr; // @[Core.scala:70:22] wire _io_imem_redirect_flush_T_9 = _io_imem_redirect_flush_T_7 | _io_imem_redirect_flush_T_8; // @[package.scala:16:47, :81:59] wire _io_imem_redirect_flush_T_11 = _io_imem_redirect_flush_T_10 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire _io_imem_redirect_flush_T_12 = _io_imem_redirect_flush_T_9 & _io_imem_redirect_flush_T_11; // @[MicroOp.scala:69:{48,55}] wire _io_imem_redirect_flush_T_13 = ~_io_imem_redirect_flush_T_12; // @[MicroOp.scala:69:48, :70:27] wire _io_imem_redirect_flush_T_14 = _io_imem_redirect_flush_T_6 & _io_imem_redirect_flush_T_13; // @[MicroOp.scala:70:{24,27}] wire _io_imem_redirect_flush_T_15 = _io_imem_redirect_flush_T_1 & _io_imem_redirect_flush_T_14; // @[Core.scala:455:{47,64}] reg [64:0] fregfile_0; // @[Core.scala:458:21] reg [64:0] fregfile_1; // @[Core.scala:458:21] reg [64:0] fregfile_2; // @[Core.scala:458:21] reg [64:0] fregfile_3; // @[Core.scala:458:21] reg [64:0] fregfile_4; // @[Core.scala:458:21] reg [64:0] fregfile_5; // @[Core.scala:458:21] reg [64:0] fregfile_6; // @[Core.scala:458:21] reg [64:0] fregfile_7; // @[Core.scala:458:21] reg [64:0] fregfile_8; // @[Core.scala:458:21] reg [64:0] fregfile_9; // @[Core.scala:458:21] reg [64:0] fregfile_10; // @[Core.scala:458:21] reg [64:0] fregfile_11; // @[Core.scala:458:21] reg [64:0] fregfile_12; // @[Core.scala:458:21] reg [64:0] fregfile_13; // @[Core.scala:458:21] reg [64:0] fregfile_14; // @[Core.scala:458:21] reg [64:0] fregfile_15; // @[Core.scala:458:21] reg [64:0] fregfile_16; // @[Core.scala:458:21] reg [64:0] fregfile_17; // @[Core.scala:458:21] reg [64:0] fregfile_18; // @[Core.scala:458:21] reg [64:0] fregfile_19; // @[Core.scala:458:21] reg [64:0] fregfile_20; // @[Core.scala:458:21] reg [64:0] fregfile_21; // @[Core.scala:458:21] reg [64:0] fregfile_22; // @[Core.scala:458:21] reg [64:0] fregfile_23; // @[Core.scala:458:21] reg [64:0] fregfile_24; // @[Core.scala:458:21] reg [64:0] fregfile_25; // @[Core.scala:458:21] reg [64:0] fregfile_26; // @[Core.scala:458:21] reg [64:0] fregfile_27; // @[Core.scala:458:21] reg [64:0] fregfile_28; // @[Core.scala:458:21] reg [64:0] fregfile_29; // @[Core.scala:458:21] reg [64:0] fregfile_30; // @[Core.scala:458:21] reg [64:0] fregfile_31; // @[Core.scala:458:21] reg fsboard_0; // @[Core.scala:459:20] reg fsboard_1; // @[Core.scala:459:20] reg fsboard_2; // @[Core.scala:459:20] reg fsboard_3; // @[Core.scala:459:20] reg fsboard_4; // @[Core.scala:459:20] reg fsboard_5; // @[Core.scala:459:20] reg fsboard_6; // @[Core.scala:459:20] reg fsboard_7; // @[Core.scala:459:20] reg fsboard_8; // @[Core.scala:459:20] reg fsboard_9; // @[Core.scala:459:20] reg fsboard_10; // @[Core.scala:459:20] reg fsboard_11; // @[Core.scala:459:20] reg fsboard_12; // @[Core.scala:459:20] reg fsboard_13; // @[Core.scala:459:20] reg fsboard_14; // @[Core.scala:459:20] reg fsboard_15; // @[Core.scala:459:20] reg fsboard_16; // @[Core.scala:459:20] reg fsboard_17; // @[Core.scala:459:20] reg fsboard_18; // @[Core.scala:459:20] reg fsboard_19; // @[Core.scala:459:20] reg fsboard_20; // @[Core.scala:459:20] reg fsboard_21; // @[Core.scala:459:20] reg fsboard_22; // @[Core.scala:459:20] reg fsboard_23; // @[Core.scala:459:20] reg fsboard_24; // @[Core.scala:459:20] reg fsboard_25; // @[Core.scala:459:20] reg fsboard_26; // @[Core.scala:459:20] reg fsboard_27; // @[Core.scala:459:20] reg fsboard_28; // @[Core.scala:459:20] reg fsboard_29; // @[Core.scala:459:20] reg fsboard_30; // @[Core.scala:459:20] reg fsboard_31; // @[Core.scala:459:20] wire _fsboard_bsy_T = fsboard_0 & fsboard_1; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_1 = _fsboard_bsy_T & fsboard_2; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_2 = _fsboard_bsy_T_1 & fsboard_3; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_3 = _fsboard_bsy_T_2 & fsboard_4; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_4 = _fsboard_bsy_T_3 & fsboard_5; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_5 = _fsboard_bsy_T_4 & fsboard_6; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_6 = _fsboard_bsy_T_5 & fsboard_7; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_7 = _fsboard_bsy_T_6 & fsboard_8; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_8 = _fsboard_bsy_T_7 & fsboard_9; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_9 = _fsboard_bsy_T_8 & fsboard_10; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_10 = _fsboard_bsy_T_9 & fsboard_11; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_11 = _fsboard_bsy_T_10 & fsboard_12; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_12 = _fsboard_bsy_T_11 & fsboard_13; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_13 = _fsboard_bsy_T_12 & fsboard_14; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_14 = _fsboard_bsy_T_13 & fsboard_15; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_15 = _fsboard_bsy_T_14 & fsboard_16; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_16 = _fsboard_bsy_T_15 & fsboard_17; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_17 = _fsboard_bsy_T_16 & fsboard_18; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_18 = _fsboard_bsy_T_17 & fsboard_19; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_19 = _fsboard_bsy_T_18 & fsboard_20; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_20 = _fsboard_bsy_T_19 & fsboard_21; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_21 = _fsboard_bsy_T_20 & fsboard_22; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_22 = _fsboard_bsy_T_21 & fsboard_23; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_23 = _fsboard_bsy_T_22 & fsboard_24; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_24 = _fsboard_bsy_T_23 & fsboard_25; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_25 = _fsboard_bsy_T_24 & fsboard_26; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_26 = _fsboard_bsy_T_25 & fsboard_27; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_27 = _fsboard_bsy_T_26 & fsboard_28; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_28 = _fsboard_bsy_T_27 & fsboard_29; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_29 = _fsboard_bsy_T_28 & fsboard_30; // @[Core.scala:459:20, :460:35] wire _fsboard_bsy_T_30 = _fsboard_bsy_T_29 & fsboard_31; // @[Core.scala:459:20, :460:35] assign _fsboard_bsy_T_31 = ~_fsboard_bsy_T_30; // @[Core.scala:460:{18,35}] assign fsboard_bsy = _fsboard_bsy_T_31; // @[Core.scala:403:25, :460:18] wire fsboard_set_0; // @[Core.scala:461:29] wire fsboard_set_1; // @[Core.scala:461:29] wire fsboard_set_2; // @[Core.scala:461:29] wire fsboard_set_3; // @[Core.scala:461:29] wire fsboard_set_4; // @[Core.scala:461:29] wire fsboard_set_5; // @[Core.scala:461:29] wire fsboard_set_6; // @[Core.scala:461:29] wire fsboard_set_7; // @[Core.scala:461:29] wire fsboard_set_8; // @[Core.scala:461:29] wire fsboard_set_9; // @[Core.scala:461:29] wire fsboard_set_10; // @[Core.scala:461:29] wire fsboard_set_11; // @[Core.scala:461:29] wire fsboard_set_12; // @[Core.scala:461:29] wire fsboard_set_13; // @[Core.scala:461:29] wire fsboard_set_14; // @[Core.scala:461:29] wire fsboard_set_15; // @[Core.scala:461:29] wire fsboard_set_16; // @[Core.scala:461:29] wire fsboard_set_17; // @[Core.scala:461:29] wire fsboard_set_18; // @[Core.scala:461:29] wire fsboard_set_19; // @[Core.scala:461:29] wire fsboard_set_20; // @[Core.scala:461:29] wire fsboard_set_21; // @[Core.scala:461:29] wire fsboard_set_22; // @[Core.scala:461:29] wire fsboard_set_23; // @[Core.scala:461:29] wire fsboard_set_24; // @[Core.scala:461:29] wire fsboard_set_25; // @[Core.scala:461:29] wire fsboard_set_26; // @[Core.scala:461:29] wire fsboard_set_27; // @[Core.scala:461:29] wire fsboard_set_28; // @[Core.scala:461:29] wire fsboard_set_29; // @[Core.scala:461:29] wire fsboard_set_30; // @[Core.scala:461:29] wire fsboard_set_31; // @[Core.scala:461:29] wire fsboard_clear_0; // @[Core.scala:462:31] wire fsboard_clear_1; // @[Core.scala:462:31] wire fsboard_clear_2; // @[Core.scala:462:31] wire fsboard_clear_3; // @[Core.scala:462:31] wire fsboard_clear_4; // @[Core.scala:462:31] wire fsboard_clear_5; // @[Core.scala:462:31] wire fsboard_clear_6; // @[Core.scala:462:31] wire fsboard_clear_7; // @[Core.scala:462:31] wire fsboard_clear_8; // @[Core.scala:462:31] wire fsboard_clear_9; // @[Core.scala:462:31] wire fsboard_clear_10; // @[Core.scala:462:31] wire fsboard_clear_11; // @[Core.scala:462:31] wire fsboard_clear_12; // @[Core.scala:462:31] wire fsboard_clear_13; // @[Core.scala:462:31] wire fsboard_clear_14; // @[Core.scala:462:31] wire fsboard_clear_15; // @[Core.scala:462:31] wire fsboard_clear_16; // @[Core.scala:462:31] wire fsboard_clear_17; // @[Core.scala:462:31] wire fsboard_clear_18; // @[Core.scala:462:31] wire fsboard_clear_19; // @[Core.scala:462:31] wire fsboard_clear_20; // @[Core.scala:462:31] wire fsboard_clear_21; // @[Core.scala:462:31] wire fsboard_clear_22; // @[Core.scala:462:31] wire fsboard_clear_23; // @[Core.scala:462:31] wire fsboard_clear_24; // @[Core.scala:462:31] wire fsboard_clear_25; // @[Core.scala:462:31] wire fsboard_clear_26; // @[Core.scala:462:31] wire fsboard_clear_27; // @[Core.scala:462:31] wire fsboard_clear_28; // @[Core.scala:462:31] wire fsboard_clear_29; // @[Core.scala:462:31] wire fsboard_clear_30; // @[Core.scala:462:31] wire fsboard_clear_31; // @[Core.scala:462:31] wire _fsboard_0_T = ~fsboard_clear_0; // @[Core.scala:462:31, :464:34] wire _fsboard_0_T_1 = fsboard_0 & _fsboard_0_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_0_T_2 = _fsboard_0_T_1 | fsboard_set_0; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_1_T = ~fsboard_clear_1; // @[Core.scala:462:31, :464:34] wire _fsboard_1_T_1 = fsboard_1 & _fsboard_1_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_1_T_2 = _fsboard_1_T_1 | fsboard_set_1; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_2_T = ~fsboard_clear_2; // @[Core.scala:462:31, :464:34] wire _fsboard_2_T_1 = fsboard_2 & _fsboard_2_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_2_T_2 = _fsboard_2_T_1 | fsboard_set_2; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_3_T = ~fsboard_clear_3; // @[Core.scala:462:31, :464:34] wire _fsboard_3_T_1 = fsboard_3 & _fsboard_3_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_3_T_2 = _fsboard_3_T_1 | fsboard_set_3; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_4_T = ~fsboard_clear_4; // @[Core.scala:462:31, :464:34] wire _fsboard_4_T_1 = fsboard_4 & _fsboard_4_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_4_T_2 = _fsboard_4_T_1 | fsboard_set_4; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_5_T = ~fsboard_clear_5; // @[Core.scala:462:31, :464:34] wire _fsboard_5_T_1 = fsboard_5 & _fsboard_5_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_5_T_2 = _fsboard_5_T_1 | fsboard_set_5; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_6_T = ~fsboard_clear_6; // @[Core.scala:462:31, :464:34] wire _fsboard_6_T_1 = fsboard_6 & _fsboard_6_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_6_T_2 = _fsboard_6_T_1 | fsboard_set_6; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_7_T = ~fsboard_clear_7; // @[Core.scala:462:31, :464:34] wire _fsboard_7_T_1 = fsboard_7 & _fsboard_7_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_7_T_2 = _fsboard_7_T_1 | fsboard_set_7; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_8_T = ~fsboard_clear_8; // @[Core.scala:462:31, :464:34] wire _fsboard_8_T_1 = fsboard_8 & _fsboard_8_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_8_T_2 = _fsboard_8_T_1 | fsboard_set_8; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_9_T = ~fsboard_clear_9; // @[Core.scala:462:31, :464:34] wire _fsboard_9_T_1 = fsboard_9 & _fsboard_9_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_9_T_2 = _fsboard_9_T_1 | fsboard_set_9; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_10_T = ~fsboard_clear_10; // @[Core.scala:462:31, :464:34] wire _fsboard_10_T_1 = fsboard_10 & _fsboard_10_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_10_T_2 = _fsboard_10_T_1 | fsboard_set_10; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_11_T = ~fsboard_clear_11; // @[Core.scala:462:31, :464:34] wire _fsboard_11_T_1 = fsboard_11 & _fsboard_11_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_11_T_2 = _fsboard_11_T_1 | fsboard_set_11; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_12_T = ~fsboard_clear_12; // @[Core.scala:462:31, :464:34] wire _fsboard_12_T_1 = fsboard_12 & _fsboard_12_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_12_T_2 = _fsboard_12_T_1 | fsboard_set_12; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_13_T = ~fsboard_clear_13; // @[Core.scala:462:31, :464:34] wire _fsboard_13_T_1 = fsboard_13 & _fsboard_13_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_13_T_2 = _fsboard_13_T_1 | fsboard_set_13; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_14_T = ~fsboard_clear_14; // @[Core.scala:462:31, :464:34] wire _fsboard_14_T_1 = fsboard_14 & _fsboard_14_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_14_T_2 = _fsboard_14_T_1 | fsboard_set_14; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_15_T = ~fsboard_clear_15; // @[Core.scala:462:31, :464:34] wire _fsboard_15_T_1 = fsboard_15 & _fsboard_15_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_15_T_2 = _fsboard_15_T_1 | fsboard_set_15; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_16_T = ~fsboard_clear_16; // @[Core.scala:462:31, :464:34] wire _fsboard_16_T_1 = fsboard_16 & _fsboard_16_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_16_T_2 = _fsboard_16_T_1 | fsboard_set_16; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_17_T = ~fsboard_clear_17; // @[Core.scala:462:31, :464:34] wire _fsboard_17_T_1 = fsboard_17 & _fsboard_17_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_17_T_2 = _fsboard_17_T_1 | fsboard_set_17; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_18_T = ~fsboard_clear_18; // @[Core.scala:462:31, :464:34] wire _fsboard_18_T_1 = fsboard_18 & _fsboard_18_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_18_T_2 = _fsboard_18_T_1 | fsboard_set_18; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_19_T = ~fsboard_clear_19; // @[Core.scala:462:31, :464:34] wire _fsboard_19_T_1 = fsboard_19 & _fsboard_19_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_19_T_2 = _fsboard_19_T_1 | fsboard_set_19; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_20_T = ~fsboard_clear_20; // @[Core.scala:462:31, :464:34] wire _fsboard_20_T_1 = fsboard_20 & _fsboard_20_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_20_T_2 = _fsboard_20_T_1 | fsboard_set_20; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_21_T = ~fsboard_clear_21; // @[Core.scala:462:31, :464:34] wire _fsboard_21_T_1 = fsboard_21 & _fsboard_21_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_21_T_2 = _fsboard_21_T_1 | fsboard_set_21; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_22_T = ~fsboard_clear_22; // @[Core.scala:462:31, :464:34] wire _fsboard_22_T_1 = fsboard_22 & _fsboard_22_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_22_T_2 = _fsboard_22_T_1 | fsboard_set_22; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_23_T = ~fsboard_clear_23; // @[Core.scala:462:31, :464:34] wire _fsboard_23_T_1 = fsboard_23 & _fsboard_23_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_23_T_2 = _fsboard_23_T_1 | fsboard_set_23; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_24_T = ~fsboard_clear_24; // @[Core.scala:462:31, :464:34] wire _fsboard_24_T_1 = fsboard_24 & _fsboard_24_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_24_T_2 = _fsboard_24_T_1 | fsboard_set_24; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_25_T = ~fsboard_clear_25; // @[Core.scala:462:31, :464:34] wire _fsboard_25_T_1 = fsboard_25 & _fsboard_25_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_25_T_2 = _fsboard_25_T_1 | fsboard_set_25; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_26_T = ~fsboard_clear_26; // @[Core.scala:462:31, :464:34] wire _fsboard_26_T_1 = fsboard_26 & _fsboard_26_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_26_T_2 = _fsboard_26_T_1 | fsboard_set_26; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_27_T = ~fsboard_clear_27; // @[Core.scala:462:31, :464:34] wire _fsboard_27_T_1 = fsboard_27 & _fsboard_27_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_27_T_2 = _fsboard_27_T_1 | fsboard_set_27; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_28_T = ~fsboard_clear_28; // @[Core.scala:462:31, :464:34] wire _fsboard_28_T_1 = fsboard_28 & _fsboard_28_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_28_T_2 = _fsboard_28_T_1 | fsboard_set_28; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_29_T = ~fsboard_clear_29; // @[Core.scala:462:31, :464:34] wire _fsboard_29_T_1 = fsboard_29 & _fsboard_29_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_29_T_2 = _fsboard_29_T_1 | fsboard_set_29; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_30_T = ~fsboard_clear_30; // @[Core.scala:462:31, :464:34] wire _fsboard_30_T_1 = fsboard_30 & _fsboard_30_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_30_T_2 = _fsboard_30_T_1 | fsboard_set_30; // @[Core.scala:461:29, :464:{31,53}] wire _fsboard_31_T = ~fsboard_clear_31; // @[Core.scala:462:31, :464:34] wire _fsboard_31_T_1 = fsboard_31 & _fsboard_31_T; // @[Core.scala:459:20, :464:{31,34}] wire _fsboard_31_T_2 = _fsboard_31_T_1 | fsboard_set_31; // @[Core.scala:461:29, :464:{31,53}] wire _ex_fp_data_hazard_0_T_3; // @[Core.scala:497:109] wire ex_fp_data_hazard_0; // @[Core.scala:470:59] wire frd_data_hazard_1; // @[Core.scala:474:68] wire ex_fp_data_hazard_1; // @[Core.scala:470:59] wire [4:0] ex_frd = ex_uops_reg_0_bits_inst[11:7]; // @[Core.scala:71:24] wire [4:0] _mul_io_req_bits_tag_T = ex_uops_reg_0_bits_inst[11:7]; // @[Core.scala:71:24] assign _ex_bypasses_0_dst_T = ex_uops_reg_0_bits_inst[11:7]; // @[Core.scala:71:24] wire frd_maybe_hazard_bypass_hit; // @[Core.scala:292:30] wire [31:0] _GEN_88 = {{fsboard_31}, {fsboard_30}, {fsboard_29}, {fsboard_28}, {fsboard_27}, {fsboard_26}, {fsboard_25}, {fsboard_24}, {fsboard_23}, {fsboard_22}, {fsboard_21}, {fsboard_20}, {fsboard_19}, {fsboard_18}, {fsboard_17}, {fsboard_16}, {fsboard_15}, {fsboard_14}, {fsboard_13}, {fsboard_12}, {fsboard_11}, {fsboard_10}, {fsboard_9}, {fsboard_8}, {fsboard_7}, {fsboard_6}, {fsboard_5}, {fsboard_4}, {fsboard_3}, {fsboard_2}, {fsboard_1}, {fsboard_0}}; // @[Core.scala:292:30, :459:20] wire _frd_maybe_hazard_T = fp_com_bypasses_0_dst == ex_frd; // @[Core.scala:102:66, :295:30] wire _frd_maybe_hazard_T_1 = fp_com_bypasses_0_valid & _frd_maybe_hazard_T; // @[Core.scala:102:66, :295:{21,30}] wire _frd_maybe_hazard_T_2 = fp_com_bypasses_1_dst == ex_frd; // @[Core.scala:102:66, :295:30] wire _frd_maybe_hazard_T_3 = fp_com_bypasses_1_valid & _frd_maybe_hazard_T_2; // @[Core.scala:102:66, :295:{21,30}] wire _frd_maybe_hazard_T_4 = fp_mem_bypasses_0_dst == ex_frd; // @[Core.scala:101:66, :295:30] wire _frd_maybe_hazard_T_5 = fp_mem_bypasses_0_valid & _frd_maybe_hazard_T_4; // @[Core.scala:101:66, :295:{21,30}] wire _frd_maybe_hazard_T_6 = fp_mem_bypasses_1_dst == ex_frd; // @[Core.scala:101:66, :295:30] wire _frd_maybe_hazard_T_7 = fp_mem_bypasses_1_valid & _frd_maybe_hazard_T_6; // @[Core.scala:101:66, :295:{21,30}] assign frd_maybe_hazard_bypass_hit = ~(_frd_maybe_hazard_T_7 | _frd_maybe_hazard_T_5 | _frd_maybe_hazard_T_3 | _frd_maybe_hazard_T_1) & _GEN_88[ex_frd]; // @[Core.scala:292:30, :295:{21,38}, :296:20] wire frd_maybe_hazard = ~frd_maybe_hazard_bypass_hit; // @[Core.scala:292:30, :300:6] wire _frd_data_hazard_T = frd_maybe_hazard & ex_uops_reg_0_valid; // @[Core.scala:71:24, :300:6, :474:44] wire frd_data_hazard = _frd_data_hazard_T & ex_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:71:24, :474:{44,68}] wire [4:0] ex_frs1 = ex_uops_reg_0_bits_inst[19:15]; // @[Core.scala:71:24] wire [4:0] ex_frs2 = ex_uops_reg_0_bits_inst[24:20]; // @[Core.scala:71:24] wire [4:0] ex_frs3 = ex_uops_reg_0_bits_inst[31:27]; // @[Core.scala:71:24] wire frs1_hazard_bypass_hit; // @[Core.scala:292:30] wire _frs1_hazard_T = fp_com_bypasses_0_dst == ex_frs1; // @[Core.scala:102:66, :295:30] wire _frs1_hazard_T_1 = fp_com_bypasses_0_valid & _frs1_hazard_T; // @[Core.scala:102:66, :295:{21,30}] wire _frs1_hazard_T_2 = fp_com_bypasses_1_dst == ex_frs1; // @[Core.scala:102:66, :295:30] wire _frs1_hazard_T_3 = fp_com_bypasses_1_valid & _frs1_hazard_T_2; // @[Core.scala:102:66, :295:{21,30}] wire _frs1_hazard_T_4 = fp_mem_bypasses_0_dst == ex_frs1; // @[Core.scala:101:66, :295:30] wire _frs1_hazard_T_5 = fp_mem_bypasses_0_valid & _frs1_hazard_T_4; // @[Core.scala:101:66, :295:{21,30}] wire _frs1_hazard_T_6 = fp_mem_bypasses_1_dst == ex_frs1; // @[Core.scala:101:66, :295:30] wire _frs1_hazard_T_7 = fp_mem_bypasses_1_valid & _frs1_hazard_T_6; // @[Core.scala:101:66, :295:{21,30}] assign frs1_hazard_bypass_hit = ~(_frs1_hazard_T_7 | _frs1_hazard_T_5 | _frs1_hazard_T_3 | _frs1_hazard_T_1) & _GEN_88[ex_frs1]; // @[Core.scala:292:30, :295:{21,38}, :296:20] wire frs1_hazard = ~frs1_hazard_bypass_hit; // @[Core.scala:292:30, :300:6] wire frs2_hazard_bypass_hit; // @[Core.scala:292:30] wire _frs2_hazard_T = fp_com_bypasses_0_dst == ex_frs2; // @[Core.scala:102:66, :295:30] wire _frs2_hazard_T_1 = fp_com_bypasses_0_valid & _frs2_hazard_T; // @[Core.scala:102:66, :295:{21,30}] wire _frs2_hazard_T_2 = fp_com_bypasses_1_dst == ex_frs2; // @[Core.scala:102:66, :295:30] wire _frs2_hazard_T_3 = fp_com_bypasses_1_valid & _frs2_hazard_T_2; // @[Core.scala:102:66, :295:{21,30}] wire _frs2_hazard_T_4 = fp_mem_bypasses_0_dst == ex_frs2; // @[Core.scala:101:66, :295:30] wire _frs2_hazard_T_5 = fp_mem_bypasses_0_valid & _frs2_hazard_T_4; // @[Core.scala:101:66, :295:{21,30}] wire _frs2_hazard_T_6 = fp_mem_bypasses_1_dst == ex_frs2; // @[Core.scala:101:66, :295:30] wire _frs2_hazard_T_7 = fp_mem_bypasses_1_valid & _frs2_hazard_T_6; // @[Core.scala:101:66, :295:{21,30}] assign frs2_hazard_bypass_hit = ~(_frs2_hazard_T_7 | _frs2_hazard_T_5 | _frs2_hazard_T_3 | _frs2_hazard_T_1) & _GEN_88[ex_frs2]; // @[Core.scala:292:30, :295:{21,38}, :296:20] wire frs2_hazard = ~frs2_hazard_bypass_hit; // @[Core.scala:292:30, :300:6] wire frs3_hazard_bypass_hit; // @[Core.scala:292:30] wire _frs3_hazard_T = fp_com_bypasses_0_dst == ex_frs3; // @[Core.scala:102:66, :295:30] wire _frs3_hazard_T_1 = fp_com_bypasses_0_valid & _frs3_hazard_T; // @[Core.scala:102:66, :295:{21,30}] wire _frs3_hazard_T_2 = fp_com_bypasses_1_dst == ex_frs3; // @[Core.scala:102:66, :295:30] wire _frs3_hazard_T_3 = fp_com_bypasses_1_valid & _frs3_hazard_T_2; // @[Core.scala:102:66, :295:{21,30}] wire _frs3_hazard_T_4 = fp_mem_bypasses_0_dst == ex_frs3; // @[Core.scala:101:66, :295:30] wire _frs3_hazard_T_5 = fp_mem_bypasses_0_valid & _frs3_hazard_T_4; // @[Core.scala:101:66, :295:{21,30}] wire _frs3_hazard_T_6 = fp_mem_bypasses_1_dst == ex_frs3; // @[Core.scala:101:66, :295:30] wire _frs3_hazard_T_7 = fp_mem_bypasses_1_valid & _frs3_hazard_T_6; // @[Core.scala:101:66, :295:{21,30}] assign frs3_hazard_bypass_hit = ~(_frs3_hazard_T_7 | _frs3_hazard_T_5 | _frs3_hazard_T_3 | _frs3_hazard_T_1) & _GEN_88[ex_frs3]; // @[Core.scala:292:30, :295:{21,38}, :296:20] wire frs3_hazard = ~frs3_hazard_bypass_hit; // @[Core.scala:292:30, :300:6] wire frs1_data_hazard = frs1_hazard & ex_uops_reg_0_bits_ctrl_rfs1; // @[Core.scala:71:24, :300:6, :493:42] wire frs2_data_hazard = frs2_hazard & ex_uops_reg_0_bits_ctrl_rfs2; // @[Core.scala:71:24, :300:6, :494:42] wire frs3_data_hazard = frs3_hazard & ex_uops_reg_0_bits_ctrl_rfs3; // @[Core.scala:71:24, :300:6, :495:42] wire _ex_fp_data_hazard_0_T = frs1_data_hazard | frs2_data_hazard; // @[Core.scala:493:42, :494:42, :497:49] wire _ex_fp_data_hazard_0_T_1 = _ex_fp_data_hazard_0_T | frs3_data_hazard; // @[Core.scala:495:42, :497:{49,69}] wire _ex_fp_data_hazard_0_T_2 = _ex_fp_data_hazard_0_T_1 | frd_data_hazard; // @[Core.scala:474:68, :497:{69,89}] assign _ex_fp_data_hazard_0_T_3 = _ex_fp_data_hazard_0_T_2 & ex_uops_reg_0_valid; // @[Core.scala:71:24, :497:{89,109}] assign ex_fp_data_hazard_0 = _ex_fp_data_hazard_0_T_3; // @[Core.scala:470:59, :497:109] wire _fp_pipe_io_in_valid_T = ex_uops_reg_0_bits_fp_ctrl_ldst & ex_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:71:24] wire _fp_pipe_io_in_valid_T_1 = ~_fp_pipe_io_in_valid_T; // @[MicroOp.scala:78:{28,43}] wire _fp_pipe_io_in_valid_T_2 = ex_uops_reg_0_bits_ctrl_fp & _fp_pipe_io_in_valid_T_1; // @[Core.scala:71:24] wire _fp_pipe_io_in_valid_T_3 = ex_uops_reg_0_valid & _fp_pipe_io_in_valid_T_2; // @[Core.scala:71:24, :499:51] wire _fp_pipe_io_in_valid_T_4 = ~ex_uops_reg_0_bits_xcpt; // @[Core.scala:71:24, :499:85] wire _fp_pipe_io_in_valid_T_5 = _fp_pipe_io_in_valid_T_3 & _fp_pipe_io_in_valid_T_4; // @[Core.scala:499:{51,82,85}] wire _fp_pipe_io_in_valid_T_6 = ~ex_stall; // @[Core.scala:107:26, :122:11, :499:114] wire _fp_pipe_io_in_valid_T_7 = _fp_pipe_io_in_valid_T_5 & _fp_pipe_io_in_valid_T_6; // @[Core.scala:499:{82,111,114}] wire _fp_pipe_io_in_valid_T_8 = ~flush_rrd_ex; // @[Core.scala:110:30, :129:54, :499:127] wire _fp_pipe_io_in_valid_T_9 = _fp_pipe_io_in_valid_T_7 & _fp_pipe_io_in_valid_T_8; // @[Core.scala:499:{111,124,127}] wire [31:0][64:0] _GEN_89 = {{fregfile_31}, {fregfile_30}, {fregfile_29}, {fregfile_28}, {fregfile_27}, {fregfile_26}, {fregfile_25}, {fregfile_24}, {fregfile_23}, {fregfile_22}, {fregfile_21}, {fregfile_20}, {fregfile_19}, {fregfile_18}, {fregfile_17}, {fregfile_16}, {fregfile_15}, {fregfile_14}, {fregfile_13}, {fregfile_12}, {fregfile_11}, {fregfile_10}, {fregfile_9}, {fregfile_8}, {fregfile_7}, {fregfile_6}, {fregfile_5}, {fregfile_4}, {fregfile_3}, {fregfile_2}, {fregfile_1}, {fregfile_0}}; // @[Core.scala:458:21, :501:28] wire [4:0] ex_frd_1 = ex_uops_reg_1_bits_inst[11:7]; // @[Core.scala:71:24] assign _ex_bypasses_1_dst_T = ex_uops_reg_1_bits_inst[11:7]; // @[Core.scala:71:24] wire frd_maybe_hazard_bypass_hit_1; // @[Core.scala:292:30] wire _frd_maybe_hazard_T_8 = fp_com_bypasses_0_dst == ex_frd_1; // @[Core.scala:102:66, :295:30] wire _frd_maybe_hazard_T_9 = fp_com_bypasses_0_valid & _frd_maybe_hazard_T_8; // @[Core.scala:102:66, :295:{21,30}] wire _frd_maybe_hazard_T_10 = fp_com_bypasses_1_dst == ex_frd_1; // @[Core.scala:102:66, :295:30] wire _frd_maybe_hazard_T_11 = fp_com_bypasses_1_valid & _frd_maybe_hazard_T_10; // @[Core.scala:102:66, :295:{21,30}] wire _frd_maybe_hazard_T_12 = fp_mem_bypasses_0_dst == ex_frd_1; // @[Core.scala:101:66, :295:30] wire _frd_maybe_hazard_T_13 = fp_mem_bypasses_0_valid & _frd_maybe_hazard_T_12; // @[Core.scala:101:66, :295:{21,30}] wire _frd_maybe_hazard_T_14 = fp_mem_bypasses_1_dst == ex_frd_1; // @[Core.scala:101:66, :295:30] wire _frd_maybe_hazard_T_15 = fp_mem_bypasses_1_valid & _frd_maybe_hazard_T_14; // @[Core.scala:101:66, :295:{21,30}] assign frd_maybe_hazard_bypass_hit_1 = ~(_frd_maybe_hazard_T_15 | _frd_maybe_hazard_T_13 | _frd_maybe_hazard_T_11 | _frd_maybe_hazard_T_9) & _GEN_88[ex_frd_1]; // @[Core.scala:292:30, :295:{21,38}, :296:20] wire frd_maybe_hazard_1 = ~frd_maybe_hazard_bypass_hit_1; // @[Core.scala:292:30, :300:6] wire _frd_data_hazard_T_1 = frd_maybe_hazard_1 & ex_uops_reg_1_valid; // @[Core.scala:71:24, :300:6, :474:44] assign frd_data_hazard_1 = _frd_data_hazard_T_1 & ex_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:71:24, :474:{44,68}] assign ex_fp_data_hazard_1 = frd_data_hazard_1; // @[Core.scala:470:59, :474:68] wire _GEN_90 = ex_uops_reg_0_bits_ctrl_csr == 3'h6; // @[Core.scala:71:24] wire _ex_fcsr_data_hazard_T; // @[package.scala:16:47] assign _ex_fcsr_data_hazard_T = _GEN_90; // @[package.scala:16:47] wire _mem_uops_reg_0_bits_wdata_valid_T_6; // @[package.scala:16:47] assign _mem_uops_reg_0_bits_wdata_valid_T_6 = _GEN_90; // @[package.scala:16:47] wire _ex_bypasses_0_can_bypass_T_6; // @[package.scala:16:47] assign _ex_bypasses_0_can_bypass_T_6 = _GEN_90; // @[package.scala:16:47] wire _ex_fcsr_data_hazard_T_1 = &ex_uops_reg_0_bits_ctrl_csr; // @[Core.scala:71:24] wire _GEN_91 = ex_uops_reg_0_bits_ctrl_csr == 3'h5; // @[Core.scala:71:24] wire _ex_fcsr_data_hazard_T_2; // @[package.scala:16:47] assign _ex_fcsr_data_hazard_T_2 = _GEN_91; // @[package.scala:16:47] wire _mem_uops_reg_0_bits_wdata_valid_T_8; // @[package.scala:16:47] assign _mem_uops_reg_0_bits_wdata_valid_T_8 = _GEN_91; // @[package.scala:16:47] wire _ex_bypasses_0_can_bypass_T_8; // @[package.scala:16:47] assign _ex_bypasses_0_can_bypass_T_8 = _GEN_91; // @[package.scala:16:47] wire _ex_fcsr_data_hazard_T_3 = _ex_fcsr_data_hazard_T | _ex_fcsr_data_hazard_T_1; // @[package.scala:16:47, :81:59] wire _ex_fcsr_data_hazard_T_4 = _ex_fcsr_data_hazard_T_3 | _ex_fcsr_data_hazard_T_2; // @[package.scala:16:47, :81:59] wire _ex_fcsr_data_hazard_T_5 = ex_uops_reg_0_valid & _ex_fcsr_data_hazard_T_4; // @[Core.scala:71:24, :507:50] wire _ex_fcsr_data_hazard_T_6 = fsboard_bsy | mem_bsy; // @[Core.scala:115:51, :403:25, :507:96] wire _ex_fcsr_data_hazard_T_7 = _ex_fcsr_data_hazard_T_6 | com_bsy; // @[Core.scala:116:51, :507:{96,107}] wire ex_fcsr_data_hazard = _ex_fcsr_data_hazard_T_5 & _ex_fcsr_data_hazard_T_7; // @[Core.scala:507:{50,80,107}] wire _ex_stall_T_1 = ex_fcsr_data_hazard; // @[Core.scala:507:80, :626:19] wire _mul_io_req_valid_T = ex_uops_reg_0_valid & ex_uops_reg_0_bits_ctrl_mul; // @[Core.scala:71:24, :536:44] wire _mul_io_req_valid_T_1 = ~ex_stall; // @[Core.scala:107:26, :122:11, :536:79] wire _mul_io_req_valid_T_2 = _mul_io_req_valid_T & _mul_io_req_valid_T_1; // @[Core.scala:536:{44,76,79}] wire ex_dmem_oh_0 = ex_uops_reg_0_valid & ex_uops_reg_0_bits_ctrl_mem; // @[Core.scala:71:24, :543:50] wire ex_dmem_oh_1 = ex_uops_reg_1_valid & ex_uops_reg_1_bits_ctrl_mem; // @[Core.scala:71:24, :543:50] wire _ex_dmem_uop_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_WIRE_inst; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_WIRE_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_WIRE_pc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_edge_inst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_legal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_fp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rocc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_branch; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_jal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_jalr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rxs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_ctrl_sel_imm; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_ctrl_alu_fn; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_ctrl_mem_cmd; // @[Mux.scala:30:73] assign io_dmem_req_bits_cmd_0 = ex_dmem_uop_bits_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rfs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rfs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_rfs3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_wfd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_mul; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_ctrl_csr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_fence_i; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_fence; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_amo; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_dp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fp_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_rvc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_sfb_br; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_sfb_shadow; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_ras_head; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_xcpt; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_needs_replay; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_rs1_data; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_rs2_data; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_rs3_data; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_uses_memalu; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_uses_latealu; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_fra1; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_fra2; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_fra3; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_fexc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_mem_size; // @[Mux.scala:30:73] assign io_dmem_req_bits_size_0 = ex_dmem_uop_bits_mem_size; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_flush_pipe; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_legal; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_fp; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rocc; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_branch; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_jal; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_jalr; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] ex_dmem_uop_bits_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] ex_dmem_uop_bits_ctrl_sel_imm; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_ctrl_alu_fn; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_mem; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_wfd; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_mul; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_div; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] ex_dmem_uop_bits_ctrl_csr; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_fence; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_amo; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_dp; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_ctrl_vec; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire [7:0] ex_dmem_uop_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] ex_dmem_uop_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] ex_dmem_uop_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] ex_dmem_uop_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_btb_resp_valid; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] ex_dmem_uop_bits_next_pc_bits; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_wdata_valid; // @[Mux.scala:30:73] wire [63:0] ex_dmem_uop_bits_wdata_bits; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_ldst; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_wen; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_ren1; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_ren2; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_ren3; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_swap12; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fdivin_typeTagOut; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_fromint; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_toint; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_fma; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_div; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_wflags; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] ex_dmem_uop_bits_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] ex_dmem_uop_bits_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] ex_dmem_uop_bits_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] ex_dmem_uop_bits_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] ex_dmem_uop_bits_fdivin_in3; // @[Mux.scala:30:73] wire [31:0] ex_dmem_uop_bits_inst; // @[Mux.scala:30:73] wire [31:0] ex_dmem_uop_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] ex_dmem_uop_bits_pc; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_edge_inst; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_rvc; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_sfb_br; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_sfb_shadow; // @[Mux.scala:30:73] wire [2:0] ex_dmem_uop_bits_ras_head; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_taken; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] ex_dmem_uop_bits_xcpt_cause; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_needs_replay; // @[Mux.scala:30:73] wire [63:0] ex_dmem_uop_bits_rs1_data; // @[Mux.scala:30:73] wire [63:0] ex_dmem_uop_bits_rs2_data; // @[Mux.scala:30:73] wire [63:0] ex_dmem_uop_bits_rs3_data; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_uses_memalu; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_uses_latealu; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_fra1; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_fra2; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_fra3; // @[Mux.scala:30:73] wire [4:0] ex_dmem_uop_bits_fexc; // @[Mux.scala:30:73] wire ex_dmem_uop_bits_flush_pipe; // @[Mux.scala:30:73] wire ex_dmem_uop_valid; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_WIRE_114; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_inst = _ex_dmem_uop_WIRE_inst; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_WIRE_113; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_raw_inst = _ex_dmem_uop_WIRE_raw_inst; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_WIRE_112; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_pc = _ex_dmem_uop_WIRE_pc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_111; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_edge_inst = _ex_dmem_uop_WIRE_edge_inst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_legal; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_legal = _ex_dmem_uop_WIRE_ctrl_legal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_fp; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_fp = _ex_dmem_uop_WIRE_ctrl_fp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rocc; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rocc = _ex_dmem_uop_WIRE_ctrl_rocc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_branch; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_branch = _ex_dmem_uop_WIRE_ctrl_branch; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_jal; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_jal = _ex_dmem_uop_WIRE_ctrl_jal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_jalr; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_jalr = _ex_dmem_uop_WIRE_ctrl_jalr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rxs2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rxs2 = _ex_dmem_uop_WIRE_ctrl_rxs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rxs1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rxs1 = _ex_dmem_uop_WIRE_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_82_sel_alu2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_sel_alu2 = _ex_dmem_uop_WIRE_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_82_sel_alu1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_sel_alu1 = _ex_dmem_uop_WIRE_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_82_sel_imm; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_sel_imm = _ex_dmem_uop_WIRE_ctrl_sel_imm; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_alu_dw; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_alu_dw = _ex_dmem_uop_WIRE_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_82_alu_fn; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_alu_fn = _ex_dmem_uop_WIRE_ctrl_alu_fn; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_mem; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_mem = _ex_dmem_uop_WIRE_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_82_mem_cmd; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_mem_cmd = _ex_dmem_uop_WIRE_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rfs1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rfs1 = _ex_dmem_uop_WIRE_ctrl_rfs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rfs2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rfs2 = _ex_dmem_uop_WIRE_ctrl_rfs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_rfs3; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_rfs3 = _ex_dmem_uop_WIRE_ctrl_rfs3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_wfd; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_wfd = _ex_dmem_uop_WIRE_ctrl_wfd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_mul; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_mul = _ex_dmem_uop_WIRE_ctrl_mul; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_div; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_div = _ex_dmem_uop_WIRE_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_wxd; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_wxd = _ex_dmem_uop_WIRE_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_82_csr; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_csr = _ex_dmem_uop_WIRE_ctrl_csr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_fence_i; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_fence_i = _ex_dmem_uop_WIRE_ctrl_fence_i; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_fence; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_fence = _ex_dmem_uop_WIRE_ctrl_fence; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_amo; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_amo = _ex_dmem_uop_WIRE_ctrl_amo; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_dp; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_dp = _ex_dmem_uop_WIRE_ctrl_dp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_82_vec; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ctrl_vec = _ex_dmem_uop_WIRE_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_ldst; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_ldst = _ex_dmem_uop_WIRE_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_wen; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_wen = _ex_dmem_uop_WIRE_fp_ctrl_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_ren1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_ren1 = _ex_dmem_uop_WIRE_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_ren2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_ren2 = _ex_dmem_uop_WIRE_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_ren3; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_ren3 = _ex_dmem_uop_WIRE_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_swap12; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_swap12 = _ex_dmem_uop_WIRE_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_swap23; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_swap23 = _ex_dmem_uop_WIRE_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_64_typeTagIn; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_typeTagIn = _ex_dmem_uop_WIRE_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_64_typeTagOut; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_typeTagOut = _ex_dmem_uop_WIRE_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_fromint; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_fromint = _ex_dmem_uop_WIRE_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_toint; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_toint = _ex_dmem_uop_WIRE_fp_ctrl_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_fastpipe; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_fastpipe = _ex_dmem_uop_WIRE_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_fma; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_fma = _ex_dmem_uop_WIRE_fp_ctrl_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_div; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_div = _ex_dmem_uop_WIRE_fp_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_sqrt; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_sqrt = _ex_dmem_uop_WIRE_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_wflags; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_wflags = _ex_dmem_uop_WIRE_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_64_vec; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fp_ctrl_vec = _ex_dmem_uop_WIRE_fp_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_63; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_rvc = _ex_dmem_uop_WIRE_rvc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_50_valid; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_valid = _ex_dmem_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_cfiType = _ex_dmem_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_taken = _ex_dmem_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_mask = _ex_dmem_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_bridx = _ex_dmem_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_target = _ex_dmem_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_entry = _ex_dmem_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_bht_history = _ex_dmem_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_btb_resp_bits_bht_value = _ex_dmem_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_49; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_sfb_br = _ex_dmem_uop_WIRE_sfb_br; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_48; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_sfb_shadow = _ex_dmem_uop_WIRE_sfb_shadow; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_45_valid; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_next_pc_valid = _ex_dmem_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_WIRE_45_bits; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_next_pc_bits = _ex_dmem_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_44; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_ras_head = _ex_dmem_uop_WIRE_ras_head; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_43; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_taken = _ex_dmem_uop_WIRE_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_42; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_xcpt = _ex_dmem_uop_WIRE_xcpt; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_41; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_xcpt_cause = _ex_dmem_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_40; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_needs_replay = _ex_dmem_uop_WIRE_needs_replay; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_39; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_rs1_data = _ex_dmem_uop_WIRE_rs1_data; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_38; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_rs2_data = _ex_dmem_uop_WIRE_rs2_data; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_37; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_rs3_data = _ex_dmem_uop_WIRE_rs3_data; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_36; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_uses_memalu = _ex_dmem_uop_WIRE_uses_memalu; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_35; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_uses_latealu = _ex_dmem_uop_WIRE_uses_latealu; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_32_valid; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_wdata_valid = _ex_dmem_uop_WIRE_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_32_bits; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_wdata_bits = _ex_dmem_uop_WIRE_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_31; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fra1 = _ex_dmem_uop_WIRE_fra1; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_30; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fra2 = _ex_dmem_uop_WIRE_fra2; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_29; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fra3 = _ex_dmem_uop_WIRE_fra3; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_28; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fexc = _ex_dmem_uop_WIRE_fexc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_ldst; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_ldst = _ex_dmem_uop_WIRE_fdivin_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_wen; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_wen = _ex_dmem_uop_WIRE_fdivin_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_ren1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_ren1 = _ex_dmem_uop_WIRE_fdivin_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_ren2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_ren2 = _ex_dmem_uop_WIRE_fdivin_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_ren3; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_ren3 = _ex_dmem_uop_WIRE_fdivin_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_swap12; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_swap12 = _ex_dmem_uop_WIRE_fdivin_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_swap23; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_swap23 = _ex_dmem_uop_WIRE_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_3_typeTagIn; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_typeTagIn = _ex_dmem_uop_WIRE_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_3_typeTagOut; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_typeTagOut = _ex_dmem_uop_WIRE_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_fromint; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_fromint = _ex_dmem_uop_WIRE_fdivin_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_toint; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_toint = _ex_dmem_uop_WIRE_fdivin_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_fastpipe; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_fastpipe = _ex_dmem_uop_WIRE_fdivin_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_fma; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_fma = _ex_dmem_uop_WIRE_fdivin_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_div; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_div = _ex_dmem_uop_WIRE_fdivin_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_sqrt; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_sqrt = _ex_dmem_uop_WIRE_fdivin_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_wflags; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_wflags = _ex_dmem_uop_WIRE_fdivin_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_3_vec; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_vec = _ex_dmem_uop_WIRE_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_3_rm; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_rm = _ex_dmem_uop_WIRE_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_3_fmaCmd; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_fmaCmd = _ex_dmem_uop_WIRE_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_3_typ; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_typ = _ex_dmem_uop_WIRE_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_3_fmt; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_fmt = _ex_dmem_uop_WIRE_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_3_in1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_in1 = _ex_dmem_uop_WIRE_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_3_in2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_in2 = _ex_dmem_uop_WIRE_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_3_in3; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_fdivin_in3 = _ex_dmem_uop_WIRE_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_2; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_mem_size = _ex_dmem_uop_WIRE_mem_size; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_1; // @[Mux.scala:30:73] assign ex_dmem_uop_bits_flush_pipe = _ex_dmem_uop_WIRE_flush_pipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T = ex_dmem_oh_0 & ex_uops_reg_0_bits_flush_pipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_1 = ex_dmem_oh_1 & ex_uops_reg_1_bits_flush_pipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_2 = _ex_dmem_uop_T | _ex_dmem_uop_T_1; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_1 = _ex_dmem_uop_T_2; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_flush_pipe = _ex_dmem_uop_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_3 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_4 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_5 = _ex_dmem_uop_T_3 | _ex_dmem_uop_T_4; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_2 = _ex_dmem_uop_T_5; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_mem_size = _ex_dmem_uop_WIRE_2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_27; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_ldst = _ex_dmem_uop_WIRE_3_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_26; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_wen = _ex_dmem_uop_WIRE_3_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_25; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_ren1 = _ex_dmem_uop_WIRE_3_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_24; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_ren2 = _ex_dmem_uop_WIRE_3_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_23; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_ren3 = _ex_dmem_uop_WIRE_3_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_22; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_swap12 = _ex_dmem_uop_WIRE_3_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_21; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_swap23 = _ex_dmem_uop_WIRE_3_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_20; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_typeTagIn = _ex_dmem_uop_WIRE_3_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_19; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_typeTagOut = _ex_dmem_uop_WIRE_3_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_18; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_fromint = _ex_dmem_uop_WIRE_3_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_17; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_toint = _ex_dmem_uop_WIRE_3_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_16; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_fastpipe = _ex_dmem_uop_WIRE_3_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_15; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_fma = _ex_dmem_uop_WIRE_3_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_14; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_div = _ex_dmem_uop_WIRE_3_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_13; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_sqrt = _ex_dmem_uop_WIRE_3_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_12; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_wflags = _ex_dmem_uop_WIRE_3_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_11; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_vec = _ex_dmem_uop_WIRE_3_vec; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_10; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_rm = _ex_dmem_uop_WIRE_3_rm; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_9; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_fmaCmd = _ex_dmem_uop_WIRE_3_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_8; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_typ = _ex_dmem_uop_WIRE_3_typ; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_7; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_fmt = _ex_dmem_uop_WIRE_3_fmt; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_6; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_in1 = _ex_dmem_uop_WIRE_3_in1; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_5; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_in2 = _ex_dmem_uop_WIRE_3_in2; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_WIRE_4; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fdivin_in3 = _ex_dmem_uop_WIRE_3_in3; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_6 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_7 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_8 = _ex_dmem_uop_T_6 | _ex_dmem_uop_T_7; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_4 = _ex_dmem_uop_T_8; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_in3 = _ex_dmem_uop_WIRE_4; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_9 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_10 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_11 = _ex_dmem_uop_T_9 | _ex_dmem_uop_T_10; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_5 = _ex_dmem_uop_T_11; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_in2 = _ex_dmem_uop_WIRE_5; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_12 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_13 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _ex_dmem_uop_T_14 = _ex_dmem_uop_T_12 | _ex_dmem_uop_T_13; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_6 = _ex_dmem_uop_T_14; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_in1 = _ex_dmem_uop_WIRE_6; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_15 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_16 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_17 = _ex_dmem_uop_T_15 | _ex_dmem_uop_T_16; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_7 = _ex_dmem_uop_T_17; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_fmt = _ex_dmem_uop_WIRE_7; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_18 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_19 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_20 = _ex_dmem_uop_T_18 | _ex_dmem_uop_T_19; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_8 = _ex_dmem_uop_T_20; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_typ = _ex_dmem_uop_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_21 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_22 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_23 = _ex_dmem_uop_T_21 | _ex_dmem_uop_T_22; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_9 = _ex_dmem_uop_T_23; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_fmaCmd = _ex_dmem_uop_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_24 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_25 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_26 = _ex_dmem_uop_T_24 | _ex_dmem_uop_T_25; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_10 = _ex_dmem_uop_T_26; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_rm = _ex_dmem_uop_WIRE_10; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_27 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_28 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_29 = _ex_dmem_uop_T_27 | _ex_dmem_uop_T_28; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_11 = _ex_dmem_uop_T_29; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_vec = _ex_dmem_uop_WIRE_11; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_30 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_31 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_32 = _ex_dmem_uop_T_30 | _ex_dmem_uop_T_31; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_12 = _ex_dmem_uop_T_32; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_wflags = _ex_dmem_uop_WIRE_12; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_33 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_34 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_35 = _ex_dmem_uop_T_33 | _ex_dmem_uop_T_34; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_13 = _ex_dmem_uop_T_35; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_sqrt = _ex_dmem_uop_WIRE_13; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_36 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_37 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_38 = _ex_dmem_uop_T_36 | _ex_dmem_uop_T_37; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_14 = _ex_dmem_uop_T_38; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_div = _ex_dmem_uop_WIRE_14; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_39 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_40 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_41 = _ex_dmem_uop_T_39 | _ex_dmem_uop_T_40; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_15 = _ex_dmem_uop_T_41; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_fma = _ex_dmem_uop_WIRE_15; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_42 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_43 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_44 = _ex_dmem_uop_T_42 | _ex_dmem_uop_T_43; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_16 = _ex_dmem_uop_T_44; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_fastpipe = _ex_dmem_uop_WIRE_16; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_45 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_46 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_47 = _ex_dmem_uop_T_45 | _ex_dmem_uop_T_46; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_17 = _ex_dmem_uop_T_47; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_toint = _ex_dmem_uop_WIRE_17; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_48 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_49 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_50 = _ex_dmem_uop_T_48 | _ex_dmem_uop_T_49; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_18 = _ex_dmem_uop_T_50; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_fromint = _ex_dmem_uop_WIRE_18; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_51 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_52 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_53 = _ex_dmem_uop_T_51 | _ex_dmem_uop_T_52; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_19 = _ex_dmem_uop_T_53; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_typeTagOut = _ex_dmem_uop_WIRE_19; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_54 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_55 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_56 = _ex_dmem_uop_T_54 | _ex_dmem_uop_T_55; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_20 = _ex_dmem_uop_T_56; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_typeTagIn = _ex_dmem_uop_WIRE_20; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_57 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_58 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_59 = _ex_dmem_uop_T_57 | _ex_dmem_uop_T_58; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_21 = _ex_dmem_uop_T_59; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_swap23 = _ex_dmem_uop_WIRE_21; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_60 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_61 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_62 = _ex_dmem_uop_T_60 | _ex_dmem_uop_T_61; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_22 = _ex_dmem_uop_T_62; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_swap12 = _ex_dmem_uop_WIRE_22; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_63 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_64 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_65 = _ex_dmem_uop_T_63 | _ex_dmem_uop_T_64; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_23 = _ex_dmem_uop_T_65; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_ren3 = _ex_dmem_uop_WIRE_23; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_66 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_67 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_68 = _ex_dmem_uop_T_66 | _ex_dmem_uop_T_67; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_24 = _ex_dmem_uop_T_68; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_ren2 = _ex_dmem_uop_WIRE_24; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_69 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_70 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_71 = _ex_dmem_uop_T_69 | _ex_dmem_uop_T_70; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_25 = _ex_dmem_uop_T_71; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_ren1 = _ex_dmem_uop_WIRE_25; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_72 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_73 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_74 = _ex_dmem_uop_T_72 | _ex_dmem_uop_T_73; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_26 = _ex_dmem_uop_T_74; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_wen = _ex_dmem_uop_WIRE_26; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_75 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_76 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_77 = _ex_dmem_uop_T_75 | _ex_dmem_uop_T_76; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_27 = _ex_dmem_uop_T_77; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_3_ldst = _ex_dmem_uop_WIRE_27; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_78 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_79 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_80 = _ex_dmem_uop_T_78 | _ex_dmem_uop_T_79; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_28 = _ex_dmem_uop_T_80; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fexc = _ex_dmem_uop_WIRE_28; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_81 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_82 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_83 = _ex_dmem_uop_T_81 | _ex_dmem_uop_T_82; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_29 = _ex_dmem_uop_T_83; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fra3 = _ex_dmem_uop_WIRE_29; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_84 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_85 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_86 = _ex_dmem_uop_T_84 | _ex_dmem_uop_T_85; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_30 = _ex_dmem_uop_T_86; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fra2 = _ex_dmem_uop_WIRE_30; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_87 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_88 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_89 = _ex_dmem_uop_T_87 | _ex_dmem_uop_T_88; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_31 = _ex_dmem_uop_T_89; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fra1 = _ex_dmem_uop_WIRE_31; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_34; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_wdata_valid = _ex_dmem_uop_WIRE_32_valid; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_WIRE_33; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_wdata_bits = _ex_dmem_uop_WIRE_32_bits; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_90 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_91 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_92 = _ex_dmem_uop_T_90 | _ex_dmem_uop_T_91; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_33 = _ex_dmem_uop_T_92; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_32_bits = _ex_dmem_uop_WIRE_33; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_93 = ex_dmem_oh_0 & ex_uops_reg_0_bits_wdata_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_94 = ex_dmem_oh_1 & ex_uops_reg_1_bits_wdata_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_95 = _ex_dmem_uop_T_93 | _ex_dmem_uop_T_94; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_34 = _ex_dmem_uop_T_95; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_32_valid = _ex_dmem_uop_WIRE_34; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_97 = ex_dmem_oh_1 & ex_uops_reg_1_bits_uses_latealu; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_98 = _ex_dmem_uop_T_97; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_35 = _ex_dmem_uop_T_98; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_uses_latealu = _ex_dmem_uop_WIRE_35; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_100 = ex_dmem_oh_1 & ex_uops_reg_1_bits_uses_memalu; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_101 = _ex_dmem_uop_T_100; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_36 = _ex_dmem_uop_T_101; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_uses_memalu = _ex_dmem_uop_WIRE_36; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_102 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_103 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_104 = _ex_dmem_uop_T_102 | _ex_dmem_uop_T_103; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_37 = _ex_dmem_uop_T_104; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_rs3_data = _ex_dmem_uop_WIRE_37; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_105 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_106 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_107 = _ex_dmem_uop_T_105 | _ex_dmem_uop_T_106; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_38 = _ex_dmem_uop_T_107; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_rs2_data = _ex_dmem_uop_WIRE_38; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_108 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_109 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_110 = _ex_dmem_uop_T_108 | _ex_dmem_uop_T_109; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_39 = _ex_dmem_uop_T_110; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_rs1_data = _ex_dmem_uop_WIRE_39; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_111 = ex_dmem_oh_0 & ex_uops_reg_0_bits_needs_replay; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_112 = ex_dmem_oh_1 & ex_uops_reg_1_bits_needs_replay; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_113 = _ex_dmem_uop_T_111 | _ex_dmem_uop_T_112; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_40 = _ex_dmem_uop_T_113; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_needs_replay = _ex_dmem_uop_WIRE_40; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_114 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_115 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _ex_dmem_uop_T_116 = _ex_dmem_uop_T_114 | _ex_dmem_uop_T_115; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_41 = _ex_dmem_uop_T_116; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_xcpt_cause = _ex_dmem_uop_WIRE_41; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_117 = ex_dmem_oh_0 & ex_uops_reg_0_bits_xcpt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_118 = ex_dmem_oh_1 & ex_uops_reg_1_bits_xcpt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_119 = _ex_dmem_uop_T_117 | _ex_dmem_uop_T_118; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_42 = _ex_dmem_uop_T_119; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_xcpt = _ex_dmem_uop_WIRE_42; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_120 = ex_dmem_oh_0 & ex_uops_reg_0_bits_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_121 = ex_dmem_oh_1 & ex_uops_reg_1_bits_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_122 = _ex_dmem_uop_T_120 | _ex_dmem_uop_T_121; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_43 = _ex_dmem_uop_T_122; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_taken = _ex_dmem_uop_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_123 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_124 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_125 = _ex_dmem_uop_T_123 | _ex_dmem_uop_T_124; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_44 = _ex_dmem_uop_T_125; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ras_head = _ex_dmem_uop_WIRE_44; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_47; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_next_pc_valid = _ex_dmem_uop_WIRE_45_valid; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_WIRE_46; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_next_pc_bits = _ex_dmem_uop_WIRE_45_bits; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_126 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_127 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_128 = _ex_dmem_uop_T_126 | _ex_dmem_uop_T_127; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_46 = _ex_dmem_uop_T_128; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_45_bits = _ex_dmem_uop_WIRE_46; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_129 = ex_dmem_oh_0 & ex_uops_reg_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_130 = ex_dmem_oh_1 & ex_uops_reg_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_131 = _ex_dmem_uop_T_129 | _ex_dmem_uop_T_130; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_47 = _ex_dmem_uop_T_131; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_45_valid = _ex_dmem_uop_WIRE_47; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_133 = ex_dmem_oh_1 & ex_uops_reg_1_bits_sfb_shadow; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_134 = _ex_dmem_uop_T_133; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_48 = _ex_dmem_uop_T_134; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_sfb_shadow = _ex_dmem_uop_WIRE_48; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_135 = ex_dmem_oh_0 & ex_uops_reg_0_bits_sfb_br; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_136 = ex_dmem_oh_1 & ex_uops_reg_1_bits_sfb_br; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_137 = _ex_dmem_uop_T_135 | _ex_dmem_uop_T_136; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_49 = _ex_dmem_uop_T_137; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_sfb_br = _ex_dmem_uop_WIRE_49; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_61; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_valid = _ex_dmem_uop_WIRE_50_valid; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_cfiType = _ex_dmem_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_51_taken; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_taken = _ex_dmem_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_WIRE_51_mask; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_mask = _ex_dmem_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_51_bridx; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_bridx = _ex_dmem_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_WIRE_51_target; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_target = _ex_dmem_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_WIRE_51_entry; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_entry = _ex_dmem_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_bht_history = _ex_dmem_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_btb_resp_bits_bht_value = _ex_dmem_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_60; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_cfiType = _ex_dmem_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_59; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_taken = _ex_dmem_uop_WIRE_51_taken; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_WIRE_58; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_mask = _ex_dmem_uop_WIRE_51_mask; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_57; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_bridx = _ex_dmem_uop_WIRE_51_bridx; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_WIRE_56; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_target = _ex_dmem_uop_WIRE_51_target; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_WIRE_55; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_entry = _ex_dmem_uop_WIRE_51_entry; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_WIRE_52_history; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_bht_history = _ex_dmem_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_52_value; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_bits_bht_value = _ex_dmem_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_WIRE_54; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_bht_history = _ex_dmem_uop_WIRE_52_history; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_53; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_bht_value = _ex_dmem_uop_WIRE_52_value; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_138 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_139 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_140 = _ex_dmem_uop_T_138 | _ex_dmem_uop_T_139; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_53 = _ex_dmem_uop_T_140; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_52_value = _ex_dmem_uop_WIRE_53; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_T_141 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_T_142 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _ex_dmem_uop_T_143 = _ex_dmem_uop_T_141 | _ex_dmem_uop_T_142; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_54 = _ex_dmem_uop_T_143; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_52_history = _ex_dmem_uop_WIRE_54; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_T_144 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_T_145 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _ex_dmem_uop_T_146 = _ex_dmem_uop_T_144 | _ex_dmem_uop_T_145; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_55 = _ex_dmem_uop_T_146; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_entry = _ex_dmem_uop_WIRE_55; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_T_147 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_T_148 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _ex_dmem_uop_T_149 = _ex_dmem_uop_T_147 | _ex_dmem_uop_T_148; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_56 = _ex_dmem_uop_T_149; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_target = _ex_dmem_uop_WIRE_56; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_150 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_151 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_152 = _ex_dmem_uop_T_150 | _ex_dmem_uop_T_151; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_57 = _ex_dmem_uop_T_152; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_bridx = _ex_dmem_uop_WIRE_57; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_T_153 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_T_154 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _ex_dmem_uop_T_155 = _ex_dmem_uop_T_153 | _ex_dmem_uop_T_154; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_58 = _ex_dmem_uop_T_155; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_mask = _ex_dmem_uop_WIRE_58; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_156 = ex_dmem_oh_0 & ex_uops_reg_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_157 = ex_dmem_oh_1 & ex_uops_reg_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_158 = _ex_dmem_uop_T_156 | _ex_dmem_uop_T_157; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_59 = _ex_dmem_uop_T_158; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_taken = _ex_dmem_uop_WIRE_59; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_159 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_160 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_161 = _ex_dmem_uop_T_159 | _ex_dmem_uop_T_160; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_60 = _ex_dmem_uop_T_161; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_51_cfiType = _ex_dmem_uop_WIRE_60; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_162 = ex_dmem_oh_0 & ex_uops_reg_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_163 = ex_dmem_oh_1 & ex_uops_reg_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_164 = _ex_dmem_uop_T_162 | _ex_dmem_uop_T_163; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_61 = _ex_dmem_uop_T_164; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_50_valid = _ex_dmem_uop_WIRE_61; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_168 = ex_dmem_oh_0 & ex_uops_reg_0_bits_rvc; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_169 = ex_dmem_oh_1 & ex_uops_reg_1_bits_rvc; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_170 = _ex_dmem_uop_T_168 | _ex_dmem_uop_T_169; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_63 = _ex_dmem_uop_T_170; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_rvc = _ex_dmem_uop_WIRE_63; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_81; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_ldst = _ex_dmem_uop_WIRE_64_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_80; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_wen = _ex_dmem_uop_WIRE_64_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_79; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_ren1 = _ex_dmem_uop_WIRE_64_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_78; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_ren2 = _ex_dmem_uop_WIRE_64_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_77; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_ren3 = _ex_dmem_uop_WIRE_64_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_76; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_swap12 = _ex_dmem_uop_WIRE_64_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_75; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_swap23 = _ex_dmem_uop_WIRE_64_swap23; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_74; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_typeTagIn = _ex_dmem_uop_WIRE_64_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_73; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_typeTagOut = _ex_dmem_uop_WIRE_64_typeTagOut; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_72; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_fromint = _ex_dmem_uop_WIRE_64_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_71; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_toint = _ex_dmem_uop_WIRE_64_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_70; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_fastpipe = _ex_dmem_uop_WIRE_64_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_69; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_fma = _ex_dmem_uop_WIRE_64_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_68; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_div = _ex_dmem_uop_WIRE_64_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_67; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_sqrt = _ex_dmem_uop_WIRE_64_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_66; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_wflags = _ex_dmem_uop_WIRE_64_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_65; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_fp_ctrl_vec = _ex_dmem_uop_WIRE_64_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_171 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_172 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_173 = _ex_dmem_uop_T_171 | _ex_dmem_uop_T_172; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_65 = _ex_dmem_uop_T_173; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_vec = _ex_dmem_uop_WIRE_65; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_174 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_175 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_176 = _ex_dmem_uop_T_174 | _ex_dmem_uop_T_175; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_66 = _ex_dmem_uop_T_176; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_wflags = _ex_dmem_uop_WIRE_66; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_177 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_178 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_179 = _ex_dmem_uop_T_177 | _ex_dmem_uop_T_178; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_67 = _ex_dmem_uop_T_179; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_sqrt = _ex_dmem_uop_WIRE_67; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_180 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_181 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_182 = _ex_dmem_uop_T_180 | _ex_dmem_uop_T_181; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_68 = _ex_dmem_uop_T_182; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_div = _ex_dmem_uop_WIRE_68; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_183 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_184 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_185 = _ex_dmem_uop_T_183 | _ex_dmem_uop_T_184; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_69 = _ex_dmem_uop_T_185; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_fma = _ex_dmem_uop_WIRE_69; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_186 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_187 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_188 = _ex_dmem_uop_T_186 | _ex_dmem_uop_T_187; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_70 = _ex_dmem_uop_T_188; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_fastpipe = _ex_dmem_uop_WIRE_70; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_189 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_190 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_191 = _ex_dmem_uop_T_189 | _ex_dmem_uop_T_190; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_71 = _ex_dmem_uop_T_191; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_toint = _ex_dmem_uop_WIRE_71; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_192 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_193 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_194 = _ex_dmem_uop_T_192 | _ex_dmem_uop_T_193; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_72 = _ex_dmem_uop_T_194; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_fromint = _ex_dmem_uop_WIRE_72; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_195 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_196 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_197 = _ex_dmem_uop_T_195 | _ex_dmem_uop_T_196; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_73 = _ex_dmem_uop_T_197; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_typeTagOut = _ex_dmem_uop_WIRE_73; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_198 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_199 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_200 = _ex_dmem_uop_T_198 | _ex_dmem_uop_T_199; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_74 = _ex_dmem_uop_T_200; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_typeTagIn = _ex_dmem_uop_WIRE_74; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_201 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_202 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_203 = _ex_dmem_uop_T_201 | _ex_dmem_uop_T_202; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_75 = _ex_dmem_uop_T_203; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_swap23 = _ex_dmem_uop_WIRE_75; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_204 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_205 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_206 = _ex_dmem_uop_T_204 | _ex_dmem_uop_T_205; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_76 = _ex_dmem_uop_T_206; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_swap12 = _ex_dmem_uop_WIRE_76; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_207 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_208 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_209 = _ex_dmem_uop_T_207 | _ex_dmem_uop_T_208; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_77 = _ex_dmem_uop_T_209; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_ren3 = _ex_dmem_uop_WIRE_77; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_210 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_211 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_212 = _ex_dmem_uop_T_210 | _ex_dmem_uop_T_211; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_78 = _ex_dmem_uop_T_212; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_ren2 = _ex_dmem_uop_WIRE_78; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_213 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_214 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_215 = _ex_dmem_uop_T_213 | _ex_dmem_uop_T_214; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_79 = _ex_dmem_uop_T_215; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_ren1 = _ex_dmem_uop_WIRE_79; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_216 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_217 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_218 = _ex_dmem_uop_T_216 | _ex_dmem_uop_T_217; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_80 = _ex_dmem_uop_T_218; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_wen = _ex_dmem_uop_WIRE_80; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_219 = ex_dmem_oh_0 & ex_uops_reg_0_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_220 = ex_dmem_oh_1 & ex_uops_reg_1_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_221 = _ex_dmem_uop_T_219 | _ex_dmem_uop_T_220; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_81 = _ex_dmem_uop_T_221; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_64_ldst = _ex_dmem_uop_WIRE_81; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_110; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_legal = _ex_dmem_uop_WIRE_82_legal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_109; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_fp = _ex_dmem_uop_WIRE_82_fp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_108; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rocc = _ex_dmem_uop_WIRE_82_rocc; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_107; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_branch = _ex_dmem_uop_WIRE_82_branch; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_106; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_jal = _ex_dmem_uop_WIRE_82_jal; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_105; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_jalr = _ex_dmem_uop_WIRE_82_jalr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_104; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rxs2 = _ex_dmem_uop_WIRE_82_rxs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_103; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rxs1 = _ex_dmem_uop_WIRE_82_rxs1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_102; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_sel_alu2 = _ex_dmem_uop_WIRE_82_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_WIRE_101; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_sel_alu1 = _ex_dmem_uop_WIRE_82_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_100; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_sel_imm = _ex_dmem_uop_WIRE_82_sel_imm; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_99; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_alu_dw = _ex_dmem_uop_WIRE_82_alu_dw; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_98; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_alu_fn = _ex_dmem_uop_WIRE_82_alu_fn; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_97; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_mem = _ex_dmem_uop_WIRE_82_mem; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_WIRE_96; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_mem_cmd = _ex_dmem_uop_WIRE_82_mem_cmd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_95; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rfs1 = _ex_dmem_uop_WIRE_82_rfs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_94; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rfs2 = _ex_dmem_uop_WIRE_82_rfs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_93; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_rfs3 = _ex_dmem_uop_WIRE_82_rfs3; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_92; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_wfd = _ex_dmem_uop_WIRE_82_wfd; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_91; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_mul = _ex_dmem_uop_WIRE_82_mul; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_90; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_div = _ex_dmem_uop_WIRE_82_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_89; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_wxd = _ex_dmem_uop_WIRE_82_wxd; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_WIRE_88; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_csr = _ex_dmem_uop_WIRE_82_csr; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_87; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_fence_i = _ex_dmem_uop_WIRE_82_fence_i; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_86; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_fence = _ex_dmem_uop_WIRE_82_fence; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_85; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_amo = _ex_dmem_uop_WIRE_82_amo; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_84; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_dp = _ex_dmem_uop_WIRE_82_dp; // @[Mux.scala:30:73] wire _ex_dmem_uop_WIRE_83; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_ctrl_vec = _ex_dmem_uop_WIRE_82_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_222 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_223 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_vec; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_224 = _ex_dmem_uop_T_222 | _ex_dmem_uop_T_223; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_83 = _ex_dmem_uop_T_224; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_vec = _ex_dmem_uop_WIRE_83; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_225 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_dp; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_226 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_dp; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_227 = _ex_dmem_uop_T_225 | _ex_dmem_uop_T_226; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_84 = _ex_dmem_uop_T_227; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_dp = _ex_dmem_uop_WIRE_84; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_228 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_amo; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_229 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_amo; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_230 = _ex_dmem_uop_T_228 | _ex_dmem_uop_T_229; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_85 = _ex_dmem_uop_T_230; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_amo = _ex_dmem_uop_WIRE_85; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_231 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_fence; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_232 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_fence; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_233 = _ex_dmem_uop_T_231 | _ex_dmem_uop_T_232; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_86 = _ex_dmem_uop_T_233; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_fence = _ex_dmem_uop_WIRE_86; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_234 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_235 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_236 = _ex_dmem_uop_T_234 | _ex_dmem_uop_T_235; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_87 = _ex_dmem_uop_T_236; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_fence_i = _ex_dmem_uop_WIRE_87; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_237 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_238 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_239 = _ex_dmem_uop_T_237 | _ex_dmem_uop_T_238; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_88 = _ex_dmem_uop_T_239; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_csr = _ex_dmem_uop_WIRE_88; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_240 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_241 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_242 = _ex_dmem_uop_T_240 | _ex_dmem_uop_T_241; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_89 = _ex_dmem_uop_T_242; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_wxd = _ex_dmem_uop_WIRE_89; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_243 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_244 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_div; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_245 = _ex_dmem_uop_T_243 | _ex_dmem_uop_T_244; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_90 = _ex_dmem_uop_T_245; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_div = _ex_dmem_uop_WIRE_90; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_246 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_mul; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_247 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_mul; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_248 = _ex_dmem_uop_T_246 | _ex_dmem_uop_T_247; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_91 = _ex_dmem_uop_T_248; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_mul = _ex_dmem_uop_WIRE_91; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_249 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_250 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_251 = _ex_dmem_uop_T_249 | _ex_dmem_uop_T_250; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_92 = _ex_dmem_uop_T_251; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_wfd = _ex_dmem_uop_WIRE_92; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_252 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_253 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_254 = _ex_dmem_uop_T_252 | _ex_dmem_uop_T_253; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_93 = _ex_dmem_uop_T_254; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rfs3 = _ex_dmem_uop_WIRE_93; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_255 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_256 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_257 = _ex_dmem_uop_T_255 | _ex_dmem_uop_T_256; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_94 = _ex_dmem_uop_T_257; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rfs2 = _ex_dmem_uop_WIRE_94; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_258 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_259 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_260 = _ex_dmem_uop_T_258 | _ex_dmem_uop_T_259; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_95 = _ex_dmem_uop_T_260; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rfs1 = _ex_dmem_uop_WIRE_95; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_261 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_262 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_263 = _ex_dmem_uop_T_261 | _ex_dmem_uop_T_262; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_96 = _ex_dmem_uop_T_263; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_mem_cmd = _ex_dmem_uop_WIRE_96; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_264 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_mem; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_265 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_mem; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_266 = _ex_dmem_uop_T_264 | _ex_dmem_uop_T_265; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_97 = _ex_dmem_uop_T_266; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_mem = _ex_dmem_uop_WIRE_97; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_267 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_268 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _ex_dmem_uop_T_269 = _ex_dmem_uop_T_267 | _ex_dmem_uop_T_268; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_98 = _ex_dmem_uop_T_269; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_alu_fn = _ex_dmem_uop_WIRE_98; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_270 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_271 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_272 = _ex_dmem_uop_T_270 | _ex_dmem_uop_T_271; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_99 = _ex_dmem_uop_T_272; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_alu_dw = _ex_dmem_uop_WIRE_99; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_273 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_274 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_275 = _ex_dmem_uop_T_273 | _ex_dmem_uop_T_274; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_100 = _ex_dmem_uop_T_275; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_sel_imm = _ex_dmem_uop_WIRE_100; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_276 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_277 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _ex_dmem_uop_T_278 = _ex_dmem_uop_T_276 | _ex_dmem_uop_T_277; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_101 = _ex_dmem_uop_T_278; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_sel_alu1 = _ex_dmem_uop_WIRE_101; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_279 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_280 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _ex_dmem_uop_T_281 = _ex_dmem_uop_T_279 | _ex_dmem_uop_T_280; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_102 = _ex_dmem_uop_T_281; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_sel_alu2 = _ex_dmem_uop_WIRE_102; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_282 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_283 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_284 = _ex_dmem_uop_T_282 | _ex_dmem_uop_T_283; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_103 = _ex_dmem_uop_T_284; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rxs1 = _ex_dmem_uop_WIRE_103; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_285 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_286 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_287 = _ex_dmem_uop_T_285 | _ex_dmem_uop_T_286; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_104 = _ex_dmem_uop_T_287; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rxs2 = _ex_dmem_uop_WIRE_104; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_288 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_289 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_290 = _ex_dmem_uop_T_288 | _ex_dmem_uop_T_289; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_105 = _ex_dmem_uop_T_290; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_jalr = _ex_dmem_uop_WIRE_105; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_291 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_jal; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_292 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_jal; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_293 = _ex_dmem_uop_T_291 | _ex_dmem_uop_T_292; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_106 = _ex_dmem_uop_T_293; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_jal = _ex_dmem_uop_WIRE_106; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_294 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_branch; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_295 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_branch; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_296 = _ex_dmem_uop_T_294 | _ex_dmem_uop_T_295; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_107 = _ex_dmem_uop_T_296; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_branch = _ex_dmem_uop_WIRE_107; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_297 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_298 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_299 = _ex_dmem_uop_T_297 | _ex_dmem_uop_T_298; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_108 = _ex_dmem_uop_T_299; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_rocc = _ex_dmem_uop_WIRE_108; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_300 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_fp; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_301 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_fp; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_302 = _ex_dmem_uop_T_300 | _ex_dmem_uop_T_301; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_109 = _ex_dmem_uop_T_302; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_fp = _ex_dmem_uop_WIRE_109; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_303 = ex_dmem_oh_0 & ex_uops_reg_0_bits_ctrl_legal; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_304 = ex_dmem_oh_1 & ex_uops_reg_1_bits_ctrl_legal; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_305 = _ex_dmem_uop_T_303 | _ex_dmem_uop_T_304; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_110 = _ex_dmem_uop_T_305; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_82_legal = _ex_dmem_uop_WIRE_110; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_306 = ex_dmem_oh_0 & ex_uops_reg_0_bits_edge_inst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_307 = ex_dmem_oh_1 & ex_uops_reg_1_bits_edge_inst; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_308 = _ex_dmem_uop_T_306 | _ex_dmem_uop_T_307; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_111 = _ex_dmem_uop_T_308; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_edge_inst = _ex_dmem_uop_WIRE_111; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_309 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_310 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_uop_T_311 = _ex_dmem_uop_T_309 | _ex_dmem_uop_T_310; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_112 = _ex_dmem_uop_T_311; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_pc = _ex_dmem_uop_WIRE_112; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_312 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_313 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_314 = _ex_dmem_uop_T_312 | _ex_dmem_uop_T_313; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_113 = _ex_dmem_uop_T_314; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_raw_inst = _ex_dmem_uop_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_315 = ex_dmem_oh_0 ? ex_uops_reg_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_316 = ex_dmem_oh_1 ? ex_uops_reg_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _ex_dmem_uop_T_317 = _ex_dmem_uop_T_315 | _ex_dmem_uop_T_316; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_114 = _ex_dmem_uop_T_317; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_inst = _ex_dmem_uop_WIRE_114; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_318 = ex_dmem_oh_0 & ex_uops_reg_0_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_319 = ex_dmem_oh_1 & ex_uops_reg_1_valid; // @[Mux.scala:30:73] wire _ex_dmem_uop_T_320 = _ex_dmem_uop_T_318 | _ex_dmem_uop_T_319; // @[Mux.scala:30:73] assign _ex_dmem_uop_WIRE_115 = _ex_dmem_uop_T_320; // @[Mux.scala:30:73] assign ex_dmem_uop_valid = _ex_dmem_uop_WIRE_115; // @[Mux.scala:30:73] wire [39:0] _ex_dmem_addrs_0_T_1; // @[Core.scala:67:8] wire [39:0] _ex_dmem_addrs_1_T_1; // @[Core.scala:67:8] wire [39:0] ex_dmem_addrs_0; // @[Core.scala:545:27] wire [39:0] ex_dmem_addrs_1; // @[Core.scala:545:27] wire _io_dmem_req_valid_T = ex_dmem_oh_0 | ex_dmem_oh_1; // @[Core.scala:543:50, :546:43] wire _io_dmem_req_valid_T_1 = ~ex_dmem_uop_bits_xcpt; // @[Mux.scala:30:73] assign _io_dmem_req_valid_T_2 = _io_dmem_req_valid_T & _io_dmem_req_valid_T_1; // @[Core.scala:546:{43,48,51}] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_2; // @[Core.scala:25:7, :546:48] wire [4:0] _io_dmem_req_bits_tag_T = ex_dmem_uop_bits_inst[11:7]; // @[Mux.scala:30:73] wire [5:0] _io_dmem_req_bits_tag_T_1 = {_io_dmem_req_bits_tag_T, ex_dmem_uop_bits_ctrl_fp}; // @[Mux.scala:30:73] assign io_dmem_req_bits_tag_0 = {1'h0, _io_dmem_req_bits_tag_T_1}; // @[Core.scala:25:7, :548:{24,30}] wire _io_dmem_req_bits_signed_T = ex_dmem_uop_bits_inst[14]; // @[Mux.scala:30:73] assign _io_dmem_req_bits_signed_T_1 = ~_io_dmem_req_bits_signed_T; // @[Core.scala:551:{30,52}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_1; // @[Core.scala:25:7, :551:30] wire [39:0] _io_dmem_req_bits_addr_T = ex_dmem_oh_0 ? ex_dmem_addrs_0 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_dmem_req_bits_addr_T_1 = ex_dmem_oh_1 ? ex_dmem_addrs_1 : 40'h0; // @[Mux.scala:30:73] wire [39:0] _io_dmem_req_bits_addr_T_2 = _io_dmem_req_bits_addr_T | _io_dmem_req_bits_addr_T_1; // @[Mux.scala:30:73] assign _io_dmem_req_bits_addr_WIRE = _io_dmem_req_bits_addr_T_2; // @[Mux.scala:30:73] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_WIRE; // @[Mux.scala:30:73] wire _GEN_92 = ex_stall | flush_rrd_ex; // @[Core.scala:107:26, :110:30, :572:35] wire _kill_T; // @[Core.scala:572:35] assign _kill_T = _GEN_92; // @[Core.scala:572:35] wire _kill_T_2; // @[Core.scala:572:35] assign _kill_T_2 = _GEN_92; // @[Core.scala:572:35] wire _T_128 = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _kill_T_1; // @[Decoupled.scala:51:35] assign _kill_T_1 = _T_128; // @[Decoupled.scala:51:35] wire _kill_T_3; // @[Decoupled.scala:51:35] assign _kill_T_3 = _T_128; // @[Decoupled.scala:51:35] reg kill_r; // @[Core.scala:572:25] wire kill = kill_r | kill_mem; // @[Core.scala:111:26, :572:{25,70}] reg REG; // @[Core.scala:573:18] wire _T_127 = REG & kill; // @[Core.scala:572:70, :573:{18,54}] reg kill_r_1; // @[Core.scala:572:25] wire kill_1 = kill_r_1 | kill_mem; // @[Core.scala:111:26, :572:{25,70}] reg REG_1; // @[Core.scala:573:18] wire _T_130 = REG_1 & kill_1; // @[Core.scala:572:70, :573:{18,54}] wire _GEN_93 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h5; // @[Core.scala:71:24] wire _imm_sign_T; // @[RocketCore.scala:1341:24] assign _imm_sign_T = _GEN_93; // @[RocketCore.scala:1341:24] wire _imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _imm_b11_T_1 = _GEN_93; // @[RocketCore.scala:1341:24, :1344:40] wire _imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _imm_b10_5_T_1 = _GEN_93; // @[RocketCore.scala:1341:24, :1347:42] wire _imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _imm_b4_1_T_5 = _GEN_93; // @[RocketCore.scala:1341:24, :1350:24] wire _imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _imm_b0_T_4 = _GEN_93; // @[RocketCore.scala:1341:24, :1353:22] wire _imm_sign_T_1 = ex_uops_reg_0_bits_inst[31]; // @[Core.scala:71:24] wire _imm_sign_T_2 = _imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire imm_sign = ~_imm_sign_T & _imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire imm_hi_hi_hi = imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_94 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h2; // @[Core.scala:71:24] wire _imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _imm_b30_20_T = _GEN_94; // @[RocketCore.scala:1342:26] wire _imm_b11_T; // @[RocketCore.scala:1344:23] assign _imm_b11_T = _GEN_94; // @[RocketCore.scala:1342:26, :1344:23] wire _imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _imm_b10_5_T = _GEN_94; // @[RocketCore.scala:1342:26, :1347:25] wire _imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _imm_b4_1_T = _GEN_94; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _imm_b30_20_T_1 = ex_uops_reg_0_bits_inst[30:20]; // @[Core.scala:71:24] wire [10:0] _imm_b30_20_T_2 = _imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] imm_b30_20 = _imm_b30_20_T ? _imm_b30_20_T_2 : {11{imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] imm_hi_hi_lo = imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _imm_b19_12_T = ex_uops_reg_0_bits_ctrl_sel_imm != 3'h2; // @[Core.scala:71:24] wire _imm_b19_12_T_1 = ex_uops_reg_0_bits_ctrl_sel_imm != 3'h3; // @[Core.scala:71:24] wire _imm_b19_12_T_2 = _imm_b19_12_T & _imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _imm_b19_12_T_3 = ex_uops_reg_0_bits_inst[19:12]; // @[Core.scala:71:24] wire [7:0] _imm_b19_12_T_4 = _imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] imm_b19_12 = _imm_b19_12_T_2 ? {8{imm_sign}} : _imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] imm_hi_lo_hi = imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _imm_b11_T_2 = _imm_b11_T | _imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _imm_b11_T_3 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h3; // @[Core.scala:71:24] wire _imm_b11_T_4 = ex_uops_reg_0_bits_inst[20]; // @[Core.scala:71:24] wire _imm_b0_T_3 = ex_uops_reg_0_bits_inst[20]; // @[Core.scala:71:24] wire _imm_b11_T_5 = _imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_95 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h1; // @[Core.scala:71:24] wire _imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _imm_b11_T_6 = _GEN_95; // @[RocketCore.scala:1346:23] wire _imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _imm_b4_1_T_2 = _GEN_95; // @[RocketCore.scala:1346:23, :1349:41] wire _imm_b11_T_7 = ex_uops_reg_0_bits_inst[7]; // @[Core.scala:71:24] wire _imm_b0_T_1 = ex_uops_reg_0_bits_inst[7]; // @[Core.scala:71:24] wire _imm_b11_T_8 = _imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _imm_b11_T_9 = _imm_b11_T_6 ? _imm_b11_T_8 : imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _imm_b11_T_10 = _imm_b11_T_3 ? _imm_b11_T_5 : _imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire imm_b11 = ~_imm_b11_T_2 & _imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire imm_hi_lo_lo = imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _imm_b10_5_T_2 = _imm_b10_5_T | _imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _imm_b10_5_T_3 = ex_uops_reg_0_bits_inst[30:25]; // @[Core.scala:71:24] wire [5:0] imm_b10_5 = _imm_b10_5_T_2 ? 6'h0 : _imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_96 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h0; // @[Core.scala:71:24] wire _imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _imm_b4_1_T_1 = _GEN_96; // @[RocketCore.scala:1349:24] wire _imm_b0_T; // @[RocketCore.scala:1351:22] assign _imm_b0_T = _GEN_96; // @[RocketCore.scala:1349:24, :1351:22] wire _imm_b4_1_T_3 = _imm_b4_1_T_1 | _imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _imm_b4_1_T_4 = ex_uops_reg_0_bits_inst[11:8]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_6 = ex_uops_reg_0_bits_inst[19:16]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_7 = ex_uops_reg_0_bits_inst[24:21]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_8 = _imm_b4_1_T_5 ? _imm_b4_1_T_6 : _imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _imm_b4_1_T_9 = _imm_b4_1_T_3 ? _imm_b4_1_T_4 : _imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] imm_b4_1 = _imm_b4_1_T ? 4'h0 : _imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _imm_b0_T_2 = ex_uops_reg_0_bits_ctrl_sel_imm == 3'h4; // @[Core.scala:71:24] wire _imm_b0_T_5 = ex_uops_reg_0_bits_inst[15]; // @[Core.scala:71:24] wire _imm_b0_T_6 = _imm_b0_T_4 & _imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _imm_b0_T_7 = _imm_b0_T_2 ? _imm_b0_T_3 : _imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire imm_b0 = _imm_b0_T ? _imm_b0_T_1 : _imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] imm_lo_hi = {imm_b10_5, imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] imm_lo = {imm_lo_hi, imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] imm_hi_lo = {imm_hi_lo_hi, imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] imm_hi_hi = {imm_hi_hi_hi, imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] imm_hi = {imm_hi_hi, imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _imm_T = {imm_hi, imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] imm = _imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_op1_T_2 = ex_uops_reg_0_bits_inst[3]; // @[Core.scala:71:24, :588:33] wire [31:0] _ex_op1_T_3 = ex_uops_reg_0_bits_rs1_data[31:0]; // @[Core.scala:71:24, :588:50] wire [63:0] _ex_op1_T_4 = _ex_op1_T_2 ? {32'h0, _ex_op1_T_3} : ex_uops_reg_0_bits_rs1_data; // @[Core.scala:71:24, :588:{24,33,50}] wire [1:0] _ex_op1_T_5 = ex_uops_reg_0_bits_inst[14:13]; // @[Core.scala:71:24, :588:83] wire [66:0] _ex_op1_T_6 = {3'h0, _ex_op1_T_4} << _ex_op1_T_5; // @[Core.scala:588:{24,72,83}] wire [66:0] _ex_op1_T_7 = _ex_op1_T_6; // @[Core.scala:588:{72,92}] wire _ex_op1_T_8 = sel_alu1 == 2'h1; // @[Core.scala:583:28, :585:42] wire [63:0] _ex_op1_T_9 = _ex_op1_T_8 ? _ex_op1_T : 64'h0; // @[Core.scala:585:42, :586:30] wire _ex_op1_T_10 = sel_alu1 == 2'h2; // @[Core.scala:583:28, :585:42] wire [63:0] _ex_op1_T_11 = _ex_op1_T_10 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_9; // @[Core.scala:585:42, :587:23] wire _ex_op1_T_12 = &sel_alu1; // @[Core.scala:583:28, :585:42] wire [66:0] ex_op1 = _ex_op1_T_12 ? _ex_op1_T_7 : {{3{_ex_op1_T_11[63]}}, _ex_op1_T_11}; // @[Core.scala:585:42, :588:92] wire [66:0] _alu_io_in1_T = ex_op1; // @[Core.scala:585:42, :602:26] wire _ex_op2_oh_T = ex_uops_reg_0_bits_ctrl_sel_alu2[0]; // @[Core.scala:71:24, :590:47] wire [11:0] _ex_op2_oh_T_1 = ex_uops_reg_0_bits_inst[31:20]; // @[Core.scala:71:24, :590:62] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_uops_reg_0_bits_rs2_data; // @[Core.scala:71:24, :590:{33,47,62}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[Core.scala:590:{33,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_uops_reg_0_bits_rvc ? 4'h2 : 4'h4; // @[Core.scala:71:24, :594:21] wire _ex_op2_T_2 = sel_alu2 == 3'h2; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[Core.scala:591:42, :592:30] wire _ex_op2_T_4 = sel_alu2 == 3'h3; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{imm[31]}}, imm} : _ex_op2_T_3; // @[Core.scala:591:42] wire _ex_op2_T_6 = sel_alu2 == 3'h1; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[Core.scala:591:42, :594:21] wire _ex_op2_T_8 = sel_alu2 == 3'h4; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[Core.scala:590:112, :591:42] wire _ex_op2_T_10 = sel_alu2 == 3'h5; // @[Core.scala:584:28, :591:42] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[Core.scala:590:112, :591:42] wire [63:0] _alu_io_in2_T = ex_op2; // @[Core.scala:591:42, :601:26] wire _mem_uops_reg_0_bits_wdata_valid_T = ~ex_uops_reg_0_bits_ctrl_mem; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_1 = ex_uops_reg_0_bits_ctrl_wxd & _mem_uops_reg_0_bits_wdata_valid_T; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_2 = ~ex_uops_reg_0_bits_ctrl_div; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_3 = _mem_uops_reg_0_bits_wdata_valid_T_1 & _mem_uops_reg_0_bits_wdata_valid_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _mem_uops_reg_0_bits_wdata_valid_T_4 = ~ex_uops_reg_0_bits_ctrl_mul; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_5 = _mem_uops_reg_0_bits_wdata_valid_T_3 & _mem_uops_reg_0_bits_wdata_valid_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _mem_uops_reg_0_bits_wdata_valid_T_7 = &ex_uops_reg_0_bits_ctrl_csr; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_9 = _mem_uops_reg_0_bits_wdata_valid_T_6 | _mem_uops_reg_0_bits_wdata_valid_T_7; // @[package.scala:16:47, :81:59] wire _mem_uops_reg_0_bits_wdata_valid_T_10 = _mem_uops_reg_0_bits_wdata_valid_T_9 | _mem_uops_reg_0_bits_wdata_valid_T_8; // @[package.scala:16:47, :81:59] wire _mem_uops_reg_0_bits_wdata_valid_T_11 = ~_mem_uops_reg_0_bits_wdata_valid_T_10; // @[MicroOp.scala:77:69] wire _mem_uops_reg_0_bits_wdata_valid_T_12 = _mem_uops_reg_0_bits_wdata_valid_T_5 & _mem_uops_reg_0_bits_wdata_valid_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _mem_uops_reg_0_bits_wdata_valid_T_13 = ~ex_uops_reg_0_bits_ctrl_fp; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_14 = _mem_uops_reg_0_bits_wdata_valid_T_12 & _mem_uops_reg_0_bits_wdata_valid_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _mem_uops_reg_0_bits_wdata_valid_T_15 = ~ex_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_16 = _mem_uops_reg_0_bits_wdata_valid_T_14 & _mem_uops_reg_0_bits_wdata_valid_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _mem_uops_reg_0_bits_wdata_valid_T_17 = ~ex_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_18 = _mem_uops_reg_0_bits_wdata_valid_T_16 & _mem_uops_reg_0_bits_wdata_valid_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _mem_uops_reg_0_bits_wdata_valid_T_19 = ~ex_uops_reg_0_bits_ctrl_vec; // @[Core.scala:71:24] wire _mem_uops_reg_0_bits_wdata_valid_T_20 = _mem_uops_reg_0_bits_wdata_valid_T_18 & _mem_uops_reg_0_bits_wdata_valid_T_19; // @[MicroOp.scala:77:{103,117,120}] wire _mem_uops_reg_0_bits_wdata_valid_T_22 = _mem_uops_reg_0_bits_wdata_valid_T_20; // @[Core.scala:604:54] wire _mem_uops_reg_0_bits_wdata_valid_T_24 = _mem_uops_reg_0_bits_wdata_valid_T_22; // @[Core.scala:604:{54,74}] wire _mem_uops_reg_0_bits_wdata_bits_T = ~ex_uops_reg_0_bits_xcpt; // @[Core.scala:71:24, :499:85, :605:61] assign _ex_bypasses_0_valid_T = ex_uops_reg_0_valid & ex_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:71:24, :610:50] assign ex_bypasses_0_valid = _ex_bypasses_0_valid_T; // @[Core.scala:92:62, :610:50] assign ex_bypasses_0_dst = _ex_bypasses_0_dst_T; // @[Core.scala:92:62] wire _ex_bypasses_0_can_bypass_T = ~ex_uops_reg_0_bits_ctrl_mem; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_1 = ex_uops_reg_0_bits_ctrl_wxd & _ex_bypasses_0_can_bypass_T; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_2 = ~ex_uops_reg_0_bits_ctrl_div; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_3 = _ex_bypasses_0_can_bypass_T_1 & _ex_bypasses_0_can_bypass_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _ex_bypasses_0_can_bypass_T_4 = ~ex_uops_reg_0_bits_ctrl_mul; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_5 = _ex_bypasses_0_can_bypass_T_3 & _ex_bypasses_0_can_bypass_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _ex_bypasses_0_can_bypass_T_7 = &ex_uops_reg_0_bits_ctrl_csr; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_9 = _ex_bypasses_0_can_bypass_T_6 | _ex_bypasses_0_can_bypass_T_7; // @[package.scala:16:47, :81:59] wire _ex_bypasses_0_can_bypass_T_10 = _ex_bypasses_0_can_bypass_T_9 | _ex_bypasses_0_can_bypass_T_8; // @[package.scala:16:47, :81:59] wire _ex_bypasses_0_can_bypass_T_11 = ~_ex_bypasses_0_can_bypass_T_10; // @[MicroOp.scala:77:69] wire _ex_bypasses_0_can_bypass_T_12 = _ex_bypasses_0_can_bypass_T_5 & _ex_bypasses_0_can_bypass_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _ex_bypasses_0_can_bypass_T_13 = ~ex_uops_reg_0_bits_ctrl_fp; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_14 = _ex_bypasses_0_can_bypass_T_12 & _ex_bypasses_0_can_bypass_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _ex_bypasses_0_can_bypass_T_15 = ~ex_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_16 = _ex_bypasses_0_can_bypass_T_14 & _ex_bypasses_0_can_bypass_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _ex_bypasses_0_can_bypass_T_17 = ~ex_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_18 = _ex_bypasses_0_can_bypass_T_16 & _ex_bypasses_0_can_bypass_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _ex_bypasses_0_can_bypass_T_19 = ~ex_uops_reg_0_bits_ctrl_vec; // @[Core.scala:71:24] wire _ex_bypasses_0_can_bypass_T_20 = _ex_bypasses_0_can_bypass_T_18 & _ex_bypasses_0_can_bypass_T_19; // @[MicroOp.scala:77:{103,117,120}] wire _ex_bypasses_0_can_bypass_T_22 = _ex_bypasses_0_can_bypass_T_20; // @[Core.scala:612:47] wire _ex_bypasses_0_can_bypass_T_24 = _ex_bypasses_0_can_bypass_T_22; // @[Core.scala:612:{47,67}] assign _ex_bypasses_0_can_bypass_T_26 = _ex_bypasses_0_can_bypass_T_24; // @[Core.scala:612:{67,88}] assign ex_bypasses_0_can_bypass = _ex_bypasses_0_can_bypass_T_26; // @[Core.scala:92:62, :612:88] assign ex_bypasses_0_data = _ex_bypasses_0_data_T; // @[Core.scala:92:62, :613:31] wire [24:0] ex_dmem_addrs_0_a = _ex_dmem_addrs_0_a_T[63:39]; // @[Core.scala:65:{16,23}] wire _ex_dmem_addrs_0_msb_T = ex_dmem_addrs_0_a == 25'h0; // @[Core.scala:65:23, :66:21] wire _ex_dmem_addrs_0_msb_T_1 = &ex_dmem_addrs_0_a; // @[Core.scala:65:23, :66:34] wire _ex_dmem_addrs_0_msb_T_2 = _ex_dmem_addrs_0_msb_T | _ex_dmem_addrs_0_msb_T_1; // @[Core.scala:66:{21,29,34}] wire _ex_dmem_addrs_0_msb_T_3 = _alu_io_adder_out[39]; // @[Core.scala:66:46, :579:21] wire _ex_dmem_addrs_0_msb_T_4 = _alu_io_adder_out[38]; // @[Core.scala:66:62, :579:21] wire _ex_dmem_addrs_0_msb_T_5 = ~_ex_dmem_addrs_0_msb_T_4; // @[Core.scala:66:{59,62}] wire ex_dmem_addrs_0_msb = _ex_dmem_addrs_0_msb_T_2 ? _ex_dmem_addrs_0_msb_T_3 : _ex_dmem_addrs_0_msb_T_5; // @[Core.scala:66:{18,29,46,59}] wire [38:0] _ex_dmem_addrs_0_T = _alu_io_adder_out[38:0]; // @[Core.scala:67:16, :579:21] assign _ex_dmem_addrs_0_T_1 = {ex_dmem_addrs_0_msb, _ex_dmem_addrs_0_T}; // @[Core.scala:66:18, :67:{8,16}] assign ex_dmem_addrs_0 = _ex_dmem_addrs_0_T_1; // @[Core.scala:67:8, :545:27] wire [1:0] size = ex_uops_reg_0_bits_ctrl_rocc ? 2'h3 : ex_uops_reg_0_bits_mem_size; // @[Core.scala:71:24, :618:21] wire [1:0] mem_uops_reg_0_bits_rs2_data_size = size; // @[Core.scala:618:21] wire _mem_uops_reg_0_bits_rs2_data_T = mem_uops_reg_0_bits_rs2_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_uops_reg_0_bits_rs2_data_T_1 = ex_uops_reg_0_bits_rs2_data[7:0]; // @[Core.scala:71:24] wire [15:0] _mem_uops_reg_0_bits_rs2_data_T_2 = {2{_mem_uops_reg_0_bits_rs2_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_uops_reg_0_bits_rs2_data_T_3 = {2{_mem_uops_reg_0_bits_rs2_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_4 = {2{_mem_uops_reg_0_bits_rs2_data_T_3}}; // @[AMOALU.scala:29:32] wire _mem_uops_reg_0_bits_rs2_data_T_5 = mem_uops_reg_0_bits_rs2_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_uops_reg_0_bits_rs2_data_T_6 = ex_uops_reg_0_bits_rs2_data[15:0]; // @[Core.scala:71:24] wire [31:0] _mem_uops_reg_0_bits_rs2_data_T_7 = {2{_mem_uops_reg_0_bits_rs2_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_8 = {2{_mem_uops_reg_0_bits_rs2_data_T_7}}; // @[AMOALU.scala:29:32] wire _mem_uops_reg_0_bits_rs2_data_T_9 = mem_uops_reg_0_bits_rs2_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_uops_reg_0_bits_rs2_data_T_10 = ex_uops_reg_0_bits_rs2_data[31:0]; // @[Core.scala:71:24] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_11 = {2{_mem_uops_reg_0_bits_rs2_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_12 = _mem_uops_reg_0_bits_rs2_data_T_9 ? _mem_uops_reg_0_bits_rs2_data_T_11 : ex_uops_reg_0_bits_rs2_data; // @[Core.scala:71:24] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_13 = _mem_uops_reg_0_bits_rs2_data_T_5 ? _mem_uops_reg_0_bits_rs2_data_T_8 : _mem_uops_reg_0_bits_rs2_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_uops_reg_0_bits_rs2_data_T_14 = _mem_uops_reg_0_bits_rs2_data_T ? _mem_uops_reg_0_bits_rs2_data_T_4 : _mem_uops_reg_0_bits_rs2_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_97 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h5; // @[Core.scala:71:24] wire _imm_sign_T_3; // @[RocketCore.scala:1341:24] assign _imm_sign_T_3 = _GEN_97; // @[RocketCore.scala:1341:24] wire _imm_b11_T_12; // @[RocketCore.scala:1344:40] assign _imm_b11_T_12 = _GEN_97; // @[RocketCore.scala:1341:24, :1344:40] wire _imm_b10_5_T_5; // @[RocketCore.scala:1347:42] assign _imm_b10_5_T_5 = _GEN_97; // @[RocketCore.scala:1341:24, :1347:42] wire _imm_b4_1_T_15; // @[RocketCore.scala:1350:24] assign _imm_b4_1_T_15 = _GEN_97; // @[RocketCore.scala:1341:24, :1350:24] wire _imm_b0_T_12; // @[RocketCore.scala:1353:22] assign _imm_b0_T_12 = _GEN_97; // @[RocketCore.scala:1341:24, :1353:22] wire _imm_sign_T_4 = ex_uops_reg_1_bits_inst[31]; // @[Core.scala:71:24] wire _imm_sign_T_5 = _imm_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire imm_sign_1 = ~_imm_sign_T_3 & _imm_sign_T_5; // @[RocketCore.scala:1341:{19,24,49}] wire imm_hi_hi_hi_1 = imm_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_98 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h2; // @[Core.scala:71:24] wire _imm_b30_20_T_3; // @[RocketCore.scala:1342:26] assign _imm_b30_20_T_3 = _GEN_98; // @[RocketCore.scala:1342:26] wire _imm_b11_T_11; // @[RocketCore.scala:1344:23] assign _imm_b11_T_11 = _GEN_98; // @[RocketCore.scala:1342:26, :1344:23] wire _imm_b10_5_T_4; // @[RocketCore.scala:1347:25] assign _imm_b10_5_T_4 = _GEN_98; // @[RocketCore.scala:1342:26, :1347:25] wire _imm_b4_1_T_10; // @[RocketCore.scala:1348:24] assign _imm_b4_1_T_10 = _GEN_98; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _imm_b30_20_T_4 = ex_uops_reg_1_bits_inst[30:20]; // @[Core.scala:71:24] wire [10:0] _imm_b30_20_T_5 = _imm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] imm_b30_20_1 = _imm_b30_20_T_3 ? _imm_b30_20_T_5 : {11{imm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] imm_hi_hi_lo_1 = imm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire _imm_b19_12_T_5 = ex_uops_reg_1_bits_ctrl_sel_imm != 3'h2; // @[Core.scala:71:24] wire _imm_b19_12_T_6 = ex_uops_reg_1_bits_ctrl_sel_imm != 3'h3; // @[Core.scala:71:24] wire _imm_b19_12_T_7 = _imm_b19_12_T_5 & _imm_b19_12_T_6; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _imm_b19_12_T_8 = ex_uops_reg_1_bits_inst[19:12]; // @[Core.scala:71:24] wire [7:0] _imm_b19_12_T_9 = _imm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] imm_b19_12_1 = _imm_b19_12_T_7 ? {8{imm_sign_1}} : _imm_b19_12_T_9; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] imm_hi_lo_hi_1 = imm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _imm_b11_T_13 = _imm_b11_T_11 | _imm_b11_T_12; // @[RocketCore.scala:1344:{23,33,40}] wire _imm_b11_T_14 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h3; // @[Core.scala:71:24] wire _imm_b11_T_15 = ex_uops_reg_1_bits_inst[20]; // @[Core.scala:71:24] wire _imm_b0_T_11 = ex_uops_reg_1_bits_inst[20]; // @[Core.scala:71:24] wire _imm_b11_T_16 = _imm_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _GEN_99 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h1; // @[Core.scala:71:24] wire _imm_b11_T_17; // @[RocketCore.scala:1346:23] assign _imm_b11_T_17 = _GEN_99; // @[RocketCore.scala:1346:23] wire _imm_b4_1_T_12; // @[RocketCore.scala:1349:41] assign _imm_b4_1_T_12 = _GEN_99; // @[RocketCore.scala:1346:23, :1349:41] wire _imm_b11_T_18 = ex_uops_reg_1_bits_inst[7]; // @[Core.scala:71:24] wire _imm_b0_T_9 = ex_uops_reg_1_bits_inst[7]; // @[Core.scala:71:24] wire _imm_b11_T_19 = _imm_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire _imm_b11_T_20 = _imm_b11_T_17 ? _imm_b11_T_19 : imm_sign_1; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _imm_b11_T_21 = _imm_b11_T_14 ? _imm_b11_T_16 : _imm_b11_T_20; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire imm_b11_1 = ~_imm_b11_T_13 & _imm_b11_T_21; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire imm_hi_lo_lo_1 = imm_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire _imm_b10_5_T_6 = _imm_b10_5_T_4 | _imm_b10_5_T_5; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _imm_b10_5_T_7 = ex_uops_reg_1_bits_inst[30:25]; // @[Core.scala:71:24] wire [5:0] imm_b10_5_1 = _imm_b10_5_T_6 ? 6'h0 : _imm_b10_5_T_7; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_100 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h0; // @[Core.scala:71:24] wire _imm_b4_1_T_11; // @[RocketCore.scala:1349:24] assign _imm_b4_1_T_11 = _GEN_100; // @[RocketCore.scala:1349:24] wire _imm_b0_T_8; // @[RocketCore.scala:1351:22] assign _imm_b0_T_8 = _GEN_100; // @[RocketCore.scala:1349:24, :1351:22] wire _imm_b4_1_T_13 = _imm_b4_1_T_11 | _imm_b4_1_T_12; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _imm_b4_1_T_14 = ex_uops_reg_1_bits_inst[11:8]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_16 = ex_uops_reg_1_bits_inst[19:16]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_17 = ex_uops_reg_1_bits_inst[24:21]; // @[Core.scala:71:24] wire [3:0] _imm_b4_1_T_18 = _imm_b4_1_T_15 ? _imm_b4_1_T_16 : _imm_b4_1_T_17; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _imm_b4_1_T_19 = _imm_b4_1_T_13 ? _imm_b4_1_T_14 : _imm_b4_1_T_18; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] imm_b4_1_1 = _imm_b4_1_T_10 ? 4'h0 : _imm_b4_1_T_19; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _imm_b0_T_10 = ex_uops_reg_1_bits_ctrl_sel_imm == 3'h4; // @[Core.scala:71:24] wire _imm_b0_T_13 = ex_uops_reg_1_bits_inst[15]; // @[Core.scala:71:24] wire _imm_b0_T_14 = _imm_b0_T_12 & _imm_b0_T_13; // @[RocketCore.scala:1353:{17,22,37}] wire _imm_b0_T_15 = _imm_b0_T_10 ? _imm_b0_T_11 : _imm_b0_T_14; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire imm_b0_1 = _imm_b0_T_8 ? _imm_b0_T_9 : _imm_b0_T_15; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] imm_lo_hi_1 = {imm_b10_5_1, imm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] imm_lo_1 = {imm_lo_hi_1, imm_b0_1}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] imm_hi_lo_1 = {imm_hi_lo_hi_1, imm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] imm_hi_hi_1 = {imm_hi_hi_hi_1, imm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] imm_hi_1 = {imm_hi_hi_1, imm_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _imm_T_1 = {imm_hi_1, imm_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] imm_1 = _imm_T_1; // @[RocketCore.scala:1355:{8,53}] wire _ex_op1_T_15 = ex_uops_reg_1_bits_inst[3]; // @[Core.scala:71:24, :588:33] wire [31:0] _ex_op1_T_16 = ex_uops_reg_1_bits_rs1_data[31:0]; // @[Core.scala:71:24, :588:50] wire [63:0] _ex_op1_T_17 = _ex_op1_T_15 ? {32'h0, _ex_op1_T_16} : ex_uops_reg_1_bits_rs1_data; // @[Core.scala:71:24, :588:{24,33,50}] wire [1:0] _ex_op1_T_18 = ex_uops_reg_1_bits_inst[14:13]; // @[Core.scala:71:24, :588:83] wire [66:0] _ex_op1_T_19 = {3'h0, _ex_op1_T_17} << _ex_op1_T_18; // @[Core.scala:588:{24,72,83}] wire [66:0] _ex_op1_T_20 = _ex_op1_T_19; // @[Core.scala:588:{72,92}] wire _ex_op1_T_21 = sel_alu1_1 == 2'h1; // @[Core.scala:583:28, :585:42] wire [63:0] _ex_op1_T_22 = _ex_op1_T_21 ? _ex_op1_T_13 : 64'h0; // @[Core.scala:585:42, :586:30] wire _ex_op1_T_23 = sel_alu1_1 == 2'h2; // @[Core.scala:583:28, :585:42] wire [63:0] _ex_op1_T_24 = _ex_op1_T_23 ? {{24{_ex_op1_T_14[39]}}, _ex_op1_T_14} : _ex_op1_T_22; // @[Core.scala:585:42, :587:23] wire _ex_op1_T_25 = &sel_alu1_1; // @[Core.scala:583:28, :585:42] wire [66:0] ex_op1_1 = _ex_op1_T_25 ? _ex_op1_T_20 : {{3{_ex_op1_T_24[63]}}, _ex_op1_T_24}; // @[Core.scala:585:42, :588:92] wire [66:0] _alu_io_in1_T_1 = ex_op1_1; // @[Core.scala:585:42, :602:26] wire _ex_op2_oh_T_5 = ex_uops_reg_1_bits_ctrl_sel_alu2[0]; // @[Core.scala:71:24, :590:47] wire [11:0] _ex_op2_oh_T_6 = ex_uops_reg_1_bits_inst[31:20]; // @[Core.scala:71:24, :590:62] wire [63:0] _ex_op2_oh_T_7 = _ex_op2_oh_T_5 ? {52'h0, _ex_op2_oh_T_6} : ex_uops_reg_1_bits_rs2_data; // @[Core.scala:71:24, :590:{33,47,62}] wire [5:0] _ex_op2_oh_T_8 = _ex_op2_oh_T_7[5:0]; // @[Core.scala:590:{33,90}] wire [63:0] _ex_op2_oh_T_9 = 64'h1 << _ex_op2_oh_T_8; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh_1 = _ex_op2_oh_T_9; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_12 = ex_uops_reg_1_bits_rvc ? 4'h2 : 4'h4; // @[Core.scala:71:24, :594:21] wire _ex_op2_T_13 = sel_alu2_1 == 3'h2; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_14 = _ex_op2_T_13 ? _ex_op2_T_11 : 64'h0; // @[Core.scala:591:42, :592:30] wire _ex_op2_T_15 = sel_alu2_1 == 3'h3; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_16 = _ex_op2_T_15 ? {{32{imm_1[31]}}, imm_1} : _ex_op2_T_14; // @[Core.scala:591:42] wire _ex_op2_T_17 = sel_alu2_1 == 3'h1; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_18 = _ex_op2_T_17 ? {{60{_ex_op2_T_12[3]}}, _ex_op2_T_12} : _ex_op2_T_16; // @[Core.scala:591:42, :594:21] wire _ex_op2_T_19 = sel_alu2_1 == 3'h4; // @[Core.scala:584:28, :591:42] wire [63:0] _ex_op2_T_20 = _ex_op2_T_19 ? ex_op2_oh_1 : _ex_op2_T_18; // @[Core.scala:590:112, :591:42] wire _ex_op2_T_21 = sel_alu2_1 == 3'h5; // @[Core.scala:584:28, :591:42] wire [63:0] ex_op2_1 = _ex_op2_T_21 ? ex_op2_oh_1 : _ex_op2_T_20; // @[Core.scala:590:112, :591:42] wire [63:0] _alu_io_in2_T_1 = ex_op2_1; // @[Core.scala:591:42, :601:26] wire _mem_uops_reg_1_bits_wdata_valid_T = ~ex_uops_reg_1_bits_ctrl_mem; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_1 = ex_uops_reg_1_bits_ctrl_wxd & _mem_uops_reg_1_bits_wdata_valid_T; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_2 = ~ex_uops_reg_1_bits_ctrl_div; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_3 = _mem_uops_reg_1_bits_wdata_valid_T_1 & _mem_uops_reg_1_bits_wdata_valid_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _mem_uops_reg_1_bits_wdata_valid_T_4 = ~ex_uops_reg_1_bits_ctrl_mul; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_5 = _mem_uops_reg_1_bits_wdata_valid_T_3 & _mem_uops_reg_1_bits_wdata_valid_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _GEN_101 = ex_uops_reg_1_bits_ctrl_csr == 3'h6; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_6; // @[package.scala:16:47] assign _mem_uops_reg_1_bits_wdata_valid_T_6 = _GEN_101; // @[package.scala:16:47] wire _ex_bypasses_1_can_bypass_T_6; // @[package.scala:16:47] assign _ex_bypasses_1_can_bypass_T_6 = _GEN_101; // @[package.scala:16:47] wire _mem_uops_reg_1_bits_wdata_valid_T_7 = &ex_uops_reg_1_bits_ctrl_csr; // @[Core.scala:71:24] wire _GEN_102 = ex_uops_reg_1_bits_ctrl_csr == 3'h5; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_8; // @[package.scala:16:47] assign _mem_uops_reg_1_bits_wdata_valid_T_8 = _GEN_102; // @[package.scala:16:47] wire _ex_bypasses_1_can_bypass_T_8; // @[package.scala:16:47] assign _ex_bypasses_1_can_bypass_T_8 = _GEN_102; // @[package.scala:16:47] wire _mem_uops_reg_1_bits_wdata_valid_T_9 = _mem_uops_reg_1_bits_wdata_valid_T_6 | _mem_uops_reg_1_bits_wdata_valid_T_7; // @[package.scala:16:47, :81:59] wire _mem_uops_reg_1_bits_wdata_valid_T_10 = _mem_uops_reg_1_bits_wdata_valid_T_9 | _mem_uops_reg_1_bits_wdata_valid_T_8; // @[package.scala:16:47, :81:59] wire _mem_uops_reg_1_bits_wdata_valid_T_11 = ~_mem_uops_reg_1_bits_wdata_valid_T_10; // @[MicroOp.scala:77:69] wire _mem_uops_reg_1_bits_wdata_valid_T_12 = _mem_uops_reg_1_bits_wdata_valid_T_5 & _mem_uops_reg_1_bits_wdata_valid_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _mem_uops_reg_1_bits_wdata_valid_T_13 = ~ex_uops_reg_1_bits_ctrl_fp; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_14 = _mem_uops_reg_1_bits_wdata_valid_T_12 & _mem_uops_reg_1_bits_wdata_valid_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _mem_uops_reg_1_bits_wdata_valid_T_15 = ~ex_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_16 = _mem_uops_reg_1_bits_wdata_valid_T_14 & _mem_uops_reg_1_bits_wdata_valid_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _mem_uops_reg_1_bits_wdata_valid_T_17 = ~ex_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_18 = _mem_uops_reg_1_bits_wdata_valid_T_16 & _mem_uops_reg_1_bits_wdata_valid_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _mem_uops_reg_1_bits_wdata_valid_T_19 = ~ex_uops_reg_1_bits_ctrl_vec; // @[Core.scala:71:24] wire _mem_uops_reg_1_bits_wdata_valid_T_20 = _mem_uops_reg_1_bits_wdata_valid_T_18 & _mem_uops_reg_1_bits_wdata_valid_T_19; // @[MicroOp.scala:77:{103,117,120}] wire _mem_uops_reg_1_bits_wdata_valid_T_21 = ~ex_uops_reg_1_bits_uses_memalu; // @[Core.scala:71:24, :604:57] wire _mem_uops_reg_1_bits_wdata_valid_T_22 = _mem_uops_reg_1_bits_wdata_valid_T_20 & _mem_uops_reg_1_bits_wdata_valid_T_21; // @[Core.scala:604:{54,57}] wire _mem_uops_reg_1_bits_wdata_valid_T_23 = ~ex_uops_reg_1_bits_uses_latealu; // @[Core.scala:71:24, :604:77] wire _mem_uops_reg_1_bits_wdata_valid_T_24 = _mem_uops_reg_1_bits_wdata_valid_T_22 & _mem_uops_reg_1_bits_wdata_valid_T_23; // @[Core.scala:604:{54,74,77}] wire _mem_uops_reg_1_bits_wdata_bits_T = ~ex_uops_reg_1_bits_xcpt; // @[Core.scala:71:24, :605:61] assign _ex_bypasses_1_valid_T = ex_uops_reg_1_valid & ex_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:71:24, :610:50] assign ex_bypasses_1_valid = _ex_bypasses_1_valid_T; // @[Core.scala:92:62, :610:50] assign ex_bypasses_1_dst = _ex_bypasses_1_dst_T; // @[Core.scala:92:62] wire _ex_bypasses_1_can_bypass_T = ~ex_uops_reg_1_bits_ctrl_mem; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_1 = ex_uops_reg_1_bits_ctrl_wxd & _ex_bypasses_1_can_bypass_T; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_2 = ~ex_uops_reg_1_bits_ctrl_div; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_3 = _ex_bypasses_1_can_bypass_T_1 & _ex_bypasses_1_can_bypass_T_2; // @[MicroOp.scala:77:{27,40,43}] wire _ex_bypasses_1_can_bypass_T_4 = ~ex_uops_reg_1_bits_ctrl_mul; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_5 = _ex_bypasses_1_can_bypass_T_3 & _ex_bypasses_1_can_bypass_T_4; // @[MicroOp.scala:77:{40,53,56}] wire _ex_bypasses_1_can_bypass_T_7 = &ex_uops_reg_1_bits_ctrl_csr; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_9 = _ex_bypasses_1_can_bypass_T_6 | _ex_bypasses_1_can_bypass_T_7; // @[package.scala:16:47, :81:59] wire _ex_bypasses_1_can_bypass_T_10 = _ex_bypasses_1_can_bypass_T_9 | _ex_bypasses_1_can_bypass_T_8; // @[package.scala:16:47, :81:59] wire _ex_bypasses_1_can_bypass_T_11 = ~_ex_bypasses_1_can_bypass_T_10; // @[MicroOp.scala:77:69] wire _ex_bypasses_1_can_bypass_T_12 = _ex_bypasses_1_can_bypass_T_5 & _ex_bypasses_1_can_bypass_T_11; // @[MicroOp.scala:77:{53,66,69}] wire _ex_bypasses_1_can_bypass_T_13 = ~ex_uops_reg_1_bits_ctrl_fp; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_14 = _ex_bypasses_1_can_bypass_T_12 & _ex_bypasses_1_can_bypass_T_13; // @[MicroOp.scala:77:{66,77,80}] wire _ex_bypasses_1_can_bypass_T_15 = ~ex_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_16 = _ex_bypasses_1_can_bypass_T_14 & _ex_bypasses_1_can_bypass_T_15; // @[MicroOp.scala:77:{77,89,92}] wire _ex_bypasses_1_can_bypass_T_17 = ~ex_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_18 = _ex_bypasses_1_can_bypass_T_16 & _ex_bypasses_1_can_bypass_T_17; // @[MicroOp.scala:77:{89,103,106}] wire _ex_bypasses_1_can_bypass_T_19 = ~ex_uops_reg_1_bits_ctrl_vec; // @[Core.scala:71:24] wire _ex_bypasses_1_can_bypass_T_20 = _ex_bypasses_1_can_bypass_T_18 & _ex_bypasses_1_can_bypass_T_19; // @[MicroOp.scala:77:{103,117,120}] wire _ex_bypasses_1_can_bypass_T_21 = ~ex_uops_reg_1_bits_uses_memalu; // @[Core.scala:71:24, :604:57, :612:50] wire _ex_bypasses_1_can_bypass_T_22 = _ex_bypasses_1_can_bypass_T_20 & _ex_bypasses_1_can_bypass_T_21; // @[Core.scala:612:{47,50}] wire _ex_bypasses_1_can_bypass_T_23 = ~ex_uops_reg_1_bits_uses_latealu; // @[Core.scala:71:24, :604:77, :612:70] wire _ex_bypasses_1_can_bypass_T_24 = _ex_bypasses_1_can_bypass_T_22 & _ex_bypasses_1_can_bypass_T_23; // @[Core.scala:612:{47,67,70}] wire _ex_bypasses_1_can_bypass_T_25 = ~ex_uops_reg_1_bits_sfb_shadow; // @[Core.scala:71:24, :612:91] assign _ex_bypasses_1_can_bypass_T_26 = _ex_bypasses_1_can_bypass_T_24 & _ex_bypasses_1_can_bypass_T_25; // @[Core.scala:612:{67,88,91}] assign ex_bypasses_1_can_bypass = _ex_bypasses_1_can_bypass_T_26; // @[Core.scala:92:62, :612:88] assign ex_bypasses_1_data = _ex_bypasses_1_data_T; // @[Core.scala:92:62, :613:31] wire [24:0] ex_dmem_addrs_1_a = _ex_dmem_addrs_1_a_T[63:39]; // @[Core.scala:65:{16,23}] wire _ex_dmem_addrs_1_msb_T = ex_dmem_addrs_1_a == 25'h0; // @[Core.scala:65:23, :66:21] wire _ex_dmem_addrs_1_msb_T_1 = &ex_dmem_addrs_1_a; // @[Core.scala:65:23, :66:34] wire _ex_dmem_addrs_1_msb_T_2 = _ex_dmem_addrs_1_msb_T | _ex_dmem_addrs_1_msb_T_1; // @[Core.scala:66:{21,29,34}] wire _ex_dmem_addrs_1_msb_T_3 = _alu_1_io_adder_out[39]; // @[Core.scala:66:46, :579:21] wire _ex_dmem_addrs_1_msb_T_4 = _alu_1_io_adder_out[38]; // @[Core.scala:66:62, :579:21] wire _ex_dmem_addrs_1_msb_T_5 = ~_ex_dmem_addrs_1_msb_T_4; // @[Core.scala:66:{59,62}] wire ex_dmem_addrs_1_msb = _ex_dmem_addrs_1_msb_T_2 ? _ex_dmem_addrs_1_msb_T_3 : _ex_dmem_addrs_1_msb_T_5; // @[Core.scala:66:{18,29,46,59}] wire [38:0] _ex_dmem_addrs_1_T = _alu_1_io_adder_out[38:0]; // @[Core.scala:67:16, :579:21] assign _ex_dmem_addrs_1_T_1 = {ex_dmem_addrs_1_msb, _ex_dmem_addrs_1_T}; // @[Core.scala:66:18, :67:{8,16}] assign ex_dmem_addrs_1 = _ex_dmem_addrs_1_T_1; // @[Core.scala:67:8, :545:27] wire [1:0] size_1 = ex_uops_reg_1_bits_ctrl_rocc ? 2'h3 : ex_uops_reg_1_bits_mem_size; // @[Core.scala:71:24, :618:21] wire [1:0] mem_uops_reg_1_bits_rs2_data_size = size_1; // @[Core.scala:618:21] wire _mem_uops_reg_1_bits_rs2_data_T = mem_uops_reg_1_bits_rs2_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_uops_reg_1_bits_rs2_data_T_1 = ex_uops_reg_1_bits_rs2_data[7:0]; // @[Core.scala:71:24] wire [15:0] _mem_uops_reg_1_bits_rs2_data_T_2 = {2{_mem_uops_reg_1_bits_rs2_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_uops_reg_1_bits_rs2_data_T_3 = {2{_mem_uops_reg_1_bits_rs2_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_4 = {2{_mem_uops_reg_1_bits_rs2_data_T_3}}; // @[AMOALU.scala:29:32] wire _mem_uops_reg_1_bits_rs2_data_T_5 = mem_uops_reg_1_bits_rs2_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_uops_reg_1_bits_rs2_data_T_6 = ex_uops_reg_1_bits_rs2_data[15:0]; // @[Core.scala:71:24] wire [31:0] _mem_uops_reg_1_bits_rs2_data_T_7 = {2{_mem_uops_reg_1_bits_rs2_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_8 = {2{_mem_uops_reg_1_bits_rs2_data_T_7}}; // @[AMOALU.scala:29:32] wire _mem_uops_reg_1_bits_rs2_data_T_9 = mem_uops_reg_1_bits_rs2_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_uops_reg_1_bits_rs2_data_T_10 = ex_uops_reg_1_bits_rs2_data[31:0]; // @[Core.scala:71:24] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_11 = {2{_mem_uops_reg_1_bits_rs2_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_12 = _mem_uops_reg_1_bits_rs2_data_T_9 ? _mem_uops_reg_1_bits_rs2_data_T_11 : ex_uops_reg_1_bits_rs2_data; // @[Core.scala:71:24] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_13 = _mem_uops_reg_1_bits_rs2_data_T_5 ? _mem_uops_reg_1_bits_rs2_data_T_8 : _mem_uops_reg_1_bits_rs2_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_uops_reg_1_bits_rs2_data_T_14 = _mem_uops_reg_1_bits_rs2_data_T ? _mem_uops_reg_1_bits_rs2_data_T_4 : _mem_uops_reg_1_bits_rs2_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _ex_dmem_structural_hazard_T = ~io_dmem_req_ready_0; // @[Core.scala:25:7, :623:56] wire ex_dmem_structural_hazard = io_dmem_req_valid_0 & _ex_dmem_structural_hazard_T; // @[Core.scala:25:7, :623:{53,56}] wire _ex_stall_T_2 = _ex_stall_T_1 | ex_dmem_structural_hazard; // @[Core.scala:623:53, :626:19, :627:25] wire _ex_stall_T_3 = ex_fp_data_hazard_0 | ex_fp_data_hazard_1; // @[Core.scala:470:59, :629:31] wire _ex_stall_T_4 = _ex_stall_T_2 | _ex_stall_T_3; // @[Core.scala:627:25, :628:31, :629:31] assign _ex_stall_T_5 = _ex_stall_T & _ex_stall_T_4; // @[Core.scala:625:{48,53}, :628:31] assign ex_stall = _ex_stall_T_5; // @[Core.scala:107:26, :625:53] wire _mem_brjmp_oh_T = mem_uops_reg_0_bits_ctrl_branch | mem_uops_reg_0_bits_ctrl_jal; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_1 = _mem_brjmp_oh_T | mem_uops_reg_0_bits_ctrl_jalr; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_2 = mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h14; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_3 = mem_uops_reg_0_bits_ctrl_mem & _mem_brjmp_oh_T_2; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_4 = _mem_brjmp_oh_T_1 | _mem_brjmp_oh_T_3; // @[MicroOp.scala:72:25, :74:37, :76:24] wire _mem_brjmp_oh_T_5 = _mem_brjmp_oh_T_4 | mem_uops_reg_0_bits_next_pc_valid; // @[Core.scala:72:25, :640:75] wire mem_brjmp_oh_0 = mem_uops_reg_0_valid & _mem_brjmp_oh_T_5; // @[Core.scala:72:25, :640:{53,75}] wire _mem_brjmp_oh_T_6 = mem_uops_reg_1_bits_ctrl_branch | mem_uops_reg_1_bits_ctrl_jal; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_7 = _mem_brjmp_oh_T_6 | mem_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_8 = mem_uops_reg_1_bits_ctrl_mem_cmd == 5'h14; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_9 = mem_uops_reg_1_bits_ctrl_mem & _mem_brjmp_oh_T_8; // @[Core.scala:72:25] wire _mem_brjmp_oh_T_10 = _mem_brjmp_oh_T_7 | _mem_brjmp_oh_T_9; // @[MicroOp.scala:72:25, :74:37, :76:24] wire _mem_brjmp_oh_T_11 = _mem_brjmp_oh_T_10 | mem_uops_reg_1_bits_next_pc_valid; // @[Core.scala:72:25, :640:75] wire mem_brjmp_oh_1 = mem_uops_reg_1_valid & _mem_brjmp_oh_T_11; // @[Core.scala:72:25, :640:{53,75}] assign mem_brjmp_val = mem_brjmp_oh_0 | mem_brjmp_oh_1; // @[Core.scala:640:53, :642:44] assign io_imem_btb_update_bits_isValid_0 = mem_brjmp_val; // @[Core.scala:25:7, :642:44] wire _mem_brjmp_uop_WIRE_116; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_1_pc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_target_T = _mem_brjmp_uop_WIRE_bits_pc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_branch; // @[Mux.scala:30:73] assign io_imem_bht_update_bits_branch_0 = _mem_brjmp_uop_WIRE_bits_ctrl_branch; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_1_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_1_ctrl_sel_imm; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_ctrl_alu_fn; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_1_ctrl_csr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_rvc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_sets_vcfg; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_cfiType_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_taken_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_mask_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_bridx_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_target_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_bht_history_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] assign io_imem_bht_update_bits_prediction_history_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_imem_btb_update_bits_prediction_bht_value_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] assign io_imem_bht_update_bits_prediction_value_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_sfb_shadow; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_needs_replay; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_1_rs1_data; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_1_rs2_data; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_1_rs3_data; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_uses_memalu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_uses_latealu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_1_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_fra1; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_npc_a_T = _mem_brjmp_uop_WIRE_bits_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_fra2; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_fra3; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_1_fexc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_1_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_1_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_1_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_1_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_1_mem_size; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_1_flush_pipe; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_bits_inst = _mem_brjmp_uop_WIRE_1_inst; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_WIRE_bits_raw_inst = _mem_brjmp_uop_WIRE_1_raw_inst; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_113; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_pc = _mem_brjmp_uop_WIRE_1_pc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_112; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_edge_inst = _mem_brjmp_uop_WIRE_1_edge_inst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_legal = _mem_brjmp_uop_WIRE_1_ctrl_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_fp = _mem_brjmp_uop_WIRE_1_ctrl_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rocc = _mem_brjmp_uop_WIRE_1_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_branch; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_ctrl_branch = _mem_brjmp_uop_WIRE_1_ctrl_branch; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_jal = _mem_brjmp_uop_WIRE_1_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_jalr = _mem_brjmp_uop_WIRE_1_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rxs2 = _mem_brjmp_uop_WIRE_1_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rxs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rxs1 = _mem_brjmp_uop_WIRE_1_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_83_sel_alu2; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_bits_ctrl_sel_alu2 = _mem_brjmp_uop_WIRE_1_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_83_sel_alu1; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_ctrl_sel_alu1 = _mem_brjmp_uop_WIRE_1_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_83_sel_imm; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_bits_ctrl_sel_imm = _mem_brjmp_uop_WIRE_1_ctrl_sel_imm; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_alu_dw; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_alu_dw = _mem_brjmp_uop_WIRE_1_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_83_alu_fn; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_ctrl_alu_fn = _mem_brjmp_uop_WIRE_1_ctrl_alu_fn; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_mem; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_mem = _mem_brjmp_uop_WIRE_1_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_83_mem_cmd; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_ctrl_mem_cmd = _mem_brjmp_uop_WIRE_1_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rfs1 = _mem_brjmp_uop_WIRE_1_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rfs2 = _mem_brjmp_uop_WIRE_1_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_rfs3 = _mem_brjmp_uop_WIRE_1_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_wfd = _mem_brjmp_uop_WIRE_1_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_mul = _mem_brjmp_uop_WIRE_1_ctrl_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_div = _mem_brjmp_uop_WIRE_1_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_wxd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_wxd = _mem_brjmp_uop_WIRE_1_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_83_csr; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_bits_ctrl_csr = _mem_brjmp_uop_WIRE_1_ctrl_csr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_fence_i = _mem_brjmp_uop_WIRE_1_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_fence = _mem_brjmp_uop_WIRE_1_ctrl_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_amo = _mem_brjmp_uop_WIRE_1_ctrl_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_dp = _mem_brjmp_uop_WIRE_1_ctrl_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_83_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_ctrl_vec = _mem_brjmp_uop_WIRE_1_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_ldst = _mem_brjmp_uop_WIRE_1_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_wen = _mem_brjmp_uop_WIRE_1_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_ren1 = _mem_brjmp_uop_WIRE_1_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_ren2 = _mem_brjmp_uop_WIRE_1_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_ren3 = _mem_brjmp_uop_WIRE_1_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_swap12 = _mem_brjmp_uop_WIRE_1_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_swap23 = _mem_brjmp_uop_WIRE_1_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_65_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fp_ctrl_typeTagIn = _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_65_typeTagOut; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fp_ctrl_typeTagOut = _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_fromint = _mem_brjmp_uop_WIRE_1_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_toint = _mem_brjmp_uop_WIRE_1_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_fastpipe = _mem_brjmp_uop_WIRE_1_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_fma = _mem_brjmp_uop_WIRE_1_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_div = _mem_brjmp_uop_WIRE_1_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_sqrt = _mem_brjmp_uop_WIRE_1_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_wflags = _mem_brjmp_uop_WIRE_1_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_65_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fp_ctrl_vec = _mem_brjmp_uop_WIRE_1_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_64; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_rvc = _mem_brjmp_uop_WIRE_1_rvc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_63; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_sets_vcfg = _mem_brjmp_uop_WIRE_1_sets_vcfg; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_51_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_btb_resp_valid = _mem_brjmp_uop_WIRE_1_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_cfiType = _mem_brjmp_uop_WIRE_1_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_51_bits_taken; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_taken = _mem_brjmp_uop_WIRE_1_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_WIRE_51_bits_mask; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_mask = _mem_brjmp_uop_WIRE_1_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_51_bits_bridx; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bridx = _mem_brjmp_uop_WIRE_1_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_WIRE_51_bits_target; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_target = _mem_brjmp_uop_WIRE_1_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_WIRE_bits_btb_resp_bits_entry = _mem_brjmp_uop_WIRE_1_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_history = _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_btb_resp_bits_bht_value = _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_50; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_sfb_br = _mem_brjmp_uop_WIRE_1_sfb_br; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_49; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_sfb_shadow = _mem_brjmp_uop_WIRE_1_sfb_shadow; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_46_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_next_pc_valid = _mem_brjmp_uop_WIRE_1_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_bits_next_pc_bits = _mem_brjmp_uop_WIRE_1_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_bits_ras_head = _mem_brjmp_uop_WIRE_1_ras_head; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_44; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_taken = _mem_brjmp_uop_WIRE_1_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_43; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_xcpt = _mem_brjmp_uop_WIRE_1_xcpt; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_42; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_bits_xcpt_cause = _mem_brjmp_uop_WIRE_1_xcpt_cause; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_41; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_needs_replay = _mem_brjmp_uop_WIRE_1_needs_replay; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_40; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_bits_rs1_data = _mem_brjmp_uop_WIRE_1_rs1_data; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_39; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_bits_rs2_data = _mem_brjmp_uop_WIRE_1_rs2_data; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_38; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_bits_rs3_data = _mem_brjmp_uop_WIRE_1_rs3_data; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_37; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_uses_memalu = _mem_brjmp_uop_WIRE_1_uses_memalu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_36; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_uses_latealu = _mem_brjmp_uop_WIRE_1_uses_latealu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_33_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_wdata_valid = _mem_brjmp_uop_WIRE_1_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_33_bits; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_bits_wdata_bits = _mem_brjmp_uop_WIRE_1_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_32; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_fra1 = _mem_brjmp_uop_WIRE_1_fra1; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_31; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_fra2 = _mem_brjmp_uop_WIRE_1_fra2; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_30; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_fra3 = _mem_brjmp_uop_WIRE_1_fra3; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_29; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_bits_fexc = _mem_brjmp_uop_WIRE_1_fexc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_ldst = _mem_brjmp_uop_WIRE_1_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_wen = _mem_brjmp_uop_WIRE_1_fdivin_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_ren1 = _mem_brjmp_uop_WIRE_1_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_ren2 = _mem_brjmp_uop_WIRE_1_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_ren3 = _mem_brjmp_uop_WIRE_1_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_swap12 = _mem_brjmp_uop_WIRE_1_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_swap23 = _mem_brjmp_uop_WIRE_1_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_4_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fdivin_typeTagIn = _mem_brjmp_uop_WIRE_1_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_4_typeTagOut; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fdivin_typeTagOut = _mem_brjmp_uop_WIRE_1_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_fromint = _mem_brjmp_uop_WIRE_1_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_toint = _mem_brjmp_uop_WIRE_1_fdivin_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_fastpipe = _mem_brjmp_uop_WIRE_1_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_fma = _mem_brjmp_uop_WIRE_1_fdivin_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_div = _mem_brjmp_uop_WIRE_1_fdivin_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_sqrt = _mem_brjmp_uop_WIRE_1_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_wflags = _mem_brjmp_uop_WIRE_1_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_4_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_fdivin_vec = _mem_brjmp_uop_WIRE_1_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_4_rm; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_bits_fdivin_rm = _mem_brjmp_uop_WIRE_1_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_4_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fdivin_fmaCmd = _mem_brjmp_uop_WIRE_1_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_4_typ; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fdivin_typ = _mem_brjmp_uop_WIRE_1_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_4_fmt; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_fdivin_fmt = _mem_brjmp_uop_WIRE_1_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_4_in1; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_bits_fdivin_in1 = _mem_brjmp_uop_WIRE_1_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_4_in2; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_bits_fdivin_in2 = _mem_brjmp_uop_WIRE_1_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_4_in3; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_bits_fdivin_in3 = _mem_brjmp_uop_WIRE_1_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_bits_mem_size = _mem_brjmp_uop_WIRE_1_mem_size; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_bits_flush_pipe = _mem_brjmp_uop_WIRE_1_flush_pipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T = mem_brjmp_oh_0 & mem_uops_reg_0_bits_flush_pipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_1 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_flush_pipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_2 = _mem_brjmp_uop_T | _mem_brjmp_uop_T_1; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_2 = _mem_brjmp_uop_T_2; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_flush_pipe = _mem_brjmp_uop_WIRE_2; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_3 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_4 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_5 = _mem_brjmp_uop_T_3 | _mem_brjmp_uop_T_4; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_3 = _mem_brjmp_uop_T_5; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_mem_size = _mem_brjmp_uop_WIRE_3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_28; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_ldst = _mem_brjmp_uop_WIRE_4_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_27; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_wen = _mem_brjmp_uop_WIRE_4_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_26; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_ren1 = _mem_brjmp_uop_WIRE_4_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_25; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_ren2 = _mem_brjmp_uop_WIRE_4_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_24; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_ren3 = _mem_brjmp_uop_WIRE_4_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_23; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_swap12 = _mem_brjmp_uop_WIRE_4_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_22; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_swap23 = _mem_brjmp_uop_WIRE_4_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_21; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_typeTagIn = _mem_brjmp_uop_WIRE_4_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_20; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_typeTagOut = _mem_brjmp_uop_WIRE_4_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_19; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_fromint = _mem_brjmp_uop_WIRE_4_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_18; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_toint = _mem_brjmp_uop_WIRE_4_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_17; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_fastpipe = _mem_brjmp_uop_WIRE_4_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_16; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_fma = _mem_brjmp_uop_WIRE_4_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_15; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_div = _mem_brjmp_uop_WIRE_4_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_14; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_sqrt = _mem_brjmp_uop_WIRE_4_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_13; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_wflags = _mem_brjmp_uop_WIRE_4_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_12; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_vec = _mem_brjmp_uop_WIRE_4_vec; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_11; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_rm = _mem_brjmp_uop_WIRE_4_rm; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_10; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_fmaCmd = _mem_brjmp_uop_WIRE_4_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_9; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_typ = _mem_brjmp_uop_WIRE_4_typ; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_8; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_fmt = _mem_brjmp_uop_WIRE_4_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_7; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_in1 = _mem_brjmp_uop_WIRE_4_in1; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_6; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_in2 = _mem_brjmp_uop_WIRE_4_in2; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_WIRE_5; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fdivin_in3 = _mem_brjmp_uop_WIRE_4_in3; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_6 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_7 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_8 = _mem_brjmp_uop_T_6 | _mem_brjmp_uop_T_7; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_5 = _mem_brjmp_uop_T_8; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_in3 = _mem_brjmp_uop_WIRE_5; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_9 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_10 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_11 = _mem_brjmp_uop_T_9 | _mem_brjmp_uop_T_10; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_6 = _mem_brjmp_uop_T_11; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_in2 = _mem_brjmp_uop_WIRE_6; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_12 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_13 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_brjmp_uop_T_14 = _mem_brjmp_uop_T_12 | _mem_brjmp_uop_T_13; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_7 = _mem_brjmp_uop_T_14; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_in1 = _mem_brjmp_uop_WIRE_7; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_15 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_16 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_17 = _mem_brjmp_uop_T_15 | _mem_brjmp_uop_T_16; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_8 = _mem_brjmp_uop_T_17; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_fmt = _mem_brjmp_uop_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_18 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_19 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_20 = _mem_brjmp_uop_T_18 | _mem_brjmp_uop_T_19; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_9 = _mem_brjmp_uop_T_20; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_typ = _mem_brjmp_uop_WIRE_9; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_21 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_22 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_23 = _mem_brjmp_uop_T_21 | _mem_brjmp_uop_T_22; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_10 = _mem_brjmp_uop_T_23; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_fmaCmd = _mem_brjmp_uop_WIRE_10; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_24 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_25 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_26 = _mem_brjmp_uop_T_24 | _mem_brjmp_uop_T_25; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_11 = _mem_brjmp_uop_T_26; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_rm = _mem_brjmp_uop_WIRE_11; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_27 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_28 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_29 = _mem_brjmp_uop_T_27 | _mem_brjmp_uop_T_28; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_12 = _mem_brjmp_uop_T_29; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_vec = _mem_brjmp_uop_WIRE_12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_30 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_31 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_32 = _mem_brjmp_uop_T_30 | _mem_brjmp_uop_T_31; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_13 = _mem_brjmp_uop_T_32; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_wflags = _mem_brjmp_uop_WIRE_13; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_33 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_34 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_35 = _mem_brjmp_uop_T_33 | _mem_brjmp_uop_T_34; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_14 = _mem_brjmp_uop_T_35; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_sqrt = _mem_brjmp_uop_WIRE_14; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_36 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_37 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_38 = _mem_brjmp_uop_T_36 | _mem_brjmp_uop_T_37; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_15 = _mem_brjmp_uop_T_38; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_div = _mem_brjmp_uop_WIRE_15; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_39 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_40 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_41 = _mem_brjmp_uop_T_39 | _mem_brjmp_uop_T_40; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_16 = _mem_brjmp_uop_T_41; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_fma = _mem_brjmp_uop_WIRE_16; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_42 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_43 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_44 = _mem_brjmp_uop_T_42 | _mem_brjmp_uop_T_43; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_17 = _mem_brjmp_uop_T_44; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_fastpipe = _mem_brjmp_uop_WIRE_17; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_45 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_46 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_47 = _mem_brjmp_uop_T_45 | _mem_brjmp_uop_T_46; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_18 = _mem_brjmp_uop_T_47; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_toint = _mem_brjmp_uop_WIRE_18; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_48 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_49 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_50 = _mem_brjmp_uop_T_48 | _mem_brjmp_uop_T_49; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_19 = _mem_brjmp_uop_T_50; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_fromint = _mem_brjmp_uop_WIRE_19; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_51 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_52 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_53 = _mem_brjmp_uop_T_51 | _mem_brjmp_uop_T_52; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_20 = _mem_brjmp_uop_T_53; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_typeTagOut = _mem_brjmp_uop_WIRE_20; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_54 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_55 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_56 = _mem_brjmp_uop_T_54 | _mem_brjmp_uop_T_55; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_21 = _mem_brjmp_uop_T_56; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_typeTagIn = _mem_brjmp_uop_WIRE_21; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_57 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_58 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_59 = _mem_brjmp_uop_T_57 | _mem_brjmp_uop_T_58; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_22 = _mem_brjmp_uop_T_59; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_swap23 = _mem_brjmp_uop_WIRE_22; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_60 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_61 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_62 = _mem_brjmp_uop_T_60 | _mem_brjmp_uop_T_61; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_23 = _mem_brjmp_uop_T_62; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_swap12 = _mem_brjmp_uop_WIRE_23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_63 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_64 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_65 = _mem_brjmp_uop_T_63 | _mem_brjmp_uop_T_64; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_24 = _mem_brjmp_uop_T_65; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_ren3 = _mem_brjmp_uop_WIRE_24; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_66 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_67 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_68 = _mem_brjmp_uop_T_66 | _mem_brjmp_uop_T_67; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_25 = _mem_brjmp_uop_T_68; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_ren2 = _mem_brjmp_uop_WIRE_25; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_69 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_70 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_71 = _mem_brjmp_uop_T_69 | _mem_brjmp_uop_T_70; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_26 = _mem_brjmp_uop_T_71; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_ren1 = _mem_brjmp_uop_WIRE_26; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_72 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_73 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_74 = _mem_brjmp_uop_T_72 | _mem_brjmp_uop_T_73; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_27 = _mem_brjmp_uop_T_74; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_wen = _mem_brjmp_uop_WIRE_27; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_75 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_76 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_77 = _mem_brjmp_uop_T_75 | _mem_brjmp_uop_T_76; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_28 = _mem_brjmp_uop_T_77; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_4_ldst = _mem_brjmp_uop_WIRE_28; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_78 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_79 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_80 = _mem_brjmp_uop_T_78 | _mem_brjmp_uop_T_79; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_29 = _mem_brjmp_uop_T_80; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fexc = _mem_brjmp_uop_WIRE_29; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_81 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_82 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_83 = _mem_brjmp_uop_T_81 | _mem_brjmp_uop_T_82; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_30 = _mem_brjmp_uop_T_83; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fra3 = _mem_brjmp_uop_WIRE_30; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_84 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_85 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_86 = _mem_brjmp_uop_T_84 | _mem_brjmp_uop_T_85; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_31 = _mem_brjmp_uop_T_86; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fra2 = _mem_brjmp_uop_WIRE_31; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_87 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_88 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_89 = _mem_brjmp_uop_T_87 | _mem_brjmp_uop_T_88; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_32 = _mem_brjmp_uop_T_89; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fra1 = _mem_brjmp_uop_WIRE_32; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_35; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_wdata_valid = _mem_brjmp_uop_WIRE_33_valid; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_WIRE_34; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_wdata_bits = _mem_brjmp_uop_WIRE_33_bits; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_90 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_91 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_92 = _mem_brjmp_uop_T_90 | _mem_brjmp_uop_T_91; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_34 = _mem_brjmp_uop_T_92; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_33_bits = _mem_brjmp_uop_WIRE_34; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_93 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_wdata_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_94 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_wdata_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_95 = _mem_brjmp_uop_T_93 | _mem_brjmp_uop_T_94; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_35 = _mem_brjmp_uop_T_95; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_33_valid = _mem_brjmp_uop_WIRE_35; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_96 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_uses_latealu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_97 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_uses_latealu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_98 = _mem_brjmp_uop_T_96 | _mem_brjmp_uop_T_97; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_36 = _mem_brjmp_uop_T_98; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_uses_latealu = _mem_brjmp_uop_WIRE_36; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_99 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_uses_memalu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_100 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_uses_memalu; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_101 = _mem_brjmp_uop_T_99 | _mem_brjmp_uop_T_100; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_37 = _mem_brjmp_uop_T_101; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_uses_memalu = _mem_brjmp_uop_WIRE_37; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_102 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_103 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_104 = _mem_brjmp_uop_T_102 | _mem_brjmp_uop_T_103; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_38 = _mem_brjmp_uop_T_104; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_rs3_data = _mem_brjmp_uop_WIRE_38; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_105 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_106 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_107 = _mem_brjmp_uop_T_105 | _mem_brjmp_uop_T_106; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_39 = _mem_brjmp_uop_T_107; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_rs2_data = _mem_brjmp_uop_WIRE_39; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_108 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_109 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_110 = _mem_brjmp_uop_T_108 | _mem_brjmp_uop_T_109; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_40 = _mem_brjmp_uop_T_110; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_rs1_data = _mem_brjmp_uop_WIRE_40; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_111 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_needs_replay; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_112 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_needs_replay; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_113 = _mem_brjmp_uop_T_111 | _mem_brjmp_uop_T_112; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_41 = _mem_brjmp_uop_T_113; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_needs_replay = _mem_brjmp_uop_WIRE_41; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_114 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_115 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_brjmp_uop_T_116 = _mem_brjmp_uop_T_114 | _mem_brjmp_uop_T_115; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_42 = _mem_brjmp_uop_T_116; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_xcpt_cause = _mem_brjmp_uop_WIRE_42; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_117 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_xcpt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_118 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_xcpt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_119 = _mem_brjmp_uop_T_117 | _mem_brjmp_uop_T_118; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_43 = _mem_brjmp_uop_T_119; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_xcpt = _mem_brjmp_uop_WIRE_43; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_120 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_121 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_122 = _mem_brjmp_uop_T_120 | _mem_brjmp_uop_T_121; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_44 = _mem_brjmp_uop_T_122; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_taken = _mem_brjmp_uop_WIRE_44; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_123 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_124 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_125 = _mem_brjmp_uop_T_123 | _mem_brjmp_uop_T_124; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_45 = _mem_brjmp_uop_T_125; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ras_head = _mem_brjmp_uop_WIRE_45; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_48; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_next_pc_valid = _mem_brjmp_uop_WIRE_46_valid; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_WIRE_47; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_next_pc_bits = _mem_brjmp_uop_WIRE_46_bits; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_126 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_127 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_128 = _mem_brjmp_uop_T_126 | _mem_brjmp_uop_T_127; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_47 = _mem_brjmp_uop_T_128; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_46_bits = _mem_brjmp_uop_WIRE_47; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_129 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_130 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_131 = _mem_brjmp_uop_T_129 | _mem_brjmp_uop_T_130; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_48 = _mem_brjmp_uop_T_131; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_46_valid = _mem_brjmp_uop_WIRE_48; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_132 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_sfb_shadow; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_133 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_sfb_shadow; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_134 = _mem_brjmp_uop_T_132 | _mem_brjmp_uop_T_133; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_49 = _mem_brjmp_uop_T_134; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_sfb_shadow = _mem_brjmp_uop_WIRE_49; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_135 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_sfb_br; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_136 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_sfb_br; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_137 = _mem_brjmp_uop_T_135 | _mem_brjmp_uop_T_136; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_50 = _mem_brjmp_uop_T_137; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_sfb_br = _mem_brjmp_uop_WIRE_50; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_62; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_valid = _mem_brjmp_uop_WIRE_51_valid; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_52_cfiType; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_cfiType = _mem_brjmp_uop_WIRE_51_bits_cfiType; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_52_taken; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_taken = _mem_brjmp_uop_WIRE_51_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_WIRE_52_mask; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_mask = _mem_brjmp_uop_WIRE_51_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_52_bridx; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_bridx = _mem_brjmp_uop_WIRE_51_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_WIRE_52_target; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_target = _mem_brjmp_uop_WIRE_51_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_WIRE_52_entry; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_entry = _mem_brjmp_uop_WIRE_51_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_52_bht_history; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_history = _mem_brjmp_uop_WIRE_51_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_52_bht_value; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_btb_resp_bits_bht_value = _mem_brjmp_uop_WIRE_51_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_61; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_cfiType = _mem_brjmp_uop_WIRE_52_cfiType; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_60; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_taken = _mem_brjmp_uop_WIRE_52_taken; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_WIRE_59; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_mask = _mem_brjmp_uop_WIRE_52_mask; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_58; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_bridx = _mem_brjmp_uop_WIRE_52_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_WIRE_57; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_target = _mem_brjmp_uop_WIRE_52_target; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_WIRE_56; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_entry = _mem_brjmp_uop_WIRE_52_entry; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_53_history; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_bht_history = _mem_brjmp_uop_WIRE_52_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_53_value; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_bits_bht_value = _mem_brjmp_uop_WIRE_52_bht_value; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_WIRE_55; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_bht_history = _mem_brjmp_uop_WIRE_53_history; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_54; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_bht_value = _mem_brjmp_uop_WIRE_53_value; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_138 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_139 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_140 = _mem_brjmp_uop_T_138 | _mem_brjmp_uop_T_139; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_54 = _mem_brjmp_uop_T_140; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_53_value = _mem_brjmp_uop_WIRE_54; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_T_141 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_T_142 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_uop_T_143 = _mem_brjmp_uop_T_141 | _mem_brjmp_uop_T_142; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_55 = _mem_brjmp_uop_T_143; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_53_history = _mem_brjmp_uop_WIRE_55; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_T_144 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_T_145 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_uop_T_146 = _mem_brjmp_uop_T_144 | _mem_brjmp_uop_T_145; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_56 = _mem_brjmp_uop_T_146; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_entry = _mem_brjmp_uop_WIRE_56; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_T_147 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_T_148 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _mem_brjmp_uop_T_149 = _mem_brjmp_uop_T_147 | _mem_brjmp_uop_T_148; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_57 = _mem_brjmp_uop_T_149; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_target = _mem_brjmp_uop_WIRE_57; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_150 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_151 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_152 = _mem_brjmp_uop_T_150 | _mem_brjmp_uop_T_151; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_58 = _mem_brjmp_uop_T_152; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_bridx = _mem_brjmp_uop_WIRE_58; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_T_153 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_T_154 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_uop_T_155 = _mem_brjmp_uop_T_153 | _mem_brjmp_uop_T_154; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_59 = _mem_brjmp_uop_T_155; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_mask = _mem_brjmp_uop_WIRE_59; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_156 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_157 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_158 = _mem_brjmp_uop_T_156 | _mem_brjmp_uop_T_157; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_60 = _mem_brjmp_uop_T_158; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_taken = _mem_brjmp_uop_WIRE_60; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_159 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_160 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_161 = _mem_brjmp_uop_T_159 | _mem_brjmp_uop_T_160; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_61 = _mem_brjmp_uop_T_161; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_52_cfiType = _mem_brjmp_uop_WIRE_61; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_162 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_163 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_164 = _mem_brjmp_uop_T_162 | _mem_brjmp_uop_T_163; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_62 = _mem_brjmp_uop_T_164; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_51_valid = _mem_brjmp_uop_WIRE_62; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_165 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_sets_vcfg; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_166 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_sets_vcfg; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_167 = _mem_brjmp_uop_T_165 | _mem_brjmp_uop_T_166; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_63 = _mem_brjmp_uop_T_167; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_sets_vcfg = _mem_brjmp_uop_WIRE_63; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_168 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_rvc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_169 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_rvc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_170 = _mem_brjmp_uop_T_168 | _mem_brjmp_uop_T_169; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_64 = _mem_brjmp_uop_T_170; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_rvc = _mem_brjmp_uop_WIRE_64; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_82; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_ldst = _mem_brjmp_uop_WIRE_65_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_81; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_wen = _mem_brjmp_uop_WIRE_65_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_80; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_ren1 = _mem_brjmp_uop_WIRE_65_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_79; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_ren2 = _mem_brjmp_uop_WIRE_65_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_78; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_ren3 = _mem_brjmp_uop_WIRE_65_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_77; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_swap12 = _mem_brjmp_uop_WIRE_65_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_76; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_swap23 = _mem_brjmp_uop_WIRE_65_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_75; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagIn = _mem_brjmp_uop_WIRE_65_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_74; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_typeTagOut = _mem_brjmp_uop_WIRE_65_typeTagOut; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_73; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_fromint = _mem_brjmp_uop_WIRE_65_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_72; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_toint = _mem_brjmp_uop_WIRE_65_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_71; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_fastpipe = _mem_brjmp_uop_WIRE_65_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_70; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_fma = _mem_brjmp_uop_WIRE_65_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_69; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_div = _mem_brjmp_uop_WIRE_65_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_68; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_sqrt = _mem_brjmp_uop_WIRE_65_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_67; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_wflags = _mem_brjmp_uop_WIRE_65_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_66; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_fp_ctrl_vec = _mem_brjmp_uop_WIRE_65_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_171 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_172 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_173 = _mem_brjmp_uop_T_171 | _mem_brjmp_uop_T_172; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_66 = _mem_brjmp_uop_T_173; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_vec = _mem_brjmp_uop_WIRE_66; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_174 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_175 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_176 = _mem_brjmp_uop_T_174 | _mem_brjmp_uop_T_175; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_67 = _mem_brjmp_uop_T_176; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_wflags = _mem_brjmp_uop_WIRE_67; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_177 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_178 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_179 = _mem_brjmp_uop_T_177 | _mem_brjmp_uop_T_178; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_68 = _mem_brjmp_uop_T_179; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_sqrt = _mem_brjmp_uop_WIRE_68; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_180 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_181 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_182 = _mem_brjmp_uop_T_180 | _mem_brjmp_uop_T_181; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_69 = _mem_brjmp_uop_T_182; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_div = _mem_brjmp_uop_WIRE_69; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_183 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_184 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_185 = _mem_brjmp_uop_T_183 | _mem_brjmp_uop_T_184; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_70 = _mem_brjmp_uop_T_185; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_fma = _mem_brjmp_uop_WIRE_70; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_186 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_187 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_188 = _mem_brjmp_uop_T_186 | _mem_brjmp_uop_T_187; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_71 = _mem_brjmp_uop_T_188; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_fastpipe = _mem_brjmp_uop_WIRE_71; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_189 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_190 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_191 = _mem_brjmp_uop_T_189 | _mem_brjmp_uop_T_190; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_72 = _mem_brjmp_uop_T_191; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_toint = _mem_brjmp_uop_WIRE_72; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_192 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_193 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_194 = _mem_brjmp_uop_T_192 | _mem_brjmp_uop_T_193; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_73 = _mem_brjmp_uop_T_194; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_fromint = _mem_brjmp_uop_WIRE_73; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_195 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_196 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_197 = _mem_brjmp_uop_T_195 | _mem_brjmp_uop_T_196; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_74 = _mem_brjmp_uop_T_197; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_typeTagOut = _mem_brjmp_uop_WIRE_74; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_198 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_199 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_200 = _mem_brjmp_uop_T_198 | _mem_brjmp_uop_T_199; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_75 = _mem_brjmp_uop_T_200; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_typeTagIn = _mem_brjmp_uop_WIRE_75; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_201 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_202 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_203 = _mem_brjmp_uop_T_201 | _mem_brjmp_uop_T_202; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_76 = _mem_brjmp_uop_T_203; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_swap23 = _mem_brjmp_uop_WIRE_76; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_204 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_205 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_206 = _mem_brjmp_uop_T_204 | _mem_brjmp_uop_T_205; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_77 = _mem_brjmp_uop_T_206; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_swap12 = _mem_brjmp_uop_WIRE_77; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_207 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_208 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_209 = _mem_brjmp_uop_T_207 | _mem_brjmp_uop_T_208; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_78 = _mem_brjmp_uop_T_209; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_ren3 = _mem_brjmp_uop_WIRE_78; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_210 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_211 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_212 = _mem_brjmp_uop_T_210 | _mem_brjmp_uop_T_211; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_79 = _mem_brjmp_uop_T_212; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_ren2 = _mem_brjmp_uop_WIRE_79; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_213 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_214 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_215 = _mem_brjmp_uop_T_213 | _mem_brjmp_uop_T_214; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_80 = _mem_brjmp_uop_T_215; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_ren1 = _mem_brjmp_uop_WIRE_80; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_216 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_217 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_218 = _mem_brjmp_uop_T_216 | _mem_brjmp_uop_T_217; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_81 = _mem_brjmp_uop_T_218; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_wen = _mem_brjmp_uop_WIRE_81; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_219 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_220 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_221 = _mem_brjmp_uop_T_219 | _mem_brjmp_uop_T_220; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_82 = _mem_brjmp_uop_T_221; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_65_ldst = _mem_brjmp_uop_WIRE_82; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_111; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_legal = _mem_brjmp_uop_WIRE_83_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_110; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_fp = _mem_brjmp_uop_WIRE_83_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_109; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rocc = _mem_brjmp_uop_WIRE_83_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_108; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_branch = _mem_brjmp_uop_WIRE_83_branch; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_107; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_jal = _mem_brjmp_uop_WIRE_83_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_106; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_jalr = _mem_brjmp_uop_WIRE_83_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_105; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rxs2 = _mem_brjmp_uop_WIRE_83_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_104; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rxs1 = _mem_brjmp_uop_WIRE_83_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_103; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_sel_alu2 = _mem_brjmp_uop_WIRE_83_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_WIRE_102; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_sel_alu1 = _mem_brjmp_uop_WIRE_83_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_101; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_sel_imm = _mem_brjmp_uop_WIRE_83_sel_imm; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_100; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_alu_dw = _mem_brjmp_uop_WIRE_83_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_99; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_alu_fn = _mem_brjmp_uop_WIRE_83_alu_fn; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_98; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_mem = _mem_brjmp_uop_WIRE_83_mem; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_WIRE_97; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_mem_cmd = _mem_brjmp_uop_WIRE_83_mem_cmd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_96; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rfs1 = _mem_brjmp_uop_WIRE_83_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_95; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rfs2 = _mem_brjmp_uop_WIRE_83_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_94; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_rfs3 = _mem_brjmp_uop_WIRE_83_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_93; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_wfd = _mem_brjmp_uop_WIRE_83_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_92; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_mul = _mem_brjmp_uop_WIRE_83_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_91; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_div = _mem_brjmp_uop_WIRE_83_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_90; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_wxd = _mem_brjmp_uop_WIRE_83_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_WIRE_89; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_csr = _mem_brjmp_uop_WIRE_83_csr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_88; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_fence_i = _mem_brjmp_uop_WIRE_83_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_87; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_fence = _mem_brjmp_uop_WIRE_83_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_86; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_amo = _mem_brjmp_uop_WIRE_83_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_85; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_dp = _mem_brjmp_uop_WIRE_83_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_84; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_ctrl_vec = _mem_brjmp_uop_WIRE_83_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_222 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_223 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_vec; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_224 = _mem_brjmp_uop_T_222 | _mem_brjmp_uop_T_223; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_84 = _mem_brjmp_uop_T_224; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_vec = _mem_brjmp_uop_WIRE_84; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_225 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_226 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_dp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_227 = _mem_brjmp_uop_T_225 | _mem_brjmp_uop_T_226; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_85 = _mem_brjmp_uop_T_227; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_dp = _mem_brjmp_uop_WIRE_85; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_228 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_229 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_amo; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_230 = _mem_brjmp_uop_T_228 | _mem_brjmp_uop_T_229; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_86 = _mem_brjmp_uop_T_230; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_amo = _mem_brjmp_uop_WIRE_86; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_231 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_232 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_fence; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_233 = _mem_brjmp_uop_T_231 | _mem_brjmp_uop_T_232; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_87 = _mem_brjmp_uop_T_233; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_fence = _mem_brjmp_uop_WIRE_87; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_234 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_235 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_236 = _mem_brjmp_uop_T_234 | _mem_brjmp_uop_T_235; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_88 = _mem_brjmp_uop_T_236; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_fence_i = _mem_brjmp_uop_WIRE_88; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_237 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_238 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_239 = _mem_brjmp_uop_T_237 | _mem_brjmp_uop_T_238; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_89 = _mem_brjmp_uop_T_239; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_csr = _mem_brjmp_uop_WIRE_89; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_240 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_241 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_242 = _mem_brjmp_uop_T_240 | _mem_brjmp_uop_T_241; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_90 = _mem_brjmp_uop_T_242; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_wxd = _mem_brjmp_uop_WIRE_90; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_243 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_244 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_div; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_245 = _mem_brjmp_uop_T_243 | _mem_brjmp_uop_T_244; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_91 = _mem_brjmp_uop_T_245; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_div = _mem_brjmp_uop_WIRE_91; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_246 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_247 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_mul; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_248 = _mem_brjmp_uop_T_246 | _mem_brjmp_uop_T_247; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_92 = _mem_brjmp_uop_T_248; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_mul = _mem_brjmp_uop_WIRE_92; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_249 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_250 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_251 = _mem_brjmp_uop_T_249 | _mem_brjmp_uop_T_250; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_93 = _mem_brjmp_uop_T_251; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_wfd = _mem_brjmp_uop_WIRE_93; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_252 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_253 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_254 = _mem_brjmp_uop_T_252 | _mem_brjmp_uop_T_253; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_94 = _mem_brjmp_uop_T_254; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rfs3 = _mem_brjmp_uop_WIRE_94; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_255 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_256 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_257 = _mem_brjmp_uop_T_255 | _mem_brjmp_uop_T_256; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_95 = _mem_brjmp_uop_T_257; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rfs2 = _mem_brjmp_uop_WIRE_95; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_258 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_259 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_260 = _mem_brjmp_uop_T_258 | _mem_brjmp_uop_T_259; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_96 = _mem_brjmp_uop_T_260; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rfs1 = _mem_brjmp_uop_WIRE_96; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_261 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_262 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_263 = _mem_brjmp_uop_T_261 | _mem_brjmp_uop_T_262; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_97 = _mem_brjmp_uop_T_263; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_mem_cmd = _mem_brjmp_uop_WIRE_97; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_264 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_mem; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_265 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_mem; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_266 = _mem_brjmp_uop_T_264 | _mem_brjmp_uop_T_265; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_98 = _mem_brjmp_uop_T_266; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_mem = _mem_brjmp_uop_WIRE_98; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_267 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_268 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_uop_T_269 = _mem_brjmp_uop_T_267 | _mem_brjmp_uop_T_268; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_99 = _mem_brjmp_uop_T_269; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_alu_fn = _mem_brjmp_uop_WIRE_99; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_270 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_271 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_272 = _mem_brjmp_uop_T_270 | _mem_brjmp_uop_T_271; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_100 = _mem_brjmp_uop_T_272; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_alu_dw = _mem_brjmp_uop_WIRE_100; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_273 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_274 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_275 = _mem_brjmp_uop_T_273 | _mem_brjmp_uop_T_274; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_101 = _mem_brjmp_uop_T_275; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_sel_imm = _mem_brjmp_uop_WIRE_101; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_276 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_277 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_brjmp_uop_T_278 = _mem_brjmp_uop_T_276 | _mem_brjmp_uop_T_277; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_102 = _mem_brjmp_uop_T_278; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_sel_alu1 = _mem_brjmp_uop_WIRE_102; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_279 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_280 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_brjmp_uop_T_281 = _mem_brjmp_uop_T_279 | _mem_brjmp_uop_T_280; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_103 = _mem_brjmp_uop_T_281; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_sel_alu2 = _mem_brjmp_uop_WIRE_103; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_282 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_283 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_284 = _mem_brjmp_uop_T_282 | _mem_brjmp_uop_T_283; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_104 = _mem_brjmp_uop_T_284; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rxs1 = _mem_brjmp_uop_WIRE_104; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_285 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_286 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_287 = _mem_brjmp_uop_T_285 | _mem_brjmp_uop_T_286; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_105 = _mem_brjmp_uop_T_287; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rxs2 = _mem_brjmp_uop_WIRE_105; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_288 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_289 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_290 = _mem_brjmp_uop_T_288 | _mem_brjmp_uop_T_289; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_106 = _mem_brjmp_uop_T_290; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_jalr = _mem_brjmp_uop_WIRE_106; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_291 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_292 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_293 = _mem_brjmp_uop_T_291 | _mem_brjmp_uop_T_292; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_107 = _mem_brjmp_uop_T_293; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_jal = _mem_brjmp_uop_WIRE_107; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_294 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_branch; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_295 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_branch; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_296 = _mem_brjmp_uop_T_294 | _mem_brjmp_uop_T_295; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_108 = _mem_brjmp_uop_T_296; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_branch = _mem_brjmp_uop_WIRE_108; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_297 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_298 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_299 = _mem_brjmp_uop_T_297 | _mem_brjmp_uop_T_298; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_109 = _mem_brjmp_uop_T_299; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_rocc = _mem_brjmp_uop_WIRE_109; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_300 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_301 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_fp; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_302 = _mem_brjmp_uop_T_300 | _mem_brjmp_uop_T_301; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_110 = _mem_brjmp_uop_T_302; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_fp = _mem_brjmp_uop_WIRE_110; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_303 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_ctrl_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_304 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_ctrl_legal; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_305 = _mem_brjmp_uop_T_303 | _mem_brjmp_uop_T_304; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_111 = _mem_brjmp_uop_T_305; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_83_legal = _mem_brjmp_uop_WIRE_111; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_306 = mem_brjmp_oh_0 & mem_uops_reg_0_bits_edge_inst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_307 = mem_brjmp_oh_1 & mem_uops_reg_1_bits_edge_inst; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_308 = _mem_brjmp_uop_T_306 | _mem_brjmp_uop_T_307; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_112 = _mem_brjmp_uop_T_308; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_edge_inst = _mem_brjmp_uop_WIRE_112; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_309 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_310 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_uop_T_311 = _mem_brjmp_uop_T_309 | _mem_brjmp_uop_T_310; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_113 = _mem_brjmp_uop_T_311; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_pc = _mem_brjmp_uop_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_312 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_313 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_314 = _mem_brjmp_uop_T_312 | _mem_brjmp_uop_T_313; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_114 = _mem_brjmp_uop_T_314; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_raw_inst = _mem_brjmp_uop_WIRE_114; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_315 = mem_brjmp_oh_0 ? mem_uops_reg_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_316 = mem_brjmp_oh_1 ? mem_uops_reg_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_uop_T_317 = _mem_brjmp_uop_T_315 | _mem_brjmp_uop_T_316; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_115 = _mem_brjmp_uop_T_317; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_1_inst = _mem_brjmp_uop_WIRE_115; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_318 = mem_brjmp_oh_0 & mem_uops_reg_0_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_319 = mem_brjmp_oh_1 & mem_uops_reg_1_valid; // @[Mux.scala:30:73] wire _mem_brjmp_uop_T_320 = _mem_brjmp_uop_T_318 | _mem_brjmp_uop_T_319; // @[Mux.scala:30:73] assign _mem_brjmp_uop_WIRE_116 = _mem_brjmp_uop_T_320; // @[Mux.scala:30:73] wire _mem_brjmp_uop_WIRE_valid = _mem_brjmp_uop_WIRE_116; // @[Mux.scala:30:73] wire _GEN_103 = _mem_brjmp_uop_WIRE_bits_ctrl_jalr | _mem_brjmp_uop_WIRE_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_call_T; // @[Core.scala:645:45] assign _mem_brjmp_call_T = _GEN_103; // @[Core.scala:645:45] wire _io_imem_btb_update_bits_cfiType_T; // @[Core.scala:665:29] assign _io_imem_btb_update_bits_cfiType_T = _GEN_103; // @[Core.scala:645:45, :665:29] wire _io_imem_btb_update_bits_cfiType_T_8; // @[Core.scala:667:28] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_103; // @[Core.scala:645:45, :667:28] wire [4:0] _mem_brjmp_call_T_1 = _mem_brjmp_uop_WIRE_bits_inst[11:7]; // @[Mux.scala:30:73] wire [4:0] _mem_brjmp_ret_T_3 = _mem_brjmp_uop_WIRE_bits_inst[11:7]; // @[Mux.scala:30:73] wire [4:0] _io_imem_btb_update_bits_cfiType_T_1 = _mem_brjmp_uop_WIRE_bits_inst[11:7]; // @[Mux.scala:30:73] wire _mem_brjmp_call_T_2 = _mem_brjmp_call_T_1 == 5'h1; // @[Core.scala:645:88] wire mem_brjmp_call = _mem_brjmp_call_T & _mem_brjmp_call_T_2; // @[Core.scala:645:{45,68,88}] wire [4:0] _mem_brjmp_ret_T = _mem_brjmp_uop_WIRE_bits_inst[19:15]; // @[Mux.scala:30:73] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _mem_brjmp_uop_WIRE_bits_inst[19:15]; // @[Mux.scala:30:73] wire _mem_brjmp_ret_T_1 = _mem_brjmp_ret_T == 5'h1; // @[Core.scala:646:64] wire _mem_brjmp_ret_T_2 = _mem_brjmp_uop_WIRE_bits_ctrl_jalr & _mem_brjmp_ret_T_1; // @[Mux.scala:30:73] wire _mem_brjmp_ret_T_4 = _mem_brjmp_ret_T_3 == 5'h0; // @[Core.scala:646:92] wire mem_brjmp_ret = _mem_brjmp_ret_T_2 & _mem_brjmp_ret_T_4; // @[Core.scala:646:{43,72,92}] wire _GEN_104 = _mem_brjmp_uop_WIRE_bits_ctrl_branch & _mem_brjmp_uop_WIRE_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_target_T_1; // @[Core.scala:648:31] assign _mem_brjmp_target_T_1 = _GEN_104; // @[Core.scala:648:31] wire _mem_brjmp_taken_T; // @[Core.scala:655:48] assign _mem_brjmp_taken_T = _GEN_104; // @[Core.scala:648:31, :655:48] wire _mem_brjmp_target_sign_T_1 = _mem_brjmp_uop_WIRE_bits_inst[31]; // @[Mux.scala:30:73] wire _mem_brjmp_target_sign_T_4 = _mem_brjmp_uop_WIRE_bits_inst[31]; // @[Mux.scala:30:73] wire _mem_brjmp_target_sign_T_2 = _mem_brjmp_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_brjmp_target_sign = _mem_brjmp_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_brjmp_target_hi_hi_hi = mem_brjmp_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_brjmp_target_b30_20_T_1 = _mem_brjmp_uop_WIRE_bits_inst[30:20]; // @[Mux.scala:30:73] wire [10:0] _mem_brjmp_target_b30_20_T_4 = _mem_brjmp_uop_WIRE_bits_inst[30:20]; // @[Mux.scala:30:73] wire [10:0] _mem_brjmp_target_b30_20_T_2 = _mem_brjmp_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_brjmp_target_b30_20 = {11{mem_brjmp_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_brjmp_target_hi_hi_lo = mem_brjmp_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_brjmp_target_b19_12_T_3 = _mem_brjmp_uop_WIRE_bits_inst[19:12]; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_target_b19_12_T_8 = _mem_brjmp_uop_WIRE_bits_inst[19:12]; // @[Mux.scala:30:73] wire [7:0] _mem_brjmp_target_b19_12_T_4 = _mem_brjmp_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_brjmp_target_b19_12 = {8{mem_brjmp_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_brjmp_target_hi_lo_hi = mem_brjmp_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_brjmp_target_b11_T_4 = _mem_brjmp_uop_WIRE_bits_inst[20]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b0_T_3 = _mem_brjmp_uop_WIRE_bits_inst[20]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b11_T_15 = _mem_brjmp_uop_WIRE_bits_inst[20]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b0_T_11 = _mem_brjmp_uop_WIRE_bits_inst[20]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b11_T_5 = _mem_brjmp_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_brjmp_target_b11_T_7 = _mem_brjmp_uop_WIRE_bits_inst[7]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b0_T_1 = _mem_brjmp_uop_WIRE_bits_inst[7]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b11_T_18 = _mem_brjmp_uop_WIRE_bits_inst[7]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b0_T_9 = _mem_brjmp_uop_WIRE_bits_inst[7]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b11_T_8 = _mem_brjmp_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_brjmp_target_b11_T_9 = _mem_brjmp_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_brjmp_target_b11_T_10 = _mem_brjmp_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_brjmp_target_b11 = _mem_brjmp_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_brjmp_target_hi_lo_lo = mem_brjmp_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_brjmp_target_b10_5_T_3 = _mem_brjmp_uop_WIRE_bits_inst[30:25]; // @[Mux.scala:30:73] wire [5:0] _mem_brjmp_target_b10_5_T_7 = _mem_brjmp_uop_WIRE_bits_inst[30:25]; // @[Mux.scala:30:73] wire [5:0] mem_brjmp_target_b10_5 = _mem_brjmp_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_brjmp_target_b4_1_T_4 = _mem_brjmp_uop_WIRE_bits_inst[11:8]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_14 = _mem_brjmp_uop_WIRE_bits_inst[11:8]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_9 = _mem_brjmp_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_brjmp_target_b4_1_T_6 = _mem_brjmp_uop_WIRE_bits_inst[19:16]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_16 = _mem_brjmp_uop_WIRE_bits_inst[19:16]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_7 = _mem_brjmp_uop_WIRE_bits_inst[24:21]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_17 = _mem_brjmp_uop_WIRE_bits_inst[24:21]; // @[Mux.scala:30:73] wire [3:0] _mem_brjmp_target_b4_1_T_8 = _mem_brjmp_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_brjmp_target_b4_1 = _mem_brjmp_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_brjmp_target_b0_T_5 = _mem_brjmp_uop_WIRE_bits_inst[15]; // @[Mux.scala:30:73] wire _mem_brjmp_target_b0_T_13 = _mem_brjmp_uop_WIRE_bits_inst[15]; // @[Mux.scala:30:73] wire [9:0] mem_brjmp_target_lo_hi = {mem_brjmp_target_b10_5, mem_brjmp_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_brjmp_target_lo = {mem_brjmp_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_brjmp_target_hi_lo = {mem_brjmp_target_hi_lo_hi, mem_brjmp_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_brjmp_target_hi_hi = {mem_brjmp_target_hi_hi_hi, mem_brjmp_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_brjmp_target_hi = {mem_brjmp_target_hi_hi, mem_brjmp_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_brjmp_target_T_2 = {mem_brjmp_target_hi, mem_brjmp_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_brjmp_target_T_3 = _mem_brjmp_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_brjmp_target_sign_T_5 = _mem_brjmp_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_brjmp_target_sign_1 = _mem_brjmp_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_brjmp_target_b11_T_20 = mem_brjmp_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_brjmp_target_hi_hi_hi_1 = mem_brjmp_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_brjmp_target_b30_20_T_5 = _mem_brjmp_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_brjmp_target_b30_20_1 = {11{mem_brjmp_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_brjmp_target_hi_hi_lo_1 = mem_brjmp_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_brjmp_target_b19_12_T_9 = _mem_brjmp_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_brjmp_target_b19_12_1 = _mem_brjmp_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_brjmp_target_hi_lo_hi_1 = mem_brjmp_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_brjmp_target_b11_T_16 = _mem_brjmp_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_brjmp_target_b11_T_21 = _mem_brjmp_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_brjmp_target_b11_T_19 = _mem_brjmp_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_brjmp_target_b11_1 = _mem_brjmp_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_brjmp_target_hi_lo_lo_1 = mem_brjmp_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_brjmp_target_b10_5_1 = _mem_brjmp_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_brjmp_target_b4_1_T_18 = _mem_brjmp_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_brjmp_target_b4_1_T_19 = _mem_brjmp_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_brjmp_target_b4_1_1 = _mem_brjmp_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_brjmp_target_lo_hi_1 = {mem_brjmp_target_b10_5_1, mem_brjmp_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_brjmp_target_lo_1 = {mem_brjmp_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_brjmp_target_hi_lo_1 = {mem_brjmp_target_hi_lo_hi_1, mem_brjmp_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_brjmp_target_hi_hi_1 = {mem_brjmp_target_hi_hi_hi_1, mem_brjmp_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_brjmp_target_hi_1 = {mem_brjmp_target_hi_hi_1, mem_brjmp_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_brjmp_target_T_4 = {mem_brjmp_target_hi_1, mem_brjmp_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_brjmp_target_T_5 = _mem_brjmp_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_brjmp_target_T_6 = _mem_brjmp_uop_WIRE_bits_rvc ? 4'h2 : 4'h4; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_target_T_7 = _mem_brjmp_uop_WIRE_bits_ctrl_jal ? _mem_brjmp_target_T_5 : {{28{_mem_brjmp_target_T_6[3]}}, _mem_brjmp_target_T_6}; // @[Mux.scala:30:73] wire [31:0] _mem_brjmp_target_T_8 = _mem_brjmp_target_T_1 ? _mem_brjmp_target_T_3 : _mem_brjmp_target_T_7; // @[Core.scala:648:{8,31}, :649:8] wire [40:0] _mem_brjmp_target_T_9 = {_mem_brjmp_target_T[39], _mem_brjmp_target_T} + {{9{_mem_brjmp_target_T_8[31]}}, _mem_brjmp_target_T_8}; // @[Core.scala:647:{43,50}, :648:8] wire [39:0] _mem_brjmp_target_T_10 = _mem_brjmp_target_T_9[39:0]; // @[Core.scala:647:50] wire [39:0] mem_brjmp_target = _mem_brjmp_target_T_10; // @[Core.scala:647:50] wire [39:0] _com_uops_reg_0_bits_wdata_bits_T = mem_brjmp_target; // @[Core.scala:647:50, :740:64] wire [39:0] _com_uops_reg_1_bits_wdata_bits_T = mem_brjmp_target; // @[Core.scala:647:50, :740:64] wire _mem_brjmp_npc_T = _mem_brjmp_uop_WIRE_bits_ctrl_mem_cmd == 5'h14; // @[Mux.scala:30:73] wire _mem_brjmp_npc_T_1 = _mem_brjmp_uop_WIRE_bits_ctrl_mem & _mem_brjmp_npc_T; // @[Mux.scala:30:73] wire _mem_brjmp_npc_T_2 = _mem_brjmp_uop_WIRE_bits_ctrl_jalr | _mem_brjmp_npc_T_1; // @[Mux.scala:30:73] wire [24:0] mem_brjmp_npc_a = _mem_brjmp_npc_a_T[63:39]; // @[Core.scala:65:{16,23}] wire _mem_brjmp_npc_msb_T = mem_brjmp_npc_a == 25'h0; // @[Core.scala:65:23, :66:21] wire _mem_brjmp_npc_msb_T_1 = &mem_brjmp_npc_a; // @[Core.scala:65:23, :66:34] wire _mem_brjmp_npc_msb_T_2 = _mem_brjmp_npc_msb_T | _mem_brjmp_npc_msb_T_1; // @[Core.scala:66:{21,29,34}] wire _mem_brjmp_npc_msb_T_3 = _mem_brjmp_uop_WIRE_bits_wdata_bits[39]; // @[Mux.scala:30:73] wire _mem_brjmp_npc_msb_T_4 = _mem_brjmp_uop_WIRE_bits_wdata_bits[38]; // @[Mux.scala:30:73] wire _mem_brjmp_npc_msb_T_5 = ~_mem_brjmp_npc_msb_T_4; // @[Core.scala:66:{59,62}] wire mem_brjmp_npc_msb = _mem_brjmp_npc_msb_T_2 ? _mem_brjmp_npc_msb_T_3 : _mem_brjmp_npc_msb_T_5; // @[Core.scala:66:{18,29,46,59}] wire [38:0] _mem_brjmp_npc_T_3 = _mem_brjmp_uop_WIRE_bits_wdata_bits[38:0]; // @[Mux.scala:30:73] wire [39:0] _mem_brjmp_npc_T_4 = {mem_brjmp_npc_msb, _mem_brjmp_npc_T_3}; // @[Core.scala:66:18, :67:{8,16}] wire [39:0] _mem_brjmp_npc_T_5 = _mem_brjmp_npc_T_4; // @[Core.scala:67:8, :652:78] wire [39:0] _mem_brjmp_npc_T_6 = _mem_brjmp_npc_T_2 ? _mem_brjmp_npc_T_5 : mem_brjmp_target; // @[Core.scala:647:50, :651:{27,48}, :652:78] wire [39:0] _mem_brjmp_npc_T_7 = _mem_brjmp_npc_T_6 & 40'hFFFFFFFFFE; // @[Core.scala:651:27, :653:23] wire [39:0] _mem_brjmp_npc_T_8 = _mem_brjmp_npc_T_7; // @[Core.scala:653:23] wire [39:0] mem_brjmp_npc = _mem_brjmp_npc_T_8; // @[Core.scala:653:{23,31}] wire mem_brjmp_wrong_npc = _mem_brjmp_uop_WIRE_bits_next_pc_bits != mem_brjmp_npc; // @[Mux.scala:30:73] wire _mem_brjmp_taken_T_1 = _mem_brjmp_taken_T | _mem_brjmp_uop_WIRE_bits_ctrl_jalr; // @[Mux.scala:30:73] assign mem_brjmp_taken = _mem_brjmp_taken_T_1 | _mem_brjmp_uop_WIRE_bits_ctrl_jal; // @[Mux.scala:30:73] assign io_imem_bht_update_bits_taken_0 = mem_brjmp_taken; // @[Core.scala:25:7, :655:95] wire _mem_brjmp_mispredict_taken_T = ~_mem_brjmp_uop_WIRE_bits_next_pc_valid; // @[Mux.scala:30:73] wire _mem_brjmp_mispredict_taken_T_1 = _mem_brjmp_mispredict_taken_T | mem_brjmp_wrong_npc; // @[Core.scala:654:56, :656:{56,85}] wire mem_brjmp_mispredict_taken = mem_brjmp_taken & _mem_brjmp_mispredict_taken_T_1; // @[Core.scala:655:95, :656:{52,85}] wire _mem_brjmp_mispredict_not_taken_T = ~_mem_brjmp_uop_WIRE_bits_taken; // @[Mux.scala:30:73] wire _mem_brjmp_mispredict_not_taken_T_1 = _mem_brjmp_uop_WIRE_bits_ctrl_branch & _mem_brjmp_mispredict_not_taken_T; // @[Mux.scala:30:73] wire _mem_brjmp_mispredict_not_taken_T_2 = _mem_brjmp_uop_WIRE_bits_ctrl_branch | _mem_brjmp_uop_WIRE_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_brjmp_mispredict_not_taken_T_3 = _mem_brjmp_mispredict_not_taken_T_2 | _mem_brjmp_uop_WIRE_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_brjmp_mispredict_not_taken_T_4 = ~_mem_brjmp_mispredict_not_taken_T_3; // @[Core.scala:657:92] wire _mem_brjmp_mispredict_not_taken_T_5 = _mem_brjmp_mispredict_not_taken_T_1 | _mem_brjmp_mispredict_not_taken_T_4; // @[Core.scala:657:{64,89,92}] wire mem_brjmp_mispredict_not_taken = _mem_brjmp_mispredict_not_taken_T_5 & _mem_brjmp_uop_WIRE_bits_next_pc_valid; // @[Mux.scala:30:73] assign mem_brjmp_mispredict = mem_brjmp_mispredict_taken | mem_brjmp_mispredict_not_taken; // @[Core.scala:656:52, :657:112, :658:57] assign io_imem_btb_update_bits_mispredict_0 = mem_brjmp_mispredict; // @[Core.scala:25:7, :658:57] assign io_imem_bht_update_bits_mispredict_0 = mem_brjmp_mispredict; // @[Core.scala:25:7, :658:57] wire mem_brjmp_sfb = mem_uops_reg_0_bits_sfb_br & mem_uops_reg_1_valid; // @[Core.scala:72:25, :659:51] wire _io_imem_btb_update_valid_T = ~mem_brjmp_sfb; // @[Core.scala:659:51, :661:48] assign _io_imem_btb_update_valid_T_1 = mem_brjmp_val & _io_imem_btb_update_valid_T; // @[Core.scala:642:44, :661:{45,48}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_1; // @[Core.scala:25:7, :661:45] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T_1[0]; // @[Core.scala:665:72] wire _io_imem_btb_update_bits_cfiType_T_3 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_2; // @[Core.scala:665:{29,53,72}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[Core.scala:666:{51,60}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[Core.scala:666:60] wire _io_imem_btb_update_bits_cfiType_T_7 = _mem_brjmp_uop_WIRE_bits_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[Mux.scala:30:73] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[Core.scala:667:{8,28}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[Core.scala:666:{8,29}, :667:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_3 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[Core.scala:665:{8,53}, :666:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[Core.scala:25:7, :665:8] wire [38:0] _mem_brjmp_bridx_T = _mem_brjmp_uop_WIRE_bits_pc[39:1]; // @[Mux.scala:30:73] wire [1:0] mem_brjmp_bridx = _mem_brjmp_bridx_T[1:0]; // @[Core.scala:670:{43,48}] wire _mem_brjmp_is_last_over_edge_T = &mem_brjmp_bridx; // @[Core.scala:670:48, :671:53] wire _mem_brjmp_is_last_over_edge_T_1 = ~_mem_brjmp_uop_WIRE_bits_rvc; // @[Mux.scala:30:73] wire mem_brjmp_is_last_over_edge = _mem_brjmp_is_last_over_edge_T & _mem_brjmp_is_last_over_edge_T_1; // @[Core.scala:671:{53,74,77}] assign io_imem_btb_update_bits_target_0 = mem_brjmp_npc[38:0]; // @[Core.scala:25:7, :653:31, :672:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {mem_brjmp_is_last_over_edge, 1'h0}; // @[Core.scala:671:74, :673:58] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, _mem_brjmp_uop_WIRE_bits_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[Mux.scala:30:73] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[Core.scala:673:53] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[Core.scala:25:7, :673:{33,53}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[Core.scala:25:7, :674:36] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:3], 3'h7}; // @[Core.scala:674:{36,67}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[Core.scala:674:{34,67}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[Core.scala:25:7, :674:34] assign io_imem_btb_update_bits_prediction_entry_0 = _mem_brjmp_uop_WIRE_bits_btb_resp_valid ? _mem_brjmp_uop_WIRE_bits_btb_resp_bits_entry : 6'h20; // @[Mux.scala:30:73] wire _io_imem_bht_update_valid_T = ~mem_brjmp_sfb; // @[Core.scala:659:51, :661:48, :681:48] assign _io_imem_bht_update_valid_T_1 = mem_brjmp_val & _io_imem_bht_update_valid_T; // @[Core.scala:642:44, :681:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[Core.scala:25:7, :681:45] assign _io_imem_ras_update_valid_T = mem_brjmp_call & mem_brjmp_val; // @[Core.scala:642:44, :645:68, :688:46] assign io_imem_ras_update_valid_0 = _io_imem_ras_update_valid_T; // @[Core.scala:25:7, :688:46] wire _GEN_105 = _mem_brjmp_uop_WIRE_bits_ras_head == 3'h5; // @[Mux.scala:30:73] wire _io_imem_ras_update_bits_head_T; // @[Core.scala:689:62] assign _io_imem_ras_update_bits_head_T = _GEN_105; // @[Core.scala:689:62] wire _io_imem_redirect_ras_head_T; // @[Core.scala:693:79] assign _io_imem_redirect_ras_head_T = _GEN_105; // @[Core.scala:689:62, :693:79] wire [3:0] _GEN_106 = {1'h0, _mem_brjmp_uop_WIRE_bits_ras_head}; // @[Mux.scala:30:73] wire [3:0] _GEN_107 = _GEN_106 + 4'h1; // @[Core.scala:689:120] wire [3:0] _io_imem_ras_update_bits_head_T_1; // @[Core.scala:689:120] assign _io_imem_ras_update_bits_head_T_1 = _GEN_107; // @[Core.scala:689:120] wire [3:0] _io_imem_redirect_ras_head_T_1; // @[Core.scala:693:137] assign _io_imem_redirect_ras_head_T_1 = _GEN_107; // @[Core.scala:689:120, :693:137] wire [2:0] _io_imem_ras_update_bits_head_T_2 = _io_imem_ras_update_bits_head_T_1[2:0]; // @[Core.scala:689:120] assign _io_imem_ras_update_bits_head_T_3 = _io_imem_ras_update_bits_head_T ? 3'h0 : _io_imem_ras_update_bits_head_T_2; // @[Core.scala:689:{38,62,120}] assign io_imem_ras_update_bits_head_0 = _io_imem_ras_update_bits_head_T_3; // @[Core.scala:25:7, :689:38] assign io_imem_ras_update_bits_addr_0 = _mem_brjmp_uop_WIRE_bits_wdata_bits[39:0]; // @[Mux.scala:30:73] wire [2:0] _io_imem_redirect_ras_head_T_2 = _io_imem_redirect_ras_head_T_1[2:0]; // @[Core.scala:693:137] wire [2:0] _io_imem_redirect_ras_head_T_3 = _io_imem_redirect_ras_head_T ? 3'h0 : _io_imem_redirect_ras_head_T_2; // @[Core.scala:693:{55,79,137}] wire _io_imem_redirect_ras_head_T_4 = _mem_brjmp_uop_WIRE_bits_ras_head == 3'h0; // @[Mux.scala:30:73] wire [3:0] _io_imem_redirect_ras_head_T_5 = _GEN_106 - 4'h1; // @[Core.scala:689:120, :694:109] wire [2:0] _io_imem_redirect_ras_head_T_6 = _io_imem_redirect_ras_head_T_5[2:0]; // @[Core.scala:694:109] wire [2:0] _io_imem_redirect_ras_head_T_7 = _io_imem_redirect_ras_head_T_4 ? 3'h5 : _io_imem_redirect_ras_head_T_6; // @[Core.scala:694:{27,51,109}] wire [2:0] _io_imem_redirect_ras_head_T_8 = mem_brjmp_ret ? _io_imem_redirect_ras_head_T_7 : _mem_brjmp_uop_WIRE_bits_ras_head; // @[Mux.scala:30:73] wire [2:0] _io_imem_redirect_ras_head_T_9 = mem_brjmp_call ? _io_imem_redirect_ras_head_T_3 : _io_imem_redirect_ras_head_T_8; // @[Core.scala:645:68, :693:{35,55}, :694:8] wire _T_150 = mem_brjmp_val & mem_brjmp_mispredict & ~mem_brjmp_sfb; // @[Core.scala:642:44, :658:57, :659:51, :661:48, :696:{23,47}] wire mem_dmem_oh_0 = mem_uops_reg_0_valid & mem_uops_reg_0_bits_ctrl_mem; // @[Core.scala:72:25, :702:51] wire mem_dmem_oh_1 = mem_uops_reg_1_valid & mem_uops_reg_1_bits_ctrl_mem; // @[Core.scala:72:25, :702:51] wire _mem_dmem_uop_WIRE_115; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_WIRE_inst; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_WIRE_raw_inst; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_WIRE_pc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_edge_inst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_legal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_fp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_branch; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_jal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_ctrl_sel_imm; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_ctrl_alu_fn; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_mul; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_ctrl_csr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_fence; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_amo; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_dp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_rvc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_sets_vcfg; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_sfb_br; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_sfb_shadow; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_ras_head; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_xcpt; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_needs_replay; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_rs1_data; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_rs2_data; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_rs3_data; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_uses_memalu; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_uses_latealu; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_fra1; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_fra2; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_fra3; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_fexc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_mem_size; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_flush_pipe; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_legal; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_fp; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rocc; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_branch; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_jal; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_jalr; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] mem_dmem_uop_bits_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] mem_dmem_uop_bits_ctrl_sel_imm; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_ctrl_alu_fn; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_ctrl_mem_cmd; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_wfd; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_mul; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_div; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] mem_dmem_uop_bits_ctrl_csr; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_fence; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_amo; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_dp; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_ctrl_vec; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire [7:0] mem_dmem_uop_bits_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] mem_dmem_uop_bits_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] mem_dmem_uop_bits_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] mem_dmem_uop_bits_btb_resp_bits_entry; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_btb_resp_valid; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] mem_dmem_uop_bits_next_pc_bits; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_wdata_valid; // @[Mux.scala:30:73] wire [63:0] mem_dmem_uop_bits_wdata_bits; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_ldst; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_wen; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_ren1; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_ren2; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_ren3; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_swap12; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fdivin_typeTagOut; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_fromint; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_toint; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_fma; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_div; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_wflags; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] mem_dmem_uop_bits_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] mem_dmem_uop_bits_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] mem_dmem_uop_bits_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] mem_dmem_uop_bits_fdivin_in3; // @[Mux.scala:30:73] wire [31:0] mem_dmem_uop_bits_inst; // @[Mux.scala:30:73] wire [31:0] mem_dmem_uop_bits_raw_inst; // @[Mux.scala:30:73] wire [39:0] mem_dmem_uop_bits_pc; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_edge_inst; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_rvc; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_sets_vcfg; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_sfb_br; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_sfb_shadow; // @[Mux.scala:30:73] wire [2:0] mem_dmem_uop_bits_ras_head; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_taken; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_xcpt; // @[Mux.scala:30:73] wire [63:0] mem_dmem_uop_bits_xcpt_cause; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_needs_replay; // @[Mux.scala:30:73] wire [63:0] mem_dmem_uop_bits_rs1_data; // @[Mux.scala:30:73] wire [63:0] mem_dmem_uop_bits_rs2_data; // @[Mux.scala:30:73] wire [63:0] mem_dmem_uop_bits_rs3_data; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_uses_memalu; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_uses_latealu; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_fra1; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_fra2; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_fra3; // @[Mux.scala:30:73] wire [4:0] mem_dmem_uop_bits_fexc; // @[Mux.scala:30:73] wire [1:0] mem_dmem_uop_bits_mem_size; // @[Mux.scala:30:73] wire mem_dmem_uop_bits_flush_pipe; // @[Mux.scala:30:73] wire mem_dmem_uop_valid; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_WIRE_114; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_inst = _mem_dmem_uop_WIRE_inst; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_WIRE_113; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_raw_inst = _mem_dmem_uop_WIRE_raw_inst; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_WIRE_112; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_pc = _mem_dmem_uop_WIRE_pc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_111; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_edge_inst = _mem_dmem_uop_WIRE_edge_inst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_legal; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_legal = _mem_dmem_uop_WIRE_ctrl_legal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_fp; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_fp = _mem_dmem_uop_WIRE_ctrl_fp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rocc; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rocc = _mem_dmem_uop_WIRE_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_branch; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_branch = _mem_dmem_uop_WIRE_ctrl_branch; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_jal; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_jal = _mem_dmem_uop_WIRE_ctrl_jal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_jalr; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_jalr = _mem_dmem_uop_WIRE_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rxs2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rxs2 = _mem_dmem_uop_WIRE_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rxs1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rxs1 = _mem_dmem_uop_WIRE_ctrl_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_82_sel_alu2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_sel_alu2 = _mem_dmem_uop_WIRE_ctrl_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_82_sel_alu1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_sel_alu1 = _mem_dmem_uop_WIRE_ctrl_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_82_sel_imm; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_sel_imm = _mem_dmem_uop_WIRE_ctrl_sel_imm; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_alu_dw; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_alu_dw = _mem_dmem_uop_WIRE_ctrl_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_82_alu_fn; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_alu_fn = _mem_dmem_uop_WIRE_ctrl_alu_fn; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_mem; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_mem = _mem_dmem_uop_WIRE_ctrl_mem; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_82_mem_cmd; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_mem_cmd = _mem_dmem_uop_WIRE_ctrl_mem_cmd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rfs1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rfs1 = _mem_dmem_uop_WIRE_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rfs2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rfs2 = _mem_dmem_uop_WIRE_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_rfs3; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_rfs3 = _mem_dmem_uop_WIRE_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_wfd; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_wfd = _mem_dmem_uop_WIRE_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_mul; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_mul = _mem_dmem_uop_WIRE_ctrl_mul; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_div; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_div = _mem_dmem_uop_WIRE_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_wxd; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_wxd = _mem_dmem_uop_WIRE_ctrl_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_82_csr; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_csr = _mem_dmem_uop_WIRE_ctrl_csr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_fence_i; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_fence_i = _mem_dmem_uop_WIRE_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_fence; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_fence = _mem_dmem_uop_WIRE_ctrl_fence; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_amo; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_amo = _mem_dmem_uop_WIRE_ctrl_amo; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_dp; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_dp = _mem_dmem_uop_WIRE_ctrl_dp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_82_vec; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ctrl_vec = _mem_dmem_uop_WIRE_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_ldst; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_ldst = _mem_dmem_uop_WIRE_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_wen; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_wen = _mem_dmem_uop_WIRE_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_ren1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_ren1 = _mem_dmem_uop_WIRE_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_ren2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_ren2 = _mem_dmem_uop_WIRE_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_ren3; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_ren3 = _mem_dmem_uop_WIRE_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_swap12; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_swap12 = _mem_dmem_uop_WIRE_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_swap23; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_swap23 = _mem_dmem_uop_WIRE_fp_ctrl_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_64_typeTagIn; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_typeTagIn = _mem_dmem_uop_WIRE_fp_ctrl_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_64_typeTagOut; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_typeTagOut = _mem_dmem_uop_WIRE_fp_ctrl_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_fromint; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_fromint = _mem_dmem_uop_WIRE_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_toint; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_toint = _mem_dmem_uop_WIRE_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_fastpipe; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_fastpipe = _mem_dmem_uop_WIRE_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_fma; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_fma = _mem_dmem_uop_WIRE_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_div; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_div = _mem_dmem_uop_WIRE_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_sqrt; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_sqrt = _mem_dmem_uop_WIRE_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_wflags; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_wflags = _mem_dmem_uop_WIRE_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_64_vec; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fp_ctrl_vec = _mem_dmem_uop_WIRE_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_63; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_rvc = _mem_dmem_uop_WIRE_rvc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_62; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_sets_vcfg = _mem_dmem_uop_WIRE_sets_vcfg; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_50_valid; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_valid = _mem_dmem_uop_WIRE_btb_resp_valid; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_cfiType = _mem_dmem_uop_WIRE_btb_resp_bits_cfiType; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_taken = _mem_dmem_uop_WIRE_btb_resp_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_mask = _mem_dmem_uop_WIRE_btb_resp_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_bridx = _mem_dmem_uop_WIRE_btb_resp_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_target = _mem_dmem_uop_WIRE_btb_resp_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_entry = _mem_dmem_uop_WIRE_btb_resp_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_bht_history = _mem_dmem_uop_WIRE_btb_resp_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_btb_resp_bits_bht_value = _mem_dmem_uop_WIRE_btb_resp_bits_bht_value; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_49; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_sfb_br = _mem_dmem_uop_WIRE_sfb_br; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_48; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_sfb_shadow = _mem_dmem_uop_WIRE_sfb_shadow; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_45_valid; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_next_pc_valid = _mem_dmem_uop_WIRE_next_pc_valid; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_WIRE_45_bits; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_next_pc_bits = _mem_dmem_uop_WIRE_next_pc_bits; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_44; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_ras_head = _mem_dmem_uop_WIRE_ras_head; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_43; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_taken = _mem_dmem_uop_WIRE_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_42; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_xcpt = _mem_dmem_uop_WIRE_xcpt; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_41; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_xcpt_cause = _mem_dmem_uop_WIRE_xcpt_cause; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_40; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_needs_replay = _mem_dmem_uop_WIRE_needs_replay; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_39; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_rs1_data = _mem_dmem_uop_WIRE_rs1_data; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_38; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_rs2_data = _mem_dmem_uop_WIRE_rs2_data; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_37; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_rs3_data = _mem_dmem_uop_WIRE_rs3_data; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_36; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_uses_memalu = _mem_dmem_uop_WIRE_uses_memalu; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_35; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_uses_latealu = _mem_dmem_uop_WIRE_uses_latealu; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_32_valid; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_wdata_valid = _mem_dmem_uop_WIRE_wdata_valid; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_32_bits; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_wdata_bits = _mem_dmem_uop_WIRE_wdata_bits; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_31; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fra1 = _mem_dmem_uop_WIRE_fra1; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_30; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fra2 = _mem_dmem_uop_WIRE_fra2; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_29; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fra3 = _mem_dmem_uop_WIRE_fra3; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_28; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fexc = _mem_dmem_uop_WIRE_fexc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_ldst; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_ldst = _mem_dmem_uop_WIRE_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_wen; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_wen = _mem_dmem_uop_WIRE_fdivin_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_ren1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_ren1 = _mem_dmem_uop_WIRE_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_ren2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_ren2 = _mem_dmem_uop_WIRE_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_ren3; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_ren3 = _mem_dmem_uop_WIRE_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_swap12; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_swap12 = _mem_dmem_uop_WIRE_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_swap23; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_swap23 = _mem_dmem_uop_WIRE_fdivin_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_3_typeTagIn; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_typeTagIn = _mem_dmem_uop_WIRE_fdivin_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_3_typeTagOut; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_typeTagOut = _mem_dmem_uop_WIRE_fdivin_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_fromint; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_fromint = _mem_dmem_uop_WIRE_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_toint; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_toint = _mem_dmem_uop_WIRE_fdivin_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_fastpipe; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_fastpipe = _mem_dmem_uop_WIRE_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_fma; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_fma = _mem_dmem_uop_WIRE_fdivin_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_div; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_div = _mem_dmem_uop_WIRE_fdivin_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_sqrt; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_sqrt = _mem_dmem_uop_WIRE_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_wflags; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_wflags = _mem_dmem_uop_WIRE_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_3_vec; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_vec = _mem_dmem_uop_WIRE_fdivin_vec; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_3_rm; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_rm = _mem_dmem_uop_WIRE_fdivin_rm; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_3_fmaCmd; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_fmaCmd = _mem_dmem_uop_WIRE_fdivin_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_3_typ; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_typ = _mem_dmem_uop_WIRE_fdivin_typ; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_3_fmt; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_fmt = _mem_dmem_uop_WIRE_fdivin_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_3_in1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_in1 = _mem_dmem_uop_WIRE_fdivin_in1; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_3_in2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_in2 = _mem_dmem_uop_WIRE_fdivin_in2; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_3_in3; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_fdivin_in3 = _mem_dmem_uop_WIRE_fdivin_in3; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_2; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_mem_size = _mem_dmem_uop_WIRE_mem_size; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_1; // @[Mux.scala:30:73] assign mem_dmem_uop_bits_flush_pipe = _mem_dmem_uop_WIRE_flush_pipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T = mem_dmem_oh_0 & mem_uops_reg_0_bits_flush_pipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_1 = mem_dmem_oh_1 & mem_uops_reg_1_bits_flush_pipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_2 = _mem_dmem_uop_T | _mem_dmem_uop_T_1; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_1 = _mem_dmem_uop_T_2; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_flush_pipe = _mem_dmem_uop_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_3 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_4 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_mem_size : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_5 = _mem_dmem_uop_T_3 | _mem_dmem_uop_T_4; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_2 = _mem_dmem_uop_T_5; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_mem_size = _mem_dmem_uop_WIRE_2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_27; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_ldst = _mem_dmem_uop_WIRE_3_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_26; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_wen = _mem_dmem_uop_WIRE_3_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_25; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_ren1 = _mem_dmem_uop_WIRE_3_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_24; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_ren2 = _mem_dmem_uop_WIRE_3_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_23; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_ren3 = _mem_dmem_uop_WIRE_3_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_22; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_swap12 = _mem_dmem_uop_WIRE_3_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_21; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_swap23 = _mem_dmem_uop_WIRE_3_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_20; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_typeTagIn = _mem_dmem_uop_WIRE_3_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_19; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_typeTagOut = _mem_dmem_uop_WIRE_3_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_18; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_fromint = _mem_dmem_uop_WIRE_3_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_17; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_toint = _mem_dmem_uop_WIRE_3_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_16; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_fastpipe = _mem_dmem_uop_WIRE_3_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_15; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_fma = _mem_dmem_uop_WIRE_3_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_14; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_div = _mem_dmem_uop_WIRE_3_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_13; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_sqrt = _mem_dmem_uop_WIRE_3_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_12; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_wflags = _mem_dmem_uop_WIRE_3_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_11; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_vec = _mem_dmem_uop_WIRE_3_vec; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_10; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_rm = _mem_dmem_uop_WIRE_3_rm; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_9; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_fmaCmd = _mem_dmem_uop_WIRE_3_fmaCmd; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_8; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_typ = _mem_dmem_uop_WIRE_3_typ; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_7; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_fmt = _mem_dmem_uop_WIRE_3_fmt; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_6; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_in1 = _mem_dmem_uop_WIRE_3_in1; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_5; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_in2 = _mem_dmem_uop_WIRE_3_in2; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_WIRE_4; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fdivin_in3 = _mem_dmem_uop_WIRE_3_in3; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_6 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_7 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_in3 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_8 = _mem_dmem_uop_T_6 | _mem_dmem_uop_T_7; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_4 = _mem_dmem_uop_T_8; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_in3 = _mem_dmem_uop_WIRE_4; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_9 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_10 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_in2 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_11 = _mem_dmem_uop_T_9 | _mem_dmem_uop_T_10; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_5 = _mem_dmem_uop_T_11; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_in2 = _mem_dmem_uop_WIRE_5; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_12 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_13 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_in1 : 65'h0; // @[Mux.scala:30:73] wire [64:0] _mem_dmem_uop_T_14 = _mem_dmem_uop_T_12 | _mem_dmem_uop_T_13; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_6 = _mem_dmem_uop_T_14; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_in1 = _mem_dmem_uop_WIRE_6; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_15 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_16 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_fmt : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_17 = _mem_dmem_uop_T_15 | _mem_dmem_uop_T_16; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_7 = _mem_dmem_uop_T_17; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_fmt = _mem_dmem_uop_WIRE_7; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_18 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_19 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_typ : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_20 = _mem_dmem_uop_T_18 | _mem_dmem_uop_T_19; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_8 = _mem_dmem_uop_T_20; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_typ = _mem_dmem_uop_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_21 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_22 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_fmaCmd : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_23 = _mem_dmem_uop_T_21 | _mem_dmem_uop_T_22; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_9 = _mem_dmem_uop_T_23; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_fmaCmd = _mem_dmem_uop_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_24 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_25 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_rm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_26 = _mem_dmem_uop_T_24 | _mem_dmem_uop_T_25; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_10 = _mem_dmem_uop_T_26; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_rm = _mem_dmem_uop_WIRE_10; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_27 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_28 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_29 = _mem_dmem_uop_T_27 | _mem_dmem_uop_T_28; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_11 = _mem_dmem_uop_T_29; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_vec = _mem_dmem_uop_WIRE_11; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_30 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_31 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_32 = _mem_dmem_uop_T_30 | _mem_dmem_uop_T_31; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_12 = _mem_dmem_uop_T_32; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_wflags = _mem_dmem_uop_WIRE_12; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_33 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_34 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_35 = _mem_dmem_uop_T_33 | _mem_dmem_uop_T_34; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_13 = _mem_dmem_uop_T_35; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_sqrt = _mem_dmem_uop_WIRE_13; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_36 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_37 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_38 = _mem_dmem_uop_T_36 | _mem_dmem_uop_T_37; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_14 = _mem_dmem_uop_T_38; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_div = _mem_dmem_uop_WIRE_14; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_39 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_40 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_41 = _mem_dmem_uop_T_39 | _mem_dmem_uop_T_40; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_15 = _mem_dmem_uop_T_41; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_fma = _mem_dmem_uop_WIRE_15; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_42 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_43 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_44 = _mem_dmem_uop_T_42 | _mem_dmem_uop_T_43; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_16 = _mem_dmem_uop_T_44; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_fastpipe = _mem_dmem_uop_WIRE_16; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_45 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_46 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_47 = _mem_dmem_uop_T_45 | _mem_dmem_uop_T_46; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_17 = _mem_dmem_uop_T_47; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_toint = _mem_dmem_uop_WIRE_17; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_48 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_49 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_50 = _mem_dmem_uop_T_48 | _mem_dmem_uop_T_49; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_18 = _mem_dmem_uop_T_50; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_fromint = _mem_dmem_uop_WIRE_18; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_51 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_52 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_53 = _mem_dmem_uop_T_51 | _mem_dmem_uop_T_52; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_19 = _mem_dmem_uop_T_53; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_typeTagOut = _mem_dmem_uop_WIRE_19; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_54 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_55 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fdivin_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_56 = _mem_dmem_uop_T_54 | _mem_dmem_uop_T_55; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_20 = _mem_dmem_uop_T_56; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_typeTagIn = _mem_dmem_uop_WIRE_20; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_57 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_58 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_swap23; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_59 = _mem_dmem_uop_T_57 | _mem_dmem_uop_T_58; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_21 = _mem_dmem_uop_T_59; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_swap23 = _mem_dmem_uop_WIRE_21; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_60 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_61 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_62 = _mem_dmem_uop_T_60 | _mem_dmem_uop_T_61; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_22 = _mem_dmem_uop_T_62; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_swap12 = _mem_dmem_uop_WIRE_22; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_63 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_64 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_65 = _mem_dmem_uop_T_63 | _mem_dmem_uop_T_64; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_23 = _mem_dmem_uop_T_65; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_ren3 = _mem_dmem_uop_WIRE_23; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_66 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_67 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_68 = _mem_dmem_uop_T_66 | _mem_dmem_uop_T_67; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_24 = _mem_dmem_uop_T_68; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_ren2 = _mem_dmem_uop_WIRE_24; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_69 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_70 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_71 = _mem_dmem_uop_T_69 | _mem_dmem_uop_T_70; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_25 = _mem_dmem_uop_T_71; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_ren1 = _mem_dmem_uop_WIRE_25; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_72 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_73 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_74 = _mem_dmem_uop_T_72 | _mem_dmem_uop_T_73; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_26 = _mem_dmem_uop_T_74; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_wen = _mem_dmem_uop_WIRE_26; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_75 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_76 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fdivin_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_77 = _mem_dmem_uop_T_75 | _mem_dmem_uop_T_76; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_27 = _mem_dmem_uop_T_77; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_3_ldst = _mem_dmem_uop_WIRE_27; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_78 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_79 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fexc : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_80 = _mem_dmem_uop_T_78 | _mem_dmem_uop_T_79; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_28 = _mem_dmem_uop_T_80; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fexc = _mem_dmem_uop_WIRE_28; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_81 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_82 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fra3 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_83 = _mem_dmem_uop_T_81 | _mem_dmem_uop_T_82; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_29 = _mem_dmem_uop_T_83; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fra3 = _mem_dmem_uop_WIRE_29; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_84 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_85 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fra2 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_86 = _mem_dmem_uop_T_84 | _mem_dmem_uop_T_85; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_30 = _mem_dmem_uop_T_86; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fra2 = _mem_dmem_uop_WIRE_30; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_87 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_88 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fra1 : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_89 = _mem_dmem_uop_T_87 | _mem_dmem_uop_T_88; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_31 = _mem_dmem_uop_T_89; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fra1 = _mem_dmem_uop_WIRE_31; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_34; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_wdata_valid = _mem_dmem_uop_WIRE_32_valid; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_WIRE_33; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_wdata_bits = _mem_dmem_uop_WIRE_32_bits; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_90 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_91 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_wdata_bits : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_92 = _mem_dmem_uop_T_90 | _mem_dmem_uop_T_91; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_33 = _mem_dmem_uop_T_92; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_32_bits = _mem_dmem_uop_WIRE_33; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_93 = mem_dmem_oh_0 & mem_uops_reg_0_bits_wdata_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_94 = mem_dmem_oh_1 & mem_uops_reg_1_bits_wdata_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_95 = _mem_dmem_uop_T_93 | _mem_dmem_uop_T_94; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_34 = _mem_dmem_uop_T_95; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_32_valid = _mem_dmem_uop_WIRE_34; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_96 = mem_dmem_oh_0 & mem_uops_reg_0_bits_uses_latealu; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_97 = mem_dmem_oh_1 & mem_uops_reg_1_bits_uses_latealu; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_98 = _mem_dmem_uop_T_96 | _mem_dmem_uop_T_97; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_35 = _mem_dmem_uop_T_98; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_uses_latealu = _mem_dmem_uop_WIRE_35; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_99 = mem_dmem_oh_0 & mem_uops_reg_0_bits_uses_memalu; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_100 = mem_dmem_oh_1 & mem_uops_reg_1_bits_uses_memalu; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_101 = _mem_dmem_uop_T_99 | _mem_dmem_uop_T_100; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_36 = _mem_dmem_uop_T_101; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_uses_memalu = _mem_dmem_uop_WIRE_36; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_102 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_103 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_rs3_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_104 = _mem_dmem_uop_T_102 | _mem_dmem_uop_T_103; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_37 = _mem_dmem_uop_T_104; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_rs3_data = _mem_dmem_uop_WIRE_37; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_105 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_106 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_rs2_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_107 = _mem_dmem_uop_T_105 | _mem_dmem_uop_T_106; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_38 = _mem_dmem_uop_T_107; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_rs2_data = _mem_dmem_uop_WIRE_38; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_108 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_109 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_rs1_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_110 = _mem_dmem_uop_T_108 | _mem_dmem_uop_T_109; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_39 = _mem_dmem_uop_T_110; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_rs1_data = _mem_dmem_uop_WIRE_39; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_111 = mem_dmem_oh_0 & mem_uops_reg_0_bits_needs_replay; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_112 = mem_dmem_oh_1 & mem_uops_reg_1_bits_needs_replay; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_113 = _mem_dmem_uop_T_111 | _mem_dmem_uop_T_112; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_40 = _mem_dmem_uop_T_113; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_needs_replay = _mem_dmem_uop_WIRE_40; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_114 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_115 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_xcpt_cause : 64'h0; // @[Mux.scala:30:73] wire [63:0] _mem_dmem_uop_T_116 = _mem_dmem_uop_T_114 | _mem_dmem_uop_T_115; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_41 = _mem_dmem_uop_T_116; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_xcpt_cause = _mem_dmem_uop_WIRE_41; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_117 = mem_dmem_oh_0 & mem_uops_reg_0_bits_xcpt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_118 = mem_dmem_oh_1 & mem_uops_reg_1_bits_xcpt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_119 = _mem_dmem_uop_T_117 | _mem_dmem_uop_T_118; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_42 = _mem_dmem_uop_T_119; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_xcpt = _mem_dmem_uop_WIRE_42; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_120 = mem_dmem_oh_0 & mem_uops_reg_0_bits_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_121 = mem_dmem_oh_1 & mem_uops_reg_1_bits_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_122 = _mem_dmem_uop_T_120 | _mem_dmem_uop_T_121; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_43 = _mem_dmem_uop_T_122; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_taken = _mem_dmem_uop_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_123 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_124 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ras_head : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_125 = _mem_dmem_uop_T_123 | _mem_dmem_uop_T_124; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_44 = _mem_dmem_uop_T_125; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ras_head = _mem_dmem_uop_WIRE_44; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_47; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_next_pc_valid = _mem_dmem_uop_WIRE_45_valid; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_WIRE_46; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_next_pc_bits = _mem_dmem_uop_WIRE_45_bits; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_126 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_127 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_next_pc_bits : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_128 = _mem_dmem_uop_T_126 | _mem_dmem_uop_T_127; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_46 = _mem_dmem_uop_T_128; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_45_bits = _mem_dmem_uop_WIRE_46; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_129 = mem_dmem_oh_0 & mem_uops_reg_0_bits_next_pc_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_130 = mem_dmem_oh_1 & mem_uops_reg_1_bits_next_pc_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_131 = _mem_dmem_uop_T_129 | _mem_dmem_uop_T_130; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_47 = _mem_dmem_uop_T_131; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_45_valid = _mem_dmem_uop_WIRE_47; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_132 = mem_dmem_oh_0 & mem_uops_reg_0_bits_sfb_shadow; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_133 = mem_dmem_oh_1 & mem_uops_reg_1_bits_sfb_shadow; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_134 = _mem_dmem_uop_T_132 | _mem_dmem_uop_T_133; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_48 = _mem_dmem_uop_T_134; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_sfb_shadow = _mem_dmem_uop_WIRE_48; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_135 = mem_dmem_oh_0 & mem_uops_reg_0_bits_sfb_br; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_136 = mem_dmem_oh_1 & mem_uops_reg_1_bits_sfb_br; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_137 = _mem_dmem_uop_T_135 | _mem_dmem_uop_T_136; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_49 = _mem_dmem_uop_T_137; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_sfb_br = _mem_dmem_uop_WIRE_49; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_61; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_valid = _mem_dmem_uop_WIRE_50_valid; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_cfiType = _mem_dmem_uop_WIRE_50_bits_cfiType; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_51_taken; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_taken = _mem_dmem_uop_WIRE_50_bits_taken; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_WIRE_51_mask; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_mask = _mem_dmem_uop_WIRE_50_bits_mask; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_51_bridx; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_bridx = _mem_dmem_uop_WIRE_50_bits_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_WIRE_51_target; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_target = _mem_dmem_uop_WIRE_50_bits_target; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_WIRE_51_entry; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_entry = _mem_dmem_uop_WIRE_50_bits_entry; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_bht_history = _mem_dmem_uop_WIRE_50_bits_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_btb_resp_bits_bht_value = _mem_dmem_uop_WIRE_50_bits_bht_value; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_60; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_cfiType = _mem_dmem_uop_WIRE_51_cfiType; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_59; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_taken = _mem_dmem_uop_WIRE_51_taken; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_WIRE_58; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_mask = _mem_dmem_uop_WIRE_51_mask; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_57; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_bridx = _mem_dmem_uop_WIRE_51_bridx; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_WIRE_56; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_target = _mem_dmem_uop_WIRE_51_target; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_WIRE_55; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_entry = _mem_dmem_uop_WIRE_51_entry; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_WIRE_52_history; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_bht_history = _mem_dmem_uop_WIRE_51_bht_history; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_52_value; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_bits_bht_value = _mem_dmem_uop_WIRE_51_bht_value; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_WIRE_54; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_bht_history = _mem_dmem_uop_WIRE_52_history; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_53; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_bht_value = _mem_dmem_uop_WIRE_52_value; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_138 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_139 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bht_value : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_140 = _mem_dmem_uop_T_138 | _mem_dmem_uop_T_139; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_53 = _mem_dmem_uop_T_140; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_52_value = _mem_dmem_uop_WIRE_53; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_T_141 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_T_142 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bht_history : 8'h0; // @[Mux.scala:30:73] wire [7:0] _mem_dmem_uop_T_143 = _mem_dmem_uop_T_141 | _mem_dmem_uop_T_142; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_54 = _mem_dmem_uop_T_143; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_52_history = _mem_dmem_uop_WIRE_54; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_T_144 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_T_145 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_entry : 6'h0; // @[Mux.scala:30:73] wire [5:0] _mem_dmem_uop_T_146 = _mem_dmem_uop_T_144 | _mem_dmem_uop_T_145; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_55 = _mem_dmem_uop_T_146; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_entry = _mem_dmem_uop_WIRE_55; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_T_147 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_T_148 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_target : 39'h0; // @[Mux.scala:30:73] wire [38:0] _mem_dmem_uop_T_149 = _mem_dmem_uop_T_147 | _mem_dmem_uop_T_148; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_56 = _mem_dmem_uop_T_149; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_target = _mem_dmem_uop_WIRE_56; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_150 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_151 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_bridx : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_152 = _mem_dmem_uop_T_150 | _mem_dmem_uop_T_151; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_57 = _mem_dmem_uop_T_152; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_bridx = _mem_dmem_uop_WIRE_57; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_T_153 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_T_154 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_mask : 4'h0; // @[Mux.scala:30:73] wire [3:0] _mem_dmem_uop_T_155 = _mem_dmem_uop_T_153 | _mem_dmem_uop_T_154; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_58 = _mem_dmem_uop_T_155; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_mask = _mem_dmem_uop_WIRE_58; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_156 = mem_dmem_oh_0 & mem_uops_reg_0_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_157 = mem_dmem_oh_1 & mem_uops_reg_1_bits_btb_resp_bits_taken; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_158 = _mem_dmem_uop_T_156 | _mem_dmem_uop_T_157; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_59 = _mem_dmem_uop_T_158; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_taken = _mem_dmem_uop_WIRE_59; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_159 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_160 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_btb_resp_bits_cfiType : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_161 = _mem_dmem_uop_T_159 | _mem_dmem_uop_T_160; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_60 = _mem_dmem_uop_T_161; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_51_cfiType = _mem_dmem_uop_WIRE_60; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_162 = mem_dmem_oh_0 & mem_uops_reg_0_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_163 = mem_dmem_oh_1 & mem_uops_reg_1_bits_btb_resp_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_164 = _mem_dmem_uop_T_162 | _mem_dmem_uop_T_163; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_61 = _mem_dmem_uop_T_164; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_50_valid = _mem_dmem_uop_WIRE_61; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_165 = mem_dmem_oh_0 & mem_uops_reg_0_bits_sets_vcfg; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_166 = mem_dmem_oh_1 & mem_uops_reg_1_bits_sets_vcfg; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_167 = _mem_dmem_uop_T_165 | _mem_dmem_uop_T_166; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_62 = _mem_dmem_uop_T_167; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_sets_vcfg = _mem_dmem_uop_WIRE_62; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_168 = mem_dmem_oh_0 & mem_uops_reg_0_bits_rvc; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_169 = mem_dmem_oh_1 & mem_uops_reg_1_bits_rvc; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_170 = _mem_dmem_uop_T_168 | _mem_dmem_uop_T_169; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_63 = _mem_dmem_uop_T_170; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_rvc = _mem_dmem_uop_WIRE_63; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_81; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_ldst = _mem_dmem_uop_WIRE_64_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_80; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_wen = _mem_dmem_uop_WIRE_64_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_79; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_ren1 = _mem_dmem_uop_WIRE_64_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_78; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_ren2 = _mem_dmem_uop_WIRE_64_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_77; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_ren3 = _mem_dmem_uop_WIRE_64_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_76; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_swap12 = _mem_dmem_uop_WIRE_64_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_75; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_swap23 = _mem_dmem_uop_WIRE_64_swap23; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_74; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_typeTagIn = _mem_dmem_uop_WIRE_64_typeTagIn; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_73; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_typeTagOut = _mem_dmem_uop_WIRE_64_typeTagOut; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_72; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_fromint = _mem_dmem_uop_WIRE_64_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_71; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_toint = _mem_dmem_uop_WIRE_64_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_70; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_fastpipe = _mem_dmem_uop_WIRE_64_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_69; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_fma = _mem_dmem_uop_WIRE_64_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_68; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_div = _mem_dmem_uop_WIRE_64_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_67; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_sqrt = _mem_dmem_uop_WIRE_64_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_66; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_wflags = _mem_dmem_uop_WIRE_64_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_65; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_fp_ctrl_vec = _mem_dmem_uop_WIRE_64_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_171 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_172 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_173 = _mem_dmem_uop_T_171 | _mem_dmem_uop_T_172; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_65 = _mem_dmem_uop_T_173; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_vec = _mem_dmem_uop_WIRE_65; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_174 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_175 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_wflags; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_176 = _mem_dmem_uop_T_174 | _mem_dmem_uop_T_175; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_66 = _mem_dmem_uop_T_176; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_wflags = _mem_dmem_uop_WIRE_66; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_177 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_178 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_sqrt; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_179 = _mem_dmem_uop_T_177 | _mem_dmem_uop_T_178; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_67 = _mem_dmem_uop_T_179; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_sqrt = _mem_dmem_uop_WIRE_67; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_180 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_181 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_182 = _mem_dmem_uop_T_180 | _mem_dmem_uop_T_181; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_68 = _mem_dmem_uop_T_182; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_div = _mem_dmem_uop_WIRE_68; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_183 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_184 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fma; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_185 = _mem_dmem_uop_T_183 | _mem_dmem_uop_T_184; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_69 = _mem_dmem_uop_T_185; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_fma = _mem_dmem_uop_WIRE_69; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_186 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_187 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_188 = _mem_dmem_uop_T_186 | _mem_dmem_uop_T_187; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_70 = _mem_dmem_uop_T_188; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_fastpipe = _mem_dmem_uop_WIRE_70; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_189 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_190 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_toint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_191 = _mem_dmem_uop_T_189 | _mem_dmem_uop_T_190; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_71 = _mem_dmem_uop_T_191; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_toint = _mem_dmem_uop_WIRE_71; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_192 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_193 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_fromint; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_194 = _mem_dmem_uop_T_192 | _mem_dmem_uop_T_193; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_72 = _mem_dmem_uop_T_194; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_fromint = _mem_dmem_uop_WIRE_72; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_195 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_196 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fp_ctrl_typeTagOut : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_197 = _mem_dmem_uop_T_195 | _mem_dmem_uop_T_196; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_73 = _mem_dmem_uop_T_197; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_typeTagOut = _mem_dmem_uop_WIRE_73; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_198 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_199 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_fp_ctrl_typeTagIn : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_200 = _mem_dmem_uop_T_198 | _mem_dmem_uop_T_199; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_74 = _mem_dmem_uop_T_200; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_typeTagIn = _mem_dmem_uop_WIRE_74; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_201 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_202 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_swap23; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_203 = _mem_dmem_uop_T_201 | _mem_dmem_uop_T_202; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_75 = _mem_dmem_uop_T_203; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_swap23 = _mem_dmem_uop_WIRE_75; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_204 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_205 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_swap12; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_206 = _mem_dmem_uop_T_204 | _mem_dmem_uop_T_205; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_76 = _mem_dmem_uop_T_206; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_swap12 = _mem_dmem_uop_WIRE_76; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_207 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_208 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_209 = _mem_dmem_uop_T_207 | _mem_dmem_uop_T_208; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_77 = _mem_dmem_uop_T_209; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_ren3 = _mem_dmem_uop_WIRE_77; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_210 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_211 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_212 = _mem_dmem_uop_T_210 | _mem_dmem_uop_T_211; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_78 = _mem_dmem_uop_T_212; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_ren2 = _mem_dmem_uop_WIRE_78; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_213 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_214 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ren1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_215 = _mem_dmem_uop_T_213 | _mem_dmem_uop_T_214; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_79 = _mem_dmem_uop_T_215; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_ren1 = _mem_dmem_uop_WIRE_79; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_216 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_217 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_wen; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_218 = _mem_dmem_uop_T_216 | _mem_dmem_uop_T_217; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_80 = _mem_dmem_uop_T_218; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_wen = _mem_dmem_uop_WIRE_80; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_219 = mem_dmem_oh_0 & mem_uops_reg_0_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_220 = mem_dmem_oh_1 & mem_uops_reg_1_bits_fp_ctrl_ldst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_221 = _mem_dmem_uop_T_219 | _mem_dmem_uop_T_220; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_81 = _mem_dmem_uop_T_221; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_64_ldst = _mem_dmem_uop_WIRE_81; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_110; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_legal = _mem_dmem_uop_WIRE_82_legal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_109; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_fp = _mem_dmem_uop_WIRE_82_fp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_108; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rocc = _mem_dmem_uop_WIRE_82_rocc; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_107; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_branch = _mem_dmem_uop_WIRE_82_branch; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_106; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_jal = _mem_dmem_uop_WIRE_82_jal; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_105; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_jalr = _mem_dmem_uop_WIRE_82_jalr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_104; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rxs2 = _mem_dmem_uop_WIRE_82_rxs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_103; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rxs1 = _mem_dmem_uop_WIRE_82_rxs1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_102; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_sel_alu2 = _mem_dmem_uop_WIRE_82_sel_alu2; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_WIRE_101; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_sel_alu1 = _mem_dmem_uop_WIRE_82_sel_alu1; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_100; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_sel_imm = _mem_dmem_uop_WIRE_82_sel_imm; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_99; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_alu_dw = _mem_dmem_uop_WIRE_82_alu_dw; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_98; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_alu_fn = _mem_dmem_uop_WIRE_82_alu_fn; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_97; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_mem = _mem_dmem_uop_WIRE_82_mem; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_WIRE_96; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_mem_cmd = _mem_dmem_uop_WIRE_82_mem_cmd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_95; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rfs1 = _mem_dmem_uop_WIRE_82_rfs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_94; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rfs2 = _mem_dmem_uop_WIRE_82_rfs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_93; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_rfs3 = _mem_dmem_uop_WIRE_82_rfs3; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_92; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_wfd = _mem_dmem_uop_WIRE_82_wfd; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_91; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_mul = _mem_dmem_uop_WIRE_82_mul; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_90; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_div = _mem_dmem_uop_WIRE_82_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_89; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_wxd = _mem_dmem_uop_WIRE_82_wxd; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_WIRE_88; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_csr = _mem_dmem_uop_WIRE_82_csr; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_87; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_fence_i = _mem_dmem_uop_WIRE_82_fence_i; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_86; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_fence = _mem_dmem_uop_WIRE_82_fence; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_85; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_amo = _mem_dmem_uop_WIRE_82_amo; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_84; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_dp = _mem_dmem_uop_WIRE_82_dp; // @[Mux.scala:30:73] wire _mem_dmem_uop_WIRE_83; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_ctrl_vec = _mem_dmem_uop_WIRE_82_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_222 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_223 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_vec; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_224 = _mem_dmem_uop_T_222 | _mem_dmem_uop_T_223; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_83 = _mem_dmem_uop_T_224; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_vec = _mem_dmem_uop_WIRE_83; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_225 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_dp; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_226 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_dp; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_227 = _mem_dmem_uop_T_225 | _mem_dmem_uop_T_226; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_84 = _mem_dmem_uop_T_227; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_dp = _mem_dmem_uop_WIRE_84; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_228 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_amo; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_229 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_amo; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_230 = _mem_dmem_uop_T_228 | _mem_dmem_uop_T_229; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_85 = _mem_dmem_uop_T_230; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_amo = _mem_dmem_uop_WIRE_85; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_231 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_fence; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_232 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_fence; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_233 = _mem_dmem_uop_T_231 | _mem_dmem_uop_T_232; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_86 = _mem_dmem_uop_T_233; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_fence = _mem_dmem_uop_WIRE_86; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_234 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_235 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_fence_i; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_236 = _mem_dmem_uop_T_234 | _mem_dmem_uop_T_235; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_87 = _mem_dmem_uop_T_236; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_fence_i = _mem_dmem_uop_WIRE_87; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_237 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_238 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_csr : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_239 = _mem_dmem_uop_T_237 | _mem_dmem_uop_T_238; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_88 = _mem_dmem_uop_T_239; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_csr = _mem_dmem_uop_WIRE_88; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_240 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_241 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_wxd; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_242 = _mem_dmem_uop_T_240 | _mem_dmem_uop_T_241; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_89 = _mem_dmem_uop_T_242; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_wxd = _mem_dmem_uop_WIRE_89; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_243 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_244 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_div; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_245 = _mem_dmem_uop_T_243 | _mem_dmem_uop_T_244; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_90 = _mem_dmem_uop_T_245; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_div = _mem_dmem_uop_WIRE_90; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_246 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_mul; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_247 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_mul; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_248 = _mem_dmem_uop_T_246 | _mem_dmem_uop_T_247; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_91 = _mem_dmem_uop_T_248; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_mul = _mem_dmem_uop_WIRE_91; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_249 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_250 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_wfd; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_251 = _mem_dmem_uop_T_249 | _mem_dmem_uop_T_250; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_92 = _mem_dmem_uop_T_251; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_wfd = _mem_dmem_uop_WIRE_92; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_252 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_253 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rfs3; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_254 = _mem_dmem_uop_T_252 | _mem_dmem_uop_T_253; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_93 = _mem_dmem_uop_T_254; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rfs3 = _mem_dmem_uop_WIRE_93; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_255 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_256 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rfs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_257 = _mem_dmem_uop_T_255 | _mem_dmem_uop_T_256; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_94 = _mem_dmem_uop_T_257; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rfs2 = _mem_dmem_uop_WIRE_94; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_258 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_259 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rfs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_260 = _mem_dmem_uop_T_258 | _mem_dmem_uop_T_259; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_95 = _mem_dmem_uop_T_260; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rfs1 = _mem_dmem_uop_WIRE_95; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_261 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_262 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_mem_cmd : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_263 = _mem_dmem_uop_T_261 | _mem_dmem_uop_T_262; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_96 = _mem_dmem_uop_T_263; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_mem_cmd = _mem_dmem_uop_WIRE_96; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_264 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_mem; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_265 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_mem; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_266 = _mem_dmem_uop_T_264 | _mem_dmem_uop_T_265; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_97 = _mem_dmem_uop_T_266; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_mem = _mem_dmem_uop_WIRE_97; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_267 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_268 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_alu_fn : 5'h0; // @[Mux.scala:30:73] wire [4:0] _mem_dmem_uop_T_269 = _mem_dmem_uop_T_267 | _mem_dmem_uop_T_268; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_98 = _mem_dmem_uop_T_269; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_alu_fn = _mem_dmem_uop_WIRE_98; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_270 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_271 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_alu_dw; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_272 = _mem_dmem_uop_T_270 | _mem_dmem_uop_T_271; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_99 = _mem_dmem_uop_T_272; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_alu_dw = _mem_dmem_uop_WIRE_99; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_273 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_274 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_imm : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_275 = _mem_dmem_uop_T_273 | _mem_dmem_uop_T_274; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_100 = _mem_dmem_uop_T_275; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_sel_imm = _mem_dmem_uop_WIRE_100; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_276 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_277 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_alu1 : 2'h0; // @[Mux.scala:30:73] wire [1:0] _mem_dmem_uop_T_278 = _mem_dmem_uop_T_276 | _mem_dmem_uop_T_277; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_101 = _mem_dmem_uop_T_278; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_sel_alu1 = _mem_dmem_uop_WIRE_101; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_279 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_280 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_ctrl_sel_alu2 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _mem_dmem_uop_T_281 = _mem_dmem_uop_T_279 | _mem_dmem_uop_T_280; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_102 = _mem_dmem_uop_T_281; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_sel_alu2 = _mem_dmem_uop_WIRE_102; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_282 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_283 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rxs1; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_284 = _mem_dmem_uop_T_282 | _mem_dmem_uop_T_283; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_103 = _mem_dmem_uop_T_284; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rxs1 = _mem_dmem_uop_WIRE_103; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_285 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_286 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rxs2; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_287 = _mem_dmem_uop_T_285 | _mem_dmem_uop_T_286; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_104 = _mem_dmem_uop_T_287; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rxs2 = _mem_dmem_uop_WIRE_104; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_288 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_289 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_jalr; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_290 = _mem_dmem_uop_T_288 | _mem_dmem_uop_T_289; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_105 = _mem_dmem_uop_T_290; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_jalr = _mem_dmem_uop_WIRE_105; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_291 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_292 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_jal; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_293 = _mem_dmem_uop_T_291 | _mem_dmem_uop_T_292; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_106 = _mem_dmem_uop_T_293; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_jal = _mem_dmem_uop_WIRE_106; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_294 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_branch; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_295 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_branch; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_296 = _mem_dmem_uop_T_294 | _mem_dmem_uop_T_295; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_107 = _mem_dmem_uop_T_296; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_branch = _mem_dmem_uop_WIRE_107; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_297 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_298 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_rocc; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_299 = _mem_dmem_uop_T_297 | _mem_dmem_uop_T_298; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_108 = _mem_dmem_uop_T_299; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_rocc = _mem_dmem_uop_WIRE_108; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_300 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_fp; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_301 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_fp; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_302 = _mem_dmem_uop_T_300 | _mem_dmem_uop_T_301; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_109 = _mem_dmem_uop_T_302; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_fp = _mem_dmem_uop_WIRE_109; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_303 = mem_dmem_oh_0 & mem_uops_reg_0_bits_ctrl_legal; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_304 = mem_dmem_oh_1 & mem_uops_reg_1_bits_ctrl_legal; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_305 = _mem_dmem_uop_T_303 | _mem_dmem_uop_T_304; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_110 = _mem_dmem_uop_T_305; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_82_legal = _mem_dmem_uop_WIRE_110; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_306 = mem_dmem_oh_0 & mem_uops_reg_0_bits_edge_inst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_307 = mem_dmem_oh_1 & mem_uops_reg_1_bits_edge_inst; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_308 = _mem_dmem_uop_T_306 | _mem_dmem_uop_T_307; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_111 = _mem_dmem_uop_T_308; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_edge_inst = _mem_dmem_uop_WIRE_111; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_309 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_310 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_pc : 40'h0; // @[Mux.scala:30:73] wire [39:0] _mem_dmem_uop_T_311 = _mem_dmem_uop_T_309 | _mem_dmem_uop_T_310; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_112 = _mem_dmem_uop_T_311; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_pc = _mem_dmem_uop_WIRE_112; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_312 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_313 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_raw_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_314 = _mem_dmem_uop_T_312 | _mem_dmem_uop_T_313; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_113 = _mem_dmem_uop_T_314; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_raw_inst = _mem_dmem_uop_WIRE_113; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_315 = mem_dmem_oh_0 ? mem_uops_reg_0_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_316 = mem_dmem_oh_1 ? mem_uops_reg_1_bits_inst : 32'h0; // @[Mux.scala:30:73] wire [31:0] _mem_dmem_uop_T_317 = _mem_dmem_uop_T_315 | _mem_dmem_uop_T_316; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_114 = _mem_dmem_uop_T_317; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_inst = _mem_dmem_uop_WIRE_114; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_318 = mem_dmem_oh_0 & mem_uops_reg_0_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_319 = mem_dmem_oh_1 & mem_uops_reg_1_valid; // @[Mux.scala:30:73] wire _mem_dmem_uop_T_320 = _mem_dmem_uop_T_318 | _mem_dmem_uop_T_319; // @[Mux.scala:30:73] assign _mem_dmem_uop_WIRE_115 = _mem_dmem_uop_T_320; // @[Mux.scala:30:73] assign mem_dmem_uop_valid = _mem_dmem_uop_WIRE_115; // @[Mux.scala:30:73] reg [39:0] dtlb_io_req_0_bits_vaddr_r; // @[Core.scala:707:43] wire _dtlb_io_sfence_valid_T = mem_dmem_uop_bits_ctrl_mem_cmd == 5'h14; // @[Mux.scala:30:73] wire _dtlb_io_sfence_valid_T_1 = mem_dmem_uop_valid & _dtlb_io_sfence_valid_T; // @[Mux.scala:30:73] wire _dtlb_io_sfence_bits_rs1_T = mem_dmem_uop_bits_mem_size[0]; // @[Mux.scala:30:73] wire _dtlb_io_sfence_bits_rs2_T = mem_dmem_uop_bits_mem_size[1]; // @[Mux.scala:30:73] wire _com_uops_reg_0_bits_wdata_bits_T_1 = _com_uops_reg_0_bits_wdata_bits_T[39]; // @[Utils.scala:35:46] wire [23:0] _com_uops_reg_0_bits_wdata_bits_T_2 = {24{_com_uops_reg_0_bits_wdata_bits_T_1}}; // @[Utils.scala:35:{25,46}] wire [63:0] _com_uops_reg_0_bits_wdata_bits_T_3 = {_com_uops_reg_0_bits_wdata_bits_T_2, _com_uops_reg_0_bits_wdata_bits_T}; // @[Utils.scala:35:{20,25}] assign io_dmem_s1_data_data_0 = mem_dmem_oh_0 & (mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h1 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h11 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h7 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h4 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h9 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hA | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hB | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'h8 | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hC | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hD | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hE | mem_uops_reg_0_bits_ctrl_mem_cmd == 5'hF) & mem_uops_reg_0_bits_ctrl_fp ? _fp_pipe_io_s1_store_data : mem_dmem_uop_bits_rs2_data; // @[Mux.scala:30:73] wire _T_188 = mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_ma_st; // @[Core.scala:72:25, :634:20, :762:17] wire _T_189 = mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_ma_ld; // @[Core.scala:72:25, :634:20, :763:17] wire _T_190 = mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_pf_st; // @[Core.scala:72:25, :634:20, :764:17] wire _T_191 = mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_pf_ld; // @[Core.scala:72:25, :634:20, :765:17] wire _T_192 = mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_ae_st; // @[Core.scala:72:25, :634:20, :766:17] wire xcpt_2 = mem_uops_reg_0_bits_xcpt | _T_188 | _T_189 | _T_190 | _T_191 | _T_192 | mem_uops_reg_0_bits_ctrl_mem & _dtlb_io_resp_0_ae_ld; // @[Core.scala:60:26, :72:25, :634:20, :762:17, :763:17, :764:17, :765:17, :766:17, :767:17] wire [63:0] cause_2 = mem_uops_reg_0_bits_xcpt ? mem_uops_reg_0_bits_xcpt_cause : {60'h0, _T_188 ? 4'h6 : _T_189 ? 4'h4 : _T_190 ? 4'hF : _T_191 ? 4'hD : {2'h1, _T_192, 1'h1}}; // @[Mux.scala:50:70] wire _mem_bypasses_0_valid_T = mem_uops_reg_0_valid & mem_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:72:25, :798:52] assign _mem_bypasses_0_valid_T_2 = _mem_bypasses_0_valid_T; // @[Core.scala:798:{52,85}] assign mem_bypasses_0_valid = _mem_bypasses_0_valid_T_2; // @[Core.scala:93:63, :798:85] assign _mem_bypasses_0_dst_T = mem_uops_reg_0_bits_inst[11:7]; // @[Core.scala:72:25] assign _fp_mem_bypasses_0_dst_T = mem_uops_reg_0_bits_inst[11:7]; // @[Core.scala:72:25] assign mem_bypasses_0_dst = _mem_bypasses_0_dst_T; // @[Core.scala:93:63] wire _fp_mem_bypasses_0_valid_T = mem_uops_reg_0_valid & mem_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:72:25, :803:55] assign _fp_mem_bypasses_0_valid_T_2 = _fp_mem_bypasses_0_valid_T; // @[Core.scala:803:{55,88}] assign fp_mem_bypasses_0_valid = _fp_mem_bypasses_0_valid_T_2; // @[Core.scala:101:66, :803:88] assign fp_mem_bypasses_0_dst = _fp_mem_bypasses_0_dst_T; // @[Core.scala:101:66] wire _com_uops_reg_1_bits_wdata_bits_T_1 = _com_uops_reg_1_bits_wdata_bits_T[39]; // @[Utils.scala:35:46] wire [23:0] _com_uops_reg_1_bits_wdata_bits_T_2 = {24{_com_uops_reg_1_bits_wdata_bits_T_1}}; // @[Utils.scala:35:{25,46}] wire [63:0] _com_uops_reg_1_bits_wdata_bits_T_3 = {_com_uops_reg_1_bits_wdata_bits_T_2, _com_uops_reg_1_bits_wdata_bits_T}; // @[Utils.scala:35:{20,25}] wire _T_213 = mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_ma_st; // @[Core.scala:72:25, :634:20, :762:17] wire _T_214 = mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_ma_ld; // @[Core.scala:72:25, :634:20, :763:17] wire _T_215 = mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_pf_st; // @[Core.scala:72:25, :634:20, :764:17] wire _T_216 = mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_pf_ld; // @[Core.scala:72:25, :634:20, :765:17] wire _T_217 = mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_ae_st; // @[Core.scala:72:25, :634:20, :766:17] wire xcpt_3 = mem_uops_reg_0_bits_xcpt | _T_213 | _T_214 | _T_215 | _T_216 | _T_217 | mem_uops_reg_1_bits_ctrl_mem & _dtlb_io_resp_0_ae_ld; // @[Core.scala:60:26, :72:25, :634:20, :762:17, :763:17, :764:17, :765:17, :766:17, :767:17] wire [63:0] cause_3 = mem_uops_reg_0_bits_xcpt ? mem_uops_reg_0_bits_xcpt_cause : {60'h0, _T_213 ? 4'h6 : _T_214 ? 4'h4 : _T_215 ? 4'hF : _T_216 ? 4'hD : {2'h1, _T_217, 1'h1}}; // @[Mux.scala:50:70] wire sfb_shadow_kill_1; // @[Core.scala:775:35] assign sfb_shadow_kill_1 = mem_brjmp_taken & mem_uops_reg_1_bits_sfb_shadow; // @[Core.scala:72:25, :655:95, :775:35, :777:29] wire _T_232 = mem_brjmp_oh_0 & ~mem_uops_reg_1_bits_sfb_shadow & mem_brjmp_mispredict; // @[Core.scala:72:25, :640:53, :658:57, :784:{38,41,74}] assign io_dmem_s1_kill_0 = _T_232 ? mem_uops_reg_1_bits_ctrl_mem | _T_130 | _T_127 : _T_130 | _T_127; // @[Core.scala:25:7, :72:25, :573:{54,63}, :574:23, :784:{38,74,99}, :786:46, :787:27] wire _GEN_108 = mem_uops_reg_1_valid & mem_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:72:25, :798:52] wire _mem_bypasses_1_valid_T; // @[Core.scala:798:52] assign _mem_bypasses_1_valid_T = _GEN_108; // @[Core.scala:798:52] wire _mem_bypasses_1_valid_T_3; // @[Core.scala:851:64] assign _mem_bypasses_1_valid_T_3 = _GEN_108; // @[Core.scala:798:52, :851:64] wire _mem_bypasses_1_valid_T_1 = ~sfb_shadow_kill_1; // @[Core.scala:775:35, :798:88] wire _mem_bypasses_1_valid_T_2 = _mem_bypasses_1_valid_T & _mem_bypasses_1_valid_T_1; // @[Core.scala:798:{52,85,88}] assign _mem_bypasses_1_dst_T = mem_uops_reg_1_bits_inst[11:7]; // @[Core.scala:72:25] assign _fp_mem_bypasses_1_dst_T = mem_uops_reg_1_bits_inst[11:7]; // @[Core.scala:72:25] assign mem_bypasses_1_dst = _mem_bypasses_1_dst_T; // @[Core.scala:93:63] wire _fp_mem_bypasses_1_valid_T = mem_uops_reg_1_valid & mem_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:72:25, :803:55] wire _fp_mem_bypasses_1_valid_T_1 = ~sfb_shadow_kill_1; // @[Core.scala:775:35, :798:88, :803:91] assign _fp_mem_bypasses_1_valid_T_2 = _fp_mem_bypasses_1_valid_T & _fp_mem_bypasses_1_valid_T_1; // @[Core.scala:803:{55,88,91}] assign fp_mem_bypasses_1_valid = _fp_mem_bypasses_1_valid_T_2; // @[Core.scala:101:66, :803:88] assign fp_mem_bypasses_1_dst = _fp_mem_bypasses_1_dst_T; // @[Core.scala:101:66] wire [39:0] _ex_op1_T_27 = mem_alu_uops_0_pc; // @[Core.scala:809:69, :832:25] wire [2:0] sel_alu2_2 = mem_alu_uops_0_ctrl_sel_alu2; // @[Core.scala:809:69, :827:30] wire [1:0] sel_alu1_2 = mem_alu_uops_0_ctrl_sel_alu1; // @[Core.scala:809:69, :826:30] wire [63:0] _ex_op1_T_26 = mem_alu_uops_0_rs1_data; // @[Core.scala:809:69, :831:28] wire [63:0] _ex_op2_T_22 = mem_alu_uops_0_rs2_data; // @[Core.scala:809:69, :837:28] wire mem_alu_uops_0_ctrl_legal; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_fp; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rocc; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_branch; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_jal; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_jalr; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rxs2; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rxs1; // @[Core.scala:809:69] wire [2:0] mem_alu_uops_0_ctrl_sel_imm; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_alu_dw; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_ctrl_alu_fn; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_mem; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_ctrl_mem_cmd; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rfs1; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rfs2; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_rfs3; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_wfd; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_mul; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_div; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_wxd; // @[Core.scala:809:69] wire [2:0] mem_alu_uops_0_ctrl_csr; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_fence_i; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_fence; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_amo; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_dp; // @[Core.scala:809:69] wire mem_alu_uops_0_ctrl_vec; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_ldst; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_wen; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_ren1; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_ren2; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_ren3; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_swap12; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_swap23; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fp_ctrl_typeTagIn; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fp_ctrl_typeTagOut; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_fromint; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_toint; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_fastpipe; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_fma; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_div; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_sqrt; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_wflags; // @[Core.scala:809:69] wire mem_alu_uops_0_fp_ctrl_vec; // @[Core.scala:809:69] wire [7:0] mem_alu_uops_0_btb_resp_bits_bht_history; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_btb_resp_bits_bht_value; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_btb_resp_bits_cfiType; // @[Core.scala:809:69] wire mem_alu_uops_0_btb_resp_bits_taken; // @[Core.scala:809:69] wire [3:0] mem_alu_uops_0_btb_resp_bits_mask; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_btb_resp_bits_bridx; // @[Core.scala:809:69] wire [38:0] mem_alu_uops_0_btb_resp_bits_target; // @[Core.scala:809:69] wire [5:0] mem_alu_uops_0_btb_resp_bits_entry; // @[Core.scala:809:69] wire mem_alu_uops_0_btb_resp_valid; // @[Core.scala:809:69] wire mem_alu_uops_0_next_pc_valid; // @[Core.scala:809:69] wire [39:0] mem_alu_uops_0_next_pc_bits; // @[Core.scala:809:69] wire mem_alu_uops_0_wdata_valid; // @[Core.scala:809:69] wire [63:0] mem_alu_uops_0_wdata_bits; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_ldst; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_wen; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_ren1; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_ren2; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_ren3; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_swap12; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_swap23; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fdivin_typeTagIn; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fdivin_typeTagOut; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_fromint; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_toint; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_fastpipe; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_fma; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_div; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_sqrt; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_wflags; // @[Core.scala:809:69] wire mem_alu_uops_0_fdivin_vec; // @[Core.scala:809:69] wire [2:0] mem_alu_uops_0_fdivin_rm; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fdivin_fmaCmd; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fdivin_typ; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_fdivin_fmt; // @[Core.scala:809:69] wire [64:0] mem_alu_uops_0_fdivin_in1; // @[Core.scala:809:69] wire [64:0] mem_alu_uops_0_fdivin_in2; // @[Core.scala:809:69] wire [64:0] mem_alu_uops_0_fdivin_in3; // @[Core.scala:809:69] wire [31:0] mem_alu_uops_0_inst; // @[Core.scala:809:69] wire [31:0] mem_alu_uops_0_raw_inst; // @[Core.scala:809:69] wire mem_alu_uops_0_edge_inst; // @[Core.scala:809:69] wire mem_alu_uops_0_rvc; // @[Core.scala:809:69] wire mem_alu_uops_0_sets_vcfg; // @[Core.scala:809:69] wire mem_alu_uops_0_sfb_br; // @[Core.scala:809:69] wire mem_alu_uops_0_sfb_shadow; // @[Core.scala:809:69] wire [2:0] mem_alu_uops_0_ras_head; // @[Core.scala:809:69] wire mem_alu_uops_0_taken; // @[Core.scala:809:69] wire mem_alu_uops_0_xcpt; // @[Core.scala:809:69] wire [63:0] mem_alu_uops_0_xcpt_cause; // @[Core.scala:809:69] wire mem_alu_uops_0_needs_replay; // @[Core.scala:809:69] wire [63:0] mem_alu_uops_0_rs3_data; // @[Core.scala:809:69] wire mem_alu_uops_0_uses_memalu; // @[Core.scala:809:69] wire mem_alu_uops_0_uses_latealu; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_fra1; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_fra2; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_fra3; // @[Core.scala:809:69] wire [4:0] mem_alu_uops_0_fexc; // @[Core.scala:809:69] wire [1:0] mem_alu_uops_0_mem_size; // @[Core.scala:809:69] wire mem_alu_uops_0_flush_pipe; // @[Core.scala:809:69] wire _GEN_109 = mem_alu_uops_0_ctrl_sel_imm == 3'h5; // @[Core.scala:809:69] wire _imm_sign_T_6; // @[RocketCore.scala:1341:24] assign _imm_sign_T_6 = _GEN_109; // @[RocketCore.scala:1341:24] wire _imm_b11_T_23; // @[RocketCore.scala:1344:40] assign _imm_b11_T_23 = _GEN_109; // @[RocketCore.scala:1341:24, :1344:40] wire _imm_b10_5_T_9; // @[RocketCore.scala:1347:42] assign _imm_b10_5_T_9 = _GEN_109; // @[RocketCore.scala:1341:24, :1347:42] wire _imm_b4_1_T_25; // @[RocketCore.scala:1350:24] assign _imm_b4_1_T_25 = _GEN_109; // @[RocketCore.scala:1341:24, :1350:24] wire _imm_b0_T_20; // @[RocketCore.scala:1353:22] assign _imm_b0_T_20 = _GEN_109; // @[RocketCore.scala:1341:24, :1353:22] wire _imm_sign_T_7 = mem_alu_uops_0_inst[31]; // @[Core.scala:809:69] wire _imm_sign_T_8 = _imm_sign_T_7; // @[RocketCore.scala:1341:{44,49}] wire imm_sign_2 = ~_imm_sign_T_6 & _imm_sign_T_8; // @[RocketCore.scala:1341:{19,24,49}] wire imm_hi_hi_hi_2 = imm_sign_2; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_110 = mem_alu_uops_0_ctrl_sel_imm == 3'h2; // @[Core.scala:809:69] wire _imm_b30_20_T_6; // @[RocketCore.scala:1342:26] assign _imm_b30_20_T_6 = _GEN_110; // @[RocketCore.scala:1342:26] wire _imm_b11_T_22; // @[RocketCore.scala:1344:23] assign _imm_b11_T_22 = _GEN_110; // @[RocketCore.scala:1342:26, :1344:23] wire _imm_b10_5_T_8; // @[RocketCore.scala:1347:25] assign _imm_b10_5_T_8 = _GEN_110; // @[RocketCore.scala:1342:26, :1347:25] wire _imm_b4_1_T_20; // @[RocketCore.scala:1348:24] assign _imm_b4_1_T_20 = _GEN_110; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _imm_b30_20_T_7 = mem_alu_uops_0_inst[30:20]; // @[Core.scala:809:69] wire [10:0] _imm_b30_20_T_8 = _imm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}] wire [10:0] imm_b30_20_2 = _imm_b30_20_T_6 ? _imm_b30_20_T_8 : {11{imm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] imm_hi_hi_lo_2 = imm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8] wire _imm_b19_12_T_10 = mem_alu_uops_0_ctrl_sel_imm != 3'h2; // @[Core.scala:809:69] wire _imm_b19_12_T_11 = mem_alu_uops_0_ctrl_sel_imm != 3'h3; // @[Core.scala:809:69] wire _imm_b19_12_T_12 = _imm_b19_12_T_10 & _imm_b19_12_T_11; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _imm_b19_12_T_13 = mem_alu_uops_0_inst[19:12]; // @[Core.scala:809:69] wire [7:0] _imm_b19_12_T_14 = _imm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}] wire [7:0] imm_b19_12_2 = _imm_b19_12_T_12 ? {8{imm_sign_2}} : _imm_b19_12_T_14; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] imm_hi_lo_hi_2 = imm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8] wire _imm_b11_T_24 = _imm_b11_T_22 | _imm_b11_T_23; // @[RocketCore.scala:1344:{23,33,40}] wire _imm_b11_T_25 = mem_alu_uops_0_ctrl_sel_imm == 3'h3; // @[Core.scala:809:69] wire _imm_b11_T_26 = mem_alu_uops_0_inst[20]; // @[Core.scala:809:69] wire _imm_b0_T_19 = mem_alu_uops_0_inst[20]; // @[Core.scala:809:69] wire _imm_b11_T_27 = _imm_b11_T_26; // @[RocketCore.scala:1345:{39,44}] wire _GEN_111 = mem_alu_uops_0_ctrl_sel_imm == 3'h1; // @[Core.scala:809:69] wire _imm_b11_T_28; // @[RocketCore.scala:1346:23] assign _imm_b11_T_28 = _GEN_111; // @[RocketCore.scala:1346:23] wire _imm_b4_1_T_22; // @[RocketCore.scala:1349:41] assign _imm_b4_1_T_22 = _GEN_111; // @[RocketCore.scala:1346:23, :1349:41] wire _imm_b11_T_29 = mem_alu_uops_0_inst[7]; // @[Core.scala:809:69] wire _imm_b0_T_17 = mem_alu_uops_0_inst[7]; // @[Core.scala:809:69] wire _imm_b11_T_30 = _imm_b11_T_29; // @[RocketCore.scala:1346:{39,43}] wire _imm_b11_T_31 = _imm_b11_T_28 ? _imm_b11_T_30 : imm_sign_2; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _imm_b11_T_32 = _imm_b11_T_25 ? _imm_b11_T_27 : _imm_b11_T_31; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire imm_b11_2 = ~_imm_b11_T_24 & _imm_b11_T_32; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire imm_hi_lo_lo_2 = imm_b11_2; // @[RocketCore.scala:1344:18, :1355:8] wire _imm_b10_5_T_10 = _imm_b10_5_T_8 | _imm_b10_5_T_9; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _imm_b10_5_T_11 = mem_alu_uops_0_inst[30:25]; // @[Core.scala:809:69] wire [5:0] imm_b10_5_2 = _imm_b10_5_T_10 ? 6'h0 : _imm_b10_5_T_11; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_112 = mem_alu_uops_0_ctrl_sel_imm == 3'h0; // @[Core.scala:809:69] wire _imm_b4_1_T_21; // @[RocketCore.scala:1349:24] assign _imm_b4_1_T_21 = _GEN_112; // @[RocketCore.scala:1349:24] wire _imm_b0_T_16; // @[RocketCore.scala:1351:22] assign _imm_b0_T_16 = _GEN_112; // @[RocketCore.scala:1349:24, :1351:22] wire _imm_b4_1_T_23 = _imm_b4_1_T_21 | _imm_b4_1_T_22; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _imm_b4_1_T_24 = mem_alu_uops_0_inst[11:8]; // @[Core.scala:809:69] wire [3:0] _imm_b4_1_T_26 = mem_alu_uops_0_inst[19:16]; // @[Core.scala:809:69] wire [3:0] _imm_b4_1_T_27 = mem_alu_uops_0_inst[24:21]; // @[Core.scala:809:69] wire [3:0] _imm_b4_1_T_28 = _imm_b4_1_T_25 ? _imm_b4_1_T_26 : _imm_b4_1_T_27; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _imm_b4_1_T_29 = _imm_b4_1_T_23 ? _imm_b4_1_T_24 : _imm_b4_1_T_28; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] imm_b4_1_2 = _imm_b4_1_T_20 ? 4'h0 : _imm_b4_1_T_29; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _imm_b0_T_18 = mem_alu_uops_0_ctrl_sel_imm == 3'h4; // @[Core.scala:809:69] wire _imm_b0_T_21 = mem_alu_uops_0_inst[15]; // @[Core.scala:809:69] wire _imm_b0_T_22 = _imm_b0_T_20 & _imm_b0_T_21; // @[RocketCore.scala:1353:{17,22,37}] wire _imm_b0_T_23 = _imm_b0_T_18 ? _imm_b0_T_19 : _imm_b0_T_22; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire imm_b0_2 = _imm_b0_T_16 ? _imm_b0_T_17 : _imm_b0_T_23; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] imm_lo_hi_2 = {imm_b10_5_2, imm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] imm_lo_2 = {imm_lo_hi_2, imm_b0_2}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] imm_hi_lo_2 = {imm_hi_lo_hi_2, imm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8] wire [11:0] imm_hi_hi_2 = {imm_hi_hi_hi_2, imm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [20:0] imm_hi_2 = {imm_hi_hi_2, imm_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] _imm_T_2 = {imm_hi_2, imm_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] imm_2 = _imm_T_2; // @[RocketCore.scala:1355:{8,53}] wire _ex_op1_T_28 = mem_alu_uops_0_inst[3]; // @[Core.scala:809:69, :833:35] wire [31:0] _ex_op1_T_29 = mem_alu_uops_0_rs1_data[31:0]; // @[Core.scala:809:69, :833:48] wire [63:0] _ex_op1_T_30 = _ex_op1_T_28 ? {32'h0, _ex_op1_T_29} : mem_alu_uops_0_rs1_data; // @[Core.scala:809:69, :833:{26,35,48}] wire [1:0] _ex_op1_T_31 = mem_alu_uops_0_inst[14:13]; // @[Core.scala:809:69, :833:77] wire [66:0] _ex_op1_T_32 = {3'h0, _ex_op1_T_30} << _ex_op1_T_31; // @[Core.scala:833:{26,66,77}] wire [66:0] _ex_op1_T_33 = _ex_op1_T_32; // @[Core.scala:833:{66,86}] wire _ex_op1_T_34 = sel_alu1_2 == 2'h1; // @[Core.scala:826:30, :830:44] wire [63:0] _ex_op1_T_35 = _ex_op1_T_34 ? _ex_op1_T_26 : 64'h0; // @[Core.scala:830:44, :831:28] wire _ex_op1_T_36 = sel_alu1_2 == 2'h2; // @[Core.scala:826:30, :830:44] wire [63:0] _ex_op1_T_37 = _ex_op1_T_36 ? {{24{_ex_op1_T_27[39]}}, _ex_op1_T_27} : _ex_op1_T_35; // @[Core.scala:830:44, :832:25] wire _ex_op1_T_38 = &sel_alu1_2; // @[Core.scala:826:30, :830:44] wire [66:0] ex_op1_2 = _ex_op1_T_38 ? _ex_op1_T_33 : {{3{_ex_op1_T_37[63]}}, _ex_op1_T_37}; // @[Core.scala:830:44, :833:86] wire [66:0] _mem_alus_0_io_in1_T = ex_op1_2; // @[Core.scala:830:44, :846:28] wire _ex_op2_oh_T_10 = mem_alu_uops_0_ctrl_sel_alu2[0]; // @[Core.scala:809:69, :835:49] wire [11:0] _ex_op2_oh_T_11 = mem_alu_uops_0_inst[31:20]; // @[Core.scala:809:69, :835:64] wire [63:0] _ex_op2_oh_T_12 = _ex_op2_oh_T_10 ? {52'h0, _ex_op2_oh_T_11} : mem_alu_uops_0_rs2_data; // @[Core.scala:809:69, :835:{35,49,64}] wire [5:0] _ex_op2_oh_T_13 = _ex_op2_oh_T_12[5:0]; // @[Core.scala:835:{35,88}] wire [63:0] _ex_op2_oh_T_14 = 64'h1 << _ex_op2_oh_T_13; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh_2 = _ex_op2_oh_T_14; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_23 = mem_alu_uops_0_rvc ? 4'h2 : 4'h4; // @[Core.scala:809:69, :839:23] wire _ex_op2_T_24 = sel_alu2_2 == 3'h2; // @[Core.scala:827:30, :836:44] wire [63:0] _ex_op2_T_25 = _ex_op2_T_24 ? _ex_op2_T_22 : 64'h0; // @[Core.scala:836:44, :837:28] wire _ex_op2_T_26 = sel_alu2_2 == 3'h3; // @[Core.scala:827:30, :836:44] wire [63:0] _ex_op2_T_27 = _ex_op2_T_26 ? {{32{imm_2[31]}}, imm_2} : _ex_op2_T_25; // @[Core.scala:836:44] wire _ex_op2_T_28 = sel_alu2_2 == 3'h1; // @[Core.scala:827:30, :836:44] wire [63:0] _ex_op2_T_29 = _ex_op2_T_28 ? {{60{_ex_op2_T_23[3]}}, _ex_op2_T_23} : _ex_op2_T_27; // @[Core.scala:836:44, :839:23] wire _ex_op2_T_30 = sel_alu2_2 == 3'h4; // @[Core.scala:827:30, :836:44] wire [63:0] _ex_op2_T_31 = _ex_op2_T_30 ? ex_op2_oh_2 : _ex_op2_T_29; // @[Core.scala:835:110, :836:44] wire _ex_op2_T_32 = sel_alu2_2 == 3'h5; // @[Core.scala:827:30, :836:44] wire [63:0] ex_op2_2 = _ex_op2_T_32 ? ex_op2_oh_2 : _ex_op2_T_31; // @[Core.scala:835:110, :836:44] wire [63:0] _mem_alus_0_io_in2_T = ex_op2_2; // @[Core.scala:836:44, :845:28] assign mem_bypasses_1_valid = mem_alu_uops_0_uses_memalu ? _mem_bypasses_1_valid_T_3 : _mem_bypasses_1_valid_T_2; // @[Core.scala:93:63, :798:{27,85}, :809:69, :848:30, :851:{31,64}] assign mem_bypasses_1_can_bypass = mem_alu_uops_0_uses_memalu | mem_uops_reg_1_bits_wdata_valid; // @[Core.scala:72:25, :93:63, :800:32, :809:69, :848:30, :852:36] assign mem_bypasses_1_data = mem_alu_uops_0_uses_memalu ? _mem_alus_0_io_out : mem_uops_reg_1_bits_wdata_bits; // @[Core.scala:72:25, :93:63, :801:26, :809:69, :810:67, :848:30, :853:30] reg REG_2; // @[Core.scala:859:18] wire _T_280 = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_mem; // @[Core.scala:73:25, :862:33] reg REG_3; // @[Core.scala:859:18] wire _T_285 = com_uops_reg_1_valid & com_uops_reg_1_bits_ctrl_mem; // @[Core.scala:73:25, :862:33] assign io_dmem_s2_kill_0 = _T_285 & (com_uops_1_bits_needs_replay | com_uops_reg_1_bits_xcpt | kill_com_1) | REG_3 | _T_280 & (com_uops_0_bits_needs_replay | com_uops_reg_0_bits_xcpt) | REG_2; // @[Core.scala:25:7, :73:25, :74:26, :112:26, :859:{18,88}, :860:23, :862:{33,66,100,129,146}, :863:23] wire _com_fp_divsqrt_valid_T = com_uops_reg_0_bits_fp_ctrl_ldst & com_uops_reg_0_bits_fp_ctrl_wen; // @[Core.scala:73:25] wire _com_fp_divsqrt_valid_T_1 = ~_com_fp_divsqrt_valid_T; // @[MicroOp.scala:78:{28,43}] wire _com_fp_divsqrt_valid_T_2 = com_uops_reg_0_bits_ctrl_fp & _com_fp_divsqrt_valid_T_1; // @[Core.scala:73:25] wire _com_fp_divsqrt_valid_T_3 = com_uops_reg_0_bits_fp_ctrl_div | com_uops_reg_0_bits_fp_ctrl_sqrt; // @[Core.scala:73:25, :870:87] wire com_fp_divsqrt_valid = _com_fp_divsqrt_valid_T_2 & _com_fp_divsqrt_valid_T_3; // @[Core.scala:870:{59,87}] reg divSqrt_val; // @[Core.scala:872:28] reg [4:0] divSqrt_waddr; // @[Core.scala:873:26] reg [1:0] divSqrt_typeTag; // @[Core.scala:874:28] reg divSqrt_wdata_valid; // @[Core.scala:875:26] reg [64:0] divSqrt_wdata_bits; // @[Core.scala:875:26] reg [4:0] divSqrt_flags; // @[Core.scala:876:26] wire _divSqrt_io_inValid_T = com_uops_reg_0_bits_fp_ctrl_typeTagOut == 2'h0; // @[Core.scala:73:25, :883:56] wire _divSqrt_io_inValid_T_1 = com_uops_reg_0_valid & _divSqrt_io_inValid_T; // @[Core.scala:73:25, :883:{49,56}] wire _divSqrt_io_inValid_T_2 = _divSqrt_io_inValid_T_1 & com_fp_divsqrt_valid; // @[Core.scala:870:59, :883:{49,73}] wire _divSqrt_io_inValid_T_3 = ~divSqrt_val; // @[Core.scala:872:28, :883:100] wire _divSqrt_io_inValid_T_4 = _divSqrt_io_inValid_T_2 & _divSqrt_io_inValid_T_3; // @[Core.scala:883:{73,97,100}] wire divSqrt_io_a_sign = com_uops_reg_0_bits_fdivin_in1[64]; // @[Core.scala:73:25] wire divSqrt_io_a_sign_1 = com_uops_reg_0_bits_fdivin_in1[64]; // @[Core.scala:73:25] wire [51:0] divSqrt_io_a_fractIn = com_uops_reg_0_bits_fdivin_in1[51:0]; // @[Core.scala:73:25] wire [51:0] divSqrt_io_a_fractIn_1 = com_uops_reg_0_bits_fdivin_in1[51:0]; // @[Core.scala:73:25] wire [11:0] divSqrt_io_a_expIn = com_uops_reg_0_bits_fdivin_in1[63:52]; // @[Core.scala:73:25] wire [11:0] divSqrt_io_a_expIn_1 = com_uops_reg_0_bits_fdivin_in1[63:52]; // @[Core.scala:73:25] wire [62:0] _divSqrt_io_a_fractOut_T = {divSqrt_io_a_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] divSqrt_io_a_fractOut = _divSqrt_io_a_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] divSqrt_io_a_expOut_expCode = divSqrt_io_a_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _divSqrt_io_a_expOut_commonCase_T = {1'h0, divSqrt_io_a_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _divSqrt_io_a_expOut_commonCase_T_1 = _divSqrt_io_a_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _divSqrt_io_a_expOut_commonCase_T_2 = {1'h0, _divSqrt_io_a_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] divSqrt_io_a_expOut_commonCase = _divSqrt_io_a_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _divSqrt_io_a_expOut_T = divSqrt_io_a_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _divSqrt_io_a_expOut_T_1 = divSqrt_io_a_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _divSqrt_io_a_expOut_T_2 = _divSqrt_io_a_expOut_T | _divSqrt_io_a_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _divSqrt_io_a_expOut_T_3 = divSqrt_io_a_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _divSqrt_io_a_expOut_T_4 = {divSqrt_io_a_expOut_expCode, _divSqrt_io_a_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _divSqrt_io_a_expOut_T_5 = divSqrt_io_a_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] divSqrt_io_a_expOut = _divSqrt_io_a_expOut_T_2 ? _divSqrt_io_a_expOut_T_4 : _divSqrt_io_a_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] divSqrt_io_a_hi = {divSqrt_io_a_sign, divSqrt_io_a_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _divSqrt_io_a_T = {divSqrt_io_a_hi, divSqrt_io_a_fractOut}; // @[FPU.scala:277:38, :283:8] wire divSqrt_io_b_sign = com_uops_reg_0_bits_fdivin_in2[64]; // @[Core.scala:73:25] wire divSqrt_io_b_sign_1 = com_uops_reg_0_bits_fdivin_in2[64]; // @[Core.scala:73:25] wire [51:0] divSqrt_io_b_fractIn = com_uops_reg_0_bits_fdivin_in2[51:0]; // @[Core.scala:73:25] wire [51:0] divSqrt_io_b_fractIn_1 = com_uops_reg_0_bits_fdivin_in2[51:0]; // @[Core.scala:73:25] wire [11:0] divSqrt_io_b_expIn = com_uops_reg_0_bits_fdivin_in2[63:52]; // @[Core.scala:73:25] wire [11:0] divSqrt_io_b_expIn_1 = com_uops_reg_0_bits_fdivin_in2[63:52]; // @[Core.scala:73:25] wire [62:0] _divSqrt_io_b_fractOut_T = {divSqrt_io_b_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] divSqrt_io_b_fractOut = _divSqrt_io_b_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] divSqrt_io_b_expOut_expCode = divSqrt_io_b_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _divSqrt_io_b_expOut_commonCase_T = {1'h0, divSqrt_io_b_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _divSqrt_io_b_expOut_commonCase_T_1 = _divSqrt_io_b_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _divSqrt_io_b_expOut_commonCase_T_2 = {1'h0, _divSqrt_io_b_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] divSqrt_io_b_expOut_commonCase = _divSqrt_io_b_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _divSqrt_io_b_expOut_T = divSqrt_io_b_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _divSqrt_io_b_expOut_T_1 = divSqrt_io_b_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _divSqrt_io_b_expOut_T_2 = _divSqrt_io_b_expOut_T | _divSqrt_io_b_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _divSqrt_io_b_expOut_T_3 = divSqrt_io_b_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _divSqrt_io_b_expOut_T_4 = {divSqrt_io_b_expOut_expCode, _divSqrt_io_b_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _divSqrt_io_b_expOut_T_5 = divSqrt_io_b_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] divSqrt_io_b_expOut = _divSqrt_io_b_expOut_T_2 ? _divSqrt_io_b_expOut_T_4 : _divSqrt_io_b_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] divSqrt_io_b_hi = {divSqrt_io_b_sign, divSqrt_io_b_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _divSqrt_io_b_T = {divSqrt_io_b_hi, divSqrt_io_b_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _divSqrt_waddr_T = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] wire [4:0] _divSqrt_waddr_T_1 = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] wire [4:0] _divSqrt_waddr_T_2 = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T_1 = _divSqrt_io_out[15]; // @[Core.scala:882:25] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T_2 = _divSqrt_io_out[16]; // @[Core.scala:882:25] wire [14:0] _divSqrt_wdata_bits_bigger_swizzledNaN_T_3 = _divSqrt_io_out[14:0]; // @[Core.scala:882:25] wire [7:0] divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi = {7'h7F, _divSqrt_wdata_bits_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [22:0] divSqrt_wdata_bits_bigger_swizzledNaN_lo = {divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi, _divSqrt_wdata_bits_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [4:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo = {4'hF, _divSqrt_wdata_bits_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [9:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi = {5'h1F, divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] divSqrt_wdata_bits_bigger_swizzledNaN = {divSqrt_wdata_bits_bigger_swizzledNaN_hi, divSqrt_wdata_bits_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [32:0] divSqrt_wdata_bits_bigger = divSqrt_wdata_bits_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] _divSqrt_wdata_bits_T = {32'hFFFFFFFF, divSqrt_wdata_bits_bigger}; // @[FPU.scala:344:8, :398:14] wire _divSqrt_io_inValid_T_5 = com_uops_reg_0_bits_fp_ctrl_typeTagOut == 2'h1; // @[Core.scala:73:25, :883:56] wire _divSqrt_io_inValid_T_6 = com_uops_reg_0_valid & _divSqrt_io_inValid_T_5; // @[Core.scala:73:25, :883:{49,56}] wire _divSqrt_io_inValid_T_7 = _divSqrt_io_inValid_T_6 & com_fp_divsqrt_valid; // @[Core.scala:870:59, :883:{49,73}] wire _divSqrt_io_inValid_T_8 = ~divSqrt_val; // @[Core.scala:872:28, :883:100] wire _divSqrt_io_inValid_T_9 = _divSqrt_io_inValid_T_7 & _divSqrt_io_inValid_T_8; // @[Core.scala:883:{73,97,100}] wire [75:0] _divSqrt_io_a_fractOut_T_1 = {divSqrt_io_a_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] divSqrt_io_a_fractOut_1 = _divSqrt_io_a_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] divSqrt_io_a_expOut_expCode_1 = divSqrt_io_a_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _divSqrt_io_a_expOut_commonCase_T_3 = {1'h0, divSqrt_io_a_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _divSqrt_io_a_expOut_commonCase_T_4 = _divSqrt_io_a_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _divSqrt_io_a_expOut_commonCase_T_5 = {1'h0, _divSqrt_io_a_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] divSqrt_io_a_expOut_commonCase_1 = _divSqrt_io_a_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _divSqrt_io_a_expOut_T_6 = divSqrt_io_a_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _divSqrt_io_a_expOut_T_7 = divSqrt_io_a_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _divSqrt_io_a_expOut_T_8 = _divSqrt_io_a_expOut_T_6 | _divSqrt_io_a_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _divSqrt_io_a_expOut_T_9 = divSqrt_io_a_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _divSqrt_io_a_expOut_T_10 = {divSqrt_io_a_expOut_expCode_1, _divSqrt_io_a_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _divSqrt_io_a_expOut_T_11 = divSqrt_io_a_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] divSqrt_io_a_expOut_1 = _divSqrt_io_a_expOut_T_8 ? _divSqrt_io_a_expOut_T_10 : _divSqrt_io_a_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] divSqrt_io_a_hi_1 = {divSqrt_io_a_sign_1, divSqrt_io_a_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _divSqrt_io_a_T_1 = {divSqrt_io_a_hi_1, divSqrt_io_a_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire [75:0] _divSqrt_io_b_fractOut_T_1 = {divSqrt_io_b_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] divSqrt_io_b_fractOut_1 = _divSqrt_io_b_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] divSqrt_io_b_expOut_expCode_1 = divSqrt_io_b_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _divSqrt_io_b_expOut_commonCase_T_3 = {1'h0, divSqrt_io_b_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _divSqrt_io_b_expOut_commonCase_T_4 = _divSqrt_io_b_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _divSqrt_io_b_expOut_commonCase_T_5 = {1'h0, _divSqrt_io_b_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] divSqrt_io_b_expOut_commonCase_1 = _divSqrt_io_b_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _divSqrt_io_b_expOut_T_6 = divSqrt_io_b_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _divSqrt_io_b_expOut_T_7 = divSqrt_io_b_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _divSqrt_io_b_expOut_T_8 = _divSqrt_io_b_expOut_T_6 | _divSqrt_io_b_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _divSqrt_io_b_expOut_T_9 = divSqrt_io_b_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _divSqrt_io_b_expOut_T_10 = {divSqrt_io_b_expOut_expCode_1, _divSqrt_io_b_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _divSqrt_io_b_expOut_T_11 = divSqrt_io_b_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] divSqrt_io_b_expOut_1 = _divSqrt_io_b_expOut_T_8 ? _divSqrt_io_b_expOut_T_10 : _divSqrt_io_b_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] divSqrt_io_b_hi_1 = {divSqrt_io_b_sign_1, divSqrt_io_b_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _divSqrt_io_b_T_1 = {divSqrt_io_b_hi_1, divSqrt_io_b_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire [32:0] divSqrt_wdata_bits_maskedNaN = _divSqrt_1_io_out & 33'h1EF7FFFFF; // @[Core.scala:882:25] wire [2:0] _divSqrt_wdata_bits_T_1 = _divSqrt_1_io_out[31:29]; // @[Core.scala:882:25] wire _divSqrt_wdata_bits_T_2 = &_divSqrt_wdata_bits_T_1; // @[FPU.scala:249:{25,56}] wire [32:0] _divSqrt_wdata_bits_T_3 = _divSqrt_wdata_bits_T_2 ? divSqrt_wdata_bits_maskedNaN : _divSqrt_1_io_out; // @[Core.scala:882:25] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T_5 = _divSqrt_wdata_bits_T_3[31]; // @[FPU.scala:340:8, :414:10] wire _divSqrt_wdata_bits_bigger_swizzledNaN_T_6 = _divSqrt_wdata_bits_T_3[32]; // @[FPU.scala:342:8, :414:10] wire [30:0] _divSqrt_wdata_bits_bigger_swizzledNaN_T_7 = _divSqrt_wdata_bits_T_3[30:0]; // @[FPU.scala:343:8, :414:10] wire [20:0] divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _divSqrt_wdata_bits_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] divSqrt_wdata_bits_bigger_swizzledNaN_lo_1 = {divSqrt_wdata_bits_bigger_swizzledNaN_lo_hi_1, _divSqrt_wdata_bits_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _divSqrt_wdata_bits_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] divSqrt_wdata_bits_bigger_swizzledNaN_hi_1 = {5'h1F, divSqrt_wdata_bits_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] divSqrt_wdata_bits_bigger_swizzledNaN_1 = {divSqrt_wdata_bits_bigger_swizzledNaN_hi_1, divSqrt_wdata_bits_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] divSqrt_wdata_bits_bigger_1 = divSqrt_wdata_bits_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] _divSqrt_wdata_bits_T_4 = divSqrt_wdata_bits_bigger_1; // @[FPU.scala:344:8, :398:14] wire _divSqrt_io_inValid_T_10 = com_uops_reg_0_bits_fp_ctrl_typeTagOut == 2'h2; // @[Core.scala:73:25, :883:56] wire _divSqrt_io_inValid_T_11 = com_uops_reg_0_valid & _divSqrt_io_inValid_T_10; // @[Core.scala:73:25, :883:{49,56}] wire _divSqrt_io_inValid_T_12 = _divSqrt_io_inValid_T_11 & com_fp_divsqrt_valid; // @[Core.scala:870:59, :883:{49,73}] wire _divSqrt_io_inValid_T_13 = ~divSqrt_val; // @[Core.scala:872:28, :883:100] wire _divSqrt_io_inValid_T_14 = _divSqrt_io_inValid_T_12 & _divSqrt_io_inValid_T_13; // @[Core.scala:883:{73,97,100}] wire [64:0] divSqrt_wdata_bits_maskedNaN_1 = _divSqrt_2_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[Core.scala:882:25] wire [2:0] _divSqrt_wdata_bits_T_5 = _divSqrt_2_io_out[63:61]; // @[Core.scala:882:25] wire _divSqrt_wdata_bits_T_6 = &_divSqrt_wdata_bits_T_5; // @[FPU.scala:249:{25,56}] wire [64:0] _divSqrt_wdata_bits_T_7 = _divSqrt_wdata_bits_T_6 ? divSqrt_wdata_bits_maskedNaN_1 : _divSqrt_2_io_out; // @[Core.scala:882:25] wire _div_io_req_valid_T = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_div; // @[Core.scala:73:25, :907:45] wire _div_io_req_valid_T_1 = ~com_uops_reg_0_bits_xcpt; // @[Core.scala:73:25, :907:81] wire _div_io_req_valid_T_2 = _div_io_req_valid_T & _div_io_req_valid_T_1; // @[Core.scala:907:{45,78,81}] wire [4:0] _div_io_req_bits_tag_T = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] assign _com_bypasses_0_dst_T = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] assign _fp_com_bypasses_0_dst_T = com_uops_reg_0_bits_inst[11:7]; // @[Core.scala:73:25] wire com_rocc_valid = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_rocc; // @[Core.scala:73:25, :923:46] wire _com_retire_0_T = ~com_uops_0_bits_xcpt; // @[Core.scala:74:26, :941:47] wire _com_retire_0_T_1 = com_uops_reg_0_valid & _com_retire_0_T; // @[Core.scala:73:25, :941:{44,47}] wire _com_retire_0_T_2 = ~com_uops_0_bits_needs_replay; // @[Core.scala:74:26, :941:73] wire _com_retire_0_T_3 = _com_retire_0_T_1 & _com_retire_0_T_2; // @[Core.scala:941:{44,70,73}] assign _com_retire_0_T_5 = _com_retire_0_T_3; // @[Core.scala:941:{70,104}] assign com_retire_0 = _com_retire_0_T_5; // @[Core.scala:118:24, :941:104] wire _com_retire_1_T = ~com_uops_1_bits_xcpt; // @[Core.scala:74:26, :941:47] wire _com_retire_1_T_1 = com_uops_reg_1_valid & _com_retire_1_T; // @[Core.scala:73:25, :941:{44,47}] wire _com_retire_1_T_2 = ~com_uops_1_bits_needs_replay; // @[Core.scala:74:26, :941:73] wire _com_retire_1_T_3 = _com_retire_1_T_1 & _com_retire_1_T_2; // @[Core.scala:941:{44,70,73}] wire _com_retire_1_T_4 = ~kill_com_1; // @[Core.scala:112:26, :941:107] assign _com_retire_1_T_5 = _com_retire_1_T_3 & _com_retire_1_T_4; // @[Core.scala:941:{70,104,107}] assign com_retire_1 = _com_retire_1_T_5; // @[Core.scala:118:24, :941:104] wire _csr_io_exception_T_2 = _csr_io_exception_T_1 & com_uops_0_bits_xcpt; // @[Core.scala:74:26, :943:{45,61}] wire _csr_io_exception_T_3 = ~com_uops_0_bits_needs_replay; // @[Core.scala:74:26, :941:73, :943:89] wire _csr_io_exception_T_4 = _csr_io_exception_T_2 & _csr_io_exception_T_3; // @[Core.scala:943:{61,86,89}] wire [1:0] _csr_io_retire_T = {1'h0, com_retire_0} + {1'h0, com_retire_1}; // @[Core.scala:118:24, :945:28] wire [1:0] _csr_io_retire_T_1 = _csr_io_retire_T; // @[Core.scala:945:28] wire [64:0] _debug_irt_reg_T = {1'h0, debug_irt_reg} + {63'h0, _csr_io_retire_T_1}; // @[Core.scala:47:30, :945:28, :946:34] wire [63:0] _debug_irt_reg_T_1 = _debug_irt_reg_T[63:0]; // @[Core.scala:946:34] wire _tval_valid_T = com_uops_0_bits_xcpt_cause == 64'h2; // @[Core.scala:74:26] wire _tval_valid_T_1 = com_uops_0_bits_xcpt_cause == 64'h3; // @[Core.scala:74:26] wire _tval_valid_T_2 = com_uops_0_bits_xcpt_cause == 64'h4; // @[Core.scala:74:26] wire _tval_valid_T_3 = com_uops_0_bits_xcpt_cause == 64'h6; // @[Core.scala:74:26] wire _tval_valid_T_4 = com_uops_0_bits_xcpt_cause == 64'h5; // @[Core.scala:74:26] wire _tval_valid_T_5 = com_uops_0_bits_xcpt_cause == 64'h7; // @[Core.scala:74:26] wire _tval_valid_T_6 = com_uops_0_bits_xcpt_cause == 64'h1; // @[Core.scala:74:26] wire _tval_valid_T_7 = com_uops_0_bits_xcpt_cause == 64'hD; // @[Core.scala:74:26] wire _tval_valid_T_8 = com_uops_0_bits_xcpt_cause == 64'hF; // @[Core.scala:74:26] wire _tval_valid_T_9 = com_uops_0_bits_xcpt_cause == 64'hC; // @[Core.scala:74:26] wire _tval_valid_T_10 = _tval_valid_T | _tval_valid_T_1; // @[package.scala:16:47, :81:59] wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_2; // @[package.scala:16:47, :81:59] wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_3; // @[package.scala:16:47, :81:59] wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_4; // @[package.scala:16:47, :81:59] wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_5; // @[package.scala:16:47, :81:59] wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_6; // @[package.scala:16:47, :81:59] wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_7; // @[package.scala:16:47, :81:59] wire _tval_valid_T_17 = _tval_valid_T_16 | _tval_valid_T_8; // @[package.scala:16:47, :81:59] wire _tval_valid_T_18 = _tval_valid_T_17 | _tval_valid_T_9; // @[package.scala:16:47, :81:59] wire tval_valid = _csr_io_exception_T_4 & _tval_valid_T_18; // @[Core.scala:943:86, :961:37] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[Core.scala:65:{16,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[Core.scala:65:23, :66:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[Core.scala:65:23, :66:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[Core.scala:66:{21,29,34}] wire _csr_io_tval_msb_T_3 = com_uops_reg_0_bits_wdata_bits[39]; // @[Core.scala:66:46, :73:25] wire _csr_io_tval_msb_T_4 = com_uops_reg_0_bits_wdata_bits[38]; // @[Core.scala:66:62, :73:25] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[Core.scala:66:{59,62}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[Core.scala:66:{18,29,46,59}] assign io_imem_sfence_bits_addr_0 = com_uops_reg_0_bits_wdata_bits[38:0]; // @[Core.scala:25:7, :67:16, :73:25] wire [38:0] _csr_io_tval_T = com_uops_reg_0_bits_wdata_bits[38:0]; // @[Core.scala:67:16, :73:25] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[Core.scala:66:18, :67:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[Core.scala:67:8, :961:37, :966:21] wire [11:0] _csr_io_rw_addr_T = com_uops_reg_0_bits_inst[31:20]; // @[Core.scala:73:25, :1028:73] wire [11:0] _csr_io_rw_addr_T_1 = com_uops_reg_0_valid ? _csr_io_rw_addr_T : 12'h0; // @[Core.scala:73:25, :1028:{24,73}] wire _csr_io_rw_cmd_T = ~com_uops_reg_0_bits_xcpt; // @[Core.scala:73:25, :907:81, :1029:57] wire _csr_io_rw_cmd_T_1 = com_uops_reg_0_valid & _csr_io_rw_cmd_T; // @[Core.scala:73:25, :1029:{54,57}] wire [2:0] _csr_io_rw_cmd_T_2 = {~_csr_io_rw_cmd_T_1, 2'h0}; // @[Core.scala:1029:54] wire [2:0] _csr_io_rw_cmd_T_3 = ~_csr_io_rw_cmd_T_2; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_4 = com_uops_reg_0_bits_ctrl_csr & _csr_io_rw_cmd_T_3; // @[Core.scala:73:25] assign io_imem_flush_icache_0 = com_uops_reg_0_valid & ~com_uops_reg_0_bits_xcpt & ~com_uops_reg_0_bits_needs_replay & com_uops_reg_0_bits_ctrl_fence_i | mem_uops_reg_1_valid & mem_uops_reg_1_bits_ctrl_jalr & _csr_io_status_debug | mem_uops_reg_0_valid & mem_uops_reg_0_bits_ctrl_jalr & _csr_io_status_debug; // @[Core.scala:25:7, :52:19, :72:25, :73:25, :735:{33,67,91}, :736:28, :907:81, :1038:{31,61,64,99,137}, :1039:26] wire [4:0] csr_fcsr_flags_0; // @[Core.scala:1045:28] wire [4:0] csr_fcsr_flags_1; // @[Core.scala:1045:28] wire [4:0] csr_fcsr_flags_2; // @[Core.scala:1045:28] wire [4:0] _csr_io_fcsr_flags_bits_T = csr_fcsr_flags_0 | csr_fcsr_flags_1; // @[Core.scala:1045:28, :1047:52] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = _csr_io_fcsr_flags_bits_T | csr_fcsr_flags_2; // @[Core.scala:1045:28, :1047:52] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = _csr_io_fcsr_flags_bits_T_1; // @[Core.scala:1047:52] assign _com_uops_0_bits_xcpt_T = com_uops_reg_0_valid & com_uops_reg_0_bits_xcpt; // @[Core.scala:73:25, :1049:50] assign com_uops_0_bits_xcpt = _com_uops_0_bits_xcpt_T; // @[Core.scala:74:26, :1049:50] assign com_uops_0_bits_needs_replay = com_rocc_valid | _T_280 & io_dmem_s2_nack_0 | _div_io_req_valid_T & ~_div_io_req_ready | com_fp_divsqrt_valid & divSqrt_val | com_uops_reg_0_bits_needs_replay; // @[Core.scala:25:7, :73:25, :74:26, :862:33, :870:59, :872:28, :877:{30,46}, :878:35, :905:19, :907:45, :914:{64,67,86}, :915:35, :923:46, :1032:50, :1052:{66,86}, :1053:37, :1055:90, :1056:37] wire _GEN_113 = com_uops_reg_1_valid & com_uops_reg_1_bits_xcpt | com_uops_reg_1_valid & com_uops_reg_1_bits_ctrl_rocc | _T_285 & io_dmem_s2_nack_0; // @[Core.scala:25:7, :73:25, :74:26, :862:33, :1052:{66,86}, :1053:37, :1055:{33,90}, :1056:37, :1083:{33,63}, :1084:37] wire [4:0] waddr = com_uops_0_bits_inst[11:7]; // @[Core.scala:74:26] wire _T_292 = com_uops_0_bits_ctrl_wxd & com_uops_0_bits_ctrl_mem & io_dmem_s2_hit_0; // @[Core.scala:25:7, :74:26, :1093:{37,66}] assign com_uops_0_bits_wdata_valid = _T_292 | (|com_uops_reg_0_bits_ctrl_csr) | com_uops_reg_0_bits_ctrl_mul | com_uops_reg_0_bits_wdata_valid; // @[Core.scala:73:25, :74:26, :918:40, :919:34, :1032:{39,50}, :1033:34, :1093:{37,66,85}, :1094:36] assign com_uops_0_bits_wdata_bits = _T_292 ? io_dmem_resp_bits_data_0 : (|com_uops_reg_0_bits_ctrl_csr) ? _csr_io_rw_rdata : com_uops_reg_0_bits_ctrl_mul ? _mul_io_resp_bits_data : com_uops_reg_0_bits_wdata_bits; // @[Core.scala:25:7, :52:19, :73:25, :74:26, :535:19, :918:40, :920:33, :1032:{39,50}, :1034:33, :1093:{37,66,85}, :1095:35] assign _com_bypasses_0_valid_T = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_wxd; // @[Core.scala:73:25, :1098:52] assign com_bypasses_0_valid = _com_bypasses_0_valid_T; // @[Core.scala:94:63, :1098:52] assign com_bypasses_0_dst = _com_bypasses_0_dst_T; // @[Core.scala:94:63] wire _T_293 = com_retire_0 & com_uops_0_bits_ctrl_wfd; // @[Core.scala:74:26, :118:24, :1103:16] assign _fp_com_bypasses_0_valid_T = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_wfd; // @[Core.scala:73:25, :1107:55] assign fp_com_bypasses_0_valid = _fp_com_bypasses_0_valid_T; // @[Core.scala:102:66, :1107:55] assign fp_com_bypasses_0_dst = _fp_com_bypasses_0_dst_T; // @[Core.scala:102:66] wire [4:0] waddr_1 = com_uops_1_bits_inst[11:7]; // @[Core.scala:74:26] wire _T_295 = com_uops_1_bits_ctrl_wxd & com_uops_1_bits_ctrl_mem & io_dmem_s2_hit_0; // @[Core.scala:25:7, :74:26, :1093:{37,66}] assign com_uops_1_bits_wdata_valid = _T_295 | com_uops_reg_1_bits_wdata_valid; // @[Core.scala:73:25, :74:26, :1093:{37,66,85}, :1094:36] assign com_uops_1_bits_wdata_bits = _T_295 ? io_dmem_resp_bits_data_0 : com_uops_reg_1_bits_wdata_bits; // @[Core.scala:25:7, :73:25, :74:26, :1093:{37,66,85}, :1095:35] assign _com_bypasses_1_valid_T = com_uops_reg_1_valid & com_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:73:25, :1098:52] assign com_bypasses_1_valid = _com_bypasses_1_valid_T; // @[Core.scala:94:63, :1098:52] assign _com_bypasses_1_dst_T = com_uops_reg_1_bits_inst[11:7]; // @[Core.scala:73:25] assign _fp_com_bypasses_1_dst_T = com_uops_reg_1_bits_inst[11:7]; // @[Core.scala:73:25] assign com_bypasses_1_dst = _com_bypasses_1_dst_T; // @[Core.scala:94:63] wire _T_296 = com_retire_1 & com_uops_1_bits_ctrl_wfd; // @[Core.scala:74:26, :118:24, :1103:16] assign fsboard_clear_0 = _T_296 & waddr_1 == 5'h0 | _T_293 & waddr == 5'h0; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_1 = _T_296 & waddr_1 == 5'h1 | _T_293 & waddr == 5'h1; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_2 = _T_296 & waddr_1 == 5'h2 | _T_293 & waddr == 5'h2; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_3 = _T_296 & waddr_1 == 5'h3 | _T_293 & waddr == 5'h3; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_4 = _T_296 & waddr_1 == 5'h4 | _T_293 & waddr == 5'h4; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_5 = _T_296 & waddr_1 == 5'h5 | _T_293 & waddr == 5'h5; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_6 = _T_296 & waddr_1 == 5'h6 | _T_293 & waddr == 5'h6; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_7 = _T_296 & waddr_1 == 5'h7 | _T_293 & waddr == 5'h7; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_8 = _T_296 & waddr_1 == 5'h8 | _T_293 & waddr == 5'h8; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_9 = _T_296 & waddr_1 == 5'h9 | _T_293 & waddr == 5'h9; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_10 = _T_296 & waddr_1 == 5'hA | _T_293 & waddr == 5'hA; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_11 = _T_296 & waddr_1 == 5'hB | _T_293 & waddr == 5'hB; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_12 = _T_296 & waddr_1 == 5'hC | _T_293 & waddr == 5'hC; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_13 = _T_296 & waddr_1 == 5'hD | _T_293 & waddr == 5'hD; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_14 = _T_296 & waddr_1 == 5'hE | _T_293 & waddr == 5'hE; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_15 = _T_296 & waddr_1 == 5'hF | _T_293 & waddr == 5'hF; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_16 = _T_296 & waddr_1 == 5'h10 | _T_293 & waddr == 5'h10; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_17 = _T_296 & waddr_1 == 5'h11 | _T_293 & waddr == 5'h11; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_18 = _T_296 & waddr_1 == 5'h12 | _T_293 & waddr == 5'h12; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_19 = _T_296 & waddr_1 == 5'h13 | _T_293 & waddr == 5'h13; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_20 = _T_296 & waddr_1 == 5'h14 | _T_293 & waddr == 5'h14; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_21 = _T_296 & waddr_1 == 5'h15 | _T_293 & waddr == 5'h15; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_22 = _T_296 & waddr_1 == 5'h16 | _T_293 & waddr == 5'h16; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_23 = _T_296 & waddr_1 == 5'h17 | _T_293 & waddr == 5'h17; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_24 = _T_296 & waddr_1 == 5'h18 | _T_293 & waddr == 5'h18; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_25 = _T_296 & waddr_1 == 5'h19 | _T_293 & waddr == 5'h19; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_26 = _T_296 & waddr_1 == 5'h1A | _T_293 & waddr == 5'h1A; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_27 = _T_296 & waddr_1 == 5'h1B | _T_293 & waddr == 5'h1B; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_28 = _T_296 & waddr_1 == 5'h1C | _T_293 & waddr == 5'h1C; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_29 = _T_296 & waddr_1 == 5'h1D | _T_293 & waddr == 5'h1D; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_30 = _T_296 & waddr_1 == 5'h1E | _T_293 & waddr == 5'h1E; // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign fsboard_clear_31 = _T_296 & (&waddr_1) | _T_293 & (&waddr); // @[Core.scala:462:31, :1103:{16,46}, :1104:28] assign _fp_com_bypasses_1_valid_T = com_uops_reg_1_valid & com_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:73:25, :1107:55] assign fp_com_bypasses_1_valid = _fp_com_bypasses_1_valid_T; // @[Core.scala:102:66, :1107:55] assign fp_com_bypasses_1_dst = _fp_com_bypasses_1_dst_T; // @[Core.scala:102:66] wire _T_303 = com_uops_reg_0_valid & com_uops_reg_0_bits_ctrl_fp & ~_com_fp_divsqrt_valid_T & com_uops_reg_0_bits_fp_ctrl_toint & ~com_uops_reg_0_bits_xcpt; // @[Core.scala:73:25, :907:81, :1113:{31,63,101}] assign csr_fcsr_flags_0 = _T_303 ? com_uops_reg_0_bits_fexc : 5'h0; // @[Core.scala:73:25, :1045:28, :1046:28, :1113:{31,63,101,132}, :1115:23] assign _io_imem_sfence_bits_rs1_T = com_uops_reg_0_bits_mem_size[0]; // @[Core.scala:73:25, :1125:59] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[Core.scala:25:7, :1125:59] assign _io_imem_sfence_bits_rs2_T = com_uops_reg_0_bits_mem_size[1]; // @[Core.scala:73:25, :1126:59] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[Core.scala:25:7, :1126:59] assign io_imem_sfence_bits_asid_0 = com_uops_reg_0_bits_rs2_data[0]; // @[Core.scala:25:7, :73:25, :1128:28] assign _io_imem_sfence_bits_hv_T = com_uops_reg_0_bits_ctrl_mem_cmd == 5'h15; // @[Core.scala:73:25, :1129:63] assign io_imem_sfence_bits_hv_0 = _io_imem_sfence_bits_hv_T; // @[Core.scala:25:7, :1129:63] assign _io_imem_sfence_bits_hg_T = com_uops_reg_0_bits_ctrl_mem_cmd == 5'h16; // @[Core.scala:73:25, :1130:63] assign io_imem_sfence_bits_hg_0 = _io_imem_sfence_bits_hg_T; // @[Core.scala:25:7, :1130:63] assign io_imem_sfence_valid_0 = com_uops_0_valid & com_uops_0_bits_ctrl_mem & com_uops_0_bits_ctrl_mem_cmd == 5'h14 & ~com_uops_0_bits_xcpt & ~com_uops_0_bits_needs_replay; // @[Core.scala:25:7, :74:26, :941:{47,73}, :1132:{27,54,80}] wire xcpt_4 = com_uops_1_bits_xcpt | _csr_io_eret; // @[Core.scala:52:19, :74:26, :1139:25] wire _GEN_114 = com_uops_1_bits_ctrl_csr == 3'h6; // @[Core.scala:74:26] wire _flush_before_next_T; // @[package.scala:16:47] assign _flush_before_next_T = _GEN_114; // @[package.scala:16:47] wire _flush_before_next_T_5; // @[package.scala:16:47] assign _flush_before_next_T_5 = _GEN_114; // @[package.scala:16:47] wire _flush_before_next_T_1 = &com_uops_1_bits_ctrl_csr; // @[Core.scala:74:26] wire _flush_before_next_T_2 = com_uops_1_bits_ctrl_csr == 3'h5; // @[Core.scala:74:26] wire _flush_before_next_T_3 = _flush_before_next_T | _flush_before_next_T_1; // @[package.scala:16:47, :81:59] wire _flush_before_next_T_4 = _flush_before_next_T_3 | _flush_before_next_T_2; // @[package.scala:16:47, :81:59] wire _flush_before_next_T_6 = &com_uops_1_bits_ctrl_csr; // @[Core.scala:74:26] wire _flush_before_next_T_7 = _flush_before_next_T_5 | _flush_before_next_T_6; // @[package.scala:16:47, :81:59] wire [4:0] _flush_before_next_T_8 = com_uops_1_bits_inst[19:15]; // @[Core.scala:74:26] wire _flush_before_next_T_9 = _flush_before_next_T_8 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire _flush_before_next_T_10 = _flush_before_next_T_7 & _flush_before_next_T_9; // @[MicroOp.scala:69:{48,55}] wire _flush_before_next_T_11 = ~_flush_before_next_T_10; // @[MicroOp.scala:69:48, :70:27] wire _flush_before_next_T_12 = _flush_before_next_T_4 & _flush_before_next_T_11; // @[MicroOp.scala:70:{24,27}] wire flush_before_next = _flush_before_next_T_12 | com_uops_1_bits_flush_pipe; // @[Core.scala:74:26, :1140:41] wire _T_313 = com_uops_1_valid & (com_uops_1_bits_needs_replay | xcpt_4 | flush_before_next); // @[Core.scala:74:26, :1139:25, :1140:41, :1142:{29,40,48}] wire [2:0] _io_imem_redirect_pc_T = com_uops_1_bits_rvc ? 3'h2 : 3'h4; // @[Core.scala:74:26, :1145:85] wire [40:0] _io_imem_redirect_pc_T_1 = {1'h0, com_uops_1_bits_pc} + {38'h0, _io_imem_redirect_pc_T}; // @[Core.scala:74:26, :1145:{80,85}] wire [39:0] _io_imem_redirect_pc_T_2 = _io_imem_redirect_pc_T_1[39:0]; // @[Core.scala:1145:80] wire [39:0] _io_imem_redirect_pc_T_3 = xcpt_4 ? _csr_io_evec : _io_imem_redirect_pc_T_2; // @[Core.scala:52:19, :1139:25, :1145:{53,80}] wire [39:0] _io_imem_redirect_pc_T_4 = com_uops_1_bits_needs_replay ? com_uops_1_bits_pc : _io_imem_redirect_pc_T_3; // @[Core.scala:74:26, :1145:{33,53}] wire xcpt_5 = com_uops_0_bits_xcpt | _csr_io_eret; // @[Core.scala:52:19, :74:26, :1139:25] wire _GEN_115 = com_uops_0_bits_ctrl_csr == 3'h6; // @[Core.scala:74:26] wire _flush_before_next_T_13; // @[package.scala:16:47] assign _flush_before_next_T_13 = _GEN_115; // @[package.scala:16:47] wire _flush_before_next_T_18; // @[package.scala:16:47] assign _flush_before_next_T_18 = _GEN_115; // @[package.scala:16:47] wire _flush_before_next_T_14 = &com_uops_0_bits_ctrl_csr; // @[Core.scala:74:26] wire _flush_before_next_T_15 = com_uops_0_bits_ctrl_csr == 3'h5; // @[Core.scala:74:26] wire _flush_before_next_T_16 = _flush_before_next_T_13 | _flush_before_next_T_14; // @[package.scala:16:47, :81:59] wire _flush_before_next_T_17 = _flush_before_next_T_16 | _flush_before_next_T_15; // @[package.scala:16:47, :81:59] wire _flush_before_next_T_19 = &com_uops_0_bits_ctrl_csr; // @[Core.scala:74:26] wire _flush_before_next_T_20 = _flush_before_next_T_18 | _flush_before_next_T_19; // @[package.scala:16:47, :81:59] wire [4:0] _flush_before_next_T_21 = com_uops_0_bits_inst[19:15]; // @[Core.scala:74:26] wire _flush_before_next_T_22 = _flush_before_next_T_21 == 5'h0; // @[MicroOp.scala:52:17, :69:55] wire _flush_before_next_T_23 = _flush_before_next_T_20 & _flush_before_next_T_22; // @[MicroOp.scala:69:{48,55}] wire _flush_before_next_T_24 = ~_flush_before_next_T_23; // @[MicroOp.scala:69:48, :70:27] wire _flush_before_next_T_25 = _flush_before_next_T_17 & _flush_before_next_T_24; // @[MicroOp.scala:70:{24,27}] wire flush_before_next_1 = _flush_before_next_T_25 | com_uops_0_bits_flush_pipe; // @[Core.scala:74:26, :1140:41] assign kill_com_1 = com_uops_0_valid & (com_uops_0_bits_needs_replay | xcpt_5 | flush_before_next_1); // @[Core.scala:74:26, :112:26, :1139:25, :1140:41, :1142:{29,40,48}] wire _GEN_116 = kill_com_1 | _T_313 | _T_150; // @[Core.scala:112:26, :696:{23,47,66}, :1142:{29,71}, :1143:28] assign io_imem_redirect_val_0 = _GEN_116; // @[Core.scala:25:7, :696:66, :1142:71, :1143:28] assign flush_rrd_ex = _GEN_116; // @[Core.scala:110:30, :696:66, :1142:71, :1143:28] assign io_imem_redirect_flush_0 = kill_com_1 | _T_313 | _T_150 | _io_imem_redirect_flush_T_15; // @[Core.scala:25:7, :112:26, :455:{26,64}, :696:{23,47,66}, :699:28, :1142:{29,71}, :1144:30] wire [2:0] _io_imem_redirect_pc_T_5 = com_uops_0_bits_rvc ? 3'h2 : 3'h4; // @[Core.scala:74:26, :1145:85] wire [40:0] _io_imem_redirect_pc_T_6 = {1'h0, com_uops_0_bits_pc} + {38'h0, _io_imem_redirect_pc_T_5}; // @[Core.scala:74:26, :1145:{80,85}] wire [39:0] _io_imem_redirect_pc_T_7 = _io_imem_redirect_pc_T_6[39:0]; // @[Core.scala:1145:80] wire [39:0] _io_imem_redirect_pc_T_8 = xcpt_5 ? _csr_io_evec : _io_imem_redirect_pc_T_7; // @[Core.scala:52:19, :1139:25, :1145:{53,80}] wire [39:0] _io_imem_redirect_pc_T_9 = com_uops_0_bits_needs_replay ? com_uops_0_bits_pc : _io_imem_redirect_pc_T_8; // @[Core.scala:74:26, :1145:{33,53}] assign io_imem_redirect_pc_0 = kill_com_1 ? _io_imem_redirect_pc_T_9 : _T_313 ? _io_imem_redirect_pc_T_4 : mem_brjmp_npc; // @[Core.scala:25:7, :112:26, :653:31, :692:23, :1142:{29,71}, :1145:{27,33}] assign io_imem_redirect_ras_head_0 = kill_com_1 ? com_uops_0_bits_ras_head : _T_313 ? com_uops_1_bits_ras_head : _io_imem_redirect_ras_head_T_9; // @[Core.scala:25:7, :74:26, :112:26, :693:{29,35}, :1142:{29,71}, :1146:33] assign kill_mem = kill_com_1 | _T_313; // @[Core.scala:111:26, :112:26, :1142:{29,71}, :1148:16] assign com_uops_1_bits_needs_replay = com_uops_reg_1_bits_uses_latealu ? ~io_dmem_s2_hit_0 | _GEN_113 | com_uops_reg_1_bits_needs_replay : _GEN_113 | com_uops_reg_1_bits_needs_replay; // @[Core.scala:25:7, :73:25, :74:26, :1052:86, :1053:37, :1055:90, :1056:37, :1083:63, :1084:37, :1169:48, :1176:{15,32}, :1177:41] wire _GEN_117 = wb_uops_0_valid & wb_uops_0_bits_ctrl_wxd; // @[Core.scala:76:25, :1195:32] wire wen; // @[Core.scala:1195:32] assign wen = _GEN_117; // @[Core.scala:1195:32] assign _wb_bypasses_0_valid_T = _GEN_117; // @[Core.scala:1195:32, :1209:46] wire _T_325 = wen & ~wb_uops_0_bits_wdata_valid; // @[Core.scala:76:25, :1195:32, :1196:{15,18}] wire _T_330 = wen & wb_uops_0_bits_wdata_valid; // @[Core.scala:76:25, :1195:32, :1199:15] wire _GEN_118 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h0; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_119 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_120 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h2; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_121 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h3; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_122 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h4; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_123 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h5; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_124 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h6; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_125 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h7; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_126 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h8; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_127 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h9; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_128 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hA; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_129 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hB; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_130 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hC; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_131 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hD; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_132 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hE; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_133 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'hF; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_134 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h10; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_135 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h11; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_136 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h12; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_137 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h13; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_138 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h14; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_139 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h15; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_140 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h16; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_141 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h17; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_142 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h18; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_143 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h19; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_144 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1A; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_145 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1B; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_146 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1C; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_147 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1D; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_148 = _T_330 & wb_uops_0_bits_inst[11:7] == 5'h1E; // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] wire _GEN_149 = _T_330 & (&(wb_uops_0_bits_inst[11:7])); // @[Core.scala:76:25, :277:21, :1199:{15,35}, :1200:24] assign _wb_bypasses_0_dst_T = wb_uops_0_bits_inst[11:7]; // @[Core.scala:76:25] wire [31:0] _GEN_150 = {31'h0, io_hartid_0}; // @[Core.scala:25:7] assign wb_bypasses_0_valid = _wb_bypasses_0_valid_T; // @[Core.scala:95:62, :1209:46] assign wb_bypasses_0_dst = _wb_bypasses_0_dst_T; // @[Core.scala:95:62] wire _T_332 = wb_uops_reg_1_valid & wb_uops_reg_1_bits_uses_latealu; // @[Core.scala:75:24, :1187:34] assign mem_alu_uops_0_flush_pipe = _T_332 ? wb_uops_reg_1_bits_flush_pipe : mem_uops_reg_1_bits_flush_pipe; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_mem_size = _T_332 ? wb_uops_reg_1_bits_mem_size : mem_uops_reg_1_bits_mem_size; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_ldst = _T_332 ? wb_uops_reg_1_bits_fdivin_ldst : mem_uops_reg_1_bits_fdivin_ldst; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_wen = _T_332 ? wb_uops_reg_1_bits_fdivin_wen : mem_uops_reg_1_bits_fdivin_wen; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_ren1 = _T_332 ? wb_uops_reg_1_bits_fdivin_ren1 : mem_uops_reg_1_bits_fdivin_ren1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_ren2 = _T_332 ? wb_uops_reg_1_bits_fdivin_ren2 : mem_uops_reg_1_bits_fdivin_ren2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_ren3 = _T_332 ? wb_uops_reg_1_bits_fdivin_ren3 : mem_uops_reg_1_bits_fdivin_ren3; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_swap12 = _T_332 ? wb_uops_reg_1_bits_fdivin_swap12 : mem_uops_reg_1_bits_fdivin_swap12; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_swap23 = _T_332 ? wb_uops_reg_1_bits_fdivin_swap23 : mem_uops_reg_1_bits_fdivin_swap23; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_typeTagIn = _T_332 ? wb_uops_reg_1_bits_fdivin_typeTagIn : mem_uops_reg_1_bits_fdivin_typeTagIn; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_typeTagOut = _T_332 ? wb_uops_reg_1_bits_fdivin_typeTagOut : mem_uops_reg_1_bits_fdivin_typeTagOut; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_fromint = _T_332 ? wb_uops_reg_1_bits_fdivin_fromint : mem_uops_reg_1_bits_fdivin_fromint; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_toint = _T_332 ? wb_uops_reg_1_bits_fdivin_toint : mem_uops_reg_1_bits_fdivin_toint; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_fastpipe = _T_332 ? wb_uops_reg_1_bits_fdivin_fastpipe : mem_uops_reg_1_bits_fdivin_fastpipe; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_fma = _T_332 ? wb_uops_reg_1_bits_fdivin_fma : mem_uops_reg_1_bits_fdivin_fma; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_div = _T_332 ? wb_uops_reg_1_bits_fdivin_div : mem_uops_reg_1_bits_fdivin_div; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_sqrt = _T_332 ? wb_uops_reg_1_bits_fdivin_sqrt : mem_uops_reg_1_bits_fdivin_sqrt; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_wflags = _T_332 ? wb_uops_reg_1_bits_fdivin_wflags : mem_uops_reg_1_bits_fdivin_wflags; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_vec = _T_332 ? wb_uops_reg_1_bits_fdivin_vec : mem_uops_reg_1_bits_fdivin_vec; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_rm = _T_332 ? wb_uops_reg_1_bits_fdivin_rm : mem_uops_reg_1_bits_fdivin_rm; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_fmaCmd = _T_332 ? wb_uops_reg_1_bits_fdivin_fmaCmd : mem_uops_reg_1_bits_fdivin_fmaCmd; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_typ = _T_332 ? wb_uops_reg_1_bits_fdivin_typ : mem_uops_reg_1_bits_fdivin_typ; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_fmt = _T_332 ? wb_uops_reg_1_bits_fdivin_fmt : mem_uops_reg_1_bits_fdivin_fmt; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_in1 = _T_332 ? wb_uops_reg_1_bits_fdivin_in1 : mem_uops_reg_1_bits_fdivin_in1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_in2 = _T_332 ? wb_uops_reg_1_bits_fdivin_in2 : mem_uops_reg_1_bits_fdivin_in2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fdivin_in3 = _T_332 ? wb_uops_reg_1_bits_fdivin_in3 : mem_uops_reg_1_bits_fdivin_in3; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fexc = _T_332 ? wb_uops_reg_1_bits_fexc : mem_uops_reg_1_bits_fexc; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fra3 = _T_332 ? wb_uops_reg_1_bits_fra3 : mem_uops_reg_1_bits_fra3; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fra2 = _T_332 ? wb_uops_reg_1_bits_fra2 : mem_uops_reg_1_bits_fra2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fra1 = _T_332 ? wb_uops_reg_1_bits_fra1 : mem_uops_reg_1_bits_fra1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_wdata_valid = _T_332 ? wb_uops_reg_1_bits_wdata_valid : mem_uops_reg_1_bits_wdata_valid; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_wdata_bits = _T_332 ? wb_uops_reg_1_bits_wdata_bits : mem_uops_reg_1_bits_wdata_bits; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_uses_latealu = _T_332 ? wb_uops_reg_1_bits_uses_latealu : mem_uops_reg_1_bits_uses_latealu; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_uses_memalu = _T_332 ? wb_uops_reg_1_bits_uses_memalu : mem_uops_reg_1_bits_uses_memalu; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_rs3_data = _T_332 ? wb_uops_reg_1_bits_rs3_data : mem_uops_reg_1_bits_rs3_data; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_rs2_data = _T_332 ? wb_uops_reg_1_bits_rs2_data : mem_uops_reg_1_bits_inst[24:20] == mem_uops_reg_0_bits_inst[11:7] ? mem_uops_reg_0_bits_wdata_bits : mem_uops_reg_1_bits_rs2_data; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :818:{38,67}, :819:36, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_rs1_data = _T_332 ? wb_uops_reg_1_bits_rs1_data : mem_uops_reg_1_bits_inst[19:15] == mem_uops_reg_0_bits_inst[11:7] ? mem_uops_reg_0_bits_wdata_bits : mem_uops_reg_1_bits_rs1_data; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :815:{38,67}, :816:36, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_needs_replay = _T_332 ? wb_uops_reg_1_bits_needs_replay : mem_uops_reg_1_bits_needs_replay; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_xcpt_cause = _T_332 ? wb_uops_reg_1_bits_xcpt_cause : mem_uops_reg_1_bits_xcpt_cause; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_xcpt = _T_332 ? wb_uops_reg_1_bits_xcpt : mem_uops_reg_1_bits_xcpt; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_taken = _T_332 ? wb_uops_reg_1_bits_taken : mem_uops_reg_1_bits_taken; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ras_head = _T_332 ? wb_uops_reg_1_bits_ras_head : mem_uops_reg_1_bits_ras_head; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_next_pc_valid = _T_332 ? wb_uops_reg_1_bits_next_pc_valid : mem_uops_reg_1_bits_next_pc_valid; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_next_pc_bits = _T_332 ? wb_uops_reg_1_bits_next_pc_bits : mem_uops_reg_1_bits_next_pc_bits; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_sfb_shadow = _T_332 ? wb_uops_reg_1_bits_sfb_shadow : mem_uops_reg_1_bits_sfb_shadow; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_sfb_br = _T_332 ? wb_uops_reg_1_bits_sfb_br : mem_uops_reg_1_bits_sfb_br; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_valid = _T_332 ? wb_uops_reg_1_bits_btb_resp_valid : mem_uops_reg_1_bits_btb_resp_valid; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_cfiType = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_cfiType : mem_uops_reg_1_bits_btb_resp_bits_cfiType; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_taken = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_taken : mem_uops_reg_1_bits_btb_resp_bits_taken; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_mask = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_mask : mem_uops_reg_1_bits_btb_resp_bits_mask; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_bridx = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_bridx : mem_uops_reg_1_bits_btb_resp_bits_bridx; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_target = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_target : mem_uops_reg_1_bits_btb_resp_bits_target; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_entry = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_entry : mem_uops_reg_1_bits_btb_resp_bits_entry; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_bht_history = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_bht_history : mem_uops_reg_1_bits_btb_resp_bits_bht_history; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_btb_resp_bits_bht_value = _T_332 ? wb_uops_reg_1_bits_btb_resp_bits_bht_value : mem_uops_reg_1_bits_btb_resp_bits_bht_value; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_sets_vcfg = _T_332 ? wb_uops_reg_1_bits_sets_vcfg : mem_uops_reg_1_bits_sets_vcfg; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_rvc = _T_332 ? wb_uops_reg_1_bits_rvc : mem_uops_reg_1_bits_rvc; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_ldst = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_ldst : mem_uops_reg_1_bits_fp_ctrl_ldst; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_wen = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_wen : mem_uops_reg_1_bits_fp_ctrl_wen; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_ren1 = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_ren1 : mem_uops_reg_1_bits_fp_ctrl_ren1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_ren2 = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_ren2 : mem_uops_reg_1_bits_fp_ctrl_ren2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_ren3 = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_ren3 : mem_uops_reg_1_bits_fp_ctrl_ren3; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_swap12 = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_swap12 : mem_uops_reg_1_bits_fp_ctrl_swap12; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_swap23 = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_swap23 : mem_uops_reg_1_bits_fp_ctrl_swap23; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_typeTagIn = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_typeTagIn : mem_uops_reg_1_bits_fp_ctrl_typeTagIn; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_typeTagOut = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_typeTagOut : mem_uops_reg_1_bits_fp_ctrl_typeTagOut; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_fromint = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_fromint : mem_uops_reg_1_bits_fp_ctrl_fromint; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_toint = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_toint : mem_uops_reg_1_bits_fp_ctrl_toint; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_fastpipe = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_fastpipe : mem_uops_reg_1_bits_fp_ctrl_fastpipe; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_fma = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_fma : mem_uops_reg_1_bits_fp_ctrl_fma; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_div = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_div : mem_uops_reg_1_bits_fp_ctrl_div; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_sqrt = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_sqrt : mem_uops_reg_1_bits_fp_ctrl_sqrt; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_wflags = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_wflags : mem_uops_reg_1_bits_fp_ctrl_wflags; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_fp_ctrl_vec = _T_332 ? wb_uops_reg_1_bits_fp_ctrl_vec : mem_uops_reg_1_bits_fp_ctrl_vec; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_legal = _T_332 ? wb_uops_reg_1_bits_ctrl_legal : mem_uops_reg_1_bits_ctrl_legal; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_fp = _T_332 ? wb_uops_reg_1_bits_ctrl_fp : mem_uops_reg_1_bits_ctrl_fp; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rocc = _T_332 ? wb_uops_reg_1_bits_ctrl_rocc : mem_uops_reg_1_bits_ctrl_rocc; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_branch = _T_332 ? wb_uops_reg_1_bits_ctrl_branch : mem_uops_reg_1_bits_ctrl_branch; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_jal = _T_332 ? wb_uops_reg_1_bits_ctrl_jal : mem_uops_reg_1_bits_ctrl_jal; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_jalr = _T_332 ? wb_uops_reg_1_bits_ctrl_jalr : mem_uops_reg_1_bits_ctrl_jalr; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rxs2 = _T_332 ? wb_uops_reg_1_bits_ctrl_rxs2 : mem_uops_reg_1_bits_ctrl_rxs2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rxs1 = _T_332 ? wb_uops_reg_1_bits_ctrl_rxs1 : mem_uops_reg_1_bits_ctrl_rxs1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_sel_alu2 = _T_332 ? wb_uops_reg_1_bits_ctrl_sel_alu2 : mem_uops_reg_1_bits_ctrl_sel_alu2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_sel_alu1 = _T_332 ? wb_uops_reg_1_bits_ctrl_sel_alu1 : mem_uops_reg_1_bits_ctrl_sel_alu1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_sel_imm = _T_332 ? wb_uops_reg_1_bits_ctrl_sel_imm : mem_uops_reg_1_bits_ctrl_sel_imm; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_alu_dw = _T_332 ? wb_uops_reg_1_bits_ctrl_alu_dw : mem_uops_reg_1_bits_ctrl_alu_dw; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_alu_fn = _T_332 ? wb_uops_reg_1_bits_ctrl_alu_fn : mem_uops_reg_1_bits_ctrl_alu_fn; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_mem = _T_332 ? wb_uops_reg_1_bits_ctrl_mem : mem_uops_reg_1_bits_ctrl_mem; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_mem_cmd = _T_332 ? wb_uops_reg_1_bits_ctrl_mem_cmd : mem_uops_reg_1_bits_ctrl_mem_cmd; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rfs1 = _T_332 ? wb_uops_reg_1_bits_ctrl_rfs1 : mem_uops_reg_1_bits_ctrl_rfs1; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rfs2 = _T_332 ? wb_uops_reg_1_bits_ctrl_rfs2 : mem_uops_reg_1_bits_ctrl_rfs2; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_rfs3 = _T_332 ? wb_uops_reg_1_bits_ctrl_rfs3 : mem_uops_reg_1_bits_ctrl_rfs3; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_wfd = _T_332 ? wb_uops_reg_1_bits_ctrl_wfd : mem_uops_reg_1_bits_ctrl_wfd; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_mul = _T_332 ? wb_uops_reg_1_bits_ctrl_mul : mem_uops_reg_1_bits_ctrl_mul; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_div = _T_332 ? wb_uops_reg_1_bits_ctrl_div : mem_uops_reg_1_bits_ctrl_div; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_wxd = _T_332 ? wb_uops_reg_1_bits_ctrl_wxd : mem_uops_reg_1_bits_ctrl_wxd; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_csr = _T_332 ? wb_uops_reg_1_bits_ctrl_csr : mem_uops_reg_1_bits_ctrl_csr; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_fence_i = _T_332 ? wb_uops_reg_1_bits_ctrl_fence_i : mem_uops_reg_1_bits_ctrl_fence_i; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_fence = _T_332 ? wb_uops_reg_1_bits_ctrl_fence : mem_uops_reg_1_bits_ctrl_fence; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_amo = _T_332 ? wb_uops_reg_1_bits_ctrl_amo : mem_uops_reg_1_bits_ctrl_amo; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_dp = _T_332 ? wb_uops_reg_1_bits_ctrl_dp : mem_uops_reg_1_bits_ctrl_dp; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_ctrl_vec = _T_332 ? wb_uops_reg_1_bits_ctrl_vec : mem_uops_reg_1_bits_ctrl_vec; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_edge_inst = _T_332 ? wb_uops_reg_1_bits_edge_inst : mem_uops_reg_1_bits_edge_inst; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_pc = _T_332 ? wb_uops_reg_1_bits_pc : mem_uops_reg_1_bits_pc; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_raw_inst = _T_332 ? wb_uops_reg_1_bits_raw_inst : mem_uops_reg_1_bits_raw_inst; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign mem_alu_uops_0_inst = _T_332 ? wb_uops_reg_1_bits_inst : mem_uops_reg_1_bits_inst; // @[Core.scala:72:25, :75:24, :809:69, :814:25, :1187:{34,71}, :1188:27] assign wb_uops_1_bits_wdata_valid = _T_332 | wb_uops_reg_1_bits_wdata_valid; // @[Core.scala:75:24, :76:25, :1187:{34,71}, :1189:37] assign wb_uops_1_bits_wdata_bits = _T_332 ? _mem_alus_0_io_out : wb_uops_reg_1_bits_wdata_bits; // @[Core.scala:75:24, :76:25, :810:67, :1187:{34,71}, :1190:36] wire _GEN_151 = wb_uops_1_valid & wb_uops_1_bits_ctrl_wxd; // @[Core.scala:76:25, :1195:32] wire wen_1; // @[Core.scala:1195:32] assign wen_1 = _GEN_151; // @[Core.scala:1195:32] assign _wb_bypasses_1_valid_T = _GEN_151; // @[Core.scala:1195:32, :1209:46] wire _T_334 = wen_1 & ~wb_uops_1_bits_wdata_valid; // @[Core.scala:76:25, :1195:32, :1196:{15,18}] assign isboard_clear_0 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h0 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h0; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_1 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_2 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h2 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h2; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_3 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h3 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h3; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_4 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h4 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h4; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_5 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h5 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h5; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_6 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h6 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h6; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_7 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h7 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h7; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_8 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h8 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h8; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_9 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h9 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h9; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_10 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hA | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hA; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_11 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hB | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hB; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_12 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hC | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hC; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_13 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hD | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hD; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_14 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hE | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hE; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_15 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'hF | _T_325 & wb_uops_0_bits_inst[11:7] == 5'hF; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_16 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h10 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h10; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_17 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h11 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h11; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_18 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h12 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h12; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_19 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h13 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h13; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_20 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h14 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h14; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_21 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h15 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h15; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_22 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h16 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h16; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_23 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h17 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h17; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_24 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h18 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h18; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_25 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h19 | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h19; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_26 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1A | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1A; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_27 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1B | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1B; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_28 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1C | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1C; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_29 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1D | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1D; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_30 = _T_334 & wb_uops_1_bits_inst[11:7] == 5'h1E | _T_325 & wb_uops_0_bits_inst[11:7] == 5'h1E; // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] assign isboard_clear_31 = _T_334 & (&(wb_uops_1_bits_inst[11:7])) | _T_325 & (&(wb_uops_0_bits_inst[11:7])); // @[Core.scala:76:25, :279:31, :1196:{15,36}, :1197:29] wire _T_339 = wen_1 & wb_uops_1_bits_wdata_valid; // @[Core.scala:76:25, :1195:32, :1199:15] wire _GEN_152 = wb_uops_1_bits_inst[11:7] == 5'h0; // @[Core.scala:76:25, :1200:24] wire _GEN_153 = wb_uops_1_bits_inst[11:7] == 5'h1; // @[Core.scala:76:25, :1200:24] wire _GEN_154 = wb_uops_1_bits_inst[11:7] == 5'h2; // @[Core.scala:76:25, :1200:24] wire _GEN_155 = wb_uops_1_bits_inst[11:7] == 5'h3; // @[Core.scala:76:25, :1200:24] wire _GEN_156 = wb_uops_1_bits_inst[11:7] == 5'h4; // @[Core.scala:76:25, :1200:24] wire _GEN_157 = wb_uops_1_bits_inst[11:7] == 5'h5; // @[Core.scala:76:25, :1200:24] wire _GEN_158 = wb_uops_1_bits_inst[11:7] == 5'h6; // @[Core.scala:76:25, :1200:24] wire _GEN_159 = wb_uops_1_bits_inst[11:7] == 5'h7; // @[Core.scala:76:25, :1200:24] wire _GEN_160 = wb_uops_1_bits_inst[11:7] == 5'h8; // @[Core.scala:76:25, :1200:24] wire _GEN_161 = wb_uops_1_bits_inst[11:7] == 5'h9; // @[Core.scala:76:25, :1200:24] wire _GEN_162 = wb_uops_1_bits_inst[11:7] == 5'hA; // @[Core.scala:76:25, :1200:24] wire _GEN_163 = wb_uops_1_bits_inst[11:7] == 5'hB; // @[Core.scala:76:25, :1200:24] wire _GEN_164 = wb_uops_1_bits_inst[11:7] == 5'hC; // @[Core.scala:76:25, :1200:24] wire _GEN_165 = wb_uops_1_bits_inst[11:7] == 5'hD; // @[Core.scala:76:25, :1200:24] wire _GEN_166 = wb_uops_1_bits_inst[11:7] == 5'hE; // @[Core.scala:76:25, :1200:24] wire _GEN_167 = wb_uops_1_bits_inst[11:7] == 5'hF; // @[Core.scala:76:25, :1200:24] wire _GEN_168 = wb_uops_1_bits_inst[11:7] == 5'h10; // @[Core.scala:76:25, :1200:24] wire _GEN_169 = wb_uops_1_bits_inst[11:7] == 5'h11; // @[Core.scala:76:25, :1200:24] wire _GEN_170 = wb_uops_1_bits_inst[11:7] == 5'h12; // @[Core.scala:76:25, :1200:24] wire _GEN_171 = wb_uops_1_bits_inst[11:7] == 5'h13; // @[Core.scala:76:25, :1200:24] wire _GEN_172 = wb_uops_1_bits_inst[11:7] == 5'h14; // @[Core.scala:76:25, :1200:24] wire _GEN_173 = wb_uops_1_bits_inst[11:7] == 5'h15; // @[Core.scala:76:25, :1200:24] wire _GEN_174 = wb_uops_1_bits_inst[11:7] == 5'h16; // @[Core.scala:76:25, :1200:24] wire _GEN_175 = wb_uops_1_bits_inst[11:7] == 5'h17; // @[Core.scala:76:25, :1200:24] wire _GEN_176 = wb_uops_1_bits_inst[11:7] == 5'h18; // @[Core.scala:76:25, :1200:24] wire _GEN_177 = wb_uops_1_bits_inst[11:7] == 5'h19; // @[Core.scala:76:25, :1200:24] wire _GEN_178 = wb_uops_1_bits_inst[11:7] == 5'h1A; // @[Core.scala:76:25, :1200:24] wire _GEN_179 = wb_uops_1_bits_inst[11:7] == 5'h1B; // @[Core.scala:76:25, :1200:24] wire _GEN_180 = wb_uops_1_bits_inst[11:7] == 5'h1C; // @[Core.scala:76:25, :1200:24] wire _GEN_181 = wb_uops_1_bits_inst[11:7] == 5'h1D; // @[Core.scala:76:25, :1200:24] wire _GEN_182 = wb_uops_1_bits_inst[11:7] == 5'h1E; // @[Core.scala:76:25, :1200:24] assign _wb_bypasses_1_dst_T = wb_uops_1_bits_inst[11:7]; // @[Core.scala:76:25] assign wb_bypasses_1_valid = _wb_bypasses_1_valid_T; // @[Core.scala:95:62, :1209:46] assign wb_bypasses_1_dst = _wb_bypasses_1_dst_T; // @[Core.scala:95:62] wire _dmem_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[Core.scala:25:7, :1217:40] wire dmem_fpu = io_dmem_resp_bits_tag_0[0]; // @[Core.scala:25:7, :1217:40, :1218:40] wire dmem_xpu = ~_dmem_xpu_T; // @[Core.scala:1217:{18,40}] wire [4:0] dmem_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[Core.scala:25:7, :1219:41] wire [4:0] _fp_load_addr_T = io_dmem_resp_bits_tag_0[5:1]; // @[Core.scala:25:7, :1219:41, :1270:53] wire _ll_arb_io_in_0_valid_T = ~io_dmem_s2_hit_0; // @[Core.scala:25:7, :1231:59] wire _ll_arb_io_in_0_valid_T_1 = _ll_arb_io_in_0_valid_T | io_dmem_s2_kill_0; // @[Core.scala:25:7, :1231:{59,75}] wire _ll_arb_io_in_0_valid_T_2 = io_dmem_resp_valid_0 & _ll_arb_io_in_0_valid_T_1; // @[Core.scala:25:7, :1231:{55,75}] wire _ll_arb_io_in_0_valid_T_3 = _ll_arb_io_in_0_valid_T_2 & io_dmem_resp_bits_has_data_0; // @[Core.scala:25:7, :1231:{55,95}] wire _ll_arb_io_in_0_valid_T_4 = _ll_arb_io_in_0_valid_T_3 & dmem_xpu; // @[Core.scala:1217:18, :1231:{95,125}] reg ll_arb_io_in_0_valid_REG; // @[Core.scala:1231:35] reg [4:0] ll_arb_io_in_0_bits_waddr_r; // @[Core.scala:1232:42] reg [63:0] ll_arb_io_in_0_bits_wdata_r; // @[Core.scala:1233:42] wire _GEN_183 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h0; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_184 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_185 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h2; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_186 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h3; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_187 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h4; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_188 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h5; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_189 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h6; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_190 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h7; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_191 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h8; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_192 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h9; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_193 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hA; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_194 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hB; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_195 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hC; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_196 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hD; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_197 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hE; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_198 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'hF; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_199 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h10; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_200 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h11; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_201 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h12; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_202 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h13; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_203 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h14; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_204 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h15; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_205 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h16; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_206 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h17; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_207 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h18; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_208 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h19; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_209 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1A; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_210 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1B; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_211 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1C; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_212 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1D; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_213 = _ll_arb_io_out_valid & _ll_arb_io_out_bits_waddr == 5'h1E; // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] wire _GEN_214 = _ll_arb_io_out_valid & (&_ll_arb_io_out_bits_waddr); // @[Core.scala:1199:35, :1228:22, :1260:17, :1261:24] assign isboard_set_0 = _GEN_183 | _T_339 & _GEN_152 | _GEN_118; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_1 = _GEN_184 | _T_339 & _GEN_153 | _GEN_119; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_2 = _GEN_185 | _T_339 & _GEN_154 | _GEN_120; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_3 = _GEN_186 | _T_339 & _GEN_155 | _GEN_121; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_4 = _GEN_187 | _T_339 & _GEN_156 | _GEN_122; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_5 = _GEN_188 | _T_339 & _GEN_157 | _GEN_123; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_6 = _GEN_189 | _T_339 & _GEN_158 | _GEN_124; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_7 = _GEN_190 | _T_339 & _GEN_159 | _GEN_125; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_8 = _GEN_191 | _T_339 & _GEN_160 | _GEN_126; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_9 = _GEN_192 | _T_339 & _GEN_161 | _GEN_127; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_10 = _GEN_193 | _T_339 & _GEN_162 | _GEN_128; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_11 = _GEN_194 | _T_339 & _GEN_163 | _GEN_129; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_12 = _GEN_195 | _T_339 & _GEN_164 | _GEN_130; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_13 = _GEN_196 | _T_339 & _GEN_165 | _GEN_131; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_14 = _GEN_197 | _T_339 & _GEN_166 | _GEN_132; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_15 = _GEN_198 | _T_339 & _GEN_167 | _GEN_133; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_16 = _GEN_199 | _T_339 & _GEN_168 | _GEN_134; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_17 = _GEN_200 | _T_339 & _GEN_169 | _GEN_135; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_18 = _GEN_201 | _T_339 & _GEN_170 | _GEN_136; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_19 = _GEN_202 | _T_339 & _GEN_171 | _GEN_137; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_20 = _GEN_203 | _T_339 & _GEN_172 | _GEN_138; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_21 = _GEN_204 | _T_339 & _GEN_173 | _GEN_139; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_22 = _GEN_205 | _T_339 & _GEN_174 | _GEN_140; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_23 = _GEN_206 | _T_339 & _GEN_175 | _GEN_141; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_24 = _GEN_207 | _T_339 & _GEN_176 | _GEN_142; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_25 = _GEN_208 | _T_339 & _GEN_177 | _GEN_143; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_26 = _GEN_209 | _T_339 & _GEN_178 | _GEN_144; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_27 = _GEN_210 | _T_339 & _GEN_179 | _GEN_145; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_28 = _GEN_211 | _T_339 & _GEN_180 | _GEN_146; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_29 = _GEN_212 | _T_339 & _GEN_181 | _GEN_147; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_30 = _GEN_213 | _T_339 & _GEN_182 | _GEN_148; // @[Core.scala:277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] assign isboard_set_31 = _GEN_214 | _T_339 & (&(wb_uops_1_bits_inst[11:7])) | _GEN_149; // @[Core.scala:76:25, :277:21, :280:29, :1199:{15,35}, :1200:24, :1201:27, :1260:17, :1261:24, :1262:27] wire _fp_load_val_T = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[Core.scala:25:7, :1268:48] wire _fp_load_val_T_1 = _fp_load_val_T & dmem_fpu; // @[Core.scala:1218:40, :1268:{48,78}] reg fp_load_val; // @[Core.scala:1268:28] wire [2:0] _fp_load_type_T = {1'h0, io_dmem_resp_bits_size_0} - 3'h1; // @[Core.scala:25:7, :1269:55] wire [1:0] _fp_load_type_T_1 = _fp_load_type_T[1:0]; // @[Core.scala:1269:55] reg [1:0] fp_load_type; // @[Core.scala:1269:31] reg [4:0] fp_load_addr; // @[Core.scala:1270:31] reg [63:0] fp_load_data; // @[Core.scala:1271:31] wire ll_fp_wval; // @[Core.scala:1273:28] wire [64:0] ll_fp_wdata; // @[Core.scala:1274:29] wire [4:0] ll_fp_waddr; // @[Core.scala:1275:29] wire _ll_fp_wdata_T = fp_load_type == 2'h1; // @[Core.scala:1269:31] wire [63:0] _ll_fp_wdata_T_1 = _ll_fp_wdata_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}] wire _ll_fp_wdata_T_2 = fp_load_type == 2'h2; // @[Core.scala:1269:31] wire [63:0] _ll_fp_wdata_T_3 = _ll_fp_wdata_T_2 ? 64'h0 : _ll_fp_wdata_T_1; // @[package.scala:39:{76,86}] wire _ll_fp_wdata_T_4 = &fp_load_type; // @[Core.scala:1269:31] wire [63:0] _ll_fp_wdata_T_5 = _ll_fp_wdata_T_4 ? 64'h0 : _ll_fp_wdata_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ll_fp_wdata_T_6 = _ll_fp_wdata_T_5 | fp_load_data; // @[Core.scala:1271:31] wire ll_fp_wdata_rawIn_sign = _ll_fp_wdata_T_6[63]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_sign_0 = ll_fp_wdata_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [10:0] ll_fp_wdata_rawIn_expIn = _ll_fp_wdata_T_6[62:52]; // @[FPU.scala:431:23] wire [51:0] ll_fp_wdata_rawIn_fractIn = _ll_fp_wdata_T_6[51:0]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_isZeroExpIn = ll_fp_wdata_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire ll_fp_wdata_rawIn_isZeroFractIn = ll_fp_wdata_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _ll_fp_wdata_rawIn_normDist_T = ll_fp_wdata_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_1 = ll_fp_wdata_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_2 = ll_fp_wdata_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_3 = ll_fp_wdata_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_4 = ll_fp_wdata_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_5 = ll_fp_wdata_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_6 = ll_fp_wdata_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_7 = ll_fp_wdata_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_8 = ll_fp_wdata_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_9 = ll_fp_wdata_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_10 = ll_fp_wdata_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_11 = ll_fp_wdata_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_12 = ll_fp_wdata_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_13 = ll_fp_wdata_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_14 = ll_fp_wdata_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_15 = ll_fp_wdata_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_16 = ll_fp_wdata_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_17 = ll_fp_wdata_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_18 = ll_fp_wdata_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_19 = ll_fp_wdata_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_20 = ll_fp_wdata_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_21 = ll_fp_wdata_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_22 = ll_fp_wdata_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_23 = ll_fp_wdata_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_24 = ll_fp_wdata_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_25 = ll_fp_wdata_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_26 = ll_fp_wdata_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_27 = ll_fp_wdata_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_28 = ll_fp_wdata_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_29 = ll_fp_wdata_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_30 = ll_fp_wdata_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_31 = ll_fp_wdata_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_32 = ll_fp_wdata_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_33 = ll_fp_wdata_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_34 = ll_fp_wdata_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_35 = ll_fp_wdata_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_36 = ll_fp_wdata_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_37 = ll_fp_wdata_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_38 = ll_fp_wdata_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_39 = ll_fp_wdata_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_40 = ll_fp_wdata_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_41 = ll_fp_wdata_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_42 = ll_fp_wdata_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_43 = ll_fp_wdata_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_44 = ll_fp_wdata_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_45 = ll_fp_wdata_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_46 = ll_fp_wdata_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_47 = ll_fp_wdata_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_48 = ll_fp_wdata_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_49 = ll_fp_wdata_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_50 = ll_fp_wdata_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_51 = ll_fp_wdata_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_52 = {5'h19, ~_ll_fp_wdata_rawIn_normDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_53 = _ll_fp_wdata_rawIn_normDist_T_2 ? 6'h31 : _ll_fp_wdata_rawIn_normDist_T_52; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_54 = _ll_fp_wdata_rawIn_normDist_T_3 ? 6'h30 : _ll_fp_wdata_rawIn_normDist_T_53; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_55 = _ll_fp_wdata_rawIn_normDist_T_4 ? 6'h2F : _ll_fp_wdata_rawIn_normDist_T_54; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_56 = _ll_fp_wdata_rawIn_normDist_T_5 ? 6'h2E : _ll_fp_wdata_rawIn_normDist_T_55; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_57 = _ll_fp_wdata_rawIn_normDist_T_6 ? 6'h2D : _ll_fp_wdata_rawIn_normDist_T_56; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_58 = _ll_fp_wdata_rawIn_normDist_T_7 ? 6'h2C : _ll_fp_wdata_rawIn_normDist_T_57; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_59 = _ll_fp_wdata_rawIn_normDist_T_8 ? 6'h2B : _ll_fp_wdata_rawIn_normDist_T_58; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_60 = _ll_fp_wdata_rawIn_normDist_T_9 ? 6'h2A : _ll_fp_wdata_rawIn_normDist_T_59; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_61 = _ll_fp_wdata_rawIn_normDist_T_10 ? 6'h29 : _ll_fp_wdata_rawIn_normDist_T_60; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_62 = _ll_fp_wdata_rawIn_normDist_T_11 ? 6'h28 : _ll_fp_wdata_rawIn_normDist_T_61; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_63 = _ll_fp_wdata_rawIn_normDist_T_12 ? 6'h27 : _ll_fp_wdata_rawIn_normDist_T_62; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_64 = _ll_fp_wdata_rawIn_normDist_T_13 ? 6'h26 : _ll_fp_wdata_rawIn_normDist_T_63; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_65 = _ll_fp_wdata_rawIn_normDist_T_14 ? 6'h25 : _ll_fp_wdata_rawIn_normDist_T_64; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_66 = _ll_fp_wdata_rawIn_normDist_T_15 ? 6'h24 : _ll_fp_wdata_rawIn_normDist_T_65; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_67 = _ll_fp_wdata_rawIn_normDist_T_16 ? 6'h23 : _ll_fp_wdata_rawIn_normDist_T_66; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_68 = _ll_fp_wdata_rawIn_normDist_T_17 ? 6'h22 : _ll_fp_wdata_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_69 = _ll_fp_wdata_rawIn_normDist_T_18 ? 6'h21 : _ll_fp_wdata_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_70 = _ll_fp_wdata_rawIn_normDist_T_19 ? 6'h20 : _ll_fp_wdata_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_71 = _ll_fp_wdata_rawIn_normDist_T_20 ? 6'h1F : _ll_fp_wdata_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_72 = _ll_fp_wdata_rawIn_normDist_T_21 ? 6'h1E : _ll_fp_wdata_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_73 = _ll_fp_wdata_rawIn_normDist_T_22 ? 6'h1D : _ll_fp_wdata_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_74 = _ll_fp_wdata_rawIn_normDist_T_23 ? 6'h1C : _ll_fp_wdata_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_75 = _ll_fp_wdata_rawIn_normDist_T_24 ? 6'h1B : _ll_fp_wdata_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_76 = _ll_fp_wdata_rawIn_normDist_T_25 ? 6'h1A : _ll_fp_wdata_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_77 = _ll_fp_wdata_rawIn_normDist_T_26 ? 6'h19 : _ll_fp_wdata_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_78 = _ll_fp_wdata_rawIn_normDist_T_27 ? 6'h18 : _ll_fp_wdata_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_79 = _ll_fp_wdata_rawIn_normDist_T_28 ? 6'h17 : _ll_fp_wdata_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_80 = _ll_fp_wdata_rawIn_normDist_T_29 ? 6'h16 : _ll_fp_wdata_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_81 = _ll_fp_wdata_rawIn_normDist_T_30 ? 6'h15 : _ll_fp_wdata_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_82 = _ll_fp_wdata_rawIn_normDist_T_31 ? 6'h14 : _ll_fp_wdata_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_83 = _ll_fp_wdata_rawIn_normDist_T_32 ? 6'h13 : _ll_fp_wdata_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_84 = _ll_fp_wdata_rawIn_normDist_T_33 ? 6'h12 : _ll_fp_wdata_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_85 = _ll_fp_wdata_rawIn_normDist_T_34 ? 6'h11 : _ll_fp_wdata_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_86 = _ll_fp_wdata_rawIn_normDist_T_35 ? 6'h10 : _ll_fp_wdata_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_87 = _ll_fp_wdata_rawIn_normDist_T_36 ? 6'hF : _ll_fp_wdata_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_88 = _ll_fp_wdata_rawIn_normDist_T_37 ? 6'hE : _ll_fp_wdata_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_89 = _ll_fp_wdata_rawIn_normDist_T_38 ? 6'hD : _ll_fp_wdata_rawIn_normDist_T_88; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_90 = _ll_fp_wdata_rawIn_normDist_T_39 ? 6'hC : _ll_fp_wdata_rawIn_normDist_T_89; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_91 = _ll_fp_wdata_rawIn_normDist_T_40 ? 6'hB : _ll_fp_wdata_rawIn_normDist_T_90; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_92 = _ll_fp_wdata_rawIn_normDist_T_41 ? 6'hA : _ll_fp_wdata_rawIn_normDist_T_91; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_93 = _ll_fp_wdata_rawIn_normDist_T_42 ? 6'h9 : _ll_fp_wdata_rawIn_normDist_T_92; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_94 = _ll_fp_wdata_rawIn_normDist_T_43 ? 6'h8 : _ll_fp_wdata_rawIn_normDist_T_93; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_95 = _ll_fp_wdata_rawIn_normDist_T_44 ? 6'h7 : _ll_fp_wdata_rawIn_normDist_T_94; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_96 = _ll_fp_wdata_rawIn_normDist_T_45 ? 6'h6 : _ll_fp_wdata_rawIn_normDist_T_95; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_97 = _ll_fp_wdata_rawIn_normDist_T_46 ? 6'h5 : _ll_fp_wdata_rawIn_normDist_T_96; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_98 = _ll_fp_wdata_rawIn_normDist_T_47 ? 6'h4 : _ll_fp_wdata_rawIn_normDist_T_97; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_99 = _ll_fp_wdata_rawIn_normDist_T_48 ? 6'h3 : _ll_fp_wdata_rawIn_normDist_T_98; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_100 = _ll_fp_wdata_rawIn_normDist_T_49 ? 6'h2 : _ll_fp_wdata_rawIn_normDist_T_99; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_normDist_T_101 = _ll_fp_wdata_rawIn_normDist_T_50 ? 6'h1 : _ll_fp_wdata_rawIn_normDist_T_100; // @[Mux.scala:50:70] wire [5:0] ll_fp_wdata_rawIn_normDist = _ll_fp_wdata_rawIn_normDist_T_51 ? 6'h0 : _ll_fp_wdata_rawIn_normDist_T_101; // @[Mux.scala:50:70] wire [114:0] _ll_fp_wdata_rawIn_subnormFract_T = {63'h0, ll_fp_wdata_rawIn_fractIn} << ll_fp_wdata_rawIn_normDist; // @[Mux.scala:50:70] wire [50:0] _ll_fp_wdata_rawIn_subnormFract_T_1 = _ll_fp_wdata_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [51:0] ll_fp_wdata_rawIn_subnormFract = {_ll_fp_wdata_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [11:0] _ll_fp_wdata_rawIn_adjustedExp_T = {6'h3F, ~ll_fp_wdata_rawIn_normDist}; // @[Mux.scala:50:70] wire [11:0] _ll_fp_wdata_rawIn_adjustedExp_T_1 = ll_fp_wdata_rawIn_isZeroExpIn ? _ll_fp_wdata_rawIn_adjustedExp_T : {1'h0, ll_fp_wdata_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _ll_fp_wdata_rawIn_adjustedExp_T_2 = ll_fp_wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [10:0] _ll_fp_wdata_rawIn_adjustedExp_T_3 = {9'h100, _ll_fp_wdata_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [12:0] _ll_fp_wdata_rawIn_adjustedExp_T_4 = {1'h0, _ll_fp_wdata_rawIn_adjustedExp_T_1} + {2'h0, _ll_fp_wdata_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [11:0] ll_fp_wdata_rawIn_adjustedExp = _ll_fp_wdata_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9] wire [11:0] _ll_fp_wdata_rawIn_out_sExp_T = ll_fp_wdata_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire ll_fp_wdata_rawIn_isZero = ll_fp_wdata_rawIn_isZeroExpIn & ll_fp_wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire ll_fp_wdata_rawIn_isZero_0 = ll_fp_wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _ll_fp_wdata_rawIn_isSpecial_T = ll_fp_wdata_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32] wire ll_fp_wdata_rawIn_isSpecial = &_ll_fp_wdata_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _ll_fp_wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _ll_fp_wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _ll_fp_wdata_T_9 = ll_fp_wdata_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [12:0] _ll_fp_wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [53:0] _ll_fp_wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire ll_fp_wdata_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [12:0] ll_fp_wdata_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [53:0] ll_fp_wdata_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _ll_fp_wdata_rawIn_out_isNaN_T = ~ll_fp_wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _ll_fp_wdata_rawIn_out_isNaN_T_1 = ll_fp_wdata_rawIn_isSpecial & _ll_fp_wdata_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign ll_fp_wdata_rawIn_isNaN = _ll_fp_wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _ll_fp_wdata_rawIn_out_isInf_T = ll_fp_wdata_rawIn_isSpecial & ll_fp_wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign ll_fp_wdata_rawIn_isInf = _ll_fp_wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _ll_fp_wdata_rawIn_out_sExp_T_1 = {1'h0, _ll_fp_wdata_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign ll_fp_wdata_rawIn_sExp = _ll_fp_wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _ll_fp_wdata_rawIn_out_sig_T = ~ll_fp_wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _ll_fp_wdata_rawIn_out_sig_T_1 = {1'h0, _ll_fp_wdata_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [51:0] _ll_fp_wdata_rawIn_out_sig_T_2 = ll_fp_wdata_rawIn_isZeroExpIn ? ll_fp_wdata_rawIn_subnormFract : ll_fp_wdata_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _ll_fp_wdata_rawIn_out_sig_T_3 = {_ll_fp_wdata_rawIn_out_sig_T_1, _ll_fp_wdata_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign ll_fp_wdata_rawIn_sig = _ll_fp_wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _ll_fp_wdata_T_7 = ll_fp_wdata_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50] wire [2:0] _ll_fp_wdata_T_8 = ll_fp_wdata_rawIn_isZero_0 ? 3'h0 : _ll_fp_wdata_T_7; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _ll_fp_wdata_T_10 = {_ll_fp_wdata_T_8[2:1], _ll_fp_wdata_T_8[0] | _ll_fp_wdata_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _ll_fp_wdata_T_11 = {ll_fp_wdata_rawIn_sign_0, _ll_fp_wdata_T_10}; // @[recFNFromFN.scala:47:20, :48:76] wire [8:0] _ll_fp_wdata_T_12 = ll_fp_wdata_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23] wire [12:0] _ll_fp_wdata_T_13 = {_ll_fp_wdata_T_11, _ll_fp_wdata_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [51:0] _ll_fp_wdata_T_14 = ll_fp_wdata_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22] wire [64:0] _ll_fp_wdata_T_15 = {_ll_fp_wdata_T_13, _ll_fp_wdata_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire ll_fp_wdata_rawIn_sign_1 = _ll_fp_wdata_T_6[31]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_1_sign = ll_fp_wdata_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] ll_fp_wdata_rawIn_expIn_1 = _ll_fp_wdata_T_6[30:23]; // @[FPU.scala:431:23] wire [22:0] ll_fp_wdata_rawIn_fractIn_1 = _ll_fp_wdata_T_6[22:0]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_isZeroExpIn_1 = ll_fp_wdata_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire ll_fp_wdata_rawIn_isZeroFractIn_1 = ll_fp_wdata_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _ll_fp_wdata_rawIn_normDist_T_102 = ll_fp_wdata_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_103 = ll_fp_wdata_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_104 = ll_fp_wdata_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_105 = ll_fp_wdata_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_106 = ll_fp_wdata_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_107 = ll_fp_wdata_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_108 = ll_fp_wdata_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_109 = ll_fp_wdata_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_110 = ll_fp_wdata_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_111 = ll_fp_wdata_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_112 = ll_fp_wdata_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_113 = ll_fp_wdata_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_114 = ll_fp_wdata_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_115 = ll_fp_wdata_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_116 = ll_fp_wdata_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_117 = ll_fp_wdata_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_118 = ll_fp_wdata_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_119 = ll_fp_wdata_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_120 = ll_fp_wdata_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_121 = ll_fp_wdata_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_122 = ll_fp_wdata_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_123 = ll_fp_wdata_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_124 = ll_fp_wdata_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_125 = _ll_fp_wdata_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_126 = _ll_fp_wdata_rawIn_normDist_T_104 ? 5'h14 : _ll_fp_wdata_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_127 = _ll_fp_wdata_rawIn_normDist_T_105 ? 5'h13 : _ll_fp_wdata_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_128 = _ll_fp_wdata_rawIn_normDist_T_106 ? 5'h12 : _ll_fp_wdata_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_129 = _ll_fp_wdata_rawIn_normDist_T_107 ? 5'h11 : _ll_fp_wdata_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_130 = _ll_fp_wdata_rawIn_normDist_T_108 ? 5'h10 : _ll_fp_wdata_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_131 = _ll_fp_wdata_rawIn_normDist_T_109 ? 5'hF : _ll_fp_wdata_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_132 = _ll_fp_wdata_rawIn_normDist_T_110 ? 5'hE : _ll_fp_wdata_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_133 = _ll_fp_wdata_rawIn_normDist_T_111 ? 5'hD : _ll_fp_wdata_rawIn_normDist_T_132; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_134 = _ll_fp_wdata_rawIn_normDist_T_112 ? 5'hC : _ll_fp_wdata_rawIn_normDist_T_133; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_135 = _ll_fp_wdata_rawIn_normDist_T_113 ? 5'hB : _ll_fp_wdata_rawIn_normDist_T_134; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_136 = _ll_fp_wdata_rawIn_normDist_T_114 ? 5'hA : _ll_fp_wdata_rawIn_normDist_T_135; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_137 = _ll_fp_wdata_rawIn_normDist_T_115 ? 5'h9 : _ll_fp_wdata_rawIn_normDist_T_136; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_138 = _ll_fp_wdata_rawIn_normDist_T_116 ? 5'h8 : _ll_fp_wdata_rawIn_normDist_T_137; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_139 = _ll_fp_wdata_rawIn_normDist_T_117 ? 5'h7 : _ll_fp_wdata_rawIn_normDist_T_138; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_140 = _ll_fp_wdata_rawIn_normDist_T_118 ? 5'h6 : _ll_fp_wdata_rawIn_normDist_T_139; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_141 = _ll_fp_wdata_rawIn_normDist_T_119 ? 5'h5 : _ll_fp_wdata_rawIn_normDist_T_140; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_142 = _ll_fp_wdata_rawIn_normDist_T_120 ? 5'h4 : _ll_fp_wdata_rawIn_normDist_T_141; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_143 = _ll_fp_wdata_rawIn_normDist_T_121 ? 5'h3 : _ll_fp_wdata_rawIn_normDist_T_142; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_144 = _ll_fp_wdata_rawIn_normDist_T_122 ? 5'h2 : _ll_fp_wdata_rawIn_normDist_T_143; // @[Mux.scala:50:70] wire [4:0] _ll_fp_wdata_rawIn_normDist_T_145 = _ll_fp_wdata_rawIn_normDist_T_123 ? 5'h1 : _ll_fp_wdata_rawIn_normDist_T_144; // @[Mux.scala:50:70] wire [4:0] ll_fp_wdata_rawIn_normDist_1 = _ll_fp_wdata_rawIn_normDist_T_124 ? 5'h0 : _ll_fp_wdata_rawIn_normDist_T_145; // @[Mux.scala:50:70] wire [53:0] _ll_fp_wdata_rawIn_subnormFract_T_2 = {31'h0, ll_fp_wdata_rawIn_fractIn_1} << ll_fp_wdata_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _ll_fp_wdata_rawIn_subnormFract_T_3 = _ll_fp_wdata_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] ll_fp_wdata_rawIn_subnormFract_1 = {_ll_fp_wdata_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _ll_fp_wdata_rawIn_adjustedExp_T_5 = {4'hF, ~ll_fp_wdata_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _ll_fp_wdata_rawIn_adjustedExp_T_6 = ll_fp_wdata_rawIn_isZeroExpIn_1 ? _ll_fp_wdata_rawIn_adjustedExp_T_5 : {1'h0, ll_fp_wdata_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _ll_fp_wdata_rawIn_adjustedExp_T_7 = ll_fp_wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _ll_fp_wdata_rawIn_adjustedExp_T_8 = {6'h20, _ll_fp_wdata_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _ll_fp_wdata_rawIn_adjustedExp_T_9 = {1'h0, _ll_fp_wdata_rawIn_adjustedExp_T_6} + {2'h0, _ll_fp_wdata_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] ll_fp_wdata_rawIn_adjustedExp_1 = _ll_fp_wdata_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _ll_fp_wdata_rawIn_out_sExp_T_2 = ll_fp_wdata_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire ll_fp_wdata_rawIn_isZero_1 = ll_fp_wdata_rawIn_isZeroExpIn_1 & ll_fp_wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire ll_fp_wdata_rawIn_1_isZero = ll_fp_wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _ll_fp_wdata_rawIn_isSpecial_T_1 = ll_fp_wdata_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire ll_fp_wdata_rawIn_isSpecial_1 = &_ll_fp_wdata_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _ll_fp_wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _ll_fp_wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _ll_fp_wdata_T_18 = ll_fp_wdata_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _ll_fp_wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _ll_fp_wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire ll_fp_wdata_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] ll_fp_wdata_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] ll_fp_wdata_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _ll_fp_wdata_rawIn_out_isNaN_T_2 = ~ll_fp_wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _ll_fp_wdata_rawIn_out_isNaN_T_3 = ll_fp_wdata_rawIn_isSpecial_1 & _ll_fp_wdata_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign ll_fp_wdata_rawIn_1_isNaN = _ll_fp_wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _ll_fp_wdata_rawIn_out_isInf_T_1 = ll_fp_wdata_rawIn_isSpecial_1 & ll_fp_wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign ll_fp_wdata_rawIn_1_isInf = _ll_fp_wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _ll_fp_wdata_rawIn_out_sExp_T_3 = {1'h0, _ll_fp_wdata_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign ll_fp_wdata_rawIn_1_sExp = _ll_fp_wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _ll_fp_wdata_rawIn_out_sig_T_4 = ~ll_fp_wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _ll_fp_wdata_rawIn_out_sig_T_5 = {1'h0, _ll_fp_wdata_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _ll_fp_wdata_rawIn_out_sig_T_6 = ll_fp_wdata_rawIn_isZeroExpIn_1 ? ll_fp_wdata_rawIn_subnormFract_1 : ll_fp_wdata_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _ll_fp_wdata_rawIn_out_sig_T_7 = {_ll_fp_wdata_rawIn_out_sig_T_5, _ll_fp_wdata_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign ll_fp_wdata_rawIn_1_sig = _ll_fp_wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _ll_fp_wdata_T_16 = ll_fp_wdata_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _ll_fp_wdata_T_17 = ll_fp_wdata_rawIn_1_isZero ? 3'h0 : _ll_fp_wdata_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _ll_fp_wdata_T_19 = {_ll_fp_wdata_T_17[2:1], _ll_fp_wdata_T_17[0] | _ll_fp_wdata_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _ll_fp_wdata_T_20 = {ll_fp_wdata_rawIn_1_sign, _ll_fp_wdata_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _ll_fp_wdata_T_21 = ll_fp_wdata_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _ll_fp_wdata_T_22 = {_ll_fp_wdata_T_20, _ll_fp_wdata_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _ll_fp_wdata_T_23 = ll_fp_wdata_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] _ll_fp_wdata_T_24 = {_ll_fp_wdata_T_22, _ll_fp_wdata_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire ll_fp_wdata_rawIn_sign_2 = _ll_fp_wdata_T_6[15]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_2_sign = ll_fp_wdata_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [4:0] ll_fp_wdata_rawIn_expIn_2 = _ll_fp_wdata_T_6[14:10]; // @[FPU.scala:431:23] wire [9:0] ll_fp_wdata_rawIn_fractIn_2 = _ll_fp_wdata_T_6[9:0]; // @[FPU.scala:431:23] wire ll_fp_wdata_rawIn_isZeroExpIn_2 = ll_fp_wdata_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire ll_fp_wdata_rawIn_isZeroFractIn_2 = ll_fp_wdata_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _ll_fp_wdata_rawIn_normDist_T_146 = ll_fp_wdata_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_147 = ll_fp_wdata_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_148 = ll_fp_wdata_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_149 = ll_fp_wdata_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_150 = ll_fp_wdata_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_151 = ll_fp_wdata_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_152 = ll_fp_wdata_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_153 = ll_fp_wdata_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_154 = ll_fp_wdata_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _ll_fp_wdata_rawIn_normDist_T_155 = ll_fp_wdata_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_156 = {3'h4, ~_ll_fp_wdata_rawIn_normDist_T_147}; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_157 = _ll_fp_wdata_rawIn_normDist_T_148 ? 4'h7 : _ll_fp_wdata_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_158 = _ll_fp_wdata_rawIn_normDist_T_149 ? 4'h6 : _ll_fp_wdata_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_159 = _ll_fp_wdata_rawIn_normDist_T_150 ? 4'h5 : _ll_fp_wdata_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_160 = _ll_fp_wdata_rawIn_normDist_T_151 ? 4'h4 : _ll_fp_wdata_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_161 = _ll_fp_wdata_rawIn_normDist_T_152 ? 4'h3 : _ll_fp_wdata_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_162 = _ll_fp_wdata_rawIn_normDist_T_153 ? 4'h2 : _ll_fp_wdata_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [3:0] _ll_fp_wdata_rawIn_normDist_T_163 = _ll_fp_wdata_rawIn_normDist_T_154 ? 4'h1 : _ll_fp_wdata_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [3:0] ll_fp_wdata_rawIn_normDist_2 = _ll_fp_wdata_rawIn_normDist_T_155 ? 4'h0 : _ll_fp_wdata_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [24:0] _ll_fp_wdata_rawIn_subnormFract_T_4 = {15'h0, ll_fp_wdata_rawIn_fractIn_2} << ll_fp_wdata_rawIn_normDist_2; // @[Mux.scala:50:70] wire [8:0] _ll_fp_wdata_rawIn_subnormFract_T_5 = _ll_fp_wdata_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [9:0] ll_fp_wdata_rawIn_subnormFract_2 = {_ll_fp_wdata_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [5:0] _ll_fp_wdata_rawIn_adjustedExp_T_10 = {2'h3, ~ll_fp_wdata_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [5:0] _ll_fp_wdata_rawIn_adjustedExp_T_11 = ll_fp_wdata_rawIn_isZeroExpIn_2 ? _ll_fp_wdata_rawIn_adjustedExp_T_10 : {1'h0, ll_fp_wdata_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _ll_fp_wdata_rawIn_adjustedExp_T_12 = ll_fp_wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [4:0] _ll_fp_wdata_rawIn_adjustedExp_T_13 = {3'h4, _ll_fp_wdata_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [6:0] _ll_fp_wdata_rawIn_adjustedExp_T_14 = {1'h0, _ll_fp_wdata_rawIn_adjustedExp_T_11} + {2'h0, _ll_fp_wdata_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [5:0] ll_fp_wdata_rawIn_adjustedExp_2 = _ll_fp_wdata_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9] wire [5:0] _ll_fp_wdata_rawIn_out_sExp_T_4 = ll_fp_wdata_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire ll_fp_wdata_rawIn_isZero_2 = ll_fp_wdata_rawIn_isZeroExpIn_2 & ll_fp_wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire ll_fp_wdata_rawIn_2_isZero = ll_fp_wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _ll_fp_wdata_rawIn_isSpecial_T_2 = ll_fp_wdata_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32] wire ll_fp_wdata_rawIn_isSpecial_2 = &_ll_fp_wdata_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _ll_fp_wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _ll_fp_wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _ll_fp_wdata_T_27 = ll_fp_wdata_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [6:0] _ll_fp_wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [11:0] _ll_fp_wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire ll_fp_wdata_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [6:0] ll_fp_wdata_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [11:0] ll_fp_wdata_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _ll_fp_wdata_rawIn_out_isNaN_T_4 = ~ll_fp_wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _ll_fp_wdata_rawIn_out_isNaN_T_5 = ll_fp_wdata_rawIn_isSpecial_2 & _ll_fp_wdata_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign ll_fp_wdata_rawIn_2_isNaN = _ll_fp_wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _ll_fp_wdata_rawIn_out_isInf_T_2 = ll_fp_wdata_rawIn_isSpecial_2 & ll_fp_wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign ll_fp_wdata_rawIn_2_isInf = _ll_fp_wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _ll_fp_wdata_rawIn_out_sExp_T_5 = {1'h0, _ll_fp_wdata_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign ll_fp_wdata_rawIn_2_sExp = _ll_fp_wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _ll_fp_wdata_rawIn_out_sig_T_8 = ~ll_fp_wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _ll_fp_wdata_rawIn_out_sig_T_9 = {1'h0, _ll_fp_wdata_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [9:0] _ll_fp_wdata_rawIn_out_sig_T_10 = ll_fp_wdata_rawIn_isZeroExpIn_2 ? ll_fp_wdata_rawIn_subnormFract_2 : ll_fp_wdata_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _ll_fp_wdata_rawIn_out_sig_T_11 = {_ll_fp_wdata_rawIn_out_sig_T_9, _ll_fp_wdata_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign ll_fp_wdata_rawIn_2_sig = _ll_fp_wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _ll_fp_wdata_T_25 = ll_fp_wdata_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50] wire [2:0] _ll_fp_wdata_T_26 = ll_fp_wdata_rawIn_2_isZero ? 3'h0 : _ll_fp_wdata_T_25; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _ll_fp_wdata_T_28 = {_ll_fp_wdata_T_26[2:1], _ll_fp_wdata_T_26[0] | _ll_fp_wdata_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _ll_fp_wdata_T_29 = {ll_fp_wdata_rawIn_2_sign, _ll_fp_wdata_T_28}; // @[recFNFromFN.scala:47:20, :48:76] wire [2:0] _ll_fp_wdata_T_30 = ll_fp_wdata_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23] wire [6:0] _ll_fp_wdata_T_31 = {_ll_fp_wdata_T_29, _ll_fp_wdata_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [9:0] _ll_fp_wdata_T_32 = ll_fp_wdata_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22] wire [16:0] _ll_fp_wdata_T_33 = {_ll_fp_wdata_T_31, _ll_fp_wdata_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [3:0] _ll_fp_wdata_swizzledNaN_T = _ll_fp_wdata_T_24[32:29]; // @[FPU.scala:337:8] wire [6:0] _ll_fp_wdata_swizzledNaN_T_1 = _ll_fp_wdata_T_24[22:16]; // @[FPU.scala:338:8] wire [6:0] _ll_fp_wdata_swizzledNaN_T_5 = _ll_fp_wdata_T_24[22:16]; // @[FPU.scala:338:8, :341:8] wire _ll_fp_wdata_swizzledNaN_T_2 = &_ll_fp_wdata_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}] wire [3:0] _ll_fp_wdata_swizzledNaN_T_3 = _ll_fp_wdata_T_24[27:24]; // @[FPU.scala:339:8] wire _ll_fp_wdata_swizzledNaN_T_4 = _ll_fp_wdata_T_33[15]; // @[FPU.scala:340:8] wire _ll_fp_wdata_swizzledNaN_T_6 = _ll_fp_wdata_T_33[16]; // @[FPU.scala:342:8] wire [14:0] _ll_fp_wdata_swizzledNaN_T_7 = _ll_fp_wdata_T_33[14:0]; // @[FPU.scala:343:8] wire [7:0] ll_fp_wdata_swizzledNaN_lo_hi = {_ll_fp_wdata_swizzledNaN_T_5, _ll_fp_wdata_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8] wire [22:0] ll_fp_wdata_swizzledNaN_lo = {ll_fp_wdata_swizzledNaN_lo_hi, _ll_fp_wdata_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [4:0] ll_fp_wdata_swizzledNaN_hi_lo = {_ll_fp_wdata_swizzledNaN_T_3, _ll_fp_wdata_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] ll_fp_wdata_swizzledNaN_hi_hi = {_ll_fp_wdata_swizzledNaN_T, _ll_fp_wdata_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42] wire [9:0] ll_fp_wdata_swizzledNaN_hi = {ll_fp_wdata_swizzledNaN_hi_hi, ll_fp_wdata_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] ll_fp_wdata_swizzledNaN = {ll_fp_wdata_swizzledNaN_hi, ll_fp_wdata_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [2:0] _ll_fp_wdata_T_34 = _ll_fp_wdata_T_24[31:29]; // @[FPU.scala:249:25] wire _ll_fp_wdata_T_35 = &_ll_fp_wdata_T_34; // @[FPU.scala:249:{25,56}] wire [32:0] _ll_fp_wdata_T_36 = _ll_fp_wdata_T_35 ? ll_fp_wdata_swizzledNaN : _ll_fp_wdata_T_24; // @[FPU.scala:249:56, :336:26, :344:8] wire [3:0] _ll_fp_wdata_swizzledNaN_T_8 = _ll_fp_wdata_T_15[64:61]; // @[FPU.scala:337:8] wire [19:0] _ll_fp_wdata_swizzledNaN_T_9 = _ll_fp_wdata_T_15[51:32]; // @[FPU.scala:338:8] wire [19:0] _ll_fp_wdata_swizzledNaN_T_13 = _ll_fp_wdata_T_15[51:32]; // @[FPU.scala:338:8, :341:8] wire _ll_fp_wdata_swizzledNaN_T_10 = &_ll_fp_wdata_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}] wire [6:0] _ll_fp_wdata_swizzledNaN_T_11 = _ll_fp_wdata_T_15[59:53]; // @[FPU.scala:339:8] wire _ll_fp_wdata_swizzledNaN_T_12 = _ll_fp_wdata_T_36[31]; // @[FPU.scala:340:8, :344:8] wire _ll_fp_wdata_swizzledNaN_T_14 = _ll_fp_wdata_T_36[32]; // @[FPU.scala:342:8, :344:8] wire [30:0] _ll_fp_wdata_swizzledNaN_T_15 = _ll_fp_wdata_T_36[30:0]; // @[FPU.scala:343:8, :344:8] wire [20:0] ll_fp_wdata_swizzledNaN_lo_hi_1 = {_ll_fp_wdata_swizzledNaN_T_13, _ll_fp_wdata_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8] wire [51:0] ll_fp_wdata_swizzledNaN_lo_1 = {ll_fp_wdata_swizzledNaN_lo_hi_1, _ll_fp_wdata_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8] wire [7:0] ll_fp_wdata_swizzledNaN_hi_lo_1 = {_ll_fp_wdata_swizzledNaN_T_11, _ll_fp_wdata_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] ll_fp_wdata_swizzledNaN_hi_hi_1 = {_ll_fp_wdata_swizzledNaN_T_8, _ll_fp_wdata_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42] wire [12:0] ll_fp_wdata_swizzledNaN_hi_1 = {ll_fp_wdata_swizzledNaN_hi_hi_1, ll_fp_wdata_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] ll_fp_wdata_swizzledNaN_1 = {ll_fp_wdata_swizzledNaN_hi_1, ll_fp_wdata_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [2:0] _ll_fp_wdata_T_37 = _ll_fp_wdata_T_15[63:61]; // @[FPU.scala:249:25] wire _ll_fp_wdata_T_38 = &_ll_fp_wdata_T_37; // @[FPU.scala:249:{25,56}] wire [64:0] _ll_fp_wdata_T_39 = _ll_fp_wdata_T_38 ? ll_fp_wdata_swizzledNaN_1 : _ll_fp_wdata_T_15; // @[FPU.scala:249:56, :336:26, :344:8] wire _T_341 = divSqrt_val & divSqrt_wdata_valid; // @[Core.scala:872:28, :875:26, :1281:28] assign ll_fp_wval = fp_load_val | _T_341; // @[Core.scala:1268:28, :1273:28, :1277:22, :1278:16, :1281:{28,52}, :1282:16] assign ll_fp_wdata = fp_load_val ? _ll_fp_wdata_T_39 : _T_341 ? divSqrt_wdata_bits : 65'h0; // @[Core.scala:875:26, :1268:28, :1274:29, :1277:22, :1279:17, :1281:{28,52}, :1283:17] wire _GEN_215 = fp_load_val | ~_T_341; // @[Core.scala:1268:28, :1277:22, :1280:17, :1281:{28,52}] assign ll_fp_waddr = _GEN_215 ? fp_load_addr : divSqrt_waddr; // @[Core.scala:873:26, :1270:31, :1275:29, :1277:22, :1280:17, :1281:52] assign csr_fcsr_flags_1 = _GEN_215 ? 5'h0 : divSqrt_flags; // @[Core.scala:876:26, :1045:28, :1046:28, :1277:22, :1280:17, :1281:52] wire _GEN_216 = ll_fp_wval & ll_fp_waddr == 5'h0; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_217 = ll_fp_wval & ll_fp_waddr == 5'h1; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_218 = ll_fp_wval & ll_fp_waddr == 5'h2; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_219 = ll_fp_wval & ll_fp_waddr == 5'h3; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_220 = ll_fp_wval & ll_fp_waddr == 5'h4; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_221 = ll_fp_wval & ll_fp_waddr == 5'h5; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_222 = ll_fp_wval & ll_fp_waddr == 5'h6; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_223 = ll_fp_wval & ll_fp_waddr == 5'h7; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_224 = ll_fp_wval & ll_fp_waddr == 5'h8; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_225 = ll_fp_wval & ll_fp_waddr == 5'h9; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_226 = ll_fp_wval & ll_fp_waddr == 5'hA; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_227 = ll_fp_wval & ll_fp_waddr == 5'hB; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_228 = ll_fp_wval & ll_fp_waddr == 5'hC; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_229 = ll_fp_wval & ll_fp_waddr == 5'hD; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_230 = ll_fp_wval & ll_fp_waddr == 5'hE; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_231 = ll_fp_wval & ll_fp_waddr == 5'hF; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_232 = ll_fp_wval & ll_fp_waddr == 5'h10; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_233 = ll_fp_wval & ll_fp_waddr == 5'h11; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_234 = ll_fp_wval & ll_fp_waddr == 5'h12; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_235 = ll_fp_wval & ll_fp_waddr == 5'h13; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_236 = ll_fp_wval & ll_fp_waddr == 5'h14; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_237 = ll_fp_wval & ll_fp_waddr == 5'h15; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_238 = ll_fp_wval & ll_fp_waddr == 5'h16; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_239 = ll_fp_wval & ll_fp_waddr == 5'h17; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_240 = ll_fp_wval & ll_fp_waddr == 5'h18; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_241 = ll_fp_wval & ll_fp_waddr == 5'h19; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_242 = ll_fp_wval & ll_fp_waddr == 5'h1A; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_243 = ll_fp_wval & ll_fp_waddr == 5'h1B; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_244 = ll_fp_wval & ll_fp_waddr == 5'h1C; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_245 = ll_fp_wval & ll_fp_waddr == 5'h1D; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_246 = ll_fp_wval & ll_fp_waddr == 5'h1E; // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _GEN_247 = ll_fp_wval & (&ll_fp_waddr); // @[Core.scala:458:21, :1273:28, :1275:29, :1302:21, :1303:27] wire _fp_wdata_opts_bigger_swizzledNaN_T_1 = _fp_pipe_io_out_bits_data[15]; // @[Core.scala:469:23] wire _fp_wdata_opts_bigger_swizzledNaN_T_2 = _fp_pipe_io_out_bits_data[16]; // @[Core.scala:469:23] wire [14:0] _fp_wdata_opts_bigger_swizzledNaN_T_3 = _fp_pipe_io_out_bits_data[14:0]; // @[Core.scala:469:23] wire [7:0] fp_wdata_opts_bigger_swizzledNaN_lo_hi = {7'h7F, _fp_wdata_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [22:0] fp_wdata_opts_bigger_swizzledNaN_lo = {fp_wdata_opts_bigger_swizzledNaN_lo_hi, _fp_wdata_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [4:0] fp_wdata_opts_bigger_swizzledNaN_hi_lo = {4'hF, _fp_wdata_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [9:0] fp_wdata_opts_bigger_swizzledNaN_hi = {5'h1F, fp_wdata_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] fp_wdata_opts_bigger_swizzledNaN = {fp_wdata_opts_bigger_swizzledNaN_hi, fp_wdata_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [32:0] fp_wdata_opts_bigger = fp_wdata_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] fp_wdata_opts_0 = {32'hFFFFFFFF, fp_wdata_opts_bigger}; // @[FPU.scala:344:8, :398:14] wire _fp_wdata_opts_bigger_swizzledNaN_T_5 = _fp_pipe_io_out_bits_data[31]; // @[Core.scala:469:23] wire _fp_wdata_opts_bigger_swizzledNaN_T_6 = _fp_pipe_io_out_bits_data[32]; // @[Core.scala:469:23] wire [30:0] _fp_wdata_opts_bigger_swizzledNaN_T_7 = _fp_pipe_io_out_bits_data[30:0]; // @[Core.scala:469:23] wire [20:0] fp_wdata_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _fp_wdata_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] fp_wdata_opts_bigger_swizzledNaN_lo_1 = {fp_wdata_opts_bigger_swizzledNaN_lo_hi_1, _fp_wdata_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] fp_wdata_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _fp_wdata_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] fp_wdata_opts_bigger_swizzledNaN_hi_1 = {5'h1F, fp_wdata_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] fp_wdata_opts_bigger_swizzledNaN_1 = {fp_wdata_opts_bigger_swizzledNaN_hi_1, fp_wdata_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] fp_wdata_opts_bigger_1 = fp_wdata_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] fp_wdata_opts_1 = fp_wdata_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire _fp_wdata_T = _fp_pipe_io_out_tag == 2'h1; // @[Core.scala:469:23] wire [64:0] _fp_wdata_T_1 = _fp_wdata_T ? fp_wdata_opts_1 : fp_wdata_opts_0; // @[package.scala:39:{76,86}] wire _fp_wdata_T_2 = _fp_pipe_io_out_tag == 2'h2; // @[Core.scala:469:23] wire [64:0] _fp_wdata_T_3 = _fp_wdata_T_2 ? _fp_pipe_io_out_bits_data : _fp_wdata_T_1; // @[Core.scala:469:23] wire _fp_wdata_T_4 = &_fp_pipe_io_out_tag; // @[Core.scala:469:23] wire [64:0] fp_wdata = _fp_wdata_T_4 ? _fp_pipe_io_out_bits_data : _fp_wdata_T_3; // @[Core.scala:469:23] wire [11:0] fp_ieee_wdata_unrecoded_rawIn_exp = fp_wdata[63:52]; // @[package.scala:39:76] wire [2:0] _fp_ieee_wdata_unrecoded_rawIn_isZero_T = fp_ieee_wdata_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire fp_ieee_wdata_unrecoded_rawIn_isZero = _fp_ieee_wdata_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire fp_ieee_wdata_unrecoded_rawIn_isZero_0 = fp_ieee_wdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _fp_ieee_wdata_unrecoded_rawIn_isSpecial_T = fp_ieee_wdata_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire fp_ieee_wdata_unrecoded_rawIn_isSpecial = &_fp_ieee_wdata_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _fp_ieee_wdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _fp_ieee_wdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire fp_ieee_wdata_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] fp_ieee_wdata_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] fp_ieee_wdata_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T = fp_ieee_wdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T = fp_ieee_wdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T_1 = fp_ieee_wdata_unrecoded_rawIn_isSpecial & _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign fp_ieee_wdata_unrecoded_rawIn_isNaN = _fp_ieee_wdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_1 = ~_fp_ieee_wdata_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_2 = fp_ieee_wdata_unrecoded_rawIn_isSpecial & _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign fp_ieee_wdata_unrecoded_rawIn_isInf = _fp_ieee_wdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _fp_ieee_wdata_unrecoded_rawIn_out_sign_T = fp_wdata[64]; // @[package.scala:39:76] assign fp_ieee_wdata_unrecoded_rawIn_sign = _fp_ieee_wdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _fp_ieee_wdata_unrecoded_rawIn_out_sExp_T = {1'h0, fp_ieee_wdata_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign fp_ieee_wdata_unrecoded_rawIn_sExp = _fp_ieee_wdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _fp_ieee_wdata_unrecoded_rawIn_out_sig_T = ~fp_ieee_wdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_ieee_wdata_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_2 = fp_wdata[51:0]; // @[package.scala:39:76] assign _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_3 = {_fp_ieee_wdata_unrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign fp_ieee_wdata_unrecoded_rawIn_sig = _fp_ieee_wdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire fp_ieee_wdata_unrecoded_isSubnormal = $signed(fp_ieee_wdata_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _fp_ieee_wdata_unrecoded_denormShiftDist_T = fp_ieee_wdata_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _fp_ieee_wdata_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _fp_ieee_wdata_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] fp_ieee_wdata_unrecoded_denormShiftDist = _fp_ieee_wdata_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _fp_ieee_wdata_unrecoded_denormFract_T = fp_ieee_wdata_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _fp_ieee_wdata_unrecoded_denormFract_T_1 = _fp_ieee_wdata_unrecoded_denormFract_T >> fp_ieee_wdata_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] fp_ieee_wdata_unrecoded_denormFract = _fp_ieee_wdata_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _fp_ieee_wdata_unrecoded_expOut_T = fp_ieee_wdata_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _fp_ieee_wdata_unrecoded_expOut_T_1 = {1'h0, _fp_ieee_wdata_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _fp_ieee_wdata_unrecoded_expOut_T_2 = _fp_ieee_wdata_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _fp_ieee_wdata_unrecoded_expOut_T_3 = fp_ieee_wdata_unrecoded_isSubnormal ? 11'h0 : _fp_ieee_wdata_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _fp_ieee_wdata_unrecoded_expOut_T_4 = fp_ieee_wdata_unrecoded_rawIn_isNaN | fp_ieee_wdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _fp_ieee_wdata_unrecoded_expOut_T_5 = {11{_fp_ieee_wdata_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] fp_ieee_wdata_unrecoded_expOut = _fp_ieee_wdata_unrecoded_expOut_T_3 | _fp_ieee_wdata_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _fp_ieee_wdata_unrecoded_fractOut_T = fp_ieee_wdata_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fp_ieee_wdata_unrecoded_fractOut_T_1 = fp_ieee_wdata_unrecoded_rawIn_isInf ? 52'h0 : _fp_ieee_wdata_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] fp_ieee_wdata_unrecoded_fractOut = fp_ieee_wdata_unrecoded_isSubnormal ? fp_ieee_wdata_unrecoded_denormFract : _fp_ieee_wdata_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] fp_ieee_wdata_unrecoded_hi = {fp_ieee_wdata_unrecoded_rawIn_sign, fp_ieee_wdata_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] fp_ieee_wdata_unrecoded = {fp_ieee_wdata_unrecoded_hi, fp_ieee_wdata_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _fp_ieee_wdata_prevRecoded_T = fp_wdata[31]; // @[package.scala:39:76] wire _fp_ieee_wdata_prevRecoded_T_1 = fp_wdata[52]; // @[package.scala:39:76] wire [30:0] _fp_ieee_wdata_prevRecoded_T_2 = fp_wdata[30:0]; // @[package.scala:39:76] wire [1:0] fp_ieee_wdata_prevRecoded_hi = {_fp_ieee_wdata_prevRecoded_T, _fp_ieee_wdata_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] fp_ieee_wdata_prevRecoded = {fp_ieee_wdata_prevRecoded_hi, _fp_ieee_wdata_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp = fp_ieee_wdata_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero_0 = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial = &_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isNaN = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isInf = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = fp_ieee_wdata_prevRecoded[32]; // @[FPU.scala:441:28] assign fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sign = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sExp = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = fp_ieee_wdata_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sig = _fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal = $signed(fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist = _fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T_1 = _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T >> fp_ieee_wdata_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract = _fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_2 = _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_3 = fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_4 = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isNaN | fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_5 = {8{_fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] fp_ieee_wdata_prevUnrecoded_unrecoded_expOut = _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_3 | _fp_ieee_wdata_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T_1 = fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut = fp_ieee_wdata_prevUnrecoded_unrecoded_isSubnormal ? fp_ieee_wdata_prevUnrecoded_unrecoded_denormFract : _fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] fp_ieee_wdata_prevUnrecoded_unrecoded_hi = {fp_ieee_wdata_prevUnrecoded_unrecoded_rawIn_sign, fp_ieee_wdata_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] fp_ieee_wdata_prevUnrecoded_unrecoded = {fp_ieee_wdata_prevUnrecoded_unrecoded_hi, fp_ieee_wdata_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _fp_ieee_wdata_prevUnrecoded_prevRecoded_T = fp_ieee_wdata_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_1 = fp_ieee_wdata_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_2 = fp_ieee_wdata_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] fp_ieee_wdata_prevUnrecoded_prevRecoded_hi = {_fp_ieee_wdata_prevUnrecoded_prevRecoded_T, _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] fp_ieee_wdata_prevUnrecoded_prevRecoded = {fp_ieee_wdata_prevUnrecoded_prevRecoded_hi, _fp_ieee_wdata_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp = fp_ieee_wdata_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isInf = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = fp_ieee_wdata_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sign = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sExp = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = fp_ieee_wdata_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sig = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T >> fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN | fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut = _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_3 | _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut = fp_ieee_wdata_prevUnrecoded_prevUnrecoded_isSubnormal ? fp_ieee_wdata_prevUnrecoded_prevUnrecoded_denormFract : _fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded_hi = {fp_ieee_wdata_prevUnrecoded_prevUnrecoded_rawIn_sign, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] fp_ieee_wdata_prevUnrecoded_prevUnrecoded = {fp_ieee_wdata_prevUnrecoded_prevUnrecoded_hi, fp_ieee_wdata_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _fp_ieee_wdata_prevUnrecoded_T = fp_ieee_wdata_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _fp_ieee_wdata_prevUnrecoded_T_1 = fp_ieee_wdata_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _fp_ieee_wdata_prevUnrecoded_T_2 = &_fp_ieee_wdata_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _fp_ieee_wdata_prevUnrecoded_T_3 = fp_ieee_wdata_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _fp_ieee_wdata_prevUnrecoded_T_4 = _fp_ieee_wdata_prevUnrecoded_T_2 ? fp_ieee_wdata_prevUnrecoded_prevUnrecoded : _fp_ieee_wdata_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] fp_ieee_wdata_prevUnrecoded = {_fp_ieee_wdata_prevUnrecoded_T, _fp_ieee_wdata_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _fp_ieee_wdata_T = fp_ieee_wdata_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _fp_ieee_wdata_T_1 = fp_wdata[63:61]; // @[package.scala:39:76] wire _fp_ieee_wdata_T_2 = &_fp_ieee_wdata_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _fp_ieee_wdata_T_3 = fp_ieee_wdata_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _fp_ieee_wdata_T_4 = _fp_ieee_wdata_T_2 ? fp_ieee_wdata_prevUnrecoded : _fp_ieee_wdata_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] fp_ieee_wdata = {_fp_ieee_wdata_T, _fp_ieee_wdata_T_4}; // @[FPU.scala:446:{10,21,44}] wire _GEN_248 = _fp_pipe_io_out_rd == 5'h0; // @[Core.scala:469:23, :1315:21] wire _GEN_249 = _fp_pipe_io_out_rd == 5'h1; // @[Core.scala:469:23, :1315:21] wire _GEN_250 = _fp_pipe_io_out_rd == 5'h2; // @[Core.scala:469:23, :1315:21] wire _GEN_251 = _fp_pipe_io_out_rd == 5'h3; // @[Core.scala:469:23, :1315:21] wire _GEN_252 = _fp_pipe_io_out_rd == 5'h4; // @[Core.scala:469:23, :1315:21] wire _GEN_253 = _fp_pipe_io_out_rd == 5'h5; // @[Core.scala:469:23, :1315:21] wire _GEN_254 = _fp_pipe_io_out_rd == 5'h6; // @[Core.scala:469:23, :1315:21] wire _GEN_255 = _fp_pipe_io_out_rd == 5'h7; // @[Core.scala:469:23, :1315:21] wire _GEN_256 = _fp_pipe_io_out_rd == 5'h8; // @[Core.scala:469:23, :1315:21] wire _GEN_257 = _fp_pipe_io_out_rd == 5'h9; // @[Core.scala:469:23, :1315:21] wire _GEN_258 = _fp_pipe_io_out_rd == 5'hA; // @[Core.scala:469:23, :1315:21] wire _GEN_259 = _fp_pipe_io_out_rd == 5'hB; // @[Core.scala:469:23, :1315:21] wire _GEN_260 = _fp_pipe_io_out_rd == 5'hC; // @[Core.scala:469:23, :1315:21] wire _GEN_261 = _fp_pipe_io_out_rd == 5'hD; // @[Core.scala:469:23, :1315:21] wire _GEN_262 = _fp_pipe_io_out_rd == 5'hE; // @[Core.scala:469:23, :1315:21] wire _GEN_263 = _fp_pipe_io_out_rd == 5'hF; // @[Core.scala:469:23, :1315:21] wire _GEN_264 = _fp_pipe_io_out_rd == 5'h10; // @[Core.scala:469:23, :1315:21] wire _GEN_265 = _fp_pipe_io_out_rd == 5'h11; // @[Core.scala:469:23, :1315:21] wire _GEN_266 = _fp_pipe_io_out_rd == 5'h12; // @[Core.scala:469:23, :1315:21] wire _GEN_267 = _fp_pipe_io_out_rd == 5'h13; // @[Core.scala:469:23, :1315:21] wire _GEN_268 = _fp_pipe_io_out_rd == 5'h14; // @[Core.scala:469:23, :1315:21] wire _GEN_269 = _fp_pipe_io_out_rd == 5'h15; // @[Core.scala:469:23, :1315:21] wire _GEN_270 = _fp_pipe_io_out_rd == 5'h16; // @[Core.scala:469:23, :1315:21] wire _GEN_271 = _fp_pipe_io_out_rd == 5'h17; // @[Core.scala:469:23, :1315:21] wire _GEN_272 = _fp_pipe_io_out_rd == 5'h18; // @[Core.scala:469:23, :1315:21] wire _GEN_273 = _fp_pipe_io_out_rd == 5'h19; // @[Core.scala:469:23, :1315:21] wire _GEN_274 = _fp_pipe_io_out_rd == 5'h1A; // @[Core.scala:469:23, :1315:21] wire _GEN_275 = _fp_pipe_io_out_rd == 5'h1B; // @[Core.scala:469:23, :1315:21] wire _GEN_276 = _fp_pipe_io_out_rd == 5'h1C; // @[Core.scala:469:23, :1315:21] wire _GEN_277 = _fp_pipe_io_out_rd == 5'h1D; // @[Core.scala:469:23, :1315:21] wire _GEN_278 = _fp_pipe_io_out_rd == 5'h1E; // @[Core.scala:469:23, :1315:21] assign fsboard_set_0 = _fp_pipe_io_out_valid & _GEN_248 | _GEN_216; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_1 = _fp_pipe_io_out_valid & _GEN_249 | _GEN_217; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_2 = _fp_pipe_io_out_valid & _GEN_250 | _GEN_218; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_3 = _fp_pipe_io_out_valid & _GEN_251 | _GEN_219; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_4 = _fp_pipe_io_out_valid & _GEN_252 | _GEN_220; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_5 = _fp_pipe_io_out_valid & _GEN_253 | _GEN_221; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_6 = _fp_pipe_io_out_valid & _GEN_254 | _GEN_222; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_7 = _fp_pipe_io_out_valid & _GEN_255 | _GEN_223; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_8 = _fp_pipe_io_out_valid & _GEN_256 | _GEN_224; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_9 = _fp_pipe_io_out_valid & _GEN_257 | _GEN_225; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_10 = _fp_pipe_io_out_valid & _GEN_258 | _GEN_226; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_11 = _fp_pipe_io_out_valid & _GEN_259 | _GEN_227; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_12 = _fp_pipe_io_out_valid & _GEN_260 | _GEN_228; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_13 = _fp_pipe_io_out_valid & _GEN_261 | _GEN_229; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_14 = _fp_pipe_io_out_valid & _GEN_262 | _GEN_230; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_15 = _fp_pipe_io_out_valid & _GEN_263 | _GEN_231; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_16 = _fp_pipe_io_out_valid & _GEN_264 | _GEN_232; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_17 = _fp_pipe_io_out_valid & _GEN_265 | _GEN_233; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_18 = _fp_pipe_io_out_valid & _GEN_266 | _GEN_234; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_19 = _fp_pipe_io_out_valid & _GEN_267 | _GEN_235; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_20 = _fp_pipe_io_out_valid & _GEN_268 | _GEN_236; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_21 = _fp_pipe_io_out_valid & _GEN_269 | _GEN_237; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_22 = _fp_pipe_io_out_valid & _GEN_270 | _GEN_238; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_23 = _fp_pipe_io_out_valid & _GEN_271 | _GEN_239; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_24 = _fp_pipe_io_out_valid & _GEN_272 | _GEN_240; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_25 = _fp_pipe_io_out_valid & _GEN_273 | _GEN_241; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_26 = _fp_pipe_io_out_valid & _GEN_274 | _GEN_242; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_27 = _fp_pipe_io_out_valid & _GEN_275 | _GEN_243; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_28 = _fp_pipe_io_out_valid & _GEN_276 | _GEN_244; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_29 = _fp_pipe_io_out_valid & _GEN_277 | _GEN_245; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_30 = _fp_pipe_io_out_valid & _GEN_278 | _GEN_246; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign fsboard_set_31 = _fp_pipe_io_out_valid & (&_fp_pipe_io_out_rd) | _GEN_247; // @[Core.scala:458:21, :461:29, :469:23, :1302:21, :1303:27, :1313:31, :1315:21, :1316:24] assign csr_fcsr_flags_2 = _fp_pipe_io_out_valid ? _fp_pipe_io_out_bits_exc : 5'h0; // @[Core.scala:469:23, :1045:28, :1046:28, :1313:31, :1319:23]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0) node _source_ok_T = shr(io.in.a.bits.source, 12) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits = bits(_uncommonBits_T, 11, 0) node _T_4 = shr(io.in.a.bits.source, 12) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<12>(0h80f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0) node _T_24 = shr(io.in.a.bits.source, 12) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0) node _T_86 = shr(io.in.a.bits.source, 12) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0) node _T_152 = shr(io.in.a.bits.source, 12) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0) node _T_199 = shr(io.in.a.bits.source, 12) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0) node _T_240 = shr(io.in.a.bits.source, 12) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<12>(0h80f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0) node _T_283 = shr(io.in.a.bits.source, 12) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<12>(0h80f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0) node _T_321 = shr(io.in.a.bits.source, 12) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<12>(0h80f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0) node _T_359 = shr(io.in.a.bits.source, 12) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<12>(0h80f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 12) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2064> connect a_set, UInt<2064>(0h0) wire a_set_wo_ready : UInt<2064> connect a_set_wo_ready, UInt<2064>(0h0) wire a_opcodes_set : UInt<8256> connect a_opcodes_set, UInt<8256>(0h0) wire a_sizes_set : UInt<8256> connect a_sizes_set, UInt<8256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<2064> connect d_clr, UInt<2064>(0h0) wire d_clr_wo_ready : UInt<2064> connect d_clr_wo_ready, UInt<2064>(0h0) wire d_opcodes_clr : UInt<8256> connect d_opcodes_clr, UInt<8256>(0h0) wire d_sizes_clr : UInt<8256> connect d_sizes_clr, UInt<8256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_134 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0) regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<12>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<12>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2064> connect c_set, UInt<2064>(0h0) wire c_set_wo_ready : UInt<2064> connect c_set_wo_ready, UInt<2064>(0h0) wire c_opcodes_set : UInt<8256> connect c_opcodes_set, UInt<8256>(0h0) wire c_sizes_set : UInt<8256> connect c_sizes_set, UInt<8256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<12>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<12>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<12>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<12>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2064> connect d_clr_1, UInt<2064>(0h0) wire d_clr_wo_ready_1 : UInt<2064> connect d_clr_wo_ready_1, UInt<2064>(0h0) wire d_opcodes_clr_1 : UInt<8256> connect d_opcodes_clr_1, UInt<8256>(0h0) wire d_sizes_clr_1 : UInt<8256> connect d_sizes_clr_1, UInt<8256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<12>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<12>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<12>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<12>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_135 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<12>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52] wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79] wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77] wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35] wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35] wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34] wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34] wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34] wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [11:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [11:0] source_1; // @[Monitor.scala:541:22] reg [2063:0] inflight; // @[Monitor.scala:614:27] reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [2063:0] a_set; // @[Monitor.scala:626:34] wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [4095:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2063:0] d_clr; // @[Monitor.scala:664:34] wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [4095:0] _GEN_5 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2063:0] inflight_1; // @[Monitor.scala:726:35] wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2063:0] d_clr_1; // @[Monitor.scala:774:34] wire [2063:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [8255:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [8255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[2063:0] : 2064'h0; // @[OneHot.scala:58:35] wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[8255:0] : 8256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113] wire [2063:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2063:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [8255:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [8255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_119 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_119( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_199 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_21 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue2_EgressFlit_21 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h1d), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h1e), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h1a), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h1b), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h1c), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_21( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<2>(0h3)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<2>(0h2)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 4) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<4>(0h9)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<2>(0h3)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<9>(0hc0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_17 = shr(io.in.a.bits.source, 4) node _T_18 = eq(_T_17, UInt<2>(0h2)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<9>(0hc0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_30 = shr(io.in.a.bits.source, 4) node _T_31 = eq(_T_30, UInt<1>(0h1)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<9>(0hc0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_43 = shr(io.in.a.bits.source, 4) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<8>(0hc0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<9>(0hc0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_66 = shr(io.in.a.bits.source, 4) node _T_67 = eq(_T_66, UInt<2>(0h3)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_72 = shr(io.in.a.bits.source, 4) node _T_73 = eq(_T_72, UInt<2>(0h2)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_78 = shr(io.in.a.bits.source, 4) node _T_79 = eq(_T_78, UInt<1>(0h1)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_84 = shr(io.in.a.bits.source, 4) node _T_85 = eq(_T_84, UInt<1>(0h0)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = and(_T_95, _T_100) node _T_102 = or(UInt<1>(0h0), _T_101) node _T_103 = and(_T_94, _T_102) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_103, UInt<1>(0h1), "") : assert_2 node _T_107 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_108 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_109 = and(_T_107, _T_108) node _T_110 = or(UInt<1>(0h0), _T_109) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = and(_T_110, _T_115) node _T_117 = or(UInt<1>(0h0), _T_116) node _T_118 = and(UInt<1>(0h0), _T_117) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_118, UInt<1>(0h1), "") : assert_3 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(source_ok, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_125 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_125, UInt<1>(0h1), "") : assert_5 node _T_129 = asUInt(reset) node _T_130 = eq(_T_129, UInt<1>(0h0)) when _T_130 : node _T_131 = eq(is_aligned, UInt<1>(0h0)) when _T_131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_132 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_132, UInt<1>(0h1), "") : assert_7 node _T_136 = not(io.in.a.bits.mask) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_137, UInt<1>(0h1), "") : assert_8 node _T_141 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_141, UInt<1>(0h1), "") : assert_9 node _T_145 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_145 : node _T_146 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_147 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_149 = shr(io.in.a.bits.source, 4) node _T_150 = eq(_T_149, UInt<2>(0h3)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_8) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_155 = shr(io.in.a.bits.source, 4) node _T_156 = eq(_T_155, UInt<2>(0h2)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_9) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_161 = shr(io.in.a.bits.source, 4) node _T_162 = eq(_T_161, UInt<1>(0h1)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_10) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_166 = and(_T_164, _T_165) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_167 = shr(io.in.a.bits.source, 4) node _T_168 = eq(_T_167, UInt<1>(0h0)) node _T_169 = leq(UInt<1>(0h0), uncommonBits_11) node _T_170 = and(_T_168, _T_169) node _T_171 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_172 = and(_T_170, _T_171) node _T_173 = or(_T_154, _T_160) node _T_174 = or(_T_173, _T_166) node _T_175 = or(_T_174, _T_172) node _T_176 = and(_T_148, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_179 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<17>(0h10000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = and(_T_178, _T_183) node _T_185 = or(UInt<1>(0h0), _T_184) node _T_186 = and(_T_177, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_186, UInt<1>(0h1), "") : assert_10 node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<17>(0h10000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = and(_T_193, _T_198) node _T_200 = or(UInt<1>(0h0), _T_199) node _T_201 = and(UInt<1>(0h0), _T_200) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_201, UInt<1>(0h1), "") : assert_11 node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(source_ok, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_208 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = asUInt(reset) node _T_210 = eq(_T_209, UInt<1>(0h0)) when _T_210 : node _T_211 = eq(_T_208, UInt<1>(0h0)) when _T_211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_208, UInt<1>(0h1), "") : assert_13 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(is_aligned, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_215 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_215, UInt<1>(0h1), "") : assert_15 node _T_219 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_219, UInt<1>(0h1), "") : assert_16 node _T_223 = not(io.in.a.bits.mask) node _T_224 = eq(_T_223, UInt<1>(0h0)) node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(_T_224, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_224, UInt<1>(0h1), "") : assert_17 node _T_228 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_228, UInt<1>(0h1), "") : assert_18 node _T_232 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_232 : node _T_233 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_234 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_236 = shr(io.in.a.bits.source, 4) node _T_237 = eq(_T_236, UInt<2>(0h3)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_242 = shr(io.in.a.bits.source, 4) node _T_243 = eq(_T_242, UInt<2>(0h2)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<4>(0h9)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_248 = shr(io.in.a.bits.source, 4) node _T_249 = eq(_T_248, UInt<1>(0h1)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<4>(0h9)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_254 = shr(io.in.a.bits.source, 4) node _T_255 = eq(_T_254, UInt<1>(0h0)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<4>(0h9)) node _T_259 = and(_T_257, _T_258) node _T_260 = or(_T_241, _T_247) node _T_261 = or(_T_260, _T_253) node _T_262 = or(_T_261, _T_259) node _T_263 = and(_T_235, _T_262) node _T_264 = or(UInt<1>(0h0), _T_263) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_264, UInt<1>(0h1), "") : assert_19 node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_270 = and(_T_268, _T_269) node _T_271 = or(UInt<1>(0h0), _T_270) node _T_272 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_278, UInt<1>(0h1), "") : assert_20 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(is_aligned, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_288 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_288, UInt<1>(0h1), "") : assert_23 node _T_292 = eq(io.in.a.bits.mask, mask) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_292, UInt<1>(0h1), "") : assert_24 node _T_296 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_296, UInt<1>(0h1), "") : assert_25 node _T_300 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_300 : node _T_301 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_302 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_303 = and(_T_301, _T_302) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_304 = shr(io.in.a.bits.source, 4) node _T_305 = eq(_T_304, UInt<2>(0h3)) node _T_306 = leq(UInt<1>(0h0), uncommonBits_16) node _T_307 = and(_T_305, _T_306) node _T_308 = leq(uncommonBits_16, UInt<4>(0h9)) node _T_309 = and(_T_307, _T_308) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_310 = shr(io.in.a.bits.source, 4) node _T_311 = eq(_T_310, UInt<2>(0h2)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_17) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_17, UInt<4>(0h9)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 3, 0) node _T_316 = shr(io.in.a.bits.source, 4) node _T_317 = eq(_T_316, UInt<1>(0h1)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_18) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_18, UInt<4>(0h9)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 3, 0) node _T_322 = shr(io.in.a.bits.source, 4) node _T_323 = eq(_T_322, UInt<1>(0h0)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_19) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_19, UInt<4>(0h9)) node _T_327 = and(_T_325, _T_326) node _T_328 = or(_T_309, _T_315) node _T_329 = or(_T_328, _T_321) node _T_330 = or(_T_329, _T_327) node _T_331 = and(_T_303, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_334 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_335 = and(_T_333, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = and(_T_336, _T_341) node _T_343 = or(UInt<1>(0h0), _T_342) node _T_344 = and(_T_332, _T_343) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_344, UInt<1>(0h1), "") : assert_26 node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(source_ok, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(is_aligned, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_354 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_354, UInt<1>(0h1), "") : assert_29 node _T_358 = eq(io.in.a.bits.mask, mask) node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_T_358, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_358, UInt<1>(0h1), "") : assert_30 node _T_362 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_362 : node _T_363 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_364 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_365 = and(_T_363, _T_364) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 3, 0) node _T_366 = shr(io.in.a.bits.source, 4) node _T_367 = eq(_T_366, UInt<2>(0h3)) node _T_368 = leq(UInt<1>(0h0), uncommonBits_20) node _T_369 = and(_T_367, _T_368) node _T_370 = leq(uncommonBits_20, UInt<4>(0h9)) node _T_371 = and(_T_369, _T_370) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 3, 0) node _T_372 = shr(io.in.a.bits.source, 4) node _T_373 = eq(_T_372, UInt<2>(0h2)) node _T_374 = leq(UInt<1>(0h0), uncommonBits_21) node _T_375 = and(_T_373, _T_374) node _T_376 = leq(uncommonBits_21, UInt<4>(0h9)) node _T_377 = and(_T_375, _T_376) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_378 = shr(io.in.a.bits.source, 4) node _T_379 = eq(_T_378, UInt<1>(0h1)) node _T_380 = leq(UInt<1>(0h0), uncommonBits_22) node _T_381 = and(_T_379, _T_380) node _T_382 = leq(uncommonBits_22, UInt<4>(0h9)) node _T_383 = and(_T_381, _T_382) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_384 = shr(io.in.a.bits.source, 4) node _T_385 = eq(_T_384, UInt<1>(0h0)) node _T_386 = leq(UInt<1>(0h0), uncommonBits_23) node _T_387 = and(_T_385, _T_386) node _T_388 = leq(uncommonBits_23, UInt<4>(0h9)) node _T_389 = and(_T_387, _T_388) node _T_390 = or(_T_371, _T_377) node _T_391 = or(_T_390, _T_383) node _T_392 = or(_T_391, _T_389) node _T_393 = and(_T_365, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<17>(0h10000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = and(_T_398, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_406, UInt<1>(0h1), "") : assert_31 node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(source_ok, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(is_aligned, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_416 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_416, UInt<1>(0h1), "") : assert_34 node _T_420 = not(mask) node _T_421 = and(io.in.a.bits.mask, _T_420) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_422, UInt<1>(0h1), "") : assert_35 node _T_426 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_426 : node _T_427 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_428 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 3, 0) node _T_430 = shr(io.in.a.bits.source, 4) node _T_431 = eq(_T_430, UInt<2>(0h3)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_24) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_24, UInt<4>(0h9)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 3, 0) node _T_436 = shr(io.in.a.bits.source, 4) node _T_437 = eq(_T_436, UInt<2>(0h2)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_25) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_25, UInt<4>(0h9)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 3, 0) node _T_442 = shr(io.in.a.bits.source, 4) node _T_443 = eq(_T_442, UInt<1>(0h1)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_26) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_26, UInt<4>(0h9)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 3, 0) node _T_448 = shr(io.in.a.bits.source, 4) node _T_449 = eq(_T_448, UInt<1>(0h0)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_27) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_27, UInt<4>(0h9)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(_T_435, _T_441) node _T_455 = or(_T_454, _T_447) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_429, _T_456) node _T_458 = or(UInt<1>(0h0), _T_457) node _T_459 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<17>(0h10000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = and(_T_459, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = and(_T_458, _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_467, UInt<1>(0h1), "") : assert_36 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(source_ok, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(is_aligned, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_477 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_477, UInt<1>(0h1), "") : assert_39 node _T_481 = eq(io.in.a.bits.mask, mask) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_481, UInt<1>(0h1), "") : assert_40 node _T_485 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_485 : node _T_486 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_487 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_489 = shr(io.in.a.bits.source, 4) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_28) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_28, UInt<4>(0h9)) node _T_494 = and(_T_492, _T_493) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_495 = shr(io.in.a.bits.source, 4) node _T_496 = eq(_T_495, UInt<2>(0h2)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_29) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_29, UInt<4>(0h9)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 3, 0) node _T_501 = shr(io.in.a.bits.source, 4) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_30) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_30, UInt<4>(0h9)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 3, 0) node _T_507 = shr(io.in.a.bits.source, 4) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_31) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_31, UInt<4>(0h9)) node _T_512 = and(_T_510, _T_511) node _T_513 = or(_T_494, _T_500) node _T_514 = or(_T_513, _T_506) node _T_515 = or(_T_514, _T_512) node _T_516 = and(_T_488, _T_515) node _T_517 = or(UInt<1>(0h0), _T_516) node _T_518 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_519 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = or(UInt<1>(0h0), _T_524) node _T_526 = and(_T_517, _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_526, UInt<1>(0h1), "") : assert_41 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(source_ok, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(is_aligned, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_536 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(_T_536, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_536, UInt<1>(0h1), "") : assert_44 node _T_540 = eq(io.in.a.bits.mask, mask) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_540, UInt<1>(0h1), "") : assert_45 node _T_544 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 3, 0) node _T_548 = shr(io.in.a.bits.source, 4) node _T_549 = eq(_T_548, UInt<2>(0h3)) node _T_550 = leq(UInt<1>(0h0), uncommonBits_32) node _T_551 = and(_T_549, _T_550) node _T_552 = leq(uncommonBits_32, UInt<4>(0h9)) node _T_553 = and(_T_551, _T_552) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 3, 0) node _T_554 = shr(io.in.a.bits.source, 4) node _T_555 = eq(_T_554, UInt<2>(0h2)) node _T_556 = leq(UInt<1>(0h0), uncommonBits_33) node _T_557 = and(_T_555, _T_556) node _T_558 = leq(uncommonBits_33, UInt<4>(0h9)) node _T_559 = and(_T_557, _T_558) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_560 = shr(io.in.a.bits.source, 4) node _T_561 = eq(_T_560, UInt<1>(0h1)) node _T_562 = leq(UInt<1>(0h0), uncommonBits_34) node _T_563 = and(_T_561, _T_562) node _T_564 = leq(uncommonBits_34, UInt<4>(0h9)) node _T_565 = and(_T_563, _T_564) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_566 = shr(io.in.a.bits.source, 4) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = leq(UInt<1>(0h0), uncommonBits_35) node _T_569 = and(_T_567, _T_568) node _T_570 = leq(uncommonBits_35, UInt<4>(0h9)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(_T_553, _T_559) node _T_573 = or(_T_572, _T_565) node _T_574 = or(_T_573, _T_571) node _T_575 = and(_T_547, _T_574) node _T_576 = or(UInt<1>(0h0), _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = and(_T_576, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_585, UInt<1>(0h1), "") : assert_46 node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(source_ok, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(is_aligned, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_595 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_595, UInt<1>(0h1), "") : assert_49 node _T_599 = eq(io.in.a.bits.mask, mask) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_599, UInt<1>(0h1), "") : assert_50 node _T_603 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_603, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_607 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_607, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 4) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<2>(0h3)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<4>(0h9)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 4) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<2>(0h2)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<4>(0h9)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 3, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 4) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<1>(0h1)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<4>(0h9)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 3, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 4) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<4>(0h9)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_611 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_611 : node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(source_ok_1, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_615 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_616 = asUInt(reset) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(_T_615, UInt<1>(0h0)) when _T_618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_615, UInt<1>(0h1), "") : assert_54 node _T_619 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_619, UInt<1>(0h1), "") : assert_55 node _T_623 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_623, UInt<1>(0h1), "") : assert_56 node _T_627 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_T_627, UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_627, UInt<1>(0h1), "") : assert_57 node _T_631 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_631 : node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok_1, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(sink_ok, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_638, UInt<1>(0h1), "") : assert_60 node _T_642 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_642, UInt<1>(0h1), "") : assert_61 node _T_646 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_646, UInt<1>(0h1), "") : assert_62 node _T_650 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_650, UInt<1>(0h1), "") : assert_63 node _T_654 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_655, UInt<1>(0h1), "") : assert_64 node _T_659 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_659 : node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(source_ok_1, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(sink_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_666 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_666, UInt<1>(0h1), "") : assert_67 node _T_670 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_670, UInt<1>(0h1), "") : assert_68 node _T_674 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_674, UInt<1>(0h1), "") : assert_69 node _T_678 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_679 = or(_T_678, io.in.d.bits.corrupt) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_679, UInt<1>(0h1), "") : assert_70 node _T_683 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_684, UInt<1>(0h1), "") : assert_71 node _T_688 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_688 : node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok_1, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_692 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_692, UInt<1>(0h1), "") : assert_73 node _T_696 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_696, UInt<1>(0h1), "") : assert_74 node _T_700 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_701 = or(UInt<1>(0h0), _T_700) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_701, UInt<1>(0h1), "") : assert_75 node _T_705 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_705 : node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(source_ok_1, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_709 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(_T_709, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_709, UInt<1>(0h1), "") : assert_77 node _T_713 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_714 = or(_T_713, io.in.d.bits.corrupt) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_714, UInt<1>(0h1), "") : assert_78 node _T_718 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_719, UInt<1>(0h1), "") : assert_79 node _T_723 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(source_ok_1, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_727 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_727, UInt<1>(0h1), "") : assert_81 node _T_731 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_731, UInt<1>(0h1), "") : assert_82 node _T_735 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_736, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_740 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_740, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_744 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_744, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_748 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_748, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_752 = eq(a_first, UInt<1>(0h0)) node _T_753 = and(io.in.a.valid, _T_752) when _T_753 : node _T_754 = eq(io.in.a.bits.opcode, opcode) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_754, UInt<1>(0h1), "") : assert_87 node _T_758 = eq(io.in.a.bits.param, param) node _T_759 = asUInt(reset) node _T_760 = eq(_T_759, UInt<1>(0h0)) when _T_760 : node _T_761 = eq(_T_758, UInt<1>(0h0)) when _T_761 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_758, UInt<1>(0h1), "") : assert_88 node _T_762 = eq(io.in.a.bits.size, size) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_762, UInt<1>(0h1), "") : assert_89 node _T_766 = eq(io.in.a.bits.source, source) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_766, UInt<1>(0h1), "") : assert_90 node _T_770 = eq(io.in.a.bits.address, address) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_770, UInt<1>(0h1), "") : assert_91 node _T_774 = and(io.in.a.ready, io.in.a.valid) node _T_775 = and(_T_774, a_first) when _T_775 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_776 = eq(d_first, UInt<1>(0h0)) node _T_777 = and(io.in.d.valid, _T_776) when _T_777 : node _T_778 = eq(io.in.d.bits.opcode, opcode_1) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_778, UInt<1>(0h1), "") : assert_92 node _T_782 = eq(io.in.d.bits.param, param_1) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_782, UInt<1>(0h1), "") : assert_93 node _T_786 = eq(io.in.d.bits.size, size_1) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_786, UInt<1>(0h1), "") : assert_94 node _T_790 = eq(io.in.d.bits.source, source_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_790, UInt<1>(0h1), "") : assert_95 node _T_794 = eq(io.in.d.bits.sink, sink) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_794, UInt<1>(0h1), "") : assert_96 node _T_798 = eq(io.in.d.bits.denied, denied) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_798, UInt<1>(0h1), "") : assert_97 node _T_802 = and(io.in.d.ready, io.in.d.valid) node _T_803 = and(_T_802, d_first) when _T_803 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<58> connect a_set, UInt<58>(0h0) wire a_set_wo_ready : UInt<58> connect a_set_wo_ready, UInt<58>(0h0) wire a_opcodes_set : UInt<232> connect a_opcodes_set, UInt<232>(0h0) wire a_sizes_set : UInt<232> connect a_sizes_set, UInt<232>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_804 = and(io.in.a.valid, a_first_1) node _T_805 = and(_T_804, UInt<1>(0h1)) when _T_805 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_806 = and(io.in.a.ready, io.in.a.valid) node _T_807 = and(_T_806, a_first_1) node _T_808 = and(_T_807, UInt<1>(0h1)) when _T_808 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_809 = dshr(inflight, io.in.a.bits.source) node _T_810 = bits(_T_809, 0, 0) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_811, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<58> connect d_clr, UInt<58>(0h0) wire d_clr_wo_ready : UInt<58> connect d_clr_wo_ready, UInt<58>(0h0) wire d_opcodes_clr : UInt<232> connect d_opcodes_clr, UInt<232>(0h0) wire d_sizes_clr : UInt<232> connect d_sizes_clr, UInt<232>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_815 = and(io.in.d.valid, d_first_1) node _T_816 = and(_T_815, UInt<1>(0h1)) node _T_817 = eq(d_release_ack, UInt<1>(0h0)) node _T_818 = and(_T_816, _T_817) when _T_818 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_819 = and(io.in.d.ready, io.in.d.valid) node _T_820 = and(_T_819, d_first_1) node _T_821 = and(_T_820, UInt<1>(0h1)) node _T_822 = eq(d_release_ack, UInt<1>(0h0)) node _T_823 = and(_T_821, _T_822) when _T_823 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_824 = and(io.in.d.valid, d_first_1) node _T_825 = and(_T_824, UInt<1>(0h1)) node _T_826 = eq(d_release_ack, UInt<1>(0h0)) node _T_827 = and(_T_825, _T_826) when _T_827 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_828 = dshr(inflight, io.in.d.bits.source) node _T_829 = bits(_T_828, 0, 0) node _T_830 = or(_T_829, same_cycle_resp) node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_T_830, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_830, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_834 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_835 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_836 = or(_T_834, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_836, UInt<1>(0h1), "") : assert_100 node _T_840 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_840, UInt<1>(0h1), "") : assert_101 else : node _T_844 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_845 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_846 = or(_T_844, _T_845) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_846, UInt<1>(0h1), "") : assert_102 node _T_850 = eq(io.in.d.bits.size, a_size_lookup) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_850, UInt<1>(0h1), "") : assert_103 node _T_854 = and(io.in.d.valid, d_first_1) node _T_855 = and(_T_854, a_first_1) node _T_856 = and(_T_855, io.in.a.valid) node _T_857 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(d_release_ack, UInt<1>(0h0)) node _T_860 = and(_T_858, _T_859) when _T_860 : node _T_861 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_862 = or(_T_861, io.in.a.ready) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_862, UInt<1>(0h1), "") : assert_104 node _T_866 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_867 = orr(a_set_wo_ready) node _T_868 = eq(_T_867, UInt<1>(0h0)) node _T_869 = or(_T_866, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_869, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_81 node _T_873 = orr(inflight) node _T_874 = eq(_T_873, UInt<1>(0h0)) node _T_875 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_876 = or(_T_874, _T_875) node _T_877 = lt(watchdog, plusarg_reader.out) node _T_878 = or(_T_876, _T_877) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_878, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_882 = and(io.in.a.ready, io.in.a.valid) node _T_883 = and(io.in.d.ready, io.in.d.valid) node _T_884 = or(_T_882, _T_883) when _T_884 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0) regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0) regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<58> connect c_set, UInt<58>(0h0) wire c_set_wo_ready : UInt<58> connect c_set_wo_ready, UInt<58>(0h0) wire c_opcodes_set : UInt<232> connect c_opcodes_set, UInt<232>(0h0) wire c_sizes_set : UInt<232> connect c_sizes_set, UInt<232>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_885 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_886 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_887 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_888 = and(_T_886, _T_887) node _T_889 = and(_T_885, _T_888) when _T_889 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_890 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_891 = and(_T_890, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_892 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_893 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_894 = and(_T_892, _T_893) node _T_895 = and(_T_891, _T_894) when _T_895 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_896 = dshr(inflight_1, _WIRE_15.bits.source) node _T_897 = bits(_T_896, 0, 0) node _T_898 = eq(_T_897, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_898, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<58> connect d_clr_1, UInt<58>(0h0) wire d_clr_wo_ready_1 : UInt<58> connect d_clr_wo_ready_1, UInt<58>(0h0) wire d_opcodes_clr_1 : UInt<232> connect d_opcodes_clr_1, UInt<232>(0h0) wire d_sizes_clr_1 : UInt<232> connect d_sizes_clr_1, UInt<232>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_902 = and(io.in.d.valid, d_first_2) node _T_903 = and(_T_902, UInt<1>(0h1)) node _T_904 = and(_T_903, d_release_ack_1) when _T_904 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_905 = and(io.in.d.ready, io.in.d.valid) node _T_906 = and(_T_905, d_first_2) node _T_907 = and(_T_906, UInt<1>(0h1)) node _T_908 = and(_T_907, d_release_ack_1) when _T_908 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_909 = and(io.in.d.valid, d_first_2) node _T_910 = and(_T_909, UInt<1>(0h1)) node _T_911 = and(_T_910, d_release_ack_1) when _T_911 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_912 = dshr(inflight_1, io.in.d.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = or(_T_913, same_cycle_resp_1) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_914, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_918 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_918, UInt<1>(0h1), "") : assert_109 else : node _T_922 = eq(io.in.d.bits.size, c_size_lookup) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_922, UInt<1>(0h1), "") : assert_110 node _T_926 = and(io.in.d.valid, d_first_2) node _T_927 = and(_T_926, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_928 = and(_T_927, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_929 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_930 = and(_T_928, _T_929) node _T_931 = and(_T_930, d_release_ack_1) node _T_932 = eq(c_probe_ack, UInt<1>(0h0)) node _T_933 = and(_T_931, _T_932) when _T_933 : node _T_934 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_935 = or(_T_934, _WIRE_23.ready) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_935, UInt<1>(0h1), "") : assert_111 node _T_939 = orr(c_set_wo_ready) when _T_939 : node _T_940 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_940, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_82 node _T_944 = orr(inflight_1) node _T_945 = eq(_T_944, UInt<1>(0h0)) node _T_946 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_947 = or(_T_945, _T_946) node _T_948 = lt(watchdog_1, plusarg_reader_1.out) node _T_949 = or(_T_947, _T_948) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_949, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_953 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_954 = and(io.in.d.ready, io.in.d.valid) node _T_955 = or(_T_953, _T_954) when _T_955 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_36( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [57:0] inflight; // @[Monitor.scala:614:27] reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [231:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [57:0] inflight_1; // @[Monitor.scala:726:35] reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter2_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[2] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) reg resp_valid : UInt<1>[2], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node clock_en = or(_clock_en_T_3, UInt<1>(0h0)) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0)) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 26, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 17, 9) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 8, 0) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = eq(stage2, UInt<1>(0h0)) node _T_11 = and(do_both_stages, _T_10) node _T_12 = shr(tmp.ppn, 27) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = shr(tmp.ppn, 20) node _T_15 = neq(_T_14, UInt<1>(0h0)) node invalid_paddr = mux(_T_11, _T_13, _T_15) node _T_16 = eq(stage2, UInt<1>(0h0)) node _T_17 = and(do_both_stages, _T_16) node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = sub(_count_T_1, UInt<1>(0h0)) node count_1 = tail(_count_T_2, 1) node idxs_0 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[1] connect _WIRE[0], idxs_0 node _T_18 = or(count_1, UInt<0>(0h0)) node _T_19 = neq(_WIRE[0], UInt<1>(0h0)) node invalid_gpa = and(_T_17, _T_19) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h2)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 18) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_20 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_21 = and(io.dpath.perf.l2hit, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_22, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) reg state_reg : UInt<0>, clock reg state_vec : UInt<0>[512], clock smem l2_tlb_ram : UInt<45>[1] [512] reg g : UInt<512>[1], clock wire _valid_WIRE : UInt<512>[1] connect _valid_WIRE[0], UInt<512>(0h0) regreset valid : UInt<512>[1], clock, reset, _valid_WIRE node _T_26 = bits(r_req.addr, 26, 0) node _T_27 = cat(r_req.vstage1, _T_26) node r_tag = bits(_T_27, 27, 9) node r_idx = bits(_T_27, 8, 0) node _r_valid_vec_T = dshr(valid[0], r_idx) node r_valid_vec = bits(_r_valid_vec_T, 0, 0) reg r_valid_vec_q : UInt<1>, clock reg r_l2_plru_way : UInt<0>, clock connect r_valid_vec_q, r_valid_vec connect r_l2_plru_way, UInt<1>(0h0) node _T_28 = eq(invalidated, UInt<1>(0h0)) node _T_29 = and(l2_refill, _T_28) when _T_29 : wire entry : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} connect entry.ppn, r_pte.ppn connect entry.d, r_pte.d connect entry.a, r_pte.a connect entry.u, r_pte.u connect entry.x, r_pte.x connect entry.w, r_pte.w connect entry.r, r_pte.r connect entry.tag, r_tag node lo_lo = cat(entry.w, entry.r) node lo_hi = cat(entry.u, entry.x) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(entry.d, entry.a) node hi_hi = cat(entry.tag, entry.ppn) node hi = cat(hi_hi, hi_lo) node _T_30 = cat(hi, lo) node _T_31 = xorr(_T_30) node _T_32 = xor(_T_31, UInt<1>(0h0)) node _T_33 = cat(_T_32, _T_30) wire _WIRE_1 : UInt<45>[1] connect _WIRE_1[0], _T_33 write mport MPORT = l2_tlb_ram[r_idx], clock when UInt<1>(0h1) : connect MPORT[0], _WIRE_1[0] node mask = dshl(UInt<1>(0h1), r_idx) when UInt<1>(0h1) : node _valid_0_T = or(valid[0], mask) connect valid[0], _valid_0_T node _g_0_T = or(g[0], mask) node _g_0_T_1 = not(mask) node _g_0_T_2 = and(g[0], _g_0_T_1) node _g_0_T_3 = mux(r_pte.g, _g_0_T, _g_0_T_2) connect g[0], _g_0_T_3 when io.dpath.sfence.valid : node hg = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _valid_0_T_1 = eq(hg, UInt<1>(0h0)) node _valid_0_T_2 = and(_valid_0_T_1, io.dpath.sfence.bits.rs1) node _valid_0_T_3 = bits(io.dpath.sfence.bits.addr, 20, 12) node _valid_0_T_4 = dshl(UInt<1>(0h1), _valid_0_T_3) node _valid_0_T_5 = not(_valid_0_T_4) node _valid_0_T_6 = and(valid[0], _valid_0_T_5) node _valid_0_T_7 = eq(hg, UInt<1>(0h0)) node _valid_0_T_8 = and(_valid_0_T_7, io.dpath.sfence.bits.rs2) node _valid_0_T_9 = and(valid[0], g[0]) node _valid_0_T_10 = mux(_valid_0_T_8, _valid_0_T_9, UInt<1>(0h0)) node _valid_0_T_11 = mux(_valid_0_T_2, _valid_0_T_6, _valid_0_T_10) connect valid[0], _valid_0_T_11 node _s0_valid_T = eq(l2_refill, UInt<1>(0h0)) node _s0_valid_T_1 = and(arb.io.out.ready, arb.io.out.valid) node s0_valid = and(_s0_valid_T, _s0_valid_T_1) node _s0_suitable_T = eq(arb.io.out.bits.bits.vstage1, arb.io.out.bits.bits.stage2) node _s0_suitable_T_1 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node s0_suitable = and(_s0_suitable_T, _s0_suitable_T_1) node _s1_valid_T = and(s0_valid, s0_suitable) node _s1_valid_T_1 = and(_s1_valid_T, arb.io.out.bits.valid) reg s1_valid : UInt<1>, clock connect s1_valid, _s1_valid_T_1 reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid node _s1_rdata_T = bits(arb.io.out.bits.bits.addr, 8, 0) wire _s1_rdata_WIRE : UInt<9> invalidate _s1_rdata_WIRE when s0_valid : connect _s1_rdata_WIRE, _s1_rdata_T read mport s1_rdata = l2_tlb_ram[_s1_rdata_WIRE], clock reg r : UInt<45>, clock when s1_valid : connect r, s1_rdata[0] node uncorrected = bits(r, 43, 0) node uncorrectable = xorr(r) reg s2_valid_vec : UInt<1>, clock when s1_valid : connect s2_valid_vec, r_valid_vec node _s2_g_vec_T = dshr(g[0], r_idx) node _s2_g_vec_T_1 = bits(_s2_g_vec_T, 0, 0) wire _s2_g_vec_WIRE : UInt<1>[1] connect _s2_g_vec_WIRE[0], _s2_g_vec_T_1 reg s2_g_vec : UInt<1>[1], clock when s1_valid : connect s2_g_vec, _s2_g_vec_WIRE node _s2_error_T = bits(s2_valid_vec, 0, 0) node _s2_error_T_1 = or(UInt<1>(0h0), uncorrectable) node l2_error = and(_s2_error_T, _s2_error_T_1) node _T_34 = and(s2_valid, l2_error) when _T_34 : connect valid[0], UInt<1>(0h0) wire s2_entry_vec_0 : { tag : UInt<18>, ppn : UInt<20>, d : UInt<1>, a : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _s2_entry_vec_WIRE : UInt<44> connect _s2_entry_vec_WIRE, uncorrected node _s2_entry_vec_T = bits(_s2_entry_vec_WIRE, 0, 0) connect s2_entry_vec_0.r, _s2_entry_vec_T node _s2_entry_vec_T_1 = bits(_s2_entry_vec_WIRE, 1, 1) connect s2_entry_vec_0.w, _s2_entry_vec_T_1 node _s2_entry_vec_T_2 = bits(_s2_entry_vec_WIRE, 2, 2) connect s2_entry_vec_0.x, _s2_entry_vec_T_2 node _s2_entry_vec_T_3 = bits(_s2_entry_vec_WIRE, 3, 3) connect s2_entry_vec_0.u, _s2_entry_vec_T_3 node _s2_entry_vec_T_4 = bits(_s2_entry_vec_WIRE, 4, 4) connect s2_entry_vec_0.a, _s2_entry_vec_T_4 node _s2_entry_vec_T_5 = bits(_s2_entry_vec_WIRE, 5, 5) connect s2_entry_vec_0.d, _s2_entry_vec_T_5 node _s2_entry_vec_T_6 = bits(_s2_entry_vec_WIRE, 25, 6) connect s2_entry_vec_0.ppn, _s2_entry_vec_T_6 node _s2_entry_vec_T_7 = bits(_s2_entry_vec_WIRE, 43, 26) connect s2_entry_vec_0.tag, _s2_entry_vec_T_7 node _s2_hit_vec_T = bits(s2_valid_vec, 0, 0) node _s2_hit_vec_T_1 = eq(r_tag, s2_entry_vec_0.tag) node s2_hit_vec_0 = and(_s2_hit_vec_T, _s2_hit_vec_T_1) node l2_hit = and(s2_valid, s2_hit_vec_0) node _io_dpath_perf_l2miss_T = eq(s2_hit_vec_0, UInt<1>(0h0)) node _io_dpath_perf_l2miss_T_1 = and(s2_valid, _io_dpath_perf_l2miss_T) connect io.dpath.perf.l2miss, _io_dpath_perf_l2miss_T_1 connect io.dpath.perf.l2hit, l2_hit when l2_hit : connect state_vec[r_idx], UInt<1>(0h0) node _T_35 = eq(s2_hit_vec_0, UInt<1>(0h1)) node _T_36 = or(_T_35, l2_error) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: L2 TLB multi-hit\n at PTW.scala:486 assert((PopCount(s2_hit_vec) === 1.U) || s2_error, \"L2 TLB multi-hit\")\n") : printf_1 assert(clock, _T_36, UInt<1>(0h1), "") : assert_1 wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte.ppn, s2_entry_vec_0.ppn connect l2_pte.d, s2_entry_vec_0.d connect l2_pte.a, s2_entry_vec_0.a connect l2_pte.g, s2_g_vec[0] connect l2_pte.u, s2_entry_vec_0.u connect l2_pte.x, s2_entry_vec_0.x connect l2_pte.w, s2_entry_vec_0.w connect l2_pte.r, s2_entry_vec_0.r connect l2_pte.v, UInt<1>(0h1) connect l2_pte.reserved_for_future, UInt<1>(0h0) connect l2_pte.reserved_for_software, UInt<1>(0h0) node _T_40 = and(l2_hit, s2_hit_vec_0) node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(l2_hit, _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8) node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10) node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13) node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12) node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21) node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23) node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25) node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38) node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40) node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43) node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48) node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53) node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58) node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63) node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68) node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73) node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78) node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83) node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42) node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98) node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100) node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102) node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110) node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115) node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120) node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125) node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135) node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137) node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140) node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139) node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node homogeneous = and(pmaHomogeneous, UInt<1>(0h1)) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_41 = eq(UInt<3>(0h0), state) when _T_41 : node _T_42 = and(arb.io.out.ready, arb.io.out.valid) when _T_42 : node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0)) node satp_initial_count = tail(_satp_initial_count_T_2, 1) node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0)) node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1) node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0)) node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_3 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0)) node resp_gf_count = tail(_resp_gf_count_T_2, 1) node resp_gf_idxs_0 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[1] connect _resp_gf_WIRE[0], resp_gf_idxs_0 node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0)) node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0)) node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_2 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_43 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_44 = or(_T_43, arb.io.out.bits.bits.stage2) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_2 assert(clock, _T_44, UInt<1>(0h1), "") : assert_2 else : node _T_48 = eq(UInt<3>(0h1), state) when _T_48 : node _T_49 = eq(count, r_hgatp_initial_count) node _T_50 = and(stage2, _T_49) when _T_50 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when UInt<1>(0h0) : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, UInt<1>(0h0) connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when UInt<1>(0h0) : node _count_T_4 = add(count, UInt<1>(0h1)) node _count_T_5 = tail(_count_T_4, 1) connect count, _count_T_5 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_51 = or(r_req_dest, UInt<1>(0h0)) node _T_52 = bits(_T_51, 0, 0) connect resp_valid[_T_52], UInt<1>(0h1) else : node _T_53 = eq(UInt<3>(0h2), state) when _T_53 : node _next_state_T_2 = mux(l2_hit, UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_54 = eq(UInt<3>(0h4), state) when _T_54 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_55 = or(r_req_dest, UInt<1>(0h0)) node _T_56 = bits(_T_55, 0, 0) connect resp_valid[_T_56], UInt<1>(0h1) else : node _T_57 = eq(UInt<3>(0h7), state) when _T_57 : connect next_state, UInt<3>(0h0) node _T_58 = or(r_req_dest, UInt<1>(0h0)) node _T_59 = bits(_T_58, 0, 0) connect resp_valid[_T_59], UInt<1>(0h1) node _T_60 = eq(homogeneous, UInt<1>(0h0)) when _T_60 : connect count, UInt<2>(0h2) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(l2_error, UInt<1>(0h0)) node _r_pte_T_1 = and(l2_hit, _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, UInt<1>(0h0)) node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0)) node r_pte_count = tail(_r_pte_count_T_2, 1) node r_pte_idxs_0 = shr(UInt<1>(0h0), 27) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, r_pte_idxs_0 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, UInt<1>(0h0)) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, UInt<1>(0h0) node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1) node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0)) node r_pte_count_1 = tail(_r_pte_count_T_5, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 27) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, r_pte_idxs_0_1 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h2)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 18) node _r_pte_T_18 = bits(r_req.addr, 17, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 9) node _r_pte_T_21 = bits(r_req.addr, 8, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_truncIdx_T = or(count, UInt<1>(0h0)) node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0) node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1)) node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_24 node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1) node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0)) node r_pte_count_2 = tail(_r_pte_count_T_8, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, r_pte_idxs_0_2 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte) node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27) node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28) node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29) node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30) node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31) node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_33.v connect r_pte_barrier.io.x.r, _r_pte_T_33.r connect r_pte_barrier.io.x.w, _r_pte_T_33.w connect r_pte_barrier.io.x.x, _r_pte_T_33.x connect r_pte_barrier.io.x.u, _r_pte_T_33.u connect r_pte_barrier.io.x.g, _r_pte_T_33.g connect r_pte_barrier.io.x.a, _r_pte_T_33.a connect r_pte_barrier.io.x.d, _r_pte_T_33.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_61 = eq(l2_error, UInt<1>(0h0)) node _T_62 = and(l2_hit, _T_61) node _T_63 = eq(resp_gf, UInt<1>(0h0)) node _T_64 = and(_T_62, _T_63) when _T_64 : node _T_65 = eq(state, UInt<3>(0h1)) node _T_66 = eq(state, UInt<3>(0h2)) node _T_67 = or(_T_65, _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h0) node _T_71 = or(r_req_dest, UInt<1>(0h0)) node _T_72 = bits(_T_71, 0, 0) connect resp_valid[_T_72], UInt<1>(0h1) connect count, UInt<2>(0h2) when mem_resp_valid : node _T_73 = eq(state, UInt<3>(0h5)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_4 assert(clock, _T_73, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when traverse : node _T_77 = eq(stage2, UInt<1>(0h0)) node _T_78 = and(do_both_stages, _T_77) when _T_78 : connect do_switch, UInt<1>(0h1) node _count_T_6 = add(count, UInt<1>(0h1)) node _count_T_7 = tail(_count_T_6, 1) connect count, _count_T_7 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_79 = eq(stage2_final, UInt<1>(0h0)) node _T_80 = and(do_both_stages, _T_79) node _T_81 = and(_T_80, success) when _T_81 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h2)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_82 = eq(count, UInt<2>(0h2)) node _T_83 = eq(do_both_stages, UInt<1>(0h0)) node _T_84 = eq(aux_count, UInt<2>(0h2)) node _T_85 = or(_T_83, _T_84) node _T_86 = and(_T_82, _T_85) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = and(UInt<1>(0h0), _T_87) when _T_88 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_89 = or(r_req_dest, UInt<1>(0h0)) node _T_90 = bits(_T_89, 0, 0) connect resp_valid[_T_90], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h2)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_3 = and(pf, stage2) node _resp_gf_T_4 = or(gf, _resp_gf_T_3) connect resp_gf, _resp_gf_T_4 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_91 = eq(state, UInt<3>(0h4)) node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : node _T_94 = eq(_T_91, UInt<1>(0h0)) when _T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_5 assert(clock, _T_91, UInt<1>(0h1), "") : assert_5 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_95 = and(leaf, pte.v) node _T_96 = eq(invalid_paddr, UInt<1>(0h0)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(invalid_gpa, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = and(leaf, pte.v) node _T_103 = and(_T_102, invalid_paddr) node _T_104 = and(leaf, pte.v) node _T_105 = and(_T_104, invalid_gpa) node _T_106 = and(leaf, pte.v) node _T_107 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = bits(mem_resp_data, 0, 0) node _T_110 = eq(_T_109, UInt<1>(0h0)) node _T_111 = and(leaf, _T_110) node _T_112 = eq(pte.v, UInt<1>(0h0)) node _T_113 = and(leaf, _T_112) node _T_114 = bits(mem_resp_data, 0, 0) node _T_115 = and(_T_113, _T_114) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_116 = and(leaf_1, pte.v) node _T_117 = eq(invalid_paddr, UInt<1>(0h0)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(invalid_gpa, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = and(leaf_1, pte.v) node _T_124 = and(_T_123, invalid_paddr) node _T_125 = and(leaf_1, pte.v) node _T_126 = and(_T_125, invalid_gpa) node _T_127 = and(leaf_1, pte.v) node _T_128 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = bits(mem_resp_data, 0, 0) node _T_131 = eq(_T_130, UInt<1>(0h0)) node _T_132 = and(leaf_1, _T_131) node _T_133 = eq(pte.v, UInt<1>(0h0)) node _T_134 = and(leaf_1, _T_133) node _T_135 = bits(mem_resp_data, 0, 0) node _T_136 = and(_T_134, _T_135) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_137 = and(leaf_2, pte.v) node _T_138 = eq(invalid_paddr, UInt<1>(0h0)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(invalid_gpa, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = and(leaf_2, pte.v) node _T_145 = and(_T_144, invalid_paddr) node _T_146 = and(leaf_2, pte.v) node _T_147 = and(_T_146, invalid_gpa) node _T_148 = and(leaf_2, pte.v) node _T_149 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = bits(mem_resp_data, 0, 0) node _T_152 = eq(_T_151, UInt<1>(0h0)) node _T_153 = and(leaf_2, _T_152) node _T_154 = eq(count, UInt<2>(0h2)) node _T_155 = and(mem_resp_valid, _T_154) node _T_156 = eq(pte.r, UInt<1>(0h0)) node _T_157 = and(pte.v, _T_156) node _T_158 = eq(pte.w, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(pte.x, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(pte.d, UInt<1>(0h0)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(pte.a, UInt<1>(0h0)) node _T_165 = and(_T_163, _T_164) node _T_166 = eq(pte.u, UInt<1>(0h0)) node _T_167 = and(_T_165, _T_166) node _T_168 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_169 = and(_T_167, _T_168) node _T_170 = and(_T_155, _T_169) node _T_171 = eq(state, UInt<3>(0h4)) node _T_172 = and(_T_171, io.mem.s2_xcpt.ae.ld)
module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_sd, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_sd, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_ordered, // @[PTW.scala:220:14] input io_mem_perf_acquire, // @[PTW.scala:220:14] input io_mem_perf_release, // @[PTW.scala:220:14] input io_mem_perf_grant, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_sd, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_hstatus_spvp, // @[PTW.scala:220:14] input io_dpath_hstatus_spv, // @[PTW.scala:220:14] input io_dpath_hstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_debug, // @[PTW.scala:220:14] input io_dpath_gstatus_cease, // @[PTW.scala:220:14] input io_dpath_gstatus_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14] input io_dpath_gstatus_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14] input io_dpath_gstatus_v, // @[PTW.scala:220:14] input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14] input io_dpath_gstatus_mpv, // @[PTW.scala:220:14] input io_dpath_gstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_mbe, // @[PTW.scala:220:14] input io_dpath_gstatus_sbe, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14] input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14] input io_dpath_gstatus_tsr, // @[PTW.scala:220:14] input io_dpath_gstatus_tw, // @[PTW.scala:220:14] input io_dpath_gstatus_tvm, // @[PTW.scala:220:14] input io_dpath_gstatus_mxr, // @[PTW.scala:220:14] input io_dpath_gstatus_sum, // @[PTW.scala:220:14] input io_dpath_gstatus_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14] input io_dpath_gstatus_spp, // @[PTW.scala:220:14] input io_dpath_gstatus_mpie, // @[PTW.scala:220:14] input io_dpath_gstatus_ube, // @[PTW.scala:220:14] input io_dpath_gstatus_spie, // @[PTW.scala:220:14] input io_dpath_gstatus_upie, // @[PTW.scala:220:14] input io_dpath_gstatus_mie, // @[PTW.scala:220:14] input io_dpath_gstatus_hie, // @[PTW.scala:220:14] input io_dpath_gstatus_sie, // @[PTW.scala:220:14] input io_dpath_gstatus_uie, // @[PTW.scala:220:14] output io_dpath_perf_l2miss, // @[PTW.scala:220:14] output io_dpath_perf_l2hit, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire s2_entry_vec_0_w; // @[PTW.scala:479:59] wire s2_entry_vec_0_x; // @[PTW.scala:479:59] wire s2_entry_vec_0_u; // @[PTW.scala:479:59] wire s2_entry_vec_0_a; // @[PTW.scala:479:59] wire s2_entry_vec_0_d; // @[PTW.scala:479:59] wire writeEnable; // @[PTW.scala:433:21] wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire [44:0] _l2_tlb_ram_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7] wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] r_pte_pte_1_ppn = 44'h0; // @[PTW.scala:771:26] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire [31:0] io_requestor_0_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa = 32'h14112D; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_uncached = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv = 1'h0; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay = 1'h0; // @[PTW.scala:219:7] wire io_mem_replay_next = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_store_pending = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_blocked = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _io_dpath_perf_pte_hit_T_1 = 1'h0; // @[PTW.scala:394:36] wire _io_dpath_perf_pte_hit_T_3 = 1'h0; // @[PTW.scala:394:57] wire hg = 1'h0; // @[PTW.scala:458:34] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire _r_pte_T_7 = 1'h0; // @[PTW.scala:674:25] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:489:22] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire _valid_0_T_1 = 1'h1; // @[PTW.scala:461:15] wire _valid_0_T_7 = 1'h1; // @[PTW.scala:462:15] wire _s0_suitable_T = 1'h1; // @[PTW.scala:468:52] wire l2_pte_v = 1'h1; // @[PTW.scala:489:22] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire r_pte_pte_v = 1'h1; // @[PTW.scala:780:26] wire r_pte_pte_1_v = 1'h1; // @[PTW.scala:771:26] wire [1:0] io_requestor_0_gstatus_fs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs = 2'h3; // @[PTW.scala:219:7] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data = 64'h0; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr = 40'h0; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa = 40'h0; // @[PTW.scala:219:7] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:489:22] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [2:0] _next_state_T = 3'h1; // @[PTW.scala:593:26] wire [511:0] _valid_WIRE_0 = 512'h0; // @[PTW.scala:422:32] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire _valid_0_T_2 = io_dpath_sfence_bits_rs1_0; // @[PTW.scala:219:7, :461:19] wire _valid_0_T_8 = io_dpath_sfence_bits_rs2_0; // @[PTW.scala:219:7, :462:19] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire _io_dpath_perf_l2miss_T_1; // @[PTW.scala:482:38] wire l2_hit; // @[PTW.scala:481:27] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire entry_d = r_pte_d; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire entry_a = r_pte_a; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire entry_u = r_pte_u; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire entry_x = r_pte_x; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire entry_w = r_pte_w; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire entry_r = r_pte_r; // @[PTW.scala:275:18, :434:23] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20] reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20] reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _GEN = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _GEN; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _GEN; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _GEN; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _GEN; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _GEN; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_154 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_154; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_154; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_154; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_154; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_154; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_154; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] wire _T_65 = state == 3'h1; // @[PTW.scala:233:22, :394:46] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_65; // @[PTW.scala:394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_65; // @[PTW.scala:394:46, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_65; // @[PTW.scala:394:46, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_65; // @[PTW.scala:394:46, :674:15] wire _io_dpath_perf_pte_hit_T_2 = ~io_dpath_perf_l2hit_0; // @[PTW.scala:219:7, :394:60] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire [8:0] r_idx; // @[package.scala:163:13] wire [8:0] _s1_rdata_WIRE; // @[PTW.scala:472:28] wire s0_valid; // @[PTW.scala:467:31] reg [511:0] g_0; // @[PTW.scala:421:16] reg [511:0] valid_0; // @[PTW.scala:422:24] wire [18:0] r_tag = {r_req_vstage1, r_req_addr[26:9]}; // @[package.scala:163:13] assign r_idx = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[package.scala:163:13] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[package.scala:163:13] wire [511:0] _GEN_0 = {503'h0, r_idx}; // @[package.scala:163:13] wire [511:0] _r_valid_vec_T = valid_0 >> _GEN_0; // @[PTW.scala:422:24, :426:34] wire r_valid_vec = _r_valid_vec_T[0]; // @[PTW.scala:426:34] reg r_valid_vec_q; // @[PTW.scala:427:28] assign writeEnable = l2_refill & ~invalidated; // @[PTW.scala:251:24, :398:26, :433:{21,24}] wire [17:0] entry_tag; // @[PTW.scala:434:23] wire [19:0] entry_ppn; // @[PTW.scala:434:23] assign entry_ppn = r_pte_ppn[19:0]; // @[PTW.scala:275:18, :434:23, :435:17] assign entry_tag = r_tag[17:0]; // @[package.scala:163:13] wire [1:0] lo_lo = {entry_w, entry_r}; // @[PTW.scala:434:23, :446:82] wire [1:0] lo_hi = {entry_u, entry_x}; // @[PTW.scala:434:23, :446:82] wire [3:0] lo = {lo_hi, lo_lo}; // @[PTW.scala:446:82] wire [1:0] hi_lo = {entry_d, entry_a}; // @[PTW.scala:434:23, :446:82] wire [37:0] hi_hi = {entry_tag, entry_ppn}; // @[PTW.scala:434:23, :446:82] wire [39:0] hi = {hi_hi, hi_lo}; // @[PTW.scala:446:82] wire [511:0] mask = 512'h1 << _GEN_0; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T = valid_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T = g_0 | mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_1 = ~mask; // @[OneHot.scala:58:35] wire [511:0] _g_0_T_2 = g_0 & _g_0_T_1; // @[PTW.scala:421:16, :452:{56,58}] wire [511:0] _g_0_T_3 = r_pte_g ? _g_0_T : _g_0_T_2; // @[PTW.scala:275:18, :452:{24,41,56}] wire [8:0] _valid_0_T_3 = io_dpath_sfence_bits_addr_0[20:12]; // @[PTW.scala:219:7, :461:96] wire [511:0] _valid_0_T_4 = 512'h1 << _valid_0_T_3; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_5 = ~_valid_0_T_4; // @[OneHot.scala:58:35] wire [511:0] _valid_0_T_6 = valid_0 & _valid_0_T_5; // @[PTW.scala:422:24, :461:{59,61}] wire [511:0] _valid_0_T_9 = valid_0 & g_0; // @[PTW.scala:421:16, :422:24, :462:59] wire [511:0] _valid_0_T_10 = _valid_0_T_8 ? _valid_0_T_9 : 512'h0; // @[PTW.scala:462:{14,19,59}] wire [511:0] _valid_0_T_11 = _valid_0_T_2 ? _valid_0_T_6 : _valid_0_T_10; // @[PTW.scala:461:{14,19,59}, :462:14] wire _s0_valid_T = ~l2_refill; // @[PTW.scala:398:26, :467:20] wire _T_42 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_1; // @[Decoupled.scala:51:35] assign _s0_valid_T_1 = _T_42; // @[Decoupled.scala:51:35] wire _r_pte_T_25; // @[Decoupled.scala:51:35] assign _r_pte_T_25 = _T_42; // @[Decoupled.scala:51:35] assign s0_valid = _s0_valid_T & _s0_valid_T_1; // @[Decoupled.scala:51:35] wire _s0_suitable_T_1 = ~_arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19, :468:87] wire s0_suitable = _s0_suitable_T_1; // @[PTW.scala:468:{84,87}] wire _s1_valid_T = s0_valid & s0_suitable; // @[PTW.scala:467:31, :468:84, :469:37] wire _s1_valid_T_1 = _s1_valid_T; // @[PTW.scala:469:{37,52}] reg s1_valid; // @[PTW.scala:469:27] reg s2_valid; // @[PTW.scala:470:27] wire [8:0] _s1_rdata_T = _arb_io_out_bits_bits_addr[8:0]; // @[PTW.scala:236:19, :472:54] assign _s1_rdata_WIRE = _s1_rdata_T; // @[PTW.scala:472:{28,54}] reg [44:0] r; // @[PTW.scala:473:66] wire [43:0] uncorrected = r[43:0]; // @[ECC.scala:75:24] wire [43:0] _s2_entry_vec_WIRE = uncorrected; // @[ECC.scala:75:24] wire uncorrectable = ^r; // @[ECC.scala:78:27] wire _s2_error_T_1 = uncorrectable; // @[ECC.scala:15:27, :78:27] reg s2_valid_vec; // @[PTW.scala:474:33] wire _s2_error_T = s2_valid_vec; // @[PTW.scala:474:33, :476:75] wire _s2_hit_vec_T = s2_valid_vec; // @[PTW.scala:474:33, :480:77] wire [511:0] _s2_g_vec_T = g_0 >> _GEN_0; // @[PTW.scala:421:16, :426:34, :475:45] wire _s2_g_vec_T_1 = _s2_g_vec_T[0]; // @[PTW.scala:475:45] wire _s2_g_vec_WIRE_0 = _s2_g_vec_T_1; // @[PTW.scala:475:{37,45}] reg s2_g_vec_0; // @[PTW.scala:475:29] wire l2_pte_g = s2_g_vec_0; // @[PTW.scala:475:29, :489:22] wire l2_error = _s2_error_T & _s2_error_T_1; // @[ECC.scala:15:27] wire [17:0] _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire [19:0] _s2_entry_vec_T_6; // @[PTW.scala:479:59] wire _s2_entry_vec_T_5; // @[PTW.scala:479:59] wire _s2_entry_vec_T_4; // @[PTW.scala:479:59] wire l2_pte_d = s2_entry_vec_0_d; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_3; // @[PTW.scala:479:59] wire l2_pte_a = s2_entry_vec_0_a; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_2; // @[PTW.scala:479:59] wire l2_pte_u = s2_entry_vec_0_u; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T_1; // @[PTW.scala:479:59] wire l2_pte_x = s2_entry_vec_0_x; // @[PTW.scala:479:59, :489:22] wire _s2_entry_vec_T; // @[PTW.scala:479:59] wire l2_pte_w = s2_entry_vec_0_w; // @[PTW.scala:479:59, :489:22] wire [17:0] s2_entry_vec_0_tag; // @[PTW.scala:479:59] wire [19:0] s2_entry_vec_0_ppn; // @[PTW.scala:479:59] wire s2_entry_vec_0_r; // @[PTW.scala:479:59] wire l2_pte_r = s2_entry_vec_0_r; // @[PTW.scala:479:59, :489:22] assign _s2_entry_vec_T = _s2_entry_vec_WIRE[0]; // @[PTW.scala:479:59] assign s2_entry_vec_0_r = _s2_entry_vec_T; // @[PTW.scala:479:59] assign _s2_entry_vec_T_1 = _s2_entry_vec_WIRE[1]; // @[PTW.scala:479:59] assign s2_entry_vec_0_w = _s2_entry_vec_T_1; // @[PTW.scala:479:59] assign _s2_entry_vec_T_2 = _s2_entry_vec_WIRE[2]; // @[PTW.scala:479:59] assign s2_entry_vec_0_x = _s2_entry_vec_T_2; // @[PTW.scala:479:59] assign _s2_entry_vec_T_3 = _s2_entry_vec_WIRE[3]; // @[PTW.scala:479:59] assign s2_entry_vec_0_u = _s2_entry_vec_T_3; // @[PTW.scala:479:59] assign _s2_entry_vec_T_4 = _s2_entry_vec_WIRE[4]; // @[PTW.scala:479:59] assign s2_entry_vec_0_a = _s2_entry_vec_T_4; // @[PTW.scala:479:59] assign _s2_entry_vec_T_5 = _s2_entry_vec_WIRE[5]; // @[PTW.scala:479:59] assign s2_entry_vec_0_d = _s2_entry_vec_T_5; // @[PTW.scala:479:59] assign _s2_entry_vec_T_6 = _s2_entry_vec_WIRE[25:6]; // @[PTW.scala:479:59] assign s2_entry_vec_0_ppn = _s2_entry_vec_T_6; // @[PTW.scala:479:59] assign _s2_entry_vec_T_7 = _s2_entry_vec_WIRE[43:26]; // @[PTW.scala:479:59] assign s2_entry_vec_0_tag = _s2_entry_vec_T_7; // @[PTW.scala:479:59] wire _s2_hit_vec_T_1 = r_tag == {1'h0, s2_entry_vec_0_tag}; // @[package.scala:163:13] wire s2_hit_vec_0 = _s2_hit_vec_T & _s2_hit_vec_T_1; // @[PTW.scala:480:{77,83,93}] assign l2_hit = s2_valid & s2_hit_vec_0; // @[PTW.scala:470:27, :480:83, :481:27] assign io_dpath_perf_l2hit_0 = l2_hit; // @[PTW.scala:219:7, :481:27] wire _io_dpath_perf_l2miss_T = ~s2_hit_vec_0; // @[PTW.scala:480:83, :482:41] assign _io_dpath_perf_l2miss_T_1 = s2_valid & _io_dpath_perf_l2miss_T; // @[PTW.scala:470:27, :482:{38,41}] assign io_dpath_perf_l2miss_0 = _io_dpath_perf_l2miss_T_1; // @[PTW.scala:219:7, :482:38] wire r_pte_pte_d = l2_pte_d; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_d = l2_pte_d; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_a = l2_pte_a; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_a = l2_pte_a; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_g = l2_pte_g; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_g = l2_pte_g; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_u = l2_pte_u; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_u = l2_pte_u; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_x = l2_pte_x; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_x = l2_pte_x; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_w = l2_pte_w; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_w = l2_pte_w; // @[PTW.scala:489:22, :771:26] wire r_pte_pte_r = l2_pte_r; // @[PTW.scala:489:22, :780:26] wire r_pte_pte_1_r = l2_pte_r; // @[PTW.scala:489:22, :771:26] wire [43:0] l2_pte_ppn; // @[PTW.scala:489:22] assign l2_pte_ppn = {24'h0, s2_entry_vec_0_ppn}; // @[PTW.scala:479:59, :489:22, :491:16] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = l2_hit | _io_mem_s1_kill_T; // @[PTW.scala:481:27, :531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN_1 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN_1; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN_1; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_98 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_115 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_68 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_120 = _GEN_4; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_135 = _GEN_4; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_5 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_83 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_125 = _GEN_5; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_140 = _GEN_5; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire homogeneous = pmaHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_84 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_84; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_84; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_84; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _GEN_6 = ~(|state) & _T_42; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_7 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_7; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_7; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_7; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_53 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire [2:0] _next_state_T_2 = l2_hit ? 3'h1 : 3'h4; // @[PTW.scala:481:27, :636:24] wire _T_54 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _T_65 | _T_53) & _T_54 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :394:46, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T = ~l2_error; // @[PTW.scala:476:81, :670:19] wire _r_pte_T_1 = l2_hit & _r_pte_T; // @[PTW.scala:481:27, :670:{16,19}] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire _r_pte_T_3 = _r_pte_T_1 & _r_pte_T_2; // @[PTW.scala:670:{16,29,32}] wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26] wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}] assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:8, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_30_ppn; // @[PTW.scala:674:8, :676:8] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_d = _r_pte_T_30_d; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_a = _r_pte_T_30_a; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_g = _r_pte_T_30_g; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_u = _r_pte_T_30_u; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_x = _r_pte_T_30_x; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_w = _r_pte_T_30_w; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_r = _r_pte_T_30_r; // @[PTW.scala:674:8, :676:8] wire _r_pte_T_31_v = _r_pte_T_30_v; // @[PTW.scala:674:8, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_3 ? 10'h0 : _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:{8,29}, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_3 ? l2_pte_ppn : _r_pte_T_32_ppn; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_3 ? 2'h0 : _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:{8,29}, :672:8] wire _r_pte_T_33_d = _r_pte_T_3 ? l2_pte_d : _r_pte_T_32_d; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_a = _r_pte_T_3 ? l2_pte_a : _r_pte_T_32_a; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_g = _r_pte_T_3 ? l2_pte_g : _r_pte_T_32_g; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_u = _r_pte_T_3 ? l2_pte_u : _r_pte_T_32_u; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_x = _r_pte_T_3 ? l2_pte_x : _r_pte_T_32_x; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_w = _r_pte_T_3 ? l2_pte_w : _r_pte_T_32_w; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_r = _r_pte_T_3 ? l2_pte_r : _r_pte_T_32_r; // @[PTW.scala:489:22, :670:{8,29}, :672:8] wire _r_pte_T_33_v = _r_pte_T_3 | _r_pte_T_32_v; // @[PTW.scala:670:{8,29}, :672:8] wire _T_64 = l2_hit & ~l2_error & ~resp_gf; // @[PTW.scala:263:20, :476:81, :481:27, :670:{19,32}, :685:{16,29}] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_81 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :566:15, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_81 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_8 = traverse | _T_81; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing_5 : input clock : Clock input reset : Reset output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3], iss_valids : UInt<1>[3], iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip fu_types : UInt<10>[3], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush_pipeline : UInt<1>, flip ld_miss : UInt<1>, event_empty : UInt<1>, flip tsc_reg : UInt<64>} wire _WIRE : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} wire _WIRE_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} wire _WIRE_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect _WIRE, io.dis_uops[0].bits connect _WIRE.iw_p1_poisoned, UInt<1>(0h0) connect _WIRE.iw_p2_poisoned, UInt<1>(0h0) connect _WIRE.iw_state, UInt<2>(0h1) node _T = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2)) node _T_1 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) node _T_2 = and(_T, _T_1) node _T_3 = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h43)) node _T_4 = or(_T_2, _T_3) when _T_4 : connect _WIRE.iw_state, UInt<2>(0h2) else : node _T_5 = eq(io.dis_uops[0].bits.uopc, UInt<7>(0h2)) node _T_6 = neq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) node _T_7 = and(_T_5, _T_6) when _T_7 : connect _WIRE.lrs2_rtype, UInt<2>(0h2) connect _WIRE.prs2_busy, UInt<1>(0h0) connect _WIRE.prs3_busy, UInt<1>(0h0) connect _WIRE_1, io.dis_uops[1].bits connect _WIRE_1.iw_p1_poisoned, UInt<1>(0h0) connect _WIRE_1.iw_p2_poisoned, UInt<1>(0h0) connect _WIRE_1.iw_state, UInt<2>(0h1) node _T_8 = eq(io.dis_uops[1].bits.uopc, UInt<7>(0h2)) node _T_9 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.dis_uops[1].bits.uopc, UInt<7>(0h43)) node _T_12 = or(_T_10, _T_11) when _T_12 : connect _WIRE_1.iw_state, UInt<2>(0h2) else : node _T_13 = eq(io.dis_uops[1].bits.uopc, UInt<7>(0h2)) node _T_14 = neq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) node _T_15 = and(_T_13, _T_14) when _T_15 : connect _WIRE_1.lrs2_rtype, UInt<2>(0h2) connect _WIRE_1.prs2_busy, UInt<1>(0h0) connect _WIRE_1.prs3_busy, UInt<1>(0h0) connect _WIRE_2, io.dis_uops[2].bits connect _WIRE_2.iw_p1_poisoned, UInt<1>(0h0) connect _WIRE_2.iw_p2_poisoned, UInt<1>(0h0) connect _WIRE_2.iw_state, UInt<2>(0h1) node _T_16 = eq(io.dis_uops[2].bits.uopc, UInt<7>(0h2)) node _T_17 = eq(io.dis_uops[2].bits.lrs2_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.dis_uops[2].bits.uopc, UInt<7>(0h43)) node _T_20 = or(_T_18, _T_19) when _T_20 : connect _WIRE_2.iw_state, UInt<2>(0h2) else : node _T_21 = eq(io.dis_uops[2].bits.uopc, UInt<7>(0h2)) node _T_22 = neq(io.dis_uops[2].bits.lrs2_rtype, UInt<2>(0h0)) node _T_23 = and(_T_21, _T_22) when _T_23 : connect _WIRE_2.lrs2_rtype, UInt<2>(0h2) connect _WIRE_2.prs2_busy, UInt<1>(0h0) connect _WIRE_2.prs3_busy, UInt<1>(0h0) inst slots_0 of IssueSlot_112 connect slots_0.clock, clock connect slots_0.reset, reset inst slots_1 of IssueSlot_113 connect slots_1.clock, clock connect slots_1.reset, reset inst slots_2 of IssueSlot_114 connect slots_2.clock, clock connect slots_2.reset, reset inst slots_3 of IssueSlot_115 connect slots_3.clock, clock connect slots_3.reset, reset inst slots_4 of IssueSlot_116 connect slots_4.clock, clock connect slots_4.reset, reset inst slots_5 of IssueSlot_117 connect slots_5.clock, clock connect slots_5.reset, reset inst slots_6 of IssueSlot_118 connect slots_6.clock, clock connect slots_6.reset, reset inst slots_7 of IssueSlot_119 connect slots_7.clock, clock connect slots_7.reset, reset inst slots_8 of IssueSlot_120 connect slots_8.clock, clock connect slots_8.reset, reset inst slots_9 of IssueSlot_121 connect slots_9.clock, clock connect slots_9.reset, reset inst slots_10 of IssueSlot_122 connect slots_10.clock, clock connect slots_10.reset, reset inst slots_11 of IssueSlot_123 connect slots_11.clock, clock connect slots_11.reset, reset inst slots_12 of IssueSlot_124 connect slots_12.clock, clock connect slots_12.reset, reset inst slots_13 of IssueSlot_125 connect slots_13.clock, clock connect slots_13.reset, reset inst slots_14 of IssueSlot_126 connect slots_14.clock, clock connect slots_14.reset, reset inst slots_15 of IssueSlot_127 connect slots_15.clock, clock connect slots_15.reset, reset inst slots_16 of IssueSlot_128 connect slots_16.clock, clock connect slots_16.reset, reset inst slots_17 of IssueSlot_129 connect slots_17.clock, clock connect slots_17.reset, reset inst slots_18 of IssueSlot_130 connect slots_18.clock, clock connect slots_18.reset, reset inst slots_19 of IssueSlot_131 connect slots_19.clock, clock connect slots_19.reset, reset inst slots_20 of IssueSlot_132 connect slots_20.clock, clock connect slots_20.reset, reset inst slots_21 of IssueSlot_133 connect slots_21.clock, clock connect slots_21.reset, reset inst slots_22 of IssueSlot_134 connect slots_22.clock, clock connect slots_22.reset, reset inst slots_23 of IssueSlot_135 connect slots_23.clock, clock connect slots_23.reset, reset inst slots_24 of IssueSlot_136 connect slots_24.clock, clock connect slots_24.reset, reset inst slots_25 of IssueSlot_137 connect slots_25.clock, clock connect slots_25.reset, reset inst slots_26 of IssueSlot_138 connect slots_26.clock, clock connect slots_26.reset, reset inst slots_27 of IssueSlot_139 connect slots_27.clock, clock connect slots_27.reset, reset inst slots_28 of IssueSlot_140 connect slots_28.clock, clock connect slots_28.reset, reset inst slots_29 of IssueSlot_141 connect slots_29.clock, clock connect slots_29.reset, reset inst slots_30 of IssueSlot_142 connect slots_30.clock, clock connect slots_30.reset, reset inst slots_31 of IssueSlot_143 connect slots_31.clock, clock connect slots_31.reset, reset wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}[32] connect issue_slots[0].debug.state, slots_0.io.debug.state connect issue_slots[0].debug.ppred, slots_0.io.debug.ppred connect issue_slots[0].debug.p3, slots_0.io.debug.p3 connect issue_slots[0].debug.p2, slots_0.io.debug.p2 connect issue_slots[0].debug.p1, slots_0.io.debug.p1 connect issue_slots[0].uop.debug_tsrc, slots_0.io.uop.debug_tsrc connect issue_slots[0].uop.debug_fsrc, slots_0.io.uop.debug_fsrc connect issue_slots[0].uop.bp_xcpt_if, slots_0.io.uop.bp_xcpt_if connect issue_slots[0].uop.bp_debug_if, slots_0.io.uop.bp_debug_if connect issue_slots[0].uop.xcpt_ma_if, slots_0.io.uop.xcpt_ma_if connect issue_slots[0].uop.xcpt_ae_if, slots_0.io.uop.xcpt_ae_if connect issue_slots[0].uop.xcpt_pf_if, slots_0.io.uop.xcpt_pf_if connect issue_slots[0].uop.fp_single, slots_0.io.uop.fp_single connect issue_slots[0].uop.fp_val, slots_0.io.uop.fp_val connect issue_slots[0].uop.frs3_en, slots_0.io.uop.frs3_en connect issue_slots[0].uop.lrs2_rtype, slots_0.io.uop.lrs2_rtype connect issue_slots[0].uop.lrs1_rtype, slots_0.io.uop.lrs1_rtype connect issue_slots[0].uop.dst_rtype, slots_0.io.uop.dst_rtype connect issue_slots[0].uop.ldst_val, slots_0.io.uop.ldst_val connect issue_slots[0].uop.lrs3, slots_0.io.uop.lrs3 connect issue_slots[0].uop.lrs2, slots_0.io.uop.lrs2 connect issue_slots[0].uop.lrs1, slots_0.io.uop.lrs1 connect issue_slots[0].uop.ldst, slots_0.io.uop.ldst connect issue_slots[0].uop.ldst_is_rs1, slots_0.io.uop.ldst_is_rs1 connect issue_slots[0].uop.flush_on_commit, slots_0.io.uop.flush_on_commit connect issue_slots[0].uop.is_unique, slots_0.io.uop.is_unique connect issue_slots[0].uop.is_sys_pc2epc, slots_0.io.uop.is_sys_pc2epc connect issue_slots[0].uop.uses_stq, slots_0.io.uop.uses_stq connect issue_slots[0].uop.uses_ldq, slots_0.io.uop.uses_ldq connect issue_slots[0].uop.is_amo, slots_0.io.uop.is_amo connect issue_slots[0].uop.is_fencei, slots_0.io.uop.is_fencei connect issue_slots[0].uop.is_fence, slots_0.io.uop.is_fence connect issue_slots[0].uop.mem_signed, slots_0.io.uop.mem_signed connect issue_slots[0].uop.mem_size, slots_0.io.uop.mem_size connect issue_slots[0].uop.mem_cmd, slots_0.io.uop.mem_cmd connect issue_slots[0].uop.bypassable, slots_0.io.uop.bypassable connect issue_slots[0].uop.exc_cause, slots_0.io.uop.exc_cause connect issue_slots[0].uop.exception, slots_0.io.uop.exception connect issue_slots[0].uop.stale_pdst, slots_0.io.uop.stale_pdst connect issue_slots[0].uop.ppred_busy, slots_0.io.uop.ppred_busy connect issue_slots[0].uop.prs3_busy, slots_0.io.uop.prs3_busy connect issue_slots[0].uop.prs2_busy, slots_0.io.uop.prs2_busy connect issue_slots[0].uop.prs1_busy, slots_0.io.uop.prs1_busy connect issue_slots[0].uop.ppred, slots_0.io.uop.ppred connect issue_slots[0].uop.prs3, slots_0.io.uop.prs3 connect issue_slots[0].uop.prs2, slots_0.io.uop.prs2 connect issue_slots[0].uop.prs1, slots_0.io.uop.prs1 connect issue_slots[0].uop.pdst, slots_0.io.uop.pdst connect issue_slots[0].uop.rxq_idx, slots_0.io.uop.rxq_idx connect issue_slots[0].uop.stq_idx, slots_0.io.uop.stq_idx connect issue_slots[0].uop.ldq_idx, slots_0.io.uop.ldq_idx connect issue_slots[0].uop.rob_idx, slots_0.io.uop.rob_idx connect issue_slots[0].uop.csr_addr, slots_0.io.uop.csr_addr connect issue_slots[0].uop.imm_packed, slots_0.io.uop.imm_packed connect issue_slots[0].uop.taken, slots_0.io.uop.taken connect issue_slots[0].uop.pc_lob, slots_0.io.uop.pc_lob connect issue_slots[0].uop.edge_inst, slots_0.io.uop.edge_inst connect issue_slots[0].uop.ftq_idx, slots_0.io.uop.ftq_idx connect issue_slots[0].uop.br_tag, slots_0.io.uop.br_tag connect issue_slots[0].uop.br_mask, slots_0.io.uop.br_mask connect issue_slots[0].uop.is_sfb, slots_0.io.uop.is_sfb connect issue_slots[0].uop.is_jal, slots_0.io.uop.is_jal connect issue_slots[0].uop.is_jalr, slots_0.io.uop.is_jalr connect issue_slots[0].uop.is_br, slots_0.io.uop.is_br connect issue_slots[0].uop.iw_p2_poisoned, slots_0.io.uop.iw_p2_poisoned connect issue_slots[0].uop.iw_p1_poisoned, slots_0.io.uop.iw_p1_poisoned connect issue_slots[0].uop.iw_state, slots_0.io.uop.iw_state connect issue_slots[0].uop.ctrl.is_std, slots_0.io.uop.ctrl.is_std connect issue_slots[0].uop.ctrl.is_sta, slots_0.io.uop.ctrl.is_sta connect issue_slots[0].uop.ctrl.is_load, slots_0.io.uop.ctrl.is_load connect issue_slots[0].uop.ctrl.csr_cmd, slots_0.io.uop.ctrl.csr_cmd connect issue_slots[0].uop.ctrl.fcn_dw, slots_0.io.uop.ctrl.fcn_dw connect issue_slots[0].uop.ctrl.op_fcn, slots_0.io.uop.ctrl.op_fcn connect issue_slots[0].uop.ctrl.imm_sel, slots_0.io.uop.ctrl.imm_sel connect issue_slots[0].uop.ctrl.op2_sel, slots_0.io.uop.ctrl.op2_sel connect issue_slots[0].uop.ctrl.op1_sel, slots_0.io.uop.ctrl.op1_sel connect issue_slots[0].uop.ctrl.br_type, slots_0.io.uop.ctrl.br_type connect issue_slots[0].uop.fu_code, slots_0.io.uop.fu_code connect issue_slots[0].uop.iq_type, slots_0.io.uop.iq_type connect issue_slots[0].uop.debug_pc, slots_0.io.uop.debug_pc connect issue_slots[0].uop.is_rvc, slots_0.io.uop.is_rvc connect issue_slots[0].uop.debug_inst, slots_0.io.uop.debug_inst connect issue_slots[0].uop.inst, slots_0.io.uop.inst connect issue_slots[0].uop.uopc, slots_0.io.uop.uopc connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if connect issue_slots[0].out_uop.fp_single, slots_0.io.out_uop.fp_single connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype connect issue_slots[0].out_uop.ldst_val, slots_0.io.out_uop.ldst_val connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd connect issue_slots[0].out_uop.bypassable, slots_0.io.out_uop.bypassable connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx connect issue_slots[0].out_uop.csr_addr, slots_0.io.out_uop.csr_addr connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb connect issue_slots[0].out_uop.is_jal, slots_0.io.out_uop.is_jal connect issue_slots[0].out_uop.is_jalr, slots_0.io.out_uop.is_jalr connect issue_slots[0].out_uop.is_br, slots_0.io.out_uop.is_br connect issue_slots[0].out_uop.iw_p2_poisoned, slots_0.io.out_uop.iw_p2_poisoned connect issue_slots[0].out_uop.iw_p1_poisoned, slots_0.io.out_uop.iw_p1_poisoned connect issue_slots[0].out_uop.iw_state, slots_0.io.out_uop.iw_state connect issue_slots[0].out_uop.ctrl.is_std, slots_0.io.out_uop.ctrl.is_std connect issue_slots[0].out_uop.ctrl.is_sta, slots_0.io.out_uop.ctrl.is_sta connect issue_slots[0].out_uop.ctrl.is_load, slots_0.io.out_uop.ctrl.is_load connect issue_slots[0].out_uop.ctrl.csr_cmd, slots_0.io.out_uop.ctrl.csr_cmd connect issue_slots[0].out_uop.ctrl.fcn_dw, slots_0.io.out_uop.ctrl.fcn_dw connect issue_slots[0].out_uop.ctrl.op_fcn, slots_0.io.out_uop.ctrl.op_fcn connect issue_slots[0].out_uop.ctrl.imm_sel, slots_0.io.out_uop.ctrl.imm_sel connect issue_slots[0].out_uop.ctrl.op2_sel, slots_0.io.out_uop.ctrl.op2_sel connect issue_slots[0].out_uop.ctrl.op1_sel, slots_0.io.out_uop.ctrl.op1_sel connect issue_slots[0].out_uop.ctrl.br_type, slots_0.io.out_uop.ctrl.br_type connect issue_slots[0].out_uop.fu_code, slots_0.io.out_uop.fu_code connect issue_slots[0].out_uop.iq_type, slots_0.io.out_uop.iq_type connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst connect issue_slots[0].out_uop.uopc, slots_0.io.out_uop.uopc connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if connect slots_0.io.in_uop.bits.fp_single, issue_slots[0].in_uop.bits.fp_single connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype connect slots_0.io.in_uop.bits.ldst_val, issue_slots[0].in_uop.bits.ldst_val connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd connect slots_0.io.in_uop.bits.bypassable, issue_slots[0].in_uop.bits.bypassable connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx connect slots_0.io.in_uop.bits.csr_addr, issue_slots[0].in_uop.bits.csr_addr connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb connect slots_0.io.in_uop.bits.is_jal, issue_slots[0].in_uop.bits.is_jal connect slots_0.io.in_uop.bits.is_jalr, issue_slots[0].in_uop.bits.is_jalr connect slots_0.io.in_uop.bits.is_br, issue_slots[0].in_uop.bits.is_br connect slots_0.io.in_uop.bits.iw_p2_poisoned, issue_slots[0].in_uop.bits.iw_p2_poisoned connect slots_0.io.in_uop.bits.iw_p1_poisoned, issue_slots[0].in_uop.bits.iw_p1_poisoned connect slots_0.io.in_uop.bits.iw_state, issue_slots[0].in_uop.bits.iw_state connect slots_0.io.in_uop.bits.ctrl.is_std, issue_slots[0].in_uop.bits.ctrl.is_std connect slots_0.io.in_uop.bits.ctrl.is_sta, issue_slots[0].in_uop.bits.ctrl.is_sta connect slots_0.io.in_uop.bits.ctrl.is_load, issue_slots[0].in_uop.bits.ctrl.is_load connect slots_0.io.in_uop.bits.ctrl.csr_cmd, issue_slots[0].in_uop.bits.ctrl.csr_cmd connect slots_0.io.in_uop.bits.ctrl.fcn_dw, issue_slots[0].in_uop.bits.ctrl.fcn_dw connect slots_0.io.in_uop.bits.ctrl.op_fcn, issue_slots[0].in_uop.bits.ctrl.op_fcn connect slots_0.io.in_uop.bits.ctrl.imm_sel, issue_slots[0].in_uop.bits.ctrl.imm_sel connect slots_0.io.in_uop.bits.ctrl.op2_sel, issue_slots[0].in_uop.bits.ctrl.op2_sel connect slots_0.io.in_uop.bits.ctrl.op1_sel, issue_slots[0].in_uop.bits.ctrl.op1_sel connect slots_0.io.in_uop.bits.ctrl.br_type, issue_slots[0].in_uop.bits.ctrl.br_type connect slots_0.io.in_uop.bits.fu_code, issue_slots[0].in_uop.bits.fu_code connect slots_0.io.in_uop.bits.iq_type, issue_slots[0].in_uop.bits.iq_type connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst connect slots_0.io.in_uop.bits.uopc, issue_slots[0].in_uop.bits.uopc connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid connect slots_0.io.spec_ld_wakeup[0].bits, issue_slots[0].spec_ld_wakeup[0].bits connect slots_0.io.spec_ld_wakeup[0].valid, issue_slots[0].spec_ld_wakeup[0].valid connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid connect slots_0.io.wakeup_ports[0].bits.poisoned, issue_slots[0].wakeup_ports[0].bits.poisoned connect slots_0.io.wakeup_ports[0].bits.pdst, issue_slots[0].wakeup_ports[0].bits.pdst connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid connect slots_0.io.wakeup_ports[1].bits.poisoned, issue_slots[0].wakeup_ports[1].bits.poisoned connect slots_0.io.wakeup_ports[1].bits.pdst, issue_slots[0].wakeup_ports[1].bits.pdst connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid connect slots_0.io.wakeup_ports[2].bits.poisoned, issue_slots[0].wakeup_ports[2].bits.poisoned connect slots_0.io.wakeup_ports[2].bits.pdst, issue_slots[0].wakeup_ports[2].bits.pdst connect slots_0.io.wakeup_ports[2].valid, issue_slots[0].wakeup_ports[2].valid connect slots_0.io.wakeup_ports[3].bits.poisoned, issue_slots[0].wakeup_ports[3].bits.poisoned connect slots_0.io.wakeup_ports[3].bits.pdst, issue_slots[0].wakeup_ports[3].bits.pdst connect slots_0.io.wakeup_ports[3].valid, issue_slots[0].wakeup_ports[3].valid connect slots_0.io.wakeup_ports[4].bits.poisoned, issue_slots[0].wakeup_ports[4].bits.poisoned connect slots_0.io.wakeup_ports[4].bits.pdst, issue_slots[0].wakeup_ports[4].bits.pdst connect slots_0.io.wakeup_ports[4].valid, issue_slots[0].wakeup_ports[4].valid connect slots_0.io.wakeup_ports[5].bits.poisoned, issue_slots[0].wakeup_ports[5].bits.poisoned connect slots_0.io.wakeup_ports[5].bits.pdst, issue_slots[0].wakeup_ports[5].bits.pdst connect slots_0.io.wakeup_ports[5].valid, issue_slots[0].wakeup_ports[5].valid connect slots_0.io.wakeup_ports[6].bits.poisoned, issue_slots[0].wakeup_ports[6].bits.poisoned connect slots_0.io.wakeup_ports[6].bits.pdst, issue_slots[0].wakeup_ports[6].bits.pdst connect slots_0.io.wakeup_ports[6].valid, issue_slots[0].wakeup_ports[6].valid connect slots_0.io.ldspec_miss, issue_slots[0].ldspec_miss connect slots_0.io.clear, issue_slots[0].clear connect slots_0.io.kill, issue_slots[0].kill connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict connect slots_0.io.brupdate.b2.valid, issue_slots[0].brupdate.b2.valid connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if connect slots_0.io.brupdate.b2.uop.fp_single, issue_slots[0].brupdate.b2.uop.fp_single connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype connect slots_0.io.brupdate.b2.uop.ldst_val, issue_slots[0].brupdate.b2.uop.ldst_val connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd connect slots_0.io.brupdate.b2.uop.bypassable, issue_slots[0].brupdate.b2.uop.bypassable connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx connect slots_0.io.brupdate.b2.uop.csr_addr, issue_slots[0].brupdate.b2.uop.csr_addr connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb connect slots_0.io.brupdate.b2.uop.is_jal, issue_slots[0].brupdate.b2.uop.is_jal connect slots_0.io.brupdate.b2.uop.is_jalr, issue_slots[0].brupdate.b2.uop.is_jalr connect slots_0.io.brupdate.b2.uop.is_br, issue_slots[0].brupdate.b2.uop.is_br connect slots_0.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[0].brupdate.b2.uop.iw_p2_poisoned connect slots_0.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[0].brupdate.b2.uop.iw_p1_poisoned connect slots_0.io.brupdate.b2.uop.iw_state, issue_slots[0].brupdate.b2.uop.iw_state connect slots_0.io.brupdate.b2.uop.ctrl.is_std, issue_slots[0].brupdate.b2.uop.ctrl.is_std connect slots_0.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[0].brupdate.b2.uop.ctrl.is_sta connect slots_0.io.brupdate.b2.uop.ctrl.is_load, issue_slots[0].brupdate.b2.uop.ctrl.is_load connect slots_0.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd connect slots_0.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw connect slots_0.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[0].brupdate.b2.uop.ctrl.op_fcn connect slots_0.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[0].brupdate.b2.uop.ctrl.imm_sel connect slots_0.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[0].brupdate.b2.uop.ctrl.op2_sel connect slots_0.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[0].brupdate.b2.uop.ctrl.op1_sel connect slots_0.io.brupdate.b2.uop.ctrl.br_type, issue_slots[0].brupdate.b2.uop.ctrl.br_type connect slots_0.io.brupdate.b2.uop.fu_code, issue_slots[0].brupdate.b2.uop.fu_code connect slots_0.io.brupdate.b2.uop.iq_type, issue_slots[0].brupdate.b2.uop.iq_type connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst connect slots_0.io.brupdate.b2.uop.uopc, issue_slots[0].brupdate.b2.uop.uopc connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask connect slots_0.io.grant, issue_slots[0].grant connect issue_slots[0].request_hp, slots_0.io.request_hp connect issue_slots[0].request, slots_0.io.request connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid connect issue_slots[0].valid, slots_0.io.valid connect issue_slots[1].debug.state, slots_1.io.debug.state connect issue_slots[1].debug.ppred, slots_1.io.debug.ppred connect issue_slots[1].debug.p3, slots_1.io.debug.p3 connect issue_slots[1].debug.p2, slots_1.io.debug.p2 connect issue_slots[1].debug.p1, slots_1.io.debug.p1 connect issue_slots[1].uop.debug_tsrc, slots_1.io.uop.debug_tsrc connect issue_slots[1].uop.debug_fsrc, slots_1.io.uop.debug_fsrc connect issue_slots[1].uop.bp_xcpt_if, slots_1.io.uop.bp_xcpt_if connect issue_slots[1].uop.bp_debug_if, slots_1.io.uop.bp_debug_if connect issue_slots[1].uop.xcpt_ma_if, slots_1.io.uop.xcpt_ma_if connect issue_slots[1].uop.xcpt_ae_if, slots_1.io.uop.xcpt_ae_if connect issue_slots[1].uop.xcpt_pf_if, slots_1.io.uop.xcpt_pf_if connect issue_slots[1].uop.fp_single, slots_1.io.uop.fp_single connect issue_slots[1].uop.fp_val, slots_1.io.uop.fp_val connect issue_slots[1].uop.frs3_en, slots_1.io.uop.frs3_en connect issue_slots[1].uop.lrs2_rtype, slots_1.io.uop.lrs2_rtype connect issue_slots[1].uop.lrs1_rtype, slots_1.io.uop.lrs1_rtype connect issue_slots[1].uop.dst_rtype, slots_1.io.uop.dst_rtype connect issue_slots[1].uop.ldst_val, slots_1.io.uop.ldst_val connect issue_slots[1].uop.lrs3, slots_1.io.uop.lrs3 connect issue_slots[1].uop.lrs2, slots_1.io.uop.lrs2 connect issue_slots[1].uop.lrs1, slots_1.io.uop.lrs1 connect issue_slots[1].uop.ldst, slots_1.io.uop.ldst connect issue_slots[1].uop.ldst_is_rs1, slots_1.io.uop.ldst_is_rs1 connect issue_slots[1].uop.flush_on_commit, slots_1.io.uop.flush_on_commit connect issue_slots[1].uop.is_unique, slots_1.io.uop.is_unique connect issue_slots[1].uop.is_sys_pc2epc, slots_1.io.uop.is_sys_pc2epc connect issue_slots[1].uop.uses_stq, slots_1.io.uop.uses_stq connect issue_slots[1].uop.uses_ldq, slots_1.io.uop.uses_ldq connect issue_slots[1].uop.is_amo, slots_1.io.uop.is_amo connect issue_slots[1].uop.is_fencei, slots_1.io.uop.is_fencei connect issue_slots[1].uop.is_fence, slots_1.io.uop.is_fence connect issue_slots[1].uop.mem_signed, slots_1.io.uop.mem_signed connect issue_slots[1].uop.mem_size, slots_1.io.uop.mem_size connect issue_slots[1].uop.mem_cmd, slots_1.io.uop.mem_cmd connect issue_slots[1].uop.bypassable, slots_1.io.uop.bypassable connect issue_slots[1].uop.exc_cause, slots_1.io.uop.exc_cause connect issue_slots[1].uop.exception, slots_1.io.uop.exception connect issue_slots[1].uop.stale_pdst, slots_1.io.uop.stale_pdst connect issue_slots[1].uop.ppred_busy, slots_1.io.uop.ppred_busy connect issue_slots[1].uop.prs3_busy, slots_1.io.uop.prs3_busy connect issue_slots[1].uop.prs2_busy, slots_1.io.uop.prs2_busy connect issue_slots[1].uop.prs1_busy, slots_1.io.uop.prs1_busy connect issue_slots[1].uop.ppred, slots_1.io.uop.ppred connect issue_slots[1].uop.prs3, slots_1.io.uop.prs3 connect issue_slots[1].uop.prs2, slots_1.io.uop.prs2 connect issue_slots[1].uop.prs1, slots_1.io.uop.prs1 connect issue_slots[1].uop.pdst, slots_1.io.uop.pdst connect issue_slots[1].uop.rxq_idx, slots_1.io.uop.rxq_idx connect issue_slots[1].uop.stq_idx, slots_1.io.uop.stq_idx connect issue_slots[1].uop.ldq_idx, slots_1.io.uop.ldq_idx connect issue_slots[1].uop.rob_idx, slots_1.io.uop.rob_idx connect issue_slots[1].uop.csr_addr, slots_1.io.uop.csr_addr connect issue_slots[1].uop.imm_packed, slots_1.io.uop.imm_packed connect issue_slots[1].uop.taken, slots_1.io.uop.taken connect issue_slots[1].uop.pc_lob, slots_1.io.uop.pc_lob connect issue_slots[1].uop.edge_inst, slots_1.io.uop.edge_inst connect issue_slots[1].uop.ftq_idx, slots_1.io.uop.ftq_idx connect issue_slots[1].uop.br_tag, slots_1.io.uop.br_tag connect issue_slots[1].uop.br_mask, slots_1.io.uop.br_mask connect issue_slots[1].uop.is_sfb, slots_1.io.uop.is_sfb connect issue_slots[1].uop.is_jal, slots_1.io.uop.is_jal connect issue_slots[1].uop.is_jalr, slots_1.io.uop.is_jalr connect issue_slots[1].uop.is_br, slots_1.io.uop.is_br connect issue_slots[1].uop.iw_p2_poisoned, slots_1.io.uop.iw_p2_poisoned connect issue_slots[1].uop.iw_p1_poisoned, slots_1.io.uop.iw_p1_poisoned connect issue_slots[1].uop.iw_state, slots_1.io.uop.iw_state connect issue_slots[1].uop.ctrl.is_std, slots_1.io.uop.ctrl.is_std connect issue_slots[1].uop.ctrl.is_sta, slots_1.io.uop.ctrl.is_sta connect issue_slots[1].uop.ctrl.is_load, slots_1.io.uop.ctrl.is_load connect issue_slots[1].uop.ctrl.csr_cmd, slots_1.io.uop.ctrl.csr_cmd connect issue_slots[1].uop.ctrl.fcn_dw, slots_1.io.uop.ctrl.fcn_dw connect issue_slots[1].uop.ctrl.op_fcn, slots_1.io.uop.ctrl.op_fcn connect issue_slots[1].uop.ctrl.imm_sel, slots_1.io.uop.ctrl.imm_sel connect issue_slots[1].uop.ctrl.op2_sel, slots_1.io.uop.ctrl.op2_sel connect issue_slots[1].uop.ctrl.op1_sel, slots_1.io.uop.ctrl.op1_sel connect issue_slots[1].uop.ctrl.br_type, slots_1.io.uop.ctrl.br_type connect issue_slots[1].uop.fu_code, slots_1.io.uop.fu_code connect issue_slots[1].uop.iq_type, slots_1.io.uop.iq_type connect issue_slots[1].uop.debug_pc, slots_1.io.uop.debug_pc connect issue_slots[1].uop.is_rvc, slots_1.io.uop.is_rvc connect issue_slots[1].uop.debug_inst, slots_1.io.uop.debug_inst connect issue_slots[1].uop.inst, slots_1.io.uop.inst connect issue_slots[1].uop.uopc, slots_1.io.uop.uopc connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if connect issue_slots[1].out_uop.fp_single, slots_1.io.out_uop.fp_single connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype connect issue_slots[1].out_uop.ldst_val, slots_1.io.out_uop.ldst_val connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd connect issue_slots[1].out_uop.bypassable, slots_1.io.out_uop.bypassable connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx connect issue_slots[1].out_uop.csr_addr, slots_1.io.out_uop.csr_addr connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb connect issue_slots[1].out_uop.is_jal, slots_1.io.out_uop.is_jal connect issue_slots[1].out_uop.is_jalr, slots_1.io.out_uop.is_jalr connect issue_slots[1].out_uop.is_br, slots_1.io.out_uop.is_br connect issue_slots[1].out_uop.iw_p2_poisoned, slots_1.io.out_uop.iw_p2_poisoned connect issue_slots[1].out_uop.iw_p1_poisoned, slots_1.io.out_uop.iw_p1_poisoned connect issue_slots[1].out_uop.iw_state, slots_1.io.out_uop.iw_state connect issue_slots[1].out_uop.ctrl.is_std, slots_1.io.out_uop.ctrl.is_std connect issue_slots[1].out_uop.ctrl.is_sta, slots_1.io.out_uop.ctrl.is_sta connect issue_slots[1].out_uop.ctrl.is_load, slots_1.io.out_uop.ctrl.is_load connect issue_slots[1].out_uop.ctrl.csr_cmd, slots_1.io.out_uop.ctrl.csr_cmd connect issue_slots[1].out_uop.ctrl.fcn_dw, slots_1.io.out_uop.ctrl.fcn_dw connect issue_slots[1].out_uop.ctrl.op_fcn, slots_1.io.out_uop.ctrl.op_fcn connect issue_slots[1].out_uop.ctrl.imm_sel, slots_1.io.out_uop.ctrl.imm_sel connect issue_slots[1].out_uop.ctrl.op2_sel, slots_1.io.out_uop.ctrl.op2_sel connect issue_slots[1].out_uop.ctrl.op1_sel, slots_1.io.out_uop.ctrl.op1_sel connect issue_slots[1].out_uop.ctrl.br_type, slots_1.io.out_uop.ctrl.br_type connect issue_slots[1].out_uop.fu_code, slots_1.io.out_uop.fu_code connect issue_slots[1].out_uop.iq_type, slots_1.io.out_uop.iq_type connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst connect issue_slots[1].out_uop.uopc, slots_1.io.out_uop.uopc connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if connect slots_1.io.in_uop.bits.fp_single, issue_slots[1].in_uop.bits.fp_single connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype connect slots_1.io.in_uop.bits.ldst_val, issue_slots[1].in_uop.bits.ldst_val connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd connect slots_1.io.in_uop.bits.bypassable, issue_slots[1].in_uop.bits.bypassable connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx connect slots_1.io.in_uop.bits.csr_addr, issue_slots[1].in_uop.bits.csr_addr connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb connect slots_1.io.in_uop.bits.is_jal, issue_slots[1].in_uop.bits.is_jal connect slots_1.io.in_uop.bits.is_jalr, issue_slots[1].in_uop.bits.is_jalr connect slots_1.io.in_uop.bits.is_br, issue_slots[1].in_uop.bits.is_br connect slots_1.io.in_uop.bits.iw_p2_poisoned, issue_slots[1].in_uop.bits.iw_p2_poisoned connect slots_1.io.in_uop.bits.iw_p1_poisoned, issue_slots[1].in_uop.bits.iw_p1_poisoned connect slots_1.io.in_uop.bits.iw_state, issue_slots[1].in_uop.bits.iw_state connect slots_1.io.in_uop.bits.ctrl.is_std, issue_slots[1].in_uop.bits.ctrl.is_std connect slots_1.io.in_uop.bits.ctrl.is_sta, issue_slots[1].in_uop.bits.ctrl.is_sta connect slots_1.io.in_uop.bits.ctrl.is_load, issue_slots[1].in_uop.bits.ctrl.is_load connect slots_1.io.in_uop.bits.ctrl.csr_cmd, issue_slots[1].in_uop.bits.ctrl.csr_cmd connect slots_1.io.in_uop.bits.ctrl.fcn_dw, issue_slots[1].in_uop.bits.ctrl.fcn_dw connect slots_1.io.in_uop.bits.ctrl.op_fcn, issue_slots[1].in_uop.bits.ctrl.op_fcn connect slots_1.io.in_uop.bits.ctrl.imm_sel, issue_slots[1].in_uop.bits.ctrl.imm_sel connect slots_1.io.in_uop.bits.ctrl.op2_sel, issue_slots[1].in_uop.bits.ctrl.op2_sel connect slots_1.io.in_uop.bits.ctrl.op1_sel, issue_slots[1].in_uop.bits.ctrl.op1_sel connect slots_1.io.in_uop.bits.ctrl.br_type, issue_slots[1].in_uop.bits.ctrl.br_type connect slots_1.io.in_uop.bits.fu_code, issue_slots[1].in_uop.bits.fu_code connect slots_1.io.in_uop.bits.iq_type, issue_slots[1].in_uop.bits.iq_type connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst connect slots_1.io.in_uop.bits.uopc, issue_slots[1].in_uop.bits.uopc connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid connect slots_1.io.spec_ld_wakeup[0].bits, issue_slots[1].spec_ld_wakeup[0].bits connect slots_1.io.spec_ld_wakeup[0].valid, issue_slots[1].spec_ld_wakeup[0].valid connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid connect slots_1.io.wakeup_ports[0].bits.poisoned, issue_slots[1].wakeup_ports[0].bits.poisoned connect slots_1.io.wakeup_ports[0].bits.pdst, issue_slots[1].wakeup_ports[0].bits.pdst connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid connect slots_1.io.wakeup_ports[1].bits.poisoned, issue_slots[1].wakeup_ports[1].bits.poisoned connect slots_1.io.wakeup_ports[1].bits.pdst, issue_slots[1].wakeup_ports[1].bits.pdst connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid connect slots_1.io.wakeup_ports[2].bits.poisoned, issue_slots[1].wakeup_ports[2].bits.poisoned connect slots_1.io.wakeup_ports[2].bits.pdst, issue_slots[1].wakeup_ports[2].bits.pdst connect slots_1.io.wakeup_ports[2].valid, issue_slots[1].wakeup_ports[2].valid connect slots_1.io.wakeup_ports[3].bits.poisoned, issue_slots[1].wakeup_ports[3].bits.poisoned connect slots_1.io.wakeup_ports[3].bits.pdst, issue_slots[1].wakeup_ports[3].bits.pdst connect slots_1.io.wakeup_ports[3].valid, issue_slots[1].wakeup_ports[3].valid connect slots_1.io.wakeup_ports[4].bits.poisoned, issue_slots[1].wakeup_ports[4].bits.poisoned connect slots_1.io.wakeup_ports[4].bits.pdst, issue_slots[1].wakeup_ports[4].bits.pdst connect slots_1.io.wakeup_ports[4].valid, issue_slots[1].wakeup_ports[4].valid connect slots_1.io.wakeup_ports[5].bits.poisoned, issue_slots[1].wakeup_ports[5].bits.poisoned connect slots_1.io.wakeup_ports[5].bits.pdst, issue_slots[1].wakeup_ports[5].bits.pdst connect slots_1.io.wakeup_ports[5].valid, issue_slots[1].wakeup_ports[5].valid connect slots_1.io.wakeup_ports[6].bits.poisoned, issue_slots[1].wakeup_ports[6].bits.poisoned connect slots_1.io.wakeup_ports[6].bits.pdst, issue_slots[1].wakeup_ports[6].bits.pdst connect slots_1.io.wakeup_ports[6].valid, issue_slots[1].wakeup_ports[6].valid connect slots_1.io.ldspec_miss, issue_slots[1].ldspec_miss connect slots_1.io.clear, issue_slots[1].clear connect slots_1.io.kill, issue_slots[1].kill connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict connect slots_1.io.brupdate.b2.valid, issue_slots[1].brupdate.b2.valid connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if connect slots_1.io.brupdate.b2.uop.fp_single, issue_slots[1].brupdate.b2.uop.fp_single connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype connect slots_1.io.brupdate.b2.uop.ldst_val, issue_slots[1].brupdate.b2.uop.ldst_val connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd connect slots_1.io.brupdate.b2.uop.bypassable, issue_slots[1].brupdate.b2.uop.bypassable connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx connect slots_1.io.brupdate.b2.uop.csr_addr, issue_slots[1].brupdate.b2.uop.csr_addr connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb connect slots_1.io.brupdate.b2.uop.is_jal, issue_slots[1].brupdate.b2.uop.is_jal connect slots_1.io.brupdate.b2.uop.is_jalr, issue_slots[1].brupdate.b2.uop.is_jalr connect slots_1.io.brupdate.b2.uop.is_br, issue_slots[1].brupdate.b2.uop.is_br connect slots_1.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[1].brupdate.b2.uop.iw_p2_poisoned connect slots_1.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[1].brupdate.b2.uop.iw_p1_poisoned connect slots_1.io.brupdate.b2.uop.iw_state, issue_slots[1].brupdate.b2.uop.iw_state connect slots_1.io.brupdate.b2.uop.ctrl.is_std, issue_slots[1].brupdate.b2.uop.ctrl.is_std connect slots_1.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[1].brupdate.b2.uop.ctrl.is_sta connect slots_1.io.brupdate.b2.uop.ctrl.is_load, issue_slots[1].brupdate.b2.uop.ctrl.is_load connect slots_1.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd connect slots_1.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw connect slots_1.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[1].brupdate.b2.uop.ctrl.op_fcn connect slots_1.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[1].brupdate.b2.uop.ctrl.imm_sel connect slots_1.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[1].brupdate.b2.uop.ctrl.op2_sel connect slots_1.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[1].brupdate.b2.uop.ctrl.op1_sel connect slots_1.io.brupdate.b2.uop.ctrl.br_type, issue_slots[1].brupdate.b2.uop.ctrl.br_type connect slots_1.io.brupdate.b2.uop.fu_code, issue_slots[1].brupdate.b2.uop.fu_code connect slots_1.io.brupdate.b2.uop.iq_type, issue_slots[1].brupdate.b2.uop.iq_type connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst connect slots_1.io.brupdate.b2.uop.uopc, issue_slots[1].brupdate.b2.uop.uopc connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask connect slots_1.io.grant, issue_slots[1].grant connect issue_slots[1].request_hp, slots_1.io.request_hp connect issue_slots[1].request, slots_1.io.request connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid connect issue_slots[1].valid, slots_1.io.valid connect issue_slots[2].debug.state, slots_2.io.debug.state connect issue_slots[2].debug.ppred, slots_2.io.debug.ppred connect issue_slots[2].debug.p3, slots_2.io.debug.p3 connect issue_slots[2].debug.p2, slots_2.io.debug.p2 connect issue_slots[2].debug.p1, slots_2.io.debug.p1 connect issue_slots[2].uop.debug_tsrc, slots_2.io.uop.debug_tsrc connect issue_slots[2].uop.debug_fsrc, slots_2.io.uop.debug_fsrc connect issue_slots[2].uop.bp_xcpt_if, slots_2.io.uop.bp_xcpt_if connect issue_slots[2].uop.bp_debug_if, slots_2.io.uop.bp_debug_if connect issue_slots[2].uop.xcpt_ma_if, slots_2.io.uop.xcpt_ma_if connect issue_slots[2].uop.xcpt_ae_if, slots_2.io.uop.xcpt_ae_if connect issue_slots[2].uop.xcpt_pf_if, slots_2.io.uop.xcpt_pf_if connect issue_slots[2].uop.fp_single, slots_2.io.uop.fp_single connect issue_slots[2].uop.fp_val, slots_2.io.uop.fp_val connect issue_slots[2].uop.frs3_en, slots_2.io.uop.frs3_en connect issue_slots[2].uop.lrs2_rtype, slots_2.io.uop.lrs2_rtype connect issue_slots[2].uop.lrs1_rtype, slots_2.io.uop.lrs1_rtype connect issue_slots[2].uop.dst_rtype, slots_2.io.uop.dst_rtype connect issue_slots[2].uop.ldst_val, slots_2.io.uop.ldst_val connect issue_slots[2].uop.lrs3, slots_2.io.uop.lrs3 connect issue_slots[2].uop.lrs2, slots_2.io.uop.lrs2 connect issue_slots[2].uop.lrs1, slots_2.io.uop.lrs1 connect issue_slots[2].uop.ldst, slots_2.io.uop.ldst connect issue_slots[2].uop.ldst_is_rs1, slots_2.io.uop.ldst_is_rs1 connect issue_slots[2].uop.flush_on_commit, slots_2.io.uop.flush_on_commit connect issue_slots[2].uop.is_unique, slots_2.io.uop.is_unique connect issue_slots[2].uop.is_sys_pc2epc, slots_2.io.uop.is_sys_pc2epc connect issue_slots[2].uop.uses_stq, slots_2.io.uop.uses_stq connect issue_slots[2].uop.uses_ldq, slots_2.io.uop.uses_ldq connect issue_slots[2].uop.is_amo, slots_2.io.uop.is_amo connect issue_slots[2].uop.is_fencei, slots_2.io.uop.is_fencei connect issue_slots[2].uop.is_fence, slots_2.io.uop.is_fence connect issue_slots[2].uop.mem_signed, slots_2.io.uop.mem_signed connect issue_slots[2].uop.mem_size, slots_2.io.uop.mem_size connect issue_slots[2].uop.mem_cmd, slots_2.io.uop.mem_cmd connect issue_slots[2].uop.bypassable, slots_2.io.uop.bypassable connect issue_slots[2].uop.exc_cause, slots_2.io.uop.exc_cause connect issue_slots[2].uop.exception, slots_2.io.uop.exception connect issue_slots[2].uop.stale_pdst, slots_2.io.uop.stale_pdst connect issue_slots[2].uop.ppred_busy, slots_2.io.uop.ppred_busy connect issue_slots[2].uop.prs3_busy, slots_2.io.uop.prs3_busy connect issue_slots[2].uop.prs2_busy, slots_2.io.uop.prs2_busy connect issue_slots[2].uop.prs1_busy, slots_2.io.uop.prs1_busy connect issue_slots[2].uop.ppred, slots_2.io.uop.ppred connect issue_slots[2].uop.prs3, slots_2.io.uop.prs3 connect issue_slots[2].uop.prs2, slots_2.io.uop.prs2 connect issue_slots[2].uop.prs1, slots_2.io.uop.prs1 connect issue_slots[2].uop.pdst, slots_2.io.uop.pdst connect issue_slots[2].uop.rxq_idx, slots_2.io.uop.rxq_idx connect issue_slots[2].uop.stq_idx, slots_2.io.uop.stq_idx connect issue_slots[2].uop.ldq_idx, slots_2.io.uop.ldq_idx connect issue_slots[2].uop.rob_idx, slots_2.io.uop.rob_idx connect issue_slots[2].uop.csr_addr, slots_2.io.uop.csr_addr connect issue_slots[2].uop.imm_packed, slots_2.io.uop.imm_packed connect issue_slots[2].uop.taken, slots_2.io.uop.taken connect issue_slots[2].uop.pc_lob, slots_2.io.uop.pc_lob connect issue_slots[2].uop.edge_inst, slots_2.io.uop.edge_inst connect issue_slots[2].uop.ftq_idx, slots_2.io.uop.ftq_idx connect issue_slots[2].uop.br_tag, slots_2.io.uop.br_tag connect issue_slots[2].uop.br_mask, slots_2.io.uop.br_mask connect issue_slots[2].uop.is_sfb, slots_2.io.uop.is_sfb connect issue_slots[2].uop.is_jal, slots_2.io.uop.is_jal connect issue_slots[2].uop.is_jalr, slots_2.io.uop.is_jalr connect issue_slots[2].uop.is_br, slots_2.io.uop.is_br connect issue_slots[2].uop.iw_p2_poisoned, slots_2.io.uop.iw_p2_poisoned connect issue_slots[2].uop.iw_p1_poisoned, slots_2.io.uop.iw_p1_poisoned connect issue_slots[2].uop.iw_state, slots_2.io.uop.iw_state connect issue_slots[2].uop.ctrl.is_std, slots_2.io.uop.ctrl.is_std connect issue_slots[2].uop.ctrl.is_sta, slots_2.io.uop.ctrl.is_sta connect issue_slots[2].uop.ctrl.is_load, slots_2.io.uop.ctrl.is_load connect issue_slots[2].uop.ctrl.csr_cmd, slots_2.io.uop.ctrl.csr_cmd connect issue_slots[2].uop.ctrl.fcn_dw, slots_2.io.uop.ctrl.fcn_dw connect issue_slots[2].uop.ctrl.op_fcn, slots_2.io.uop.ctrl.op_fcn connect issue_slots[2].uop.ctrl.imm_sel, slots_2.io.uop.ctrl.imm_sel connect issue_slots[2].uop.ctrl.op2_sel, slots_2.io.uop.ctrl.op2_sel connect issue_slots[2].uop.ctrl.op1_sel, slots_2.io.uop.ctrl.op1_sel connect issue_slots[2].uop.ctrl.br_type, slots_2.io.uop.ctrl.br_type connect issue_slots[2].uop.fu_code, slots_2.io.uop.fu_code connect issue_slots[2].uop.iq_type, slots_2.io.uop.iq_type connect issue_slots[2].uop.debug_pc, slots_2.io.uop.debug_pc connect issue_slots[2].uop.is_rvc, slots_2.io.uop.is_rvc connect issue_slots[2].uop.debug_inst, slots_2.io.uop.debug_inst connect issue_slots[2].uop.inst, slots_2.io.uop.inst connect issue_slots[2].uop.uopc, slots_2.io.uop.uopc connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if connect issue_slots[2].out_uop.fp_single, slots_2.io.out_uop.fp_single connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype connect issue_slots[2].out_uop.ldst_val, slots_2.io.out_uop.ldst_val connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd connect issue_slots[2].out_uop.bypassable, slots_2.io.out_uop.bypassable connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx connect issue_slots[2].out_uop.csr_addr, slots_2.io.out_uop.csr_addr connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb connect issue_slots[2].out_uop.is_jal, slots_2.io.out_uop.is_jal connect issue_slots[2].out_uop.is_jalr, slots_2.io.out_uop.is_jalr connect issue_slots[2].out_uop.is_br, slots_2.io.out_uop.is_br connect issue_slots[2].out_uop.iw_p2_poisoned, slots_2.io.out_uop.iw_p2_poisoned connect issue_slots[2].out_uop.iw_p1_poisoned, slots_2.io.out_uop.iw_p1_poisoned connect issue_slots[2].out_uop.iw_state, slots_2.io.out_uop.iw_state connect issue_slots[2].out_uop.ctrl.is_std, slots_2.io.out_uop.ctrl.is_std connect issue_slots[2].out_uop.ctrl.is_sta, slots_2.io.out_uop.ctrl.is_sta connect issue_slots[2].out_uop.ctrl.is_load, slots_2.io.out_uop.ctrl.is_load connect issue_slots[2].out_uop.ctrl.csr_cmd, slots_2.io.out_uop.ctrl.csr_cmd connect issue_slots[2].out_uop.ctrl.fcn_dw, slots_2.io.out_uop.ctrl.fcn_dw connect issue_slots[2].out_uop.ctrl.op_fcn, slots_2.io.out_uop.ctrl.op_fcn connect issue_slots[2].out_uop.ctrl.imm_sel, slots_2.io.out_uop.ctrl.imm_sel connect issue_slots[2].out_uop.ctrl.op2_sel, slots_2.io.out_uop.ctrl.op2_sel connect issue_slots[2].out_uop.ctrl.op1_sel, slots_2.io.out_uop.ctrl.op1_sel connect issue_slots[2].out_uop.ctrl.br_type, slots_2.io.out_uop.ctrl.br_type connect issue_slots[2].out_uop.fu_code, slots_2.io.out_uop.fu_code connect issue_slots[2].out_uop.iq_type, slots_2.io.out_uop.iq_type connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst connect issue_slots[2].out_uop.uopc, slots_2.io.out_uop.uopc connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if connect slots_2.io.in_uop.bits.fp_single, issue_slots[2].in_uop.bits.fp_single connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype connect slots_2.io.in_uop.bits.ldst_val, issue_slots[2].in_uop.bits.ldst_val connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd connect slots_2.io.in_uop.bits.bypassable, issue_slots[2].in_uop.bits.bypassable connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx connect slots_2.io.in_uop.bits.csr_addr, issue_slots[2].in_uop.bits.csr_addr connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb connect slots_2.io.in_uop.bits.is_jal, issue_slots[2].in_uop.bits.is_jal connect slots_2.io.in_uop.bits.is_jalr, issue_slots[2].in_uop.bits.is_jalr connect slots_2.io.in_uop.bits.is_br, issue_slots[2].in_uop.bits.is_br connect slots_2.io.in_uop.bits.iw_p2_poisoned, issue_slots[2].in_uop.bits.iw_p2_poisoned connect slots_2.io.in_uop.bits.iw_p1_poisoned, issue_slots[2].in_uop.bits.iw_p1_poisoned connect slots_2.io.in_uop.bits.iw_state, issue_slots[2].in_uop.bits.iw_state connect slots_2.io.in_uop.bits.ctrl.is_std, issue_slots[2].in_uop.bits.ctrl.is_std connect slots_2.io.in_uop.bits.ctrl.is_sta, issue_slots[2].in_uop.bits.ctrl.is_sta connect slots_2.io.in_uop.bits.ctrl.is_load, issue_slots[2].in_uop.bits.ctrl.is_load connect slots_2.io.in_uop.bits.ctrl.csr_cmd, issue_slots[2].in_uop.bits.ctrl.csr_cmd connect slots_2.io.in_uop.bits.ctrl.fcn_dw, issue_slots[2].in_uop.bits.ctrl.fcn_dw connect slots_2.io.in_uop.bits.ctrl.op_fcn, issue_slots[2].in_uop.bits.ctrl.op_fcn connect slots_2.io.in_uop.bits.ctrl.imm_sel, issue_slots[2].in_uop.bits.ctrl.imm_sel connect slots_2.io.in_uop.bits.ctrl.op2_sel, issue_slots[2].in_uop.bits.ctrl.op2_sel connect slots_2.io.in_uop.bits.ctrl.op1_sel, issue_slots[2].in_uop.bits.ctrl.op1_sel connect slots_2.io.in_uop.bits.ctrl.br_type, issue_slots[2].in_uop.bits.ctrl.br_type connect slots_2.io.in_uop.bits.fu_code, issue_slots[2].in_uop.bits.fu_code connect slots_2.io.in_uop.bits.iq_type, issue_slots[2].in_uop.bits.iq_type connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst connect slots_2.io.in_uop.bits.uopc, issue_slots[2].in_uop.bits.uopc connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid connect slots_2.io.spec_ld_wakeup[0].bits, issue_slots[2].spec_ld_wakeup[0].bits connect slots_2.io.spec_ld_wakeup[0].valid, issue_slots[2].spec_ld_wakeup[0].valid connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid connect slots_2.io.wakeup_ports[0].bits.poisoned, issue_slots[2].wakeup_ports[0].bits.poisoned connect slots_2.io.wakeup_ports[0].bits.pdst, issue_slots[2].wakeup_ports[0].bits.pdst connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid connect slots_2.io.wakeup_ports[1].bits.poisoned, issue_slots[2].wakeup_ports[1].bits.poisoned connect slots_2.io.wakeup_ports[1].bits.pdst, issue_slots[2].wakeup_ports[1].bits.pdst connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid connect slots_2.io.wakeup_ports[2].bits.poisoned, issue_slots[2].wakeup_ports[2].bits.poisoned connect slots_2.io.wakeup_ports[2].bits.pdst, issue_slots[2].wakeup_ports[2].bits.pdst connect slots_2.io.wakeup_ports[2].valid, issue_slots[2].wakeup_ports[2].valid connect slots_2.io.wakeup_ports[3].bits.poisoned, issue_slots[2].wakeup_ports[3].bits.poisoned connect slots_2.io.wakeup_ports[3].bits.pdst, issue_slots[2].wakeup_ports[3].bits.pdst connect slots_2.io.wakeup_ports[3].valid, issue_slots[2].wakeup_ports[3].valid connect slots_2.io.wakeup_ports[4].bits.poisoned, issue_slots[2].wakeup_ports[4].bits.poisoned connect slots_2.io.wakeup_ports[4].bits.pdst, issue_slots[2].wakeup_ports[4].bits.pdst connect slots_2.io.wakeup_ports[4].valid, issue_slots[2].wakeup_ports[4].valid connect slots_2.io.wakeup_ports[5].bits.poisoned, issue_slots[2].wakeup_ports[5].bits.poisoned connect slots_2.io.wakeup_ports[5].bits.pdst, issue_slots[2].wakeup_ports[5].bits.pdst connect slots_2.io.wakeup_ports[5].valid, issue_slots[2].wakeup_ports[5].valid connect slots_2.io.wakeup_ports[6].bits.poisoned, issue_slots[2].wakeup_ports[6].bits.poisoned connect slots_2.io.wakeup_ports[6].bits.pdst, issue_slots[2].wakeup_ports[6].bits.pdst connect slots_2.io.wakeup_ports[6].valid, issue_slots[2].wakeup_ports[6].valid connect slots_2.io.ldspec_miss, issue_slots[2].ldspec_miss connect slots_2.io.clear, issue_slots[2].clear connect slots_2.io.kill, issue_slots[2].kill connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict connect slots_2.io.brupdate.b2.valid, issue_slots[2].brupdate.b2.valid connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if connect slots_2.io.brupdate.b2.uop.fp_single, issue_slots[2].brupdate.b2.uop.fp_single connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype connect slots_2.io.brupdate.b2.uop.ldst_val, issue_slots[2].brupdate.b2.uop.ldst_val connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd connect slots_2.io.brupdate.b2.uop.bypassable, issue_slots[2].brupdate.b2.uop.bypassable connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx connect slots_2.io.brupdate.b2.uop.csr_addr, issue_slots[2].brupdate.b2.uop.csr_addr connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb connect slots_2.io.brupdate.b2.uop.is_jal, issue_slots[2].brupdate.b2.uop.is_jal connect slots_2.io.brupdate.b2.uop.is_jalr, issue_slots[2].brupdate.b2.uop.is_jalr connect slots_2.io.brupdate.b2.uop.is_br, issue_slots[2].brupdate.b2.uop.is_br connect slots_2.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[2].brupdate.b2.uop.iw_p2_poisoned connect slots_2.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[2].brupdate.b2.uop.iw_p1_poisoned connect slots_2.io.brupdate.b2.uop.iw_state, issue_slots[2].brupdate.b2.uop.iw_state connect slots_2.io.brupdate.b2.uop.ctrl.is_std, issue_slots[2].brupdate.b2.uop.ctrl.is_std connect slots_2.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[2].brupdate.b2.uop.ctrl.is_sta connect slots_2.io.brupdate.b2.uop.ctrl.is_load, issue_slots[2].brupdate.b2.uop.ctrl.is_load connect slots_2.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd connect slots_2.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw connect slots_2.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[2].brupdate.b2.uop.ctrl.op_fcn connect slots_2.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[2].brupdate.b2.uop.ctrl.imm_sel connect slots_2.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[2].brupdate.b2.uop.ctrl.op2_sel connect slots_2.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[2].brupdate.b2.uop.ctrl.op1_sel connect slots_2.io.brupdate.b2.uop.ctrl.br_type, issue_slots[2].brupdate.b2.uop.ctrl.br_type connect slots_2.io.brupdate.b2.uop.fu_code, issue_slots[2].brupdate.b2.uop.fu_code connect slots_2.io.brupdate.b2.uop.iq_type, issue_slots[2].brupdate.b2.uop.iq_type connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst connect slots_2.io.brupdate.b2.uop.uopc, issue_slots[2].brupdate.b2.uop.uopc connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask connect slots_2.io.grant, issue_slots[2].grant connect issue_slots[2].request_hp, slots_2.io.request_hp connect issue_slots[2].request, slots_2.io.request connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid connect issue_slots[2].valid, slots_2.io.valid connect issue_slots[3].debug.state, slots_3.io.debug.state connect issue_slots[3].debug.ppred, slots_3.io.debug.ppred connect issue_slots[3].debug.p3, slots_3.io.debug.p3 connect issue_slots[3].debug.p2, slots_3.io.debug.p2 connect issue_slots[3].debug.p1, slots_3.io.debug.p1 connect issue_slots[3].uop.debug_tsrc, slots_3.io.uop.debug_tsrc connect issue_slots[3].uop.debug_fsrc, slots_3.io.uop.debug_fsrc connect issue_slots[3].uop.bp_xcpt_if, slots_3.io.uop.bp_xcpt_if connect issue_slots[3].uop.bp_debug_if, slots_3.io.uop.bp_debug_if connect issue_slots[3].uop.xcpt_ma_if, slots_3.io.uop.xcpt_ma_if connect issue_slots[3].uop.xcpt_ae_if, slots_3.io.uop.xcpt_ae_if connect issue_slots[3].uop.xcpt_pf_if, slots_3.io.uop.xcpt_pf_if connect issue_slots[3].uop.fp_single, slots_3.io.uop.fp_single connect issue_slots[3].uop.fp_val, slots_3.io.uop.fp_val connect issue_slots[3].uop.frs3_en, slots_3.io.uop.frs3_en connect issue_slots[3].uop.lrs2_rtype, slots_3.io.uop.lrs2_rtype connect issue_slots[3].uop.lrs1_rtype, slots_3.io.uop.lrs1_rtype connect issue_slots[3].uop.dst_rtype, slots_3.io.uop.dst_rtype connect issue_slots[3].uop.ldst_val, slots_3.io.uop.ldst_val connect issue_slots[3].uop.lrs3, slots_3.io.uop.lrs3 connect issue_slots[3].uop.lrs2, slots_3.io.uop.lrs2 connect issue_slots[3].uop.lrs1, slots_3.io.uop.lrs1 connect issue_slots[3].uop.ldst, slots_3.io.uop.ldst connect issue_slots[3].uop.ldst_is_rs1, slots_3.io.uop.ldst_is_rs1 connect issue_slots[3].uop.flush_on_commit, slots_3.io.uop.flush_on_commit connect issue_slots[3].uop.is_unique, slots_3.io.uop.is_unique connect issue_slots[3].uop.is_sys_pc2epc, slots_3.io.uop.is_sys_pc2epc connect issue_slots[3].uop.uses_stq, slots_3.io.uop.uses_stq connect issue_slots[3].uop.uses_ldq, slots_3.io.uop.uses_ldq connect issue_slots[3].uop.is_amo, slots_3.io.uop.is_amo connect issue_slots[3].uop.is_fencei, slots_3.io.uop.is_fencei connect issue_slots[3].uop.is_fence, slots_3.io.uop.is_fence connect issue_slots[3].uop.mem_signed, slots_3.io.uop.mem_signed connect issue_slots[3].uop.mem_size, slots_3.io.uop.mem_size connect issue_slots[3].uop.mem_cmd, slots_3.io.uop.mem_cmd connect issue_slots[3].uop.bypassable, slots_3.io.uop.bypassable connect issue_slots[3].uop.exc_cause, slots_3.io.uop.exc_cause connect issue_slots[3].uop.exception, slots_3.io.uop.exception connect issue_slots[3].uop.stale_pdst, slots_3.io.uop.stale_pdst connect issue_slots[3].uop.ppred_busy, slots_3.io.uop.ppred_busy connect issue_slots[3].uop.prs3_busy, slots_3.io.uop.prs3_busy connect issue_slots[3].uop.prs2_busy, slots_3.io.uop.prs2_busy connect issue_slots[3].uop.prs1_busy, slots_3.io.uop.prs1_busy connect issue_slots[3].uop.ppred, slots_3.io.uop.ppred connect issue_slots[3].uop.prs3, slots_3.io.uop.prs3 connect issue_slots[3].uop.prs2, slots_3.io.uop.prs2 connect issue_slots[3].uop.prs1, slots_3.io.uop.prs1 connect issue_slots[3].uop.pdst, slots_3.io.uop.pdst connect issue_slots[3].uop.rxq_idx, slots_3.io.uop.rxq_idx connect issue_slots[3].uop.stq_idx, slots_3.io.uop.stq_idx connect issue_slots[3].uop.ldq_idx, slots_3.io.uop.ldq_idx connect issue_slots[3].uop.rob_idx, slots_3.io.uop.rob_idx connect issue_slots[3].uop.csr_addr, slots_3.io.uop.csr_addr connect issue_slots[3].uop.imm_packed, slots_3.io.uop.imm_packed connect issue_slots[3].uop.taken, slots_3.io.uop.taken connect issue_slots[3].uop.pc_lob, slots_3.io.uop.pc_lob connect issue_slots[3].uop.edge_inst, slots_3.io.uop.edge_inst connect issue_slots[3].uop.ftq_idx, slots_3.io.uop.ftq_idx connect issue_slots[3].uop.br_tag, slots_3.io.uop.br_tag connect issue_slots[3].uop.br_mask, slots_3.io.uop.br_mask connect issue_slots[3].uop.is_sfb, slots_3.io.uop.is_sfb connect issue_slots[3].uop.is_jal, slots_3.io.uop.is_jal connect issue_slots[3].uop.is_jalr, slots_3.io.uop.is_jalr connect issue_slots[3].uop.is_br, slots_3.io.uop.is_br connect issue_slots[3].uop.iw_p2_poisoned, slots_3.io.uop.iw_p2_poisoned connect issue_slots[3].uop.iw_p1_poisoned, slots_3.io.uop.iw_p1_poisoned connect issue_slots[3].uop.iw_state, slots_3.io.uop.iw_state connect issue_slots[3].uop.ctrl.is_std, slots_3.io.uop.ctrl.is_std connect issue_slots[3].uop.ctrl.is_sta, slots_3.io.uop.ctrl.is_sta connect issue_slots[3].uop.ctrl.is_load, slots_3.io.uop.ctrl.is_load connect issue_slots[3].uop.ctrl.csr_cmd, slots_3.io.uop.ctrl.csr_cmd connect issue_slots[3].uop.ctrl.fcn_dw, slots_3.io.uop.ctrl.fcn_dw connect issue_slots[3].uop.ctrl.op_fcn, slots_3.io.uop.ctrl.op_fcn connect issue_slots[3].uop.ctrl.imm_sel, slots_3.io.uop.ctrl.imm_sel connect issue_slots[3].uop.ctrl.op2_sel, slots_3.io.uop.ctrl.op2_sel connect issue_slots[3].uop.ctrl.op1_sel, slots_3.io.uop.ctrl.op1_sel connect issue_slots[3].uop.ctrl.br_type, slots_3.io.uop.ctrl.br_type connect issue_slots[3].uop.fu_code, slots_3.io.uop.fu_code connect issue_slots[3].uop.iq_type, slots_3.io.uop.iq_type connect issue_slots[3].uop.debug_pc, slots_3.io.uop.debug_pc connect issue_slots[3].uop.is_rvc, slots_3.io.uop.is_rvc connect issue_slots[3].uop.debug_inst, slots_3.io.uop.debug_inst connect issue_slots[3].uop.inst, slots_3.io.uop.inst connect issue_slots[3].uop.uopc, slots_3.io.uop.uopc connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if connect issue_slots[3].out_uop.fp_single, slots_3.io.out_uop.fp_single connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype connect issue_slots[3].out_uop.ldst_val, slots_3.io.out_uop.ldst_val connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd connect issue_slots[3].out_uop.bypassable, slots_3.io.out_uop.bypassable connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx connect issue_slots[3].out_uop.csr_addr, slots_3.io.out_uop.csr_addr connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb connect issue_slots[3].out_uop.is_jal, slots_3.io.out_uop.is_jal connect issue_slots[3].out_uop.is_jalr, slots_3.io.out_uop.is_jalr connect issue_slots[3].out_uop.is_br, slots_3.io.out_uop.is_br connect issue_slots[3].out_uop.iw_p2_poisoned, slots_3.io.out_uop.iw_p2_poisoned connect issue_slots[3].out_uop.iw_p1_poisoned, slots_3.io.out_uop.iw_p1_poisoned connect issue_slots[3].out_uop.iw_state, slots_3.io.out_uop.iw_state connect issue_slots[3].out_uop.ctrl.is_std, slots_3.io.out_uop.ctrl.is_std connect issue_slots[3].out_uop.ctrl.is_sta, slots_3.io.out_uop.ctrl.is_sta connect issue_slots[3].out_uop.ctrl.is_load, slots_3.io.out_uop.ctrl.is_load connect issue_slots[3].out_uop.ctrl.csr_cmd, slots_3.io.out_uop.ctrl.csr_cmd connect issue_slots[3].out_uop.ctrl.fcn_dw, slots_3.io.out_uop.ctrl.fcn_dw connect issue_slots[3].out_uop.ctrl.op_fcn, slots_3.io.out_uop.ctrl.op_fcn connect issue_slots[3].out_uop.ctrl.imm_sel, slots_3.io.out_uop.ctrl.imm_sel connect issue_slots[3].out_uop.ctrl.op2_sel, slots_3.io.out_uop.ctrl.op2_sel connect issue_slots[3].out_uop.ctrl.op1_sel, slots_3.io.out_uop.ctrl.op1_sel connect issue_slots[3].out_uop.ctrl.br_type, slots_3.io.out_uop.ctrl.br_type connect issue_slots[3].out_uop.fu_code, slots_3.io.out_uop.fu_code connect issue_slots[3].out_uop.iq_type, slots_3.io.out_uop.iq_type connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst connect issue_slots[3].out_uop.uopc, slots_3.io.out_uop.uopc connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if connect slots_3.io.in_uop.bits.fp_single, issue_slots[3].in_uop.bits.fp_single connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype connect slots_3.io.in_uop.bits.ldst_val, issue_slots[3].in_uop.bits.ldst_val connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd connect slots_3.io.in_uop.bits.bypassable, issue_slots[3].in_uop.bits.bypassable connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx connect slots_3.io.in_uop.bits.csr_addr, issue_slots[3].in_uop.bits.csr_addr connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb connect slots_3.io.in_uop.bits.is_jal, issue_slots[3].in_uop.bits.is_jal connect slots_3.io.in_uop.bits.is_jalr, issue_slots[3].in_uop.bits.is_jalr connect slots_3.io.in_uop.bits.is_br, issue_slots[3].in_uop.bits.is_br connect slots_3.io.in_uop.bits.iw_p2_poisoned, issue_slots[3].in_uop.bits.iw_p2_poisoned connect slots_3.io.in_uop.bits.iw_p1_poisoned, issue_slots[3].in_uop.bits.iw_p1_poisoned connect slots_3.io.in_uop.bits.iw_state, issue_slots[3].in_uop.bits.iw_state connect slots_3.io.in_uop.bits.ctrl.is_std, issue_slots[3].in_uop.bits.ctrl.is_std connect slots_3.io.in_uop.bits.ctrl.is_sta, issue_slots[3].in_uop.bits.ctrl.is_sta connect slots_3.io.in_uop.bits.ctrl.is_load, issue_slots[3].in_uop.bits.ctrl.is_load connect slots_3.io.in_uop.bits.ctrl.csr_cmd, issue_slots[3].in_uop.bits.ctrl.csr_cmd connect slots_3.io.in_uop.bits.ctrl.fcn_dw, issue_slots[3].in_uop.bits.ctrl.fcn_dw connect slots_3.io.in_uop.bits.ctrl.op_fcn, issue_slots[3].in_uop.bits.ctrl.op_fcn connect slots_3.io.in_uop.bits.ctrl.imm_sel, issue_slots[3].in_uop.bits.ctrl.imm_sel connect slots_3.io.in_uop.bits.ctrl.op2_sel, issue_slots[3].in_uop.bits.ctrl.op2_sel connect slots_3.io.in_uop.bits.ctrl.op1_sel, issue_slots[3].in_uop.bits.ctrl.op1_sel connect slots_3.io.in_uop.bits.ctrl.br_type, issue_slots[3].in_uop.bits.ctrl.br_type connect slots_3.io.in_uop.bits.fu_code, issue_slots[3].in_uop.bits.fu_code connect slots_3.io.in_uop.bits.iq_type, issue_slots[3].in_uop.bits.iq_type connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst connect slots_3.io.in_uop.bits.uopc, issue_slots[3].in_uop.bits.uopc connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid connect slots_3.io.spec_ld_wakeup[0].bits, issue_slots[3].spec_ld_wakeup[0].bits connect slots_3.io.spec_ld_wakeup[0].valid, issue_slots[3].spec_ld_wakeup[0].valid connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid connect slots_3.io.wakeup_ports[0].bits.poisoned, issue_slots[3].wakeup_ports[0].bits.poisoned connect slots_3.io.wakeup_ports[0].bits.pdst, issue_slots[3].wakeup_ports[0].bits.pdst connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid connect slots_3.io.wakeup_ports[1].bits.poisoned, issue_slots[3].wakeup_ports[1].bits.poisoned connect slots_3.io.wakeup_ports[1].bits.pdst, issue_slots[3].wakeup_ports[1].bits.pdst connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid connect slots_3.io.wakeup_ports[2].bits.poisoned, issue_slots[3].wakeup_ports[2].bits.poisoned connect slots_3.io.wakeup_ports[2].bits.pdst, issue_slots[3].wakeup_ports[2].bits.pdst connect slots_3.io.wakeup_ports[2].valid, issue_slots[3].wakeup_ports[2].valid connect slots_3.io.wakeup_ports[3].bits.poisoned, issue_slots[3].wakeup_ports[3].bits.poisoned connect slots_3.io.wakeup_ports[3].bits.pdst, issue_slots[3].wakeup_ports[3].bits.pdst connect slots_3.io.wakeup_ports[3].valid, issue_slots[3].wakeup_ports[3].valid connect slots_3.io.wakeup_ports[4].bits.poisoned, issue_slots[3].wakeup_ports[4].bits.poisoned connect slots_3.io.wakeup_ports[4].bits.pdst, issue_slots[3].wakeup_ports[4].bits.pdst connect slots_3.io.wakeup_ports[4].valid, issue_slots[3].wakeup_ports[4].valid connect slots_3.io.wakeup_ports[5].bits.poisoned, issue_slots[3].wakeup_ports[5].bits.poisoned connect slots_3.io.wakeup_ports[5].bits.pdst, issue_slots[3].wakeup_ports[5].bits.pdst connect slots_3.io.wakeup_ports[5].valid, issue_slots[3].wakeup_ports[5].valid connect slots_3.io.wakeup_ports[6].bits.poisoned, issue_slots[3].wakeup_ports[6].bits.poisoned connect slots_3.io.wakeup_ports[6].bits.pdst, issue_slots[3].wakeup_ports[6].bits.pdst connect slots_3.io.wakeup_ports[6].valid, issue_slots[3].wakeup_ports[6].valid connect slots_3.io.ldspec_miss, issue_slots[3].ldspec_miss connect slots_3.io.clear, issue_slots[3].clear connect slots_3.io.kill, issue_slots[3].kill connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict connect slots_3.io.brupdate.b2.valid, issue_slots[3].brupdate.b2.valid connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if connect slots_3.io.brupdate.b2.uop.fp_single, issue_slots[3].brupdate.b2.uop.fp_single connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype connect slots_3.io.brupdate.b2.uop.ldst_val, issue_slots[3].brupdate.b2.uop.ldst_val connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd connect slots_3.io.brupdate.b2.uop.bypassable, issue_slots[3].brupdate.b2.uop.bypassable connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx connect slots_3.io.brupdate.b2.uop.csr_addr, issue_slots[3].brupdate.b2.uop.csr_addr connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb connect slots_3.io.brupdate.b2.uop.is_jal, issue_slots[3].brupdate.b2.uop.is_jal connect slots_3.io.brupdate.b2.uop.is_jalr, issue_slots[3].brupdate.b2.uop.is_jalr connect slots_3.io.brupdate.b2.uop.is_br, issue_slots[3].brupdate.b2.uop.is_br connect slots_3.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[3].brupdate.b2.uop.iw_p2_poisoned connect slots_3.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[3].brupdate.b2.uop.iw_p1_poisoned connect slots_3.io.brupdate.b2.uop.iw_state, issue_slots[3].brupdate.b2.uop.iw_state connect slots_3.io.brupdate.b2.uop.ctrl.is_std, issue_slots[3].brupdate.b2.uop.ctrl.is_std connect slots_3.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[3].brupdate.b2.uop.ctrl.is_sta connect slots_3.io.brupdate.b2.uop.ctrl.is_load, issue_slots[3].brupdate.b2.uop.ctrl.is_load connect slots_3.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd connect slots_3.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw connect slots_3.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[3].brupdate.b2.uop.ctrl.op_fcn connect slots_3.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[3].brupdate.b2.uop.ctrl.imm_sel connect slots_3.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[3].brupdate.b2.uop.ctrl.op2_sel connect slots_3.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[3].brupdate.b2.uop.ctrl.op1_sel connect slots_3.io.brupdate.b2.uop.ctrl.br_type, issue_slots[3].brupdate.b2.uop.ctrl.br_type connect slots_3.io.brupdate.b2.uop.fu_code, issue_slots[3].brupdate.b2.uop.fu_code connect slots_3.io.brupdate.b2.uop.iq_type, issue_slots[3].brupdate.b2.uop.iq_type connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst connect slots_3.io.brupdate.b2.uop.uopc, issue_slots[3].brupdate.b2.uop.uopc connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask connect slots_3.io.grant, issue_slots[3].grant connect issue_slots[3].request_hp, slots_3.io.request_hp connect issue_slots[3].request, slots_3.io.request connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid connect issue_slots[3].valid, slots_3.io.valid connect issue_slots[4].debug.state, slots_4.io.debug.state connect issue_slots[4].debug.ppred, slots_4.io.debug.ppred connect issue_slots[4].debug.p3, slots_4.io.debug.p3 connect issue_slots[4].debug.p2, slots_4.io.debug.p2 connect issue_slots[4].debug.p1, slots_4.io.debug.p1 connect issue_slots[4].uop.debug_tsrc, slots_4.io.uop.debug_tsrc connect issue_slots[4].uop.debug_fsrc, slots_4.io.uop.debug_fsrc connect issue_slots[4].uop.bp_xcpt_if, slots_4.io.uop.bp_xcpt_if connect issue_slots[4].uop.bp_debug_if, slots_4.io.uop.bp_debug_if connect issue_slots[4].uop.xcpt_ma_if, slots_4.io.uop.xcpt_ma_if connect issue_slots[4].uop.xcpt_ae_if, slots_4.io.uop.xcpt_ae_if connect issue_slots[4].uop.xcpt_pf_if, slots_4.io.uop.xcpt_pf_if connect issue_slots[4].uop.fp_single, slots_4.io.uop.fp_single connect issue_slots[4].uop.fp_val, slots_4.io.uop.fp_val connect issue_slots[4].uop.frs3_en, slots_4.io.uop.frs3_en connect issue_slots[4].uop.lrs2_rtype, slots_4.io.uop.lrs2_rtype connect issue_slots[4].uop.lrs1_rtype, slots_4.io.uop.lrs1_rtype connect issue_slots[4].uop.dst_rtype, slots_4.io.uop.dst_rtype connect issue_slots[4].uop.ldst_val, slots_4.io.uop.ldst_val connect issue_slots[4].uop.lrs3, slots_4.io.uop.lrs3 connect issue_slots[4].uop.lrs2, slots_4.io.uop.lrs2 connect issue_slots[4].uop.lrs1, slots_4.io.uop.lrs1 connect issue_slots[4].uop.ldst, slots_4.io.uop.ldst connect issue_slots[4].uop.ldst_is_rs1, slots_4.io.uop.ldst_is_rs1 connect issue_slots[4].uop.flush_on_commit, slots_4.io.uop.flush_on_commit connect issue_slots[4].uop.is_unique, slots_4.io.uop.is_unique connect issue_slots[4].uop.is_sys_pc2epc, slots_4.io.uop.is_sys_pc2epc connect issue_slots[4].uop.uses_stq, slots_4.io.uop.uses_stq connect issue_slots[4].uop.uses_ldq, slots_4.io.uop.uses_ldq connect issue_slots[4].uop.is_amo, slots_4.io.uop.is_amo connect issue_slots[4].uop.is_fencei, slots_4.io.uop.is_fencei connect issue_slots[4].uop.is_fence, slots_4.io.uop.is_fence connect issue_slots[4].uop.mem_signed, slots_4.io.uop.mem_signed connect issue_slots[4].uop.mem_size, slots_4.io.uop.mem_size connect issue_slots[4].uop.mem_cmd, slots_4.io.uop.mem_cmd connect issue_slots[4].uop.bypassable, slots_4.io.uop.bypassable connect issue_slots[4].uop.exc_cause, slots_4.io.uop.exc_cause connect issue_slots[4].uop.exception, slots_4.io.uop.exception connect issue_slots[4].uop.stale_pdst, slots_4.io.uop.stale_pdst connect issue_slots[4].uop.ppred_busy, slots_4.io.uop.ppred_busy connect issue_slots[4].uop.prs3_busy, slots_4.io.uop.prs3_busy connect issue_slots[4].uop.prs2_busy, slots_4.io.uop.prs2_busy connect issue_slots[4].uop.prs1_busy, slots_4.io.uop.prs1_busy connect issue_slots[4].uop.ppred, slots_4.io.uop.ppred connect issue_slots[4].uop.prs3, slots_4.io.uop.prs3 connect issue_slots[4].uop.prs2, slots_4.io.uop.prs2 connect issue_slots[4].uop.prs1, slots_4.io.uop.prs1 connect issue_slots[4].uop.pdst, slots_4.io.uop.pdst connect issue_slots[4].uop.rxq_idx, slots_4.io.uop.rxq_idx connect issue_slots[4].uop.stq_idx, slots_4.io.uop.stq_idx connect issue_slots[4].uop.ldq_idx, slots_4.io.uop.ldq_idx connect issue_slots[4].uop.rob_idx, slots_4.io.uop.rob_idx connect issue_slots[4].uop.csr_addr, slots_4.io.uop.csr_addr connect issue_slots[4].uop.imm_packed, slots_4.io.uop.imm_packed connect issue_slots[4].uop.taken, slots_4.io.uop.taken connect issue_slots[4].uop.pc_lob, slots_4.io.uop.pc_lob connect issue_slots[4].uop.edge_inst, slots_4.io.uop.edge_inst connect issue_slots[4].uop.ftq_idx, slots_4.io.uop.ftq_idx connect issue_slots[4].uop.br_tag, slots_4.io.uop.br_tag connect issue_slots[4].uop.br_mask, slots_4.io.uop.br_mask connect issue_slots[4].uop.is_sfb, slots_4.io.uop.is_sfb connect issue_slots[4].uop.is_jal, slots_4.io.uop.is_jal connect issue_slots[4].uop.is_jalr, slots_4.io.uop.is_jalr connect issue_slots[4].uop.is_br, slots_4.io.uop.is_br connect issue_slots[4].uop.iw_p2_poisoned, slots_4.io.uop.iw_p2_poisoned connect issue_slots[4].uop.iw_p1_poisoned, slots_4.io.uop.iw_p1_poisoned connect issue_slots[4].uop.iw_state, slots_4.io.uop.iw_state connect issue_slots[4].uop.ctrl.is_std, slots_4.io.uop.ctrl.is_std connect issue_slots[4].uop.ctrl.is_sta, slots_4.io.uop.ctrl.is_sta connect issue_slots[4].uop.ctrl.is_load, slots_4.io.uop.ctrl.is_load connect issue_slots[4].uop.ctrl.csr_cmd, slots_4.io.uop.ctrl.csr_cmd connect issue_slots[4].uop.ctrl.fcn_dw, slots_4.io.uop.ctrl.fcn_dw connect issue_slots[4].uop.ctrl.op_fcn, slots_4.io.uop.ctrl.op_fcn connect issue_slots[4].uop.ctrl.imm_sel, slots_4.io.uop.ctrl.imm_sel connect issue_slots[4].uop.ctrl.op2_sel, slots_4.io.uop.ctrl.op2_sel connect issue_slots[4].uop.ctrl.op1_sel, slots_4.io.uop.ctrl.op1_sel connect issue_slots[4].uop.ctrl.br_type, slots_4.io.uop.ctrl.br_type connect issue_slots[4].uop.fu_code, slots_4.io.uop.fu_code connect issue_slots[4].uop.iq_type, slots_4.io.uop.iq_type connect issue_slots[4].uop.debug_pc, slots_4.io.uop.debug_pc connect issue_slots[4].uop.is_rvc, slots_4.io.uop.is_rvc connect issue_slots[4].uop.debug_inst, slots_4.io.uop.debug_inst connect issue_slots[4].uop.inst, slots_4.io.uop.inst connect issue_slots[4].uop.uopc, slots_4.io.uop.uopc connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if connect issue_slots[4].out_uop.fp_single, slots_4.io.out_uop.fp_single connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype connect issue_slots[4].out_uop.ldst_val, slots_4.io.out_uop.ldst_val connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd connect issue_slots[4].out_uop.bypassable, slots_4.io.out_uop.bypassable connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx connect issue_slots[4].out_uop.csr_addr, slots_4.io.out_uop.csr_addr connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb connect issue_slots[4].out_uop.is_jal, slots_4.io.out_uop.is_jal connect issue_slots[4].out_uop.is_jalr, slots_4.io.out_uop.is_jalr connect issue_slots[4].out_uop.is_br, slots_4.io.out_uop.is_br connect issue_slots[4].out_uop.iw_p2_poisoned, slots_4.io.out_uop.iw_p2_poisoned connect issue_slots[4].out_uop.iw_p1_poisoned, slots_4.io.out_uop.iw_p1_poisoned connect issue_slots[4].out_uop.iw_state, slots_4.io.out_uop.iw_state connect issue_slots[4].out_uop.ctrl.is_std, slots_4.io.out_uop.ctrl.is_std connect issue_slots[4].out_uop.ctrl.is_sta, slots_4.io.out_uop.ctrl.is_sta connect issue_slots[4].out_uop.ctrl.is_load, slots_4.io.out_uop.ctrl.is_load connect issue_slots[4].out_uop.ctrl.csr_cmd, slots_4.io.out_uop.ctrl.csr_cmd connect issue_slots[4].out_uop.ctrl.fcn_dw, slots_4.io.out_uop.ctrl.fcn_dw connect issue_slots[4].out_uop.ctrl.op_fcn, slots_4.io.out_uop.ctrl.op_fcn connect issue_slots[4].out_uop.ctrl.imm_sel, slots_4.io.out_uop.ctrl.imm_sel connect issue_slots[4].out_uop.ctrl.op2_sel, slots_4.io.out_uop.ctrl.op2_sel connect issue_slots[4].out_uop.ctrl.op1_sel, slots_4.io.out_uop.ctrl.op1_sel connect issue_slots[4].out_uop.ctrl.br_type, slots_4.io.out_uop.ctrl.br_type connect issue_slots[4].out_uop.fu_code, slots_4.io.out_uop.fu_code connect issue_slots[4].out_uop.iq_type, slots_4.io.out_uop.iq_type connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst connect issue_slots[4].out_uop.uopc, slots_4.io.out_uop.uopc connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if connect slots_4.io.in_uop.bits.fp_single, issue_slots[4].in_uop.bits.fp_single connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype connect slots_4.io.in_uop.bits.ldst_val, issue_slots[4].in_uop.bits.ldst_val connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd connect slots_4.io.in_uop.bits.bypassable, issue_slots[4].in_uop.bits.bypassable connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx connect slots_4.io.in_uop.bits.csr_addr, issue_slots[4].in_uop.bits.csr_addr connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb connect slots_4.io.in_uop.bits.is_jal, issue_slots[4].in_uop.bits.is_jal connect slots_4.io.in_uop.bits.is_jalr, issue_slots[4].in_uop.bits.is_jalr connect slots_4.io.in_uop.bits.is_br, issue_slots[4].in_uop.bits.is_br connect slots_4.io.in_uop.bits.iw_p2_poisoned, issue_slots[4].in_uop.bits.iw_p2_poisoned connect slots_4.io.in_uop.bits.iw_p1_poisoned, issue_slots[4].in_uop.bits.iw_p1_poisoned connect slots_4.io.in_uop.bits.iw_state, issue_slots[4].in_uop.bits.iw_state connect slots_4.io.in_uop.bits.ctrl.is_std, issue_slots[4].in_uop.bits.ctrl.is_std connect slots_4.io.in_uop.bits.ctrl.is_sta, issue_slots[4].in_uop.bits.ctrl.is_sta connect slots_4.io.in_uop.bits.ctrl.is_load, issue_slots[4].in_uop.bits.ctrl.is_load connect slots_4.io.in_uop.bits.ctrl.csr_cmd, issue_slots[4].in_uop.bits.ctrl.csr_cmd connect slots_4.io.in_uop.bits.ctrl.fcn_dw, issue_slots[4].in_uop.bits.ctrl.fcn_dw connect slots_4.io.in_uop.bits.ctrl.op_fcn, issue_slots[4].in_uop.bits.ctrl.op_fcn connect slots_4.io.in_uop.bits.ctrl.imm_sel, issue_slots[4].in_uop.bits.ctrl.imm_sel connect slots_4.io.in_uop.bits.ctrl.op2_sel, issue_slots[4].in_uop.bits.ctrl.op2_sel connect slots_4.io.in_uop.bits.ctrl.op1_sel, issue_slots[4].in_uop.bits.ctrl.op1_sel connect slots_4.io.in_uop.bits.ctrl.br_type, issue_slots[4].in_uop.bits.ctrl.br_type connect slots_4.io.in_uop.bits.fu_code, issue_slots[4].in_uop.bits.fu_code connect slots_4.io.in_uop.bits.iq_type, issue_slots[4].in_uop.bits.iq_type connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst connect slots_4.io.in_uop.bits.uopc, issue_slots[4].in_uop.bits.uopc connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid connect slots_4.io.spec_ld_wakeup[0].bits, issue_slots[4].spec_ld_wakeup[0].bits connect slots_4.io.spec_ld_wakeup[0].valid, issue_slots[4].spec_ld_wakeup[0].valid connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid connect slots_4.io.wakeup_ports[0].bits.poisoned, issue_slots[4].wakeup_ports[0].bits.poisoned connect slots_4.io.wakeup_ports[0].bits.pdst, issue_slots[4].wakeup_ports[0].bits.pdst connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid connect slots_4.io.wakeup_ports[1].bits.poisoned, issue_slots[4].wakeup_ports[1].bits.poisoned connect slots_4.io.wakeup_ports[1].bits.pdst, issue_slots[4].wakeup_ports[1].bits.pdst connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid connect slots_4.io.wakeup_ports[2].bits.poisoned, issue_slots[4].wakeup_ports[2].bits.poisoned connect slots_4.io.wakeup_ports[2].bits.pdst, issue_slots[4].wakeup_ports[2].bits.pdst connect slots_4.io.wakeup_ports[2].valid, issue_slots[4].wakeup_ports[2].valid connect slots_4.io.wakeup_ports[3].bits.poisoned, issue_slots[4].wakeup_ports[3].bits.poisoned connect slots_4.io.wakeup_ports[3].bits.pdst, issue_slots[4].wakeup_ports[3].bits.pdst connect slots_4.io.wakeup_ports[3].valid, issue_slots[4].wakeup_ports[3].valid connect slots_4.io.wakeup_ports[4].bits.poisoned, issue_slots[4].wakeup_ports[4].bits.poisoned connect slots_4.io.wakeup_ports[4].bits.pdst, issue_slots[4].wakeup_ports[4].bits.pdst connect slots_4.io.wakeup_ports[4].valid, issue_slots[4].wakeup_ports[4].valid connect slots_4.io.wakeup_ports[5].bits.poisoned, issue_slots[4].wakeup_ports[5].bits.poisoned connect slots_4.io.wakeup_ports[5].bits.pdst, issue_slots[4].wakeup_ports[5].bits.pdst connect slots_4.io.wakeup_ports[5].valid, issue_slots[4].wakeup_ports[5].valid connect slots_4.io.wakeup_ports[6].bits.poisoned, issue_slots[4].wakeup_ports[6].bits.poisoned connect slots_4.io.wakeup_ports[6].bits.pdst, issue_slots[4].wakeup_ports[6].bits.pdst connect slots_4.io.wakeup_ports[6].valid, issue_slots[4].wakeup_ports[6].valid connect slots_4.io.ldspec_miss, issue_slots[4].ldspec_miss connect slots_4.io.clear, issue_slots[4].clear connect slots_4.io.kill, issue_slots[4].kill connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict connect slots_4.io.brupdate.b2.valid, issue_slots[4].brupdate.b2.valid connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if connect slots_4.io.brupdate.b2.uop.fp_single, issue_slots[4].brupdate.b2.uop.fp_single connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype connect slots_4.io.brupdate.b2.uop.ldst_val, issue_slots[4].brupdate.b2.uop.ldst_val connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd connect slots_4.io.brupdate.b2.uop.bypassable, issue_slots[4].brupdate.b2.uop.bypassable connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx connect slots_4.io.brupdate.b2.uop.csr_addr, issue_slots[4].brupdate.b2.uop.csr_addr connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb connect slots_4.io.brupdate.b2.uop.is_jal, issue_slots[4].brupdate.b2.uop.is_jal connect slots_4.io.brupdate.b2.uop.is_jalr, issue_slots[4].brupdate.b2.uop.is_jalr connect slots_4.io.brupdate.b2.uop.is_br, issue_slots[4].brupdate.b2.uop.is_br connect slots_4.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[4].brupdate.b2.uop.iw_p2_poisoned connect slots_4.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[4].brupdate.b2.uop.iw_p1_poisoned connect slots_4.io.brupdate.b2.uop.iw_state, issue_slots[4].brupdate.b2.uop.iw_state connect slots_4.io.brupdate.b2.uop.ctrl.is_std, issue_slots[4].brupdate.b2.uop.ctrl.is_std connect slots_4.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[4].brupdate.b2.uop.ctrl.is_sta connect slots_4.io.brupdate.b2.uop.ctrl.is_load, issue_slots[4].brupdate.b2.uop.ctrl.is_load connect slots_4.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd connect slots_4.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw connect slots_4.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[4].brupdate.b2.uop.ctrl.op_fcn connect slots_4.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[4].brupdate.b2.uop.ctrl.imm_sel connect slots_4.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[4].brupdate.b2.uop.ctrl.op2_sel connect slots_4.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[4].brupdate.b2.uop.ctrl.op1_sel connect slots_4.io.brupdate.b2.uop.ctrl.br_type, issue_slots[4].brupdate.b2.uop.ctrl.br_type connect slots_4.io.brupdate.b2.uop.fu_code, issue_slots[4].brupdate.b2.uop.fu_code connect slots_4.io.brupdate.b2.uop.iq_type, issue_slots[4].brupdate.b2.uop.iq_type connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst connect slots_4.io.brupdate.b2.uop.uopc, issue_slots[4].brupdate.b2.uop.uopc connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask connect slots_4.io.grant, issue_slots[4].grant connect issue_slots[4].request_hp, slots_4.io.request_hp connect issue_slots[4].request, slots_4.io.request connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid connect issue_slots[4].valid, slots_4.io.valid connect issue_slots[5].debug.state, slots_5.io.debug.state connect issue_slots[5].debug.ppred, slots_5.io.debug.ppred connect issue_slots[5].debug.p3, slots_5.io.debug.p3 connect issue_slots[5].debug.p2, slots_5.io.debug.p2 connect issue_slots[5].debug.p1, slots_5.io.debug.p1 connect issue_slots[5].uop.debug_tsrc, slots_5.io.uop.debug_tsrc connect issue_slots[5].uop.debug_fsrc, slots_5.io.uop.debug_fsrc connect issue_slots[5].uop.bp_xcpt_if, slots_5.io.uop.bp_xcpt_if connect issue_slots[5].uop.bp_debug_if, slots_5.io.uop.bp_debug_if connect issue_slots[5].uop.xcpt_ma_if, slots_5.io.uop.xcpt_ma_if connect issue_slots[5].uop.xcpt_ae_if, slots_5.io.uop.xcpt_ae_if connect issue_slots[5].uop.xcpt_pf_if, slots_5.io.uop.xcpt_pf_if connect issue_slots[5].uop.fp_single, slots_5.io.uop.fp_single connect issue_slots[5].uop.fp_val, slots_5.io.uop.fp_val connect issue_slots[5].uop.frs3_en, slots_5.io.uop.frs3_en connect issue_slots[5].uop.lrs2_rtype, slots_5.io.uop.lrs2_rtype connect issue_slots[5].uop.lrs1_rtype, slots_5.io.uop.lrs1_rtype connect issue_slots[5].uop.dst_rtype, slots_5.io.uop.dst_rtype connect issue_slots[5].uop.ldst_val, slots_5.io.uop.ldst_val connect issue_slots[5].uop.lrs3, slots_5.io.uop.lrs3 connect issue_slots[5].uop.lrs2, slots_5.io.uop.lrs2 connect issue_slots[5].uop.lrs1, slots_5.io.uop.lrs1 connect issue_slots[5].uop.ldst, slots_5.io.uop.ldst connect issue_slots[5].uop.ldst_is_rs1, slots_5.io.uop.ldst_is_rs1 connect issue_slots[5].uop.flush_on_commit, slots_5.io.uop.flush_on_commit connect issue_slots[5].uop.is_unique, slots_5.io.uop.is_unique connect issue_slots[5].uop.is_sys_pc2epc, slots_5.io.uop.is_sys_pc2epc connect issue_slots[5].uop.uses_stq, slots_5.io.uop.uses_stq connect issue_slots[5].uop.uses_ldq, slots_5.io.uop.uses_ldq connect issue_slots[5].uop.is_amo, slots_5.io.uop.is_amo connect issue_slots[5].uop.is_fencei, slots_5.io.uop.is_fencei connect issue_slots[5].uop.is_fence, slots_5.io.uop.is_fence connect issue_slots[5].uop.mem_signed, slots_5.io.uop.mem_signed connect issue_slots[5].uop.mem_size, slots_5.io.uop.mem_size connect issue_slots[5].uop.mem_cmd, slots_5.io.uop.mem_cmd connect issue_slots[5].uop.bypassable, slots_5.io.uop.bypassable connect issue_slots[5].uop.exc_cause, slots_5.io.uop.exc_cause connect issue_slots[5].uop.exception, slots_5.io.uop.exception connect issue_slots[5].uop.stale_pdst, slots_5.io.uop.stale_pdst connect issue_slots[5].uop.ppred_busy, slots_5.io.uop.ppred_busy connect issue_slots[5].uop.prs3_busy, slots_5.io.uop.prs3_busy connect issue_slots[5].uop.prs2_busy, slots_5.io.uop.prs2_busy connect issue_slots[5].uop.prs1_busy, slots_5.io.uop.prs1_busy connect issue_slots[5].uop.ppred, slots_5.io.uop.ppred connect issue_slots[5].uop.prs3, slots_5.io.uop.prs3 connect issue_slots[5].uop.prs2, slots_5.io.uop.prs2 connect issue_slots[5].uop.prs1, slots_5.io.uop.prs1 connect issue_slots[5].uop.pdst, slots_5.io.uop.pdst connect issue_slots[5].uop.rxq_idx, slots_5.io.uop.rxq_idx connect issue_slots[5].uop.stq_idx, slots_5.io.uop.stq_idx connect issue_slots[5].uop.ldq_idx, slots_5.io.uop.ldq_idx connect issue_slots[5].uop.rob_idx, slots_5.io.uop.rob_idx connect issue_slots[5].uop.csr_addr, slots_5.io.uop.csr_addr connect issue_slots[5].uop.imm_packed, slots_5.io.uop.imm_packed connect issue_slots[5].uop.taken, slots_5.io.uop.taken connect issue_slots[5].uop.pc_lob, slots_5.io.uop.pc_lob connect issue_slots[5].uop.edge_inst, slots_5.io.uop.edge_inst connect issue_slots[5].uop.ftq_idx, slots_5.io.uop.ftq_idx connect issue_slots[5].uop.br_tag, slots_5.io.uop.br_tag connect issue_slots[5].uop.br_mask, slots_5.io.uop.br_mask connect issue_slots[5].uop.is_sfb, slots_5.io.uop.is_sfb connect issue_slots[5].uop.is_jal, slots_5.io.uop.is_jal connect issue_slots[5].uop.is_jalr, slots_5.io.uop.is_jalr connect issue_slots[5].uop.is_br, slots_5.io.uop.is_br connect issue_slots[5].uop.iw_p2_poisoned, slots_5.io.uop.iw_p2_poisoned connect issue_slots[5].uop.iw_p1_poisoned, slots_5.io.uop.iw_p1_poisoned connect issue_slots[5].uop.iw_state, slots_5.io.uop.iw_state connect issue_slots[5].uop.ctrl.is_std, slots_5.io.uop.ctrl.is_std connect issue_slots[5].uop.ctrl.is_sta, slots_5.io.uop.ctrl.is_sta connect issue_slots[5].uop.ctrl.is_load, slots_5.io.uop.ctrl.is_load connect issue_slots[5].uop.ctrl.csr_cmd, slots_5.io.uop.ctrl.csr_cmd connect issue_slots[5].uop.ctrl.fcn_dw, slots_5.io.uop.ctrl.fcn_dw connect issue_slots[5].uop.ctrl.op_fcn, slots_5.io.uop.ctrl.op_fcn connect issue_slots[5].uop.ctrl.imm_sel, slots_5.io.uop.ctrl.imm_sel connect issue_slots[5].uop.ctrl.op2_sel, slots_5.io.uop.ctrl.op2_sel connect issue_slots[5].uop.ctrl.op1_sel, slots_5.io.uop.ctrl.op1_sel connect issue_slots[5].uop.ctrl.br_type, slots_5.io.uop.ctrl.br_type connect issue_slots[5].uop.fu_code, slots_5.io.uop.fu_code connect issue_slots[5].uop.iq_type, slots_5.io.uop.iq_type connect issue_slots[5].uop.debug_pc, slots_5.io.uop.debug_pc connect issue_slots[5].uop.is_rvc, slots_5.io.uop.is_rvc connect issue_slots[5].uop.debug_inst, slots_5.io.uop.debug_inst connect issue_slots[5].uop.inst, slots_5.io.uop.inst connect issue_slots[5].uop.uopc, slots_5.io.uop.uopc connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if connect issue_slots[5].out_uop.fp_single, slots_5.io.out_uop.fp_single connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype connect issue_slots[5].out_uop.ldst_val, slots_5.io.out_uop.ldst_val connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd connect issue_slots[5].out_uop.bypassable, slots_5.io.out_uop.bypassable connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx connect issue_slots[5].out_uop.csr_addr, slots_5.io.out_uop.csr_addr connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb connect issue_slots[5].out_uop.is_jal, slots_5.io.out_uop.is_jal connect issue_slots[5].out_uop.is_jalr, slots_5.io.out_uop.is_jalr connect issue_slots[5].out_uop.is_br, slots_5.io.out_uop.is_br connect issue_slots[5].out_uop.iw_p2_poisoned, slots_5.io.out_uop.iw_p2_poisoned connect issue_slots[5].out_uop.iw_p1_poisoned, slots_5.io.out_uop.iw_p1_poisoned connect issue_slots[5].out_uop.iw_state, slots_5.io.out_uop.iw_state connect issue_slots[5].out_uop.ctrl.is_std, slots_5.io.out_uop.ctrl.is_std connect issue_slots[5].out_uop.ctrl.is_sta, slots_5.io.out_uop.ctrl.is_sta connect issue_slots[5].out_uop.ctrl.is_load, slots_5.io.out_uop.ctrl.is_load connect issue_slots[5].out_uop.ctrl.csr_cmd, slots_5.io.out_uop.ctrl.csr_cmd connect issue_slots[5].out_uop.ctrl.fcn_dw, slots_5.io.out_uop.ctrl.fcn_dw connect issue_slots[5].out_uop.ctrl.op_fcn, slots_5.io.out_uop.ctrl.op_fcn connect issue_slots[5].out_uop.ctrl.imm_sel, slots_5.io.out_uop.ctrl.imm_sel connect issue_slots[5].out_uop.ctrl.op2_sel, slots_5.io.out_uop.ctrl.op2_sel connect issue_slots[5].out_uop.ctrl.op1_sel, slots_5.io.out_uop.ctrl.op1_sel connect issue_slots[5].out_uop.ctrl.br_type, slots_5.io.out_uop.ctrl.br_type connect issue_slots[5].out_uop.fu_code, slots_5.io.out_uop.fu_code connect issue_slots[5].out_uop.iq_type, slots_5.io.out_uop.iq_type connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst connect issue_slots[5].out_uop.uopc, slots_5.io.out_uop.uopc connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if connect slots_5.io.in_uop.bits.fp_single, issue_slots[5].in_uop.bits.fp_single connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype connect slots_5.io.in_uop.bits.ldst_val, issue_slots[5].in_uop.bits.ldst_val connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd connect slots_5.io.in_uop.bits.bypassable, issue_slots[5].in_uop.bits.bypassable connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx connect slots_5.io.in_uop.bits.csr_addr, issue_slots[5].in_uop.bits.csr_addr connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb connect slots_5.io.in_uop.bits.is_jal, issue_slots[5].in_uop.bits.is_jal connect slots_5.io.in_uop.bits.is_jalr, issue_slots[5].in_uop.bits.is_jalr connect slots_5.io.in_uop.bits.is_br, issue_slots[5].in_uop.bits.is_br connect slots_5.io.in_uop.bits.iw_p2_poisoned, issue_slots[5].in_uop.bits.iw_p2_poisoned connect slots_5.io.in_uop.bits.iw_p1_poisoned, issue_slots[5].in_uop.bits.iw_p1_poisoned connect slots_5.io.in_uop.bits.iw_state, issue_slots[5].in_uop.bits.iw_state connect slots_5.io.in_uop.bits.ctrl.is_std, issue_slots[5].in_uop.bits.ctrl.is_std connect slots_5.io.in_uop.bits.ctrl.is_sta, issue_slots[5].in_uop.bits.ctrl.is_sta connect slots_5.io.in_uop.bits.ctrl.is_load, issue_slots[5].in_uop.bits.ctrl.is_load connect slots_5.io.in_uop.bits.ctrl.csr_cmd, issue_slots[5].in_uop.bits.ctrl.csr_cmd connect slots_5.io.in_uop.bits.ctrl.fcn_dw, issue_slots[5].in_uop.bits.ctrl.fcn_dw connect slots_5.io.in_uop.bits.ctrl.op_fcn, issue_slots[5].in_uop.bits.ctrl.op_fcn connect slots_5.io.in_uop.bits.ctrl.imm_sel, issue_slots[5].in_uop.bits.ctrl.imm_sel connect slots_5.io.in_uop.bits.ctrl.op2_sel, issue_slots[5].in_uop.bits.ctrl.op2_sel connect slots_5.io.in_uop.bits.ctrl.op1_sel, issue_slots[5].in_uop.bits.ctrl.op1_sel connect slots_5.io.in_uop.bits.ctrl.br_type, issue_slots[5].in_uop.bits.ctrl.br_type connect slots_5.io.in_uop.bits.fu_code, issue_slots[5].in_uop.bits.fu_code connect slots_5.io.in_uop.bits.iq_type, issue_slots[5].in_uop.bits.iq_type connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst connect slots_5.io.in_uop.bits.uopc, issue_slots[5].in_uop.bits.uopc connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid connect slots_5.io.spec_ld_wakeup[0].bits, issue_slots[5].spec_ld_wakeup[0].bits connect slots_5.io.spec_ld_wakeup[0].valid, issue_slots[5].spec_ld_wakeup[0].valid connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid connect slots_5.io.wakeup_ports[0].bits.poisoned, issue_slots[5].wakeup_ports[0].bits.poisoned connect slots_5.io.wakeup_ports[0].bits.pdst, issue_slots[5].wakeup_ports[0].bits.pdst connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid connect slots_5.io.wakeup_ports[1].bits.poisoned, issue_slots[5].wakeup_ports[1].bits.poisoned connect slots_5.io.wakeup_ports[1].bits.pdst, issue_slots[5].wakeup_ports[1].bits.pdst connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid connect slots_5.io.wakeup_ports[2].bits.poisoned, issue_slots[5].wakeup_ports[2].bits.poisoned connect slots_5.io.wakeup_ports[2].bits.pdst, issue_slots[5].wakeup_ports[2].bits.pdst connect slots_5.io.wakeup_ports[2].valid, issue_slots[5].wakeup_ports[2].valid connect slots_5.io.wakeup_ports[3].bits.poisoned, issue_slots[5].wakeup_ports[3].bits.poisoned connect slots_5.io.wakeup_ports[3].bits.pdst, issue_slots[5].wakeup_ports[3].bits.pdst connect slots_5.io.wakeup_ports[3].valid, issue_slots[5].wakeup_ports[3].valid connect slots_5.io.wakeup_ports[4].bits.poisoned, issue_slots[5].wakeup_ports[4].bits.poisoned connect slots_5.io.wakeup_ports[4].bits.pdst, issue_slots[5].wakeup_ports[4].bits.pdst connect slots_5.io.wakeup_ports[4].valid, issue_slots[5].wakeup_ports[4].valid connect slots_5.io.wakeup_ports[5].bits.poisoned, issue_slots[5].wakeup_ports[5].bits.poisoned connect slots_5.io.wakeup_ports[5].bits.pdst, issue_slots[5].wakeup_ports[5].bits.pdst connect slots_5.io.wakeup_ports[5].valid, issue_slots[5].wakeup_ports[5].valid connect slots_5.io.wakeup_ports[6].bits.poisoned, issue_slots[5].wakeup_ports[6].bits.poisoned connect slots_5.io.wakeup_ports[6].bits.pdst, issue_slots[5].wakeup_ports[6].bits.pdst connect slots_5.io.wakeup_ports[6].valid, issue_slots[5].wakeup_ports[6].valid connect slots_5.io.ldspec_miss, issue_slots[5].ldspec_miss connect slots_5.io.clear, issue_slots[5].clear connect slots_5.io.kill, issue_slots[5].kill connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict connect slots_5.io.brupdate.b2.valid, issue_slots[5].brupdate.b2.valid connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if connect slots_5.io.brupdate.b2.uop.fp_single, issue_slots[5].brupdate.b2.uop.fp_single connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype connect slots_5.io.brupdate.b2.uop.ldst_val, issue_slots[5].brupdate.b2.uop.ldst_val connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd connect slots_5.io.brupdate.b2.uop.bypassable, issue_slots[5].brupdate.b2.uop.bypassable connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx connect slots_5.io.brupdate.b2.uop.csr_addr, issue_slots[5].brupdate.b2.uop.csr_addr connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb connect slots_5.io.brupdate.b2.uop.is_jal, issue_slots[5].brupdate.b2.uop.is_jal connect slots_5.io.brupdate.b2.uop.is_jalr, issue_slots[5].brupdate.b2.uop.is_jalr connect slots_5.io.brupdate.b2.uop.is_br, issue_slots[5].brupdate.b2.uop.is_br connect slots_5.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[5].brupdate.b2.uop.iw_p2_poisoned connect slots_5.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[5].brupdate.b2.uop.iw_p1_poisoned connect slots_5.io.brupdate.b2.uop.iw_state, issue_slots[5].brupdate.b2.uop.iw_state connect slots_5.io.brupdate.b2.uop.ctrl.is_std, issue_slots[5].brupdate.b2.uop.ctrl.is_std connect slots_5.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[5].brupdate.b2.uop.ctrl.is_sta connect slots_5.io.brupdate.b2.uop.ctrl.is_load, issue_slots[5].brupdate.b2.uop.ctrl.is_load connect slots_5.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd connect slots_5.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw connect slots_5.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[5].brupdate.b2.uop.ctrl.op_fcn connect slots_5.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[5].brupdate.b2.uop.ctrl.imm_sel connect slots_5.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[5].brupdate.b2.uop.ctrl.op2_sel connect slots_5.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[5].brupdate.b2.uop.ctrl.op1_sel connect slots_5.io.brupdate.b2.uop.ctrl.br_type, issue_slots[5].brupdate.b2.uop.ctrl.br_type connect slots_5.io.brupdate.b2.uop.fu_code, issue_slots[5].brupdate.b2.uop.fu_code connect slots_5.io.brupdate.b2.uop.iq_type, issue_slots[5].brupdate.b2.uop.iq_type connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst connect slots_5.io.brupdate.b2.uop.uopc, issue_slots[5].brupdate.b2.uop.uopc connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask connect slots_5.io.grant, issue_slots[5].grant connect issue_slots[5].request_hp, slots_5.io.request_hp connect issue_slots[5].request, slots_5.io.request connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid connect issue_slots[5].valid, slots_5.io.valid connect issue_slots[6].debug.state, slots_6.io.debug.state connect issue_slots[6].debug.ppred, slots_6.io.debug.ppred connect issue_slots[6].debug.p3, slots_6.io.debug.p3 connect issue_slots[6].debug.p2, slots_6.io.debug.p2 connect issue_slots[6].debug.p1, slots_6.io.debug.p1 connect issue_slots[6].uop.debug_tsrc, slots_6.io.uop.debug_tsrc connect issue_slots[6].uop.debug_fsrc, slots_6.io.uop.debug_fsrc connect issue_slots[6].uop.bp_xcpt_if, slots_6.io.uop.bp_xcpt_if connect issue_slots[6].uop.bp_debug_if, slots_6.io.uop.bp_debug_if connect issue_slots[6].uop.xcpt_ma_if, slots_6.io.uop.xcpt_ma_if connect issue_slots[6].uop.xcpt_ae_if, slots_6.io.uop.xcpt_ae_if connect issue_slots[6].uop.xcpt_pf_if, slots_6.io.uop.xcpt_pf_if connect issue_slots[6].uop.fp_single, slots_6.io.uop.fp_single connect issue_slots[6].uop.fp_val, slots_6.io.uop.fp_val connect issue_slots[6].uop.frs3_en, slots_6.io.uop.frs3_en connect issue_slots[6].uop.lrs2_rtype, slots_6.io.uop.lrs2_rtype connect issue_slots[6].uop.lrs1_rtype, slots_6.io.uop.lrs1_rtype connect issue_slots[6].uop.dst_rtype, slots_6.io.uop.dst_rtype connect issue_slots[6].uop.ldst_val, slots_6.io.uop.ldst_val connect issue_slots[6].uop.lrs3, slots_6.io.uop.lrs3 connect issue_slots[6].uop.lrs2, slots_6.io.uop.lrs2 connect issue_slots[6].uop.lrs1, slots_6.io.uop.lrs1 connect issue_slots[6].uop.ldst, slots_6.io.uop.ldst connect issue_slots[6].uop.ldst_is_rs1, slots_6.io.uop.ldst_is_rs1 connect issue_slots[6].uop.flush_on_commit, slots_6.io.uop.flush_on_commit connect issue_slots[6].uop.is_unique, slots_6.io.uop.is_unique connect issue_slots[6].uop.is_sys_pc2epc, slots_6.io.uop.is_sys_pc2epc connect issue_slots[6].uop.uses_stq, slots_6.io.uop.uses_stq connect issue_slots[6].uop.uses_ldq, slots_6.io.uop.uses_ldq connect issue_slots[6].uop.is_amo, slots_6.io.uop.is_amo connect issue_slots[6].uop.is_fencei, slots_6.io.uop.is_fencei connect issue_slots[6].uop.is_fence, slots_6.io.uop.is_fence connect issue_slots[6].uop.mem_signed, slots_6.io.uop.mem_signed connect issue_slots[6].uop.mem_size, slots_6.io.uop.mem_size connect issue_slots[6].uop.mem_cmd, slots_6.io.uop.mem_cmd connect issue_slots[6].uop.bypassable, slots_6.io.uop.bypassable connect issue_slots[6].uop.exc_cause, slots_6.io.uop.exc_cause connect issue_slots[6].uop.exception, slots_6.io.uop.exception connect issue_slots[6].uop.stale_pdst, slots_6.io.uop.stale_pdst connect issue_slots[6].uop.ppred_busy, slots_6.io.uop.ppred_busy connect issue_slots[6].uop.prs3_busy, slots_6.io.uop.prs3_busy connect issue_slots[6].uop.prs2_busy, slots_6.io.uop.prs2_busy connect issue_slots[6].uop.prs1_busy, slots_6.io.uop.prs1_busy connect issue_slots[6].uop.ppred, slots_6.io.uop.ppred connect issue_slots[6].uop.prs3, slots_6.io.uop.prs3 connect issue_slots[6].uop.prs2, slots_6.io.uop.prs2 connect issue_slots[6].uop.prs1, slots_6.io.uop.prs1 connect issue_slots[6].uop.pdst, slots_6.io.uop.pdst connect issue_slots[6].uop.rxq_idx, slots_6.io.uop.rxq_idx connect issue_slots[6].uop.stq_idx, slots_6.io.uop.stq_idx connect issue_slots[6].uop.ldq_idx, slots_6.io.uop.ldq_idx connect issue_slots[6].uop.rob_idx, slots_6.io.uop.rob_idx connect issue_slots[6].uop.csr_addr, slots_6.io.uop.csr_addr connect issue_slots[6].uop.imm_packed, slots_6.io.uop.imm_packed connect issue_slots[6].uop.taken, slots_6.io.uop.taken connect issue_slots[6].uop.pc_lob, slots_6.io.uop.pc_lob connect issue_slots[6].uop.edge_inst, slots_6.io.uop.edge_inst connect issue_slots[6].uop.ftq_idx, slots_6.io.uop.ftq_idx connect issue_slots[6].uop.br_tag, slots_6.io.uop.br_tag connect issue_slots[6].uop.br_mask, slots_6.io.uop.br_mask connect issue_slots[6].uop.is_sfb, slots_6.io.uop.is_sfb connect issue_slots[6].uop.is_jal, slots_6.io.uop.is_jal connect issue_slots[6].uop.is_jalr, slots_6.io.uop.is_jalr connect issue_slots[6].uop.is_br, slots_6.io.uop.is_br connect issue_slots[6].uop.iw_p2_poisoned, slots_6.io.uop.iw_p2_poisoned connect issue_slots[6].uop.iw_p1_poisoned, slots_6.io.uop.iw_p1_poisoned connect issue_slots[6].uop.iw_state, slots_6.io.uop.iw_state connect issue_slots[6].uop.ctrl.is_std, slots_6.io.uop.ctrl.is_std connect issue_slots[6].uop.ctrl.is_sta, slots_6.io.uop.ctrl.is_sta connect issue_slots[6].uop.ctrl.is_load, slots_6.io.uop.ctrl.is_load connect issue_slots[6].uop.ctrl.csr_cmd, slots_6.io.uop.ctrl.csr_cmd connect issue_slots[6].uop.ctrl.fcn_dw, slots_6.io.uop.ctrl.fcn_dw connect issue_slots[6].uop.ctrl.op_fcn, slots_6.io.uop.ctrl.op_fcn connect issue_slots[6].uop.ctrl.imm_sel, slots_6.io.uop.ctrl.imm_sel connect issue_slots[6].uop.ctrl.op2_sel, slots_6.io.uop.ctrl.op2_sel connect issue_slots[6].uop.ctrl.op1_sel, slots_6.io.uop.ctrl.op1_sel connect issue_slots[6].uop.ctrl.br_type, slots_6.io.uop.ctrl.br_type connect issue_slots[6].uop.fu_code, slots_6.io.uop.fu_code connect issue_slots[6].uop.iq_type, slots_6.io.uop.iq_type connect issue_slots[6].uop.debug_pc, slots_6.io.uop.debug_pc connect issue_slots[6].uop.is_rvc, slots_6.io.uop.is_rvc connect issue_slots[6].uop.debug_inst, slots_6.io.uop.debug_inst connect issue_slots[6].uop.inst, slots_6.io.uop.inst connect issue_slots[6].uop.uopc, slots_6.io.uop.uopc connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if connect issue_slots[6].out_uop.fp_single, slots_6.io.out_uop.fp_single connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype connect issue_slots[6].out_uop.ldst_val, slots_6.io.out_uop.ldst_val connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd connect issue_slots[6].out_uop.bypassable, slots_6.io.out_uop.bypassable connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx connect issue_slots[6].out_uop.csr_addr, slots_6.io.out_uop.csr_addr connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb connect issue_slots[6].out_uop.is_jal, slots_6.io.out_uop.is_jal connect issue_slots[6].out_uop.is_jalr, slots_6.io.out_uop.is_jalr connect issue_slots[6].out_uop.is_br, slots_6.io.out_uop.is_br connect issue_slots[6].out_uop.iw_p2_poisoned, slots_6.io.out_uop.iw_p2_poisoned connect issue_slots[6].out_uop.iw_p1_poisoned, slots_6.io.out_uop.iw_p1_poisoned connect issue_slots[6].out_uop.iw_state, slots_6.io.out_uop.iw_state connect issue_slots[6].out_uop.ctrl.is_std, slots_6.io.out_uop.ctrl.is_std connect issue_slots[6].out_uop.ctrl.is_sta, slots_6.io.out_uop.ctrl.is_sta connect issue_slots[6].out_uop.ctrl.is_load, slots_6.io.out_uop.ctrl.is_load connect issue_slots[6].out_uop.ctrl.csr_cmd, slots_6.io.out_uop.ctrl.csr_cmd connect issue_slots[6].out_uop.ctrl.fcn_dw, slots_6.io.out_uop.ctrl.fcn_dw connect issue_slots[6].out_uop.ctrl.op_fcn, slots_6.io.out_uop.ctrl.op_fcn connect issue_slots[6].out_uop.ctrl.imm_sel, slots_6.io.out_uop.ctrl.imm_sel connect issue_slots[6].out_uop.ctrl.op2_sel, slots_6.io.out_uop.ctrl.op2_sel connect issue_slots[6].out_uop.ctrl.op1_sel, slots_6.io.out_uop.ctrl.op1_sel connect issue_slots[6].out_uop.ctrl.br_type, slots_6.io.out_uop.ctrl.br_type connect issue_slots[6].out_uop.fu_code, slots_6.io.out_uop.fu_code connect issue_slots[6].out_uop.iq_type, slots_6.io.out_uop.iq_type connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst connect issue_slots[6].out_uop.uopc, slots_6.io.out_uop.uopc connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if connect slots_6.io.in_uop.bits.fp_single, issue_slots[6].in_uop.bits.fp_single connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype connect slots_6.io.in_uop.bits.ldst_val, issue_slots[6].in_uop.bits.ldst_val connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd connect slots_6.io.in_uop.bits.bypassable, issue_slots[6].in_uop.bits.bypassable connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx connect slots_6.io.in_uop.bits.csr_addr, issue_slots[6].in_uop.bits.csr_addr connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb connect slots_6.io.in_uop.bits.is_jal, issue_slots[6].in_uop.bits.is_jal connect slots_6.io.in_uop.bits.is_jalr, issue_slots[6].in_uop.bits.is_jalr connect slots_6.io.in_uop.bits.is_br, issue_slots[6].in_uop.bits.is_br connect slots_6.io.in_uop.bits.iw_p2_poisoned, issue_slots[6].in_uop.bits.iw_p2_poisoned connect slots_6.io.in_uop.bits.iw_p1_poisoned, issue_slots[6].in_uop.bits.iw_p1_poisoned connect slots_6.io.in_uop.bits.iw_state, issue_slots[6].in_uop.bits.iw_state connect slots_6.io.in_uop.bits.ctrl.is_std, issue_slots[6].in_uop.bits.ctrl.is_std connect slots_6.io.in_uop.bits.ctrl.is_sta, issue_slots[6].in_uop.bits.ctrl.is_sta connect slots_6.io.in_uop.bits.ctrl.is_load, issue_slots[6].in_uop.bits.ctrl.is_load connect slots_6.io.in_uop.bits.ctrl.csr_cmd, issue_slots[6].in_uop.bits.ctrl.csr_cmd connect slots_6.io.in_uop.bits.ctrl.fcn_dw, issue_slots[6].in_uop.bits.ctrl.fcn_dw connect slots_6.io.in_uop.bits.ctrl.op_fcn, issue_slots[6].in_uop.bits.ctrl.op_fcn connect slots_6.io.in_uop.bits.ctrl.imm_sel, issue_slots[6].in_uop.bits.ctrl.imm_sel connect slots_6.io.in_uop.bits.ctrl.op2_sel, issue_slots[6].in_uop.bits.ctrl.op2_sel connect slots_6.io.in_uop.bits.ctrl.op1_sel, issue_slots[6].in_uop.bits.ctrl.op1_sel connect slots_6.io.in_uop.bits.ctrl.br_type, issue_slots[6].in_uop.bits.ctrl.br_type connect slots_6.io.in_uop.bits.fu_code, issue_slots[6].in_uop.bits.fu_code connect slots_6.io.in_uop.bits.iq_type, issue_slots[6].in_uop.bits.iq_type connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst connect slots_6.io.in_uop.bits.uopc, issue_slots[6].in_uop.bits.uopc connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid connect slots_6.io.spec_ld_wakeup[0].bits, issue_slots[6].spec_ld_wakeup[0].bits connect slots_6.io.spec_ld_wakeup[0].valid, issue_slots[6].spec_ld_wakeup[0].valid connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid connect slots_6.io.wakeup_ports[0].bits.poisoned, issue_slots[6].wakeup_ports[0].bits.poisoned connect slots_6.io.wakeup_ports[0].bits.pdst, issue_slots[6].wakeup_ports[0].bits.pdst connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid connect slots_6.io.wakeup_ports[1].bits.poisoned, issue_slots[6].wakeup_ports[1].bits.poisoned connect slots_6.io.wakeup_ports[1].bits.pdst, issue_slots[6].wakeup_ports[1].bits.pdst connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid connect slots_6.io.wakeup_ports[2].bits.poisoned, issue_slots[6].wakeup_ports[2].bits.poisoned connect slots_6.io.wakeup_ports[2].bits.pdst, issue_slots[6].wakeup_ports[2].bits.pdst connect slots_6.io.wakeup_ports[2].valid, issue_slots[6].wakeup_ports[2].valid connect slots_6.io.wakeup_ports[3].bits.poisoned, issue_slots[6].wakeup_ports[3].bits.poisoned connect slots_6.io.wakeup_ports[3].bits.pdst, issue_slots[6].wakeup_ports[3].bits.pdst connect slots_6.io.wakeup_ports[3].valid, issue_slots[6].wakeup_ports[3].valid connect slots_6.io.wakeup_ports[4].bits.poisoned, issue_slots[6].wakeup_ports[4].bits.poisoned connect slots_6.io.wakeup_ports[4].bits.pdst, issue_slots[6].wakeup_ports[4].bits.pdst connect slots_6.io.wakeup_ports[4].valid, issue_slots[6].wakeup_ports[4].valid connect slots_6.io.wakeup_ports[5].bits.poisoned, issue_slots[6].wakeup_ports[5].bits.poisoned connect slots_6.io.wakeup_ports[5].bits.pdst, issue_slots[6].wakeup_ports[5].bits.pdst connect slots_6.io.wakeup_ports[5].valid, issue_slots[6].wakeup_ports[5].valid connect slots_6.io.wakeup_ports[6].bits.poisoned, issue_slots[6].wakeup_ports[6].bits.poisoned connect slots_6.io.wakeup_ports[6].bits.pdst, issue_slots[6].wakeup_ports[6].bits.pdst connect slots_6.io.wakeup_ports[6].valid, issue_slots[6].wakeup_ports[6].valid connect slots_6.io.ldspec_miss, issue_slots[6].ldspec_miss connect slots_6.io.clear, issue_slots[6].clear connect slots_6.io.kill, issue_slots[6].kill connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict connect slots_6.io.brupdate.b2.valid, issue_slots[6].brupdate.b2.valid connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if connect slots_6.io.brupdate.b2.uop.fp_single, issue_slots[6].brupdate.b2.uop.fp_single connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype connect slots_6.io.brupdate.b2.uop.ldst_val, issue_slots[6].brupdate.b2.uop.ldst_val connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd connect slots_6.io.brupdate.b2.uop.bypassable, issue_slots[6].brupdate.b2.uop.bypassable connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx connect slots_6.io.brupdate.b2.uop.csr_addr, issue_slots[6].brupdate.b2.uop.csr_addr connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb connect slots_6.io.brupdate.b2.uop.is_jal, issue_slots[6].brupdate.b2.uop.is_jal connect slots_6.io.brupdate.b2.uop.is_jalr, issue_slots[6].brupdate.b2.uop.is_jalr connect slots_6.io.brupdate.b2.uop.is_br, issue_slots[6].brupdate.b2.uop.is_br connect slots_6.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[6].brupdate.b2.uop.iw_p2_poisoned connect slots_6.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[6].brupdate.b2.uop.iw_p1_poisoned connect slots_6.io.brupdate.b2.uop.iw_state, issue_slots[6].brupdate.b2.uop.iw_state connect slots_6.io.brupdate.b2.uop.ctrl.is_std, issue_slots[6].brupdate.b2.uop.ctrl.is_std connect slots_6.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[6].brupdate.b2.uop.ctrl.is_sta connect slots_6.io.brupdate.b2.uop.ctrl.is_load, issue_slots[6].brupdate.b2.uop.ctrl.is_load connect slots_6.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd connect slots_6.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw connect slots_6.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[6].brupdate.b2.uop.ctrl.op_fcn connect slots_6.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[6].brupdate.b2.uop.ctrl.imm_sel connect slots_6.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[6].brupdate.b2.uop.ctrl.op2_sel connect slots_6.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[6].brupdate.b2.uop.ctrl.op1_sel connect slots_6.io.brupdate.b2.uop.ctrl.br_type, issue_slots[6].brupdate.b2.uop.ctrl.br_type connect slots_6.io.brupdate.b2.uop.fu_code, issue_slots[6].brupdate.b2.uop.fu_code connect slots_6.io.brupdate.b2.uop.iq_type, issue_slots[6].brupdate.b2.uop.iq_type connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst connect slots_6.io.brupdate.b2.uop.uopc, issue_slots[6].brupdate.b2.uop.uopc connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask connect slots_6.io.grant, issue_slots[6].grant connect issue_slots[6].request_hp, slots_6.io.request_hp connect issue_slots[6].request, slots_6.io.request connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid connect issue_slots[6].valid, slots_6.io.valid connect issue_slots[7].debug.state, slots_7.io.debug.state connect issue_slots[7].debug.ppred, slots_7.io.debug.ppred connect issue_slots[7].debug.p3, slots_7.io.debug.p3 connect issue_slots[7].debug.p2, slots_7.io.debug.p2 connect issue_slots[7].debug.p1, slots_7.io.debug.p1 connect issue_slots[7].uop.debug_tsrc, slots_7.io.uop.debug_tsrc connect issue_slots[7].uop.debug_fsrc, slots_7.io.uop.debug_fsrc connect issue_slots[7].uop.bp_xcpt_if, slots_7.io.uop.bp_xcpt_if connect issue_slots[7].uop.bp_debug_if, slots_7.io.uop.bp_debug_if connect issue_slots[7].uop.xcpt_ma_if, slots_7.io.uop.xcpt_ma_if connect issue_slots[7].uop.xcpt_ae_if, slots_7.io.uop.xcpt_ae_if connect issue_slots[7].uop.xcpt_pf_if, slots_7.io.uop.xcpt_pf_if connect issue_slots[7].uop.fp_single, slots_7.io.uop.fp_single connect issue_slots[7].uop.fp_val, slots_7.io.uop.fp_val connect issue_slots[7].uop.frs3_en, slots_7.io.uop.frs3_en connect issue_slots[7].uop.lrs2_rtype, slots_7.io.uop.lrs2_rtype connect issue_slots[7].uop.lrs1_rtype, slots_7.io.uop.lrs1_rtype connect issue_slots[7].uop.dst_rtype, slots_7.io.uop.dst_rtype connect issue_slots[7].uop.ldst_val, slots_7.io.uop.ldst_val connect issue_slots[7].uop.lrs3, slots_7.io.uop.lrs3 connect issue_slots[7].uop.lrs2, slots_7.io.uop.lrs2 connect issue_slots[7].uop.lrs1, slots_7.io.uop.lrs1 connect issue_slots[7].uop.ldst, slots_7.io.uop.ldst connect issue_slots[7].uop.ldst_is_rs1, slots_7.io.uop.ldst_is_rs1 connect issue_slots[7].uop.flush_on_commit, slots_7.io.uop.flush_on_commit connect issue_slots[7].uop.is_unique, slots_7.io.uop.is_unique connect issue_slots[7].uop.is_sys_pc2epc, slots_7.io.uop.is_sys_pc2epc connect issue_slots[7].uop.uses_stq, slots_7.io.uop.uses_stq connect issue_slots[7].uop.uses_ldq, slots_7.io.uop.uses_ldq connect issue_slots[7].uop.is_amo, slots_7.io.uop.is_amo connect issue_slots[7].uop.is_fencei, slots_7.io.uop.is_fencei connect issue_slots[7].uop.is_fence, slots_7.io.uop.is_fence connect issue_slots[7].uop.mem_signed, slots_7.io.uop.mem_signed connect issue_slots[7].uop.mem_size, slots_7.io.uop.mem_size connect issue_slots[7].uop.mem_cmd, slots_7.io.uop.mem_cmd connect issue_slots[7].uop.bypassable, slots_7.io.uop.bypassable connect issue_slots[7].uop.exc_cause, slots_7.io.uop.exc_cause connect issue_slots[7].uop.exception, slots_7.io.uop.exception connect issue_slots[7].uop.stale_pdst, slots_7.io.uop.stale_pdst connect issue_slots[7].uop.ppred_busy, slots_7.io.uop.ppred_busy connect issue_slots[7].uop.prs3_busy, slots_7.io.uop.prs3_busy connect issue_slots[7].uop.prs2_busy, slots_7.io.uop.prs2_busy connect issue_slots[7].uop.prs1_busy, slots_7.io.uop.prs1_busy connect issue_slots[7].uop.ppred, slots_7.io.uop.ppred connect issue_slots[7].uop.prs3, slots_7.io.uop.prs3 connect issue_slots[7].uop.prs2, slots_7.io.uop.prs2 connect issue_slots[7].uop.prs1, slots_7.io.uop.prs1 connect issue_slots[7].uop.pdst, slots_7.io.uop.pdst connect issue_slots[7].uop.rxq_idx, slots_7.io.uop.rxq_idx connect issue_slots[7].uop.stq_idx, slots_7.io.uop.stq_idx connect issue_slots[7].uop.ldq_idx, slots_7.io.uop.ldq_idx connect issue_slots[7].uop.rob_idx, slots_7.io.uop.rob_idx connect issue_slots[7].uop.csr_addr, slots_7.io.uop.csr_addr connect issue_slots[7].uop.imm_packed, slots_7.io.uop.imm_packed connect issue_slots[7].uop.taken, slots_7.io.uop.taken connect issue_slots[7].uop.pc_lob, slots_7.io.uop.pc_lob connect issue_slots[7].uop.edge_inst, slots_7.io.uop.edge_inst connect issue_slots[7].uop.ftq_idx, slots_7.io.uop.ftq_idx connect issue_slots[7].uop.br_tag, slots_7.io.uop.br_tag connect issue_slots[7].uop.br_mask, slots_7.io.uop.br_mask connect issue_slots[7].uop.is_sfb, slots_7.io.uop.is_sfb connect issue_slots[7].uop.is_jal, slots_7.io.uop.is_jal connect issue_slots[7].uop.is_jalr, slots_7.io.uop.is_jalr connect issue_slots[7].uop.is_br, slots_7.io.uop.is_br connect issue_slots[7].uop.iw_p2_poisoned, slots_7.io.uop.iw_p2_poisoned connect issue_slots[7].uop.iw_p1_poisoned, slots_7.io.uop.iw_p1_poisoned connect issue_slots[7].uop.iw_state, slots_7.io.uop.iw_state connect issue_slots[7].uop.ctrl.is_std, slots_7.io.uop.ctrl.is_std connect issue_slots[7].uop.ctrl.is_sta, slots_7.io.uop.ctrl.is_sta connect issue_slots[7].uop.ctrl.is_load, slots_7.io.uop.ctrl.is_load connect issue_slots[7].uop.ctrl.csr_cmd, slots_7.io.uop.ctrl.csr_cmd connect issue_slots[7].uop.ctrl.fcn_dw, slots_7.io.uop.ctrl.fcn_dw connect issue_slots[7].uop.ctrl.op_fcn, slots_7.io.uop.ctrl.op_fcn connect issue_slots[7].uop.ctrl.imm_sel, slots_7.io.uop.ctrl.imm_sel connect issue_slots[7].uop.ctrl.op2_sel, slots_7.io.uop.ctrl.op2_sel connect issue_slots[7].uop.ctrl.op1_sel, slots_7.io.uop.ctrl.op1_sel connect issue_slots[7].uop.ctrl.br_type, slots_7.io.uop.ctrl.br_type connect issue_slots[7].uop.fu_code, slots_7.io.uop.fu_code connect issue_slots[7].uop.iq_type, slots_7.io.uop.iq_type connect issue_slots[7].uop.debug_pc, slots_7.io.uop.debug_pc connect issue_slots[7].uop.is_rvc, slots_7.io.uop.is_rvc connect issue_slots[7].uop.debug_inst, slots_7.io.uop.debug_inst connect issue_slots[7].uop.inst, slots_7.io.uop.inst connect issue_slots[7].uop.uopc, slots_7.io.uop.uopc connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if connect issue_slots[7].out_uop.fp_single, slots_7.io.out_uop.fp_single connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype connect issue_slots[7].out_uop.ldst_val, slots_7.io.out_uop.ldst_val connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd connect issue_slots[7].out_uop.bypassable, slots_7.io.out_uop.bypassable connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx connect issue_slots[7].out_uop.csr_addr, slots_7.io.out_uop.csr_addr connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb connect issue_slots[7].out_uop.is_jal, slots_7.io.out_uop.is_jal connect issue_slots[7].out_uop.is_jalr, slots_7.io.out_uop.is_jalr connect issue_slots[7].out_uop.is_br, slots_7.io.out_uop.is_br connect issue_slots[7].out_uop.iw_p2_poisoned, slots_7.io.out_uop.iw_p2_poisoned connect issue_slots[7].out_uop.iw_p1_poisoned, slots_7.io.out_uop.iw_p1_poisoned connect issue_slots[7].out_uop.iw_state, slots_7.io.out_uop.iw_state connect issue_slots[7].out_uop.ctrl.is_std, slots_7.io.out_uop.ctrl.is_std connect issue_slots[7].out_uop.ctrl.is_sta, slots_7.io.out_uop.ctrl.is_sta connect issue_slots[7].out_uop.ctrl.is_load, slots_7.io.out_uop.ctrl.is_load connect issue_slots[7].out_uop.ctrl.csr_cmd, slots_7.io.out_uop.ctrl.csr_cmd connect issue_slots[7].out_uop.ctrl.fcn_dw, slots_7.io.out_uop.ctrl.fcn_dw connect issue_slots[7].out_uop.ctrl.op_fcn, slots_7.io.out_uop.ctrl.op_fcn connect issue_slots[7].out_uop.ctrl.imm_sel, slots_7.io.out_uop.ctrl.imm_sel connect issue_slots[7].out_uop.ctrl.op2_sel, slots_7.io.out_uop.ctrl.op2_sel connect issue_slots[7].out_uop.ctrl.op1_sel, slots_7.io.out_uop.ctrl.op1_sel connect issue_slots[7].out_uop.ctrl.br_type, slots_7.io.out_uop.ctrl.br_type connect issue_slots[7].out_uop.fu_code, slots_7.io.out_uop.fu_code connect issue_slots[7].out_uop.iq_type, slots_7.io.out_uop.iq_type connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst connect issue_slots[7].out_uop.uopc, slots_7.io.out_uop.uopc connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if connect slots_7.io.in_uop.bits.fp_single, issue_slots[7].in_uop.bits.fp_single connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype connect slots_7.io.in_uop.bits.ldst_val, issue_slots[7].in_uop.bits.ldst_val connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd connect slots_7.io.in_uop.bits.bypassable, issue_slots[7].in_uop.bits.bypassable connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx connect slots_7.io.in_uop.bits.csr_addr, issue_slots[7].in_uop.bits.csr_addr connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb connect slots_7.io.in_uop.bits.is_jal, issue_slots[7].in_uop.bits.is_jal connect slots_7.io.in_uop.bits.is_jalr, issue_slots[7].in_uop.bits.is_jalr connect slots_7.io.in_uop.bits.is_br, issue_slots[7].in_uop.bits.is_br connect slots_7.io.in_uop.bits.iw_p2_poisoned, issue_slots[7].in_uop.bits.iw_p2_poisoned connect slots_7.io.in_uop.bits.iw_p1_poisoned, issue_slots[7].in_uop.bits.iw_p1_poisoned connect slots_7.io.in_uop.bits.iw_state, issue_slots[7].in_uop.bits.iw_state connect slots_7.io.in_uop.bits.ctrl.is_std, issue_slots[7].in_uop.bits.ctrl.is_std connect slots_7.io.in_uop.bits.ctrl.is_sta, issue_slots[7].in_uop.bits.ctrl.is_sta connect slots_7.io.in_uop.bits.ctrl.is_load, issue_slots[7].in_uop.bits.ctrl.is_load connect slots_7.io.in_uop.bits.ctrl.csr_cmd, issue_slots[7].in_uop.bits.ctrl.csr_cmd connect slots_7.io.in_uop.bits.ctrl.fcn_dw, issue_slots[7].in_uop.bits.ctrl.fcn_dw connect slots_7.io.in_uop.bits.ctrl.op_fcn, issue_slots[7].in_uop.bits.ctrl.op_fcn connect slots_7.io.in_uop.bits.ctrl.imm_sel, issue_slots[7].in_uop.bits.ctrl.imm_sel connect slots_7.io.in_uop.bits.ctrl.op2_sel, issue_slots[7].in_uop.bits.ctrl.op2_sel connect slots_7.io.in_uop.bits.ctrl.op1_sel, issue_slots[7].in_uop.bits.ctrl.op1_sel connect slots_7.io.in_uop.bits.ctrl.br_type, issue_slots[7].in_uop.bits.ctrl.br_type connect slots_7.io.in_uop.bits.fu_code, issue_slots[7].in_uop.bits.fu_code connect slots_7.io.in_uop.bits.iq_type, issue_slots[7].in_uop.bits.iq_type connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst connect slots_7.io.in_uop.bits.uopc, issue_slots[7].in_uop.bits.uopc connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid connect slots_7.io.spec_ld_wakeup[0].bits, issue_slots[7].spec_ld_wakeup[0].bits connect slots_7.io.spec_ld_wakeup[0].valid, issue_slots[7].spec_ld_wakeup[0].valid connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid connect slots_7.io.wakeup_ports[0].bits.poisoned, issue_slots[7].wakeup_ports[0].bits.poisoned connect slots_7.io.wakeup_ports[0].bits.pdst, issue_slots[7].wakeup_ports[0].bits.pdst connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid connect slots_7.io.wakeup_ports[1].bits.poisoned, issue_slots[7].wakeup_ports[1].bits.poisoned connect slots_7.io.wakeup_ports[1].bits.pdst, issue_slots[7].wakeup_ports[1].bits.pdst connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid connect slots_7.io.wakeup_ports[2].bits.poisoned, issue_slots[7].wakeup_ports[2].bits.poisoned connect slots_7.io.wakeup_ports[2].bits.pdst, issue_slots[7].wakeup_ports[2].bits.pdst connect slots_7.io.wakeup_ports[2].valid, issue_slots[7].wakeup_ports[2].valid connect slots_7.io.wakeup_ports[3].bits.poisoned, issue_slots[7].wakeup_ports[3].bits.poisoned connect slots_7.io.wakeup_ports[3].bits.pdst, issue_slots[7].wakeup_ports[3].bits.pdst connect slots_7.io.wakeup_ports[3].valid, issue_slots[7].wakeup_ports[3].valid connect slots_7.io.wakeup_ports[4].bits.poisoned, issue_slots[7].wakeup_ports[4].bits.poisoned connect slots_7.io.wakeup_ports[4].bits.pdst, issue_slots[7].wakeup_ports[4].bits.pdst connect slots_7.io.wakeup_ports[4].valid, issue_slots[7].wakeup_ports[4].valid connect slots_7.io.wakeup_ports[5].bits.poisoned, issue_slots[7].wakeup_ports[5].bits.poisoned connect slots_7.io.wakeup_ports[5].bits.pdst, issue_slots[7].wakeup_ports[5].bits.pdst connect slots_7.io.wakeup_ports[5].valid, issue_slots[7].wakeup_ports[5].valid connect slots_7.io.wakeup_ports[6].bits.poisoned, issue_slots[7].wakeup_ports[6].bits.poisoned connect slots_7.io.wakeup_ports[6].bits.pdst, issue_slots[7].wakeup_ports[6].bits.pdst connect slots_7.io.wakeup_ports[6].valid, issue_slots[7].wakeup_ports[6].valid connect slots_7.io.ldspec_miss, issue_slots[7].ldspec_miss connect slots_7.io.clear, issue_slots[7].clear connect slots_7.io.kill, issue_slots[7].kill connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict connect slots_7.io.brupdate.b2.valid, issue_slots[7].brupdate.b2.valid connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if connect slots_7.io.brupdate.b2.uop.fp_single, issue_slots[7].brupdate.b2.uop.fp_single connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype connect slots_7.io.brupdate.b2.uop.ldst_val, issue_slots[7].brupdate.b2.uop.ldst_val connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd connect slots_7.io.brupdate.b2.uop.bypassable, issue_slots[7].brupdate.b2.uop.bypassable connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx connect slots_7.io.brupdate.b2.uop.csr_addr, issue_slots[7].brupdate.b2.uop.csr_addr connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb connect slots_7.io.brupdate.b2.uop.is_jal, issue_slots[7].brupdate.b2.uop.is_jal connect slots_7.io.brupdate.b2.uop.is_jalr, issue_slots[7].brupdate.b2.uop.is_jalr connect slots_7.io.brupdate.b2.uop.is_br, issue_slots[7].brupdate.b2.uop.is_br connect slots_7.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[7].brupdate.b2.uop.iw_p2_poisoned connect slots_7.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[7].brupdate.b2.uop.iw_p1_poisoned connect slots_7.io.brupdate.b2.uop.iw_state, issue_slots[7].brupdate.b2.uop.iw_state connect slots_7.io.brupdate.b2.uop.ctrl.is_std, issue_slots[7].brupdate.b2.uop.ctrl.is_std connect slots_7.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[7].brupdate.b2.uop.ctrl.is_sta connect slots_7.io.brupdate.b2.uop.ctrl.is_load, issue_slots[7].brupdate.b2.uop.ctrl.is_load connect slots_7.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd connect slots_7.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw connect slots_7.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[7].brupdate.b2.uop.ctrl.op_fcn connect slots_7.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[7].brupdate.b2.uop.ctrl.imm_sel connect slots_7.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[7].brupdate.b2.uop.ctrl.op2_sel connect slots_7.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[7].brupdate.b2.uop.ctrl.op1_sel connect slots_7.io.brupdate.b2.uop.ctrl.br_type, issue_slots[7].brupdate.b2.uop.ctrl.br_type connect slots_7.io.brupdate.b2.uop.fu_code, issue_slots[7].brupdate.b2.uop.fu_code connect slots_7.io.brupdate.b2.uop.iq_type, issue_slots[7].brupdate.b2.uop.iq_type connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst connect slots_7.io.brupdate.b2.uop.uopc, issue_slots[7].brupdate.b2.uop.uopc connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask connect slots_7.io.grant, issue_slots[7].grant connect issue_slots[7].request_hp, slots_7.io.request_hp connect issue_slots[7].request, slots_7.io.request connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid connect issue_slots[7].valid, slots_7.io.valid connect issue_slots[8].debug.state, slots_8.io.debug.state connect issue_slots[8].debug.ppred, slots_8.io.debug.ppred connect issue_slots[8].debug.p3, slots_8.io.debug.p3 connect issue_slots[8].debug.p2, slots_8.io.debug.p2 connect issue_slots[8].debug.p1, slots_8.io.debug.p1 connect issue_slots[8].uop.debug_tsrc, slots_8.io.uop.debug_tsrc connect issue_slots[8].uop.debug_fsrc, slots_8.io.uop.debug_fsrc connect issue_slots[8].uop.bp_xcpt_if, slots_8.io.uop.bp_xcpt_if connect issue_slots[8].uop.bp_debug_if, slots_8.io.uop.bp_debug_if connect issue_slots[8].uop.xcpt_ma_if, slots_8.io.uop.xcpt_ma_if connect issue_slots[8].uop.xcpt_ae_if, slots_8.io.uop.xcpt_ae_if connect issue_slots[8].uop.xcpt_pf_if, slots_8.io.uop.xcpt_pf_if connect issue_slots[8].uop.fp_single, slots_8.io.uop.fp_single connect issue_slots[8].uop.fp_val, slots_8.io.uop.fp_val connect issue_slots[8].uop.frs3_en, slots_8.io.uop.frs3_en connect issue_slots[8].uop.lrs2_rtype, slots_8.io.uop.lrs2_rtype connect issue_slots[8].uop.lrs1_rtype, slots_8.io.uop.lrs1_rtype connect issue_slots[8].uop.dst_rtype, slots_8.io.uop.dst_rtype connect issue_slots[8].uop.ldst_val, slots_8.io.uop.ldst_val connect issue_slots[8].uop.lrs3, slots_8.io.uop.lrs3 connect issue_slots[8].uop.lrs2, slots_8.io.uop.lrs2 connect issue_slots[8].uop.lrs1, slots_8.io.uop.lrs1 connect issue_slots[8].uop.ldst, slots_8.io.uop.ldst connect issue_slots[8].uop.ldst_is_rs1, slots_8.io.uop.ldst_is_rs1 connect issue_slots[8].uop.flush_on_commit, slots_8.io.uop.flush_on_commit connect issue_slots[8].uop.is_unique, slots_8.io.uop.is_unique connect issue_slots[8].uop.is_sys_pc2epc, slots_8.io.uop.is_sys_pc2epc connect issue_slots[8].uop.uses_stq, slots_8.io.uop.uses_stq connect issue_slots[8].uop.uses_ldq, slots_8.io.uop.uses_ldq connect issue_slots[8].uop.is_amo, slots_8.io.uop.is_amo connect issue_slots[8].uop.is_fencei, slots_8.io.uop.is_fencei connect issue_slots[8].uop.is_fence, slots_8.io.uop.is_fence connect issue_slots[8].uop.mem_signed, slots_8.io.uop.mem_signed connect issue_slots[8].uop.mem_size, slots_8.io.uop.mem_size connect issue_slots[8].uop.mem_cmd, slots_8.io.uop.mem_cmd connect issue_slots[8].uop.bypassable, slots_8.io.uop.bypassable connect issue_slots[8].uop.exc_cause, slots_8.io.uop.exc_cause connect issue_slots[8].uop.exception, slots_8.io.uop.exception connect issue_slots[8].uop.stale_pdst, slots_8.io.uop.stale_pdst connect issue_slots[8].uop.ppred_busy, slots_8.io.uop.ppred_busy connect issue_slots[8].uop.prs3_busy, slots_8.io.uop.prs3_busy connect issue_slots[8].uop.prs2_busy, slots_8.io.uop.prs2_busy connect issue_slots[8].uop.prs1_busy, slots_8.io.uop.prs1_busy connect issue_slots[8].uop.ppred, slots_8.io.uop.ppred connect issue_slots[8].uop.prs3, slots_8.io.uop.prs3 connect issue_slots[8].uop.prs2, slots_8.io.uop.prs2 connect issue_slots[8].uop.prs1, slots_8.io.uop.prs1 connect issue_slots[8].uop.pdst, slots_8.io.uop.pdst connect issue_slots[8].uop.rxq_idx, slots_8.io.uop.rxq_idx connect issue_slots[8].uop.stq_idx, slots_8.io.uop.stq_idx connect issue_slots[8].uop.ldq_idx, slots_8.io.uop.ldq_idx connect issue_slots[8].uop.rob_idx, slots_8.io.uop.rob_idx connect issue_slots[8].uop.csr_addr, slots_8.io.uop.csr_addr connect issue_slots[8].uop.imm_packed, slots_8.io.uop.imm_packed connect issue_slots[8].uop.taken, slots_8.io.uop.taken connect issue_slots[8].uop.pc_lob, slots_8.io.uop.pc_lob connect issue_slots[8].uop.edge_inst, slots_8.io.uop.edge_inst connect issue_slots[8].uop.ftq_idx, slots_8.io.uop.ftq_idx connect issue_slots[8].uop.br_tag, slots_8.io.uop.br_tag connect issue_slots[8].uop.br_mask, slots_8.io.uop.br_mask connect issue_slots[8].uop.is_sfb, slots_8.io.uop.is_sfb connect issue_slots[8].uop.is_jal, slots_8.io.uop.is_jal connect issue_slots[8].uop.is_jalr, slots_8.io.uop.is_jalr connect issue_slots[8].uop.is_br, slots_8.io.uop.is_br connect issue_slots[8].uop.iw_p2_poisoned, slots_8.io.uop.iw_p2_poisoned connect issue_slots[8].uop.iw_p1_poisoned, slots_8.io.uop.iw_p1_poisoned connect issue_slots[8].uop.iw_state, slots_8.io.uop.iw_state connect issue_slots[8].uop.ctrl.is_std, slots_8.io.uop.ctrl.is_std connect issue_slots[8].uop.ctrl.is_sta, slots_8.io.uop.ctrl.is_sta connect issue_slots[8].uop.ctrl.is_load, slots_8.io.uop.ctrl.is_load connect issue_slots[8].uop.ctrl.csr_cmd, slots_8.io.uop.ctrl.csr_cmd connect issue_slots[8].uop.ctrl.fcn_dw, slots_8.io.uop.ctrl.fcn_dw connect issue_slots[8].uop.ctrl.op_fcn, slots_8.io.uop.ctrl.op_fcn connect issue_slots[8].uop.ctrl.imm_sel, slots_8.io.uop.ctrl.imm_sel connect issue_slots[8].uop.ctrl.op2_sel, slots_8.io.uop.ctrl.op2_sel connect issue_slots[8].uop.ctrl.op1_sel, slots_8.io.uop.ctrl.op1_sel connect issue_slots[8].uop.ctrl.br_type, slots_8.io.uop.ctrl.br_type connect issue_slots[8].uop.fu_code, slots_8.io.uop.fu_code connect issue_slots[8].uop.iq_type, slots_8.io.uop.iq_type connect issue_slots[8].uop.debug_pc, slots_8.io.uop.debug_pc connect issue_slots[8].uop.is_rvc, slots_8.io.uop.is_rvc connect issue_slots[8].uop.debug_inst, slots_8.io.uop.debug_inst connect issue_slots[8].uop.inst, slots_8.io.uop.inst connect issue_slots[8].uop.uopc, slots_8.io.uop.uopc connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if connect issue_slots[8].out_uop.fp_single, slots_8.io.out_uop.fp_single connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype connect issue_slots[8].out_uop.ldst_val, slots_8.io.out_uop.ldst_val connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3 connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2 connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1 connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1 connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd connect issue_slots[8].out_uop.bypassable, slots_8.io.out_uop.bypassable connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3 connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2 connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1 connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx connect issue_slots[8].out_uop.csr_addr, slots_8.io.out_uop.csr_addr connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb connect issue_slots[8].out_uop.is_jal, slots_8.io.out_uop.is_jal connect issue_slots[8].out_uop.is_jalr, slots_8.io.out_uop.is_jalr connect issue_slots[8].out_uop.is_br, slots_8.io.out_uop.is_br connect issue_slots[8].out_uop.iw_p2_poisoned, slots_8.io.out_uop.iw_p2_poisoned connect issue_slots[8].out_uop.iw_p1_poisoned, slots_8.io.out_uop.iw_p1_poisoned connect issue_slots[8].out_uop.iw_state, slots_8.io.out_uop.iw_state connect issue_slots[8].out_uop.ctrl.is_std, slots_8.io.out_uop.ctrl.is_std connect issue_slots[8].out_uop.ctrl.is_sta, slots_8.io.out_uop.ctrl.is_sta connect issue_slots[8].out_uop.ctrl.is_load, slots_8.io.out_uop.ctrl.is_load connect issue_slots[8].out_uop.ctrl.csr_cmd, slots_8.io.out_uop.ctrl.csr_cmd connect issue_slots[8].out_uop.ctrl.fcn_dw, slots_8.io.out_uop.ctrl.fcn_dw connect issue_slots[8].out_uop.ctrl.op_fcn, slots_8.io.out_uop.ctrl.op_fcn connect issue_slots[8].out_uop.ctrl.imm_sel, slots_8.io.out_uop.ctrl.imm_sel connect issue_slots[8].out_uop.ctrl.op2_sel, slots_8.io.out_uop.ctrl.op2_sel connect issue_slots[8].out_uop.ctrl.op1_sel, slots_8.io.out_uop.ctrl.op1_sel connect issue_slots[8].out_uop.ctrl.br_type, slots_8.io.out_uop.ctrl.br_type connect issue_slots[8].out_uop.fu_code, slots_8.io.out_uop.fu_code connect issue_slots[8].out_uop.iq_type, slots_8.io.out_uop.iq_type connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst connect issue_slots[8].out_uop.uopc, slots_8.io.out_uop.uopc connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if connect slots_8.io.in_uop.bits.fp_single, issue_slots[8].in_uop.bits.fp_single connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype connect slots_8.io.in_uop.bits.ldst_val, issue_slots[8].in_uop.bits.ldst_val connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3 connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2 connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1 connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1 connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd connect slots_8.io.in_uop.bits.bypassable, issue_slots[8].in_uop.bits.bypassable connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3 connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2 connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1 connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx connect slots_8.io.in_uop.bits.csr_addr, issue_slots[8].in_uop.bits.csr_addr connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb connect slots_8.io.in_uop.bits.is_jal, issue_slots[8].in_uop.bits.is_jal connect slots_8.io.in_uop.bits.is_jalr, issue_slots[8].in_uop.bits.is_jalr connect slots_8.io.in_uop.bits.is_br, issue_slots[8].in_uop.bits.is_br connect slots_8.io.in_uop.bits.iw_p2_poisoned, issue_slots[8].in_uop.bits.iw_p2_poisoned connect slots_8.io.in_uop.bits.iw_p1_poisoned, issue_slots[8].in_uop.bits.iw_p1_poisoned connect slots_8.io.in_uop.bits.iw_state, issue_slots[8].in_uop.bits.iw_state connect slots_8.io.in_uop.bits.ctrl.is_std, issue_slots[8].in_uop.bits.ctrl.is_std connect slots_8.io.in_uop.bits.ctrl.is_sta, issue_slots[8].in_uop.bits.ctrl.is_sta connect slots_8.io.in_uop.bits.ctrl.is_load, issue_slots[8].in_uop.bits.ctrl.is_load connect slots_8.io.in_uop.bits.ctrl.csr_cmd, issue_slots[8].in_uop.bits.ctrl.csr_cmd connect slots_8.io.in_uop.bits.ctrl.fcn_dw, issue_slots[8].in_uop.bits.ctrl.fcn_dw connect slots_8.io.in_uop.bits.ctrl.op_fcn, issue_slots[8].in_uop.bits.ctrl.op_fcn connect slots_8.io.in_uop.bits.ctrl.imm_sel, issue_slots[8].in_uop.bits.ctrl.imm_sel connect slots_8.io.in_uop.bits.ctrl.op2_sel, issue_slots[8].in_uop.bits.ctrl.op2_sel connect slots_8.io.in_uop.bits.ctrl.op1_sel, issue_slots[8].in_uop.bits.ctrl.op1_sel connect slots_8.io.in_uop.bits.ctrl.br_type, issue_slots[8].in_uop.bits.ctrl.br_type connect slots_8.io.in_uop.bits.fu_code, issue_slots[8].in_uop.bits.fu_code connect slots_8.io.in_uop.bits.iq_type, issue_slots[8].in_uop.bits.iq_type connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst connect slots_8.io.in_uop.bits.uopc, issue_slots[8].in_uop.bits.uopc connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid connect slots_8.io.spec_ld_wakeup[0].bits, issue_slots[8].spec_ld_wakeup[0].bits connect slots_8.io.spec_ld_wakeup[0].valid, issue_slots[8].spec_ld_wakeup[0].valid connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid connect slots_8.io.wakeup_ports[0].bits.poisoned, issue_slots[8].wakeup_ports[0].bits.poisoned connect slots_8.io.wakeup_ports[0].bits.pdst, issue_slots[8].wakeup_ports[0].bits.pdst connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid connect slots_8.io.wakeup_ports[1].bits.poisoned, issue_slots[8].wakeup_ports[1].bits.poisoned connect slots_8.io.wakeup_ports[1].bits.pdst, issue_slots[8].wakeup_ports[1].bits.pdst connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid connect slots_8.io.wakeup_ports[2].bits.poisoned, issue_slots[8].wakeup_ports[2].bits.poisoned connect slots_8.io.wakeup_ports[2].bits.pdst, issue_slots[8].wakeup_ports[2].bits.pdst connect slots_8.io.wakeup_ports[2].valid, issue_slots[8].wakeup_ports[2].valid connect slots_8.io.wakeup_ports[3].bits.poisoned, issue_slots[8].wakeup_ports[3].bits.poisoned connect slots_8.io.wakeup_ports[3].bits.pdst, issue_slots[8].wakeup_ports[3].bits.pdst connect slots_8.io.wakeup_ports[3].valid, issue_slots[8].wakeup_ports[3].valid connect slots_8.io.wakeup_ports[4].bits.poisoned, issue_slots[8].wakeup_ports[4].bits.poisoned connect slots_8.io.wakeup_ports[4].bits.pdst, issue_slots[8].wakeup_ports[4].bits.pdst connect slots_8.io.wakeup_ports[4].valid, issue_slots[8].wakeup_ports[4].valid connect slots_8.io.wakeup_ports[5].bits.poisoned, issue_slots[8].wakeup_ports[5].bits.poisoned connect slots_8.io.wakeup_ports[5].bits.pdst, issue_slots[8].wakeup_ports[5].bits.pdst connect slots_8.io.wakeup_ports[5].valid, issue_slots[8].wakeup_ports[5].valid connect slots_8.io.wakeup_ports[6].bits.poisoned, issue_slots[8].wakeup_ports[6].bits.poisoned connect slots_8.io.wakeup_ports[6].bits.pdst, issue_slots[8].wakeup_ports[6].bits.pdst connect slots_8.io.wakeup_ports[6].valid, issue_slots[8].wakeup_ports[6].valid connect slots_8.io.ldspec_miss, issue_slots[8].ldspec_miss connect slots_8.io.clear, issue_slots[8].clear connect slots_8.io.kill, issue_slots[8].kill connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict connect slots_8.io.brupdate.b2.valid, issue_slots[8].brupdate.b2.valid connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if connect slots_8.io.brupdate.b2.uop.fp_single, issue_slots[8].brupdate.b2.uop.fp_single connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype connect slots_8.io.brupdate.b2.uop.ldst_val, issue_slots[8].brupdate.b2.uop.ldst_val connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3 connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2 connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1 connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1 connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd connect slots_8.io.brupdate.b2.uop.bypassable, issue_slots[8].brupdate.b2.uop.bypassable connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3 connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2 connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1 connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx connect slots_8.io.brupdate.b2.uop.csr_addr, issue_slots[8].brupdate.b2.uop.csr_addr connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb connect slots_8.io.brupdate.b2.uop.is_jal, issue_slots[8].brupdate.b2.uop.is_jal connect slots_8.io.brupdate.b2.uop.is_jalr, issue_slots[8].brupdate.b2.uop.is_jalr connect slots_8.io.brupdate.b2.uop.is_br, issue_slots[8].brupdate.b2.uop.is_br connect slots_8.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[8].brupdate.b2.uop.iw_p2_poisoned connect slots_8.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[8].brupdate.b2.uop.iw_p1_poisoned connect slots_8.io.brupdate.b2.uop.iw_state, issue_slots[8].brupdate.b2.uop.iw_state connect slots_8.io.brupdate.b2.uop.ctrl.is_std, issue_slots[8].brupdate.b2.uop.ctrl.is_std connect slots_8.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[8].brupdate.b2.uop.ctrl.is_sta connect slots_8.io.brupdate.b2.uop.ctrl.is_load, issue_slots[8].brupdate.b2.uop.ctrl.is_load connect slots_8.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[8].brupdate.b2.uop.ctrl.csr_cmd connect slots_8.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[8].brupdate.b2.uop.ctrl.fcn_dw connect slots_8.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[8].brupdate.b2.uop.ctrl.op_fcn connect slots_8.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[8].brupdate.b2.uop.ctrl.imm_sel connect slots_8.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[8].brupdate.b2.uop.ctrl.op2_sel connect slots_8.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[8].brupdate.b2.uop.ctrl.op1_sel connect slots_8.io.brupdate.b2.uop.ctrl.br_type, issue_slots[8].brupdate.b2.uop.ctrl.br_type connect slots_8.io.brupdate.b2.uop.fu_code, issue_slots[8].brupdate.b2.uop.fu_code connect slots_8.io.brupdate.b2.uop.iq_type, issue_slots[8].brupdate.b2.uop.iq_type connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst connect slots_8.io.brupdate.b2.uop.uopc, issue_slots[8].brupdate.b2.uop.uopc connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask connect slots_8.io.grant, issue_slots[8].grant connect issue_slots[8].request_hp, slots_8.io.request_hp connect issue_slots[8].request, slots_8.io.request connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid connect issue_slots[8].valid, slots_8.io.valid connect issue_slots[9].debug.state, slots_9.io.debug.state connect issue_slots[9].debug.ppred, slots_9.io.debug.ppred connect issue_slots[9].debug.p3, slots_9.io.debug.p3 connect issue_slots[9].debug.p2, slots_9.io.debug.p2 connect issue_slots[9].debug.p1, slots_9.io.debug.p1 connect issue_slots[9].uop.debug_tsrc, slots_9.io.uop.debug_tsrc connect issue_slots[9].uop.debug_fsrc, slots_9.io.uop.debug_fsrc connect issue_slots[9].uop.bp_xcpt_if, slots_9.io.uop.bp_xcpt_if connect issue_slots[9].uop.bp_debug_if, slots_9.io.uop.bp_debug_if connect issue_slots[9].uop.xcpt_ma_if, slots_9.io.uop.xcpt_ma_if connect issue_slots[9].uop.xcpt_ae_if, slots_9.io.uop.xcpt_ae_if connect issue_slots[9].uop.xcpt_pf_if, slots_9.io.uop.xcpt_pf_if connect issue_slots[9].uop.fp_single, slots_9.io.uop.fp_single connect issue_slots[9].uop.fp_val, slots_9.io.uop.fp_val connect issue_slots[9].uop.frs3_en, slots_9.io.uop.frs3_en connect issue_slots[9].uop.lrs2_rtype, slots_9.io.uop.lrs2_rtype connect issue_slots[9].uop.lrs1_rtype, slots_9.io.uop.lrs1_rtype connect issue_slots[9].uop.dst_rtype, slots_9.io.uop.dst_rtype connect issue_slots[9].uop.ldst_val, slots_9.io.uop.ldst_val connect issue_slots[9].uop.lrs3, slots_9.io.uop.lrs3 connect issue_slots[9].uop.lrs2, slots_9.io.uop.lrs2 connect issue_slots[9].uop.lrs1, slots_9.io.uop.lrs1 connect issue_slots[9].uop.ldst, slots_9.io.uop.ldst connect issue_slots[9].uop.ldst_is_rs1, slots_9.io.uop.ldst_is_rs1 connect issue_slots[9].uop.flush_on_commit, slots_9.io.uop.flush_on_commit connect issue_slots[9].uop.is_unique, slots_9.io.uop.is_unique connect issue_slots[9].uop.is_sys_pc2epc, slots_9.io.uop.is_sys_pc2epc connect issue_slots[9].uop.uses_stq, slots_9.io.uop.uses_stq connect issue_slots[9].uop.uses_ldq, slots_9.io.uop.uses_ldq connect issue_slots[9].uop.is_amo, slots_9.io.uop.is_amo connect issue_slots[9].uop.is_fencei, slots_9.io.uop.is_fencei connect issue_slots[9].uop.is_fence, slots_9.io.uop.is_fence connect issue_slots[9].uop.mem_signed, slots_9.io.uop.mem_signed connect issue_slots[9].uop.mem_size, slots_9.io.uop.mem_size connect issue_slots[9].uop.mem_cmd, slots_9.io.uop.mem_cmd connect issue_slots[9].uop.bypassable, slots_9.io.uop.bypassable connect issue_slots[9].uop.exc_cause, slots_9.io.uop.exc_cause connect issue_slots[9].uop.exception, slots_9.io.uop.exception connect issue_slots[9].uop.stale_pdst, slots_9.io.uop.stale_pdst connect issue_slots[9].uop.ppred_busy, slots_9.io.uop.ppred_busy connect issue_slots[9].uop.prs3_busy, slots_9.io.uop.prs3_busy connect issue_slots[9].uop.prs2_busy, slots_9.io.uop.prs2_busy connect issue_slots[9].uop.prs1_busy, slots_9.io.uop.prs1_busy connect issue_slots[9].uop.ppred, slots_9.io.uop.ppred connect issue_slots[9].uop.prs3, slots_9.io.uop.prs3 connect issue_slots[9].uop.prs2, slots_9.io.uop.prs2 connect issue_slots[9].uop.prs1, slots_9.io.uop.prs1 connect issue_slots[9].uop.pdst, slots_9.io.uop.pdst connect issue_slots[9].uop.rxq_idx, slots_9.io.uop.rxq_idx connect issue_slots[9].uop.stq_idx, slots_9.io.uop.stq_idx connect issue_slots[9].uop.ldq_idx, slots_9.io.uop.ldq_idx connect issue_slots[9].uop.rob_idx, slots_9.io.uop.rob_idx connect issue_slots[9].uop.csr_addr, slots_9.io.uop.csr_addr connect issue_slots[9].uop.imm_packed, slots_9.io.uop.imm_packed connect issue_slots[9].uop.taken, slots_9.io.uop.taken connect issue_slots[9].uop.pc_lob, slots_9.io.uop.pc_lob connect issue_slots[9].uop.edge_inst, slots_9.io.uop.edge_inst connect issue_slots[9].uop.ftq_idx, slots_9.io.uop.ftq_idx connect issue_slots[9].uop.br_tag, slots_9.io.uop.br_tag connect issue_slots[9].uop.br_mask, slots_9.io.uop.br_mask connect issue_slots[9].uop.is_sfb, slots_9.io.uop.is_sfb connect issue_slots[9].uop.is_jal, slots_9.io.uop.is_jal connect issue_slots[9].uop.is_jalr, slots_9.io.uop.is_jalr connect issue_slots[9].uop.is_br, slots_9.io.uop.is_br connect issue_slots[9].uop.iw_p2_poisoned, slots_9.io.uop.iw_p2_poisoned connect issue_slots[9].uop.iw_p1_poisoned, slots_9.io.uop.iw_p1_poisoned connect issue_slots[9].uop.iw_state, slots_9.io.uop.iw_state connect issue_slots[9].uop.ctrl.is_std, slots_9.io.uop.ctrl.is_std connect issue_slots[9].uop.ctrl.is_sta, slots_9.io.uop.ctrl.is_sta connect issue_slots[9].uop.ctrl.is_load, slots_9.io.uop.ctrl.is_load connect issue_slots[9].uop.ctrl.csr_cmd, slots_9.io.uop.ctrl.csr_cmd connect issue_slots[9].uop.ctrl.fcn_dw, slots_9.io.uop.ctrl.fcn_dw connect issue_slots[9].uop.ctrl.op_fcn, slots_9.io.uop.ctrl.op_fcn connect issue_slots[9].uop.ctrl.imm_sel, slots_9.io.uop.ctrl.imm_sel connect issue_slots[9].uop.ctrl.op2_sel, slots_9.io.uop.ctrl.op2_sel connect issue_slots[9].uop.ctrl.op1_sel, slots_9.io.uop.ctrl.op1_sel connect issue_slots[9].uop.ctrl.br_type, slots_9.io.uop.ctrl.br_type connect issue_slots[9].uop.fu_code, slots_9.io.uop.fu_code connect issue_slots[9].uop.iq_type, slots_9.io.uop.iq_type connect issue_slots[9].uop.debug_pc, slots_9.io.uop.debug_pc connect issue_slots[9].uop.is_rvc, slots_9.io.uop.is_rvc connect issue_slots[9].uop.debug_inst, slots_9.io.uop.debug_inst connect issue_slots[9].uop.inst, slots_9.io.uop.inst connect issue_slots[9].uop.uopc, slots_9.io.uop.uopc connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if connect issue_slots[9].out_uop.fp_single, slots_9.io.out_uop.fp_single connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype connect issue_slots[9].out_uop.ldst_val, slots_9.io.out_uop.ldst_val connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3 connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2 connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1 connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1 connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd connect issue_slots[9].out_uop.bypassable, slots_9.io.out_uop.bypassable connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3 connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2 connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1 connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx connect issue_slots[9].out_uop.csr_addr, slots_9.io.out_uop.csr_addr connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb connect issue_slots[9].out_uop.is_jal, slots_9.io.out_uop.is_jal connect issue_slots[9].out_uop.is_jalr, slots_9.io.out_uop.is_jalr connect issue_slots[9].out_uop.is_br, slots_9.io.out_uop.is_br connect issue_slots[9].out_uop.iw_p2_poisoned, slots_9.io.out_uop.iw_p2_poisoned connect issue_slots[9].out_uop.iw_p1_poisoned, slots_9.io.out_uop.iw_p1_poisoned connect issue_slots[9].out_uop.iw_state, slots_9.io.out_uop.iw_state connect issue_slots[9].out_uop.ctrl.is_std, slots_9.io.out_uop.ctrl.is_std connect issue_slots[9].out_uop.ctrl.is_sta, slots_9.io.out_uop.ctrl.is_sta connect issue_slots[9].out_uop.ctrl.is_load, slots_9.io.out_uop.ctrl.is_load connect issue_slots[9].out_uop.ctrl.csr_cmd, slots_9.io.out_uop.ctrl.csr_cmd connect issue_slots[9].out_uop.ctrl.fcn_dw, slots_9.io.out_uop.ctrl.fcn_dw connect issue_slots[9].out_uop.ctrl.op_fcn, slots_9.io.out_uop.ctrl.op_fcn connect issue_slots[9].out_uop.ctrl.imm_sel, slots_9.io.out_uop.ctrl.imm_sel connect issue_slots[9].out_uop.ctrl.op2_sel, slots_9.io.out_uop.ctrl.op2_sel connect issue_slots[9].out_uop.ctrl.op1_sel, slots_9.io.out_uop.ctrl.op1_sel connect issue_slots[9].out_uop.ctrl.br_type, slots_9.io.out_uop.ctrl.br_type connect issue_slots[9].out_uop.fu_code, slots_9.io.out_uop.fu_code connect issue_slots[9].out_uop.iq_type, slots_9.io.out_uop.iq_type connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst connect issue_slots[9].out_uop.uopc, slots_9.io.out_uop.uopc connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if connect slots_9.io.in_uop.bits.fp_single, issue_slots[9].in_uop.bits.fp_single connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype connect slots_9.io.in_uop.bits.ldst_val, issue_slots[9].in_uop.bits.ldst_val connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3 connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2 connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1 connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1 connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd connect slots_9.io.in_uop.bits.bypassable, issue_slots[9].in_uop.bits.bypassable connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3 connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2 connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1 connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx connect slots_9.io.in_uop.bits.csr_addr, issue_slots[9].in_uop.bits.csr_addr connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb connect slots_9.io.in_uop.bits.is_jal, issue_slots[9].in_uop.bits.is_jal connect slots_9.io.in_uop.bits.is_jalr, issue_slots[9].in_uop.bits.is_jalr connect slots_9.io.in_uop.bits.is_br, issue_slots[9].in_uop.bits.is_br connect slots_9.io.in_uop.bits.iw_p2_poisoned, issue_slots[9].in_uop.bits.iw_p2_poisoned connect slots_9.io.in_uop.bits.iw_p1_poisoned, issue_slots[9].in_uop.bits.iw_p1_poisoned connect slots_9.io.in_uop.bits.iw_state, issue_slots[9].in_uop.bits.iw_state connect slots_9.io.in_uop.bits.ctrl.is_std, issue_slots[9].in_uop.bits.ctrl.is_std connect slots_9.io.in_uop.bits.ctrl.is_sta, issue_slots[9].in_uop.bits.ctrl.is_sta connect slots_9.io.in_uop.bits.ctrl.is_load, issue_slots[9].in_uop.bits.ctrl.is_load connect slots_9.io.in_uop.bits.ctrl.csr_cmd, issue_slots[9].in_uop.bits.ctrl.csr_cmd connect slots_9.io.in_uop.bits.ctrl.fcn_dw, issue_slots[9].in_uop.bits.ctrl.fcn_dw connect slots_9.io.in_uop.bits.ctrl.op_fcn, issue_slots[9].in_uop.bits.ctrl.op_fcn connect slots_9.io.in_uop.bits.ctrl.imm_sel, issue_slots[9].in_uop.bits.ctrl.imm_sel connect slots_9.io.in_uop.bits.ctrl.op2_sel, issue_slots[9].in_uop.bits.ctrl.op2_sel connect slots_9.io.in_uop.bits.ctrl.op1_sel, issue_slots[9].in_uop.bits.ctrl.op1_sel connect slots_9.io.in_uop.bits.ctrl.br_type, issue_slots[9].in_uop.bits.ctrl.br_type connect slots_9.io.in_uop.bits.fu_code, issue_slots[9].in_uop.bits.fu_code connect slots_9.io.in_uop.bits.iq_type, issue_slots[9].in_uop.bits.iq_type connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst connect slots_9.io.in_uop.bits.uopc, issue_slots[9].in_uop.bits.uopc connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid connect slots_9.io.spec_ld_wakeup[0].bits, issue_slots[9].spec_ld_wakeup[0].bits connect slots_9.io.spec_ld_wakeup[0].valid, issue_slots[9].spec_ld_wakeup[0].valid connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid connect slots_9.io.wakeup_ports[0].bits.poisoned, issue_slots[9].wakeup_ports[0].bits.poisoned connect slots_9.io.wakeup_ports[0].bits.pdst, issue_slots[9].wakeup_ports[0].bits.pdst connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid connect slots_9.io.wakeup_ports[1].bits.poisoned, issue_slots[9].wakeup_ports[1].bits.poisoned connect slots_9.io.wakeup_ports[1].bits.pdst, issue_slots[9].wakeup_ports[1].bits.pdst connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid connect slots_9.io.wakeup_ports[2].bits.poisoned, issue_slots[9].wakeup_ports[2].bits.poisoned connect slots_9.io.wakeup_ports[2].bits.pdst, issue_slots[9].wakeup_ports[2].bits.pdst connect slots_9.io.wakeup_ports[2].valid, issue_slots[9].wakeup_ports[2].valid connect slots_9.io.wakeup_ports[3].bits.poisoned, issue_slots[9].wakeup_ports[3].bits.poisoned connect slots_9.io.wakeup_ports[3].bits.pdst, issue_slots[9].wakeup_ports[3].bits.pdst connect slots_9.io.wakeup_ports[3].valid, issue_slots[9].wakeup_ports[3].valid connect slots_9.io.wakeup_ports[4].bits.poisoned, issue_slots[9].wakeup_ports[4].bits.poisoned connect slots_9.io.wakeup_ports[4].bits.pdst, issue_slots[9].wakeup_ports[4].bits.pdst connect slots_9.io.wakeup_ports[4].valid, issue_slots[9].wakeup_ports[4].valid connect slots_9.io.wakeup_ports[5].bits.poisoned, issue_slots[9].wakeup_ports[5].bits.poisoned connect slots_9.io.wakeup_ports[5].bits.pdst, issue_slots[9].wakeup_ports[5].bits.pdst connect slots_9.io.wakeup_ports[5].valid, issue_slots[9].wakeup_ports[5].valid connect slots_9.io.wakeup_ports[6].bits.poisoned, issue_slots[9].wakeup_ports[6].bits.poisoned connect slots_9.io.wakeup_ports[6].bits.pdst, issue_slots[9].wakeup_ports[6].bits.pdst connect slots_9.io.wakeup_ports[6].valid, issue_slots[9].wakeup_ports[6].valid connect slots_9.io.ldspec_miss, issue_slots[9].ldspec_miss connect slots_9.io.clear, issue_slots[9].clear connect slots_9.io.kill, issue_slots[9].kill connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict connect slots_9.io.brupdate.b2.valid, issue_slots[9].brupdate.b2.valid connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if connect slots_9.io.brupdate.b2.uop.fp_single, issue_slots[9].brupdate.b2.uop.fp_single connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype connect slots_9.io.brupdate.b2.uop.ldst_val, issue_slots[9].brupdate.b2.uop.ldst_val connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3 connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2 connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1 connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1 connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd connect slots_9.io.brupdate.b2.uop.bypassable, issue_slots[9].brupdate.b2.uop.bypassable connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3 connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2 connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1 connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx connect slots_9.io.brupdate.b2.uop.csr_addr, issue_slots[9].brupdate.b2.uop.csr_addr connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb connect slots_9.io.brupdate.b2.uop.is_jal, issue_slots[9].brupdate.b2.uop.is_jal connect slots_9.io.brupdate.b2.uop.is_jalr, issue_slots[9].brupdate.b2.uop.is_jalr connect slots_9.io.brupdate.b2.uop.is_br, issue_slots[9].brupdate.b2.uop.is_br connect slots_9.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[9].brupdate.b2.uop.iw_p2_poisoned connect slots_9.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[9].brupdate.b2.uop.iw_p1_poisoned connect slots_9.io.brupdate.b2.uop.iw_state, issue_slots[9].brupdate.b2.uop.iw_state connect slots_9.io.brupdate.b2.uop.ctrl.is_std, issue_slots[9].brupdate.b2.uop.ctrl.is_std connect slots_9.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[9].brupdate.b2.uop.ctrl.is_sta connect slots_9.io.brupdate.b2.uop.ctrl.is_load, issue_slots[9].brupdate.b2.uop.ctrl.is_load connect slots_9.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[9].brupdate.b2.uop.ctrl.csr_cmd connect slots_9.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[9].brupdate.b2.uop.ctrl.fcn_dw connect slots_9.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[9].brupdate.b2.uop.ctrl.op_fcn connect slots_9.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[9].brupdate.b2.uop.ctrl.imm_sel connect slots_9.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[9].brupdate.b2.uop.ctrl.op2_sel connect slots_9.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[9].brupdate.b2.uop.ctrl.op1_sel connect slots_9.io.brupdate.b2.uop.ctrl.br_type, issue_slots[9].brupdate.b2.uop.ctrl.br_type connect slots_9.io.brupdate.b2.uop.fu_code, issue_slots[9].brupdate.b2.uop.fu_code connect slots_9.io.brupdate.b2.uop.iq_type, issue_slots[9].brupdate.b2.uop.iq_type connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst connect slots_9.io.brupdate.b2.uop.uopc, issue_slots[9].brupdate.b2.uop.uopc connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask connect slots_9.io.grant, issue_slots[9].grant connect issue_slots[9].request_hp, slots_9.io.request_hp connect issue_slots[9].request, slots_9.io.request connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid connect issue_slots[9].valid, slots_9.io.valid connect issue_slots[10].debug.state, slots_10.io.debug.state connect issue_slots[10].debug.ppred, slots_10.io.debug.ppred connect issue_slots[10].debug.p3, slots_10.io.debug.p3 connect issue_slots[10].debug.p2, slots_10.io.debug.p2 connect issue_slots[10].debug.p1, slots_10.io.debug.p1 connect issue_slots[10].uop.debug_tsrc, slots_10.io.uop.debug_tsrc connect issue_slots[10].uop.debug_fsrc, slots_10.io.uop.debug_fsrc connect issue_slots[10].uop.bp_xcpt_if, slots_10.io.uop.bp_xcpt_if connect issue_slots[10].uop.bp_debug_if, slots_10.io.uop.bp_debug_if connect issue_slots[10].uop.xcpt_ma_if, slots_10.io.uop.xcpt_ma_if connect issue_slots[10].uop.xcpt_ae_if, slots_10.io.uop.xcpt_ae_if connect issue_slots[10].uop.xcpt_pf_if, slots_10.io.uop.xcpt_pf_if connect issue_slots[10].uop.fp_single, slots_10.io.uop.fp_single connect issue_slots[10].uop.fp_val, slots_10.io.uop.fp_val connect issue_slots[10].uop.frs3_en, slots_10.io.uop.frs3_en connect issue_slots[10].uop.lrs2_rtype, slots_10.io.uop.lrs2_rtype connect issue_slots[10].uop.lrs1_rtype, slots_10.io.uop.lrs1_rtype connect issue_slots[10].uop.dst_rtype, slots_10.io.uop.dst_rtype connect issue_slots[10].uop.ldst_val, slots_10.io.uop.ldst_val connect issue_slots[10].uop.lrs3, slots_10.io.uop.lrs3 connect issue_slots[10].uop.lrs2, slots_10.io.uop.lrs2 connect issue_slots[10].uop.lrs1, slots_10.io.uop.lrs1 connect issue_slots[10].uop.ldst, slots_10.io.uop.ldst connect issue_slots[10].uop.ldst_is_rs1, slots_10.io.uop.ldst_is_rs1 connect issue_slots[10].uop.flush_on_commit, slots_10.io.uop.flush_on_commit connect issue_slots[10].uop.is_unique, slots_10.io.uop.is_unique connect issue_slots[10].uop.is_sys_pc2epc, slots_10.io.uop.is_sys_pc2epc connect issue_slots[10].uop.uses_stq, slots_10.io.uop.uses_stq connect issue_slots[10].uop.uses_ldq, slots_10.io.uop.uses_ldq connect issue_slots[10].uop.is_amo, slots_10.io.uop.is_amo connect issue_slots[10].uop.is_fencei, slots_10.io.uop.is_fencei connect issue_slots[10].uop.is_fence, slots_10.io.uop.is_fence connect issue_slots[10].uop.mem_signed, slots_10.io.uop.mem_signed connect issue_slots[10].uop.mem_size, slots_10.io.uop.mem_size connect issue_slots[10].uop.mem_cmd, slots_10.io.uop.mem_cmd connect issue_slots[10].uop.bypassable, slots_10.io.uop.bypassable connect issue_slots[10].uop.exc_cause, slots_10.io.uop.exc_cause connect issue_slots[10].uop.exception, slots_10.io.uop.exception connect issue_slots[10].uop.stale_pdst, slots_10.io.uop.stale_pdst connect issue_slots[10].uop.ppred_busy, slots_10.io.uop.ppred_busy connect issue_slots[10].uop.prs3_busy, slots_10.io.uop.prs3_busy connect issue_slots[10].uop.prs2_busy, slots_10.io.uop.prs2_busy connect issue_slots[10].uop.prs1_busy, slots_10.io.uop.prs1_busy connect issue_slots[10].uop.ppred, slots_10.io.uop.ppred connect issue_slots[10].uop.prs3, slots_10.io.uop.prs3 connect issue_slots[10].uop.prs2, slots_10.io.uop.prs2 connect issue_slots[10].uop.prs1, slots_10.io.uop.prs1 connect issue_slots[10].uop.pdst, slots_10.io.uop.pdst connect issue_slots[10].uop.rxq_idx, slots_10.io.uop.rxq_idx connect issue_slots[10].uop.stq_idx, slots_10.io.uop.stq_idx connect issue_slots[10].uop.ldq_idx, slots_10.io.uop.ldq_idx connect issue_slots[10].uop.rob_idx, slots_10.io.uop.rob_idx connect issue_slots[10].uop.csr_addr, slots_10.io.uop.csr_addr connect issue_slots[10].uop.imm_packed, slots_10.io.uop.imm_packed connect issue_slots[10].uop.taken, slots_10.io.uop.taken connect issue_slots[10].uop.pc_lob, slots_10.io.uop.pc_lob connect issue_slots[10].uop.edge_inst, slots_10.io.uop.edge_inst connect issue_slots[10].uop.ftq_idx, slots_10.io.uop.ftq_idx connect issue_slots[10].uop.br_tag, slots_10.io.uop.br_tag connect issue_slots[10].uop.br_mask, slots_10.io.uop.br_mask connect issue_slots[10].uop.is_sfb, slots_10.io.uop.is_sfb connect issue_slots[10].uop.is_jal, slots_10.io.uop.is_jal connect issue_slots[10].uop.is_jalr, slots_10.io.uop.is_jalr connect issue_slots[10].uop.is_br, slots_10.io.uop.is_br connect issue_slots[10].uop.iw_p2_poisoned, slots_10.io.uop.iw_p2_poisoned connect issue_slots[10].uop.iw_p1_poisoned, slots_10.io.uop.iw_p1_poisoned connect issue_slots[10].uop.iw_state, slots_10.io.uop.iw_state connect issue_slots[10].uop.ctrl.is_std, slots_10.io.uop.ctrl.is_std connect issue_slots[10].uop.ctrl.is_sta, slots_10.io.uop.ctrl.is_sta connect issue_slots[10].uop.ctrl.is_load, slots_10.io.uop.ctrl.is_load connect issue_slots[10].uop.ctrl.csr_cmd, slots_10.io.uop.ctrl.csr_cmd connect issue_slots[10].uop.ctrl.fcn_dw, slots_10.io.uop.ctrl.fcn_dw connect issue_slots[10].uop.ctrl.op_fcn, slots_10.io.uop.ctrl.op_fcn connect issue_slots[10].uop.ctrl.imm_sel, slots_10.io.uop.ctrl.imm_sel connect issue_slots[10].uop.ctrl.op2_sel, slots_10.io.uop.ctrl.op2_sel connect issue_slots[10].uop.ctrl.op1_sel, slots_10.io.uop.ctrl.op1_sel connect issue_slots[10].uop.ctrl.br_type, slots_10.io.uop.ctrl.br_type connect issue_slots[10].uop.fu_code, slots_10.io.uop.fu_code connect issue_slots[10].uop.iq_type, slots_10.io.uop.iq_type connect issue_slots[10].uop.debug_pc, slots_10.io.uop.debug_pc connect issue_slots[10].uop.is_rvc, slots_10.io.uop.is_rvc connect issue_slots[10].uop.debug_inst, slots_10.io.uop.debug_inst connect issue_slots[10].uop.inst, slots_10.io.uop.inst connect issue_slots[10].uop.uopc, slots_10.io.uop.uopc connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if connect issue_slots[10].out_uop.fp_single, slots_10.io.out_uop.fp_single connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype connect issue_slots[10].out_uop.ldst_val, slots_10.io.out_uop.ldst_val connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3 connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2 connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1 connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1 connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd connect issue_slots[10].out_uop.bypassable, slots_10.io.out_uop.bypassable connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3 connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2 connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1 connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx connect issue_slots[10].out_uop.csr_addr, slots_10.io.out_uop.csr_addr connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb connect issue_slots[10].out_uop.is_jal, slots_10.io.out_uop.is_jal connect issue_slots[10].out_uop.is_jalr, slots_10.io.out_uop.is_jalr connect issue_slots[10].out_uop.is_br, slots_10.io.out_uop.is_br connect issue_slots[10].out_uop.iw_p2_poisoned, slots_10.io.out_uop.iw_p2_poisoned connect issue_slots[10].out_uop.iw_p1_poisoned, slots_10.io.out_uop.iw_p1_poisoned connect issue_slots[10].out_uop.iw_state, slots_10.io.out_uop.iw_state connect issue_slots[10].out_uop.ctrl.is_std, slots_10.io.out_uop.ctrl.is_std connect issue_slots[10].out_uop.ctrl.is_sta, slots_10.io.out_uop.ctrl.is_sta connect issue_slots[10].out_uop.ctrl.is_load, slots_10.io.out_uop.ctrl.is_load connect issue_slots[10].out_uop.ctrl.csr_cmd, slots_10.io.out_uop.ctrl.csr_cmd connect issue_slots[10].out_uop.ctrl.fcn_dw, slots_10.io.out_uop.ctrl.fcn_dw connect issue_slots[10].out_uop.ctrl.op_fcn, slots_10.io.out_uop.ctrl.op_fcn connect issue_slots[10].out_uop.ctrl.imm_sel, slots_10.io.out_uop.ctrl.imm_sel connect issue_slots[10].out_uop.ctrl.op2_sel, slots_10.io.out_uop.ctrl.op2_sel connect issue_slots[10].out_uop.ctrl.op1_sel, slots_10.io.out_uop.ctrl.op1_sel connect issue_slots[10].out_uop.ctrl.br_type, slots_10.io.out_uop.ctrl.br_type connect issue_slots[10].out_uop.fu_code, slots_10.io.out_uop.fu_code connect issue_slots[10].out_uop.iq_type, slots_10.io.out_uop.iq_type connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst connect issue_slots[10].out_uop.uopc, slots_10.io.out_uop.uopc connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if connect slots_10.io.in_uop.bits.fp_single, issue_slots[10].in_uop.bits.fp_single connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype connect slots_10.io.in_uop.bits.ldst_val, issue_slots[10].in_uop.bits.ldst_val connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3 connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2 connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1 connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1 connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd connect slots_10.io.in_uop.bits.bypassable, issue_slots[10].in_uop.bits.bypassable connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3 connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2 connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1 connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx connect slots_10.io.in_uop.bits.csr_addr, issue_slots[10].in_uop.bits.csr_addr connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb connect slots_10.io.in_uop.bits.is_jal, issue_slots[10].in_uop.bits.is_jal connect slots_10.io.in_uop.bits.is_jalr, issue_slots[10].in_uop.bits.is_jalr connect slots_10.io.in_uop.bits.is_br, issue_slots[10].in_uop.bits.is_br connect slots_10.io.in_uop.bits.iw_p2_poisoned, issue_slots[10].in_uop.bits.iw_p2_poisoned connect slots_10.io.in_uop.bits.iw_p1_poisoned, issue_slots[10].in_uop.bits.iw_p1_poisoned connect slots_10.io.in_uop.bits.iw_state, issue_slots[10].in_uop.bits.iw_state connect slots_10.io.in_uop.bits.ctrl.is_std, issue_slots[10].in_uop.bits.ctrl.is_std connect slots_10.io.in_uop.bits.ctrl.is_sta, issue_slots[10].in_uop.bits.ctrl.is_sta connect slots_10.io.in_uop.bits.ctrl.is_load, issue_slots[10].in_uop.bits.ctrl.is_load connect slots_10.io.in_uop.bits.ctrl.csr_cmd, issue_slots[10].in_uop.bits.ctrl.csr_cmd connect slots_10.io.in_uop.bits.ctrl.fcn_dw, issue_slots[10].in_uop.bits.ctrl.fcn_dw connect slots_10.io.in_uop.bits.ctrl.op_fcn, issue_slots[10].in_uop.bits.ctrl.op_fcn connect slots_10.io.in_uop.bits.ctrl.imm_sel, issue_slots[10].in_uop.bits.ctrl.imm_sel connect slots_10.io.in_uop.bits.ctrl.op2_sel, issue_slots[10].in_uop.bits.ctrl.op2_sel connect slots_10.io.in_uop.bits.ctrl.op1_sel, issue_slots[10].in_uop.bits.ctrl.op1_sel connect slots_10.io.in_uop.bits.ctrl.br_type, issue_slots[10].in_uop.bits.ctrl.br_type connect slots_10.io.in_uop.bits.fu_code, issue_slots[10].in_uop.bits.fu_code connect slots_10.io.in_uop.bits.iq_type, issue_slots[10].in_uop.bits.iq_type connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst connect slots_10.io.in_uop.bits.uopc, issue_slots[10].in_uop.bits.uopc connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid connect slots_10.io.spec_ld_wakeup[0].bits, issue_slots[10].spec_ld_wakeup[0].bits connect slots_10.io.spec_ld_wakeup[0].valid, issue_slots[10].spec_ld_wakeup[0].valid connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid connect slots_10.io.wakeup_ports[0].bits.poisoned, issue_slots[10].wakeup_ports[0].bits.poisoned connect slots_10.io.wakeup_ports[0].bits.pdst, issue_slots[10].wakeup_ports[0].bits.pdst connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid connect slots_10.io.wakeup_ports[1].bits.poisoned, issue_slots[10].wakeup_ports[1].bits.poisoned connect slots_10.io.wakeup_ports[1].bits.pdst, issue_slots[10].wakeup_ports[1].bits.pdst connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid connect slots_10.io.wakeup_ports[2].bits.poisoned, issue_slots[10].wakeup_ports[2].bits.poisoned connect slots_10.io.wakeup_ports[2].bits.pdst, issue_slots[10].wakeup_ports[2].bits.pdst connect slots_10.io.wakeup_ports[2].valid, issue_slots[10].wakeup_ports[2].valid connect slots_10.io.wakeup_ports[3].bits.poisoned, issue_slots[10].wakeup_ports[3].bits.poisoned connect slots_10.io.wakeup_ports[3].bits.pdst, issue_slots[10].wakeup_ports[3].bits.pdst connect slots_10.io.wakeup_ports[3].valid, issue_slots[10].wakeup_ports[3].valid connect slots_10.io.wakeup_ports[4].bits.poisoned, issue_slots[10].wakeup_ports[4].bits.poisoned connect slots_10.io.wakeup_ports[4].bits.pdst, issue_slots[10].wakeup_ports[4].bits.pdst connect slots_10.io.wakeup_ports[4].valid, issue_slots[10].wakeup_ports[4].valid connect slots_10.io.wakeup_ports[5].bits.poisoned, issue_slots[10].wakeup_ports[5].bits.poisoned connect slots_10.io.wakeup_ports[5].bits.pdst, issue_slots[10].wakeup_ports[5].bits.pdst connect slots_10.io.wakeup_ports[5].valid, issue_slots[10].wakeup_ports[5].valid connect slots_10.io.wakeup_ports[6].bits.poisoned, issue_slots[10].wakeup_ports[6].bits.poisoned connect slots_10.io.wakeup_ports[6].bits.pdst, issue_slots[10].wakeup_ports[6].bits.pdst connect slots_10.io.wakeup_ports[6].valid, issue_slots[10].wakeup_ports[6].valid connect slots_10.io.ldspec_miss, issue_slots[10].ldspec_miss connect slots_10.io.clear, issue_slots[10].clear connect slots_10.io.kill, issue_slots[10].kill connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict connect slots_10.io.brupdate.b2.valid, issue_slots[10].brupdate.b2.valid connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if connect slots_10.io.brupdate.b2.uop.fp_single, issue_slots[10].brupdate.b2.uop.fp_single connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype connect slots_10.io.brupdate.b2.uop.ldst_val, issue_slots[10].brupdate.b2.uop.ldst_val connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3 connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2 connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1 connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1 connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd connect slots_10.io.brupdate.b2.uop.bypassable, issue_slots[10].brupdate.b2.uop.bypassable connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3 connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2 connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1 connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx connect slots_10.io.brupdate.b2.uop.csr_addr, issue_slots[10].brupdate.b2.uop.csr_addr connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb connect slots_10.io.brupdate.b2.uop.is_jal, issue_slots[10].brupdate.b2.uop.is_jal connect slots_10.io.brupdate.b2.uop.is_jalr, issue_slots[10].brupdate.b2.uop.is_jalr connect slots_10.io.brupdate.b2.uop.is_br, issue_slots[10].brupdate.b2.uop.is_br connect slots_10.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[10].brupdate.b2.uop.iw_p2_poisoned connect slots_10.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[10].brupdate.b2.uop.iw_p1_poisoned connect slots_10.io.brupdate.b2.uop.iw_state, issue_slots[10].brupdate.b2.uop.iw_state connect slots_10.io.brupdate.b2.uop.ctrl.is_std, issue_slots[10].brupdate.b2.uop.ctrl.is_std connect slots_10.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[10].brupdate.b2.uop.ctrl.is_sta connect slots_10.io.brupdate.b2.uop.ctrl.is_load, issue_slots[10].brupdate.b2.uop.ctrl.is_load connect slots_10.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[10].brupdate.b2.uop.ctrl.csr_cmd connect slots_10.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[10].brupdate.b2.uop.ctrl.fcn_dw connect slots_10.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[10].brupdate.b2.uop.ctrl.op_fcn connect slots_10.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[10].brupdate.b2.uop.ctrl.imm_sel connect slots_10.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[10].brupdate.b2.uop.ctrl.op2_sel connect slots_10.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[10].brupdate.b2.uop.ctrl.op1_sel connect slots_10.io.brupdate.b2.uop.ctrl.br_type, issue_slots[10].brupdate.b2.uop.ctrl.br_type connect slots_10.io.brupdate.b2.uop.fu_code, issue_slots[10].brupdate.b2.uop.fu_code connect slots_10.io.brupdate.b2.uop.iq_type, issue_slots[10].brupdate.b2.uop.iq_type connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst connect slots_10.io.brupdate.b2.uop.uopc, issue_slots[10].brupdate.b2.uop.uopc connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask connect slots_10.io.grant, issue_slots[10].grant connect issue_slots[10].request_hp, slots_10.io.request_hp connect issue_slots[10].request, slots_10.io.request connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid connect issue_slots[10].valid, slots_10.io.valid connect issue_slots[11].debug.state, slots_11.io.debug.state connect issue_slots[11].debug.ppred, slots_11.io.debug.ppred connect issue_slots[11].debug.p3, slots_11.io.debug.p3 connect issue_slots[11].debug.p2, slots_11.io.debug.p2 connect issue_slots[11].debug.p1, slots_11.io.debug.p1 connect issue_slots[11].uop.debug_tsrc, slots_11.io.uop.debug_tsrc connect issue_slots[11].uop.debug_fsrc, slots_11.io.uop.debug_fsrc connect issue_slots[11].uop.bp_xcpt_if, slots_11.io.uop.bp_xcpt_if connect issue_slots[11].uop.bp_debug_if, slots_11.io.uop.bp_debug_if connect issue_slots[11].uop.xcpt_ma_if, slots_11.io.uop.xcpt_ma_if connect issue_slots[11].uop.xcpt_ae_if, slots_11.io.uop.xcpt_ae_if connect issue_slots[11].uop.xcpt_pf_if, slots_11.io.uop.xcpt_pf_if connect issue_slots[11].uop.fp_single, slots_11.io.uop.fp_single connect issue_slots[11].uop.fp_val, slots_11.io.uop.fp_val connect issue_slots[11].uop.frs3_en, slots_11.io.uop.frs3_en connect issue_slots[11].uop.lrs2_rtype, slots_11.io.uop.lrs2_rtype connect issue_slots[11].uop.lrs1_rtype, slots_11.io.uop.lrs1_rtype connect issue_slots[11].uop.dst_rtype, slots_11.io.uop.dst_rtype connect issue_slots[11].uop.ldst_val, slots_11.io.uop.ldst_val connect issue_slots[11].uop.lrs3, slots_11.io.uop.lrs3 connect issue_slots[11].uop.lrs2, slots_11.io.uop.lrs2 connect issue_slots[11].uop.lrs1, slots_11.io.uop.lrs1 connect issue_slots[11].uop.ldst, slots_11.io.uop.ldst connect issue_slots[11].uop.ldst_is_rs1, slots_11.io.uop.ldst_is_rs1 connect issue_slots[11].uop.flush_on_commit, slots_11.io.uop.flush_on_commit connect issue_slots[11].uop.is_unique, slots_11.io.uop.is_unique connect issue_slots[11].uop.is_sys_pc2epc, slots_11.io.uop.is_sys_pc2epc connect issue_slots[11].uop.uses_stq, slots_11.io.uop.uses_stq connect issue_slots[11].uop.uses_ldq, slots_11.io.uop.uses_ldq connect issue_slots[11].uop.is_amo, slots_11.io.uop.is_amo connect issue_slots[11].uop.is_fencei, slots_11.io.uop.is_fencei connect issue_slots[11].uop.is_fence, slots_11.io.uop.is_fence connect issue_slots[11].uop.mem_signed, slots_11.io.uop.mem_signed connect issue_slots[11].uop.mem_size, slots_11.io.uop.mem_size connect issue_slots[11].uop.mem_cmd, slots_11.io.uop.mem_cmd connect issue_slots[11].uop.bypassable, slots_11.io.uop.bypassable connect issue_slots[11].uop.exc_cause, slots_11.io.uop.exc_cause connect issue_slots[11].uop.exception, slots_11.io.uop.exception connect issue_slots[11].uop.stale_pdst, slots_11.io.uop.stale_pdst connect issue_slots[11].uop.ppred_busy, slots_11.io.uop.ppred_busy connect issue_slots[11].uop.prs3_busy, slots_11.io.uop.prs3_busy connect issue_slots[11].uop.prs2_busy, slots_11.io.uop.prs2_busy connect issue_slots[11].uop.prs1_busy, slots_11.io.uop.prs1_busy connect issue_slots[11].uop.ppred, slots_11.io.uop.ppred connect issue_slots[11].uop.prs3, slots_11.io.uop.prs3 connect issue_slots[11].uop.prs2, slots_11.io.uop.prs2 connect issue_slots[11].uop.prs1, slots_11.io.uop.prs1 connect issue_slots[11].uop.pdst, slots_11.io.uop.pdst connect issue_slots[11].uop.rxq_idx, slots_11.io.uop.rxq_idx connect issue_slots[11].uop.stq_idx, slots_11.io.uop.stq_idx connect issue_slots[11].uop.ldq_idx, slots_11.io.uop.ldq_idx connect issue_slots[11].uop.rob_idx, slots_11.io.uop.rob_idx connect issue_slots[11].uop.csr_addr, slots_11.io.uop.csr_addr connect issue_slots[11].uop.imm_packed, slots_11.io.uop.imm_packed connect issue_slots[11].uop.taken, slots_11.io.uop.taken connect issue_slots[11].uop.pc_lob, slots_11.io.uop.pc_lob connect issue_slots[11].uop.edge_inst, slots_11.io.uop.edge_inst connect issue_slots[11].uop.ftq_idx, slots_11.io.uop.ftq_idx connect issue_slots[11].uop.br_tag, slots_11.io.uop.br_tag connect issue_slots[11].uop.br_mask, slots_11.io.uop.br_mask connect issue_slots[11].uop.is_sfb, slots_11.io.uop.is_sfb connect issue_slots[11].uop.is_jal, slots_11.io.uop.is_jal connect issue_slots[11].uop.is_jalr, slots_11.io.uop.is_jalr connect issue_slots[11].uop.is_br, slots_11.io.uop.is_br connect issue_slots[11].uop.iw_p2_poisoned, slots_11.io.uop.iw_p2_poisoned connect issue_slots[11].uop.iw_p1_poisoned, slots_11.io.uop.iw_p1_poisoned connect issue_slots[11].uop.iw_state, slots_11.io.uop.iw_state connect issue_slots[11].uop.ctrl.is_std, slots_11.io.uop.ctrl.is_std connect issue_slots[11].uop.ctrl.is_sta, slots_11.io.uop.ctrl.is_sta connect issue_slots[11].uop.ctrl.is_load, slots_11.io.uop.ctrl.is_load connect issue_slots[11].uop.ctrl.csr_cmd, slots_11.io.uop.ctrl.csr_cmd connect issue_slots[11].uop.ctrl.fcn_dw, slots_11.io.uop.ctrl.fcn_dw connect issue_slots[11].uop.ctrl.op_fcn, slots_11.io.uop.ctrl.op_fcn connect issue_slots[11].uop.ctrl.imm_sel, slots_11.io.uop.ctrl.imm_sel connect issue_slots[11].uop.ctrl.op2_sel, slots_11.io.uop.ctrl.op2_sel connect issue_slots[11].uop.ctrl.op1_sel, slots_11.io.uop.ctrl.op1_sel connect issue_slots[11].uop.ctrl.br_type, slots_11.io.uop.ctrl.br_type connect issue_slots[11].uop.fu_code, slots_11.io.uop.fu_code connect issue_slots[11].uop.iq_type, slots_11.io.uop.iq_type connect issue_slots[11].uop.debug_pc, slots_11.io.uop.debug_pc connect issue_slots[11].uop.is_rvc, slots_11.io.uop.is_rvc connect issue_slots[11].uop.debug_inst, slots_11.io.uop.debug_inst connect issue_slots[11].uop.inst, slots_11.io.uop.inst connect issue_slots[11].uop.uopc, slots_11.io.uop.uopc connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if connect issue_slots[11].out_uop.fp_single, slots_11.io.out_uop.fp_single connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype connect issue_slots[11].out_uop.ldst_val, slots_11.io.out_uop.ldst_val connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3 connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2 connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1 connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1 connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd connect issue_slots[11].out_uop.bypassable, slots_11.io.out_uop.bypassable connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3 connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2 connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1 connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx connect issue_slots[11].out_uop.csr_addr, slots_11.io.out_uop.csr_addr connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb connect issue_slots[11].out_uop.is_jal, slots_11.io.out_uop.is_jal connect issue_slots[11].out_uop.is_jalr, slots_11.io.out_uop.is_jalr connect issue_slots[11].out_uop.is_br, slots_11.io.out_uop.is_br connect issue_slots[11].out_uop.iw_p2_poisoned, slots_11.io.out_uop.iw_p2_poisoned connect issue_slots[11].out_uop.iw_p1_poisoned, slots_11.io.out_uop.iw_p1_poisoned connect issue_slots[11].out_uop.iw_state, slots_11.io.out_uop.iw_state connect issue_slots[11].out_uop.ctrl.is_std, slots_11.io.out_uop.ctrl.is_std connect issue_slots[11].out_uop.ctrl.is_sta, slots_11.io.out_uop.ctrl.is_sta connect issue_slots[11].out_uop.ctrl.is_load, slots_11.io.out_uop.ctrl.is_load connect issue_slots[11].out_uop.ctrl.csr_cmd, slots_11.io.out_uop.ctrl.csr_cmd connect issue_slots[11].out_uop.ctrl.fcn_dw, slots_11.io.out_uop.ctrl.fcn_dw connect issue_slots[11].out_uop.ctrl.op_fcn, slots_11.io.out_uop.ctrl.op_fcn connect issue_slots[11].out_uop.ctrl.imm_sel, slots_11.io.out_uop.ctrl.imm_sel connect issue_slots[11].out_uop.ctrl.op2_sel, slots_11.io.out_uop.ctrl.op2_sel connect issue_slots[11].out_uop.ctrl.op1_sel, slots_11.io.out_uop.ctrl.op1_sel connect issue_slots[11].out_uop.ctrl.br_type, slots_11.io.out_uop.ctrl.br_type connect issue_slots[11].out_uop.fu_code, slots_11.io.out_uop.fu_code connect issue_slots[11].out_uop.iq_type, slots_11.io.out_uop.iq_type connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst connect issue_slots[11].out_uop.uopc, slots_11.io.out_uop.uopc connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if connect slots_11.io.in_uop.bits.fp_single, issue_slots[11].in_uop.bits.fp_single connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype connect slots_11.io.in_uop.bits.ldst_val, issue_slots[11].in_uop.bits.ldst_val connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3 connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2 connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1 connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1 connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd connect slots_11.io.in_uop.bits.bypassable, issue_slots[11].in_uop.bits.bypassable connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3 connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2 connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1 connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx connect slots_11.io.in_uop.bits.csr_addr, issue_slots[11].in_uop.bits.csr_addr connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb connect slots_11.io.in_uop.bits.is_jal, issue_slots[11].in_uop.bits.is_jal connect slots_11.io.in_uop.bits.is_jalr, issue_slots[11].in_uop.bits.is_jalr connect slots_11.io.in_uop.bits.is_br, issue_slots[11].in_uop.bits.is_br connect slots_11.io.in_uop.bits.iw_p2_poisoned, issue_slots[11].in_uop.bits.iw_p2_poisoned connect slots_11.io.in_uop.bits.iw_p1_poisoned, issue_slots[11].in_uop.bits.iw_p1_poisoned connect slots_11.io.in_uop.bits.iw_state, issue_slots[11].in_uop.bits.iw_state connect slots_11.io.in_uop.bits.ctrl.is_std, issue_slots[11].in_uop.bits.ctrl.is_std connect slots_11.io.in_uop.bits.ctrl.is_sta, issue_slots[11].in_uop.bits.ctrl.is_sta connect slots_11.io.in_uop.bits.ctrl.is_load, issue_slots[11].in_uop.bits.ctrl.is_load connect slots_11.io.in_uop.bits.ctrl.csr_cmd, issue_slots[11].in_uop.bits.ctrl.csr_cmd connect slots_11.io.in_uop.bits.ctrl.fcn_dw, issue_slots[11].in_uop.bits.ctrl.fcn_dw connect slots_11.io.in_uop.bits.ctrl.op_fcn, issue_slots[11].in_uop.bits.ctrl.op_fcn connect slots_11.io.in_uop.bits.ctrl.imm_sel, issue_slots[11].in_uop.bits.ctrl.imm_sel connect slots_11.io.in_uop.bits.ctrl.op2_sel, issue_slots[11].in_uop.bits.ctrl.op2_sel connect slots_11.io.in_uop.bits.ctrl.op1_sel, issue_slots[11].in_uop.bits.ctrl.op1_sel connect slots_11.io.in_uop.bits.ctrl.br_type, issue_slots[11].in_uop.bits.ctrl.br_type connect slots_11.io.in_uop.bits.fu_code, issue_slots[11].in_uop.bits.fu_code connect slots_11.io.in_uop.bits.iq_type, issue_slots[11].in_uop.bits.iq_type connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst connect slots_11.io.in_uop.bits.uopc, issue_slots[11].in_uop.bits.uopc connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid connect slots_11.io.spec_ld_wakeup[0].bits, issue_slots[11].spec_ld_wakeup[0].bits connect slots_11.io.spec_ld_wakeup[0].valid, issue_slots[11].spec_ld_wakeup[0].valid connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid connect slots_11.io.wakeup_ports[0].bits.poisoned, issue_slots[11].wakeup_ports[0].bits.poisoned connect slots_11.io.wakeup_ports[0].bits.pdst, issue_slots[11].wakeup_ports[0].bits.pdst connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid connect slots_11.io.wakeup_ports[1].bits.poisoned, issue_slots[11].wakeup_ports[1].bits.poisoned connect slots_11.io.wakeup_ports[1].bits.pdst, issue_slots[11].wakeup_ports[1].bits.pdst connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid connect slots_11.io.wakeup_ports[2].bits.poisoned, issue_slots[11].wakeup_ports[2].bits.poisoned connect slots_11.io.wakeup_ports[2].bits.pdst, issue_slots[11].wakeup_ports[2].bits.pdst connect slots_11.io.wakeup_ports[2].valid, issue_slots[11].wakeup_ports[2].valid connect slots_11.io.wakeup_ports[3].bits.poisoned, issue_slots[11].wakeup_ports[3].bits.poisoned connect slots_11.io.wakeup_ports[3].bits.pdst, issue_slots[11].wakeup_ports[3].bits.pdst connect slots_11.io.wakeup_ports[3].valid, issue_slots[11].wakeup_ports[3].valid connect slots_11.io.wakeup_ports[4].bits.poisoned, issue_slots[11].wakeup_ports[4].bits.poisoned connect slots_11.io.wakeup_ports[4].bits.pdst, issue_slots[11].wakeup_ports[4].bits.pdst connect slots_11.io.wakeup_ports[4].valid, issue_slots[11].wakeup_ports[4].valid connect slots_11.io.wakeup_ports[5].bits.poisoned, issue_slots[11].wakeup_ports[5].bits.poisoned connect slots_11.io.wakeup_ports[5].bits.pdst, issue_slots[11].wakeup_ports[5].bits.pdst connect slots_11.io.wakeup_ports[5].valid, issue_slots[11].wakeup_ports[5].valid connect slots_11.io.wakeup_ports[6].bits.poisoned, issue_slots[11].wakeup_ports[6].bits.poisoned connect slots_11.io.wakeup_ports[6].bits.pdst, issue_slots[11].wakeup_ports[6].bits.pdst connect slots_11.io.wakeup_ports[6].valid, issue_slots[11].wakeup_ports[6].valid connect slots_11.io.ldspec_miss, issue_slots[11].ldspec_miss connect slots_11.io.clear, issue_slots[11].clear connect slots_11.io.kill, issue_slots[11].kill connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict connect slots_11.io.brupdate.b2.valid, issue_slots[11].brupdate.b2.valid connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if connect slots_11.io.brupdate.b2.uop.fp_single, issue_slots[11].brupdate.b2.uop.fp_single connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype connect slots_11.io.brupdate.b2.uop.ldst_val, issue_slots[11].brupdate.b2.uop.ldst_val connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3 connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2 connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1 connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1 connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd connect slots_11.io.brupdate.b2.uop.bypassable, issue_slots[11].brupdate.b2.uop.bypassable connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3 connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2 connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1 connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx connect slots_11.io.brupdate.b2.uop.csr_addr, issue_slots[11].brupdate.b2.uop.csr_addr connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb connect slots_11.io.brupdate.b2.uop.is_jal, issue_slots[11].brupdate.b2.uop.is_jal connect slots_11.io.brupdate.b2.uop.is_jalr, issue_slots[11].brupdate.b2.uop.is_jalr connect slots_11.io.brupdate.b2.uop.is_br, issue_slots[11].brupdate.b2.uop.is_br connect slots_11.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[11].brupdate.b2.uop.iw_p2_poisoned connect slots_11.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[11].brupdate.b2.uop.iw_p1_poisoned connect slots_11.io.brupdate.b2.uop.iw_state, issue_slots[11].brupdate.b2.uop.iw_state connect slots_11.io.brupdate.b2.uop.ctrl.is_std, issue_slots[11].brupdate.b2.uop.ctrl.is_std connect slots_11.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[11].brupdate.b2.uop.ctrl.is_sta connect slots_11.io.brupdate.b2.uop.ctrl.is_load, issue_slots[11].brupdate.b2.uop.ctrl.is_load connect slots_11.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[11].brupdate.b2.uop.ctrl.csr_cmd connect slots_11.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[11].brupdate.b2.uop.ctrl.fcn_dw connect slots_11.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[11].brupdate.b2.uop.ctrl.op_fcn connect slots_11.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[11].brupdate.b2.uop.ctrl.imm_sel connect slots_11.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[11].brupdate.b2.uop.ctrl.op2_sel connect slots_11.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[11].brupdate.b2.uop.ctrl.op1_sel connect slots_11.io.brupdate.b2.uop.ctrl.br_type, issue_slots[11].brupdate.b2.uop.ctrl.br_type connect slots_11.io.brupdate.b2.uop.fu_code, issue_slots[11].brupdate.b2.uop.fu_code connect slots_11.io.brupdate.b2.uop.iq_type, issue_slots[11].brupdate.b2.uop.iq_type connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst connect slots_11.io.brupdate.b2.uop.uopc, issue_slots[11].brupdate.b2.uop.uopc connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask connect slots_11.io.grant, issue_slots[11].grant connect issue_slots[11].request_hp, slots_11.io.request_hp connect issue_slots[11].request, slots_11.io.request connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid connect issue_slots[11].valid, slots_11.io.valid connect issue_slots[12].debug.state, slots_12.io.debug.state connect issue_slots[12].debug.ppred, slots_12.io.debug.ppred connect issue_slots[12].debug.p3, slots_12.io.debug.p3 connect issue_slots[12].debug.p2, slots_12.io.debug.p2 connect issue_slots[12].debug.p1, slots_12.io.debug.p1 connect issue_slots[12].uop.debug_tsrc, slots_12.io.uop.debug_tsrc connect issue_slots[12].uop.debug_fsrc, slots_12.io.uop.debug_fsrc connect issue_slots[12].uop.bp_xcpt_if, slots_12.io.uop.bp_xcpt_if connect issue_slots[12].uop.bp_debug_if, slots_12.io.uop.bp_debug_if connect issue_slots[12].uop.xcpt_ma_if, slots_12.io.uop.xcpt_ma_if connect issue_slots[12].uop.xcpt_ae_if, slots_12.io.uop.xcpt_ae_if connect issue_slots[12].uop.xcpt_pf_if, slots_12.io.uop.xcpt_pf_if connect issue_slots[12].uop.fp_single, slots_12.io.uop.fp_single connect issue_slots[12].uop.fp_val, slots_12.io.uop.fp_val connect issue_slots[12].uop.frs3_en, slots_12.io.uop.frs3_en connect issue_slots[12].uop.lrs2_rtype, slots_12.io.uop.lrs2_rtype connect issue_slots[12].uop.lrs1_rtype, slots_12.io.uop.lrs1_rtype connect issue_slots[12].uop.dst_rtype, slots_12.io.uop.dst_rtype connect issue_slots[12].uop.ldst_val, slots_12.io.uop.ldst_val connect issue_slots[12].uop.lrs3, slots_12.io.uop.lrs3 connect issue_slots[12].uop.lrs2, slots_12.io.uop.lrs2 connect issue_slots[12].uop.lrs1, slots_12.io.uop.lrs1 connect issue_slots[12].uop.ldst, slots_12.io.uop.ldst connect issue_slots[12].uop.ldst_is_rs1, slots_12.io.uop.ldst_is_rs1 connect issue_slots[12].uop.flush_on_commit, slots_12.io.uop.flush_on_commit connect issue_slots[12].uop.is_unique, slots_12.io.uop.is_unique connect issue_slots[12].uop.is_sys_pc2epc, slots_12.io.uop.is_sys_pc2epc connect issue_slots[12].uop.uses_stq, slots_12.io.uop.uses_stq connect issue_slots[12].uop.uses_ldq, slots_12.io.uop.uses_ldq connect issue_slots[12].uop.is_amo, slots_12.io.uop.is_amo connect issue_slots[12].uop.is_fencei, slots_12.io.uop.is_fencei connect issue_slots[12].uop.is_fence, slots_12.io.uop.is_fence connect issue_slots[12].uop.mem_signed, slots_12.io.uop.mem_signed connect issue_slots[12].uop.mem_size, slots_12.io.uop.mem_size connect issue_slots[12].uop.mem_cmd, slots_12.io.uop.mem_cmd connect issue_slots[12].uop.bypassable, slots_12.io.uop.bypassable connect issue_slots[12].uop.exc_cause, slots_12.io.uop.exc_cause connect issue_slots[12].uop.exception, slots_12.io.uop.exception connect issue_slots[12].uop.stale_pdst, slots_12.io.uop.stale_pdst connect issue_slots[12].uop.ppred_busy, slots_12.io.uop.ppred_busy connect issue_slots[12].uop.prs3_busy, slots_12.io.uop.prs3_busy connect issue_slots[12].uop.prs2_busy, slots_12.io.uop.prs2_busy connect issue_slots[12].uop.prs1_busy, slots_12.io.uop.prs1_busy connect issue_slots[12].uop.ppred, slots_12.io.uop.ppred connect issue_slots[12].uop.prs3, slots_12.io.uop.prs3 connect issue_slots[12].uop.prs2, slots_12.io.uop.prs2 connect issue_slots[12].uop.prs1, slots_12.io.uop.prs1 connect issue_slots[12].uop.pdst, slots_12.io.uop.pdst connect issue_slots[12].uop.rxq_idx, slots_12.io.uop.rxq_idx connect issue_slots[12].uop.stq_idx, slots_12.io.uop.stq_idx connect issue_slots[12].uop.ldq_idx, slots_12.io.uop.ldq_idx connect issue_slots[12].uop.rob_idx, slots_12.io.uop.rob_idx connect issue_slots[12].uop.csr_addr, slots_12.io.uop.csr_addr connect issue_slots[12].uop.imm_packed, slots_12.io.uop.imm_packed connect issue_slots[12].uop.taken, slots_12.io.uop.taken connect issue_slots[12].uop.pc_lob, slots_12.io.uop.pc_lob connect issue_slots[12].uop.edge_inst, slots_12.io.uop.edge_inst connect issue_slots[12].uop.ftq_idx, slots_12.io.uop.ftq_idx connect issue_slots[12].uop.br_tag, slots_12.io.uop.br_tag connect issue_slots[12].uop.br_mask, slots_12.io.uop.br_mask connect issue_slots[12].uop.is_sfb, slots_12.io.uop.is_sfb connect issue_slots[12].uop.is_jal, slots_12.io.uop.is_jal connect issue_slots[12].uop.is_jalr, slots_12.io.uop.is_jalr connect issue_slots[12].uop.is_br, slots_12.io.uop.is_br connect issue_slots[12].uop.iw_p2_poisoned, slots_12.io.uop.iw_p2_poisoned connect issue_slots[12].uop.iw_p1_poisoned, slots_12.io.uop.iw_p1_poisoned connect issue_slots[12].uop.iw_state, slots_12.io.uop.iw_state connect issue_slots[12].uop.ctrl.is_std, slots_12.io.uop.ctrl.is_std connect issue_slots[12].uop.ctrl.is_sta, slots_12.io.uop.ctrl.is_sta connect issue_slots[12].uop.ctrl.is_load, slots_12.io.uop.ctrl.is_load connect issue_slots[12].uop.ctrl.csr_cmd, slots_12.io.uop.ctrl.csr_cmd connect issue_slots[12].uop.ctrl.fcn_dw, slots_12.io.uop.ctrl.fcn_dw connect issue_slots[12].uop.ctrl.op_fcn, slots_12.io.uop.ctrl.op_fcn connect issue_slots[12].uop.ctrl.imm_sel, slots_12.io.uop.ctrl.imm_sel connect issue_slots[12].uop.ctrl.op2_sel, slots_12.io.uop.ctrl.op2_sel connect issue_slots[12].uop.ctrl.op1_sel, slots_12.io.uop.ctrl.op1_sel connect issue_slots[12].uop.ctrl.br_type, slots_12.io.uop.ctrl.br_type connect issue_slots[12].uop.fu_code, slots_12.io.uop.fu_code connect issue_slots[12].uop.iq_type, slots_12.io.uop.iq_type connect issue_slots[12].uop.debug_pc, slots_12.io.uop.debug_pc connect issue_slots[12].uop.is_rvc, slots_12.io.uop.is_rvc connect issue_slots[12].uop.debug_inst, slots_12.io.uop.debug_inst connect issue_slots[12].uop.inst, slots_12.io.uop.inst connect issue_slots[12].uop.uopc, slots_12.io.uop.uopc connect issue_slots[12].out_uop.debug_tsrc, slots_12.io.out_uop.debug_tsrc connect issue_slots[12].out_uop.debug_fsrc, slots_12.io.out_uop.debug_fsrc connect issue_slots[12].out_uop.bp_xcpt_if, slots_12.io.out_uop.bp_xcpt_if connect issue_slots[12].out_uop.bp_debug_if, slots_12.io.out_uop.bp_debug_if connect issue_slots[12].out_uop.xcpt_ma_if, slots_12.io.out_uop.xcpt_ma_if connect issue_slots[12].out_uop.xcpt_ae_if, slots_12.io.out_uop.xcpt_ae_if connect issue_slots[12].out_uop.xcpt_pf_if, slots_12.io.out_uop.xcpt_pf_if connect issue_slots[12].out_uop.fp_single, slots_12.io.out_uop.fp_single connect issue_slots[12].out_uop.fp_val, slots_12.io.out_uop.fp_val connect issue_slots[12].out_uop.frs3_en, slots_12.io.out_uop.frs3_en connect issue_slots[12].out_uop.lrs2_rtype, slots_12.io.out_uop.lrs2_rtype connect issue_slots[12].out_uop.lrs1_rtype, slots_12.io.out_uop.lrs1_rtype connect issue_slots[12].out_uop.dst_rtype, slots_12.io.out_uop.dst_rtype connect issue_slots[12].out_uop.ldst_val, slots_12.io.out_uop.ldst_val connect issue_slots[12].out_uop.lrs3, slots_12.io.out_uop.lrs3 connect issue_slots[12].out_uop.lrs2, slots_12.io.out_uop.lrs2 connect issue_slots[12].out_uop.lrs1, slots_12.io.out_uop.lrs1 connect issue_slots[12].out_uop.ldst, slots_12.io.out_uop.ldst connect issue_slots[12].out_uop.ldst_is_rs1, slots_12.io.out_uop.ldst_is_rs1 connect issue_slots[12].out_uop.flush_on_commit, slots_12.io.out_uop.flush_on_commit connect issue_slots[12].out_uop.is_unique, slots_12.io.out_uop.is_unique connect issue_slots[12].out_uop.is_sys_pc2epc, slots_12.io.out_uop.is_sys_pc2epc connect issue_slots[12].out_uop.uses_stq, slots_12.io.out_uop.uses_stq connect issue_slots[12].out_uop.uses_ldq, slots_12.io.out_uop.uses_ldq connect issue_slots[12].out_uop.is_amo, slots_12.io.out_uop.is_amo connect issue_slots[12].out_uop.is_fencei, slots_12.io.out_uop.is_fencei connect issue_slots[12].out_uop.is_fence, slots_12.io.out_uop.is_fence connect issue_slots[12].out_uop.mem_signed, slots_12.io.out_uop.mem_signed connect issue_slots[12].out_uop.mem_size, slots_12.io.out_uop.mem_size connect issue_slots[12].out_uop.mem_cmd, slots_12.io.out_uop.mem_cmd connect issue_slots[12].out_uop.bypassable, slots_12.io.out_uop.bypassable connect issue_slots[12].out_uop.exc_cause, slots_12.io.out_uop.exc_cause connect issue_slots[12].out_uop.exception, slots_12.io.out_uop.exception connect issue_slots[12].out_uop.stale_pdst, slots_12.io.out_uop.stale_pdst connect issue_slots[12].out_uop.ppred_busy, slots_12.io.out_uop.ppred_busy connect issue_slots[12].out_uop.prs3_busy, slots_12.io.out_uop.prs3_busy connect issue_slots[12].out_uop.prs2_busy, slots_12.io.out_uop.prs2_busy connect issue_slots[12].out_uop.prs1_busy, slots_12.io.out_uop.prs1_busy connect issue_slots[12].out_uop.ppred, slots_12.io.out_uop.ppred connect issue_slots[12].out_uop.prs3, slots_12.io.out_uop.prs3 connect issue_slots[12].out_uop.prs2, slots_12.io.out_uop.prs2 connect issue_slots[12].out_uop.prs1, slots_12.io.out_uop.prs1 connect issue_slots[12].out_uop.pdst, slots_12.io.out_uop.pdst connect issue_slots[12].out_uop.rxq_idx, slots_12.io.out_uop.rxq_idx connect issue_slots[12].out_uop.stq_idx, slots_12.io.out_uop.stq_idx connect issue_slots[12].out_uop.ldq_idx, slots_12.io.out_uop.ldq_idx connect issue_slots[12].out_uop.rob_idx, slots_12.io.out_uop.rob_idx connect issue_slots[12].out_uop.csr_addr, slots_12.io.out_uop.csr_addr connect issue_slots[12].out_uop.imm_packed, slots_12.io.out_uop.imm_packed connect issue_slots[12].out_uop.taken, slots_12.io.out_uop.taken connect issue_slots[12].out_uop.pc_lob, slots_12.io.out_uop.pc_lob connect issue_slots[12].out_uop.edge_inst, slots_12.io.out_uop.edge_inst connect issue_slots[12].out_uop.ftq_idx, slots_12.io.out_uop.ftq_idx connect issue_slots[12].out_uop.br_tag, slots_12.io.out_uop.br_tag connect issue_slots[12].out_uop.br_mask, slots_12.io.out_uop.br_mask connect issue_slots[12].out_uop.is_sfb, slots_12.io.out_uop.is_sfb connect issue_slots[12].out_uop.is_jal, slots_12.io.out_uop.is_jal connect issue_slots[12].out_uop.is_jalr, slots_12.io.out_uop.is_jalr connect issue_slots[12].out_uop.is_br, slots_12.io.out_uop.is_br connect issue_slots[12].out_uop.iw_p2_poisoned, slots_12.io.out_uop.iw_p2_poisoned connect issue_slots[12].out_uop.iw_p1_poisoned, slots_12.io.out_uop.iw_p1_poisoned connect issue_slots[12].out_uop.iw_state, slots_12.io.out_uop.iw_state connect issue_slots[12].out_uop.ctrl.is_std, slots_12.io.out_uop.ctrl.is_std connect issue_slots[12].out_uop.ctrl.is_sta, slots_12.io.out_uop.ctrl.is_sta connect issue_slots[12].out_uop.ctrl.is_load, slots_12.io.out_uop.ctrl.is_load connect issue_slots[12].out_uop.ctrl.csr_cmd, slots_12.io.out_uop.ctrl.csr_cmd connect issue_slots[12].out_uop.ctrl.fcn_dw, slots_12.io.out_uop.ctrl.fcn_dw connect issue_slots[12].out_uop.ctrl.op_fcn, slots_12.io.out_uop.ctrl.op_fcn connect issue_slots[12].out_uop.ctrl.imm_sel, slots_12.io.out_uop.ctrl.imm_sel connect issue_slots[12].out_uop.ctrl.op2_sel, slots_12.io.out_uop.ctrl.op2_sel connect issue_slots[12].out_uop.ctrl.op1_sel, slots_12.io.out_uop.ctrl.op1_sel connect issue_slots[12].out_uop.ctrl.br_type, slots_12.io.out_uop.ctrl.br_type connect issue_slots[12].out_uop.fu_code, slots_12.io.out_uop.fu_code connect issue_slots[12].out_uop.iq_type, slots_12.io.out_uop.iq_type connect issue_slots[12].out_uop.debug_pc, slots_12.io.out_uop.debug_pc connect issue_slots[12].out_uop.is_rvc, slots_12.io.out_uop.is_rvc connect issue_slots[12].out_uop.debug_inst, slots_12.io.out_uop.debug_inst connect issue_slots[12].out_uop.inst, slots_12.io.out_uop.inst connect issue_slots[12].out_uop.uopc, slots_12.io.out_uop.uopc connect slots_12.io.in_uop.bits.debug_tsrc, issue_slots[12].in_uop.bits.debug_tsrc connect slots_12.io.in_uop.bits.debug_fsrc, issue_slots[12].in_uop.bits.debug_fsrc connect slots_12.io.in_uop.bits.bp_xcpt_if, issue_slots[12].in_uop.bits.bp_xcpt_if connect slots_12.io.in_uop.bits.bp_debug_if, issue_slots[12].in_uop.bits.bp_debug_if connect slots_12.io.in_uop.bits.xcpt_ma_if, issue_slots[12].in_uop.bits.xcpt_ma_if connect slots_12.io.in_uop.bits.xcpt_ae_if, issue_slots[12].in_uop.bits.xcpt_ae_if connect slots_12.io.in_uop.bits.xcpt_pf_if, issue_slots[12].in_uop.bits.xcpt_pf_if connect slots_12.io.in_uop.bits.fp_single, issue_slots[12].in_uop.bits.fp_single connect slots_12.io.in_uop.bits.fp_val, issue_slots[12].in_uop.bits.fp_val connect slots_12.io.in_uop.bits.frs3_en, issue_slots[12].in_uop.bits.frs3_en connect slots_12.io.in_uop.bits.lrs2_rtype, issue_slots[12].in_uop.bits.lrs2_rtype connect slots_12.io.in_uop.bits.lrs1_rtype, issue_slots[12].in_uop.bits.lrs1_rtype connect slots_12.io.in_uop.bits.dst_rtype, issue_slots[12].in_uop.bits.dst_rtype connect slots_12.io.in_uop.bits.ldst_val, issue_slots[12].in_uop.bits.ldst_val connect slots_12.io.in_uop.bits.lrs3, issue_slots[12].in_uop.bits.lrs3 connect slots_12.io.in_uop.bits.lrs2, issue_slots[12].in_uop.bits.lrs2 connect slots_12.io.in_uop.bits.lrs1, issue_slots[12].in_uop.bits.lrs1 connect slots_12.io.in_uop.bits.ldst, issue_slots[12].in_uop.bits.ldst connect slots_12.io.in_uop.bits.ldst_is_rs1, issue_slots[12].in_uop.bits.ldst_is_rs1 connect slots_12.io.in_uop.bits.flush_on_commit, issue_slots[12].in_uop.bits.flush_on_commit connect slots_12.io.in_uop.bits.is_unique, issue_slots[12].in_uop.bits.is_unique connect slots_12.io.in_uop.bits.is_sys_pc2epc, issue_slots[12].in_uop.bits.is_sys_pc2epc connect slots_12.io.in_uop.bits.uses_stq, issue_slots[12].in_uop.bits.uses_stq connect slots_12.io.in_uop.bits.uses_ldq, issue_slots[12].in_uop.bits.uses_ldq connect slots_12.io.in_uop.bits.is_amo, issue_slots[12].in_uop.bits.is_amo connect slots_12.io.in_uop.bits.is_fencei, issue_slots[12].in_uop.bits.is_fencei connect slots_12.io.in_uop.bits.is_fence, issue_slots[12].in_uop.bits.is_fence connect slots_12.io.in_uop.bits.mem_signed, issue_slots[12].in_uop.bits.mem_signed connect slots_12.io.in_uop.bits.mem_size, issue_slots[12].in_uop.bits.mem_size connect slots_12.io.in_uop.bits.mem_cmd, issue_slots[12].in_uop.bits.mem_cmd connect slots_12.io.in_uop.bits.bypassable, issue_slots[12].in_uop.bits.bypassable connect slots_12.io.in_uop.bits.exc_cause, issue_slots[12].in_uop.bits.exc_cause connect slots_12.io.in_uop.bits.exception, issue_slots[12].in_uop.bits.exception connect slots_12.io.in_uop.bits.stale_pdst, issue_slots[12].in_uop.bits.stale_pdst connect slots_12.io.in_uop.bits.ppred_busy, issue_slots[12].in_uop.bits.ppred_busy connect slots_12.io.in_uop.bits.prs3_busy, issue_slots[12].in_uop.bits.prs3_busy connect slots_12.io.in_uop.bits.prs2_busy, issue_slots[12].in_uop.bits.prs2_busy connect slots_12.io.in_uop.bits.prs1_busy, issue_slots[12].in_uop.bits.prs1_busy connect slots_12.io.in_uop.bits.ppred, issue_slots[12].in_uop.bits.ppred connect slots_12.io.in_uop.bits.prs3, issue_slots[12].in_uop.bits.prs3 connect slots_12.io.in_uop.bits.prs2, issue_slots[12].in_uop.bits.prs2 connect slots_12.io.in_uop.bits.prs1, issue_slots[12].in_uop.bits.prs1 connect slots_12.io.in_uop.bits.pdst, issue_slots[12].in_uop.bits.pdst connect slots_12.io.in_uop.bits.rxq_idx, issue_slots[12].in_uop.bits.rxq_idx connect slots_12.io.in_uop.bits.stq_idx, issue_slots[12].in_uop.bits.stq_idx connect slots_12.io.in_uop.bits.ldq_idx, issue_slots[12].in_uop.bits.ldq_idx connect slots_12.io.in_uop.bits.rob_idx, issue_slots[12].in_uop.bits.rob_idx connect slots_12.io.in_uop.bits.csr_addr, issue_slots[12].in_uop.bits.csr_addr connect slots_12.io.in_uop.bits.imm_packed, issue_slots[12].in_uop.bits.imm_packed connect slots_12.io.in_uop.bits.taken, issue_slots[12].in_uop.bits.taken connect slots_12.io.in_uop.bits.pc_lob, issue_slots[12].in_uop.bits.pc_lob connect slots_12.io.in_uop.bits.edge_inst, issue_slots[12].in_uop.bits.edge_inst connect slots_12.io.in_uop.bits.ftq_idx, issue_slots[12].in_uop.bits.ftq_idx connect slots_12.io.in_uop.bits.br_tag, issue_slots[12].in_uop.bits.br_tag connect slots_12.io.in_uop.bits.br_mask, issue_slots[12].in_uop.bits.br_mask connect slots_12.io.in_uop.bits.is_sfb, issue_slots[12].in_uop.bits.is_sfb connect slots_12.io.in_uop.bits.is_jal, issue_slots[12].in_uop.bits.is_jal connect slots_12.io.in_uop.bits.is_jalr, issue_slots[12].in_uop.bits.is_jalr connect slots_12.io.in_uop.bits.is_br, issue_slots[12].in_uop.bits.is_br connect slots_12.io.in_uop.bits.iw_p2_poisoned, issue_slots[12].in_uop.bits.iw_p2_poisoned connect slots_12.io.in_uop.bits.iw_p1_poisoned, issue_slots[12].in_uop.bits.iw_p1_poisoned connect slots_12.io.in_uop.bits.iw_state, issue_slots[12].in_uop.bits.iw_state connect slots_12.io.in_uop.bits.ctrl.is_std, issue_slots[12].in_uop.bits.ctrl.is_std connect slots_12.io.in_uop.bits.ctrl.is_sta, issue_slots[12].in_uop.bits.ctrl.is_sta connect slots_12.io.in_uop.bits.ctrl.is_load, issue_slots[12].in_uop.bits.ctrl.is_load connect slots_12.io.in_uop.bits.ctrl.csr_cmd, issue_slots[12].in_uop.bits.ctrl.csr_cmd connect slots_12.io.in_uop.bits.ctrl.fcn_dw, issue_slots[12].in_uop.bits.ctrl.fcn_dw connect slots_12.io.in_uop.bits.ctrl.op_fcn, issue_slots[12].in_uop.bits.ctrl.op_fcn connect slots_12.io.in_uop.bits.ctrl.imm_sel, issue_slots[12].in_uop.bits.ctrl.imm_sel connect slots_12.io.in_uop.bits.ctrl.op2_sel, issue_slots[12].in_uop.bits.ctrl.op2_sel connect slots_12.io.in_uop.bits.ctrl.op1_sel, issue_slots[12].in_uop.bits.ctrl.op1_sel connect slots_12.io.in_uop.bits.ctrl.br_type, issue_slots[12].in_uop.bits.ctrl.br_type connect slots_12.io.in_uop.bits.fu_code, issue_slots[12].in_uop.bits.fu_code connect slots_12.io.in_uop.bits.iq_type, issue_slots[12].in_uop.bits.iq_type connect slots_12.io.in_uop.bits.debug_pc, issue_slots[12].in_uop.bits.debug_pc connect slots_12.io.in_uop.bits.is_rvc, issue_slots[12].in_uop.bits.is_rvc connect slots_12.io.in_uop.bits.debug_inst, issue_slots[12].in_uop.bits.debug_inst connect slots_12.io.in_uop.bits.inst, issue_slots[12].in_uop.bits.inst connect slots_12.io.in_uop.bits.uopc, issue_slots[12].in_uop.bits.uopc connect slots_12.io.in_uop.valid, issue_slots[12].in_uop.valid connect slots_12.io.spec_ld_wakeup[0].bits, issue_slots[12].spec_ld_wakeup[0].bits connect slots_12.io.spec_ld_wakeup[0].valid, issue_slots[12].spec_ld_wakeup[0].valid connect slots_12.io.pred_wakeup_port.bits, issue_slots[12].pred_wakeup_port.bits connect slots_12.io.pred_wakeup_port.valid, issue_slots[12].pred_wakeup_port.valid connect slots_12.io.wakeup_ports[0].bits.poisoned, issue_slots[12].wakeup_ports[0].bits.poisoned connect slots_12.io.wakeup_ports[0].bits.pdst, issue_slots[12].wakeup_ports[0].bits.pdst connect slots_12.io.wakeup_ports[0].valid, issue_slots[12].wakeup_ports[0].valid connect slots_12.io.wakeup_ports[1].bits.poisoned, issue_slots[12].wakeup_ports[1].bits.poisoned connect slots_12.io.wakeup_ports[1].bits.pdst, issue_slots[12].wakeup_ports[1].bits.pdst connect slots_12.io.wakeup_ports[1].valid, issue_slots[12].wakeup_ports[1].valid connect slots_12.io.wakeup_ports[2].bits.poisoned, issue_slots[12].wakeup_ports[2].bits.poisoned connect slots_12.io.wakeup_ports[2].bits.pdst, issue_slots[12].wakeup_ports[2].bits.pdst connect slots_12.io.wakeup_ports[2].valid, issue_slots[12].wakeup_ports[2].valid connect slots_12.io.wakeup_ports[3].bits.poisoned, issue_slots[12].wakeup_ports[3].bits.poisoned connect slots_12.io.wakeup_ports[3].bits.pdst, issue_slots[12].wakeup_ports[3].bits.pdst connect slots_12.io.wakeup_ports[3].valid, issue_slots[12].wakeup_ports[3].valid connect slots_12.io.wakeup_ports[4].bits.poisoned, issue_slots[12].wakeup_ports[4].bits.poisoned connect slots_12.io.wakeup_ports[4].bits.pdst, issue_slots[12].wakeup_ports[4].bits.pdst connect slots_12.io.wakeup_ports[4].valid, issue_slots[12].wakeup_ports[4].valid connect slots_12.io.wakeup_ports[5].bits.poisoned, issue_slots[12].wakeup_ports[5].bits.poisoned connect slots_12.io.wakeup_ports[5].bits.pdst, issue_slots[12].wakeup_ports[5].bits.pdst connect slots_12.io.wakeup_ports[5].valid, issue_slots[12].wakeup_ports[5].valid connect slots_12.io.wakeup_ports[6].bits.poisoned, issue_slots[12].wakeup_ports[6].bits.poisoned connect slots_12.io.wakeup_ports[6].bits.pdst, issue_slots[12].wakeup_ports[6].bits.pdst connect slots_12.io.wakeup_ports[6].valid, issue_slots[12].wakeup_ports[6].valid connect slots_12.io.ldspec_miss, issue_slots[12].ldspec_miss connect slots_12.io.clear, issue_slots[12].clear connect slots_12.io.kill, issue_slots[12].kill connect slots_12.io.brupdate.b2.target_offset, issue_slots[12].brupdate.b2.target_offset connect slots_12.io.brupdate.b2.jalr_target, issue_slots[12].brupdate.b2.jalr_target connect slots_12.io.brupdate.b2.pc_sel, issue_slots[12].brupdate.b2.pc_sel connect slots_12.io.brupdate.b2.cfi_type, issue_slots[12].brupdate.b2.cfi_type connect slots_12.io.brupdate.b2.taken, issue_slots[12].brupdate.b2.taken connect slots_12.io.brupdate.b2.mispredict, issue_slots[12].brupdate.b2.mispredict connect slots_12.io.brupdate.b2.valid, issue_slots[12].brupdate.b2.valid connect slots_12.io.brupdate.b2.uop.debug_tsrc, issue_slots[12].brupdate.b2.uop.debug_tsrc connect slots_12.io.brupdate.b2.uop.debug_fsrc, issue_slots[12].brupdate.b2.uop.debug_fsrc connect slots_12.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[12].brupdate.b2.uop.bp_xcpt_if connect slots_12.io.brupdate.b2.uop.bp_debug_if, issue_slots[12].brupdate.b2.uop.bp_debug_if connect slots_12.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[12].brupdate.b2.uop.xcpt_ma_if connect slots_12.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[12].brupdate.b2.uop.xcpt_ae_if connect slots_12.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[12].brupdate.b2.uop.xcpt_pf_if connect slots_12.io.brupdate.b2.uop.fp_single, issue_slots[12].brupdate.b2.uop.fp_single connect slots_12.io.brupdate.b2.uop.fp_val, issue_slots[12].brupdate.b2.uop.fp_val connect slots_12.io.brupdate.b2.uop.frs3_en, issue_slots[12].brupdate.b2.uop.frs3_en connect slots_12.io.brupdate.b2.uop.lrs2_rtype, issue_slots[12].brupdate.b2.uop.lrs2_rtype connect slots_12.io.brupdate.b2.uop.lrs1_rtype, issue_slots[12].brupdate.b2.uop.lrs1_rtype connect slots_12.io.brupdate.b2.uop.dst_rtype, issue_slots[12].brupdate.b2.uop.dst_rtype connect slots_12.io.brupdate.b2.uop.ldst_val, issue_slots[12].brupdate.b2.uop.ldst_val connect slots_12.io.brupdate.b2.uop.lrs3, issue_slots[12].brupdate.b2.uop.lrs3 connect slots_12.io.brupdate.b2.uop.lrs2, issue_slots[12].brupdate.b2.uop.lrs2 connect slots_12.io.brupdate.b2.uop.lrs1, issue_slots[12].brupdate.b2.uop.lrs1 connect slots_12.io.brupdate.b2.uop.ldst, issue_slots[12].brupdate.b2.uop.ldst connect slots_12.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[12].brupdate.b2.uop.ldst_is_rs1 connect slots_12.io.brupdate.b2.uop.flush_on_commit, issue_slots[12].brupdate.b2.uop.flush_on_commit connect slots_12.io.brupdate.b2.uop.is_unique, issue_slots[12].brupdate.b2.uop.is_unique connect slots_12.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[12].brupdate.b2.uop.is_sys_pc2epc connect slots_12.io.brupdate.b2.uop.uses_stq, issue_slots[12].brupdate.b2.uop.uses_stq connect slots_12.io.brupdate.b2.uop.uses_ldq, issue_slots[12].brupdate.b2.uop.uses_ldq connect slots_12.io.brupdate.b2.uop.is_amo, issue_slots[12].brupdate.b2.uop.is_amo connect slots_12.io.brupdate.b2.uop.is_fencei, issue_slots[12].brupdate.b2.uop.is_fencei connect slots_12.io.brupdate.b2.uop.is_fence, issue_slots[12].brupdate.b2.uop.is_fence connect slots_12.io.brupdate.b2.uop.mem_signed, issue_slots[12].brupdate.b2.uop.mem_signed connect slots_12.io.brupdate.b2.uop.mem_size, issue_slots[12].brupdate.b2.uop.mem_size connect slots_12.io.brupdate.b2.uop.mem_cmd, issue_slots[12].brupdate.b2.uop.mem_cmd connect slots_12.io.brupdate.b2.uop.bypassable, issue_slots[12].brupdate.b2.uop.bypassable connect slots_12.io.brupdate.b2.uop.exc_cause, issue_slots[12].brupdate.b2.uop.exc_cause connect slots_12.io.brupdate.b2.uop.exception, issue_slots[12].brupdate.b2.uop.exception connect slots_12.io.brupdate.b2.uop.stale_pdst, issue_slots[12].brupdate.b2.uop.stale_pdst connect slots_12.io.brupdate.b2.uop.ppred_busy, issue_slots[12].brupdate.b2.uop.ppred_busy connect slots_12.io.brupdate.b2.uop.prs3_busy, issue_slots[12].brupdate.b2.uop.prs3_busy connect slots_12.io.brupdate.b2.uop.prs2_busy, issue_slots[12].brupdate.b2.uop.prs2_busy connect slots_12.io.brupdate.b2.uop.prs1_busy, issue_slots[12].brupdate.b2.uop.prs1_busy connect slots_12.io.brupdate.b2.uop.ppred, issue_slots[12].brupdate.b2.uop.ppred connect slots_12.io.brupdate.b2.uop.prs3, issue_slots[12].brupdate.b2.uop.prs3 connect slots_12.io.brupdate.b2.uop.prs2, issue_slots[12].brupdate.b2.uop.prs2 connect slots_12.io.brupdate.b2.uop.prs1, issue_slots[12].brupdate.b2.uop.prs1 connect slots_12.io.brupdate.b2.uop.pdst, issue_slots[12].brupdate.b2.uop.pdst connect slots_12.io.brupdate.b2.uop.rxq_idx, issue_slots[12].brupdate.b2.uop.rxq_idx connect slots_12.io.brupdate.b2.uop.stq_idx, issue_slots[12].brupdate.b2.uop.stq_idx connect slots_12.io.brupdate.b2.uop.ldq_idx, issue_slots[12].brupdate.b2.uop.ldq_idx connect slots_12.io.brupdate.b2.uop.rob_idx, issue_slots[12].brupdate.b2.uop.rob_idx connect slots_12.io.brupdate.b2.uop.csr_addr, issue_slots[12].brupdate.b2.uop.csr_addr connect slots_12.io.brupdate.b2.uop.imm_packed, issue_slots[12].brupdate.b2.uop.imm_packed connect slots_12.io.brupdate.b2.uop.taken, issue_slots[12].brupdate.b2.uop.taken connect slots_12.io.brupdate.b2.uop.pc_lob, issue_slots[12].brupdate.b2.uop.pc_lob connect slots_12.io.brupdate.b2.uop.edge_inst, issue_slots[12].brupdate.b2.uop.edge_inst connect slots_12.io.brupdate.b2.uop.ftq_idx, issue_slots[12].brupdate.b2.uop.ftq_idx connect slots_12.io.brupdate.b2.uop.br_tag, issue_slots[12].brupdate.b2.uop.br_tag connect slots_12.io.brupdate.b2.uop.br_mask, issue_slots[12].brupdate.b2.uop.br_mask connect slots_12.io.brupdate.b2.uop.is_sfb, issue_slots[12].brupdate.b2.uop.is_sfb connect slots_12.io.brupdate.b2.uop.is_jal, issue_slots[12].brupdate.b2.uop.is_jal connect slots_12.io.brupdate.b2.uop.is_jalr, issue_slots[12].brupdate.b2.uop.is_jalr connect slots_12.io.brupdate.b2.uop.is_br, issue_slots[12].brupdate.b2.uop.is_br connect slots_12.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[12].brupdate.b2.uop.iw_p2_poisoned connect slots_12.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[12].brupdate.b2.uop.iw_p1_poisoned connect slots_12.io.brupdate.b2.uop.iw_state, issue_slots[12].brupdate.b2.uop.iw_state connect slots_12.io.brupdate.b2.uop.ctrl.is_std, issue_slots[12].brupdate.b2.uop.ctrl.is_std connect slots_12.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[12].brupdate.b2.uop.ctrl.is_sta connect slots_12.io.brupdate.b2.uop.ctrl.is_load, issue_slots[12].brupdate.b2.uop.ctrl.is_load connect slots_12.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[12].brupdate.b2.uop.ctrl.csr_cmd connect slots_12.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[12].brupdate.b2.uop.ctrl.fcn_dw connect slots_12.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[12].brupdate.b2.uop.ctrl.op_fcn connect slots_12.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[12].brupdate.b2.uop.ctrl.imm_sel connect slots_12.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[12].brupdate.b2.uop.ctrl.op2_sel connect slots_12.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[12].brupdate.b2.uop.ctrl.op1_sel connect slots_12.io.brupdate.b2.uop.ctrl.br_type, issue_slots[12].brupdate.b2.uop.ctrl.br_type connect slots_12.io.brupdate.b2.uop.fu_code, issue_slots[12].brupdate.b2.uop.fu_code connect slots_12.io.brupdate.b2.uop.iq_type, issue_slots[12].brupdate.b2.uop.iq_type connect slots_12.io.brupdate.b2.uop.debug_pc, issue_slots[12].brupdate.b2.uop.debug_pc connect slots_12.io.brupdate.b2.uop.is_rvc, issue_slots[12].brupdate.b2.uop.is_rvc connect slots_12.io.brupdate.b2.uop.debug_inst, issue_slots[12].brupdate.b2.uop.debug_inst connect slots_12.io.brupdate.b2.uop.inst, issue_slots[12].brupdate.b2.uop.inst connect slots_12.io.brupdate.b2.uop.uopc, issue_slots[12].brupdate.b2.uop.uopc connect slots_12.io.brupdate.b1.mispredict_mask, issue_slots[12].brupdate.b1.mispredict_mask connect slots_12.io.brupdate.b1.resolve_mask, issue_slots[12].brupdate.b1.resolve_mask connect slots_12.io.grant, issue_slots[12].grant connect issue_slots[12].request_hp, slots_12.io.request_hp connect issue_slots[12].request, slots_12.io.request connect issue_slots[12].will_be_valid, slots_12.io.will_be_valid connect issue_slots[12].valid, slots_12.io.valid connect issue_slots[13].debug.state, slots_13.io.debug.state connect issue_slots[13].debug.ppred, slots_13.io.debug.ppred connect issue_slots[13].debug.p3, slots_13.io.debug.p3 connect issue_slots[13].debug.p2, slots_13.io.debug.p2 connect issue_slots[13].debug.p1, slots_13.io.debug.p1 connect issue_slots[13].uop.debug_tsrc, slots_13.io.uop.debug_tsrc connect issue_slots[13].uop.debug_fsrc, slots_13.io.uop.debug_fsrc connect issue_slots[13].uop.bp_xcpt_if, slots_13.io.uop.bp_xcpt_if connect issue_slots[13].uop.bp_debug_if, slots_13.io.uop.bp_debug_if connect issue_slots[13].uop.xcpt_ma_if, slots_13.io.uop.xcpt_ma_if connect issue_slots[13].uop.xcpt_ae_if, slots_13.io.uop.xcpt_ae_if connect issue_slots[13].uop.xcpt_pf_if, slots_13.io.uop.xcpt_pf_if connect issue_slots[13].uop.fp_single, slots_13.io.uop.fp_single connect issue_slots[13].uop.fp_val, slots_13.io.uop.fp_val connect issue_slots[13].uop.frs3_en, slots_13.io.uop.frs3_en connect issue_slots[13].uop.lrs2_rtype, slots_13.io.uop.lrs2_rtype connect issue_slots[13].uop.lrs1_rtype, slots_13.io.uop.lrs1_rtype connect issue_slots[13].uop.dst_rtype, slots_13.io.uop.dst_rtype connect issue_slots[13].uop.ldst_val, slots_13.io.uop.ldst_val connect issue_slots[13].uop.lrs3, slots_13.io.uop.lrs3 connect issue_slots[13].uop.lrs2, slots_13.io.uop.lrs2 connect issue_slots[13].uop.lrs1, slots_13.io.uop.lrs1 connect issue_slots[13].uop.ldst, slots_13.io.uop.ldst connect issue_slots[13].uop.ldst_is_rs1, slots_13.io.uop.ldst_is_rs1 connect issue_slots[13].uop.flush_on_commit, slots_13.io.uop.flush_on_commit connect issue_slots[13].uop.is_unique, slots_13.io.uop.is_unique connect issue_slots[13].uop.is_sys_pc2epc, slots_13.io.uop.is_sys_pc2epc connect issue_slots[13].uop.uses_stq, slots_13.io.uop.uses_stq connect issue_slots[13].uop.uses_ldq, slots_13.io.uop.uses_ldq connect issue_slots[13].uop.is_amo, slots_13.io.uop.is_amo connect issue_slots[13].uop.is_fencei, slots_13.io.uop.is_fencei connect issue_slots[13].uop.is_fence, slots_13.io.uop.is_fence connect issue_slots[13].uop.mem_signed, slots_13.io.uop.mem_signed connect issue_slots[13].uop.mem_size, slots_13.io.uop.mem_size connect issue_slots[13].uop.mem_cmd, slots_13.io.uop.mem_cmd connect issue_slots[13].uop.bypassable, slots_13.io.uop.bypassable connect issue_slots[13].uop.exc_cause, slots_13.io.uop.exc_cause connect issue_slots[13].uop.exception, slots_13.io.uop.exception connect issue_slots[13].uop.stale_pdst, slots_13.io.uop.stale_pdst connect issue_slots[13].uop.ppred_busy, slots_13.io.uop.ppred_busy connect issue_slots[13].uop.prs3_busy, slots_13.io.uop.prs3_busy connect issue_slots[13].uop.prs2_busy, slots_13.io.uop.prs2_busy connect issue_slots[13].uop.prs1_busy, slots_13.io.uop.prs1_busy connect issue_slots[13].uop.ppred, slots_13.io.uop.ppred connect issue_slots[13].uop.prs3, slots_13.io.uop.prs3 connect issue_slots[13].uop.prs2, slots_13.io.uop.prs2 connect issue_slots[13].uop.prs1, slots_13.io.uop.prs1 connect issue_slots[13].uop.pdst, slots_13.io.uop.pdst connect issue_slots[13].uop.rxq_idx, slots_13.io.uop.rxq_idx connect issue_slots[13].uop.stq_idx, slots_13.io.uop.stq_idx connect issue_slots[13].uop.ldq_idx, slots_13.io.uop.ldq_idx connect issue_slots[13].uop.rob_idx, slots_13.io.uop.rob_idx connect issue_slots[13].uop.csr_addr, slots_13.io.uop.csr_addr connect issue_slots[13].uop.imm_packed, slots_13.io.uop.imm_packed connect issue_slots[13].uop.taken, slots_13.io.uop.taken connect issue_slots[13].uop.pc_lob, slots_13.io.uop.pc_lob connect issue_slots[13].uop.edge_inst, slots_13.io.uop.edge_inst connect issue_slots[13].uop.ftq_idx, slots_13.io.uop.ftq_idx connect issue_slots[13].uop.br_tag, slots_13.io.uop.br_tag connect issue_slots[13].uop.br_mask, slots_13.io.uop.br_mask connect issue_slots[13].uop.is_sfb, slots_13.io.uop.is_sfb connect issue_slots[13].uop.is_jal, slots_13.io.uop.is_jal connect issue_slots[13].uop.is_jalr, slots_13.io.uop.is_jalr connect issue_slots[13].uop.is_br, slots_13.io.uop.is_br connect issue_slots[13].uop.iw_p2_poisoned, slots_13.io.uop.iw_p2_poisoned connect issue_slots[13].uop.iw_p1_poisoned, slots_13.io.uop.iw_p1_poisoned connect issue_slots[13].uop.iw_state, slots_13.io.uop.iw_state connect issue_slots[13].uop.ctrl.is_std, slots_13.io.uop.ctrl.is_std connect issue_slots[13].uop.ctrl.is_sta, slots_13.io.uop.ctrl.is_sta connect issue_slots[13].uop.ctrl.is_load, slots_13.io.uop.ctrl.is_load connect issue_slots[13].uop.ctrl.csr_cmd, slots_13.io.uop.ctrl.csr_cmd connect issue_slots[13].uop.ctrl.fcn_dw, slots_13.io.uop.ctrl.fcn_dw connect issue_slots[13].uop.ctrl.op_fcn, slots_13.io.uop.ctrl.op_fcn connect issue_slots[13].uop.ctrl.imm_sel, slots_13.io.uop.ctrl.imm_sel connect issue_slots[13].uop.ctrl.op2_sel, slots_13.io.uop.ctrl.op2_sel connect issue_slots[13].uop.ctrl.op1_sel, slots_13.io.uop.ctrl.op1_sel connect issue_slots[13].uop.ctrl.br_type, slots_13.io.uop.ctrl.br_type connect issue_slots[13].uop.fu_code, slots_13.io.uop.fu_code connect issue_slots[13].uop.iq_type, slots_13.io.uop.iq_type connect issue_slots[13].uop.debug_pc, slots_13.io.uop.debug_pc connect issue_slots[13].uop.is_rvc, slots_13.io.uop.is_rvc connect issue_slots[13].uop.debug_inst, slots_13.io.uop.debug_inst connect issue_slots[13].uop.inst, slots_13.io.uop.inst connect issue_slots[13].uop.uopc, slots_13.io.uop.uopc connect issue_slots[13].out_uop.debug_tsrc, slots_13.io.out_uop.debug_tsrc connect issue_slots[13].out_uop.debug_fsrc, slots_13.io.out_uop.debug_fsrc connect issue_slots[13].out_uop.bp_xcpt_if, slots_13.io.out_uop.bp_xcpt_if connect issue_slots[13].out_uop.bp_debug_if, slots_13.io.out_uop.bp_debug_if connect issue_slots[13].out_uop.xcpt_ma_if, slots_13.io.out_uop.xcpt_ma_if connect issue_slots[13].out_uop.xcpt_ae_if, slots_13.io.out_uop.xcpt_ae_if connect issue_slots[13].out_uop.xcpt_pf_if, slots_13.io.out_uop.xcpt_pf_if connect issue_slots[13].out_uop.fp_single, slots_13.io.out_uop.fp_single connect issue_slots[13].out_uop.fp_val, slots_13.io.out_uop.fp_val connect issue_slots[13].out_uop.frs3_en, slots_13.io.out_uop.frs3_en connect issue_slots[13].out_uop.lrs2_rtype, slots_13.io.out_uop.lrs2_rtype connect issue_slots[13].out_uop.lrs1_rtype, slots_13.io.out_uop.lrs1_rtype connect issue_slots[13].out_uop.dst_rtype, slots_13.io.out_uop.dst_rtype connect issue_slots[13].out_uop.ldst_val, slots_13.io.out_uop.ldst_val connect issue_slots[13].out_uop.lrs3, slots_13.io.out_uop.lrs3 connect issue_slots[13].out_uop.lrs2, slots_13.io.out_uop.lrs2 connect issue_slots[13].out_uop.lrs1, slots_13.io.out_uop.lrs1 connect issue_slots[13].out_uop.ldst, slots_13.io.out_uop.ldst connect issue_slots[13].out_uop.ldst_is_rs1, slots_13.io.out_uop.ldst_is_rs1 connect issue_slots[13].out_uop.flush_on_commit, slots_13.io.out_uop.flush_on_commit connect issue_slots[13].out_uop.is_unique, slots_13.io.out_uop.is_unique connect issue_slots[13].out_uop.is_sys_pc2epc, slots_13.io.out_uop.is_sys_pc2epc connect issue_slots[13].out_uop.uses_stq, slots_13.io.out_uop.uses_stq connect issue_slots[13].out_uop.uses_ldq, slots_13.io.out_uop.uses_ldq connect issue_slots[13].out_uop.is_amo, slots_13.io.out_uop.is_amo connect issue_slots[13].out_uop.is_fencei, slots_13.io.out_uop.is_fencei connect issue_slots[13].out_uop.is_fence, slots_13.io.out_uop.is_fence connect issue_slots[13].out_uop.mem_signed, slots_13.io.out_uop.mem_signed connect issue_slots[13].out_uop.mem_size, slots_13.io.out_uop.mem_size connect issue_slots[13].out_uop.mem_cmd, slots_13.io.out_uop.mem_cmd connect issue_slots[13].out_uop.bypassable, slots_13.io.out_uop.bypassable connect issue_slots[13].out_uop.exc_cause, slots_13.io.out_uop.exc_cause connect issue_slots[13].out_uop.exception, slots_13.io.out_uop.exception connect issue_slots[13].out_uop.stale_pdst, slots_13.io.out_uop.stale_pdst connect issue_slots[13].out_uop.ppred_busy, slots_13.io.out_uop.ppred_busy connect issue_slots[13].out_uop.prs3_busy, slots_13.io.out_uop.prs3_busy connect issue_slots[13].out_uop.prs2_busy, slots_13.io.out_uop.prs2_busy connect issue_slots[13].out_uop.prs1_busy, slots_13.io.out_uop.prs1_busy connect issue_slots[13].out_uop.ppred, slots_13.io.out_uop.ppred connect issue_slots[13].out_uop.prs3, slots_13.io.out_uop.prs3 connect issue_slots[13].out_uop.prs2, slots_13.io.out_uop.prs2 connect issue_slots[13].out_uop.prs1, slots_13.io.out_uop.prs1 connect issue_slots[13].out_uop.pdst, slots_13.io.out_uop.pdst connect issue_slots[13].out_uop.rxq_idx, slots_13.io.out_uop.rxq_idx connect issue_slots[13].out_uop.stq_idx, slots_13.io.out_uop.stq_idx connect issue_slots[13].out_uop.ldq_idx, slots_13.io.out_uop.ldq_idx connect issue_slots[13].out_uop.rob_idx, slots_13.io.out_uop.rob_idx connect issue_slots[13].out_uop.csr_addr, slots_13.io.out_uop.csr_addr connect issue_slots[13].out_uop.imm_packed, slots_13.io.out_uop.imm_packed connect issue_slots[13].out_uop.taken, slots_13.io.out_uop.taken connect issue_slots[13].out_uop.pc_lob, slots_13.io.out_uop.pc_lob connect issue_slots[13].out_uop.edge_inst, slots_13.io.out_uop.edge_inst connect issue_slots[13].out_uop.ftq_idx, slots_13.io.out_uop.ftq_idx connect issue_slots[13].out_uop.br_tag, slots_13.io.out_uop.br_tag connect issue_slots[13].out_uop.br_mask, slots_13.io.out_uop.br_mask connect issue_slots[13].out_uop.is_sfb, slots_13.io.out_uop.is_sfb connect issue_slots[13].out_uop.is_jal, slots_13.io.out_uop.is_jal connect issue_slots[13].out_uop.is_jalr, slots_13.io.out_uop.is_jalr connect issue_slots[13].out_uop.is_br, slots_13.io.out_uop.is_br connect issue_slots[13].out_uop.iw_p2_poisoned, slots_13.io.out_uop.iw_p2_poisoned connect issue_slots[13].out_uop.iw_p1_poisoned, slots_13.io.out_uop.iw_p1_poisoned connect issue_slots[13].out_uop.iw_state, slots_13.io.out_uop.iw_state connect issue_slots[13].out_uop.ctrl.is_std, slots_13.io.out_uop.ctrl.is_std connect issue_slots[13].out_uop.ctrl.is_sta, slots_13.io.out_uop.ctrl.is_sta connect issue_slots[13].out_uop.ctrl.is_load, slots_13.io.out_uop.ctrl.is_load connect issue_slots[13].out_uop.ctrl.csr_cmd, slots_13.io.out_uop.ctrl.csr_cmd connect issue_slots[13].out_uop.ctrl.fcn_dw, slots_13.io.out_uop.ctrl.fcn_dw connect issue_slots[13].out_uop.ctrl.op_fcn, slots_13.io.out_uop.ctrl.op_fcn connect issue_slots[13].out_uop.ctrl.imm_sel, slots_13.io.out_uop.ctrl.imm_sel connect issue_slots[13].out_uop.ctrl.op2_sel, slots_13.io.out_uop.ctrl.op2_sel connect issue_slots[13].out_uop.ctrl.op1_sel, slots_13.io.out_uop.ctrl.op1_sel connect issue_slots[13].out_uop.ctrl.br_type, slots_13.io.out_uop.ctrl.br_type connect issue_slots[13].out_uop.fu_code, slots_13.io.out_uop.fu_code connect issue_slots[13].out_uop.iq_type, slots_13.io.out_uop.iq_type connect issue_slots[13].out_uop.debug_pc, slots_13.io.out_uop.debug_pc connect issue_slots[13].out_uop.is_rvc, slots_13.io.out_uop.is_rvc connect issue_slots[13].out_uop.debug_inst, slots_13.io.out_uop.debug_inst connect issue_slots[13].out_uop.inst, slots_13.io.out_uop.inst connect issue_slots[13].out_uop.uopc, slots_13.io.out_uop.uopc connect slots_13.io.in_uop.bits.debug_tsrc, issue_slots[13].in_uop.bits.debug_tsrc connect slots_13.io.in_uop.bits.debug_fsrc, issue_slots[13].in_uop.bits.debug_fsrc connect slots_13.io.in_uop.bits.bp_xcpt_if, issue_slots[13].in_uop.bits.bp_xcpt_if connect slots_13.io.in_uop.bits.bp_debug_if, issue_slots[13].in_uop.bits.bp_debug_if connect slots_13.io.in_uop.bits.xcpt_ma_if, issue_slots[13].in_uop.bits.xcpt_ma_if connect slots_13.io.in_uop.bits.xcpt_ae_if, issue_slots[13].in_uop.bits.xcpt_ae_if connect slots_13.io.in_uop.bits.xcpt_pf_if, issue_slots[13].in_uop.bits.xcpt_pf_if connect slots_13.io.in_uop.bits.fp_single, issue_slots[13].in_uop.bits.fp_single connect slots_13.io.in_uop.bits.fp_val, issue_slots[13].in_uop.bits.fp_val connect slots_13.io.in_uop.bits.frs3_en, issue_slots[13].in_uop.bits.frs3_en connect slots_13.io.in_uop.bits.lrs2_rtype, issue_slots[13].in_uop.bits.lrs2_rtype connect slots_13.io.in_uop.bits.lrs1_rtype, issue_slots[13].in_uop.bits.lrs1_rtype connect slots_13.io.in_uop.bits.dst_rtype, issue_slots[13].in_uop.bits.dst_rtype connect slots_13.io.in_uop.bits.ldst_val, issue_slots[13].in_uop.bits.ldst_val connect slots_13.io.in_uop.bits.lrs3, issue_slots[13].in_uop.bits.lrs3 connect slots_13.io.in_uop.bits.lrs2, issue_slots[13].in_uop.bits.lrs2 connect slots_13.io.in_uop.bits.lrs1, issue_slots[13].in_uop.bits.lrs1 connect slots_13.io.in_uop.bits.ldst, issue_slots[13].in_uop.bits.ldst connect slots_13.io.in_uop.bits.ldst_is_rs1, issue_slots[13].in_uop.bits.ldst_is_rs1 connect slots_13.io.in_uop.bits.flush_on_commit, issue_slots[13].in_uop.bits.flush_on_commit connect slots_13.io.in_uop.bits.is_unique, issue_slots[13].in_uop.bits.is_unique connect slots_13.io.in_uop.bits.is_sys_pc2epc, issue_slots[13].in_uop.bits.is_sys_pc2epc connect slots_13.io.in_uop.bits.uses_stq, issue_slots[13].in_uop.bits.uses_stq connect slots_13.io.in_uop.bits.uses_ldq, issue_slots[13].in_uop.bits.uses_ldq connect slots_13.io.in_uop.bits.is_amo, issue_slots[13].in_uop.bits.is_amo connect slots_13.io.in_uop.bits.is_fencei, issue_slots[13].in_uop.bits.is_fencei connect slots_13.io.in_uop.bits.is_fence, issue_slots[13].in_uop.bits.is_fence connect slots_13.io.in_uop.bits.mem_signed, issue_slots[13].in_uop.bits.mem_signed connect slots_13.io.in_uop.bits.mem_size, issue_slots[13].in_uop.bits.mem_size connect slots_13.io.in_uop.bits.mem_cmd, issue_slots[13].in_uop.bits.mem_cmd connect slots_13.io.in_uop.bits.bypassable, issue_slots[13].in_uop.bits.bypassable connect slots_13.io.in_uop.bits.exc_cause, issue_slots[13].in_uop.bits.exc_cause connect slots_13.io.in_uop.bits.exception, issue_slots[13].in_uop.bits.exception connect slots_13.io.in_uop.bits.stale_pdst, issue_slots[13].in_uop.bits.stale_pdst connect slots_13.io.in_uop.bits.ppred_busy, issue_slots[13].in_uop.bits.ppred_busy connect slots_13.io.in_uop.bits.prs3_busy, issue_slots[13].in_uop.bits.prs3_busy connect slots_13.io.in_uop.bits.prs2_busy, issue_slots[13].in_uop.bits.prs2_busy connect slots_13.io.in_uop.bits.prs1_busy, issue_slots[13].in_uop.bits.prs1_busy connect slots_13.io.in_uop.bits.ppred, issue_slots[13].in_uop.bits.ppred connect slots_13.io.in_uop.bits.prs3, issue_slots[13].in_uop.bits.prs3 connect slots_13.io.in_uop.bits.prs2, issue_slots[13].in_uop.bits.prs2 connect slots_13.io.in_uop.bits.prs1, issue_slots[13].in_uop.bits.prs1 connect slots_13.io.in_uop.bits.pdst, issue_slots[13].in_uop.bits.pdst connect slots_13.io.in_uop.bits.rxq_idx, issue_slots[13].in_uop.bits.rxq_idx connect slots_13.io.in_uop.bits.stq_idx, issue_slots[13].in_uop.bits.stq_idx connect slots_13.io.in_uop.bits.ldq_idx, issue_slots[13].in_uop.bits.ldq_idx connect slots_13.io.in_uop.bits.rob_idx, issue_slots[13].in_uop.bits.rob_idx connect slots_13.io.in_uop.bits.csr_addr, issue_slots[13].in_uop.bits.csr_addr connect slots_13.io.in_uop.bits.imm_packed, issue_slots[13].in_uop.bits.imm_packed connect slots_13.io.in_uop.bits.taken, issue_slots[13].in_uop.bits.taken connect slots_13.io.in_uop.bits.pc_lob, issue_slots[13].in_uop.bits.pc_lob connect slots_13.io.in_uop.bits.edge_inst, issue_slots[13].in_uop.bits.edge_inst connect slots_13.io.in_uop.bits.ftq_idx, issue_slots[13].in_uop.bits.ftq_idx connect slots_13.io.in_uop.bits.br_tag, issue_slots[13].in_uop.bits.br_tag connect slots_13.io.in_uop.bits.br_mask, issue_slots[13].in_uop.bits.br_mask connect slots_13.io.in_uop.bits.is_sfb, issue_slots[13].in_uop.bits.is_sfb connect slots_13.io.in_uop.bits.is_jal, issue_slots[13].in_uop.bits.is_jal connect slots_13.io.in_uop.bits.is_jalr, issue_slots[13].in_uop.bits.is_jalr connect slots_13.io.in_uop.bits.is_br, issue_slots[13].in_uop.bits.is_br connect slots_13.io.in_uop.bits.iw_p2_poisoned, issue_slots[13].in_uop.bits.iw_p2_poisoned connect slots_13.io.in_uop.bits.iw_p1_poisoned, issue_slots[13].in_uop.bits.iw_p1_poisoned connect slots_13.io.in_uop.bits.iw_state, issue_slots[13].in_uop.bits.iw_state connect slots_13.io.in_uop.bits.ctrl.is_std, issue_slots[13].in_uop.bits.ctrl.is_std connect slots_13.io.in_uop.bits.ctrl.is_sta, issue_slots[13].in_uop.bits.ctrl.is_sta connect slots_13.io.in_uop.bits.ctrl.is_load, issue_slots[13].in_uop.bits.ctrl.is_load connect slots_13.io.in_uop.bits.ctrl.csr_cmd, issue_slots[13].in_uop.bits.ctrl.csr_cmd connect slots_13.io.in_uop.bits.ctrl.fcn_dw, issue_slots[13].in_uop.bits.ctrl.fcn_dw connect slots_13.io.in_uop.bits.ctrl.op_fcn, issue_slots[13].in_uop.bits.ctrl.op_fcn connect slots_13.io.in_uop.bits.ctrl.imm_sel, issue_slots[13].in_uop.bits.ctrl.imm_sel connect slots_13.io.in_uop.bits.ctrl.op2_sel, issue_slots[13].in_uop.bits.ctrl.op2_sel connect slots_13.io.in_uop.bits.ctrl.op1_sel, issue_slots[13].in_uop.bits.ctrl.op1_sel connect slots_13.io.in_uop.bits.ctrl.br_type, issue_slots[13].in_uop.bits.ctrl.br_type connect slots_13.io.in_uop.bits.fu_code, issue_slots[13].in_uop.bits.fu_code connect slots_13.io.in_uop.bits.iq_type, issue_slots[13].in_uop.bits.iq_type connect slots_13.io.in_uop.bits.debug_pc, issue_slots[13].in_uop.bits.debug_pc connect slots_13.io.in_uop.bits.is_rvc, issue_slots[13].in_uop.bits.is_rvc connect slots_13.io.in_uop.bits.debug_inst, issue_slots[13].in_uop.bits.debug_inst connect slots_13.io.in_uop.bits.inst, issue_slots[13].in_uop.bits.inst connect slots_13.io.in_uop.bits.uopc, issue_slots[13].in_uop.bits.uopc connect slots_13.io.in_uop.valid, issue_slots[13].in_uop.valid connect slots_13.io.spec_ld_wakeup[0].bits, issue_slots[13].spec_ld_wakeup[0].bits connect slots_13.io.spec_ld_wakeup[0].valid, issue_slots[13].spec_ld_wakeup[0].valid connect slots_13.io.pred_wakeup_port.bits, issue_slots[13].pred_wakeup_port.bits connect slots_13.io.pred_wakeup_port.valid, issue_slots[13].pred_wakeup_port.valid connect slots_13.io.wakeup_ports[0].bits.poisoned, issue_slots[13].wakeup_ports[0].bits.poisoned connect slots_13.io.wakeup_ports[0].bits.pdst, issue_slots[13].wakeup_ports[0].bits.pdst connect slots_13.io.wakeup_ports[0].valid, issue_slots[13].wakeup_ports[0].valid connect slots_13.io.wakeup_ports[1].bits.poisoned, issue_slots[13].wakeup_ports[1].bits.poisoned connect slots_13.io.wakeup_ports[1].bits.pdst, issue_slots[13].wakeup_ports[1].bits.pdst connect slots_13.io.wakeup_ports[1].valid, issue_slots[13].wakeup_ports[1].valid connect slots_13.io.wakeup_ports[2].bits.poisoned, issue_slots[13].wakeup_ports[2].bits.poisoned connect slots_13.io.wakeup_ports[2].bits.pdst, issue_slots[13].wakeup_ports[2].bits.pdst connect slots_13.io.wakeup_ports[2].valid, issue_slots[13].wakeup_ports[2].valid connect slots_13.io.wakeup_ports[3].bits.poisoned, issue_slots[13].wakeup_ports[3].bits.poisoned connect slots_13.io.wakeup_ports[3].bits.pdst, issue_slots[13].wakeup_ports[3].bits.pdst connect slots_13.io.wakeup_ports[3].valid, issue_slots[13].wakeup_ports[3].valid connect slots_13.io.wakeup_ports[4].bits.poisoned, issue_slots[13].wakeup_ports[4].bits.poisoned connect slots_13.io.wakeup_ports[4].bits.pdst, issue_slots[13].wakeup_ports[4].bits.pdst connect slots_13.io.wakeup_ports[4].valid, issue_slots[13].wakeup_ports[4].valid connect slots_13.io.wakeup_ports[5].bits.poisoned, issue_slots[13].wakeup_ports[5].bits.poisoned connect slots_13.io.wakeup_ports[5].bits.pdst, issue_slots[13].wakeup_ports[5].bits.pdst connect slots_13.io.wakeup_ports[5].valid, issue_slots[13].wakeup_ports[5].valid connect slots_13.io.wakeup_ports[6].bits.poisoned, issue_slots[13].wakeup_ports[6].bits.poisoned connect slots_13.io.wakeup_ports[6].bits.pdst, issue_slots[13].wakeup_ports[6].bits.pdst connect slots_13.io.wakeup_ports[6].valid, issue_slots[13].wakeup_ports[6].valid connect slots_13.io.ldspec_miss, issue_slots[13].ldspec_miss connect slots_13.io.clear, issue_slots[13].clear connect slots_13.io.kill, issue_slots[13].kill connect slots_13.io.brupdate.b2.target_offset, issue_slots[13].brupdate.b2.target_offset connect slots_13.io.brupdate.b2.jalr_target, issue_slots[13].brupdate.b2.jalr_target connect slots_13.io.brupdate.b2.pc_sel, issue_slots[13].brupdate.b2.pc_sel connect slots_13.io.brupdate.b2.cfi_type, issue_slots[13].brupdate.b2.cfi_type connect slots_13.io.brupdate.b2.taken, issue_slots[13].brupdate.b2.taken connect slots_13.io.brupdate.b2.mispredict, issue_slots[13].brupdate.b2.mispredict connect slots_13.io.brupdate.b2.valid, issue_slots[13].brupdate.b2.valid connect slots_13.io.brupdate.b2.uop.debug_tsrc, issue_slots[13].brupdate.b2.uop.debug_tsrc connect slots_13.io.brupdate.b2.uop.debug_fsrc, issue_slots[13].brupdate.b2.uop.debug_fsrc connect slots_13.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[13].brupdate.b2.uop.bp_xcpt_if connect slots_13.io.brupdate.b2.uop.bp_debug_if, issue_slots[13].brupdate.b2.uop.bp_debug_if connect slots_13.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[13].brupdate.b2.uop.xcpt_ma_if connect slots_13.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[13].brupdate.b2.uop.xcpt_ae_if connect slots_13.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[13].brupdate.b2.uop.xcpt_pf_if connect slots_13.io.brupdate.b2.uop.fp_single, issue_slots[13].brupdate.b2.uop.fp_single connect slots_13.io.brupdate.b2.uop.fp_val, issue_slots[13].brupdate.b2.uop.fp_val connect slots_13.io.brupdate.b2.uop.frs3_en, issue_slots[13].brupdate.b2.uop.frs3_en connect slots_13.io.brupdate.b2.uop.lrs2_rtype, issue_slots[13].brupdate.b2.uop.lrs2_rtype connect slots_13.io.brupdate.b2.uop.lrs1_rtype, issue_slots[13].brupdate.b2.uop.lrs1_rtype connect slots_13.io.brupdate.b2.uop.dst_rtype, issue_slots[13].brupdate.b2.uop.dst_rtype connect slots_13.io.brupdate.b2.uop.ldst_val, issue_slots[13].brupdate.b2.uop.ldst_val connect slots_13.io.brupdate.b2.uop.lrs3, issue_slots[13].brupdate.b2.uop.lrs3 connect slots_13.io.brupdate.b2.uop.lrs2, issue_slots[13].brupdate.b2.uop.lrs2 connect slots_13.io.brupdate.b2.uop.lrs1, issue_slots[13].brupdate.b2.uop.lrs1 connect slots_13.io.brupdate.b2.uop.ldst, issue_slots[13].brupdate.b2.uop.ldst connect slots_13.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[13].brupdate.b2.uop.ldst_is_rs1 connect slots_13.io.brupdate.b2.uop.flush_on_commit, issue_slots[13].brupdate.b2.uop.flush_on_commit connect slots_13.io.brupdate.b2.uop.is_unique, issue_slots[13].brupdate.b2.uop.is_unique connect slots_13.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[13].brupdate.b2.uop.is_sys_pc2epc connect slots_13.io.brupdate.b2.uop.uses_stq, issue_slots[13].brupdate.b2.uop.uses_stq connect slots_13.io.brupdate.b2.uop.uses_ldq, issue_slots[13].brupdate.b2.uop.uses_ldq connect slots_13.io.brupdate.b2.uop.is_amo, issue_slots[13].brupdate.b2.uop.is_amo connect slots_13.io.brupdate.b2.uop.is_fencei, issue_slots[13].brupdate.b2.uop.is_fencei connect slots_13.io.brupdate.b2.uop.is_fence, issue_slots[13].brupdate.b2.uop.is_fence connect slots_13.io.brupdate.b2.uop.mem_signed, issue_slots[13].brupdate.b2.uop.mem_signed connect slots_13.io.brupdate.b2.uop.mem_size, issue_slots[13].brupdate.b2.uop.mem_size connect slots_13.io.brupdate.b2.uop.mem_cmd, issue_slots[13].brupdate.b2.uop.mem_cmd connect slots_13.io.brupdate.b2.uop.bypassable, issue_slots[13].brupdate.b2.uop.bypassable connect slots_13.io.brupdate.b2.uop.exc_cause, issue_slots[13].brupdate.b2.uop.exc_cause connect slots_13.io.brupdate.b2.uop.exception, issue_slots[13].brupdate.b2.uop.exception connect slots_13.io.brupdate.b2.uop.stale_pdst, issue_slots[13].brupdate.b2.uop.stale_pdst connect slots_13.io.brupdate.b2.uop.ppred_busy, issue_slots[13].brupdate.b2.uop.ppred_busy connect slots_13.io.brupdate.b2.uop.prs3_busy, issue_slots[13].brupdate.b2.uop.prs3_busy connect slots_13.io.brupdate.b2.uop.prs2_busy, issue_slots[13].brupdate.b2.uop.prs2_busy connect slots_13.io.brupdate.b2.uop.prs1_busy, issue_slots[13].brupdate.b2.uop.prs1_busy connect slots_13.io.brupdate.b2.uop.ppred, issue_slots[13].brupdate.b2.uop.ppred connect slots_13.io.brupdate.b2.uop.prs3, issue_slots[13].brupdate.b2.uop.prs3 connect slots_13.io.brupdate.b2.uop.prs2, issue_slots[13].brupdate.b2.uop.prs2 connect slots_13.io.brupdate.b2.uop.prs1, issue_slots[13].brupdate.b2.uop.prs1 connect slots_13.io.brupdate.b2.uop.pdst, issue_slots[13].brupdate.b2.uop.pdst connect slots_13.io.brupdate.b2.uop.rxq_idx, issue_slots[13].brupdate.b2.uop.rxq_idx connect slots_13.io.brupdate.b2.uop.stq_idx, issue_slots[13].brupdate.b2.uop.stq_idx connect slots_13.io.brupdate.b2.uop.ldq_idx, issue_slots[13].brupdate.b2.uop.ldq_idx connect slots_13.io.brupdate.b2.uop.rob_idx, issue_slots[13].brupdate.b2.uop.rob_idx connect slots_13.io.brupdate.b2.uop.csr_addr, issue_slots[13].brupdate.b2.uop.csr_addr connect slots_13.io.brupdate.b2.uop.imm_packed, issue_slots[13].brupdate.b2.uop.imm_packed connect slots_13.io.brupdate.b2.uop.taken, issue_slots[13].brupdate.b2.uop.taken connect slots_13.io.brupdate.b2.uop.pc_lob, issue_slots[13].brupdate.b2.uop.pc_lob connect slots_13.io.brupdate.b2.uop.edge_inst, issue_slots[13].brupdate.b2.uop.edge_inst connect slots_13.io.brupdate.b2.uop.ftq_idx, issue_slots[13].brupdate.b2.uop.ftq_idx connect slots_13.io.brupdate.b2.uop.br_tag, issue_slots[13].brupdate.b2.uop.br_tag connect slots_13.io.brupdate.b2.uop.br_mask, issue_slots[13].brupdate.b2.uop.br_mask connect slots_13.io.brupdate.b2.uop.is_sfb, issue_slots[13].brupdate.b2.uop.is_sfb connect slots_13.io.brupdate.b2.uop.is_jal, issue_slots[13].brupdate.b2.uop.is_jal connect slots_13.io.brupdate.b2.uop.is_jalr, issue_slots[13].brupdate.b2.uop.is_jalr connect slots_13.io.brupdate.b2.uop.is_br, issue_slots[13].brupdate.b2.uop.is_br connect slots_13.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[13].brupdate.b2.uop.iw_p2_poisoned connect slots_13.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[13].brupdate.b2.uop.iw_p1_poisoned connect slots_13.io.brupdate.b2.uop.iw_state, issue_slots[13].brupdate.b2.uop.iw_state connect slots_13.io.brupdate.b2.uop.ctrl.is_std, issue_slots[13].brupdate.b2.uop.ctrl.is_std connect slots_13.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[13].brupdate.b2.uop.ctrl.is_sta connect slots_13.io.brupdate.b2.uop.ctrl.is_load, issue_slots[13].brupdate.b2.uop.ctrl.is_load connect slots_13.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[13].brupdate.b2.uop.ctrl.csr_cmd connect slots_13.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[13].brupdate.b2.uop.ctrl.fcn_dw connect slots_13.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[13].brupdate.b2.uop.ctrl.op_fcn connect slots_13.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[13].brupdate.b2.uop.ctrl.imm_sel connect slots_13.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[13].brupdate.b2.uop.ctrl.op2_sel connect slots_13.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[13].brupdate.b2.uop.ctrl.op1_sel connect slots_13.io.brupdate.b2.uop.ctrl.br_type, issue_slots[13].brupdate.b2.uop.ctrl.br_type connect slots_13.io.brupdate.b2.uop.fu_code, issue_slots[13].brupdate.b2.uop.fu_code connect slots_13.io.brupdate.b2.uop.iq_type, issue_slots[13].brupdate.b2.uop.iq_type connect slots_13.io.brupdate.b2.uop.debug_pc, issue_slots[13].brupdate.b2.uop.debug_pc connect slots_13.io.brupdate.b2.uop.is_rvc, issue_slots[13].brupdate.b2.uop.is_rvc connect slots_13.io.brupdate.b2.uop.debug_inst, issue_slots[13].brupdate.b2.uop.debug_inst connect slots_13.io.brupdate.b2.uop.inst, issue_slots[13].brupdate.b2.uop.inst connect slots_13.io.brupdate.b2.uop.uopc, issue_slots[13].brupdate.b2.uop.uopc connect slots_13.io.brupdate.b1.mispredict_mask, issue_slots[13].brupdate.b1.mispredict_mask connect slots_13.io.brupdate.b1.resolve_mask, issue_slots[13].brupdate.b1.resolve_mask connect slots_13.io.grant, issue_slots[13].grant connect issue_slots[13].request_hp, slots_13.io.request_hp connect issue_slots[13].request, slots_13.io.request connect issue_slots[13].will_be_valid, slots_13.io.will_be_valid connect issue_slots[13].valid, slots_13.io.valid connect issue_slots[14].debug.state, slots_14.io.debug.state connect issue_slots[14].debug.ppred, slots_14.io.debug.ppred connect issue_slots[14].debug.p3, slots_14.io.debug.p3 connect issue_slots[14].debug.p2, slots_14.io.debug.p2 connect issue_slots[14].debug.p1, slots_14.io.debug.p1 connect issue_slots[14].uop.debug_tsrc, slots_14.io.uop.debug_tsrc connect issue_slots[14].uop.debug_fsrc, slots_14.io.uop.debug_fsrc connect issue_slots[14].uop.bp_xcpt_if, slots_14.io.uop.bp_xcpt_if connect issue_slots[14].uop.bp_debug_if, slots_14.io.uop.bp_debug_if connect issue_slots[14].uop.xcpt_ma_if, slots_14.io.uop.xcpt_ma_if connect issue_slots[14].uop.xcpt_ae_if, slots_14.io.uop.xcpt_ae_if connect issue_slots[14].uop.xcpt_pf_if, slots_14.io.uop.xcpt_pf_if connect issue_slots[14].uop.fp_single, slots_14.io.uop.fp_single connect issue_slots[14].uop.fp_val, slots_14.io.uop.fp_val connect issue_slots[14].uop.frs3_en, slots_14.io.uop.frs3_en connect issue_slots[14].uop.lrs2_rtype, slots_14.io.uop.lrs2_rtype connect issue_slots[14].uop.lrs1_rtype, slots_14.io.uop.lrs1_rtype connect issue_slots[14].uop.dst_rtype, slots_14.io.uop.dst_rtype connect issue_slots[14].uop.ldst_val, slots_14.io.uop.ldst_val connect issue_slots[14].uop.lrs3, slots_14.io.uop.lrs3 connect issue_slots[14].uop.lrs2, slots_14.io.uop.lrs2 connect issue_slots[14].uop.lrs1, slots_14.io.uop.lrs1 connect issue_slots[14].uop.ldst, slots_14.io.uop.ldst connect issue_slots[14].uop.ldst_is_rs1, slots_14.io.uop.ldst_is_rs1 connect issue_slots[14].uop.flush_on_commit, slots_14.io.uop.flush_on_commit connect issue_slots[14].uop.is_unique, slots_14.io.uop.is_unique connect issue_slots[14].uop.is_sys_pc2epc, slots_14.io.uop.is_sys_pc2epc connect issue_slots[14].uop.uses_stq, slots_14.io.uop.uses_stq connect issue_slots[14].uop.uses_ldq, slots_14.io.uop.uses_ldq connect issue_slots[14].uop.is_amo, slots_14.io.uop.is_amo connect issue_slots[14].uop.is_fencei, slots_14.io.uop.is_fencei connect issue_slots[14].uop.is_fence, slots_14.io.uop.is_fence connect issue_slots[14].uop.mem_signed, slots_14.io.uop.mem_signed connect issue_slots[14].uop.mem_size, slots_14.io.uop.mem_size connect issue_slots[14].uop.mem_cmd, slots_14.io.uop.mem_cmd connect issue_slots[14].uop.bypassable, slots_14.io.uop.bypassable connect issue_slots[14].uop.exc_cause, slots_14.io.uop.exc_cause connect issue_slots[14].uop.exception, slots_14.io.uop.exception connect issue_slots[14].uop.stale_pdst, slots_14.io.uop.stale_pdst connect issue_slots[14].uop.ppred_busy, slots_14.io.uop.ppred_busy connect issue_slots[14].uop.prs3_busy, slots_14.io.uop.prs3_busy connect issue_slots[14].uop.prs2_busy, slots_14.io.uop.prs2_busy connect issue_slots[14].uop.prs1_busy, slots_14.io.uop.prs1_busy connect issue_slots[14].uop.ppred, slots_14.io.uop.ppred connect issue_slots[14].uop.prs3, slots_14.io.uop.prs3 connect issue_slots[14].uop.prs2, slots_14.io.uop.prs2 connect issue_slots[14].uop.prs1, slots_14.io.uop.prs1 connect issue_slots[14].uop.pdst, slots_14.io.uop.pdst connect issue_slots[14].uop.rxq_idx, slots_14.io.uop.rxq_idx connect issue_slots[14].uop.stq_idx, slots_14.io.uop.stq_idx connect issue_slots[14].uop.ldq_idx, slots_14.io.uop.ldq_idx connect issue_slots[14].uop.rob_idx, slots_14.io.uop.rob_idx connect issue_slots[14].uop.csr_addr, slots_14.io.uop.csr_addr connect issue_slots[14].uop.imm_packed, slots_14.io.uop.imm_packed connect issue_slots[14].uop.taken, slots_14.io.uop.taken connect issue_slots[14].uop.pc_lob, slots_14.io.uop.pc_lob connect issue_slots[14].uop.edge_inst, slots_14.io.uop.edge_inst connect issue_slots[14].uop.ftq_idx, slots_14.io.uop.ftq_idx connect issue_slots[14].uop.br_tag, slots_14.io.uop.br_tag connect issue_slots[14].uop.br_mask, slots_14.io.uop.br_mask connect issue_slots[14].uop.is_sfb, slots_14.io.uop.is_sfb connect issue_slots[14].uop.is_jal, slots_14.io.uop.is_jal connect issue_slots[14].uop.is_jalr, slots_14.io.uop.is_jalr connect issue_slots[14].uop.is_br, slots_14.io.uop.is_br connect issue_slots[14].uop.iw_p2_poisoned, slots_14.io.uop.iw_p2_poisoned connect issue_slots[14].uop.iw_p1_poisoned, slots_14.io.uop.iw_p1_poisoned connect issue_slots[14].uop.iw_state, slots_14.io.uop.iw_state connect issue_slots[14].uop.ctrl.is_std, slots_14.io.uop.ctrl.is_std connect issue_slots[14].uop.ctrl.is_sta, slots_14.io.uop.ctrl.is_sta connect issue_slots[14].uop.ctrl.is_load, slots_14.io.uop.ctrl.is_load connect issue_slots[14].uop.ctrl.csr_cmd, slots_14.io.uop.ctrl.csr_cmd connect issue_slots[14].uop.ctrl.fcn_dw, slots_14.io.uop.ctrl.fcn_dw connect issue_slots[14].uop.ctrl.op_fcn, slots_14.io.uop.ctrl.op_fcn connect issue_slots[14].uop.ctrl.imm_sel, slots_14.io.uop.ctrl.imm_sel connect issue_slots[14].uop.ctrl.op2_sel, slots_14.io.uop.ctrl.op2_sel connect issue_slots[14].uop.ctrl.op1_sel, slots_14.io.uop.ctrl.op1_sel connect issue_slots[14].uop.ctrl.br_type, slots_14.io.uop.ctrl.br_type connect issue_slots[14].uop.fu_code, slots_14.io.uop.fu_code connect issue_slots[14].uop.iq_type, slots_14.io.uop.iq_type connect issue_slots[14].uop.debug_pc, slots_14.io.uop.debug_pc connect issue_slots[14].uop.is_rvc, slots_14.io.uop.is_rvc connect issue_slots[14].uop.debug_inst, slots_14.io.uop.debug_inst connect issue_slots[14].uop.inst, slots_14.io.uop.inst connect issue_slots[14].uop.uopc, slots_14.io.uop.uopc connect issue_slots[14].out_uop.debug_tsrc, slots_14.io.out_uop.debug_tsrc connect issue_slots[14].out_uop.debug_fsrc, slots_14.io.out_uop.debug_fsrc connect issue_slots[14].out_uop.bp_xcpt_if, slots_14.io.out_uop.bp_xcpt_if connect issue_slots[14].out_uop.bp_debug_if, slots_14.io.out_uop.bp_debug_if connect issue_slots[14].out_uop.xcpt_ma_if, slots_14.io.out_uop.xcpt_ma_if connect issue_slots[14].out_uop.xcpt_ae_if, slots_14.io.out_uop.xcpt_ae_if connect issue_slots[14].out_uop.xcpt_pf_if, slots_14.io.out_uop.xcpt_pf_if connect issue_slots[14].out_uop.fp_single, slots_14.io.out_uop.fp_single connect issue_slots[14].out_uop.fp_val, slots_14.io.out_uop.fp_val connect issue_slots[14].out_uop.frs3_en, slots_14.io.out_uop.frs3_en connect issue_slots[14].out_uop.lrs2_rtype, slots_14.io.out_uop.lrs2_rtype connect issue_slots[14].out_uop.lrs1_rtype, slots_14.io.out_uop.lrs1_rtype connect issue_slots[14].out_uop.dst_rtype, slots_14.io.out_uop.dst_rtype connect issue_slots[14].out_uop.ldst_val, slots_14.io.out_uop.ldst_val connect issue_slots[14].out_uop.lrs3, slots_14.io.out_uop.lrs3 connect issue_slots[14].out_uop.lrs2, slots_14.io.out_uop.lrs2 connect issue_slots[14].out_uop.lrs1, slots_14.io.out_uop.lrs1 connect issue_slots[14].out_uop.ldst, slots_14.io.out_uop.ldst connect issue_slots[14].out_uop.ldst_is_rs1, slots_14.io.out_uop.ldst_is_rs1 connect issue_slots[14].out_uop.flush_on_commit, slots_14.io.out_uop.flush_on_commit connect issue_slots[14].out_uop.is_unique, slots_14.io.out_uop.is_unique connect issue_slots[14].out_uop.is_sys_pc2epc, slots_14.io.out_uop.is_sys_pc2epc connect issue_slots[14].out_uop.uses_stq, slots_14.io.out_uop.uses_stq connect issue_slots[14].out_uop.uses_ldq, slots_14.io.out_uop.uses_ldq connect issue_slots[14].out_uop.is_amo, slots_14.io.out_uop.is_amo connect issue_slots[14].out_uop.is_fencei, slots_14.io.out_uop.is_fencei connect issue_slots[14].out_uop.is_fence, slots_14.io.out_uop.is_fence connect issue_slots[14].out_uop.mem_signed, slots_14.io.out_uop.mem_signed connect issue_slots[14].out_uop.mem_size, slots_14.io.out_uop.mem_size connect issue_slots[14].out_uop.mem_cmd, slots_14.io.out_uop.mem_cmd connect issue_slots[14].out_uop.bypassable, slots_14.io.out_uop.bypassable connect issue_slots[14].out_uop.exc_cause, slots_14.io.out_uop.exc_cause connect issue_slots[14].out_uop.exception, slots_14.io.out_uop.exception connect issue_slots[14].out_uop.stale_pdst, slots_14.io.out_uop.stale_pdst connect issue_slots[14].out_uop.ppred_busy, slots_14.io.out_uop.ppred_busy connect issue_slots[14].out_uop.prs3_busy, slots_14.io.out_uop.prs3_busy connect issue_slots[14].out_uop.prs2_busy, slots_14.io.out_uop.prs2_busy connect issue_slots[14].out_uop.prs1_busy, slots_14.io.out_uop.prs1_busy connect issue_slots[14].out_uop.ppred, slots_14.io.out_uop.ppred connect issue_slots[14].out_uop.prs3, slots_14.io.out_uop.prs3 connect issue_slots[14].out_uop.prs2, slots_14.io.out_uop.prs2 connect issue_slots[14].out_uop.prs1, slots_14.io.out_uop.prs1 connect issue_slots[14].out_uop.pdst, slots_14.io.out_uop.pdst connect issue_slots[14].out_uop.rxq_idx, slots_14.io.out_uop.rxq_idx connect issue_slots[14].out_uop.stq_idx, slots_14.io.out_uop.stq_idx connect issue_slots[14].out_uop.ldq_idx, slots_14.io.out_uop.ldq_idx connect issue_slots[14].out_uop.rob_idx, slots_14.io.out_uop.rob_idx connect issue_slots[14].out_uop.csr_addr, slots_14.io.out_uop.csr_addr connect issue_slots[14].out_uop.imm_packed, slots_14.io.out_uop.imm_packed connect issue_slots[14].out_uop.taken, slots_14.io.out_uop.taken connect issue_slots[14].out_uop.pc_lob, slots_14.io.out_uop.pc_lob connect issue_slots[14].out_uop.edge_inst, slots_14.io.out_uop.edge_inst connect issue_slots[14].out_uop.ftq_idx, slots_14.io.out_uop.ftq_idx connect issue_slots[14].out_uop.br_tag, slots_14.io.out_uop.br_tag connect issue_slots[14].out_uop.br_mask, slots_14.io.out_uop.br_mask connect issue_slots[14].out_uop.is_sfb, slots_14.io.out_uop.is_sfb connect issue_slots[14].out_uop.is_jal, slots_14.io.out_uop.is_jal connect issue_slots[14].out_uop.is_jalr, slots_14.io.out_uop.is_jalr connect issue_slots[14].out_uop.is_br, slots_14.io.out_uop.is_br connect issue_slots[14].out_uop.iw_p2_poisoned, slots_14.io.out_uop.iw_p2_poisoned connect issue_slots[14].out_uop.iw_p1_poisoned, slots_14.io.out_uop.iw_p1_poisoned connect issue_slots[14].out_uop.iw_state, slots_14.io.out_uop.iw_state connect issue_slots[14].out_uop.ctrl.is_std, slots_14.io.out_uop.ctrl.is_std connect issue_slots[14].out_uop.ctrl.is_sta, slots_14.io.out_uop.ctrl.is_sta connect issue_slots[14].out_uop.ctrl.is_load, slots_14.io.out_uop.ctrl.is_load connect issue_slots[14].out_uop.ctrl.csr_cmd, slots_14.io.out_uop.ctrl.csr_cmd connect issue_slots[14].out_uop.ctrl.fcn_dw, slots_14.io.out_uop.ctrl.fcn_dw connect issue_slots[14].out_uop.ctrl.op_fcn, slots_14.io.out_uop.ctrl.op_fcn connect issue_slots[14].out_uop.ctrl.imm_sel, slots_14.io.out_uop.ctrl.imm_sel connect issue_slots[14].out_uop.ctrl.op2_sel, slots_14.io.out_uop.ctrl.op2_sel connect issue_slots[14].out_uop.ctrl.op1_sel, slots_14.io.out_uop.ctrl.op1_sel connect issue_slots[14].out_uop.ctrl.br_type, slots_14.io.out_uop.ctrl.br_type connect issue_slots[14].out_uop.fu_code, slots_14.io.out_uop.fu_code connect issue_slots[14].out_uop.iq_type, slots_14.io.out_uop.iq_type connect issue_slots[14].out_uop.debug_pc, slots_14.io.out_uop.debug_pc connect issue_slots[14].out_uop.is_rvc, slots_14.io.out_uop.is_rvc connect issue_slots[14].out_uop.debug_inst, slots_14.io.out_uop.debug_inst connect issue_slots[14].out_uop.inst, slots_14.io.out_uop.inst connect issue_slots[14].out_uop.uopc, slots_14.io.out_uop.uopc connect slots_14.io.in_uop.bits.debug_tsrc, issue_slots[14].in_uop.bits.debug_tsrc connect slots_14.io.in_uop.bits.debug_fsrc, issue_slots[14].in_uop.bits.debug_fsrc connect slots_14.io.in_uop.bits.bp_xcpt_if, issue_slots[14].in_uop.bits.bp_xcpt_if connect slots_14.io.in_uop.bits.bp_debug_if, issue_slots[14].in_uop.bits.bp_debug_if connect slots_14.io.in_uop.bits.xcpt_ma_if, issue_slots[14].in_uop.bits.xcpt_ma_if connect slots_14.io.in_uop.bits.xcpt_ae_if, issue_slots[14].in_uop.bits.xcpt_ae_if connect slots_14.io.in_uop.bits.xcpt_pf_if, issue_slots[14].in_uop.bits.xcpt_pf_if connect slots_14.io.in_uop.bits.fp_single, issue_slots[14].in_uop.bits.fp_single connect slots_14.io.in_uop.bits.fp_val, issue_slots[14].in_uop.bits.fp_val connect slots_14.io.in_uop.bits.frs3_en, issue_slots[14].in_uop.bits.frs3_en connect slots_14.io.in_uop.bits.lrs2_rtype, issue_slots[14].in_uop.bits.lrs2_rtype connect slots_14.io.in_uop.bits.lrs1_rtype, issue_slots[14].in_uop.bits.lrs1_rtype connect slots_14.io.in_uop.bits.dst_rtype, issue_slots[14].in_uop.bits.dst_rtype connect slots_14.io.in_uop.bits.ldst_val, issue_slots[14].in_uop.bits.ldst_val connect slots_14.io.in_uop.bits.lrs3, issue_slots[14].in_uop.bits.lrs3 connect slots_14.io.in_uop.bits.lrs2, issue_slots[14].in_uop.bits.lrs2 connect slots_14.io.in_uop.bits.lrs1, issue_slots[14].in_uop.bits.lrs1 connect slots_14.io.in_uop.bits.ldst, issue_slots[14].in_uop.bits.ldst connect slots_14.io.in_uop.bits.ldst_is_rs1, issue_slots[14].in_uop.bits.ldst_is_rs1 connect slots_14.io.in_uop.bits.flush_on_commit, issue_slots[14].in_uop.bits.flush_on_commit connect slots_14.io.in_uop.bits.is_unique, issue_slots[14].in_uop.bits.is_unique connect slots_14.io.in_uop.bits.is_sys_pc2epc, issue_slots[14].in_uop.bits.is_sys_pc2epc connect slots_14.io.in_uop.bits.uses_stq, issue_slots[14].in_uop.bits.uses_stq connect slots_14.io.in_uop.bits.uses_ldq, issue_slots[14].in_uop.bits.uses_ldq connect slots_14.io.in_uop.bits.is_amo, issue_slots[14].in_uop.bits.is_amo connect slots_14.io.in_uop.bits.is_fencei, issue_slots[14].in_uop.bits.is_fencei connect slots_14.io.in_uop.bits.is_fence, issue_slots[14].in_uop.bits.is_fence connect slots_14.io.in_uop.bits.mem_signed, issue_slots[14].in_uop.bits.mem_signed connect slots_14.io.in_uop.bits.mem_size, issue_slots[14].in_uop.bits.mem_size connect slots_14.io.in_uop.bits.mem_cmd, issue_slots[14].in_uop.bits.mem_cmd connect slots_14.io.in_uop.bits.bypassable, issue_slots[14].in_uop.bits.bypassable connect slots_14.io.in_uop.bits.exc_cause, issue_slots[14].in_uop.bits.exc_cause connect slots_14.io.in_uop.bits.exception, issue_slots[14].in_uop.bits.exception connect slots_14.io.in_uop.bits.stale_pdst, issue_slots[14].in_uop.bits.stale_pdst connect slots_14.io.in_uop.bits.ppred_busy, issue_slots[14].in_uop.bits.ppred_busy connect slots_14.io.in_uop.bits.prs3_busy, issue_slots[14].in_uop.bits.prs3_busy connect slots_14.io.in_uop.bits.prs2_busy, issue_slots[14].in_uop.bits.prs2_busy connect slots_14.io.in_uop.bits.prs1_busy, issue_slots[14].in_uop.bits.prs1_busy connect slots_14.io.in_uop.bits.ppred, issue_slots[14].in_uop.bits.ppred connect slots_14.io.in_uop.bits.prs3, issue_slots[14].in_uop.bits.prs3 connect slots_14.io.in_uop.bits.prs2, issue_slots[14].in_uop.bits.prs2 connect slots_14.io.in_uop.bits.prs1, issue_slots[14].in_uop.bits.prs1 connect slots_14.io.in_uop.bits.pdst, issue_slots[14].in_uop.bits.pdst connect slots_14.io.in_uop.bits.rxq_idx, issue_slots[14].in_uop.bits.rxq_idx connect slots_14.io.in_uop.bits.stq_idx, issue_slots[14].in_uop.bits.stq_idx connect slots_14.io.in_uop.bits.ldq_idx, issue_slots[14].in_uop.bits.ldq_idx connect slots_14.io.in_uop.bits.rob_idx, issue_slots[14].in_uop.bits.rob_idx connect slots_14.io.in_uop.bits.csr_addr, issue_slots[14].in_uop.bits.csr_addr connect slots_14.io.in_uop.bits.imm_packed, issue_slots[14].in_uop.bits.imm_packed connect slots_14.io.in_uop.bits.taken, issue_slots[14].in_uop.bits.taken connect slots_14.io.in_uop.bits.pc_lob, issue_slots[14].in_uop.bits.pc_lob connect slots_14.io.in_uop.bits.edge_inst, issue_slots[14].in_uop.bits.edge_inst connect slots_14.io.in_uop.bits.ftq_idx, issue_slots[14].in_uop.bits.ftq_idx connect slots_14.io.in_uop.bits.br_tag, issue_slots[14].in_uop.bits.br_tag connect slots_14.io.in_uop.bits.br_mask, issue_slots[14].in_uop.bits.br_mask connect slots_14.io.in_uop.bits.is_sfb, issue_slots[14].in_uop.bits.is_sfb connect slots_14.io.in_uop.bits.is_jal, issue_slots[14].in_uop.bits.is_jal connect slots_14.io.in_uop.bits.is_jalr, issue_slots[14].in_uop.bits.is_jalr connect slots_14.io.in_uop.bits.is_br, issue_slots[14].in_uop.bits.is_br connect slots_14.io.in_uop.bits.iw_p2_poisoned, issue_slots[14].in_uop.bits.iw_p2_poisoned connect slots_14.io.in_uop.bits.iw_p1_poisoned, issue_slots[14].in_uop.bits.iw_p1_poisoned connect slots_14.io.in_uop.bits.iw_state, issue_slots[14].in_uop.bits.iw_state connect slots_14.io.in_uop.bits.ctrl.is_std, issue_slots[14].in_uop.bits.ctrl.is_std connect slots_14.io.in_uop.bits.ctrl.is_sta, issue_slots[14].in_uop.bits.ctrl.is_sta connect slots_14.io.in_uop.bits.ctrl.is_load, issue_slots[14].in_uop.bits.ctrl.is_load connect slots_14.io.in_uop.bits.ctrl.csr_cmd, issue_slots[14].in_uop.bits.ctrl.csr_cmd connect slots_14.io.in_uop.bits.ctrl.fcn_dw, issue_slots[14].in_uop.bits.ctrl.fcn_dw connect slots_14.io.in_uop.bits.ctrl.op_fcn, issue_slots[14].in_uop.bits.ctrl.op_fcn connect slots_14.io.in_uop.bits.ctrl.imm_sel, issue_slots[14].in_uop.bits.ctrl.imm_sel connect slots_14.io.in_uop.bits.ctrl.op2_sel, issue_slots[14].in_uop.bits.ctrl.op2_sel connect slots_14.io.in_uop.bits.ctrl.op1_sel, issue_slots[14].in_uop.bits.ctrl.op1_sel connect slots_14.io.in_uop.bits.ctrl.br_type, issue_slots[14].in_uop.bits.ctrl.br_type connect slots_14.io.in_uop.bits.fu_code, issue_slots[14].in_uop.bits.fu_code connect slots_14.io.in_uop.bits.iq_type, issue_slots[14].in_uop.bits.iq_type connect slots_14.io.in_uop.bits.debug_pc, issue_slots[14].in_uop.bits.debug_pc connect slots_14.io.in_uop.bits.is_rvc, issue_slots[14].in_uop.bits.is_rvc connect slots_14.io.in_uop.bits.debug_inst, issue_slots[14].in_uop.bits.debug_inst connect slots_14.io.in_uop.bits.inst, issue_slots[14].in_uop.bits.inst connect slots_14.io.in_uop.bits.uopc, issue_slots[14].in_uop.bits.uopc connect slots_14.io.in_uop.valid, issue_slots[14].in_uop.valid connect slots_14.io.spec_ld_wakeup[0].bits, issue_slots[14].spec_ld_wakeup[0].bits connect slots_14.io.spec_ld_wakeup[0].valid, issue_slots[14].spec_ld_wakeup[0].valid connect slots_14.io.pred_wakeup_port.bits, issue_slots[14].pred_wakeup_port.bits connect slots_14.io.pred_wakeup_port.valid, issue_slots[14].pred_wakeup_port.valid connect slots_14.io.wakeup_ports[0].bits.poisoned, issue_slots[14].wakeup_ports[0].bits.poisoned connect slots_14.io.wakeup_ports[0].bits.pdst, issue_slots[14].wakeup_ports[0].bits.pdst connect slots_14.io.wakeup_ports[0].valid, issue_slots[14].wakeup_ports[0].valid connect slots_14.io.wakeup_ports[1].bits.poisoned, issue_slots[14].wakeup_ports[1].bits.poisoned connect slots_14.io.wakeup_ports[1].bits.pdst, issue_slots[14].wakeup_ports[1].bits.pdst connect slots_14.io.wakeup_ports[1].valid, issue_slots[14].wakeup_ports[1].valid connect slots_14.io.wakeup_ports[2].bits.poisoned, issue_slots[14].wakeup_ports[2].bits.poisoned connect slots_14.io.wakeup_ports[2].bits.pdst, issue_slots[14].wakeup_ports[2].bits.pdst connect slots_14.io.wakeup_ports[2].valid, issue_slots[14].wakeup_ports[2].valid connect slots_14.io.wakeup_ports[3].bits.poisoned, issue_slots[14].wakeup_ports[3].bits.poisoned connect slots_14.io.wakeup_ports[3].bits.pdst, issue_slots[14].wakeup_ports[3].bits.pdst connect slots_14.io.wakeup_ports[3].valid, issue_slots[14].wakeup_ports[3].valid connect slots_14.io.wakeup_ports[4].bits.poisoned, issue_slots[14].wakeup_ports[4].bits.poisoned connect slots_14.io.wakeup_ports[4].bits.pdst, issue_slots[14].wakeup_ports[4].bits.pdst connect slots_14.io.wakeup_ports[4].valid, issue_slots[14].wakeup_ports[4].valid connect slots_14.io.wakeup_ports[5].bits.poisoned, issue_slots[14].wakeup_ports[5].bits.poisoned connect slots_14.io.wakeup_ports[5].bits.pdst, issue_slots[14].wakeup_ports[5].bits.pdst connect slots_14.io.wakeup_ports[5].valid, issue_slots[14].wakeup_ports[5].valid connect slots_14.io.wakeup_ports[6].bits.poisoned, issue_slots[14].wakeup_ports[6].bits.poisoned connect slots_14.io.wakeup_ports[6].bits.pdst, issue_slots[14].wakeup_ports[6].bits.pdst connect slots_14.io.wakeup_ports[6].valid, issue_slots[14].wakeup_ports[6].valid connect slots_14.io.ldspec_miss, issue_slots[14].ldspec_miss connect slots_14.io.clear, issue_slots[14].clear connect slots_14.io.kill, issue_slots[14].kill connect slots_14.io.brupdate.b2.target_offset, issue_slots[14].brupdate.b2.target_offset connect slots_14.io.brupdate.b2.jalr_target, issue_slots[14].brupdate.b2.jalr_target connect slots_14.io.brupdate.b2.pc_sel, issue_slots[14].brupdate.b2.pc_sel connect slots_14.io.brupdate.b2.cfi_type, issue_slots[14].brupdate.b2.cfi_type connect slots_14.io.brupdate.b2.taken, issue_slots[14].brupdate.b2.taken connect slots_14.io.brupdate.b2.mispredict, issue_slots[14].brupdate.b2.mispredict connect slots_14.io.brupdate.b2.valid, issue_slots[14].brupdate.b2.valid connect slots_14.io.brupdate.b2.uop.debug_tsrc, issue_slots[14].brupdate.b2.uop.debug_tsrc connect slots_14.io.brupdate.b2.uop.debug_fsrc, issue_slots[14].brupdate.b2.uop.debug_fsrc connect slots_14.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[14].brupdate.b2.uop.bp_xcpt_if connect slots_14.io.brupdate.b2.uop.bp_debug_if, issue_slots[14].brupdate.b2.uop.bp_debug_if connect slots_14.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[14].brupdate.b2.uop.xcpt_ma_if connect slots_14.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[14].brupdate.b2.uop.xcpt_ae_if connect slots_14.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[14].brupdate.b2.uop.xcpt_pf_if connect slots_14.io.brupdate.b2.uop.fp_single, issue_slots[14].brupdate.b2.uop.fp_single connect slots_14.io.brupdate.b2.uop.fp_val, issue_slots[14].brupdate.b2.uop.fp_val connect slots_14.io.brupdate.b2.uop.frs3_en, issue_slots[14].brupdate.b2.uop.frs3_en connect slots_14.io.brupdate.b2.uop.lrs2_rtype, issue_slots[14].brupdate.b2.uop.lrs2_rtype connect slots_14.io.brupdate.b2.uop.lrs1_rtype, issue_slots[14].brupdate.b2.uop.lrs1_rtype connect slots_14.io.brupdate.b2.uop.dst_rtype, issue_slots[14].brupdate.b2.uop.dst_rtype connect slots_14.io.brupdate.b2.uop.ldst_val, issue_slots[14].brupdate.b2.uop.ldst_val connect slots_14.io.brupdate.b2.uop.lrs3, issue_slots[14].brupdate.b2.uop.lrs3 connect slots_14.io.brupdate.b2.uop.lrs2, issue_slots[14].brupdate.b2.uop.lrs2 connect slots_14.io.brupdate.b2.uop.lrs1, issue_slots[14].brupdate.b2.uop.lrs1 connect slots_14.io.brupdate.b2.uop.ldst, issue_slots[14].brupdate.b2.uop.ldst connect slots_14.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[14].brupdate.b2.uop.ldst_is_rs1 connect slots_14.io.brupdate.b2.uop.flush_on_commit, issue_slots[14].brupdate.b2.uop.flush_on_commit connect slots_14.io.brupdate.b2.uop.is_unique, issue_slots[14].brupdate.b2.uop.is_unique connect slots_14.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[14].brupdate.b2.uop.is_sys_pc2epc connect slots_14.io.brupdate.b2.uop.uses_stq, issue_slots[14].brupdate.b2.uop.uses_stq connect slots_14.io.brupdate.b2.uop.uses_ldq, issue_slots[14].brupdate.b2.uop.uses_ldq connect slots_14.io.brupdate.b2.uop.is_amo, issue_slots[14].brupdate.b2.uop.is_amo connect slots_14.io.brupdate.b2.uop.is_fencei, issue_slots[14].brupdate.b2.uop.is_fencei connect slots_14.io.brupdate.b2.uop.is_fence, issue_slots[14].brupdate.b2.uop.is_fence connect slots_14.io.brupdate.b2.uop.mem_signed, issue_slots[14].brupdate.b2.uop.mem_signed connect slots_14.io.brupdate.b2.uop.mem_size, issue_slots[14].brupdate.b2.uop.mem_size connect slots_14.io.brupdate.b2.uop.mem_cmd, issue_slots[14].brupdate.b2.uop.mem_cmd connect slots_14.io.brupdate.b2.uop.bypassable, issue_slots[14].brupdate.b2.uop.bypassable connect slots_14.io.brupdate.b2.uop.exc_cause, issue_slots[14].brupdate.b2.uop.exc_cause connect slots_14.io.brupdate.b2.uop.exception, issue_slots[14].brupdate.b2.uop.exception connect slots_14.io.brupdate.b2.uop.stale_pdst, issue_slots[14].brupdate.b2.uop.stale_pdst connect slots_14.io.brupdate.b2.uop.ppred_busy, issue_slots[14].brupdate.b2.uop.ppred_busy connect slots_14.io.brupdate.b2.uop.prs3_busy, issue_slots[14].brupdate.b2.uop.prs3_busy connect slots_14.io.brupdate.b2.uop.prs2_busy, issue_slots[14].brupdate.b2.uop.prs2_busy connect slots_14.io.brupdate.b2.uop.prs1_busy, issue_slots[14].brupdate.b2.uop.prs1_busy connect slots_14.io.brupdate.b2.uop.ppred, issue_slots[14].brupdate.b2.uop.ppred connect slots_14.io.brupdate.b2.uop.prs3, issue_slots[14].brupdate.b2.uop.prs3 connect slots_14.io.brupdate.b2.uop.prs2, issue_slots[14].brupdate.b2.uop.prs2 connect slots_14.io.brupdate.b2.uop.prs1, issue_slots[14].brupdate.b2.uop.prs1 connect slots_14.io.brupdate.b2.uop.pdst, issue_slots[14].brupdate.b2.uop.pdst connect slots_14.io.brupdate.b2.uop.rxq_idx, issue_slots[14].brupdate.b2.uop.rxq_idx connect slots_14.io.brupdate.b2.uop.stq_idx, issue_slots[14].brupdate.b2.uop.stq_idx connect slots_14.io.brupdate.b2.uop.ldq_idx, issue_slots[14].brupdate.b2.uop.ldq_idx connect slots_14.io.brupdate.b2.uop.rob_idx, issue_slots[14].brupdate.b2.uop.rob_idx connect slots_14.io.brupdate.b2.uop.csr_addr, issue_slots[14].brupdate.b2.uop.csr_addr connect slots_14.io.brupdate.b2.uop.imm_packed, issue_slots[14].brupdate.b2.uop.imm_packed connect slots_14.io.brupdate.b2.uop.taken, issue_slots[14].brupdate.b2.uop.taken connect slots_14.io.brupdate.b2.uop.pc_lob, issue_slots[14].brupdate.b2.uop.pc_lob connect slots_14.io.brupdate.b2.uop.edge_inst, issue_slots[14].brupdate.b2.uop.edge_inst connect slots_14.io.brupdate.b2.uop.ftq_idx, issue_slots[14].brupdate.b2.uop.ftq_idx connect slots_14.io.brupdate.b2.uop.br_tag, issue_slots[14].brupdate.b2.uop.br_tag connect slots_14.io.brupdate.b2.uop.br_mask, issue_slots[14].brupdate.b2.uop.br_mask connect slots_14.io.brupdate.b2.uop.is_sfb, issue_slots[14].brupdate.b2.uop.is_sfb connect slots_14.io.brupdate.b2.uop.is_jal, issue_slots[14].brupdate.b2.uop.is_jal connect slots_14.io.brupdate.b2.uop.is_jalr, issue_slots[14].brupdate.b2.uop.is_jalr connect slots_14.io.brupdate.b2.uop.is_br, issue_slots[14].brupdate.b2.uop.is_br connect slots_14.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[14].brupdate.b2.uop.iw_p2_poisoned connect slots_14.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[14].brupdate.b2.uop.iw_p1_poisoned connect slots_14.io.brupdate.b2.uop.iw_state, issue_slots[14].brupdate.b2.uop.iw_state connect slots_14.io.brupdate.b2.uop.ctrl.is_std, issue_slots[14].brupdate.b2.uop.ctrl.is_std connect slots_14.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[14].brupdate.b2.uop.ctrl.is_sta connect slots_14.io.brupdate.b2.uop.ctrl.is_load, issue_slots[14].brupdate.b2.uop.ctrl.is_load connect slots_14.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[14].brupdate.b2.uop.ctrl.csr_cmd connect slots_14.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[14].brupdate.b2.uop.ctrl.fcn_dw connect slots_14.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[14].brupdate.b2.uop.ctrl.op_fcn connect slots_14.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[14].brupdate.b2.uop.ctrl.imm_sel connect slots_14.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[14].brupdate.b2.uop.ctrl.op2_sel connect slots_14.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[14].brupdate.b2.uop.ctrl.op1_sel connect slots_14.io.brupdate.b2.uop.ctrl.br_type, issue_slots[14].brupdate.b2.uop.ctrl.br_type connect slots_14.io.brupdate.b2.uop.fu_code, issue_slots[14].brupdate.b2.uop.fu_code connect slots_14.io.brupdate.b2.uop.iq_type, issue_slots[14].brupdate.b2.uop.iq_type connect slots_14.io.brupdate.b2.uop.debug_pc, issue_slots[14].brupdate.b2.uop.debug_pc connect slots_14.io.brupdate.b2.uop.is_rvc, issue_slots[14].brupdate.b2.uop.is_rvc connect slots_14.io.brupdate.b2.uop.debug_inst, issue_slots[14].brupdate.b2.uop.debug_inst connect slots_14.io.brupdate.b2.uop.inst, issue_slots[14].brupdate.b2.uop.inst connect slots_14.io.brupdate.b2.uop.uopc, issue_slots[14].brupdate.b2.uop.uopc connect slots_14.io.brupdate.b1.mispredict_mask, issue_slots[14].brupdate.b1.mispredict_mask connect slots_14.io.brupdate.b1.resolve_mask, issue_slots[14].brupdate.b1.resolve_mask connect slots_14.io.grant, issue_slots[14].grant connect issue_slots[14].request_hp, slots_14.io.request_hp connect issue_slots[14].request, slots_14.io.request connect issue_slots[14].will_be_valid, slots_14.io.will_be_valid connect issue_slots[14].valid, slots_14.io.valid connect issue_slots[15].debug.state, slots_15.io.debug.state connect issue_slots[15].debug.ppred, slots_15.io.debug.ppred connect issue_slots[15].debug.p3, slots_15.io.debug.p3 connect issue_slots[15].debug.p2, slots_15.io.debug.p2 connect issue_slots[15].debug.p1, slots_15.io.debug.p1 connect issue_slots[15].uop.debug_tsrc, slots_15.io.uop.debug_tsrc connect issue_slots[15].uop.debug_fsrc, slots_15.io.uop.debug_fsrc connect issue_slots[15].uop.bp_xcpt_if, slots_15.io.uop.bp_xcpt_if connect issue_slots[15].uop.bp_debug_if, slots_15.io.uop.bp_debug_if connect issue_slots[15].uop.xcpt_ma_if, slots_15.io.uop.xcpt_ma_if connect issue_slots[15].uop.xcpt_ae_if, slots_15.io.uop.xcpt_ae_if connect issue_slots[15].uop.xcpt_pf_if, slots_15.io.uop.xcpt_pf_if connect issue_slots[15].uop.fp_single, slots_15.io.uop.fp_single connect issue_slots[15].uop.fp_val, slots_15.io.uop.fp_val connect issue_slots[15].uop.frs3_en, slots_15.io.uop.frs3_en connect issue_slots[15].uop.lrs2_rtype, slots_15.io.uop.lrs2_rtype connect issue_slots[15].uop.lrs1_rtype, slots_15.io.uop.lrs1_rtype connect issue_slots[15].uop.dst_rtype, slots_15.io.uop.dst_rtype connect issue_slots[15].uop.ldst_val, slots_15.io.uop.ldst_val connect issue_slots[15].uop.lrs3, slots_15.io.uop.lrs3 connect issue_slots[15].uop.lrs2, slots_15.io.uop.lrs2 connect issue_slots[15].uop.lrs1, slots_15.io.uop.lrs1 connect issue_slots[15].uop.ldst, slots_15.io.uop.ldst connect issue_slots[15].uop.ldst_is_rs1, slots_15.io.uop.ldst_is_rs1 connect issue_slots[15].uop.flush_on_commit, slots_15.io.uop.flush_on_commit connect issue_slots[15].uop.is_unique, slots_15.io.uop.is_unique connect issue_slots[15].uop.is_sys_pc2epc, slots_15.io.uop.is_sys_pc2epc connect issue_slots[15].uop.uses_stq, slots_15.io.uop.uses_stq connect issue_slots[15].uop.uses_ldq, slots_15.io.uop.uses_ldq connect issue_slots[15].uop.is_amo, slots_15.io.uop.is_amo connect issue_slots[15].uop.is_fencei, slots_15.io.uop.is_fencei connect issue_slots[15].uop.is_fence, slots_15.io.uop.is_fence connect issue_slots[15].uop.mem_signed, slots_15.io.uop.mem_signed connect issue_slots[15].uop.mem_size, slots_15.io.uop.mem_size connect issue_slots[15].uop.mem_cmd, slots_15.io.uop.mem_cmd connect issue_slots[15].uop.bypassable, slots_15.io.uop.bypassable connect issue_slots[15].uop.exc_cause, slots_15.io.uop.exc_cause connect issue_slots[15].uop.exception, slots_15.io.uop.exception connect issue_slots[15].uop.stale_pdst, slots_15.io.uop.stale_pdst connect issue_slots[15].uop.ppred_busy, slots_15.io.uop.ppred_busy connect issue_slots[15].uop.prs3_busy, slots_15.io.uop.prs3_busy connect issue_slots[15].uop.prs2_busy, slots_15.io.uop.prs2_busy connect issue_slots[15].uop.prs1_busy, slots_15.io.uop.prs1_busy connect issue_slots[15].uop.ppred, slots_15.io.uop.ppred connect issue_slots[15].uop.prs3, slots_15.io.uop.prs3 connect issue_slots[15].uop.prs2, slots_15.io.uop.prs2 connect issue_slots[15].uop.prs1, slots_15.io.uop.prs1 connect issue_slots[15].uop.pdst, slots_15.io.uop.pdst connect issue_slots[15].uop.rxq_idx, slots_15.io.uop.rxq_idx connect issue_slots[15].uop.stq_idx, slots_15.io.uop.stq_idx connect issue_slots[15].uop.ldq_idx, slots_15.io.uop.ldq_idx connect issue_slots[15].uop.rob_idx, slots_15.io.uop.rob_idx connect issue_slots[15].uop.csr_addr, slots_15.io.uop.csr_addr connect issue_slots[15].uop.imm_packed, slots_15.io.uop.imm_packed connect issue_slots[15].uop.taken, slots_15.io.uop.taken connect issue_slots[15].uop.pc_lob, slots_15.io.uop.pc_lob connect issue_slots[15].uop.edge_inst, slots_15.io.uop.edge_inst connect issue_slots[15].uop.ftq_idx, slots_15.io.uop.ftq_idx connect issue_slots[15].uop.br_tag, slots_15.io.uop.br_tag connect issue_slots[15].uop.br_mask, slots_15.io.uop.br_mask connect issue_slots[15].uop.is_sfb, slots_15.io.uop.is_sfb connect issue_slots[15].uop.is_jal, slots_15.io.uop.is_jal connect issue_slots[15].uop.is_jalr, slots_15.io.uop.is_jalr connect issue_slots[15].uop.is_br, slots_15.io.uop.is_br connect issue_slots[15].uop.iw_p2_poisoned, slots_15.io.uop.iw_p2_poisoned connect issue_slots[15].uop.iw_p1_poisoned, slots_15.io.uop.iw_p1_poisoned connect issue_slots[15].uop.iw_state, slots_15.io.uop.iw_state connect issue_slots[15].uop.ctrl.is_std, slots_15.io.uop.ctrl.is_std connect issue_slots[15].uop.ctrl.is_sta, slots_15.io.uop.ctrl.is_sta connect issue_slots[15].uop.ctrl.is_load, slots_15.io.uop.ctrl.is_load connect issue_slots[15].uop.ctrl.csr_cmd, slots_15.io.uop.ctrl.csr_cmd connect issue_slots[15].uop.ctrl.fcn_dw, slots_15.io.uop.ctrl.fcn_dw connect issue_slots[15].uop.ctrl.op_fcn, slots_15.io.uop.ctrl.op_fcn connect issue_slots[15].uop.ctrl.imm_sel, slots_15.io.uop.ctrl.imm_sel connect issue_slots[15].uop.ctrl.op2_sel, slots_15.io.uop.ctrl.op2_sel connect issue_slots[15].uop.ctrl.op1_sel, slots_15.io.uop.ctrl.op1_sel connect issue_slots[15].uop.ctrl.br_type, slots_15.io.uop.ctrl.br_type connect issue_slots[15].uop.fu_code, slots_15.io.uop.fu_code connect issue_slots[15].uop.iq_type, slots_15.io.uop.iq_type connect issue_slots[15].uop.debug_pc, slots_15.io.uop.debug_pc connect issue_slots[15].uop.is_rvc, slots_15.io.uop.is_rvc connect issue_slots[15].uop.debug_inst, slots_15.io.uop.debug_inst connect issue_slots[15].uop.inst, slots_15.io.uop.inst connect issue_slots[15].uop.uopc, slots_15.io.uop.uopc connect issue_slots[15].out_uop.debug_tsrc, slots_15.io.out_uop.debug_tsrc connect issue_slots[15].out_uop.debug_fsrc, slots_15.io.out_uop.debug_fsrc connect issue_slots[15].out_uop.bp_xcpt_if, slots_15.io.out_uop.bp_xcpt_if connect issue_slots[15].out_uop.bp_debug_if, slots_15.io.out_uop.bp_debug_if connect issue_slots[15].out_uop.xcpt_ma_if, slots_15.io.out_uop.xcpt_ma_if connect issue_slots[15].out_uop.xcpt_ae_if, slots_15.io.out_uop.xcpt_ae_if connect issue_slots[15].out_uop.xcpt_pf_if, slots_15.io.out_uop.xcpt_pf_if connect issue_slots[15].out_uop.fp_single, slots_15.io.out_uop.fp_single connect issue_slots[15].out_uop.fp_val, slots_15.io.out_uop.fp_val connect issue_slots[15].out_uop.frs3_en, slots_15.io.out_uop.frs3_en connect issue_slots[15].out_uop.lrs2_rtype, slots_15.io.out_uop.lrs2_rtype connect issue_slots[15].out_uop.lrs1_rtype, slots_15.io.out_uop.lrs1_rtype connect issue_slots[15].out_uop.dst_rtype, slots_15.io.out_uop.dst_rtype connect issue_slots[15].out_uop.ldst_val, slots_15.io.out_uop.ldst_val connect issue_slots[15].out_uop.lrs3, slots_15.io.out_uop.lrs3 connect issue_slots[15].out_uop.lrs2, slots_15.io.out_uop.lrs2 connect issue_slots[15].out_uop.lrs1, slots_15.io.out_uop.lrs1 connect issue_slots[15].out_uop.ldst, slots_15.io.out_uop.ldst connect issue_slots[15].out_uop.ldst_is_rs1, slots_15.io.out_uop.ldst_is_rs1 connect issue_slots[15].out_uop.flush_on_commit, slots_15.io.out_uop.flush_on_commit connect issue_slots[15].out_uop.is_unique, slots_15.io.out_uop.is_unique connect issue_slots[15].out_uop.is_sys_pc2epc, slots_15.io.out_uop.is_sys_pc2epc connect issue_slots[15].out_uop.uses_stq, slots_15.io.out_uop.uses_stq connect issue_slots[15].out_uop.uses_ldq, slots_15.io.out_uop.uses_ldq connect issue_slots[15].out_uop.is_amo, slots_15.io.out_uop.is_amo connect issue_slots[15].out_uop.is_fencei, slots_15.io.out_uop.is_fencei connect issue_slots[15].out_uop.is_fence, slots_15.io.out_uop.is_fence connect issue_slots[15].out_uop.mem_signed, slots_15.io.out_uop.mem_signed connect issue_slots[15].out_uop.mem_size, slots_15.io.out_uop.mem_size connect issue_slots[15].out_uop.mem_cmd, slots_15.io.out_uop.mem_cmd connect issue_slots[15].out_uop.bypassable, slots_15.io.out_uop.bypassable connect issue_slots[15].out_uop.exc_cause, slots_15.io.out_uop.exc_cause connect issue_slots[15].out_uop.exception, slots_15.io.out_uop.exception connect issue_slots[15].out_uop.stale_pdst, slots_15.io.out_uop.stale_pdst connect issue_slots[15].out_uop.ppred_busy, slots_15.io.out_uop.ppred_busy connect issue_slots[15].out_uop.prs3_busy, slots_15.io.out_uop.prs3_busy connect issue_slots[15].out_uop.prs2_busy, slots_15.io.out_uop.prs2_busy connect issue_slots[15].out_uop.prs1_busy, slots_15.io.out_uop.prs1_busy connect issue_slots[15].out_uop.ppred, slots_15.io.out_uop.ppred connect issue_slots[15].out_uop.prs3, slots_15.io.out_uop.prs3 connect issue_slots[15].out_uop.prs2, slots_15.io.out_uop.prs2 connect issue_slots[15].out_uop.prs1, slots_15.io.out_uop.prs1 connect issue_slots[15].out_uop.pdst, slots_15.io.out_uop.pdst connect issue_slots[15].out_uop.rxq_idx, slots_15.io.out_uop.rxq_idx connect issue_slots[15].out_uop.stq_idx, slots_15.io.out_uop.stq_idx connect issue_slots[15].out_uop.ldq_idx, slots_15.io.out_uop.ldq_idx connect issue_slots[15].out_uop.rob_idx, slots_15.io.out_uop.rob_idx connect issue_slots[15].out_uop.csr_addr, slots_15.io.out_uop.csr_addr connect issue_slots[15].out_uop.imm_packed, slots_15.io.out_uop.imm_packed connect issue_slots[15].out_uop.taken, slots_15.io.out_uop.taken connect issue_slots[15].out_uop.pc_lob, slots_15.io.out_uop.pc_lob connect issue_slots[15].out_uop.edge_inst, slots_15.io.out_uop.edge_inst connect issue_slots[15].out_uop.ftq_idx, slots_15.io.out_uop.ftq_idx connect issue_slots[15].out_uop.br_tag, slots_15.io.out_uop.br_tag connect issue_slots[15].out_uop.br_mask, slots_15.io.out_uop.br_mask connect issue_slots[15].out_uop.is_sfb, slots_15.io.out_uop.is_sfb connect issue_slots[15].out_uop.is_jal, slots_15.io.out_uop.is_jal connect issue_slots[15].out_uop.is_jalr, slots_15.io.out_uop.is_jalr connect issue_slots[15].out_uop.is_br, slots_15.io.out_uop.is_br connect issue_slots[15].out_uop.iw_p2_poisoned, slots_15.io.out_uop.iw_p2_poisoned connect issue_slots[15].out_uop.iw_p1_poisoned, slots_15.io.out_uop.iw_p1_poisoned connect issue_slots[15].out_uop.iw_state, slots_15.io.out_uop.iw_state connect issue_slots[15].out_uop.ctrl.is_std, slots_15.io.out_uop.ctrl.is_std connect issue_slots[15].out_uop.ctrl.is_sta, slots_15.io.out_uop.ctrl.is_sta connect issue_slots[15].out_uop.ctrl.is_load, slots_15.io.out_uop.ctrl.is_load connect issue_slots[15].out_uop.ctrl.csr_cmd, slots_15.io.out_uop.ctrl.csr_cmd connect issue_slots[15].out_uop.ctrl.fcn_dw, slots_15.io.out_uop.ctrl.fcn_dw connect issue_slots[15].out_uop.ctrl.op_fcn, slots_15.io.out_uop.ctrl.op_fcn connect issue_slots[15].out_uop.ctrl.imm_sel, slots_15.io.out_uop.ctrl.imm_sel connect issue_slots[15].out_uop.ctrl.op2_sel, slots_15.io.out_uop.ctrl.op2_sel connect issue_slots[15].out_uop.ctrl.op1_sel, slots_15.io.out_uop.ctrl.op1_sel connect issue_slots[15].out_uop.ctrl.br_type, slots_15.io.out_uop.ctrl.br_type connect issue_slots[15].out_uop.fu_code, slots_15.io.out_uop.fu_code connect issue_slots[15].out_uop.iq_type, slots_15.io.out_uop.iq_type connect issue_slots[15].out_uop.debug_pc, slots_15.io.out_uop.debug_pc connect issue_slots[15].out_uop.is_rvc, slots_15.io.out_uop.is_rvc connect issue_slots[15].out_uop.debug_inst, slots_15.io.out_uop.debug_inst connect issue_slots[15].out_uop.inst, slots_15.io.out_uop.inst connect issue_slots[15].out_uop.uopc, slots_15.io.out_uop.uopc connect slots_15.io.in_uop.bits.debug_tsrc, issue_slots[15].in_uop.bits.debug_tsrc connect slots_15.io.in_uop.bits.debug_fsrc, issue_slots[15].in_uop.bits.debug_fsrc connect slots_15.io.in_uop.bits.bp_xcpt_if, issue_slots[15].in_uop.bits.bp_xcpt_if connect slots_15.io.in_uop.bits.bp_debug_if, issue_slots[15].in_uop.bits.bp_debug_if connect slots_15.io.in_uop.bits.xcpt_ma_if, issue_slots[15].in_uop.bits.xcpt_ma_if connect slots_15.io.in_uop.bits.xcpt_ae_if, issue_slots[15].in_uop.bits.xcpt_ae_if connect slots_15.io.in_uop.bits.xcpt_pf_if, issue_slots[15].in_uop.bits.xcpt_pf_if connect slots_15.io.in_uop.bits.fp_single, issue_slots[15].in_uop.bits.fp_single connect slots_15.io.in_uop.bits.fp_val, issue_slots[15].in_uop.bits.fp_val connect slots_15.io.in_uop.bits.frs3_en, issue_slots[15].in_uop.bits.frs3_en connect slots_15.io.in_uop.bits.lrs2_rtype, issue_slots[15].in_uop.bits.lrs2_rtype connect slots_15.io.in_uop.bits.lrs1_rtype, issue_slots[15].in_uop.bits.lrs1_rtype connect slots_15.io.in_uop.bits.dst_rtype, issue_slots[15].in_uop.bits.dst_rtype connect slots_15.io.in_uop.bits.ldst_val, issue_slots[15].in_uop.bits.ldst_val connect slots_15.io.in_uop.bits.lrs3, issue_slots[15].in_uop.bits.lrs3 connect slots_15.io.in_uop.bits.lrs2, issue_slots[15].in_uop.bits.lrs2 connect slots_15.io.in_uop.bits.lrs1, issue_slots[15].in_uop.bits.lrs1 connect slots_15.io.in_uop.bits.ldst, issue_slots[15].in_uop.bits.ldst connect slots_15.io.in_uop.bits.ldst_is_rs1, issue_slots[15].in_uop.bits.ldst_is_rs1 connect slots_15.io.in_uop.bits.flush_on_commit, issue_slots[15].in_uop.bits.flush_on_commit connect slots_15.io.in_uop.bits.is_unique, issue_slots[15].in_uop.bits.is_unique connect slots_15.io.in_uop.bits.is_sys_pc2epc, issue_slots[15].in_uop.bits.is_sys_pc2epc connect slots_15.io.in_uop.bits.uses_stq, issue_slots[15].in_uop.bits.uses_stq connect slots_15.io.in_uop.bits.uses_ldq, issue_slots[15].in_uop.bits.uses_ldq connect slots_15.io.in_uop.bits.is_amo, issue_slots[15].in_uop.bits.is_amo connect slots_15.io.in_uop.bits.is_fencei, issue_slots[15].in_uop.bits.is_fencei connect slots_15.io.in_uop.bits.is_fence, issue_slots[15].in_uop.bits.is_fence connect slots_15.io.in_uop.bits.mem_signed, issue_slots[15].in_uop.bits.mem_signed connect slots_15.io.in_uop.bits.mem_size, issue_slots[15].in_uop.bits.mem_size connect slots_15.io.in_uop.bits.mem_cmd, issue_slots[15].in_uop.bits.mem_cmd connect slots_15.io.in_uop.bits.bypassable, issue_slots[15].in_uop.bits.bypassable connect slots_15.io.in_uop.bits.exc_cause, issue_slots[15].in_uop.bits.exc_cause connect slots_15.io.in_uop.bits.exception, issue_slots[15].in_uop.bits.exception connect slots_15.io.in_uop.bits.stale_pdst, issue_slots[15].in_uop.bits.stale_pdst connect slots_15.io.in_uop.bits.ppred_busy, issue_slots[15].in_uop.bits.ppred_busy connect slots_15.io.in_uop.bits.prs3_busy, issue_slots[15].in_uop.bits.prs3_busy connect slots_15.io.in_uop.bits.prs2_busy, issue_slots[15].in_uop.bits.prs2_busy connect slots_15.io.in_uop.bits.prs1_busy, issue_slots[15].in_uop.bits.prs1_busy connect slots_15.io.in_uop.bits.ppred, issue_slots[15].in_uop.bits.ppred connect slots_15.io.in_uop.bits.prs3, issue_slots[15].in_uop.bits.prs3 connect slots_15.io.in_uop.bits.prs2, issue_slots[15].in_uop.bits.prs2 connect slots_15.io.in_uop.bits.prs1, issue_slots[15].in_uop.bits.prs1 connect slots_15.io.in_uop.bits.pdst, issue_slots[15].in_uop.bits.pdst connect slots_15.io.in_uop.bits.rxq_idx, issue_slots[15].in_uop.bits.rxq_idx connect slots_15.io.in_uop.bits.stq_idx, issue_slots[15].in_uop.bits.stq_idx connect slots_15.io.in_uop.bits.ldq_idx, issue_slots[15].in_uop.bits.ldq_idx connect slots_15.io.in_uop.bits.rob_idx, issue_slots[15].in_uop.bits.rob_idx connect slots_15.io.in_uop.bits.csr_addr, issue_slots[15].in_uop.bits.csr_addr connect slots_15.io.in_uop.bits.imm_packed, issue_slots[15].in_uop.bits.imm_packed connect slots_15.io.in_uop.bits.taken, issue_slots[15].in_uop.bits.taken connect slots_15.io.in_uop.bits.pc_lob, issue_slots[15].in_uop.bits.pc_lob connect slots_15.io.in_uop.bits.edge_inst, issue_slots[15].in_uop.bits.edge_inst connect slots_15.io.in_uop.bits.ftq_idx, issue_slots[15].in_uop.bits.ftq_idx connect slots_15.io.in_uop.bits.br_tag, issue_slots[15].in_uop.bits.br_tag connect slots_15.io.in_uop.bits.br_mask, issue_slots[15].in_uop.bits.br_mask connect slots_15.io.in_uop.bits.is_sfb, issue_slots[15].in_uop.bits.is_sfb connect slots_15.io.in_uop.bits.is_jal, issue_slots[15].in_uop.bits.is_jal connect slots_15.io.in_uop.bits.is_jalr, issue_slots[15].in_uop.bits.is_jalr connect slots_15.io.in_uop.bits.is_br, issue_slots[15].in_uop.bits.is_br connect slots_15.io.in_uop.bits.iw_p2_poisoned, issue_slots[15].in_uop.bits.iw_p2_poisoned connect slots_15.io.in_uop.bits.iw_p1_poisoned, issue_slots[15].in_uop.bits.iw_p1_poisoned connect slots_15.io.in_uop.bits.iw_state, issue_slots[15].in_uop.bits.iw_state connect slots_15.io.in_uop.bits.ctrl.is_std, issue_slots[15].in_uop.bits.ctrl.is_std connect slots_15.io.in_uop.bits.ctrl.is_sta, issue_slots[15].in_uop.bits.ctrl.is_sta connect slots_15.io.in_uop.bits.ctrl.is_load, issue_slots[15].in_uop.bits.ctrl.is_load connect slots_15.io.in_uop.bits.ctrl.csr_cmd, issue_slots[15].in_uop.bits.ctrl.csr_cmd connect slots_15.io.in_uop.bits.ctrl.fcn_dw, issue_slots[15].in_uop.bits.ctrl.fcn_dw connect slots_15.io.in_uop.bits.ctrl.op_fcn, issue_slots[15].in_uop.bits.ctrl.op_fcn connect slots_15.io.in_uop.bits.ctrl.imm_sel, issue_slots[15].in_uop.bits.ctrl.imm_sel connect slots_15.io.in_uop.bits.ctrl.op2_sel, issue_slots[15].in_uop.bits.ctrl.op2_sel connect slots_15.io.in_uop.bits.ctrl.op1_sel, issue_slots[15].in_uop.bits.ctrl.op1_sel connect slots_15.io.in_uop.bits.ctrl.br_type, issue_slots[15].in_uop.bits.ctrl.br_type connect slots_15.io.in_uop.bits.fu_code, issue_slots[15].in_uop.bits.fu_code connect slots_15.io.in_uop.bits.iq_type, issue_slots[15].in_uop.bits.iq_type connect slots_15.io.in_uop.bits.debug_pc, issue_slots[15].in_uop.bits.debug_pc connect slots_15.io.in_uop.bits.is_rvc, issue_slots[15].in_uop.bits.is_rvc connect slots_15.io.in_uop.bits.debug_inst, issue_slots[15].in_uop.bits.debug_inst connect slots_15.io.in_uop.bits.inst, issue_slots[15].in_uop.bits.inst connect slots_15.io.in_uop.bits.uopc, issue_slots[15].in_uop.bits.uopc connect slots_15.io.in_uop.valid, issue_slots[15].in_uop.valid connect slots_15.io.spec_ld_wakeup[0].bits, issue_slots[15].spec_ld_wakeup[0].bits connect slots_15.io.spec_ld_wakeup[0].valid, issue_slots[15].spec_ld_wakeup[0].valid connect slots_15.io.pred_wakeup_port.bits, issue_slots[15].pred_wakeup_port.bits connect slots_15.io.pred_wakeup_port.valid, issue_slots[15].pred_wakeup_port.valid connect slots_15.io.wakeup_ports[0].bits.poisoned, issue_slots[15].wakeup_ports[0].bits.poisoned connect slots_15.io.wakeup_ports[0].bits.pdst, issue_slots[15].wakeup_ports[0].bits.pdst connect slots_15.io.wakeup_ports[0].valid, issue_slots[15].wakeup_ports[0].valid connect slots_15.io.wakeup_ports[1].bits.poisoned, issue_slots[15].wakeup_ports[1].bits.poisoned connect slots_15.io.wakeup_ports[1].bits.pdst, issue_slots[15].wakeup_ports[1].bits.pdst connect slots_15.io.wakeup_ports[1].valid, issue_slots[15].wakeup_ports[1].valid connect slots_15.io.wakeup_ports[2].bits.poisoned, issue_slots[15].wakeup_ports[2].bits.poisoned connect slots_15.io.wakeup_ports[2].bits.pdst, issue_slots[15].wakeup_ports[2].bits.pdst connect slots_15.io.wakeup_ports[2].valid, issue_slots[15].wakeup_ports[2].valid connect slots_15.io.wakeup_ports[3].bits.poisoned, issue_slots[15].wakeup_ports[3].bits.poisoned connect slots_15.io.wakeup_ports[3].bits.pdst, issue_slots[15].wakeup_ports[3].bits.pdst connect slots_15.io.wakeup_ports[3].valid, issue_slots[15].wakeup_ports[3].valid connect slots_15.io.wakeup_ports[4].bits.poisoned, issue_slots[15].wakeup_ports[4].bits.poisoned connect slots_15.io.wakeup_ports[4].bits.pdst, issue_slots[15].wakeup_ports[4].bits.pdst connect slots_15.io.wakeup_ports[4].valid, issue_slots[15].wakeup_ports[4].valid connect slots_15.io.wakeup_ports[5].bits.poisoned, issue_slots[15].wakeup_ports[5].bits.poisoned connect slots_15.io.wakeup_ports[5].bits.pdst, issue_slots[15].wakeup_ports[5].bits.pdst connect slots_15.io.wakeup_ports[5].valid, issue_slots[15].wakeup_ports[5].valid connect slots_15.io.wakeup_ports[6].bits.poisoned, issue_slots[15].wakeup_ports[6].bits.poisoned connect slots_15.io.wakeup_ports[6].bits.pdst, issue_slots[15].wakeup_ports[6].bits.pdst connect slots_15.io.wakeup_ports[6].valid, issue_slots[15].wakeup_ports[6].valid connect slots_15.io.ldspec_miss, issue_slots[15].ldspec_miss connect slots_15.io.clear, issue_slots[15].clear connect slots_15.io.kill, issue_slots[15].kill connect slots_15.io.brupdate.b2.target_offset, issue_slots[15].brupdate.b2.target_offset connect slots_15.io.brupdate.b2.jalr_target, issue_slots[15].brupdate.b2.jalr_target connect slots_15.io.brupdate.b2.pc_sel, issue_slots[15].brupdate.b2.pc_sel connect slots_15.io.brupdate.b2.cfi_type, issue_slots[15].brupdate.b2.cfi_type connect slots_15.io.brupdate.b2.taken, issue_slots[15].brupdate.b2.taken connect slots_15.io.brupdate.b2.mispredict, issue_slots[15].brupdate.b2.mispredict connect slots_15.io.brupdate.b2.valid, issue_slots[15].brupdate.b2.valid connect slots_15.io.brupdate.b2.uop.debug_tsrc, issue_slots[15].brupdate.b2.uop.debug_tsrc connect slots_15.io.brupdate.b2.uop.debug_fsrc, issue_slots[15].brupdate.b2.uop.debug_fsrc connect slots_15.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[15].brupdate.b2.uop.bp_xcpt_if connect slots_15.io.brupdate.b2.uop.bp_debug_if, issue_slots[15].brupdate.b2.uop.bp_debug_if connect slots_15.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[15].brupdate.b2.uop.xcpt_ma_if connect slots_15.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[15].brupdate.b2.uop.xcpt_ae_if connect slots_15.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[15].brupdate.b2.uop.xcpt_pf_if connect slots_15.io.brupdate.b2.uop.fp_single, issue_slots[15].brupdate.b2.uop.fp_single connect slots_15.io.brupdate.b2.uop.fp_val, issue_slots[15].brupdate.b2.uop.fp_val connect slots_15.io.brupdate.b2.uop.frs3_en, issue_slots[15].brupdate.b2.uop.frs3_en connect slots_15.io.brupdate.b2.uop.lrs2_rtype, issue_slots[15].brupdate.b2.uop.lrs2_rtype connect slots_15.io.brupdate.b2.uop.lrs1_rtype, issue_slots[15].brupdate.b2.uop.lrs1_rtype connect slots_15.io.brupdate.b2.uop.dst_rtype, issue_slots[15].brupdate.b2.uop.dst_rtype connect slots_15.io.brupdate.b2.uop.ldst_val, issue_slots[15].brupdate.b2.uop.ldst_val connect slots_15.io.brupdate.b2.uop.lrs3, issue_slots[15].brupdate.b2.uop.lrs3 connect slots_15.io.brupdate.b2.uop.lrs2, issue_slots[15].brupdate.b2.uop.lrs2 connect slots_15.io.brupdate.b2.uop.lrs1, issue_slots[15].brupdate.b2.uop.lrs1 connect slots_15.io.brupdate.b2.uop.ldst, issue_slots[15].brupdate.b2.uop.ldst connect slots_15.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[15].brupdate.b2.uop.ldst_is_rs1 connect slots_15.io.brupdate.b2.uop.flush_on_commit, issue_slots[15].brupdate.b2.uop.flush_on_commit connect slots_15.io.brupdate.b2.uop.is_unique, issue_slots[15].brupdate.b2.uop.is_unique connect slots_15.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[15].brupdate.b2.uop.is_sys_pc2epc connect slots_15.io.brupdate.b2.uop.uses_stq, issue_slots[15].brupdate.b2.uop.uses_stq connect slots_15.io.brupdate.b2.uop.uses_ldq, issue_slots[15].brupdate.b2.uop.uses_ldq connect slots_15.io.brupdate.b2.uop.is_amo, issue_slots[15].brupdate.b2.uop.is_amo connect slots_15.io.brupdate.b2.uop.is_fencei, issue_slots[15].brupdate.b2.uop.is_fencei connect slots_15.io.brupdate.b2.uop.is_fence, issue_slots[15].brupdate.b2.uop.is_fence connect slots_15.io.brupdate.b2.uop.mem_signed, issue_slots[15].brupdate.b2.uop.mem_signed connect slots_15.io.brupdate.b2.uop.mem_size, issue_slots[15].brupdate.b2.uop.mem_size connect slots_15.io.brupdate.b2.uop.mem_cmd, issue_slots[15].brupdate.b2.uop.mem_cmd connect slots_15.io.brupdate.b2.uop.bypassable, issue_slots[15].brupdate.b2.uop.bypassable connect slots_15.io.brupdate.b2.uop.exc_cause, issue_slots[15].brupdate.b2.uop.exc_cause connect slots_15.io.brupdate.b2.uop.exception, issue_slots[15].brupdate.b2.uop.exception connect slots_15.io.brupdate.b2.uop.stale_pdst, issue_slots[15].brupdate.b2.uop.stale_pdst connect slots_15.io.brupdate.b2.uop.ppred_busy, issue_slots[15].brupdate.b2.uop.ppred_busy connect slots_15.io.brupdate.b2.uop.prs3_busy, issue_slots[15].brupdate.b2.uop.prs3_busy connect slots_15.io.brupdate.b2.uop.prs2_busy, issue_slots[15].brupdate.b2.uop.prs2_busy connect slots_15.io.brupdate.b2.uop.prs1_busy, issue_slots[15].brupdate.b2.uop.prs1_busy connect slots_15.io.brupdate.b2.uop.ppred, issue_slots[15].brupdate.b2.uop.ppred connect slots_15.io.brupdate.b2.uop.prs3, issue_slots[15].brupdate.b2.uop.prs3 connect slots_15.io.brupdate.b2.uop.prs2, issue_slots[15].brupdate.b2.uop.prs2 connect slots_15.io.brupdate.b2.uop.prs1, issue_slots[15].brupdate.b2.uop.prs1 connect slots_15.io.brupdate.b2.uop.pdst, issue_slots[15].brupdate.b2.uop.pdst connect slots_15.io.brupdate.b2.uop.rxq_idx, issue_slots[15].brupdate.b2.uop.rxq_idx connect slots_15.io.brupdate.b2.uop.stq_idx, issue_slots[15].brupdate.b2.uop.stq_idx connect slots_15.io.brupdate.b2.uop.ldq_idx, issue_slots[15].brupdate.b2.uop.ldq_idx connect slots_15.io.brupdate.b2.uop.rob_idx, issue_slots[15].brupdate.b2.uop.rob_idx connect slots_15.io.brupdate.b2.uop.csr_addr, issue_slots[15].brupdate.b2.uop.csr_addr connect slots_15.io.brupdate.b2.uop.imm_packed, issue_slots[15].brupdate.b2.uop.imm_packed connect slots_15.io.brupdate.b2.uop.taken, issue_slots[15].brupdate.b2.uop.taken connect slots_15.io.brupdate.b2.uop.pc_lob, issue_slots[15].brupdate.b2.uop.pc_lob connect slots_15.io.brupdate.b2.uop.edge_inst, issue_slots[15].brupdate.b2.uop.edge_inst connect slots_15.io.brupdate.b2.uop.ftq_idx, issue_slots[15].brupdate.b2.uop.ftq_idx connect slots_15.io.brupdate.b2.uop.br_tag, issue_slots[15].brupdate.b2.uop.br_tag connect slots_15.io.brupdate.b2.uop.br_mask, issue_slots[15].brupdate.b2.uop.br_mask connect slots_15.io.brupdate.b2.uop.is_sfb, issue_slots[15].brupdate.b2.uop.is_sfb connect slots_15.io.brupdate.b2.uop.is_jal, issue_slots[15].brupdate.b2.uop.is_jal connect slots_15.io.brupdate.b2.uop.is_jalr, issue_slots[15].brupdate.b2.uop.is_jalr connect slots_15.io.brupdate.b2.uop.is_br, issue_slots[15].brupdate.b2.uop.is_br connect slots_15.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[15].brupdate.b2.uop.iw_p2_poisoned connect slots_15.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[15].brupdate.b2.uop.iw_p1_poisoned connect slots_15.io.brupdate.b2.uop.iw_state, issue_slots[15].brupdate.b2.uop.iw_state connect slots_15.io.brupdate.b2.uop.ctrl.is_std, issue_slots[15].brupdate.b2.uop.ctrl.is_std connect slots_15.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[15].brupdate.b2.uop.ctrl.is_sta connect slots_15.io.brupdate.b2.uop.ctrl.is_load, issue_slots[15].brupdate.b2.uop.ctrl.is_load connect slots_15.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[15].brupdate.b2.uop.ctrl.csr_cmd connect slots_15.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[15].brupdate.b2.uop.ctrl.fcn_dw connect slots_15.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[15].brupdate.b2.uop.ctrl.op_fcn connect slots_15.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[15].brupdate.b2.uop.ctrl.imm_sel connect slots_15.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[15].brupdate.b2.uop.ctrl.op2_sel connect slots_15.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[15].brupdate.b2.uop.ctrl.op1_sel connect slots_15.io.brupdate.b2.uop.ctrl.br_type, issue_slots[15].brupdate.b2.uop.ctrl.br_type connect slots_15.io.brupdate.b2.uop.fu_code, issue_slots[15].brupdate.b2.uop.fu_code connect slots_15.io.brupdate.b2.uop.iq_type, issue_slots[15].brupdate.b2.uop.iq_type connect slots_15.io.brupdate.b2.uop.debug_pc, issue_slots[15].brupdate.b2.uop.debug_pc connect slots_15.io.brupdate.b2.uop.is_rvc, issue_slots[15].brupdate.b2.uop.is_rvc connect slots_15.io.brupdate.b2.uop.debug_inst, issue_slots[15].brupdate.b2.uop.debug_inst connect slots_15.io.brupdate.b2.uop.inst, issue_slots[15].brupdate.b2.uop.inst connect slots_15.io.brupdate.b2.uop.uopc, issue_slots[15].brupdate.b2.uop.uopc connect slots_15.io.brupdate.b1.mispredict_mask, issue_slots[15].brupdate.b1.mispredict_mask connect slots_15.io.brupdate.b1.resolve_mask, issue_slots[15].brupdate.b1.resolve_mask connect slots_15.io.grant, issue_slots[15].grant connect issue_slots[15].request_hp, slots_15.io.request_hp connect issue_slots[15].request, slots_15.io.request connect issue_slots[15].will_be_valid, slots_15.io.will_be_valid connect issue_slots[15].valid, slots_15.io.valid connect issue_slots[16].debug.state, slots_16.io.debug.state connect issue_slots[16].debug.ppred, slots_16.io.debug.ppred connect issue_slots[16].debug.p3, slots_16.io.debug.p3 connect issue_slots[16].debug.p2, slots_16.io.debug.p2 connect issue_slots[16].debug.p1, slots_16.io.debug.p1 connect issue_slots[16].uop.debug_tsrc, slots_16.io.uop.debug_tsrc connect issue_slots[16].uop.debug_fsrc, slots_16.io.uop.debug_fsrc connect issue_slots[16].uop.bp_xcpt_if, slots_16.io.uop.bp_xcpt_if connect issue_slots[16].uop.bp_debug_if, slots_16.io.uop.bp_debug_if connect issue_slots[16].uop.xcpt_ma_if, slots_16.io.uop.xcpt_ma_if connect issue_slots[16].uop.xcpt_ae_if, slots_16.io.uop.xcpt_ae_if connect issue_slots[16].uop.xcpt_pf_if, slots_16.io.uop.xcpt_pf_if connect issue_slots[16].uop.fp_single, slots_16.io.uop.fp_single connect issue_slots[16].uop.fp_val, slots_16.io.uop.fp_val connect issue_slots[16].uop.frs3_en, slots_16.io.uop.frs3_en connect issue_slots[16].uop.lrs2_rtype, slots_16.io.uop.lrs2_rtype connect issue_slots[16].uop.lrs1_rtype, slots_16.io.uop.lrs1_rtype connect issue_slots[16].uop.dst_rtype, slots_16.io.uop.dst_rtype connect issue_slots[16].uop.ldst_val, slots_16.io.uop.ldst_val connect issue_slots[16].uop.lrs3, slots_16.io.uop.lrs3 connect issue_slots[16].uop.lrs2, slots_16.io.uop.lrs2 connect issue_slots[16].uop.lrs1, slots_16.io.uop.lrs1 connect issue_slots[16].uop.ldst, slots_16.io.uop.ldst connect issue_slots[16].uop.ldst_is_rs1, slots_16.io.uop.ldst_is_rs1 connect issue_slots[16].uop.flush_on_commit, slots_16.io.uop.flush_on_commit connect issue_slots[16].uop.is_unique, slots_16.io.uop.is_unique connect issue_slots[16].uop.is_sys_pc2epc, slots_16.io.uop.is_sys_pc2epc connect issue_slots[16].uop.uses_stq, slots_16.io.uop.uses_stq connect issue_slots[16].uop.uses_ldq, slots_16.io.uop.uses_ldq connect issue_slots[16].uop.is_amo, slots_16.io.uop.is_amo connect issue_slots[16].uop.is_fencei, slots_16.io.uop.is_fencei connect issue_slots[16].uop.is_fence, slots_16.io.uop.is_fence connect issue_slots[16].uop.mem_signed, slots_16.io.uop.mem_signed connect issue_slots[16].uop.mem_size, slots_16.io.uop.mem_size connect issue_slots[16].uop.mem_cmd, slots_16.io.uop.mem_cmd connect issue_slots[16].uop.bypassable, slots_16.io.uop.bypassable connect issue_slots[16].uop.exc_cause, slots_16.io.uop.exc_cause connect issue_slots[16].uop.exception, slots_16.io.uop.exception connect issue_slots[16].uop.stale_pdst, slots_16.io.uop.stale_pdst connect issue_slots[16].uop.ppred_busy, slots_16.io.uop.ppred_busy connect issue_slots[16].uop.prs3_busy, slots_16.io.uop.prs3_busy connect issue_slots[16].uop.prs2_busy, slots_16.io.uop.prs2_busy connect issue_slots[16].uop.prs1_busy, slots_16.io.uop.prs1_busy connect issue_slots[16].uop.ppred, slots_16.io.uop.ppred connect issue_slots[16].uop.prs3, slots_16.io.uop.prs3 connect issue_slots[16].uop.prs2, slots_16.io.uop.prs2 connect issue_slots[16].uop.prs1, slots_16.io.uop.prs1 connect issue_slots[16].uop.pdst, slots_16.io.uop.pdst connect issue_slots[16].uop.rxq_idx, slots_16.io.uop.rxq_idx connect issue_slots[16].uop.stq_idx, slots_16.io.uop.stq_idx connect issue_slots[16].uop.ldq_idx, slots_16.io.uop.ldq_idx connect issue_slots[16].uop.rob_idx, slots_16.io.uop.rob_idx connect issue_slots[16].uop.csr_addr, slots_16.io.uop.csr_addr connect issue_slots[16].uop.imm_packed, slots_16.io.uop.imm_packed connect issue_slots[16].uop.taken, slots_16.io.uop.taken connect issue_slots[16].uop.pc_lob, slots_16.io.uop.pc_lob connect issue_slots[16].uop.edge_inst, slots_16.io.uop.edge_inst connect issue_slots[16].uop.ftq_idx, slots_16.io.uop.ftq_idx connect issue_slots[16].uop.br_tag, slots_16.io.uop.br_tag connect issue_slots[16].uop.br_mask, slots_16.io.uop.br_mask connect issue_slots[16].uop.is_sfb, slots_16.io.uop.is_sfb connect issue_slots[16].uop.is_jal, slots_16.io.uop.is_jal connect issue_slots[16].uop.is_jalr, slots_16.io.uop.is_jalr connect issue_slots[16].uop.is_br, slots_16.io.uop.is_br connect issue_slots[16].uop.iw_p2_poisoned, slots_16.io.uop.iw_p2_poisoned connect issue_slots[16].uop.iw_p1_poisoned, slots_16.io.uop.iw_p1_poisoned connect issue_slots[16].uop.iw_state, slots_16.io.uop.iw_state connect issue_slots[16].uop.ctrl.is_std, slots_16.io.uop.ctrl.is_std connect issue_slots[16].uop.ctrl.is_sta, slots_16.io.uop.ctrl.is_sta connect issue_slots[16].uop.ctrl.is_load, slots_16.io.uop.ctrl.is_load connect issue_slots[16].uop.ctrl.csr_cmd, slots_16.io.uop.ctrl.csr_cmd connect issue_slots[16].uop.ctrl.fcn_dw, slots_16.io.uop.ctrl.fcn_dw connect issue_slots[16].uop.ctrl.op_fcn, slots_16.io.uop.ctrl.op_fcn connect issue_slots[16].uop.ctrl.imm_sel, slots_16.io.uop.ctrl.imm_sel connect issue_slots[16].uop.ctrl.op2_sel, slots_16.io.uop.ctrl.op2_sel connect issue_slots[16].uop.ctrl.op1_sel, slots_16.io.uop.ctrl.op1_sel connect issue_slots[16].uop.ctrl.br_type, slots_16.io.uop.ctrl.br_type connect issue_slots[16].uop.fu_code, slots_16.io.uop.fu_code connect issue_slots[16].uop.iq_type, slots_16.io.uop.iq_type connect issue_slots[16].uop.debug_pc, slots_16.io.uop.debug_pc connect issue_slots[16].uop.is_rvc, slots_16.io.uop.is_rvc connect issue_slots[16].uop.debug_inst, slots_16.io.uop.debug_inst connect issue_slots[16].uop.inst, slots_16.io.uop.inst connect issue_slots[16].uop.uopc, slots_16.io.uop.uopc connect issue_slots[16].out_uop.debug_tsrc, slots_16.io.out_uop.debug_tsrc connect issue_slots[16].out_uop.debug_fsrc, slots_16.io.out_uop.debug_fsrc connect issue_slots[16].out_uop.bp_xcpt_if, slots_16.io.out_uop.bp_xcpt_if connect issue_slots[16].out_uop.bp_debug_if, slots_16.io.out_uop.bp_debug_if connect issue_slots[16].out_uop.xcpt_ma_if, slots_16.io.out_uop.xcpt_ma_if connect issue_slots[16].out_uop.xcpt_ae_if, slots_16.io.out_uop.xcpt_ae_if connect issue_slots[16].out_uop.xcpt_pf_if, slots_16.io.out_uop.xcpt_pf_if connect issue_slots[16].out_uop.fp_single, slots_16.io.out_uop.fp_single connect issue_slots[16].out_uop.fp_val, slots_16.io.out_uop.fp_val connect issue_slots[16].out_uop.frs3_en, slots_16.io.out_uop.frs3_en connect issue_slots[16].out_uop.lrs2_rtype, slots_16.io.out_uop.lrs2_rtype connect issue_slots[16].out_uop.lrs1_rtype, slots_16.io.out_uop.lrs1_rtype connect issue_slots[16].out_uop.dst_rtype, slots_16.io.out_uop.dst_rtype connect issue_slots[16].out_uop.ldst_val, slots_16.io.out_uop.ldst_val connect issue_slots[16].out_uop.lrs3, slots_16.io.out_uop.lrs3 connect issue_slots[16].out_uop.lrs2, slots_16.io.out_uop.lrs2 connect issue_slots[16].out_uop.lrs1, slots_16.io.out_uop.lrs1 connect issue_slots[16].out_uop.ldst, slots_16.io.out_uop.ldst connect issue_slots[16].out_uop.ldst_is_rs1, slots_16.io.out_uop.ldst_is_rs1 connect issue_slots[16].out_uop.flush_on_commit, slots_16.io.out_uop.flush_on_commit connect issue_slots[16].out_uop.is_unique, slots_16.io.out_uop.is_unique connect issue_slots[16].out_uop.is_sys_pc2epc, slots_16.io.out_uop.is_sys_pc2epc connect issue_slots[16].out_uop.uses_stq, slots_16.io.out_uop.uses_stq connect issue_slots[16].out_uop.uses_ldq, slots_16.io.out_uop.uses_ldq connect issue_slots[16].out_uop.is_amo, slots_16.io.out_uop.is_amo connect issue_slots[16].out_uop.is_fencei, slots_16.io.out_uop.is_fencei connect issue_slots[16].out_uop.is_fence, slots_16.io.out_uop.is_fence connect issue_slots[16].out_uop.mem_signed, slots_16.io.out_uop.mem_signed connect issue_slots[16].out_uop.mem_size, slots_16.io.out_uop.mem_size connect issue_slots[16].out_uop.mem_cmd, slots_16.io.out_uop.mem_cmd connect issue_slots[16].out_uop.bypassable, slots_16.io.out_uop.bypassable connect issue_slots[16].out_uop.exc_cause, slots_16.io.out_uop.exc_cause connect issue_slots[16].out_uop.exception, slots_16.io.out_uop.exception connect issue_slots[16].out_uop.stale_pdst, slots_16.io.out_uop.stale_pdst connect issue_slots[16].out_uop.ppred_busy, slots_16.io.out_uop.ppred_busy connect issue_slots[16].out_uop.prs3_busy, slots_16.io.out_uop.prs3_busy connect issue_slots[16].out_uop.prs2_busy, slots_16.io.out_uop.prs2_busy connect issue_slots[16].out_uop.prs1_busy, slots_16.io.out_uop.prs1_busy connect issue_slots[16].out_uop.ppred, slots_16.io.out_uop.ppred connect issue_slots[16].out_uop.prs3, slots_16.io.out_uop.prs3 connect issue_slots[16].out_uop.prs2, slots_16.io.out_uop.prs2 connect issue_slots[16].out_uop.prs1, slots_16.io.out_uop.prs1 connect issue_slots[16].out_uop.pdst, slots_16.io.out_uop.pdst connect issue_slots[16].out_uop.rxq_idx, slots_16.io.out_uop.rxq_idx connect issue_slots[16].out_uop.stq_idx, slots_16.io.out_uop.stq_idx connect issue_slots[16].out_uop.ldq_idx, slots_16.io.out_uop.ldq_idx connect issue_slots[16].out_uop.rob_idx, slots_16.io.out_uop.rob_idx connect issue_slots[16].out_uop.csr_addr, slots_16.io.out_uop.csr_addr connect issue_slots[16].out_uop.imm_packed, slots_16.io.out_uop.imm_packed connect issue_slots[16].out_uop.taken, slots_16.io.out_uop.taken connect issue_slots[16].out_uop.pc_lob, slots_16.io.out_uop.pc_lob connect issue_slots[16].out_uop.edge_inst, slots_16.io.out_uop.edge_inst connect issue_slots[16].out_uop.ftq_idx, slots_16.io.out_uop.ftq_idx connect issue_slots[16].out_uop.br_tag, slots_16.io.out_uop.br_tag connect issue_slots[16].out_uop.br_mask, slots_16.io.out_uop.br_mask connect issue_slots[16].out_uop.is_sfb, slots_16.io.out_uop.is_sfb connect issue_slots[16].out_uop.is_jal, slots_16.io.out_uop.is_jal connect issue_slots[16].out_uop.is_jalr, slots_16.io.out_uop.is_jalr connect issue_slots[16].out_uop.is_br, slots_16.io.out_uop.is_br connect issue_slots[16].out_uop.iw_p2_poisoned, slots_16.io.out_uop.iw_p2_poisoned connect issue_slots[16].out_uop.iw_p1_poisoned, slots_16.io.out_uop.iw_p1_poisoned connect issue_slots[16].out_uop.iw_state, slots_16.io.out_uop.iw_state connect issue_slots[16].out_uop.ctrl.is_std, slots_16.io.out_uop.ctrl.is_std connect issue_slots[16].out_uop.ctrl.is_sta, slots_16.io.out_uop.ctrl.is_sta connect issue_slots[16].out_uop.ctrl.is_load, slots_16.io.out_uop.ctrl.is_load connect issue_slots[16].out_uop.ctrl.csr_cmd, slots_16.io.out_uop.ctrl.csr_cmd connect issue_slots[16].out_uop.ctrl.fcn_dw, slots_16.io.out_uop.ctrl.fcn_dw connect issue_slots[16].out_uop.ctrl.op_fcn, slots_16.io.out_uop.ctrl.op_fcn connect issue_slots[16].out_uop.ctrl.imm_sel, slots_16.io.out_uop.ctrl.imm_sel connect issue_slots[16].out_uop.ctrl.op2_sel, slots_16.io.out_uop.ctrl.op2_sel connect issue_slots[16].out_uop.ctrl.op1_sel, slots_16.io.out_uop.ctrl.op1_sel connect issue_slots[16].out_uop.ctrl.br_type, slots_16.io.out_uop.ctrl.br_type connect issue_slots[16].out_uop.fu_code, slots_16.io.out_uop.fu_code connect issue_slots[16].out_uop.iq_type, slots_16.io.out_uop.iq_type connect issue_slots[16].out_uop.debug_pc, slots_16.io.out_uop.debug_pc connect issue_slots[16].out_uop.is_rvc, slots_16.io.out_uop.is_rvc connect issue_slots[16].out_uop.debug_inst, slots_16.io.out_uop.debug_inst connect issue_slots[16].out_uop.inst, slots_16.io.out_uop.inst connect issue_slots[16].out_uop.uopc, slots_16.io.out_uop.uopc connect slots_16.io.in_uop.bits.debug_tsrc, issue_slots[16].in_uop.bits.debug_tsrc connect slots_16.io.in_uop.bits.debug_fsrc, issue_slots[16].in_uop.bits.debug_fsrc connect slots_16.io.in_uop.bits.bp_xcpt_if, issue_slots[16].in_uop.bits.bp_xcpt_if connect slots_16.io.in_uop.bits.bp_debug_if, issue_slots[16].in_uop.bits.bp_debug_if connect slots_16.io.in_uop.bits.xcpt_ma_if, issue_slots[16].in_uop.bits.xcpt_ma_if connect slots_16.io.in_uop.bits.xcpt_ae_if, issue_slots[16].in_uop.bits.xcpt_ae_if connect slots_16.io.in_uop.bits.xcpt_pf_if, issue_slots[16].in_uop.bits.xcpt_pf_if connect slots_16.io.in_uop.bits.fp_single, issue_slots[16].in_uop.bits.fp_single connect slots_16.io.in_uop.bits.fp_val, issue_slots[16].in_uop.bits.fp_val connect slots_16.io.in_uop.bits.frs3_en, issue_slots[16].in_uop.bits.frs3_en connect slots_16.io.in_uop.bits.lrs2_rtype, issue_slots[16].in_uop.bits.lrs2_rtype connect slots_16.io.in_uop.bits.lrs1_rtype, issue_slots[16].in_uop.bits.lrs1_rtype connect slots_16.io.in_uop.bits.dst_rtype, issue_slots[16].in_uop.bits.dst_rtype connect slots_16.io.in_uop.bits.ldst_val, issue_slots[16].in_uop.bits.ldst_val connect slots_16.io.in_uop.bits.lrs3, issue_slots[16].in_uop.bits.lrs3 connect slots_16.io.in_uop.bits.lrs2, issue_slots[16].in_uop.bits.lrs2 connect slots_16.io.in_uop.bits.lrs1, issue_slots[16].in_uop.bits.lrs1 connect slots_16.io.in_uop.bits.ldst, issue_slots[16].in_uop.bits.ldst connect slots_16.io.in_uop.bits.ldst_is_rs1, issue_slots[16].in_uop.bits.ldst_is_rs1 connect slots_16.io.in_uop.bits.flush_on_commit, issue_slots[16].in_uop.bits.flush_on_commit connect slots_16.io.in_uop.bits.is_unique, issue_slots[16].in_uop.bits.is_unique connect slots_16.io.in_uop.bits.is_sys_pc2epc, issue_slots[16].in_uop.bits.is_sys_pc2epc connect slots_16.io.in_uop.bits.uses_stq, issue_slots[16].in_uop.bits.uses_stq connect slots_16.io.in_uop.bits.uses_ldq, issue_slots[16].in_uop.bits.uses_ldq connect slots_16.io.in_uop.bits.is_amo, issue_slots[16].in_uop.bits.is_amo connect slots_16.io.in_uop.bits.is_fencei, issue_slots[16].in_uop.bits.is_fencei connect slots_16.io.in_uop.bits.is_fence, issue_slots[16].in_uop.bits.is_fence connect slots_16.io.in_uop.bits.mem_signed, issue_slots[16].in_uop.bits.mem_signed connect slots_16.io.in_uop.bits.mem_size, issue_slots[16].in_uop.bits.mem_size connect slots_16.io.in_uop.bits.mem_cmd, issue_slots[16].in_uop.bits.mem_cmd connect slots_16.io.in_uop.bits.bypassable, issue_slots[16].in_uop.bits.bypassable connect slots_16.io.in_uop.bits.exc_cause, issue_slots[16].in_uop.bits.exc_cause connect slots_16.io.in_uop.bits.exception, issue_slots[16].in_uop.bits.exception connect slots_16.io.in_uop.bits.stale_pdst, issue_slots[16].in_uop.bits.stale_pdst connect slots_16.io.in_uop.bits.ppred_busy, issue_slots[16].in_uop.bits.ppred_busy connect slots_16.io.in_uop.bits.prs3_busy, issue_slots[16].in_uop.bits.prs3_busy connect slots_16.io.in_uop.bits.prs2_busy, issue_slots[16].in_uop.bits.prs2_busy connect slots_16.io.in_uop.bits.prs1_busy, issue_slots[16].in_uop.bits.prs1_busy connect slots_16.io.in_uop.bits.ppred, issue_slots[16].in_uop.bits.ppred connect slots_16.io.in_uop.bits.prs3, issue_slots[16].in_uop.bits.prs3 connect slots_16.io.in_uop.bits.prs2, issue_slots[16].in_uop.bits.prs2 connect slots_16.io.in_uop.bits.prs1, issue_slots[16].in_uop.bits.prs1 connect slots_16.io.in_uop.bits.pdst, issue_slots[16].in_uop.bits.pdst connect slots_16.io.in_uop.bits.rxq_idx, issue_slots[16].in_uop.bits.rxq_idx connect slots_16.io.in_uop.bits.stq_idx, issue_slots[16].in_uop.bits.stq_idx connect slots_16.io.in_uop.bits.ldq_idx, issue_slots[16].in_uop.bits.ldq_idx connect slots_16.io.in_uop.bits.rob_idx, issue_slots[16].in_uop.bits.rob_idx connect slots_16.io.in_uop.bits.csr_addr, issue_slots[16].in_uop.bits.csr_addr connect slots_16.io.in_uop.bits.imm_packed, issue_slots[16].in_uop.bits.imm_packed connect slots_16.io.in_uop.bits.taken, issue_slots[16].in_uop.bits.taken connect slots_16.io.in_uop.bits.pc_lob, issue_slots[16].in_uop.bits.pc_lob connect slots_16.io.in_uop.bits.edge_inst, issue_slots[16].in_uop.bits.edge_inst connect slots_16.io.in_uop.bits.ftq_idx, issue_slots[16].in_uop.bits.ftq_idx connect slots_16.io.in_uop.bits.br_tag, issue_slots[16].in_uop.bits.br_tag connect slots_16.io.in_uop.bits.br_mask, issue_slots[16].in_uop.bits.br_mask connect slots_16.io.in_uop.bits.is_sfb, issue_slots[16].in_uop.bits.is_sfb connect slots_16.io.in_uop.bits.is_jal, issue_slots[16].in_uop.bits.is_jal connect slots_16.io.in_uop.bits.is_jalr, issue_slots[16].in_uop.bits.is_jalr connect slots_16.io.in_uop.bits.is_br, issue_slots[16].in_uop.bits.is_br connect slots_16.io.in_uop.bits.iw_p2_poisoned, issue_slots[16].in_uop.bits.iw_p2_poisoned connect slots_16.io.in_uop.bits.iw_p1_poisoned, issue_slots[16].in_uop.bits.iw_p1_poisoned connect slots_16.io.in_uop.bits.iw_state, issue_slots[16].in_uop.bits.iw_state connect slots_16.io.in_uop.bits.ctrl.is_std, issue_slots[16].in_uop.bits.ctrl.is_std connect slots_16.io.in_uop.bits.ctrl.is_sta, issue_slots[16].in_uop.bits.ctrl.is_sta connect slots_16.io.in_uop.bits.ctrl.is_load, issue_slots[16].in_uop.bits.ctrl.is_load connect slots_16.io.in_uop.bits.ctrl.csr_cmd, issue_slots[16].in_uop.bits.ctrl.csr_cmd connect slots_16.io.in_uop.bits.ctrl.fcn_dw, issue_slots[16].in_uop.bits.ctrl.fcn_dw connect slots_16.io.in_uop.bits.ctrl.op_fcn, issue_slots[16].in_uop.bits.ctrl.op_fcn connect slots_16.io.in_uop.bits.ctrl.imm_sel, issue_slots[16].in_uop.bits.ctrl.imm_sel connect slots_16.io.in_uop.bits.ctrl.op2_sel, issue_slots[16].in_uop.bits.ctrl.op2_sel connect slots_16.io.in_uop.bits.ctrl.op1_sel, issue_slots[16].in_uop.bits.ctrl.op1_sel connect slots_16.io.in_uop.bits.ctrl.br_type, issue_slots[16].in_uop.bits.ctrl.br_type connect slots_16.io.in_uop.bits.fu_code, issue_slots[16].in_uop.bits.fu_code connect slots_16.io.in_uop.bits.iq_type, issue_slots[16].in_uop.bits.iq_type connect slots_16.io.in_uop.bits.debug_pc, issue_slots[16].in_uop.bits.debug_pc connect slots_16.io.in_uop.bits.is_rvc, issue_slots[16].in_uop.bits.is_rvc connect slots_16.io.in_uop.bits.debug_inst, issue_slots[16].in_uop.bits.debug_inst connect slots_16.io.in_uop.bits.inst, issue_slots[16].in_uop.bits.inst connect slots_16.io.in_uop.bits.uopc, issue_slots[16].in_uop.bits.uopc connect slots_16.io.in_uop.valid, issue_slots[16].in_uop.valid connect slots_16.io.spec_ld_wakeup[0].bits, issue_slots[16].spec_ld_wakeup[0].bits connect slots_16.io.spec_ld_wakeup[0].valid, issue_slots[16].spec_ld_wakeup[0].valid connect slots_16.io.pred_wakeup_port.bits, issue_slots[16].pred_wakeup_port.bits connect slots_16.io.pred_wakeup_port.valid, issue_slots[16].pred_wakeup_port.valid connect slots_16.io.wakeup_ports[0].bits.poisoned, issue_slots[16].wakeup_ports[0].bits.poisoned connect slots_16.io.wakeup_ports[0].bits.pdst, issue_slots[16].wakeup_ports[0].bits.pdst connect slots_16.io.wakeup_ports[0].valid, issue_slots[16].wakeup_ports[0].valid connect slots_16.io.wakeup_ports[1].bits.poisoned, issue_slots[16].wakeup_ports[1].bits.poisoned connect slots_16.io.wakeup_ports[1].bits.pdst, issue_slots[16].wakeup_ports[1].bits.pdst connect slots_16.io.wakeup_ports[1].valid, issue_slots[16].wakeup_ports[1].valid connect slots_16.io.wakeup_ports[2].bits.poisoned, issue_slots[16].wakeup_ports[2].bits.poisoned connect slots_16.io.wakeup_ports[2].bits.pdst, issue_slots[16].wakeup_ports[2].bits.pdst connect slots_16.io.wakeup_ports[2].valid, issue_slots[16].wakeup_ports[2].valid connect slots_16.io.wakeup_ports[3].bits.poisoned, issue_slots[16].wakeup_ports[3].bits.poisoned connect slots_16.io.wakeup_ports[3].bits.pdst, issue_slots[16].wakeup_ports[3].bits.pdst connect slots_16.io.wakeup_ports[3].valid, issue_slots[16].wakeup_ports[3].valid connect slots_16.io.wakeup_ports[4].bits.poisoned, issue_slots[16].wakeup_ports[4].bits.poisoned connect slots_16.io.wakeup_ports[4].bits.pdst, issue_slots[16].wakeup_ports[4].bits.pdst connect slots_16.io.wakeup_ports[4].valid, issue_slots[16].wakeup_ports[4].valid connect slots_16.io.wakeup_ports[5].bits.poisoned, issue_slots[16].wakeup_ports[5].bits.poisoned connect slots_16.io.wakeup_ports[5].bits.pdst, issue_slots[16].wakeup_ports[5].bits.pdst connect slots_16.io.wakeup_ports[5].valid, issue_slots[16].wakeup_ports[5].valid connect slots_16.io.wakeup_ports[6].bits.poisoned, issue_slots[16].wakeup_ports[6].bits.poisoned connect slots_16.io.wakeup_ports[6].bits.pdst, issue_slots[16].wakeup_ports[6].bits.pdst connect slots_16.io.wakeup_ports[6].valid, issue_slots[16].wakeup_ports[6].valid connect slots_16.io.ldspec_miss, issue_slots[16].ldspec_miss connect slots_16.io.clear, issue_slots[16].clear connect slots_16.io.kill, issue_slots[16].kill connect slots_16.io.brupdate.b2.target_offset, issue_slots[16].brupdate.b2.target_offset connect slots_16.io.brupdate.b2.jalr_target, issue_slots[16].brupdate.b2.jalr_target connect slots_16.io.brupdate.b2.pc_sel, issue_slots[16].brupdate.b2.pc_sel connect slots_16.io.brupdate.b2.cfi_type, issue_slots[16].brupdate.b2.cfi_type connect slots_16.io.brupdate.b2.taken, issue_slots[16].brupdate.b2.taken connect slots_16.io.brupdate.b2.mispredict, issue_slots[16].brupdate.b2.mispredict connect slots_16.io.brupdate.b2.valid, issue_slots[16].brupdate.b2.valid connect slots_16.io.brupdate.b2.uop.debug_tsrc, issue_slots[16].brupdate.b2.uop.debug_tsrc connect slots_16.io.brupdate.b2.uop.debug_fsrc, issue_slots[16].brupdate.b2.uop.debug_fsrc connect slots_16.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[16].brupdate.b2.uop.bp_xcpt_if connect slots_16.io.brupdate.b2.uop.bp_debug_if, issue_slots[16].brupdate.b2.uop.bp_debug_if connect slots_16.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[16].brupdate.b2.uop.xcpt_ma_if connect slots_16.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[16].brupdate.b2.uop.xcpt_ae_if connect slots_16.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[16].brupdate.b2.uop.xcpt_pf_if connect slots_16.io.brupdate.b2.uop.fp_single, issue_slots[16].brupdate.b2.uop.fp_single connect slots_16.io.brupdate.b2.uop.fp_val, issue_slots[16].brupdate.b2.uop.fp_val connect slots_16.io.brupdate.b2.uop.frs3_en, issue_slots[16].brupdate.b2.uop.frs3_en connect slots_16.io.brupdate.b2.uop.lrs2_rtype, issue_slots[16].brupdate.b2.uop.lrs2_rtype connect slots_16.io.brupdate.b2.uop.lrs1_rtype, issue_slots[16].brupdate.b2.uop.lrs1_rtype connect slots_16.io.brupdate.b2.uop.dst_rtype, issue_slots[16].brupdate.b2.uop.dst_rtype connect slots_16.io.brupdate.b2.uop.ldst_val, issue_slots[16].brupdate.b2.uop.ldst_val connect slots_16.io.brupdate.b2.uop.lrs3, issue_slots[16].brupdate.b2.uop.lrs3 connect slots_16.io.brupdate.b2.uop.lrs2, issue_slots[16].brupdate.b2.uop.lrs2 connect slots_16.io.brupdate.b2.uop.lrs1, issue_slots[16].brupdate.b2.uop.lrs1 connect slots_16.io.brupdate.b2.uop.ldst, issue_slots[16].brupdate.b2.uop.ldst connect slots_16.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[16].brupdate.b2.uop.ldst_is_rs1 connect slots_16.io.brupdate.b2.uop.flush_on_commit, issue_slots[16].brupdate.b2.uop.flush_on_commit connect slots_16.io.brupdate.b2.uop.is_unique, issue_slots[16].brupdate.b2.uop.is_unique connect slots_16.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[16].brupdate.b2.uop.is_sys_pc2epc connect slots_16.io.brupdate.b2.uop.uses_stq, issue_slots[16].brupdate.b2.uop.uses_stq connect slots_16.io.brupdate.b2.uop.uses_ldq, issue_slots[16].brupdate.b2.uop.uses_ldq connect slots_16.io.brupdate.b2.uop.is_amo, issue_slots[16].brupdate.b2.uop.is_amo connect slots_16.io.brupdate.b2.uop.is_fencei, issue_slots[16].brupdate.b2.uop.is_fencei connect slots_16.io.brupdate.b2.uop.is_fence, issue_slots[16].brupdate.b2.uop.is_fence connect slots_16.io.brupdate.b2.uop.mem_signed, issue_slots[16].brupdate.b2.uop.mem_signed connect slots_16.io.brupdate.b2.uop.mem_size, issue_slots[16].brupdate.b2.uop.mem_size connect slots_16.io.brupdate.b2.uop.mem_cmd, issue_slots[16].brupdate.b2.uop.mem_cmd connect slots_16.io.brupdate.b2.uop.bypassable, issue_slots[16].brupdate.b2.uop.bypassable connect slots_16.io.brupdate.b2.uop.exc_cause, issue_slots[16].brupdate.b2.uop.exc_cause connect slots_16.io.brupdate.b2.uop.exception, issue_slots[16].brupdate.b2.uop.exception connect slots_16.io.brupdate.b2.uop.stale_pdst, issue_slots[16].brupdate.b2.uop.stale_pdst connect slots_16.io.brupdate.b2.uop.ppred_busy, issue_slots[16].brupdate.b2.uop.ppred_busy connect slots_16.io.brupdate.b2.uop.prs3_busy, issue_slots[16].brupdate.b2.uop.prs3_busy connect slots_16.io.brupdate.b2.uop.prs2_busy, issue_slots[16].brupdate.b2.uop.prs2_busy connect slots_16.io.brupdate.b2.uop.prs1_busy, issue_slots[16].brupdate.b2.uop.prs1_busy connect slots_16.io.brupdate.b2.uop.ppred, issue_slots[16].brupdate.b2.uop.ppred connect slots_16.io.brupdate.b2.uop.prs3, issue_slots[16].brupdate.b2.uop.prs3 connect slots_16.io.brupdate.b2.uop.prs2, issue_slots[16].brupdate.b2.uop.prs2 connect slots_16.io.brupdate.b2.uop.prs1, issue_slots[16].brupdate.b2.uop.prs1 connect slots_16.io.brupdate.b2.uop.pdst, issue_slots[16].brupdate.b2.uop.pdst connect slots_16.io.brupdate.b2.uop.rxq_idx, issue_slots[16].brupdate.b2.uop.rxq_idx connect slots_16.io.brupdate.b2.uop.stq_idx, issue_slots[16].brupdate.b2.uop.stq_idx connect slots_16.io.brupdate.b2.uop.ldq_idx, issue_slots[16].brupdate.b2.uop.ldq_idx connect slots_16.io.brupdate.b2.uop.rob_idx, issue_slots[16].brupdate.b2.uop.rob_idx connect slots_16.io.brupdate.b2.uop.csr_addr, issue_slots[16].brupdate.b2.uop.csr_addr connect slots_16.io.brupdate.b2.uop.imm_packed, issue_slots[16].brupdate.b2.uop.imm_packed connect slots_16.io.brupdate.b2.uop.taken, issue_slots[16].brupdate.b2.uop.taken connect slots_16.io.brupdate.b2.uop.pc_lob, issue_slots[16].brupdate.b2.uop.pc_lob connect slots_16.io.brupdate.b2.uop.edge_inst, issue_slots[16].brupdate.b2.uop.edge_inst connect slots_16.io.brupdate.b2.uop.ftq_idx, issue_slots[16].brupdate.b2.uop.ftq_idx connect slots_16.io.brupdate.b2.uop.br_tag, issue_slots[16].brupdate.b2.uop.br_tag connect slots_16.io.brupdate.b2.uop.br_mask, issue_slots[16].brupdate.b2.uop.br_mask connect slots_16.io.brupdate.b2.uop.is_sfb, issue_slots[16].brupdate.b2.uop.is_sfb connect slots_16.io.brupdate.b2.uop.is_jal, issue_slots[16].brupdate.b2.uop.is_jal connect slots_16.io.brupdate.b2.uop.is_jalr, issue_slots[16].brupdate.b2.uop.is_jalr connect slots_16.io.brupdate.b2.uop.is_br, issue_slots[16].brupdate.b2.uop.is_br connect slots_16.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[16].brupdate.b2.uop.iw_p2_poisoned connect slots_16.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[16].brupdate.b2.uop.iw_p1_poisoned connect slots_16.io.brupdate.b2.uop.iw_state, issue_slots[16].brupdate.b2.uop.iw_state connect slots_16.io.brupdate.b2.uop.ctrl.is_std, issue_slots[16].brupdate.b2.uop.ctrl.is_std connect slots_16.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[16].brupdate.b2.uop.ctrl.is_sta connect slots_16.io.brupdate.b2.uop.ctrl.is_load, issue_slots[16].brupdate.b2.uop.ctrl.is_load connect slots_16.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[16].brupdate.b2.uop.ctrl.csr_cmd connect slots_16.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[16].brupdate.b2.uop.ctrl.fcn_dw connect slots_16.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[16].brupdate.b2.uop.ctrl.op_fcn connect slots_16.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[16].brupdate.b2.uop.ctrl.imm_sel connect slots_16.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[16].brupdate.b2.uop.ctrl.op2_sel connect slots_16.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[16].brupdate.b2.uop.ctrl.op1_sel connect slots_16.io.brupdate.b2.uop.ctrl.br_type, issue_slots[16].brupdate.b2.uop.ctrl.br_type connect slots_16.io.brupdate.b2.uop.fu_code, issue_slots[16].brupdate.b2.uop.fu_code connect slots_16.io.brupdate.b2.uop.iq_type, issue_slots[16].brupdate.b2.uop.iq_type connect slots_16.io.brupdate.b2.uop.debug_pc, issue_slots[16].brupdate.b2.uop.debug_pc connect slots_16.io.brupdate.b2.uop.is_rvc, issue_slots[16].brupdate.b2.uop.is_rvc connect slots_16.io.brupdate.b2.uop.debug_inst, issue_slots[16].brupdate.b2.uop.debug_inst connect slots_16.io.brupdate.b2.uop.inst, issue_slots[16].brupdate.b2.uop.inst connect slots_16.io.brupdate.b2.uop.uopc, issue_slots[16].brupdate.b2.uop.uopc connect slots_16.io.brupdate.b1.mispredict_mask, issue_slots[16].brupdate.b1.mispredict_mask connect slots_16.io.brupdate.b1.resolve_mask, issue_slots[16].brupdate.b1.resolve_mask connect slots_16.io.grant, issue_slots[16].grant connect issue_slots[16].request_hp, slots_16.io.request_hp connect issue_slots[16].request, slots_16.io.request connect issue_slots[16].will_be_valid, slots_16.io.will_be_valid connect issue_slots[16].valid, slots_16.io.valid connect issue_slots[17].debug.state, slots_17.io.debug.state connect issue_slots[17].debug.ppred, slots_17.io.debug.ppred connect issue_slots[17].debug.p3, slots_17.io.debug.p3 connect issue_slots[17].debug.p2, slots_17.io.debug.p2 connect issue_slots[17].debug.p1, slots_17.io.debug.p1 connect issue_slots[17].uop.debug_tsrc, slots_17.io.uop.debug_tsrc connect issue_slots[17].uop.debug_fsrc, slots_17.io.uop.debug_fsrc connect issue_slots[17].uop.bp_xcpt_if, slots_17.io.uop.bp_xcpt_if connect issue_slots[17].uop.bp_debug_if, slots_17.io.uop.bp_debug_if connect issue_slots[17].uop.xcpt_ma_if, slots_17.io.uop.xcpt_ma_if connect issue_slots[17].uop.xcpt_ae_if, slots_17.io.uop.xcpt_ae_if connect issue_slots[17].uop.xcpt_pf_if, slots_17.io.uop.xcpt_pf_if connect issue_slots[17].uop.fp_single, slots_17.io.uop.fp_single connect issue_slots[17].uop.fp_val, slots_17.io.uop.fp_val connect issue_slots[17].uop.frs3_en, slots_17.io.uop.frs3_en connect issue_slots[17].uop.lrs2_rtype, slots_17.io.uop.lrs2_rtype connect issue_slots[17].uop.lrs1_rtype, slots_17.io.uop.lrs1_rtype connect issue_slots[17].uop.dst_rtype, slots_17.io.uop.dst_rtype connect issue_slots[17].uop.ldst_val, slots_17.io.uop.ldst_val connect issue_slots[17].uop.lrs3, slots_17.io.uop.lrs3 connect issue_slots[17].uop.lrs2, slots_17.io.uop.lrs2 connect issue_slots[17].uop.lrs1, slots_17.io.uop.lrs1 connect issue_slots[17].uop.ldst, slots_17.io.uop.ldst connect issue_slots[17].uop.ldst_is_rs1, slots_17.io.uop.ldst_is_rs1 connect issue_slots[17].uop.flush_on_commit, slots_17.io.uop.flush_on_commit connect issue_slots[17].uop.is_unique, slots_17.io.uop.is_unique connect issue_slots[17].uop.is_sys_pc2epc, slots_17.io.uop.is_sys_pc2epc connect issue_slots[17].uop.uses_stq, slots_17.io.uop.uses_stq connect issue_slots[17].uop.uses_ldq, slots_17.io.uop.uses_ldq connect issue_slots[17].uop.is_amo, slots_17.io.uop.is_amo connect issue_slots[17].uop.is_fencei, slots_17.io.uop.is_fencei connect issue_slots[17].uop.is_fence, slots_17.io.uop.is_fence connect issue_slots[17].uop.mem_signed, slots_17.io.uop.mem_signed connect issue_slots[17].uop.mem_size, slots_17.io.uop.mem_size connect issue_slots[17].uop.mem_cmd, slots_17.io.uop.mem_cmd connect issue_slots[17].uop.bypassable, slots_17.io.uop.bypassable connect issue_slots[17].uop.exc_cause, slots_17.io.uop.exc_cause connect issue_slots[17].uop.exception, slots_17.io.uop.exception connect issue_slots[17].uop.stale_pdst, slots_17.io.uop.stale_pdst connect issue_slots[17].uop.ppred_busy, slots_17.io.uop.ppred_busy connect issue_slots[17].uop.prs3_busy, slots_17.io.uop.prs3_busy connect issue_slots[17].uop.prs2_busy, slots_17.io.uop.prs2_busy connect issue_slots[17].uop.prs1_busy, slots_17.io.uop.prs1_busy connect issue_slots[17].uop.ppred, slots_17.io.uop.ppred connect issue_slots[17].uop.prs3, slots_17.io.uop.prs3 connect issue_slots[17].uop.prs2, slots_17.io.uop.prs2 connect issue_slots[17].uop.prs1, slots_17.io.uop.prs1 connect issue_slots[17].uop.pdst, slots_17.io.uop.pdst connect issue_slots[17].uop.rxq_idx, slots_17.io.uop.rxq_idx connect issue_slots[17].uop.stq_idx, slots_17.io.uop.stq_idx connect issue_slots[17].uop.ldq_idx, slots_17.io.uop.ldq_idx connect issue_slots[17].uop.rob_idx, slots_17.io.uop.rob_idx connect issue_slots[17].uop.csr_addr, slots_17.io.uop.csr_addr connect issue_slots[17].uop.imm_packed, slots_17.io.uop.imm_packed connect issue_slots[17].uop.taken, slots_17.io.uop.taken connect issue_slots[17].uop.pc_lob, slots_17.io.uop.pc_lob connect issue_slots[17].uop.edge_inst, slots_17.io.uop.edge_inst connect issue_slots[17].uop.ftq_idx, slots_17.io.uop.ftq_idx connect issue_slots[17].uop.br_tag, slots_17.io.uop.br_tag connect issue_slots[17].uop.br_mask, slots_17.io.uop.br_mask connect issue_slots[17].uop.is_sfb, slots_17.io.uop.is_sfb connect issue_slots[17].uop.is_jal, slots_17.io.uop.is_jal connect issue_slots[17].uop.is_jalr, slots_17.io.uop.is_jalr connect issue_slots[17].uop.is_br, slots_17.io.uop.is_br connect issue_slots[17].uop.iw_p2_poisoned, slots_17.io.uop.iw_p2_poisoned connect issue_slots[17].uop.iw_p1_poisoned, slots_17.io.uop.iw_p1_poisoned connect issue_slots[17].uop.iw_state, slots_17.io.uop.iw_state connect issue_slots[17].uop.ctrl.is_std, slots_17.io.uop.ctrl.is_std connect issue_slots[17].uop.ctrl.is_sta, slots_17.io.uop.ctrl.is_sta connect issue_slots[17].uop.ctrl.is_load, slots_17.io.uop.ctrl.is_load connect issue_slots[17].uop.ctrl.csr_cmd, slots_17.io.uop.ctrl.csr_cmd connect issue_slots[17].uop.ctrl.fcn_dw, slots_17.io.uop.ctrl.fcn_dw connect issue_slots[17].uop.ctrl.op_fcn, slots_17.io.uop.ctrl.op_fcn connect issue_slots[17].uop.ctrl.imm_sel, slots_17.io.uop.ctrl.imm_sel connect issue_slots[17].uop.ctrl.op2_sel, slots_17.io.uop.ctrl.op2_sel connect issue_slots[17].uop.ctrl.op1_sel, slots_17.io.uop.ctrl.op1_sel connect issue_slots[17].uop.ctrl.br_type, slots_17.io.uop.ctrl.br_type connect issue_slots[17].uop.fu_code, slots_17.io.uop.fu_code connect issue_slots[17].uop.iq_type, slots_17.io.uop.iq_type connect issue_slots[17].uop.debug_pc, slots_17.io.uop.debug_pc connect issue_slots[17].uop.is_rvc, slots_17.io.uop.is_rvc connect issue_slots[17].uop.debug_inst, slots_17.io.uop.debug_inst connect issue_slots[17].uop.inst, slots_17.io.uop.inst connect issue_slots[17].uop.uopc, slots_17.io.uop.uopc connect issue_slots[17].out_uop.debug_tsrc, slots_17.io.out_uop.debug_tsrc connect issue_slots[17].out_uop.debug_fsrc, slots_17.io.out_uop.debug_fsrc connect issue_slots[17].out_uop.bp_xcpt_if, slots_17.io.out_uop.bp_xcpt_if connect issue_slots[17].out_uop.bp_debug_if, slots_17.io.out_uop.bp_debug_if connect issue_slots[17].out_uop.xcpt_ma_if, slots_17.io.out_uop.xcpt_ma_if connect issue_slots[17].out_uop.xcpt_ae_if, slots_17.io.out_uop.xcpt_ae_if connect issue_slots[17].out_uop.xcpt_pf_if, slots_17.io.out_uop.xcpt_pf_if connect issue_slots[17].out_uop.fp_single, slots_17.io.out_uop.fp_single connect issue_slots[17].out_uop.fp_val, slots_17.io.out_uop.fp_val connect issue_slots[17].out_uop.frs3_en, slots_17.io.out_uop.frs3_en connect issue_slots[17].out_uop.lrs2_rtype, slots_17.io.out_uop.lrs2_rtype connect issue_slots[17].out_uop.lrs1_rtype, slots_17.io.out_uop.lrs1_rtype connect issue_slots[17].out_uop.dst_rtype, slots_17.io.out_uop.dst_rtype connect issue_slots[17].out_uop.ldst_val, slots_17.io.out_uop.ldst_val connect issue_slots[17].out_uop.lrs3, slots_17.io.out_uop.lrs3 connect issue_slots[17].out_uop.lrs2, slots_17.io.out_uop.lrs2 connect issue_slots[17].out_uop.lrs1, slots_17.io.out_uop.lrs1 connect issue_slots[17].out_uop.ldst, slots_17.io.out_uop.ldst connect issue_slots[17].out_uop.ldst_is_rs1, slots_17.io.out_uop.ldst_is_rs1 connect issue_slots[17].out_uop.flush_on_commit, slots_17.io.out_uop.flush_on_commit connect issue_slots[17].out_uop.is_unique, slots_17.io.out_uop.is_unique connect issue_slots[17].out_uop.is_sys_pc2epc, slots_17.io.out_uop.is_sys_pc2epc connect issue_slots[17].out_uop.uses_stq, slots_17.io.out_uop.uses_stq connect issue_slots[17].out_uop.uses_ldq, slots_17.io.out_uop.uses_ldq connect issue_slots[17].out_uop.is_amo, slots_17.io.out_uop.is_amo connect issue_slots[17].out_uop.is_fencei, slots_17.io.out_uop.is_fencei connect issue_slots[17].out_uop.is_fence, slots_17.io.out_uop.is_fence connect issue_slots[17].out_uop.mem_signed, slots_17.io.out_uop.mem_signed connect issue_slots[17].out_uop.mem_size, slots_17.io.out_uop.mem_size connect issue_slots[17].out_uop.mem_cmd, slots_17.io.out_uop.mem_cmd connect issue_slots[17].out_uop.bypassable, slots_17.io.out_uop.bypassable connect issue_slots[17].out_uop.exc_cause, slots_17.io.out_uop.exc_cause connect issue_slots[17].out_uop.exception, slots_17.io.out_uop.exception connect issue_slots[17].out_uop.stale_pdst, slots_17.io.out_uop.stale_pdst connect issue_slots[17].out_uop.ppred_busy, slots_17.io.out_uop.ppred_busy connect issue_slots[17].out_uop.prs3_busy, slots_17.io.out_uop.prs3_busy connect issue_slots[17].out_uop.prs2_busy, slots_17.io.out_uop.prs2_busy connect issue_slots[17].out_uop.prs1_busy, slots_17.io.out_uop.prs1_busy connect issue_slots[17].out_uop.ppred, slots_17.io.out_uop.ppred connect issue_slots[17].out_uop.prs3, slots_17.io.out_uop.prs3 connect issue_slots[17].out_uop.prs2, slots_17.io.out_uop.prs2 connect issue_slots[17].out_uop.prs1, slots_17.io.out_uop.prs1 connect issue_slots[17].out_uop.pdst, slots_17.io.out_uop.pdst connect issue_slots[17].out_uop.rxq_idx, slots_17.io.out_uop.rxq_idx connect issue_slots[17].out_uop.stq_idx, slots_17.io.out_uop.stq_idx connect issue_slots[17].out_uop.ldq_idx, slots_17.io.out_uop.ldq_idx connect issue_slots[17].out_uop.rob_idx, slots_17.io.out_uop.rob_idx connect issue_slots[17].out_uop.csr_addr, slots_17.io.out_uop.csr_addr connect issue_slots[17].out_uop.imm_packed, slots_17.io.out_uop.imm_packed connect issue_slots[17].out_uop.taken, slots_17.io.out_uop.taken connect issue_slots[17].out_uop.pc_lob, slots_17.io.out_uop.pc_lob connect issue_slots[17].out_uop.edge_inst, slots_17.io.out_uop.edge_inst connect issue_slots[17].out_uop.ftq_idx, slots_17.io.out_uop.ftq_idx connect issue_slots[17].out_uop.br_tag, slots_17.io.out_uop.br_tag connect issue_slots[17].out_uop.br_mask, slots_17.io.out_uop.br_mask connect issue_slots[17].out_uop.is_sfb, slots_17.io.out_uop.is_sfb connect issue_slots[17].out_uop.is_jal, slots_17.io.out_uop.is_jal connect issue_slots[17].out_uop.is_jalr, slots_17.io.out_uop.is_jalr connect issue_slots[17].out_uop.is_br, slots_17.io.out_uop.is_br connect issue_slots[17].out_uop.iw_p2_poisoned, slots_17.io.out_uop.iw_p2_poisoned connect issue_slots[17].out_uop.iw_p1_poisoned, slots_17.io.out_uop.iw_p1_poisoned connect issue_slots[17].out_uop.iw_state, slots_17.io.out_uop.iw_state connect issue_slots[17].out_uop.ctrl.is_std, slots_17.io.out_uop.ctrl.is_std connect issue_slots[17].out_uop.ctrl.is_sta, slots_17.io.out_uop.ctrl.is_sta connect issue_slots[17].out_uop.ctrl.is_load, slots_17.io.out_uop.ctrl.is_load connect issue_slots[17].out_uop.ctrl.csr_cmd, slots_17.io.out_uop.ctrl.csr_cmd connect issue_slots[17].out_uop.ctrl.fcn_dw, slots_17.io.out_uop.ctrl.fcn_dw connect issue_slots[17].out_uop.ctrl.op_fcn, slots_17.io.out_uop.ctrl.op_fcn connect issue_slots[17].out_uop.ctrl.imm_sel, slots_17.io.out_uop.ctrl.imm_sel connect issue_slots[17].out_uop.ctrl.op2_sel, slots_17.io.out_uop.ctrl.op2_sel connect issue_slots[17].out_uop.ctrl.op1_sel, slots_17.io.out_uop.ctrl.op1_sel connect issue_slots[17].out_uop.ctrl.br_type, slots_17.io.out_uop.ctrl.br_type connect issue_slots[17].out_uop.fu_code, slots_17.io.out_uop.fu_code connect issue_slots[17].out_uop.iq_type, slots_17.io.out_uop.iq_type connect issue_slots[17].out_uop.debug_pc, slots_17.io.out_uop.debug_pc connect issue_slots[17].out_uop.is_rvc, slots_17.io.out_uop.is_rvc connect issue_slots[17].out_uop.debug_inst, slots_17.io.out_uop.debug_inst connect issue_slots[17].out_uop.inst, slots_17.io.out_uop.inst connect issue_slots[17].out_uop.uopc, slots_17.io.out_uop.uopc connect slots_17.io.in_uop.bits.debug_tsrc, issue_slots[17].in_uop.bits.debug_tsrc connect slots_17.io.in_uop.bits.debug_fsrc, issue_slots[17].in_uop.bits.debug_fsrc connect slots_17.io.in_uop.bits.bp_xcpt_if, issue_slots[17].in_uop.bits.bp_xcpt_if connect slots_17.io.in_uop.bits.bp_debug_if, issue_slots[17].in_uop.bits.bp_debug_if connect slots_17.io.in_uop.bits.xcpt_ma_if, issue_slots[17].in_uop.bits.xcpt_ma_if connect slots_17.io.in_uop.bits.xcpt_ae_if, issue_slots[17].in_uop.bits.xcpt_ae_if connect slots_17.io.in_uop.bits.xcpt_pf_if, issue_slots[17].in_uop.bits.xcpt_pf_if connect slots_17.io.in_uop.bits.fp_single, issue_slots[17].in_uop.bits.fp_single connect slots_17.io.in_uop.bits.fp_val, issue_slots[17].in_uop.bits.fp_val connect slots_17.io.in_uop.bits.frs3_en, issue_slots[17].in_uop.bits.frs3_en connect slots_17.io.in_uop.bits.lrs2_rtype, issue_slots[17].in_uop.bits.lrs2_rtype connect slots_17.io.in_uop.bits.lrs1_rtype, issue_slots[17].in_uop.bits.lrs1_rtype connect slots_17.io.in_uop.bits.dst_rtype, issue_slots[17].in_uop.bits.dst_rtype connect slots_17.io.in_uop.bits.ldst_val, issue_slots[17].in_uop.bits.ldst_val connect slots_17.io.in_uop.bits.lrs3, issue_slots[17].in_uop.bits.lrs3 connect slots_17.io.in_uop.bits.lrs2, issue_slots[17].in_uop.bits.lrs2 connect slots_17.io.in_uop.bits.lrs1, issue_slots[17].in_uop.bits.lrs1 connect slots_17.io.in_uop.bits.ldst, issue_slots[17].in_uop.bits.ldst connect slots_17.io.in_uop.bits.ldst_is_rs1, issue_slots[17].in_uop.bits.ldst_is_rs1 connect slots_17.io.in_uop.bits.flush_on_commit, issue_slots[17].in_uop.bits.flush_on_commit connect slots_17.io.in_uop.bits.is_unique, issue_slots[17].in_uop.bits.is_unique connect slots_17.io.in_uop.bits.is_sys_pc2epc, issue_slots[17].in_uop.bits.is_sys_pc2epc connect slots_17.io.in_uop.bits.uses_stq, issue_slots[17].in_uop.bits.uses_stq connect slots_17.io.in_uop.bits.uses_ldq, issue_slots[17].in_uop.bits.uses_ldq connect slots_17.io.in_uop.bits.is_amo, issue_slots[17].in_uop.bits.is_amo connect slots_17.io.in_uop.bits.is_fencei, issue_slots[17].in_uop.bits.is_fencei connect slots_17.io.in_uop.bits.is_fence, issue_slots[17].in_uop.bits.is_fence connect slots_17.io.in_uop.bits.mem_signed, issue_slots[17].in_uop.bits.mem_signed connect slots_17.io.in_uop.bits.mem_size, issue_slots[17].in_uop.bits.mem_size connect slots_17.io.in_uop.bits.mem_cmd, issue_slots[17].in_uop.bits.mem_cmd connect slots_17.io.in_uop.bits.bypassable, issue_slots[17].in_uop.bits.bypassable connect slots_17.io.in_uop.bits.exc_cause, issue_slots[17].in_uop.bits.exc_cause connect slots_17.io.in_uop.bits.exception, issue_slots[17].in_uop.bits.exception connect slots_17.io.in_uop.bits.stale_pdst, issue_slots[17].in_uop.bits.stale_pdst connect slots_17.io.in_uop.bits.ppred_busy, issue_slots[17].in_uop.bits.ppred_busy connect slots_17.io.in_uop.bits.prs3_busy, issue_slots[17].in_uop.bits.prs3_busy connect slots_17.io.in_uop.bits.prs2_busy, issue_slots[17].in_uop.bits.prs2_busy connect slots_17.io.in_uop.bits.prs1_busy, issue_slots[17].in_uop.bits.prs1_busy connect slots_17.io.in_uop.bits.ppred, issue_slots[17].in_uop.bits.ppred connect slots_17.io.in_uop.bits.prs3, issue_slots[17].in_uop.bits.prs3 connect slots_17.io.in_uop.bits.prs2, issue_slots[17].in_uop.bits.prs2 connect slots_17.io.in_uop.bits.prs1, issue_slots[17].in_uop.bits.prs1 connect slots_17.io.in_uop.bits.pdst, issue_slots[17].in_uop.bits.pdst connect slots_17.io.in_uop.bits.rxq_idx, issue_slots[17].in_uop.bits.rxq_idx connect slots_17.io.in_uop.bits.stq_idx, issue_slots[17].in_uop.bits.stq_idx connect slots_17.io.in_uop.bits.ldq_idx, issue_slots[17].in_uop.bits.ldq_idx connect slots_17.io.in_uop.bits.rob_idx, issue_slots[17].in_uop.bits.rob_idx connect slots_17.io.in_uop.bits.csr_addr, issue_slots[17].in_uop.bits.csr_addr connect slots_17.io.in_uop.bits.imm_packed, issue_slots[17].in_uop.bits.imm_packed connect slots_17.io.in_uop.bits.taken, issue_slots[17].in_uop.bits.taken connect slots_17.io.in_uop.bits.pc_lob, issue_slots[17].in_uop.bits.pc_lob connect slots_17.io.in_uop.bits.edge_inst, issue_slots[17].in_uop.bits.edge_inst connect slots_17.io.in_uop.bits.ftq_idx, issue_slots[17].in_uop.bits.ftq_idx connect slots_17.io.in_uop.bits.br_tag, issue_slots[17].in_uop.bits.br_tag connect slots_17.io.in_uop.bits.br_mask, issue_slots[17].in_uop.bits.br_mask connect slots_17.io.in_uop.bits.is_sfb, issue_slots[17].in_uop.bits.is_sfb connect slots_17.io.in_uop.bits.is_jal, issue_slots[17].in_uop.bits.is_jal connect slots_17.io.in_uop.bits.is_jalr, issue_slots[17].in_uop.bits.is_jalr connect slots_17.io.in_uop.bits.is_br, issue_slots[17].in_uop.bits.is_br connect slots_17.io.in_uop.bits.iw_p2_poisoned, issue_slots[17].in_uop.bits.iw_p2_poisoned connect slots_17.io.in_uop.bits.iw_p1_poisoned, issue_slots[17].in_uop.bits.iw_p1_poisoned connect slots_17.io.in_uop.bits.iw_state, issue_slots[17].in_uop.bits.iw_state connect slots_17.io.in_uop.bits.ctrl.is_std, issue_slots[17].in_uop.bits.ctrl.is_std connect slots_17.io.in_uop.bits.ctrl.is_sta, issue_slots[17].in_uop.bits.ctrl.is_sta connect slots_17.io.in_uop.bits.ctrl.is_load, issue_slots[17].in_uop.bits.ctrl.is_load connect slots_17.io.in_uop.bits.ctrl.csr_cmd, issue_slots[17].in_uop.bits.ctrl.csr_cmd connect slots_17.io.in_uop.bits.ctrl.fcn_dw, issue_slots[17].in_uop.bits.ctrl.fcn_dw connect slots_17.io.in_uop.bits.ctrl.op_fcn, issue_slots[17].in_uop.bits.ctrl.op_fcn connect slots_17.io.in_uop.bits.ctrl.imm_sel, issue_slots[17].in_uop.bits.ctrl.imm_sel connect slots_17.io.in_uop.bits.ctrl.op2_sel, issue_slots[17].in_uop.bits.ctrl.op2_sel connect slots_17.io.in_uop.bits.ctrl.op1_sel, issue_slots[17].in_uop.bits.ctrl.op1_sel connect slots_17.io.in_uop.bits.ctrl.br_type, issue_slots[17].in_uop.bits.ctrl.br_type connect slots_17.io.in_uop.bits.fu_code, issue_slots[17].in_uop.bits.fu_code connect slots_17.io.in_uop.bits.iq_type, issue_slots[17].in_uop.bits.iq_type connect slots_17.io.in_uop.bits.debug_pc, issue_slots[17].in_uop.bits.debug_pc connect slots_17.io.in_uop.bits.is_rvc, issue_slots[17].in_uop.bits.is_rvc connect slots_17.io.in_uop.bits.debug_inst, issue_slots[17].in_uop.bits.debug_inst connect slots_17.io.in_uop.bits.inst, issue_slots[17].in_uop.bits.inst connect slots_17.io.in_uop.bits.uopc, issue_slots[17].in_uop.bits.uopc connect slots_17.io.in_uop.valid, issue_slots[17].in_uop.valid connect slots_17.io.spec_ld_wakeup[0].bits, issue_slots[17].spec_ld_wakeup[0].bits connect slots_17.io.spec_ld_wakeup[0].valid, issue_slots[17].spec_ld_wakeup[0].valid connect slots_17.io.pred_wakeup_port.bits, issue_slots[17].pred_wakeup_port.bits connect slots_17.io.pred_wakeup_port.valid, issue_slots[17].pred_wakeup_port.valid connect slots_17.io.wakeup_ports[0].bits.poisoned, issue_slots[17].wakeup_ports[0].bits.poisoned connect slots_17.io.wakeup_ports[0].bits.pdst, issue_slots[17].wakeup_ports[0].bits.pdst connect slots_17.io.wakeup_ports[0].valid, issue_slots[17].wakeup_ports[0].valid connect slots_17.io.wakeup_ports[1].bits.poisoned, issue_slots[17].wakeup_ports[1].bits.poisoned connect slots_17.io.wakeup_ports[1].bits.pdst, issue_slots[17].wakeup_ports[1].bits.pdst connect slots_17.io.wakeup_ports[1].valid, issue_slots[17].wakeup_ports[1].valid connect slots_17.io.wakeup_ports[2].bits.poisoned, issue_slots[17].wakeup_ports[2].bits.poisoned connect slots_17.io.wakeup_ports[2].bits.pdst, issue_slots[17].wakeup_ports[2].bits.pdst connect slots_17.io.wakeup_ports[2].valid, issue_slots[17].wakeup_ports[2].valid connect slots_17.io.wakeup_ports[3].bits.poisoned, issue_slots[17].wakeup_ports[3].bits.poisoned connect slots_17.io.wakeup_ports[3].bits.pdst, issue_slots[17].wakeup_ports[3].bits.pdst connect slots_17.io.wakeup_ports[3].valid, issue_slots[17].wakeup_ports[3].valid connect slots_17.io.wakeup_ports[4].bits.poisoned, issue_slots[17].wakeup_ports[4].bits.poisoned connect slots_17.io.wakeup_ports[4].bits.pdst, issue_slots[17].wakeup_ports[4].bits.pdst connect slots_17.io.wakeup_ports[4].valid, issue_slots[17].wakeup_ports[4].valid connect slots_17.io.wakeup_ports[5].bits.poisoned, issue_slots[17].wakeup_ports[5].bits.poisoned connect slots_17.io.wakeup_ports[5].bits.pdst, issue_slots[17].wakeup_ports[5].bits.pdst connect slots_17.io.wakeup_ports[5].valid, issue_slots[17].wakeup_ports[5].valid connect slots_17.io.wakeup_ports[6].bits.poisoned, issue_slots[17].wakeup_ports[6].bits.poisoned connect slots_17.io.wakeup_ports[6].bits.pdst, issue_slots[17].wakeup_ports[6].bits.pdst connect slots_17.io.wakeup_ports[6].valid, issue_slots[17].wakeup_ports[6].valid connect slots_17.io.ldspec_miss, issue_slots[17].ldspec_miss connect slots_17.io.clear, issue_slots[17].clear connect slots_17.io.kill, issue_slots[17].kill connect slots_17.io.brupdate.b2.target_offset, issue_slots[17].brupdate.b2.target_offset connect slots_17.io.brupdate.b2.jalr_target, issue_slots[17].brupdate.b2.jalr_target connect slots_17.io.brupdate.b2.pc_sel, issue_slots[17].brupdate.b2.pc_sel connect slots_17.io.brupdate.b2.cfi_type, issue_slots[17].brupdate.b2.cfi_type connect slots_17.io.brupdate.b2.taken, issue_slots[17].brupdate.b2.taken connect slots_17.io.brupdate.b2.mispredict, issue_slots[17].brupdate.b2.mispredict connect slots_17.io.brupdate.b2.valid, issue_slots[17].brupdate.b2.valid connect slots_17.io.brupdate.b2.uop.debug_tsrc, issue_slots[17].brupdate.b2.uop.debug_tsrc connect slots_17.io.brupdate.b2.uop.debug_fsrc, issue_slots[17].brupdate.b2.uop.debug_fsrc connect slots_17.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[17].brupdate.b2.uop.bp_xcpt_if connect slots_17.io.brupdate.b2.uop.bp_debug_if, issue_slots[17].brupdate.b2.uop.bp_debug_if connect slots_17.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[17].brupdate.b2.uop.xcpt_ma_if connect slots_17.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[17].brupdate.b2.uop.xcpt_ae_if connect slots_17.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[17].brupdate.b2.uop.xcpt_pf_if connect slots_17.io.brupdate.b2.uop.fp_single, issue_slots[17].brupdate.b2.uop.fp_single connect slots_17.io.brupdate.b2.uop.fp_val, issue_slots[17].brupdate.b2.uop.fp_val connect slots_17.io.brupdate.b2.uop.frs3_en, issue_slots[17].brupdate.b2.uop.frs3_en connect slots_17.io.brupdate.b2.uop.lrs2_rtype, issue_slots[17].brupdate.b2.uop.lrs2_rtype connect slots_17.io.brupdate.b2.uop.lrs1_rtype, issue_slots[17].brupdate.b2.uop.lrs1_rtype connect slots_17.io.brupdate.b2.uop.dst_rtype, issue_slots[17].brupdate.b2.uop.dst_rtype connect slots_17.io.brupdate.b2.uop.ldst_val, issue_slots[17].brupdate.b2.uop.ldst_val connect slots_17.io.brupdate.b2.uop.lrs3, issue_slots[17].brupdate.b2.uop.lrs3 connect slots_17.io.brupdate.b2.uop.lrs2, issue_slots[17].brupdate.b2.uop.lrs2 connect slots_17.io.brupdate.b2.uop.lrs1, issue_slots[17].brupdate.b2.uop.lrs1 connect slots_17.io.brupdate.b2.uop.ldst, issue_slots[17].brupdate.b2.uop.ldst connect slots_17.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[17].brupdate.b2.uop.ldst_is_rs1 connect slots_17.io.brupdate.b2.uop.flush_on_commit, issue_slots[17].brupdate.b2.uop.flush_on_commit connect slots_17.io.brupdate.b2.uop.is_unique, issue_slots[17].brupdate.b2.uop.is_unique connect slots_17.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[17].brupdate.b2.uop.is_sys_pc2epc connect slots_17.io.brupdate.b2.uop.uses_stq, issue_slots[17].brupdate.b2.uop.uses_stq connect slots_17.io.brupdate.b2.uop.uses_ldq, issue_slots[17].brupdate.b2.uop.uses_ldq connect slots_17.io.brupdate.b2.uop.is_amo, issue_slots[17].brupdate.b2.uop.is_amo connect slots_17.io.brupdate.b2.uop.is_fencei, issue_slots[17].brupdate.b2.uop.is_fencei connect slots_17.io.brupdate.b2.uop.is_fence, issue_slots[17].brupdate.b2.uop.is_fence connect slots_17.io.brupdate.b2.uop.mem_signed, issue_slots[17].brupdate.b2.uop.mem_signed connect slots_17.io.brupdate.b2.uop.mem_size, issue_slots[17].brupdate.b2.uop.mem_size connect slots_17.io.brupdate.b2.uop.mem_cmd, issue_slots[17].brupdate.b2.uop.mem_cmd connect slots_17.io.brupdate.b2.uop.bypassable, issue_slots[17].brupdate.b2.uop.bypassable connect slots_17.io.brupdate.b2.uop.exc_cause, issue_slots[17].brupdate.b2.uop.exc_cause connect slots_17.io.brupdate.b2.uop.exception, issue_slots[17].brupdate.b2.uop.exception connect slots_17.io.brupdate.b2.uop.stale_pdst, issue_slots[17].brupdate.b2.uop.stale_pdst connect slots_17.io.brupdate.b2.uop.ppred_busy, issue_slots[17].brupdate.b2.uop.ppred_busy connect slots_17.io.brupdate.b2.uop.prs3_busy, issue_slots[17].brupdate.b2.uop.prs3_busy connect slots_17.io.brupdate.b2.uop.prs2_busy, issue_slots[17].brupdate.b2.uop.prs2_busy connect slots_17.io.brupdate.b2.uop.prs1_busy, issue_slots[17].brupdate.b2.uop.prs1_busy connect slots_17.io.brupdate.b2.uop.ppred, issue_slots[17].brupdate.b2.uop.ppred connect slots_17.io.brupdate.b2.uop.prs3, issue_slots[17].brupdate.b2.uop.prs3 connect slots_17.io.brupdate.b2.uop.prs2, issue_slots[17].brupdate.b2.uop.prs2 connect slots_17.io.brupdate.b2.uop.prs1, issue_slots[17].brupdate.b2.uop.prs1 connect slots_17.io.brupdate.b2.uop.pdst, issue_slots[17].brupdate.b2.uop.pdst connect slots_17.io.brupdate.b2.uop.rxq_idx, issue_slots[17].brupdate.b2.uop.rxq_idx connect slots_17.io.brupdate.b2.uop.stq_idx, issue_slots[17].brupdate.b2.uop.stq_idx connect slots_17.io.brupdate.b2.uop.ldq_idx, issue_slots[17].brupdate.b2.uop.ldq_idx connect slots_17.io.brupdate.b2.uop.rob_idx, issue_slots[17].brupdate.b2.uop.rob_idx connect slots_17.io.brupdate.b2.uop.csr_addr, issue_slots[17].brupdate.b2.uop.csr_addr connect slots_17.io.brupdate.b2.uop.imm_packed, issue_slots[17].brupdate.b2.uop.imm_packed connect slots_17.io.brupdate.b2.uop.taken, issue_slots[17].brupdate.b2.uop.taken connect slots_17.io.brupdate.b2.uop.pc_lob, issue_slots[17].brupdate.b2.uop.pc_lob connect slots_17.io.brupdate.b2.uop.edge_inst, issue_slots[17].brupdate.b2.uop.edge_inst connect slots_17.io.brupdate.b2.uop.ftq_idx, issue_slots[17].brupdate.b2.uop.ftq_idx connect slots_17.io.brupdate.b2.uop.br_tag, issue_slots[17].brupdate.b2.uop.br_tag connect slots_17.io.brupdate.b2.uop.br_mask, issue_slots[17].brupdate.b2.uop.br_mask connect slots_17.io.brupdate.b2.uop.is_sfb, issue_slots[17].brupdate.b2.uop.is_sfb connect slots_17.io.brupdate.b2.uop.is_jal, issue_slots[17].brupdate.b2.uop.is_jal connect slots_17.io.brupdate.b2.uop.is_jalr, issue_slots[17].brupdate.b2.uop.is_jalr connect slots_17.io.brupdate.b2.uop.is_br, issue_slots[17].brupdate.b2.uop.is_br connect slots_17.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[17].brupdate.b2.uop.iw_p2_poisoned connect slots_17.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[17].brupdate.b2.uop.iw_p1_poisoned connect slots_17.io.brupdate.b2.uop.iw_state, issue_slots[17].brupdate.b2.uop.iw_state connect slots_17.io.brupdate.b2.uop.ctrl.is_std, issue_slots[17].brupdate.b2.uop.ctrl.is_std connect slots_17.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[17].brupdate.b2.uop.ctrl.is_sta connect slots_17.io.brupdate.b2.uop.ctrl.is_load, issue_slots[17].brupdate.b2.uop.ctrl.is_load connect slots_17.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[17].brupdate.b2.uop.ctrl.csr_cmd connect slots_17.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[17].brupdate.b2.uop.ctrl.fcn_dw connect slots_17.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[17].brupdate.b2.uop.ctrl.op_fcn connect slots_17.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[17].brupdate.b2.uop.ctrl.imm_sel connect slots_17.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[17].brupdate.b2.uop.ctrl.op2_sel connect slots_17.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[17].brupdate.b2.uop.ctrl.op1_sel connect slots_17.io.brupdate.b2.uop.ctrl.br_type, issue_slots[17].brupdate.b2.uop.ctrl.br_type connect slots_17.io.brupdate.b2.uop.fu_code, issue_slots[17].brupdate.b2.uop.fu_code connect slots_17.io.brupdate.b2.uop.iq_type, issue_slots[17].brupdate.b2.uop.iq_type connect slots_17.io.brupdate.b2.uop.debug_pc, issue_slots[17].brupdate.b2.uop.debug_pc connect slots_17.io.brupdate.b2.uop.is_rvc, issue_slots[17].brupdate.b2.uop.is_rvc connect slots_17.io.brupdate.b2.uop.debug_inst, issue_slots[17].brupdate.b2.uop.debug_inst connect slots_17.io.brupdate.b2.uop.inst, issue_slots[17].brupdate.b2.uop.inst connect slots_17.io.brupdate.b2.uop.uopc, issue_slots[17].brupdate.b2.uop.uopc connect slots_17.io.brupdate.b1.mispredict_mask, issue_slots[17].brupdate.b1.mispredict_mask connect slots_17.io.brupdate.b1.resolve_mask, issue_slots[17].brupdate.b1.resolve_mask connect slots_17.io.grant, issue_slots[17].grant connect issue_slots[17].request_hp, slots_17.io.request_hp connect issue_slots[17].request, slots_17.io.request connect issue_slots[17].will_be_valid, slots_17.io.will_be_valid connect issue_slots[17].valid, slots_17.io.valid connect issue_slots[18].debug.state, slots_18.io.debug.state connect issue_slots[18].debug.ppred, slots_18.io.debug.ppred connect issue_slots[18].debug.p3, slots_18.io.debug.p3 connect issue_slots[18].debug.p2, slots_18.io.debug.p2 connect issue_slots[18].debug.p1, slots_18.io.debug.p1 connect issue_slots[18].uop.debug_tsrc, slots_18.io.uop.debug_tsrc connect issue_slots[18].uop.debug_fsrc, slots_18.io.uop.debug_fsrc connect issue_slots[18].uop.bp_xcpt_if, slots_18.io.uop.bp_xcpt_if connect issue_slots[18].uop.bp_debug_if, slots_18.io.uop.bp_debug_if connect issue_slots[18].uop.xcpt_ma_if, slots_18.io.uop.xcpt_ma_if connect issue_slots[18].uop.xcpt_ae_if, slots_18.io.uop.xcpt_ae_if connect issue_slots[18].uop.xcpt_pf_if, slots_18.io.uop.xcpt_pf_if connect issue_slots[18].uop.fp_single, slots_18.io.uop.fp_single connect issue_slots[18].uop.fp_val, slots_18.io.uop.fp_val connect issue_slots[18].uop.frs3_en, slots_18.io.uop.frs3_en connect issue_slots[18].uop.lrs2_rtype, slots_18.io.uop.lrs2_rtype connect issue_slots[18].uop.lrs1_rtype, slots_18.io.uop.lrs1_rtype connect issue_slots[18].uop.dst_rtype, slots_18.io.uop.dst_rtype connect issue_slots[18].uop.ldst_val, slots_18.io.uop.ldst_val connect issue_slots[18].uop.lrs3, slots_18.io.uop.lrs3 connect issue_slots[18].uop.lrs2, slots_18.io.uop.lrs2 connect issue_slots[18].uop.lrs1, slots_18.io.uop.lrs1 connect issue_slots[18].uop.ldst, slots_18.io.uop.ldst connect issue_slots[18].uop.ldst_is_rs1, slots_18.io.uop.ldst_is_rs1 connect issue_slots[18].uop.flush_on_commit, slots_18.io.uop.flush_on_commit connect issue_slots[18].uop.is_unique, slots_18.io.uop.is_unique connect issue_slots[18].uop.is_sys_pc2epc, slots_18.io.uop.is_sys_pc2epc connect issue_slots[18].uop.uses_stq, slots_18.io.uop.uses_stq connect issue_slots[18].uop.uses_ldq, slots_18.io.uop.uses_ldq connect issue_slots[18].uop.is_amo, slots_18.io.uop.is_amo connect issue_slots[18].uop.is_fencei, slots_18.io.uop.is_fencei connect issue_slots[18].uop.is_fence, slots_18.io.uop.is_fence connect issue_slots[18].uop.mem_signed, slots_18.io.uop.mem_signed connect issue_slots[18].uop.mem_size, slots_18.io.uop.mem_size connect issue_slots[18].uop.mem_cmd, slots_18.io.uop.mem_cmd connect issue_slots[18].uop.bypassable, slots_18.io.uop.bypassable connect issue_slots[18].uop.exc_cause, slots_18.io.uop.exc_cause connect issue_slots[18].uop.exception, slots_18.io.uop.exception connect issue_slots[18].uop.stale_pdst, slots_18.io.uop.stale_pdst connect issue_slots[18].uop.ppred_busy, slots_18.io.uop.ppred_busy connect issue_slots[18].uop.prs3_busy, slots_18.io.uop.prs3_busy connect issue_slots[18].uop.prs2_busy, slots_18.io.uop.prs2_busy connect issue_slots[18].uop.prs1_busy, slots_18.io.uop.prs1_busy connect issue_slots[18].uop.ppred, slots_18.io.uop.ppred connect issue_slots[18].uop.prs3, slots_18.io.uop.prs3 connect issue_slots[18].uop.prs2, slots_18.io.uop.prs2 connect issue_slots[18].uop.prs1, slots_18.io.uop.prs1 connect issue_slots[18].uop.pdst, slots_18.io.uop.pdst connect issue_slots[18].uop.rxq_idx, slots_18.io.uop.rxq_idx connect issue_slots[18].uop.stq_idx, slots_18.io.uop.stq_idx connect issue_slots[18].uop.ldq_idx, slots_18.io.uop.ldq_idx connect issue_slots[18].uop.rob_idx, slots_18.io.uop.rob_idx connect issue_slots[18].uop.csr_addr, slots_18.io.uop.csr_addr connect issue_slots[18].uop.imm_packed, slots_18.io.uop.imm_packed connect issue_slots[18].uop.taken, slots_18.io.uop.taken connect issue_slots[18].uop.pc_lob, slots_18.io.uop.pc_lob connect issue_slots[18].uop.edge_inst, slots_18.io.uop.edge_inst connect issue_slots[18].uop.ftq_idx, slots_18.io.uop.ftq_idx connect issue_slots[18].uop.br_tag, slots_18.io.uop.br_tag connect issue_slots[18].uop.br_mask, slots_18.io.uop.br_mask connect issue_slots[18].uop.is_sfb, slots_18.io.uop.is_sfb connect issue_slots[18].uop.is_jal, slots_18.io.uop.is_jal connect issue_slots[18].uop.is_jalr, slots_18.io.uop.is_jalr connect issue_slots[18].uop.is_br, slots_18.io.uop.is_br connect issue_slots[18].uop.iw_p2_poisoned, slots_18.io.uop.iw_p2_poisoned connect issue_slots[18].uop.iw_p1_poisoned, slots_18.io.uop.iw_p1_poisoned connect issue_slots[18].uop.iw_state, slots_18.io.uop.iw_state connect issue_slots[18].uop.ctrl.is_std, slots_18.io.uop.ctrl.is_std connect issue_slots[18].uop.ctrl.is_sta, slots_18.io.uop.ctrl.is_sta connect issue_slots[18].uop.ctrl.is_load, slots_18.io.uop.ctrl.is_load connect issue_slots[18].uop.ctrl.csr_cmd, slots_18.io.uop.ctrl.csr_cmd connect issue_slots[18].uop.ctrl.fcn_dw, slots_18.io.uop.ctrl.fcn_dw connect issue_slots[18].uop.ctrl.op_fcn, slots_18.io.uop.ctrl.op_fcn connect issue_slots[18].uop.ctrl.imm_sel, slots_18.io.uop.ctrl.imm_sel connect issue_slots[18].uop.ctrl.op2_sel, slots_18.io.uop.ctrl.op2_sel connect issue_slots[18].uop.ctrl.op1_sel, slots_18.io.uop.ctrl.op1_sel connect issue_slots[18].uop.ctrl.br_type, slots_18.io.uop.ctrl.br_type connect issue_slots[18].uop.fu_code, slots_18.io.uop.fu_code connect issue_slots[18].uop.iq_type, slots_18.io.uop.iq_type connect issue_slots[18].uop.debug_pc, slots_18.io.uop.debug_pc connect issue_slots[18].uop.is_rvc, slots_18.io.uop.is_rvc connect issue_slots[18].uop.debug_inst, slots_18.io.uop.debug_inst connect issue_slots[18].uop.inst, slots_18.io.uop.inst connect issue_slots[18].uop.uopc, slots_18.io.uop.uopc connect issue_slots[18].out_uop.debug_tsrc, slots_18.io.out_uop.debug_tsrc connect issue_slots[18].out_uop.debug_fsrc, slots_18.io.out_uop.debug_fsrc connect issue_slots[18].out_uop.bp_xcpt_if, slots_18.io.out_uop.bp_xcpt_if connect issue_slots[18].out_uop.bp_debug_if, slots_18.io.out_uop.bp_debug_if connect issue_slots[18].out_uop.xcpt_ma_if, slots_18.io.out_uop.xcpt_ma_if connect issue_slots[18].out_uop.xcpt_ae_if, slots_18.io.out_uop.xcpt_ae_if connect issue_slots[18].out_uop.xcpt_pf_if, slots_18.io.out_uop.xcpt_pf_if connect issue_slots[18].out_uop.fp_single, slots_18.io.out_uop.fp_single connect issue_slots[18].out_uop.fp_val, slots_18.io.out_uop.fp_val connect issue_slots[18].out_uop.frs3_en, slots_18.io.out_uop.frs3_en connect issue_slots[18].out_uop.lrs2_rtype, slots_18.io.out_uop.lrs2_rtype connect issue_slots[18].out_uop.lrs1_rtype, slots_18.io.out_uop.lrs1_rtype connect issue_slots[18].out_uop.dst_rtype, slots_18.io.out_uop.dst_rtype connect issue_slots[18].out_uop.ldst_val, slots_18.io.out_uop.ldst_val connect issue_slots[18].out_uop.lrs3, slots_18.io.out_uop.lrs3 connect issue_slots[18].out_uop.lrs2, slots_18.io.out_uop.lrs2 connect issue_slots[18].out_uop.lrs1, slots_18.io.out_uop.lrs1 connect issue_slots[18].out_uop.ldst, slots_18.io.out_uop.ldst connect issue_slots[18].out_uop.ldst_is_rs1, slots_18.io.out_uop.ldst_is_rs1 connect issue_slots[18].out_uop.flush_on_commit, slots_18.io.out_uop.flush_on_commit connect issue_slots[18].out_uop.is_unique, slots_18.io.out_uop.is_unique connect issue_slots[18].out_uop.is_sys_pc2epc, slots_18.io.out_uop.is_sys_pc2epc connect issue_slots[18].out_uop.uses_stq, slots_18.io.out_uop.uses_stq connect issue_slots[18].out_uop.uses_ldq, slots_18.io.out_uop.uses_ldq connect issue_slots[18].out_uop.is_amo, slots_18.io.out_uop.is_amo connect issue_slots[18].out_uop.is_fencei, slots_18.io.out_uop.is_fencei connect issue_slots[18].out_uop.is_fence, slots_18.io.out_uop.is_fence connect issue_slots[18].out_uop.mem_signed, slots_18.io.out_uop.mem_signed connect issue_slots[18].out_uop.mem_size, slots_18.io.out_uop.mem_size connect issue_slots[18].out_uop.mem_cmd, slots_18.io.out_uop.mem_cmd connect issue_slots[18].out_uop.bypassable, slots_18.io.out_uop.bypassable connect issue_slots[18].out_uop.exc_cause, slots_18.io.out_uop.exc_cause connect issue_slots[18].out_uop.exception, slots_18.io.out_uop.exception connect issue_slots[18].out_uop.stale_pdst, slots_18.io.out_uop.stale_pdst connect issue_slots[18].out_uop.ppred_busy, slots_18.io.out_uop.ppred_busy connect issue_slots[18].out_uop.prs3_busy, slots_18.io.out_uop.prs3_busy connect issue_slots[18].out_uop.prs2_busy, slots_18.io.out_uop.prs2_busy connect issue_slots[18].out_uop.prs1_busy, slots_18.io.out_uop.prs1_busy connect issue_slots[18].out_uop.ppred, slots_18.io.out_uop.ppred connect issue_slots[18].out_uop.prs3, slots_18.io.out_uop.prs3 connect issue_slots[18].out_uop.prs2, slots_18.io.out_uop.prs2 connect issue_slots[18].out_uop.prs1, slots_18.io.out_uop.prs1 connect issue_slots[18].out_uop.pdst, slots_18.io.out_uop.pdst connect issue_slots[18].out_uop.rxq_idx, slots_18.io.out_uop.rxq_idx connect issue_slots[18].out_uop.stq_idx, slots_18.io.out_uop.stq_idx connect issue_slots[18].out_uop.ldq_idx, slots_18.io.out_uop.ldq_idx connect issue_slots[18].out_uop.rob_idx, slots_18.io.out_uop.rob_idx connect issue_slots[18].out_uop.csr_addr, slots_18.io.out_uop.csr_addr connect issue_slots[18].out_uop.imm_packed, slots_18.io.out_uop.imm_packed connect issue_slots[18].out_uop.taken, slots_18.io.out_uop.taken connect issue_slots[18].out_uop.pc_lob, slots_18.io.out_uop.pc_lob connect issue_slots[18].out_uop.edge_inst, slots_18.io.out_uop.edge_inst connect issue_slots[18].out_uop.ftq_idx, slots_18.io.out_uop.ftq_idx connect issue_slots[18].out_uop.br_tag, slots_18.io.out_uop.br_tag connect issue_slots[18].out_uop.br_mask, slots_18.io.out_uop.br_mask connect issue_slots[18].out_uop.is_sfb, slots_18.io.out_uop.is_sfb connect issue_slots[18].out_uop.is_jal, slots_18.io.out_uop.is_jal connect issue_slots[18].out_uop.is_jalr, slots_18.io.out_uop.is_jalr connect issue_slots[18].out_uop.is_br, slots_18.io.out_uop.is_br connect issue_slots[18].out_uop.iw_p2_poisoned, slots_18.io.out_uop.iw_p2_poisoned connect issue_slots[18].out_uop.iw_p1_poisoned, slots_18.io.out_uop.iw_p1_poisoned connect issue_slots[18].out_uop.iw_state, slots_18.io.out_uop.iw_state connect issue_slots[18].out_uop.ctrl.is_std, slots_18.io.out_uop.ctrl.is_std connect issue_slots[18].out_uop.ctrl.is_sta, slots_18.io.out_uop.ctrl.is_sta connect issue_slots[18].out_uop.ctrl.is_load, slots_18.io.out_uop.ctrl.is_load connect issue_slots[18].out_uop.ctrl.csr_cmd, slots_18.io.out_uop.ctrl.csr_cmd connect issue_slots[18].out_uop.ctrl.fcn_dw, slots_18.io.out_uop.ctrl.fcn_dw connect issue_slots[18].out_uop.ctrl.op_fcn, slots_18.io.out_uop.ctrl.op_fcn connect issue_slots[18].out_uop.ctrl.imm_sel, slots_18.io.out_uop.ctrl.imm_sel connect issue_slots[18].out_uop.ctrl.op2_sel, slots_18.io.out_uop.ctrl.op2_sel connect issue_slots[18].out_uop.ctrl.op1_sel, slots_18.io.out_uop.ctrl.op1_sel connect issue_slots[18].out_uop.ctrl.br_type, slots_18.io.out_uop.ctrl.br_type connect issue_slots[18].out_uop.fu_code, slots_18.io.out_uop.fu_code connect issue_slots[18].out_uop.iq_type, slots_18.io.out_uop.iq_type connect issue_slots[18].out_uop.debug_pc, slots_18.io.out_uop.debug_pc connect issue_slots[18].out_uop.is_rvc, slots_18.io.out_uop.is_rvc connect issue_slots[18].out_uop.debug_inst, slots_18.io.out_uop.debug_inst connect issue_slots[18].out_uop.inst, slots_18.io.out_uop.inst connect issue_slots[18].out_uop.uopc, slots_18.io.out_uop.uopc connect slots_18.io.in_uop.bits.debug_tsrc, issue_slots[18].in_uop.bits.debug_tsrc connect slots_18.io.in_uop.bits.debug_fsrc, issue_slots[18].in_uop.bits.debug_fsrc connect slots_18.io.in_uop.bits.bp_xcpt_if, issue_slots[18].in_uop.bits.bp_xcpt_if connect slots_18.io.in_uop.bits.bp_debug_if, issue_slots[18].in_uop.bits.bp_debug_if connect slots_18.io.in_uop.bits.xcpt_ma_if, issue_slots[18].in_uop.bits.xcpt_ma_if connect slots_18.io.in_uop.bits.xcpt_ae_if, issue_slots[18].in_uop.bits.xcpt_ae_if connect slots_18.io.in_uop.bits.xcpt_pf_if, issue_slots[18].in_uop.bits.xcpt_pf_if connect slots_18.io.in_uop.bits.fp_single, issue_slots[18].in_uop.bits.fp_single connect slots_18.io.in_uop.bits.fp_val, issue_slots[18].in_uop.bits.fp_val connect slots_18.io.in_uop.bits.frs3_en, issue_slots[18].in_uop.bits.frs3_en connect slots_18.io.in_uop.bits.lrs2_rtype, issue_slots[18].in_uop.bits.lrs2_rtype connect slots_18.io.in_uop.bits.lrs1_rtype, issue_slots[18].in_uop.bits.lrs1_rtype connect slots_18.io.in_uop.bits.dst_rtype, issue_slots[18].in_uop.bits.dst_rtype connect slots_18.io.in_uop.bits.ldst_val, issue_slots[18].in_uop.bits.ldst_val connect slots_18.io.in_uop.bits.lrs3, issue_slots[18].in_uop.bits.lrs3 connect slots_18.io.in_uop.bits.lrs2, issue_slots[18].in_uop.bits.lrs2 connect slots_18.io.in_uop.bits.lrs1, issue_slots[18].in_uop.bits.lrs1 connect slots_18.io.in_uop.bits.ldst, issue_slots[18].in_uop.bits.ldst connect slots_18.io.in_uop.bits.ldst_is_rs1, issue_slots[18].in_uop.bits.ldst_is_rs1 connect slots_18.io.in_uop.bits.flush_on_commit, issue_slots[18].in_uop.bits.flush_on_commit connect slots_18.io.in_uop.bits.is_unique, issue_slots[18].in_uop.bits.is_unique connect slots_18.io.in_uop.bits.is_sys_pc2epc, issue_slots[18].in_uop.bits.is_sys_pc2epc connect slots_18.io.in_uop.bits.uses_stq, issue_slots[18].in_uop.bits.uses_stq connect slots_18.io.in_uop.bits.uses_ldq, issue_slots[18].in_uop.bits.uses_ldq connect slots_18.io.in_uop.bits.is_amo, issue_slots[18].in_uop.bits.is_amo connect slots_18.io.in_uop.bits.is_fencei, issue_slots[18].in_uop.bits.is_fencei connect slots_18.io.in_uop.bits.is_fence, issue_slots[18].in_uop.bits.is_fence connect slots_18.io.in_uop.bits.mem_signed, issue_slots[18].in_uop.bits.mem_signed connect slots_18.io.in_uop.bits.mem_size, issue_slots[18].in_uop.bits.mem_size connect slots_18.io.in_uop.bits.mem_cmd, issue_slots[18].in_uop.bits.mem_cmd connect slots_18.io.in_uop.bits.bypassable, issue_slots[18].in_uop.bits.bypassable connect slots_18.io.in_uop.bits.exc_cause, issue_slots[18].in_uop.bits.exc_cause connect slots_18.io.in_uop.bits.exception, issue_slots[18].in_uop.bits.exception connect slots_18.io.in_uop.bits.stale_pdst, issue_slots[18].in_uop.bits.stale_pdst connect slots_18.io.in_uop.bits.ppred_busy, issue_slots[18].in_uop.bits.ppred_busy connect slots_18.io.in_uop.bits.prs3_busy, issue_slots[18].in_uop.bits.prs3_busy connect slots_18.io.in_uop.bits.prs2_busy, issue_slots[18].in_uop.bits.prs2_busy connect slots_18.io.in_uop.bits.prs1_busy, issue_slots[18].in_uop.bits.prs1_busy connect slots_18.io.in_uop.bits.ppred, issue_slots[18].in_uop.bits.ppred connect slots_18.io.in_uop.bits.prs3, issue_slots[18].in_uop.bits.prs3 connect slots_18.io.in_uop.bits.prs2, issue_slots[18].in_uop.bits.prs2 connect slots_18.io.in_uop.bits.prs1, issue_slots[18].in_uop.bits.prs1 connect slots_18.io.in_uop.bits.pdst, issue_slots[18].in_uop.bits.pdst connect slots_18.io.in_uop.bits.rxq_idx, issue_slots[18].in_uop.bits.rxq_idx connect slots_18.io.in_uop.bits.stq_idx, issue_slots[18].in_uop.bits.stq_idx connect slots_18.io.in_uop.bits.ldq_idx, issue_slots[18].in_uop.bits.ldq_idx connect slots_18.io.in_uop.bits.rob_idx, issue_slots[18].in_uop.bits.rob_idx connect slots_18.io.in_uop.bits.csr_addr, issue_slots[18].in_uop.bits.csr_addr connect slots_18.io.in_uop.bits.imm_packed, issue_slots[18].in_uop.bits.imm_packed connect slots_18.io.in_uop.bits.taken, issue_slots[18].in_uop.bits.taken connect slots_18.io.in_uop.bits.pc_lob, issue_slots[18].in_uop.bits.pc_lob connect slots_18.io.in_uop.bits.edge_inst, issue_slots[18].in_uop.bits.edge_inst connect slots_18.io.in_uop.bits.ftq_idx, issue_slots[18].in_uop.bits.ftq_idx connect slots_18.io.in_uop.bits.br_tag, issue_slots[18].in_uop.bits.br_tag connect slots_18.io.in_uop.bits.br_mask, issue_slots[18].in_uop.bits.br_mask connect slots_18.io.in_uop.bits.is_sfb, issue_slots[18].in_uop.bits.is_sfb connect slots_18.io.in_uop.bits.is_jal, issue_slots[18].in_uop.bits.is_jal connect slots_18.io.in_uop.bits.is_jalr, issue_slots[18].in_uop.bits.is_jalr connect slots_18.io.in_uop.bits.is_br, issue_slots[18].in_uop.bits.is_br connect slots_18.io.in_uop.bits.iw_p2_poisoned, issue_slots[18].in_uop.bits.iw_p2_poisoned connect slots_18.io.in_uop.bits.iw_p1_poisoned, issue_slots[18].in_uop.bits.iw_p1_poisoned connect slots_18.io.in_uop.bits.iw_state, issue_slots[18].in_uop.bits.iw_state connect slots_18.io.in_uop.bits.ctrl.is_std, issue_slots[18].in_uop.bits.ctrl.is_std connect slots_18.io.in_uop.bits.ctrl.is_sta, issue_slots[18].in_uop.bits.ctrl.is_sta connect slots_18.io.in_uop.bits.ctrl.is_load, issue_slots[18].in_uop.bits.ctrl.is_load connect slots_18.io.in_uop.bits.ctrl.csr_cmd, issue_slots[18].in_uop.bits.ctrl.csr_cmd connect slots_18.io.in_uop.bits.ctrl.fcn_dw, issue_slots[18].in_uop.bits.ctrl.fcn_dw connect slots_18.io.in_uop.bits.ctrl.op_fcn, issue_slots[18].in_uop.bits.ctrl.op_fcn connect slots_18.io.in_uop.bits.ctrl.imm_sel, issue_slots[18].in_uop.bits.ctrl.imm_sel connect slots_18.io.in_uop.bits.ctrl.op2_sel, issue_slots[18].in_uop.bits.ctrl.op2_sel connect slots_18.io.in_uop.bits.ctrl.op1_sel, issue_slots[18].in_uop.bits.ctrl.op1_sel connect slots_18.io.in_uop.bits.ctrl.br_type, issue_slots[18].in_uop.bits.ctrl.br_type connect slots_18.io.in_uop.bits.fu_code, issue_slots[18].in_uop.bits.fu_code connect slots_18.io.in_uop.bits.iq_type, issue_slots[18].in_uop.bits.iq_type connect slots_18.io.in_uop.bits.debug_pc, issue_slots[18].in_uop.bits.debug_pc connect slots_18.io.in_uop.bits.is_rvc, issue_slots[18].in_uop.bits.is_rvc connect slots_18.io.in_uop.bits.debug_inst, issue_slots[18].in_uop.bits.debug_inst connect slots_18.io.in_uop.bits.inst, issue_slots[18].in_uop.bits.inst connect slots_18.io.in_uop.bits.uopc, issue_slots[18].in_uop.bits.uopc connect slots_18.io.in_uop.valid, issue_slots[18].in_uop.valid connect slots_18.io.spec_ld_wakeup[0].bits, issue_slots[18].spec_ld_wakeup[0].bits connect slots_18.io.spec_ld_wakeup[0].valid, issue_slots[18].spec_ld_wakeup[0].valid connect slots_18.io.pred_wakeup_port.bits, issue_slots[18].pred_wakeup_port.bits connect slots_18.io.pred_wakeup_port.valid, issue_slots[18].pred_wakeup_port.valid connect slots_18.io.wakeup_ports[0].bits.poisoned, issue_slots[18].wakeup_ports[0].bits.poisoned connect slots_18.io.wakeup_ports[0].bits.pdst, issue_slots[18].wakeup_ports[0].bits.pdst connect slots_18.io.wakeup_ports[0].valid, issue_slots[18].wakeup_ports[0].valid connect slots_18.io.wakeup_ports[1].bits.poisoned, issue_slots[18].wakeup_ports[1].bits.poisoned connect slots_18.io.wakeup_ports[1].bits.pdst, issue_slots[18].wakeup_ports[1].bits.pdst connect slots_18.io.wakeup_ports[1].valid, issue_slots[18].wakeup_ports[1].valid connect slots_18.io.wakeup_ports[2].bits.poisoned, issue_slots[18].wakeup_ports[2].bits.poisoned connect slots_18.io.wakeup_ports[2].bits.pdst, issue_slots[18].wakeup_ports[2].bits.pdst connect slots_18.io.wakeup_ports[2].valid, issue_slots[18].wakeup_ports[2].valid connect slots_18.io.wakeup_ports[3].bits.poisoned, issue_slots[18].wakeup_ports[3].bits.poisoned connect slots_18.io.wakeup_ports[3].bits.pdst, issue_slots[18].wakeup_ports[3].bits.pdst connect slots_18.io.wakeup_ports[3].valid, issue_slots[18].wakeup_ports[3].valid connect slots_18.io.wakeup_ports[4].bits.poisoned, issue_slots[18].wakeup_ports[4].bits.poisoned connect slots_18.io.wakeup_ports[4].bits.pdst, issue_slots[18].wakeup_ports[4].bits.pdst connect slots_18.io.wakeup_ports[4].valid, issue_slots[18].wakeup_ports[4].valid connect slots_18.io.wakeup_ports[5].bits.poisoned, issue_slots[18].wakeup_ports[5].bits.poisoned connect slots_18.io.wakeup_ports[5].bits.pdst, issue_slots[18].wakeup_ports[5].bits.pdst connect slots_18.io.wakeup_ports[5].valid, issue_slots[18].wakeup_ports[5].valid connect slots_18.io.wakeup_ports[6].bits.poisoned, issue_slots[18].wakeup_ports[6].bits.poisoned connect slots_18.io.wakeup_ports[6].bits.pdst, issue_slots[18].wakeup_ports[6].bits.pdst connect slots_18.io.wakeup_ports[6].valid, issue_slots[18].wakeup_ports[6].valid connect slots_18.io.ldspec_miss, issue_slots[18].ldspec_miss connect slots_18.io.clear, issue_slots[18].clear connect slots_18.io.kill, issue_slots[18].kill connect slots_18.io.brupdate.b2.target_offset, issue_slots[18].brupdate.b2.target_offset connect slots_18.io.brupdate.b2.jalr_target, issue_slots[18].brupdate.b2.jalr_target connect slots_18.io.brupdate.b2.pc_sel, issue_slots[18].brupdate.b2.pc_sel connect slots_18.io.brupdate.b2.cfi_type, issue_slots[18].brupdate.b2.cfi_type connect slots_18.io.brupdate.b2.taken, issue_slots[18].brupdate.b2.taken connect slots_18.io.brupdate.b2.mispredict, issue_slots[18].brupdate.b2.mispredict connect slots_18.io.brupdate.b2.valid, issue_slots[18].brupdate.b2.valid connect slots_18.io.brupdate.b2.uop.debug_tsrc, issue_slots[18].brupdate.b2.uop.debug_tsrc connect slots_18.io.brupdate.b2.uop.debug_fsrc, issue_slots[18].brupdate.b2.uop.debug_fsrc connect slots_18.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[18].brupdate.b2.uop.bp_xcpt_if connect slots_18.io.brupdate.b2.uop.bp_debug_if, issue_slots[18].brupdate.b2.uop.bp_debug_if connect slots_18.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[18].brupdate.b2.uop.xcpt_ma_if connect slots_18.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[18].brupdate.b2.uop.xcpt_ae_if connect slots_18.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[18].brupdate.b2.uop.xcpt_pf_if connect slots_18.io.brupdate.b2.uop.fp_single, issue_slots[18].brupdate.b2.uop.fp_single connect slots_18.io.brupdate.b2.uop.fp_val, issue_slots[18].brupdate.b2.uop.fp_val connect slots_18.io.brupdate.b2.uop.frs3_en, issue_slots[18].brupdate.b2.uop.frs3_en connect slots_18.io.brupdate.b2.uop.lrs2_rtype, issue_slots[18].brupdate.b2.uop.lrs2_rtype connect slots_18.io.brupdate.b2.uop.lrs1_rtype, issue_slots[18].brupdate.b2.uop.lrs1_rtype connect slots_18.io.brupdate.b2.uop.dst_rtype, issue_slots[18].brupdate.b2.uop.dst_rtype connect slots_18.io.brupdate.b2.uop.ldst_val, issue_slots[18].brupdate.b2.uop.ldst_val connect slots_18.io.brupdate.b2.uop.lrs3, issue_slots[18].brupdate.b2.uop.lrs3 connect slots_18.io.brupdate.b2.uop.lrs2, issue_slots[18].brupdate.b2.uop.lrs2 connect slots_18.io.brupdate.b2.uop.lrs1, issue_slots[18].brupdate.b2.uop.lrs1 connect slots_18.io.brupdate.b2.uop.ldst, issue_slots[18].brupdate.b2.uop.ldst connect slots_18.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[18].brupdate.b2.uop.ldst_is_rs1 connect slots_18.io.brupdate.b2.uop.flush_on_commit, issue_slots[18].brupdate.b2.uop.flush_on_commit connect slots_18.io.brupdate.b2.uop.is_unique, issue_slots[18].brupdate.b2.uop.is_unique connect slots_18.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[18].brupdate.b2.uop.is_sys_pc2epc connect slots_18.io.brupdate.b2.uop.uses_stq, issue_slots[18].brupdate.b2.uop.uses_stq connect slots_18.io.brupdate.b2.uop.uses_ldq, issue_slots[18].brupdate.b2.uop.uses_ldq connect slots_18.io.brupdate.b2.uop.is_amo, issue_slots[18].brupdate.b2.uop.is_amo connect slots_18.io.brupdate.b2.uop.is_fencei, issue_slots[18].brupdate.b2.uop.is_fencei connect slots_18.io.brupdate.b2.uop.is_fence, issue_slots[18].brupdate.b2.uop.is_fence connect slots_18.io.brupdate.b2.uop.mem_signed, issue_slots[18].brupdate.b2.uop.mem_signed connect slots_18.io.brupdate.b2.uop.mem_size, issue_slots[18].brupdate.b2.uop.mem_size connect slots_18.io.brupdate.b2.uop.mem_cmd, issue_slots[18].brupdate.b2.uop.mem_cmd connect slots_18.io.brupdate.b2.uop.bypassable, issue_slots[18].brupdate.b2.uop.bypassable connect slots_18.io.brupdate.b2.uop.exc_cause, issue_slots[18].brupdate.b2.uop.exc_cause connect slots_18.io.brupdate.b2.uop.exception, issue_slots[18].brupdate.b2.uop.exception connect slots_18.io.brupdate.b2.uop.stale_pdst, issue_slots[18].brupdate.b2.uop.stale_pdst connect slots_18.io.brupdate.b2.uop.ppred_busy, issue_slots[18].brupdate.b2.uop.ppred_busy connect slots_18.io.brupdate.b2.uop.prs3_busy, issue_slots[18].brupdate.b2.uop.prs3_busy connect slots_18.io.brupdate.b2.uop.prs2_busy, issue_slots[18].brupdate.b2.uop.prs2_busy connect slots_18.io.brupdate.b2.uop.prs1_busy, issue_slots[18].brupdate.b2.uop.prs1_busy connect slots_18.io.brupdate.b2.uop.ppred, issue_slots[18].brupdate.b2.uop.ppred connect slots_18.io.brupdate.b2.uop.prs3, issue_slots[18].brupdate.b2.uop.prs3 connect slots_18.io.brupdate.b2.uop.prs2, issue_slots[18].brupdate.b2.uop.prs2 connect slots_18.io.brupdate.b2.uop.prs1, issue_slots[18].brupdate.b2.uop.prs1 connect slots_18.io.brupdate.b2.uop.pdst, issue_slots[18].brupdate.b2.uop.pdst connect slots_18.io.brupdate.b2.uop.rxq_idx, issue_slots[18].brupdate.b2.uop.rxq_idx connect slots_18.io.brupdate.b2.uop.stq_idx, issue_slots[18].brupdate.b2.uop.stq_idx connect slots_18.io.brupdate.b2.uop.ldq_idx, issue_slots[18].brupdate.b2.uop.ldq_idx connect slots_18.io.brupdate.b2.uop.rob_idx, issue_slots[18].brupdate.b2.uop.rob_idx connect slots_18.io.brupdate.b2.uop.csr_addr, issue_slots[18].brupdate.b2.uop.csr_addr connect slots_18.io.brupdate.b2.uop.imm_packed, issue_slots[18].brupdate.b2.uop.imm_packed connect slots_18.io.brupdate.b2.uop.taken, issue_slots[18].brupdate.b2.uop.taken connect slots_18.io.brupdate.b2.uop.pc_lob, issue_slots[18].brupdate.b2.uop.pc_lob connect slots_18.io.brupdate.b2.uop.edge_inst, issue_slots[18].brupdate.b2.uop.edge_inst connect slots_18.io.brupdate.b2.uop.ftq_idx, issue_slots[18].brupdate.b2.uop.ftq_idx connect slots_18.io.brupdate.b2.uop.br_tag, issue_slots[18].brupdate.b2.uop.br_tag connect slots_18.io.brupdate.b2.uop.br_mask, issue_slots[18].brupdate.b2.uop.br_mask connect slots_18.io.brupdate.b2.uop.is_sfb, issue_slots[18].brupdate.b2.uop.is_sfb connect slots_18.io.brupdate.b2.uop.is_jal, issue_slots[18].brupdate.b2.uop.is_jal connect slots_18.io.brupdate.b2.uop.is_jalr, issue_slots[18].brupdate.b2.uop.is_jalr connect slots_18.io.brupdate.b2.uop.is_br, issue_slots[18].brupdate.b2.uop.is_br connect slots_18.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[18].brupdate.b2.uop.iw_p2_poisoned connect slots_18.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[18].brupdate.b2.uop.iw_p1_poisoned connect slots_18.io.brupdate.b2.uop.iw_state, issue_slots[18].brupdate.b2.uop.iw_state connect slots_18.io.brupdate.b2.uop.ctrl.is_std, issue_slots[18].brupdate.b2.uop.ctrl.is_std connect slots_18.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[18].brupdate.b2.uop.ctrl.is_sta connect slots_18.io.brupdate.b2.uop.ctrl.is_load, issue_slots[18].brupdate.b2.uop.ctrl.is_load connect slots_18.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[18].brupdate.b2.uop.ctrl.csr_cmd connect slots_18.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[18].brupdate.b2.uop.ctrl.fcn_dw connect slots_18.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[18].brupdate.b2.uop.ctrl.op_fcn connect slots_18.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[18].brupdate.b2.uop.ctrl.imm_sel connect slots_18.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[18].brupdate.b2.uop.ctrl.op2_sel connect slots_18.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[18].brupdate.b2.uop.ctrl.op1_sel connect slots_18.io.brupdate.b2.uop.ctrl.br_type, issue_slots[18].brupdate.b2.uop.ctrl.br_type connect slots_18.io.brupdate.b2.uop.fu_code, issue_slots[18].brupdate.b2.uop.fu_code connect slots_18.io.brupdate.b2.uop.iq_type, issue_slots[18].brupdate.b2.uop.iq_type connect slots_18.io.brupdate.b2.uop.debug_pc, issue_slots[18].brupdate.b2.uop.debug_pc connect slots_18.io.brupdate.b2.uop.is_rvc, issue_slots[18].brupdate.b2.uop.is_rvc connect slots_18.io.brupdate.b2.uop.debug_inst, issue_slots[18].brupdate.b2.uop.debug_inst connect slots_18.io.brupdate.b2.uop.inst, issue_slots[18].brupdate.b2.uop.inst connect slots_18.io.brupdate.b2.uop.uopc, issue_slots[18].brupdate.b2.uop.uopc connect slots_18.io.brupdate.b1.mispredict_mask, issue_slots[18].brupdate.b1.mispredict_mask connect slots_18.io.brupdate.b1.resolve_mask, issue_slots[18].brupdate.b1.resolve_mask connect slots_18.io.grant, issue_slots[18].grant connect issue_slots[18].request_hp, slots_18.io.request_hp connect issue_slots[18].request, slots_18.io.request connect issue_slots[18].will_be_valid, slots_18.io.will_be_valid connect issue_slots[18].valid, slots_18.io.valid connect issue_slots[19].debug.state, slots_19.io.debug.state connect issue_slots[19].debug.ppred, slots_19.io.debug.ppred connect issue_slots[19].debug.p3, slots_19.io.debug.p3 connect issue_slots[19].debug.p2, slots_19.io.debug.p2 connect issue_slots[19].debug.p1, slots_19.io.debug.p1 connect issue_slots[19].uop.debug_tsrc, slots_19.io.uop.debug_tsrc connect issue_slots[19].uop.debug_fsrc, slots_19.io.uop.debug_fsrc connect issue_slots[19].uop.bp_xcpt_if, slots_19.io.uop.bp_xcpt_if connect issue_slots[19].uop.bp_debug_if, slots_19.io.uop.bp_debug_if connect issue_slots[19].uop.xcpt_ma_if, slots_19.io.uop.xcpt_ma_if connect issue_slots[19].uop.xcpt_ae_if, slots_19.io.uop.xcpt_ae_if connect issue_slots[19].uop.xcpt_pf_if, slots_19.io.uop.xcpt_pf_if connect issue_slots[19].uop.fp_single, slots_19.io.uop.fp_single connect issue_slots[19].uop.fp_val, slots_19.io.uop.fp_val connect issue_slots[19].uop.frs3_en, slots_19.io.uop.frs3_en connect issue_slots[19].uop.lrs2_rtype, slots_19.io.uop.lrs2_rtype connect issue_slots[19].uop.lrs1_rtype, slots_19.io.uop.lrs1_rtype connect issue_slots[19].uop.dst_rtype, slots_19.io.uop.dst_rtype connect issue_slots[19].uop.ldst_val, slots_19.io.uop.ldst_val connect issue_slots[19].uop.lrs3, slots_19.io.uop.lrs3 connect issue_slots[19].uop.lrs2, slots_19.io.uop.lrs2 connect issue_slots[19].uop.lrs1, slots_19.io.uop.lrs1 connect issue_slots[19].uop.ldst, slots_19.io.uop.ldst connect issue_slots[19].uop.ldst_is_rs1, slots_19.io.uop.ldst_is_rs1 connect issue_slots[19].uop.flush_on_commit, slots_19.io.uop.flush_on_commit connect issue_slots[19].uop.is_unique, slots_19.io.uop.is_unique connect issue_slots[19].uop.is_sys_pc2epc, slots_19.io.uop.is_sys_pc2epc connect issue_slots[19].uop.uses_stq, slots_19.io.uop.uses_stq connect issue_slots[19].uop.uses_ldq, slots_19.io.uop.uses_ldq connect issue_slots[19].uop.is_amo, slots_19.io.uop.is_amo connect issue_slots[19].uop.is_fencei, slots_19.io.uop.is_fencei connect issue_slots[19].uop.is_fence, slots_19.io.uop.is_fence connect issue_slots[19].uop.mem_signed, slots_19.io.uop.mem_signed connect issue_slots[19].uop.mem_size, slots_19.io.uop.mem_size connect issue_slots[19].uop.mem_cmd, slots_19.io.uop.mem_cmd connect issue_slots[19].uop.bypassable, slots_19.io.uop.bypassable connect issue_slots[19].uop.exc_cause, slots_19.io.uop.exc_cause connect issue_slots[19].uop.exception, slots_19.io.uop.exception connect issue_slots[19].uop.stale_pdst, slots_19.io.uop.stale_pdst connect issue_slots[19].uop.ppred_busy, slots_19.io.uop.ppred_busy connect issue_slots[19].uop.prs3_busy, slots_19.io.uop.prs3_busy connect issue_slots[19].uop.prs2_busy, slots_19.io.uop.prs2_busy connect issue_slots[19].uop.prs1_busy, slots_19.io.uop.prs1_busy connect issue_slots[19].uop.ppred, slots_19.io.uop.ppred connect issue_slots[19].uop.prs3, slots_19.io.uop.prs3 connect issue_slots[19].uop.prs2, slots_19.io.uop.prs2 connect issue_slots[19].uop.prs1, slots_19.io.uop.prs1 connect issue_slots[19].uop.pdst, slots_19.io.uop.pdst connect issue_slots[19].uop.rxq_idx, slots_19.io.uop.rxq_idx connect issue_slots[19].uop.stq_idx, slots_19.io.uop.stq_idx connect issue_slots[19].uop.ldq_idx, slots_19.io.uop.ldq_idx connect issue_slots[19].uop.rob_idx, slots_19.io.uop.rob_idx connect issue_slots[19].uop.csr_addr, slots_19.io.uop.csr_addr connect issue_slots[19].uop.imm_packed, slots_19.io.uop.imm_packed connect issue_slots[19].uop.taken, slots_19.io.uop.taken connect issue_slots[19].uop.pc_lob, slots_19.io.uop.pc_lob connect issue_slots[19].uop.edge_inst, slots_19.io.uop.edge_inst connect issue_slots[19].uop.ftq_idx, slots_19.io.uop.ftq_idx connect issue_slots[19].uop.br_tag, slots_19.io.uop.br_tag connect issue_slots[19].uop.br_mask, slots_19.io.uop.br_mask connect issue_slots[19].uop.is_sfb, slots_19.io.uop.is_sfb connect issue_slots[19].uop.is_jal, slots_19.io.uop.is_jal connect issue_slots[19].uop.is_jalr, slots_19.io.uop.is_jalr connect issue_slots[19].uop.is_br, slots_19.io.uop.is_br connect issue_slots[19].uop.iw_p2_poisoned, slots_19.io.uop.iw_p2_poisoned connect issue_slots[19].uop.iw_p1_poisoned, slots_19.io.uop.iw_p1_poisoned connect issue_slots[19].uop.iw_state, slots_19.io.uop.iw_state connect issue_slots[19].uop.ctrl.is_std, slots_19.io.uop.ctrl.is_std connect issue_slots[19].uop.ctrl.is_sta, slots_19.io.uop.ctrl.is_sta connect issue_slots[19].uop.ctrl.is_load, slots_19.io.uop.ctrl.is_load connect issue_slots[19].uop.ctrl.csr_cmd, slots_19.io.uop.ctrl.csr_cmd connect issue_slots[19].uop.ctrl.fcn_dw, slots_19.io.uop.ctrl.fcn_dw connect issue_slots[19].uop.ctrl.op_fcn, slots_19.io.uop.ctrl.op_fcn connect issue_slots[19].uop.ctrl.imm_sel, slots_19.io.uop.ctrl.imm_sel connect issue_slots[19].uop.ctrl.op2_sel, slots_19.io.uop.ctrl.op2_sel connect issue_slots[19].uop.ctrl.op1_sel, slots_19.io.uop.ctrl.op1_sel connect issue_slots[19].uop.ctrl.br_type, slots_19.io.uop.ctrl.br_type connect issue_slots[19].uop.fu_code, slots_19.io.uop.fu_code connect issue_slots[19].uop.iq_type, slots_19.io.uop.iq_type connect issue_slots[19].uop.debug_pc, slots_19.io.uop.debug_pc connect issue_slots[19].uop.is_rvc, slots_19.io.uop.is_rvc connect issue_slots[19].uop.debug_inst, slots_19.io.uop.debug_inst connect issue_slots[19].uop.inst, slots_19.io.uop.inst connect issue_slots[19].uop.uopc, slots_19.io.uop.uopc connect issue_slots[19].out_uop.debug_tsrc, slots_19.io.out_uop.debug_tsrc connect issue_slots[19].out_uop.debug_fsrc, slots_19.io.out_uop.debug_fsrc connect issue_slots[19].out_uop.bp_xcpt_if, slots_19.io.out_uop.bp_xcpt_if connect issue_slots[19].out_uop.bp_debug_if, slots_19.io.out_uop.bp_debug_if connect issue_slots[19].out_uop.xcpt_ma_if, slots_19.io.out_uop.xcpt_ma_if connect issue_slots[19].out_uop.xcpt_ae_if, slots_19.io.out_uop.xcpt_ae_if connect issue_slots[19].out_uop.xcpt_pf_if, slots_19.io.out_uop.xcpt_pf_if connect issue_slots[19].out_uop.fp_single, slots_19.io.out_uop.fp_single connect issue_slots[19].out_uop.fp_val, slots_19.io.out_uop.fp_val connect issue_slots[19].out_uop.frs3_en, slots_19.io.out_uop.frs3_en connect issue_slots[19].out_uop.lrs2_rtype, slots_19.io.out_uop.lrs2_rtype connect issue_slots[19].out_uop.lrs1_rtype, slots_19.io.out_uop.lrs1_rtype connect issue_slots[19].out_uop.dst_rtype, slots_19.io.out_uop.dst_rtype connect issue_slots[19].out_uop.ldst_val, slots_19.io.out_uop.ldst_val connect issue_slots[19].out_uop.lrs3, slots_19.io.out_uop.lrs3 connect issue_slots[19].out_uop.lrs2, slots_19.io.out_uop.lrs2 connect issue_slots[19].out_uop.lrs1, slots_19.io.out_uop.lrs1 connect issue_slots[19].out_uop.ldst, slots_19.io.out_uop.ldst connect issue_slots[19].out_uop.ldst_is_rs1, slots_19.io.out_uop.ldst_is_rs1 connect issue_slots[19].out_uop.flush_on_commit, slots_19.io.out_uop.flush_on_commit connect issue_slots[19].out_uop.is_unique, slots_19.io.out_uop.is_unique connect issue_slots[19].out_uop.is_sys_pc2epc, slots_19.io.out_uop.is_sys_pc2epc connect issue_slots[19].out_uop.uses_stq, slots_19.io.out_uop.uses_stq connect issue_slots[19].out_uop.uses_ldq, slots_19.io.out_uop.uses_ldq connect issue_slots[19].out_uop.is_amo, slots_19.io.out_uop.is_amo connect issue_slots[19].out_uop.is_fencei, slots_19.io.out_uop.is_fencei connect issue_slots[19].out_uop.is_fence, slots_19.io.out_uop.is_fence connect issue_slots[19].out_uop.mem_signed, slots_19.io.out_uop.mem_signed connect issue_slots[19].out_uop.mem_size, slots_19.io.out_uop.mem_size connect issue_slots[19].out_uop.mem_cmd, slots_19.io.out_uop.mem_cmd connect issue_slots[19].out_uop.bypassable, slots_19.io.out_uop.bypassable connect issue_slots[19].out_uop.exc_cause, slots_19.io.out_uop.exc_cause connect issue_slots[19].out_uop.exception, slots_19.io.out_uop.exception connect issue_slots[19].out_uop.stale_pdst, slots_19.io.out_uop.stale_pdst connect issue_slots[19].out_uop.ppred_busy, slots_19.io.out_uop.ppred_busy connect issue_slots[19].out_uop.prs3_busy, slots_19.io.out_uop.prs3_busy connect issue_slots[19].out_uop.prs2_busy, slots_19.io.out_uop.prs2_busy connect issue_slots[19].out_uop.prs1_busy, slots_19.io.out_uop.prs1_busy connect issue_slots[19].out_uop.ppred, slots_19.io.out_uop.ppred connect issue_slots[19].out_uop.prs3, slots_19.io.out_uop.prs3 connect issue_slots[19].out_uop.prs2, slots_19.io.out_uop.prs2 connect issue_slots[19].out_uop.prs1, slots_19.io.out_uop.prs1 connect issue_slots[19].out_uop.pdst, slots_19.io.out_uop.pdst connect issue_slots[19].out_uop.rxq_idx, slots_19.io.out_uop.rxq_idx connect issue_slots[19].out_uop.stq_idx, slots_19.io.out_uop.stq_idx connect issue_slots[19].out_uop.ldq_idx, slots_19.io.out_uop.ldq_idx connect issue_slots[19].out_uop.rob_idx, slots_19.io.out_uop.rob_idx connect issue_slots[19].out_uop.csr_addr, slots_19.io.out_uop.csr_addr connect issue_slots[19].out_uop.imm_packed, slots_19.io.out_uop.imm_packed connect issue_slots[19].out_uop.taken, slots_19.io.out_uop.taken connect issue_slots[19].out_uop.pc_lob, slots_19.io.out_uop.pc_lob connect issue_slots[19].out_uop.edge_inst, slots_19.io.out_uop.edge_inst connect issue_slots[19].out_uop.ftq_idx, slots_19.io.out_uop.ftq_idx connect issue_slots[19].out_uop.br_tag, slots_19.io.out_uop.br_tag connect issue_slots[19].out_uop.br_mask, slots_19.io.out_uop.br_mask connect issue_slots[19].out_uop.is_sfb, slots_19.io.out_uop.is_sfb connect issue_slots[19].out_uop.is_jal, slots_19.io.out_uop.is_jal connect issue_slots[19].out_uop.is_jalr, slots_19.io.out_uop.is_jalr connect issue_slots[19].out_uop.is_br, slots_19.io.out_uop.is_br connect issue_slots[19].out_uop.iw_p2_poisoned, slots_19.io.out_uop.iw_p2_poisoned connect issue_slots[19].out_uop.iw_p1_poisoned, slots_19.io.out_uop.iw_p1_poisoned connect issue_slots[19].out_uop.iw_state, slots_19.io.out_uop.iw_state connect issue_slots[19].out_uop.ctrl.is_std, slots_19.io.out_uop.ctrl.is_std connect issue_slots[19].out_uop.ctrl.is_sta, slots_19.io.out_uop.ctrl.is_sta connect issue_slots[19].out_uop.ctrl.is_load, slots_19.io.out_uop.ctrl.is_load connect issue_slots[19].out_uop.ctrl.csr_cmd, slots_19.io.out_uop.ctrl.csr_cmd connect issue_slots[19].out_uop.ctrl.fcn_dw, slots_19.io.out_uop.ctrl.fcn_dw connect issue_slots[19].out_uop.ctrl.op_fcn, slots_19.io.out_uop.ctrl.op_fcn connect issue_slots[19].out_uop.ctrl.imm_sel, slots_19.io.out_uop.ctrl.imm_sel connect issue_slots[19].out_uop.ctrl.op2_sel, slots_19.io.out_uop.ctrl.op2_sel connect issue_slots[19].out_uop.ctrl.op1_sel, slots_19.io.out_uop.ctrl.op1_sel connect issue_slots[19].out_uop.ctrl.br_type, slots_19.io.out_uop.ctrl.br_type connect issue_slots[19].out_uop.fu_code, slots_19.io.out_uop.fu_code connect issue_slots[19].out_uop.iq_type, slots_19.io.out_uop.iq_type connect issue_slots[19].out_uop.debug_pc, slots_19.io.out_uop.debug_pc connect issue_slots[19].out_uop.is_rvc, slots_19.io.out_uop.is_rvc connect issue_slots[19].out_uop.debug_inst, slots_19.io.out_uop.debug_inst connect issue_slots[19].out_uop.inst, slots_19.io.out_uop.inst connect issue_slots[19].out_uop.uopc, slots_19.io.out_uop.uopc connect slots_19.io.in_uop.bits.debug_tsrc, issue_slots[19].in_uop.bits.debug_tsrc connect slots_19.io.in_uop.bits.debug_fsrc, issue_slots[19].in_uop.bits.debug_fsrc connect slots_19.io.in_uop.bits.bp_xcpt_if, issue_slots[19].in_uop.bits.bp_xcpt_if connect slots_19.io.in_uop.bits.bp_debug_if, issue_slots[19].in_uop.bits.bp_debug_if connect slots_19.io.in_uop.bits.xcpt_ma_if, issue_slots[19].in_uop.bits.xcpt_ma_if connect slots_19.io.in_uop.bits.xcpt_ae_if, issue_slots[19].in_uop.bits.xcpt_ae_if connect slots_19.io.in_uop.bits.xcpt_pf_if, issue_slots[19].in_uop.bits.xcpt_pf_if connect slots_19.io.in_uop.bits.fp_single, issue_slots[19].in_uop.bits.fp_single connect slots_19.io.in_uop.bits.fp_val, issue_slots[19].in_uop.bits.fp_val connect slots_19.io.in_uop.bits.frs3_en, issue_slots[19].in_uop.bits.frs3_en connect slots_19.io.in_uop.bits.lrs2_rtype, issue_slots[19].in_uop.bits.lrs2_rtype connect slots_19.io.in_uop.bits.lrs1_rtype, issue_slots[19].in_uop.bits.lrs1_rtype connect slots_19.io.in_uop.bits.dst_rtype, issue_slots[19].in_uop.bits.dst_rtype connect slots_19.io.in_uop.bits.ldst_val, issue_slots[19].in_uop.bits.ldst_val connect slots_19.io.in_uop.bits.lrs3, issue_slots[19].in_uop.bits.lrs3 connect slots_19.io.in_uop.bits.lrs2, issue_slots[19].in_uop.bits.lrs2 connect slots_19.io.in_uop.bits.lrs1, issue_slots[19].in_uop.bits.lrs1 connect slots_19.io.in_uop.bits.ldst, issue_slots[19].in_uop.bits.ldst connect slots_19.io.in_uop.bits.ldst_is_rs1, issue_slots[19].in_uop.bits.ldst_is_rs1 connect slots_19.io.in_uop.bits.flush_on_commit, issue_slots[19].in_uop.bits.flush_on_commit connect slots_19.io.in_uop.bits.is_unique, issue_slots[19].in_uop.bits.is_unique connect slots_19.io.in_uop.bits.is_sys_pc2epc, issue_slots[19].in_uop.bits.is_sys_pc2epc connect slots_19.io.in_uop.bits.uses_stq, issue_slots[19].in_uop.bits.uses_stq connect slots_19.io.in_uop.bits.uses_ldq, issue_slots[19].in_uop.bits.uses_ldq connect slots_19.io.in_uop.bits.is_amo, issue_slots[19].in_uop.bits.is_amo connect slots_19.io.in_uop.bits.is_fencei, issue_slots[19].in_uop.bits.is_fencei connect slots_19.io.in_uop.bits.is_fence, issue_slots[19].in_uop.bits.is_fence connect slots_19.io.in_uop.bits.mem_signed, issue_slots[19].in_uop.bits.mem_signed connect slots_19.io.in_uop.bits.mem_size, issue_slots[19].in_uop.bits.mem_size connect slots_19.io.in_uop.bits.mem_cmd, issue_slots[19].in_uop.bits.mem_cmd connect slots_19.io.in_uop.bits.bypassable, issue_slots[19].in_uop.bits.bypassable connect slots_19.io.in_uop.bits.exc_cause, issue_slots[19].in_uop.bits.exc_cause connect slots_19.io.in_uop.bits.exception, issue_slots[19].in_uop.bits.exception connect slots_19.io.in_uop.bits.stale_pdst, issue_slots[19].in_uop.bits.stale_pdst connect slots_19.io.in_uop.bits.ppred_busy, issue_slots[19].in_uop.bits.ppred_busy connect slots_19.io.in_uop.bits.prs3_busy, issue_slots[19].in_uop.bits.prs3_busy connect slots_19.io.in_uop.bits.prs2_busy, issue_slots[19].in_uop.bits.prs2_busy connect slots_19.io.in_uop.bits.prs1_busy, issue_slots[19].in_uop.bits.prs1_busy connect slots_19.io.in_uop.bits.ppred, issue_slots[19].in_uop.bits.ppred connect slots_19.io.in_uop.bits.prs3, issue_slots[19].in_uop.bits.prs3 connect slots_19.io.in_uop.bits.prs2, issue_slots[19].in_uop.bits.prs2 connect slots_19.io.in_uop.bits.prs1, issue_slots[19].in_uop.bits.prs1 connect slots_19.io.in_uop.bits.pdst, issue_slots[19].in_uop.bits.pdst connect slots_19.io.in_uop.bits.rxq_idx, issue_slots[19].in_uop.bits.rxq_idx connect slots_19.io.in_uop.bits.stq_idx, issue_slots[19].in_uop.bits.stq_idx connect slots_19.io.in_uop.bits.ldq_idx, issue_slots[19].in_uop.bits.ldq_idx connect slots_19.io.in_uop.bits.rob_idx, issue_slots[19].in_uop.bits.rob_idx connect slots_19.io.in_uop.bits.csr_addr, issue_slots[19].in_uop.bits.csr_addr connect slots_19.io.in_uop.bits.imm_packed, issue_slots[19].in_uop.bits.imm_packed connect slots_19.io.in_uop.bits.taken, issue_slots[19].in_uop.bits.taken connect slots_19.io.in_uop.bits.pc_lob, issue_slots[19].in_uop.bits.pc_lob connect slots_19.io.in_uop.bits.edge_inst, issue_slots[19].in_uop.bits.edge_inst connect slots_19.io.in_uop.bits.ftq_idx, issue_slots[19].in_uop.bits.ftq_idx connect slots_19.io.in_uop.bits.br_tag, issue_slots[19].in_uop.bits.br_tag connect slots_19.io.in_uop.bits.br_mask, issue_slots[19].in_uop.bits.br_mask connect slots_19.io.in_uop.bits.is_sfb, issue_slots[19].in_uop.bits.is_sfb connect slots_19.io.in_uop.bits.is_jal, issue_slots[19].in_uop.bits.is_jal connect slots_19.io.in_uop.bits.is_jalr, issue_slots[19].in_uop.bits.is_jalr connect slots_19.io.in_uop.bits.is_br, issue_slots[19].in_uop.bits.is_br connect slots_19.io.in_uop.bits.iw_p2_poisoned, issue_slots[19].in_uop.bits.iw_p2_poisoned connect slots_19.io.in_uop.bits.iw_p1_poisoned, issue_slots[19].in_uop.bits.iw_p1_poisoned connect slots_19.io.in_uop.bits.iw_state, issue_slots[19].in_uop.bits.iw_state connect slots_19.io.in_uop.bits.ctrl.is_std, issue_slots[19].in_uop.bits.ctrl.is_std connect slots_19.io.in_uop.bits.ctrl.is_sta, issue_slots[19].in_uop.bits.ctrl.is_sta connect slots_19.io.in_uop.bits.ctrl.is_load, issue_slots[19].in_uop.bits.ctrl.is_load connect slots_19.io.in_uop.bits.ctrl.csr_cmd, issue_slots[19].in_uop.bits.ctrl.csr_cmd connect slots_19.io.in_uop.bits.ctrl.fcn_dw, issue_slots[19].in_uop.bits.ctrl.fcn_dw connect slots_19.io.in_uop.bits.ctrl.op_fcn, issue_slots[19].in_uop.bits.ctrl.op_fcn connect slots_19.io.in_uop.bits.ctrl.imm_sel, issue_slots[19].in_uop.bits.ctrl.imm_sel connect slots_19.io.in_uop.bits.ctrl.op2_sel, issue_slots[19].in_uop.bits.ctrl.op2_sel connect slots_19.io.in_uop.bits.ctrl.op1_sel, issue_slots[19].in_uop.bits.ctrl.op1_sel connect slots_19.io.in_uop.bits.ctrl.br_type, issue_slots[19].in_uop.bits.ctrl.br_type connect slots_19.io.in_uop.bits.fu_code, issue_slots[19].in_uop.bits.fu_code connect slots_19.io.in_uop.bits.iq_type, issue_slots[19].in_uop.bits.iq_type connect slots_19.io.in_uop.bits.debug_pc, issue_slots[19].in_uop.bits.debug_pc connect slots_19.io.in_uop.bits.is_rvc, issue_slots[19].in_uop.bits.is_rvc connect slots_19.io.in_uop.bits.debug_inst, issue_slots[19].in_uop.bits.debug_inst connect slots_19.io.in_uop.bits.inst, issue_slots[19].in_uop.bits.inst connect slots_19.io.in_uop.bits.uopc, issue_slots[19].in_uop.bits.uopc connect slots_19.io.in_uop.valid, issue_slots[19].in_uop.valid connect slots_19.io.spec_ld_wakeup[0].bits, issue_slots[19].spec_ld_wakeup[0].bits connect slots_19.io.spec_ld_wakeup[0].valid, issue_slots[19].spec_ld_wakeup[0].valid connect slots_19.io.pred_wakeup_port.bits, issue_slots[19].pred_wakeup_port.bits connect slots_19.io.pred_wakeup_port.valid, issue_slots[19].pred_wakeup_port.valid connect slots_19.io.wakeup_ports[0].bits.poisoned, issue_slots[19].wakeup_ports[0].bits.poisoned connect slots_19.io.wakeup_ports[0].bits.pdst, issue_slots[19].wakeup_ports[0].bits.pdst connect slots_19.io.wakeup_ports[0].valid, issue_slots[19].wakeup_ports[0].valid connect slots_19.io.wakeup_ports[1].bits.poisoned, issue_slots[19].wakeup_ports[1].bits.poisoned connect slots_19.io.wakeup_ports[1].bits.pdst, issue_slots[19].wakeup_ports[1].bits.pdst connect slots_19.io.wakeup_ports[1].valid, issue_slots[19].wakeup_ports[1].valid connect slots_19.io.wakeup_ports[2].bits.poisoned, issue_slots[19].wakeup_ports[2].bits.poisoned connect slots_19.io.wakeup_ports[2].bits.pdst, issue_slots[19].wakeup_ports[2].bits.pdst connect slots_19.io.wakeup_ports[2].valid, issue_slots[19].wakeup_ports[2].valid connect slots_19.io.wakeup_ports[3].bits.poisoned, issue_slots[19].wakeup_ports[3].bits.poisoned connect slots_19.io.wakeup_ports[3].bits.pdst, issue_slots[19].wakeup_ports[3].bits.pdst connect slots_19.io.wakeup_ports[3].valid, issue_slots[19].wakeup_ports[3].valid connect slots_19.io.wakeup_ports[4].bits.poisoned, issue_slots[19].wakeup_ports[4].bits.poisoned connect slots_19.io.wakeup_ports[4].bits.pdst, issue_slots[19].wakeup_ports[4].bits.pdst connect slots_19.io.wakeup_ports[4].valid, issue_slots[19].wakeup_ports[4].valid connect slots_19.io.wakeup_ports[5].bits.poisoned, issue_slots[19].wakeup_ports[5].bits.poisoned connect slots_19.io.wakeup_ports[5].bits.pdst, issue_slots[19].wakeup_ports[5].bits.pdst connect slots_19.io.wakeup_ports[5].valid, issue_slots[19].wakeup_ports[5].valid connect slots_19.io.wakeup_ports[6].bits.poisoned, issue_slots[19].wakeup_ports[6].bits.poisoned connect slots_19.io.wakeup_ports[6].bits.pdst, issue_slots[19].wakeup_ports[6].bits.pdst connect slots_19.io.wakeup_ports[6].valid, issue_slots[19].wakeup_ports[6].valid connect slots_19.io.ldspec_miss, issue_slots[19].ldspec_miss connect slots_19.io.clear, issue_slots[19].clear connect slots_19.io.kill, issue_slots[19].kill connect slots_19.io.brupdate.b2.target_offset, issue_slots[19].brupdate.b2.target_offset connect slots_19.io.brupdate.b2.jalr_target, issue_slots[19].brupdate.b2.jalr_target connect slots_19.io.brupdate.b2.pc_sel, issue_slots[19].brupdate.b2.pc_sel connect slots_19.io.brupdate.b2.cfi_type, issue_slots[19].brupdate.b2.cfi_type connect slots_19.io.brupdate.b2.taken, issue_slots[19].brupdate.b2.taken connect slots_19.io.brupdate.b2.mispredict, issue_slots[19].brupdate.b2.mispredict connect slots_19.io.brupdate.b2.valid, issue_slots[19].brupdate.b2.valid connect slots_19.io.brupdate.b2.uop.debug_tsrc, issue_slots[19].brupdate.b2.uop.debug_tsrc connect slots_19.io.brupdate.b2.uop.debug_fsrc, issue_slots[19].brupdate.b2.uop.debug_fsrc connect slots_19.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[19].brupdate.b2.uop.bp_xcpt_if connect slots_19.io.brupdate.b2.uop.bp_debug_if, issue_slots[19].brupdate.b2.uop.bp_debug_if connect slots_19.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[19].brupdate.b2.uop.xcpt_ma_if connect slots_19.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[19].brupdate.b2.uop.xcpt_ae_if connect slots_19.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[19].brupdate.b2.uop.xcpt_pf_if connect slots_19.io.brupdate.b2.uop.fp_single, issue_slots[19].brupdate.b2.uop.fp_single connect slots_19.io.brupdate.b2.uop.fp_val, issue_slots[19].brupdate.b2.uop.fp_val connect slots_19.io.brupdate.b2.uop.frs3_en, issue_slots[19].brupdate.b2.uop.frs3_en connect slots_19.io.brupdate.b2.uop.lrs2_rtype, issue_slots[19].brupdate.b2.uop.lrs2_rtype connect slots_19.io.brupdate.b2.uop.lrs1_rtype, issue_slots[19].brupdate.b2.uop.lrs1_rtype connect slots_19.io.brupdate.b2.uop.dst_rtype, issue_slots[19].brupdate.b2.uop.dst_rtype connect slots_19.io.brupdate.b2.uop.ldst_val, issue_slots[19].brupdate.b2.uop.ldst_val connect slots_19.io.brupdate.b2.uop.lrs3, issue_slots[19].brupdate.b2.uop.lrs3 connect slots_19.io.brupdate.b2.uop.lrs2, issue_slots[19].brupdate.b2.uop.lrs2 connect slots_19.io.brupdate.b2.uop.lrs1, issue_slots[19].brupdate.b2.uop.lrs1 connect slots_19.io.brupdate.b2.uop.ldst, issue_slots[19].brupdate.b2.uop.ldst connect slots_19.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[19].brupdate.b2.uop.ldst_is_rs1 connect slots_19.io.brupdate.b2.uop.flush_on_commit, issue_slots[19].brupdate.b2.uop.flush_on_commit connect slots_19.io.brupdate.b2.uop.is_unique, issue_slots[19].brupdate.b2.uop.is_unique connect slots_19.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[19].brupdate.b2.uop.is_sys_pc2epc connect slots_19.io.brupdate.b2.uop.uses_stq, issue_slots[19].brupdate.b2.uop.uses_stq connect slots_19.io.brupdate.b2.uop.uses_ldq, issue_slots[19].brupdate.b2.uop.uses_ldq connect slots_19.io.brupdate.b2.uop.is_amo, issue_slots[19].brupdate.b2.uop.is_amo connect slots_19.io.brupdate.b2.uop.is_fencei, issue_slots[19].brupdate.b2.uop.is_fencei connect slots_19.io.brupdate.b2.uop.is_fence, issue_slots[19].brupdate.b2.uop.is_fence connect slots_19.io.brupdate.b2.uop.mem_signed, issue_slots[19].brupdate.b2.uop.mem_signed connect slots_19.io.brupdate.b2.uop.mem_size, issue_slots[19].brupdate.b2.uop.mem_size connect slots_19.io.brupdate.b2.uop.mem_cmd, issue_slots[19].brupdate.b2.uop.mem_cmd connect slots_19.io.brupdate.b2.uop.bypassable, issue_slots[19].brupdate.b2.uop.bypassable connect slots_19.io.brupdate.b2.uop.exc_cause, issue_slots[19].brupdate.b2.uop.exc_cause connect slots_19.io.brupdate.b2.uop.exception, issue_slots[19].brupdate.b2.uop.exception connect slots_19.io.brupdate.b2.uop.stale_pdst, issue_slots[19].brupdate.b2.uop.stale_pdst connect slots_19.io.brupdate.b2.uop.ppred_busy, issue_slots[19].brupdate.b2.uop.ppred_busy connect slots_19.io.brupdate.b2.uop.prs3_busy, issue_slots[19].brupdate.b2.uop.prs3_busy connect slots_19.io.brupdate.b2.uop.prs2_busy, issue_slots[19].brupdate.b2.uop.prs2_busy connect slots_19.io.brupdate.b2.uop.prs1_busy, issue_slots[19].brupdate.b2.uop.prs1_busy connect slots_19.io.brupdate.b2.uop.ppred, issue_slots[19].brupdate.b2.uop.ppred connect slots_19.io.brupdate.b2.uop.prs3, issue_slots[19].brupdate.b2.uop.prs3 connect slots_19.io.brupdate.b2.uop.prs2, issue_slots[19].brupdate.b2.uop.prs2 connect slots_19.io.brupdate.b2.uop.prs1, issue_slots[19].brupdate.b2.uop.prs1 connect slots_19.io.brupdate.b2.uop.pdst, issue_slots[19].brupdate.b2.uop.pdst connect slots_19.io.brupdate.b2.uop.rxq_idx, issue_slots[19].brupdate.b2.uop.rxq_idx connect slots_19.io.brupdate.b2.uop.stq_idx, issue_slots[19].brupdate.b2.uop.stq_idx connect slots_19.io.brupdate.b2.uop.ldq_idx, issue_slots[19].brupdate.b2.uop.ldq_idx connect slots_19.io.brupdate.b2.uop.rob_idx, issue_slots[19].brupdate.b2.uop.rob_idx connect slots_19.io.brupdate.b2.uop.csr_addr, issue_slots[19].brupdate.b2.uop.csr_addr connect slots_19.io.brupdate.b2.uop.imm_packed, issue_slots[19].brupdate.b2.uop.imm_packed connect slots_19.io.brupdate.b2.uop.taken, issue_slots[19].brupdate.b2.uop.taken connect slots_19.io.brupdate.b2.uop.pc_lob, issue_slots[19].brupdate.b2.uop.pc_lob connect slots_19.io.brupdate.b2.uop.edge_inst, issue_slots[19].brupdate.b2.uop.edge_inst connect slots_19.io.brupdate.b2.uop.ftq_idx, issue_slots[19].brupdate.b2.uop.ftq_idx connect slots_19.io.brupdate.b2.uop.br_tag, issue_slots[19].brupdate.b2.uop.br_tag connect slots_19.io.brupdate.b2.uop.br_mask, issue_slots[19].brupdate.b2.uop.br_mask connect slots_19.io.brupdate.b2.uop.is_sfb, issue_slots[19].brupdate.b2.uop.is_sfb connect slots_19.io.brupdate.b2.uop.is_jal, issue_slots[19].brupdate.b2.uop.is_jal connect slots_19.io.brupdate.b2.uop.is_jalr, issue_slots[19].brupdate.b2.uop.is_jalr connect slots_19.io.brupdate.b2.uop.is_br, issue_slots[19].brupdate.b2.uop.is_br connect slots_19.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[19].brupdate.b2.uop.iw_p2_poisoned connect slots_19.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[19].brupdate.b2.uop.iw_p1_poisoned connect slots_19.io.brupdate.b2.uop.iw_state, issue_slots[19].brupdate.b2.uop.iw_state connect slots_19.io.brupdate.b2.uop.ctrl.is_std, issue_slots[19].brupdate.b2.uop.ctrl.is_std connect slots_19.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[19].brupdate.b2.uop.ctrl.is_sta connect slots_19.io.brupdate.b2.uop.ctrl.is_load, issue_slots[19].brupdate.b2.uop.ctrl.is_load connect slots_19.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[19].brupdate.b2.uop.ctrl.csr_cmd connect slots_19.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[19].brupdate.b2.uop.ctrl.fcn_dw connect slots_19.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[19].brupdate.b2.uop.ctrl.op_fcn connect slots_19.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[19].brupdate.b2.uop.ctrl.imm_sel connect slots_19.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[19].brupdate.b2.uop.ctrl.op2_sel connect slots_19.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[19].brupdate.b2.uop.ctrl.op1_sel connect slots_19.io.brupdate.b2.uop.ctrl.br_type, issue_slots[19].brupdate.b2.uop.ctrl.br_type connect slots_19.io.brupdate.b2.uop.fu_code, issue_slots[19].brupdate.b2.uop.fu_code connect slots_19.io.brupdate.b2.uop.iq_type, issue_slots[19].brupdate.b2.uop.iq_type connect slots_19.io.brupdate.b2.uop.debug_pc, issue_slots[19].brupdate.b2.uop.debug_pc connect slots_19.io.brupdate.b2.uop.is_rvc, issue_slots[19].brupdate.b2.uop.is_rvc connect slots_19.io.brupdate.b2.uop.debug_inst, issue_slots[19].brupdate.b2.uop.debug_inst connect slots_19.io.brupdate.b2.uop.inst, issue_slots[19].brupdate.b2.uop.inst connect slots_19.io.brupdate.b2.uop.uopc, issue_slots[19].brupdate.b2.uop.uopc connect slots_19.io.brupdate.b1.mispredict_mask, issue_slots[19].brupdate.b1.mispredict_mask connect slots_19.io.brupdate.b1.resolve_mask, issue_slots[19].brupdate.b1.resolve_mask connect slots_19.io.grant, issue_slots[19].grant connect issue_slots[19].request_hp, slots_19.io.request_hp connect issue_slots[19].request, slots_19.io.request connect issue_slots[19].will_be_valid, slots_19.io.will_be_valid connect issue_slots[19].valid, slots_19.io.valid connect issue_slots[20].debug.state, slots_20.io.debug.state connect issue_slots[20].debug.ppred, slots_20.io.debug.ppred connect issue_slots[20].debug.p3, slots_20.io.debug.p3 connect issue_slots[20].debug.p2, slots_20.io.debug.p2 connect issue_slots[20].debug.p1, slots_20.io.debug.p1 connect issue_slots[20].uop.debug_tsrc, slots_20.io.uop.debug_tsrc connect issue_slots[20].uop.debug_fsrc, slots_20.io.uop.debug_fsrc connect issue_slots[20].uop.bp_xcpt_if, slots_20.io.uop.bp_xcpt_if connect issue_slots[20].uop.bp_debug_if, slots_20.io.uop.bp_debug_if connect issue_slots[20].uop.xcpt_ma_if, slots_20.io.uop.xcpt_ma_if connect issue_slots[20].uop.xcpt_ae_if, slots_20.io.uop.xcpt_ae_if connect issue_slots[20].uop.xcpt_pf_if, slots_20.io.uop.xcpt_pf_if connect issue_slots[20].uop.fp_single, slots_20.io.uop.fp_single connect issue_slots[20].uop.fp_val, slots_20.io.uop.fp_val connect issue_slots[20].uop.frs3_en, slots_20.io.uop.frs3_en connect issue_slots[20].uop.lrs2_rtype, slots_20.io.uop.lrs2_rtype connect issue_slots[20].uop.lrs1_rtype, slots_20.io.uop.lrs1_rtype connect issue_slots[20].uop.dst_rtype, slots_20.io.uop.dst_rtype connect issue_slots[20].uop.ldst_val, slots_20.io.uop.ldst_val connect issue_slots[20].uop.lrs3, slots_20.io.uop.lrs3 connect issue_slots[20].uop.lrs2, slots_20.io.uop.lrs2 connect issue_slots[20].uop.lrs1, slots_20.io.uop.lrs1 connect issue_slots[20].uop.ldst, slots_20.io.uop.ldst connect issue_slots[20].uop.ldst_is_rs1, slots_20.io.uop.ldst_is_rs1 connect issue_slots[20].uop.flush_on_commit, slots_20.io.uop.flush_on_commit connect issue_slots[20].uop.is_unique, slots_20.io.uop.is_unique connect issue_slots[20].uop.is_sys_pc2epc, slots_20.io.uop.is_sys_pc2epc connect issue_slots[20].uop.uses_stq, slots_20.io.uop.uses_stq connect issue_slots[20].uop.uses_ldq, slots_20.io.uop.uses_ldq connect issue_slots[20].uop.is_amo, slots_20.io.uop.is_amo connect issue_slots[20].uop.is_fencei, slots_20.io.uop.is_fencei connect issue_slots[20].uop.is_fence, slots_20.io.uop.is_fence connect issue_slots[20].uop.mem_signed, slots_20.io.uop.mem_signed connect issue_slots[20].uop.mem_size, slots_20.io.uop.mem_size connect issue_slots[20].uop.mem_cmd, slots_20.io.uop.mem_cmd connect issue_slots[20].uop.bypassable, slots_20.io.uop.bypassable connect issue_slots[20].uop.exc_cause, slots_20.io.uop.exc_cause connect issue_slots[20].uop.exception, slots_20.io.uop.exception connect issue_slots[20].uop.stale_pdst, slots_20.io.uop.stale_pdst connect issue_slots[20].uop.ppred_busy, slots_20.io.uop.ppred_busy connect issue_slots[20].uop.prs3_busy, slots_20.io.uop.prs3_busy connect issue_slots[20].uop.prs2_busy, slots_20.io.uop.prs2_busy connect issue_slots[20].uop.prs1_busy, slots_20.io.uop.prs1_busy connect issue_slots[20].uop.ppred, slots_20.io.uop.ppred connect issue_slots[20].uop.prs3, slots_20.io.uop.prs3 connect issue_slots[20].uop.prs2, slots_20.io.uop.prs2 connect issue_slots[20].uop.prs1, slots_20.io.uop.prs1 connect issue_slots[20].uop.pdst, slots_20.io.uop.pdst connect issue_slots[20].uop.rxq_idx, slots_20.io.uop.rxq_idx connect issue_slots[20].uop.stq_idx, slots_20.io.uop.stq_idx connect issue_slots[20].uop.ldq_idx, slots_20.io.uop.ldq_idx connect issue_slots[20].uop.rob_idx, slots_20.io.uop.rob_idx connect issue_slots[20].uop.csr_addr, slots_20.io.uop.csr_addr connect issue_slots[20].uop.imm_packed, slots_20.io.uop.imm_packed connect issue_slots[20].uop.taken, slots_20.io.uop.taken connect issue_slots[20].uop.pc_lob, slots_20.io.uop.pc_lob connect issue_slots[20].uop.edge_inst, slots_20.io.uop.edge_inst connect issue_slots[20].uop.ftq_idx, slots_20.io.uop.ftq_idx connect issue_slots[20].uop.br_tag, slots_20.io.uop.br_tag connect issue_slots[20].uop.br_mask, slots_20.io.uop.br_mask connect issue_slots[20].uop.is_sfb, slots_20.io.uop.is_sfb connect issue_slots[20].uop.is_jal, slots_20.io.uop.is_jal connect issue_slots[20].uop.is_jalr, slots_20.io.uop.is_jalr connect issue_slots[20].uop.is_br, slots_20.io.uop.is_br connect issue_slots[20].uop.iw_p2_poisoned, slots_20.io.uop.iw_p2_poisoned connect issue_slots[20].uop.iw_p1_poisoned, slots_20.io.uop.iw_p1_poisoned connect issue_slots[20].uop.iw_state, slots_20.io.uop.iw_state connect issue_slots[20].uop.ctrl.is_std, slots_20.io.uop.ctrl.is_std connect issue_slots[20].uop.ctrl.is_sta, slots_20.io.uop.ctrl.is_sta connect issue_slots[20].uop.ctrl.is_load, slots_20.io.uop.ctrl.is_load connect issue_slots[20].uop.ctrl.csr_cmd, slots_20.io.uop.ctrl.csr_cmd connect issue_slots[20].uop.ctrl.fcn_dw, slots_20.io.uop.ctrl.fcn_dw connect issue_slots[20].uop.ctrl.op_fcn, slots_20.io.uop.ctrl.op_fcn connect issue_slots[20].uop.ctrl.imm_sel, slots_20.io.uop.ctrl.imm_sel connect issue_slots[20].uop.ctrl.op2_sel, slots_20.io.uop.ctrl.op2_sel connect issue_slots[20].uop.ctrl.op1_sel, slots_20.io.uop.ctrl.op1_sel connect issue_slots[20].uop.ctrl.br_type, slots_20.io.uop.ctrl.br_type connect issue_slots[20].uop.fu_code, slots_20.io.uop.fu_code connect issue_slots[20].uop.iq_type, slots_20.io.uop.iq_type connect issue_slots[20].uop.debug_pc, slots_20.io.uop.debug_pc connect issue_slots[20].uop.is_rvc, slots_20.io.uop.is_rvc connect issue_slots[20].uop.debug_inst, slots_20.io.uop.debug_inst connect issue_slots[20].uop.inst, slots_20.io.uop.inst connect issue_slots[20].uop.uopc, slots_20.io.uop.uopc connect issue_slots[20].out_uop.debug_tsrc, slots_20.io.out_uop.debug_tsrc connect issue_slots[20].out_uop.debug_fsrc, slots_20.io.out_uop.debug_fsrc connect issue_slots[20].out_uop.bp_xcpt_if, slots_20.io.out_uop.bp_xcpt_if connect issue_slots[20].out_uop.bp_debug_if, slots_20.io.out_uop.bp_debug_if connect issue_slots[20].out_uop.xcpt_ma_if, slots_20.io.out_uop.xcpt_ma_if connect issue_slots[20].out_uop.xcpt_ae_if, slots_20.io.out_uop.xcpt_ae_if connect issue_slots[20].out_uop.xcpt_pf_if, slots_20.io.out_uop.xcpt_pf_if connect issue_slots[20].out_uop.fp_single, slots_20.io.out_uop.fp_single connect issue_slots[20].out_uop.fp_val, slots_20.io.out_uop.fp_val connect issue_slots[20].out_uop.frs3_en, slots_20.io.out_uop.frs3_en connect issue_slots[20].out_uop.lrs2_rtype, slots_20.io.out_uop.lrs2_rtype connect issue_slots[20].out_uop.lrs1_rtype, slots_20.io.out_uop.lrs1_rtype connect issue_slots[20].out_uop.dst_rtype, slots_20.io.out_uop.dst_rtype connect issue_slots[20].out_uop.ldst_val, slots_20.io.out_uop.ldst_val connect issue_slots[20].out_uop.lrs3, slots_20.io.out_uop.lrs3 connect issue_slots[20].out_uop.lrs2, slots_20.io.out_uop.lrs2 connect issue_slots[20].out_uop.lrs1, slots_20.io.out_uop.lrs1 connect issue_slots[20].out_uop.ldst, slots_20.io.out_uop.ldst connect issue_slots[20].out_uop.ldst_is_rs1, slots_20.io.out_uop.ldst_is_rs1 connect issue_slots[20].out_uop.flush_on_commit, slots_20.io.out_uop.flush_on_commit connect issue_slots[20].out_uop.is_unique, slots_20.io.out_uop.is_unique connect issue_slots[20].out_uop.is_sys_pc2epc, slots_20.io.out_uop.is_sys_pc2epc connect issue_slots[20].out_uop.uses_stq, slots_20.io.out_uop.uses_stq connect issue_slots[20].out_uop.uses_ldq, slots_20.io.out_uop.uses_ldq connect issue_slots[20].out_uop.is_amo, slots_20.io.out_uop.is_amo connect issue_slots[20].out_uop.is_fencei, slots_20.io.out_uop.is_fencei connect issue_slots[20].out_uop.is_fence, slots_20.io.out_uop.is_fence connect issue_slots[20].out_uop.mem_signed, slots_20.io.out_uop.mem_signed connect issue_slots[20].out_uop.mem_size, slots_20.io.out_uop.mem_size connect issue_slots[20].out_uop.mem_cmd, slots_20.io.out_uop.mem_cmd connect issue_slots[20].out_uop.bypassable, slots_20.io.out_uop.bypassable connect issue_slots[20].out_uop.exc_cause, slots_20.io.out_uop.exc_cause connect issue_slots[20].out_uop.exception, slots_20.io.out_uop.exception connect issue_slots[20].out_uop.stale_pdst, slots_20.io.out_uop.stale_pdst connect issue_slots[20].out_uop.ppred_busy, slots_20.io.out_uop.ppred_busy connect issue_slots[20].out_uop.prs3_busy, slots_20.io.out_uop.prs3_busy connect issue_slots[20].out_uop.prs2_busy, slots_20.io.out_uop.prs2_busy connect issue_slots[20].out_uop.prs1_busy, slots_20.io.out_uop.prs1_busy connect issue_slots[20].out_uop.ppred, slots_20.io.out_uop.ppred connect issue_slots[20].out_uop.prs3, slots_20.io.out_uop.prs3 connect issue_slots[20].out_uop.prs2, slots_20.io.out_uop.prs2 connect issue_slots[20].out_uop.prs1, slots_20.io.out_uop.prs1 connect issue_slots[20].out_uop.pdst, slots_20.io.out_uop.pdst connect issue_slots[20].out_uop.rxq_idx, slots_20.io.out_uop.rxq_idx connect issue_slots[20].out_uop.stq_idx, slots_20.io.out_uop.stq_idx connect issue_slots[20].out_uop.ldq_idx, slots_20.io.out_uop.ldq_idx connect issue_slots[20].out_uop.rob_idx, slots_20.io.out_uop.rob_idx connect issue_slots[20].out_uop.csr_addr, slots_20.io.out_uop.csr_addr connect issue_slots[20].out_uop.imm_packed, slots_20.io.out_uop.imm_packed connect issue_slots[20].out_uop.taken, slots_20.io.out_uop.taken connect issue_slots[20].out_uop.pc_lob, slots_20.io.out_uop.pc_lob connect issue_slots[20].out_uop.edge_inst, slots_20.io.out_uop.edge_inst connect issue_slots[20].out_uop.ftq_idx, slots_20.io.out_uop.ftq_idx connect issue_slots[20].out_uop.br_tag, slots_20.io.out_uop.br_tag connect issue_slots[20].out_uop.br_mask, slots_20.io.out_uop.br_mask connect issue_slots[20].out_uop.is_sfb, slots_20.io.out_uop.is_sfb connect issue_slots[20].out_uop.is_jal, slots_20.io.out_uop.is_jal connect issue_slots[20].out_uop.is_jalr, slots_20.io.out_uop.is_jalr connect issue_slots[20].out_uop.is_br, slots_20.io.out_uop.is_br connect issue_slots[20].out_uop.iw_p2_poisoned, slots_20.io.out_uop.iw_p2_poisoned connect issue_slots[20].out_uop.iw_p1_poisoned, slots_20.io.out_uop.iw_p1_poisoned connect issue_slots[20].out_uop.iw_state, slots_20.io.out_uop.iw_state connect issue_slots[20].out_uop.ctrl.is_std, slots_20.io.out_uop.ctrl.is_std connect issue_slots[20].out_uop.ctrl.is_sta, slots_20.io.out_uop.ctrl.is_sta connect issue_slots[20].out_uop.ctrl.is_load, slots_20.io.out_uop.ctrl.is_load connect issue_slots[20].out_uop.ctrl.csr_cmd, slots_20.io.out_uop.ctrl.csr_cmd connect issue_slots[20].out_uop.ctrl.fcn_dw, slots_20.io.out_uop.ctrl.fcn_dw connect issue_slots[20].out_uop.ctrl.op_fcn, slots_20.io.out_uop.ctrl.op_fcn connect issue_slots[20].out_uop.ctrl.imm_sel, slots_20.io.out_uop.ctrl.imm_sel connect issue_slots[20].out_uop.ctrl.op2_sel, slots_20.io.out_uop.ctrl.op2_sel connect issue_slots[20].out_uop.ctrl.op1_sel, slots_20.io.out_uop.ctrl.op1_sel connect issue_slots[20].out_uop.ctrl.br_type, slots_20.io.out_uop.ctrl.br_type connect issue_slots[20].out_uop.fu_code, slots_20.io.out_uop.fu_code connect issue_slots[20].out_uop.iq_type, slots_20.io.out_uop.iq_type connect issue_slots[20].out_uop.debug_pc, slots_20.io.out_uop.debug_pc connect issue_slots[20].out_uop.is_rvc, slots_20.io.out_uop.is_rvc connect issue_slots[20].out_uop.debug_inst, slots_20.io.out_uop.debug_inst connect issue_slots[20].out_uop.inst, slots_20.io.out_uop.inst connect issue_slots[20].out_uop.uopc, slots_20.io.out_uop.uopc connect slots_20.io.in_uop.bits.debug_tsrc, issue_slots[20].in_uop.bits.debug_tsrc connect slots_20.io.in_uop.bits.debug_fsrc, issue_slots[20].in_uop.bits.debug_fsrc connect slots_20.io.in_uop.bits.bp_xcpt_if, issue_slots[20].in_uop.bits.bp_xcpt_if connect slots_20.io.in_uop.bits.bp_debug_if, issue_slots[20].in_uop.bits.bp_debug_if connect slots_20.io.in_uop.bits.xcpt_ma_if, issue_slots[20].in_uop.bits.xcpt_ma_if connect slots_20.io.in_uop.bits.xcpt_ae_if, issue_slots[20].in_uop.bits.xcpt_ae_if connect slots_20.io.in_uop.bits.xcpt_pf_if, issue_slots[20].in_uop.bits.xcpt_pf_if connect slots_20.io.in_uop.bits.fp_single, issue_slots[20].in_uop.bits.fp_single connect slots_20.io.in_uop.bits.fp_val, issue_slots[20].in_uop.bits.fp_val connect slots_20.io.in_uop.bits.frs3_en, issue_slots[20].in_uop.bits.frs3_en connect slots_20.io.in_uop.bits.lrs2_rtype, issue_slots[20].in_uop.bits.lrs2_rtype connect slots_20.io.in_uop.bits.lrs1_rtype, issue_slots[20].in_uop.bits.lrs1_rtype connect slots_20.io.in_uop.bits.dst_rtype, issue_slots[20].in_uop.bits.dst_rtype connect slots_20.io.in_uop.bits.ldst_val, issue_slots[20].in_uop.bits.ldst_val connect slots_20.io.in_uop.bits.lrs3, issue_slots[20].in_uop.bits.lrs3 connect slots_20.io.in_uop.bits.lrs2, issue_slots[20].in_uop.bits.lrs2 connect slots_20.io.in_uop.bits.lrs1, issue_slots[20].in_uop.bits.lrs1 connect slots_20.io.in_uop.bits.ldst, issue_slots[20].in_uop.bits.ldst connect slots_20.io.in_uop.bits.ldst_is_rs1, issue_slots[20].in_uop.bits.ldst_is_rs1 connect slots_20.io.in_uop.bits.flush_on_commit, issue_slots[20].in_uop.bits.flush_on_commit connect slots_20.io.in_uop.bits.is_unique, issue_slots[20].in_uop.bits.is_unique connect slots_20.io.in_uop.bits.is_sys_pc2epc, issue_slots[20].in_uop.bits.is_sys_pc2epc connect slots_20.io.in_uop.bits.uses_stq, issue_slots[20].in_uop.bits.uses_stq connect slots_20.io.in_uop.bits.uses_ldq, issue_slots[20].in_uop.bits.uses_ldq connect slots_20.io.in_uop.bits.is_amo, issue_slots[20].in_uop.bits.is_amo connect slots_20.io.in_uop.bits.is_fencei, issue_slots[20].in_uop.bits.is_fencei connect slots_20.io.in_uop.bits.is_fence, issue_slots[20].in_uop.bits.is_fence connect slots_20.io.in_uop.bits.mem_signed, issue_slots[20].in_uop.bits.mem_signed connect slots_20.io.in_uop.bits.mem_size, issue_slots[20].in_uop.bits.mem_size connect slots_20.io.in_uop.bits.mem_cmd, issue_slots[20].in_uop.bits.mem_cmd connect slots_20.io.in_uop.bits.bypassable, issue_slots[20].in_uop.bits.bypassable connect slots_20.io.in_uop.bits.exc_cause, issue_slots[20].in_uop.bits.exc_cause connect slots_20.io.in_uop.bits.exception, issue_slots[20].in_uop.bits.exception connect slots_20.io.in_uop.bits.stale_pdst, issue_slots[20].in_uop.bits.stale_pdst connect slots_20.io.in_uop.bits.ppred_busy, issue_slots[20].in_uop.bits.ppred_busy connect slots_20.io.in_uop.bits.prs3_busy, issue_slots[20].in_uop.bits.prs3_busy connect slots_20.io.in_uop.bits.prs2_busy, issue_slots[20].in_uop.bits.prs2_busy connect slots_20.io.in_uop.bits.prs1_busy, issue_slots[20].in_uop.bits.prs1_busy connect slots_20.io.in_uop.bits.ppred, issue_slots[20].in_uop.bits.ppred connect slots_20.io.in_uop.bits.prs3, issue_slots[20].in_uop.bits.prs3 connect slots_20.io.in_uop.bits.prs2, issue_slots[20].in_uop.bits.prs2 connect slots_20.io.in_uop.bits.prs1, issue_slots[20].in_uop.bits.prs1 connect slots_20.io.in_uop.bits.pdst, issue_slots[20].in_uop.bits.pdst connect slots_20.io.in_uop.bits.rxq_idx, issue_slots[20].in_uop.bits.rxq_idx connect slots_20.io.in_uop.bits.stq_idx, issue_slots[20].in_uop.bits.stq_idx connect slots_20.io.in_uop.bits.ldq_idx, issue_slots[20].in_uop.bits.ldq_idx connect slots_20.io.in_uop.bits.rob_idx, issue_slots[20].in_uop.bits.rob_idx connect slots_20.io.in_uop.bits.csr_addr, issue_slots[20].in_uop.bits.csr_addr connect slots_20.io.in_uop.bits.imm_packed, issue_slots[20].in_uop.bits.imm_packed connect slots_20.io.in_uop.bits.taken, issue_slots[20].in_uop.bits.taken connect slots_20.io.in_uop.bits.pc_lob, issue_slots[20].in_uop.bits.pc_lob connect slots_20.io.in_uop.bits.edge_inst, issue_slots[20].in_uop.bits.edge_inst connect slots_20.io.in_uop.bits.ftq_idx, issue_slots[20].in_uop.bits.ftq_idx connect slots_20.io.in_uop.bits.br_tag, issue_slots[20].in_uop.bits.br_tag connect slots_20.io.in_uop.bits.br_mask, issue_slots[20].in_uop.bits.br_mask connect slots_20.io.in_uop.bits.is_sfb, issue_slots[20].in_uop.bits.is_sfb connect slots_20.io.in_uop.bits.is_jal, issue_slots[20].in_uop.bits.is_jal connect slots_20.io.in_uop.bits.is_jalr, issue_slots[20].in_uop.bits.is_jalr connect slots_20.io.in_uop.bits.is_br, issue_slots[20].in_uop.bits.is_br connect slots_20.io.in_uop.bits.iw_p2_poisoned, issue_slots[20].in_uop.bits.iw_p2_poisoned connect slots_20.io.in_uop.bits.iw_p1_poisoned, issue_slots[20].in_uop.bits.iw_p1_poisoned connect slots_20.io.in_uop.bits.iw_state, issue_slots[20].in_uop.bits.iw_state connect slots_20.io.in_uop.bits.ctrl.is_std, issue_slots[20].in_uop.bits.ctrl.is_std connect slots_20.io.in_uop.bits.ctrl.is_sta, issue_slots[20].in_uop.bits.ctrl.is_sta connect slots_20.io.in_uop.bits.ctrl.is_load, issue_slots[20].in_uop.bits.ctrl.is_load connect slots_20.io.in_uop.bits.ctrl.csr_cmd, issue_slots[20].in_uop.bits.ctrl.csr_cmd connect slots_20.io.in_uop.bits.ctrl.fcn_dw, issue_slots[20].in_uop.bits.ctrl.fcn_dw connect slots_20.io.in_uop.bits.ctrl.op_fcn, issue_slots[20].in_uop.bits.ctrl.op_fcn connect slots_20.io.in_uop.bits.ctrl.imm_sel, issue_slots[20].in_uop.bits.ctrl.imm_sel connect slots_20.io.in_uop.bits.ctrl.op2_sel, issue_slots[20].in_uop.bits.ctrl.op2_sel connect slots_20.io.in_uop.bits.ctrl.op1_sel, issue_slots[20].in_uop.bits.ctrl.op1_sel connect slots_20.io.in_uop.bits.ctrl.br_type, issue_slots[20].in_uop.bits.ctrl.br_type connect slots_20.io.in_uop.bits.fu_code, issue_slots[20].in_uop.bits.fu_code connect slots_20.io.in_uop.bits.iq_type, issue_slots[20].in_uop.bits.iq_type connect slots_20.io.in_uop.bits.debug_pc, issue_slots[20].in_uop.bits.debug_pc connect slots_20.io.in_uop.bits.is_rvc, issue_slots[20].in_uop.bits.is_rvc connect slots_20.io.in_uop.bits.debug_inst, issue_slots[20].in_uop.bits.debug_inst connect slots_20.io.in_uop.bits.inst, issue_slots[20].in_uop.bits.inst connect slots_20.io.in_uop.bits.uopc, issue_slots[20].in_uop.bits.uopc connect slots_20.io.in_uop.valid, issue_slots[20].in_uop.valid connect slots_20.io.spec_ld_wakeup[0].bits, issue_slots[20].spec_ld_wakeup[0].bits connect slots_20.io.spec_ld_wakeup[0].valid, issue_slots[20].spec_ld_wakeup[0].valid connect slots_20.io.pred_wakeup_port.bits, issue_slots[20].pred_wakeup_port.bits connect slots_20.io.pred_wakeup_port.valid, issue_slots[20].pred_wakeup_port.valid connect slots_20.io.wakeup_ports[0].bits.poisoned, issue_slots[20].wakeup_ports[0].bits.poisoned connect slots_20.io.wakeup_ports[0].bits.pdst, issue_slots[20].wakeup_ports[0].bits.pdst connect slots_20.io.wakeup_ports[0].valid, issue_slots[20].wakeup_ports[0].valid connect slots_20.io.wakeup_ports[1].bits.poisoned, issue_slots[20].wakeup_ports[1].bits.poisoned connect slots_20.io.wakeup_ports[1].bits.pdst, issue_slots[20].wakeup_ports[1].bits.pdst connect slots_20.io.wakeup_ports[1].valid, issue_slots[20].wakeup_ports[1].valid connect slots_20.io.wakeup_ports[2].bits.poisoned, issue_slots[20].wakeup_ports[2].bits.poisoned connect slots_20.io.wakeup_ports[2].bits.pdst, issue_slots[20].wakeup_ports[2].bits.pdst connect slots_20.io.wakeup_ports[2].valid, issue_slots[20].wakeup_ports[2].valid connect slots_20.io.wakeup_ports[3].bits.poisoned, issue_slots[20].wakeup_ports[3].bits.poisoned connect slots_20.io.wakeup_ports[3].bits.pdst, issue_slots[20].wakeup_ports[3].bits.pdst connect slots_20.io.wakeup_ports[3].valid, issue_slots[20].wakeup_ports[3].valid connect slots_20.io.wakeup_ports[4].bits.poisoned, issue_slots[20].wakeup_ports[4].bits.poisoned connect slots_20.io.wakeup_ports[4].bits.pdst, issue_slots[20].wakeup_ports[4].bits.pdst connect slots_20.io.wakeup_ports[4].valid, issue_slots[20].wakeup_ports[4].valid connect slots_20.io.wakeup_ports[5].bits.poisoned, issue_slots[20].wakeup_ports[5].bits.poisoned connect slots_20.io.wakeup_ports[5].bits.pdst, issue_slots[20].wakeup_ports[5].bits.pdst connect slots_20.io.wakeup_ports[5].valid, issue_slots[20].wakeup_ports[5].valid connect slots_20.io.wakeup_ports[6].bits.poisoned, issue_slots[20].wakeup_ports[6].bits.poisoned connect slots_20.io.wakeup_ports[6].bits.pdst, issue_slots[20].wakeup_ports[6].bits.pdst connect slots_20.io.wakeup_ports[6].valid, issue_slots[20].wakeup_ports[6].valid connect slots_20.io.ldspec_miss, issue_slots[20].ldspec_miss connect slots_20.io.clear, issue_slots[20].clear connect slots_20.io.kill, issue_slots[20].kill connect slots_20.io.brupdate.b2.target_offset, issue_slots[20].brupdate.b2.target_offset connect slots_20.io.brupdate.b2.jalr_target, issue_slots[20].brupdate.b2.jalr_target connect slots_20.io.brupdate.b2.pc_sel, issue_slots[20].brupdate.b2.pc_sel connect slots_20.io.brupdate.b2.cfi_type, issue_slots[20].brupdate.b2.cfi_type connect slots_20.io.brupdate.b2.taken, issue_slots[20].brupdate.b2.taken connect slots_20.io.brupdate.b2.mispredict, issue_slots[20].brupdate.b2.mispredict connect slots_20.io.brupdate.b2.valid, issue_slots[20].brupdate.b2.valid connect slots_20.io.brupdate.b2.uop.debug_tsrc, issue_slots[20].brupdate.b2.uop.debug_tsrc connect slots_20.io.brupdate.b2.uop.debug_fsrc, issue_slots[20].brupdate.b2.uop.debug_fsrc connect slots_20.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[20].brupdate.b2.uop.bp_xcpt_if connect slots_20.io.brupdate.b2.uop.bp_debug_if, issue_slots[20].brupdate.b2.uop.bp_debug_if connect slots_20.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[20].brupdate.b2.uop.xcpt_ma_if connect slots_20.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[20].brupdate.b2.uop.xcpt_ae_if connect slots_20.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[20].brupdate.b2.uop.xcpt_pf_if connect slots_20.io.brupdate.b2.uop.fp_single, issue_slots[20].brupdate.b2.uop.fp_single connect slots_20.io.brupdate.b2.uop.fp_val, issue_slots[20].brupdate.b2.uop.fp_val connect slots_20.io.brupdate.b2.uop.frs3_en, issue_slots[20].brupdate.b2.uop.frs3_en connect slots_20.io.brupdate.b2.uop.lrs2_rtype, issue_slots[20].brupdate.b2.uop.lrs2_rtype connect slots_20.io.brupdate.b2.uop.lrs1_rtype, issue_slots[20].brupdate.b2.uop.lrs1_rtype connect slots_20.io.brupdate.b2.uop.dst_rtype, issue_slots[20].brupdate.b2.uop.dst_rtype connect slots_20.io.brupdate.b2.uop.ldst_val, issue_slots[20].brupdate.b2.uop.ldst_val connect slots_20.io.brupdate.b2.uop.lrs3, issue_slots[20].brupdate.b2.uop.lrs3 connect slots_20.io.brupdate.b2.uop.lrs2, issue_slots[20].brupdate.b2.uop.lrs2 connect slots_20.io.brupdate.b2.uop.lrs1, issue_slots[20].brupdate.b2.uop.lrs1 connect slots_20.io.brupdate.b2.uop.ldst, issue_slots[20].brupdate.b2.uop.ldst connect slots_20.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[20].brupdate.b2.uop.ldst_is_rs1 connect slots_20.io.brupdate.b2.uop.flush_on_commit, issue_slots[20].brupdate.b2.uop.flush_on_commit connect slots_20.io.brupdate.b2.uop.is_unique, issue_slots[20].brupdate.b2.uop.is_unique connect slots_20.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[20].brupdate.b2.uop.is_sys_pc2epc connect slots_20.io.brupdate.b2.uop.uses_stq, issue_slots[20].brupdate.b2.uop.uses_stq connect slots_20.io.brupdate.b2.uop.uses_ldq, issue_slots[20].brupdate.b2.uop.uses_ldq connect slots_20.io.brupdate.b2.uop.is_amo, issue_slots[20].brupdate.b2.uop.is_amo connect slots_20.io.brupdate.b2.uop.is_fencei, issue_slots[20].brupdate.b2.uop.is_fencei connect slots_20.io.brupdate.b2.uop.is_fence, issue_slots[20].brupdate.b2.uop.is_fence connect slots_20.io.brupdate.b2.uop.mem_signed, issue_slots[20].brupdate.b2.uop.mem_signed connect slots_20.io.brupdate.b2.uop.mem_size, issue_slots[20].brupdate.b2.uop.mem_size connect slots_20.io.brupdate.b2.uop.mem_cmd, issue_slots[20].brupdate.b2.uop.mem_cmd connect slots_20.io.brupdate.b2.uop.bypassable, issue_slots[20].brupdate.b2.uop.bypassable connect slots_20.io.brupdate.b2.uop.exc_cause, issue_slots[20].brupdate.b2.uop.exc_cause connect slots_20.io.brupdate.b2.uop.exception, issue_slots[20].brupdate.b2.uop.exception connect slots_20.io.brupdate.b2.uop.stale_pdst, issue_slots[20].brupdate.b2.uop.stale_pdst connect slots_20.io.brupdate.b2.uop.ppred_busy, issue_slots[20].brupdate.b2.uop.ppred_busy connect slots_20.io.brupdate.b2.uop.prs3_busy, issue_slots[20].brupdate.b2.uop.prs3_busy connect slots_20.io.brupdate.b2.uop.prs2_busy, issue_slots[20].brupdate.b2.uop.prs2_busy connect slots_20.io.brupdate.b2.uop.prs1_busy, issue_slots[20].brupdate.b2.uop.prs1_busy connect slots_20.io.brupdate.b2.uop.ppred, issue_slots[20].brupdate.b2.uop.ppred connect slots_20.io.brupdate.b2.uop.prs3, issue_slots[20].brupdate.b2.uop.prs3 connect slots_20.io.brupdate.b2.uop.prs2, issue_slots[20].brupdate.b2.uop.prs2 connect slots_20.io.brupdate.b2.uop.prs1, issue_slots[20].brupdate.b2.uop.prs1 connect slots_20.io.brupdate.b2.uop.pdst, issue_slots[20].brupdate.b2.uop.pdst connect slots_20.io.brupdate.b2.uop.rxq_idx, issue_slots[20].brupdate.b2.uop.rxq_idx connect slots_20.io.brupdate.b2.uop.stq_idx, issue_slots[20].brupdate.b2.uop.stq_idx connect slots_20.io.brupdate.b2.uop.ldq_idx, issue_slots[20].brupdate.b2.uop.ldq_idx connect slots_20.io.brupdate.b2.uop.rob_idx, issue_slots[20].brupdate.b2.uop.rob_idx connect slots_20.io.brupdate.b2.uop.csr_addr, issue_slots[20].brupdate.b2.uop.csr_addr connect slots_20.io.brupdate.b2.uop.imm_packed, issue_slots[20].brupdate.b2.uop.imm_packed connect slots_20.io.brupdate.b2.uop.taken, issue_slots[20].brupdate.b2.uop.taken connect slots_20.io.brupdate.b2.uop.pc_lob, issue_slots[20].brupdate.b2.uop.pc_lob connect slots_20.io.brupdate.b2.uop.edge_inst, issue_slots[20].brupdate.b2.uop.edge_inst connect slots_20.io.brupdate.b2.uop.ftq_idx, issue_slots[20].brupdate.b2.uop.ftq_idx connect slots_20.io.brupdate.b2.uop.br_tag, issue_slots[20].brupdate.b2.uop.br_tag connect slots_20.io.brupdate.b2.uop.br_mask, issue_slots[20].brupdate.b2.uop.br_mask connect slots_20.io.brupdate.b2.uop.is_sfb, issue_slots[20].brupdate.b2.uop.is_sfb connect slots_20.io.brupdate.b2.uop.is_jal, issue_slots[20].brupdate.b2.uop.is_jal connect slots_20.io.brupdate.b2.uop.is_jalr, issue_slots[20].brupdate.b2.uop.is_jalr connect slots_20.io.brupdate.b2.uop.is_br, issue_slots[20].brupdate.b2.uop.is_br connect slots_20.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[20].brupdate.b2.uop.iw_p2_poisoned connect slots_20.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[20].brupdate.b2.uop.iw_p1_poisoned connect slots_20.io.brupdate.b2.uop.iw_state, issue_slots[20].brupdate.b2.uop.iw_state connect slots_20.io.brupdate.b2.uop.ctrl.is_std, issue_slots[20].brupdate.b2.uop.ctrl.is_std connect slots_20.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[20].brupdate.b2.uop.ctrl.is_sta connect slots_20.io.brupdate.b2.uop.ctrl.is_load, issue_slots[20].brupdate.b2.uop.ctrl.is_load connect slots_20.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[20].brupdate.b2.uop.ctrl.csr_cmd connect slots_20.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[20].brupdate.b2.uop.ctrl.fcn_dw connect slots_20.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[20].brupdate.b2.uop.ctrl.op_fcn connect slots_20.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[20].brupdate.b2.uop.ctrl.imm_sel connect slots_20.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[20].brupdate.b2.uop.ctrl.op2_sel connect slots_20.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[20].brupdate.b2.uop.ctrl.op1_sel connect slots_20.io.brupdate.b2.uop.ctrl.br_type, issue_slots[20].brupdate.b2.uop.ctrl.br_type connect slots_20.io.brupdate.b2.uop.fu_code, issue_slots[20].brupdate.b2.uop.fu_code connect slots_20.io.brupdate.b2.uop.iq_type, issue_slots[20].brupdate.b2.uop.iq_type connect slots_20.io.brupdate.b2.uop.debug_pc, issue_slots[20].brupdate.b2.uop.debug_pc connect slots_20.io.brupdate.b2.uop.is_rvc, issue_slots[20].brupdate.b2.uop.is_rvc connect slots_20.io.brupdate.b2.uop.debug_inst, issue_slots[20].brupdate.b2.uop.debug_inst connect slots_20.io.brupdate.b2.uop.inst, issue_slots[20].brupdate.b2.uop.inst connect slots_20.io.brupdate.b2.uop.uopc, issue_slots[20].brupdate.b2.uop.uopc connect slots_20.io.brupdate.b1.mispredict_mask, issue_slots[20].brupdate.b1.mispredict_mask connect slots_20.io.brupdate.b1.resolve_mask, issue_slots[20].brupdate.b1.resolve_mask connect slots_20.io.grant, issue_slots[20].grant connect issue_slots[20].request_hp, slots_20.io.request_hp connect issue_slots[20].request, slots_20.io.request connect issue_slots[20].will_be_valid, slots_20.io.will_be_valid connect issue_slots[20].valid, slots_20.io.valid connect issue_slots[21].debug.state, slots_21.io.debug.state connect issue_slots[21].debug.ppred, slots_21.io.debug.ppred connect issue_slots[21].debug.p3, slots_21.io.debug.p3 connect issue_slots[21].debug.p2, slots_21.io.debug.p2 connect issue_slots[21].debug.p1, slots_21.io.debug.p1 connect issue_slots[21].uop.debug_tsrc, slots_21.io.uop.debug_tsrc connect issue_slots[21].uop.debug_fsrc, slots_21.io.uop.debug_fsrc connect issue_slots[21].uop.bp_xcpt_if, slots_21.io.uop.bp_xcpt_if connect issue_slots[21].uop.bp_debug_if, slots_21.io.uop.bp_debug_if connect issue_slots[21].uop.xcpt_ma_if, slots_21.io.uop.xcpt_ma_if connect issue_slots[21].uop.xcpt_ae_if, slots_21.io.uop.xcpt_ae_if connect issue_slots[21].uop.xcpt_pf_if, slots_21.io.uop.xcpt_pf_if connect issue_slots[21].uop.fp_single, slots_21.io.uop.fp_single connect issue_slots[21].uop.fp_val, slots_21.io.uop.fp_val connect issue_slots[21].uop.frs3_en, slots_21.io.uop.frs3_en connect issue_slots[21].uop.lrs2_rtype, slots_21.io.uop.lrs2_rtype connect issue_slots[21].uop.lrs1_rtype, slots_21.io.uop.lrs1_rtype connect issue_slots[21].uop.dst_rtype, slots_21.io.uop.dst_rtype connect issue_slots[21].uop.ldst_val, slots_21.io.uop.ldst_val connect issue_slots[21].uop.lrs3, slots_21.io.uop.lrs3 connect issue_slots[21].uop.lrs2, slots_21.io.uop.lrs2 connect issue_slots[21].uop.lrs1, slots_21.io.uop.lrs1 connect issue_slots[21].uop.ldst, slots_21.io.uop.ldst connect issue_slots[21].uop.ldst_is_rs1, slots_21.io.uop.ldst_is_rs1 connect issue_slots[21].uop.flush_on_commit, slots_21.io.uop.flush_on_commit connect issue_slots[21].uop.is_unique, slots_21.io.uop.is_unique connect issue_slots[21].uop.is_sys_pc2epc, slots_21.io.uop.is_sys_pc2epc connect issue_slots[21].uop.uses_stq, slots_21.io.uop.uses_stq connect issue_slots[21].uop.uses_ldq, slots_21.io.uop.uses_ldq connect issue_slots[21].uop.is_amo, slots_21.io.uop.is_amo connect issue_slots[21].uop.is_fencei, slots_21.io.uop.is_fencei connect issue_slots[21].uop.is_fence, slots_21.io.uop.is_fence connect issue_slots[21].uop.mem_signed, slots_21.io.uop.mem_signed connect issue_slots[21].uop.mem_size, slots_21.io.uop.mem_size connect issue_slots[21].uop.mem_cmd, slots_21.io.uop.mem_cmd connect issue_slots[21].uop.bypassable, slots_21.io.uop.bypassable connect issue_slots[21].uop.exc_cause, slots_21.io.uop.exc_cause connect issue_slots[21].uop.exception, slots_21.io.uop.exception connect issue_slots[21].uop.stale_pdst, slots_21.io.uop.stale_pdst connect issue_slots[21].uop.ppred_busy, slots_21.io.uop.ppred_busy connect issue_slots[21].uop.prs3_busy, slots_21.io.uop.prs3_busy connect issue_slots[21].uop.prs2_busy, slots_21.io.uop.prs2_busy connect issue_slots[21].uop.prs1_busy, slots_21.io.uop.prs1_busy connect issue_slots[21].uop.ppred, slots_21.io.uop.ppred connect issue_slots[21].uop.prs3, slots_21.io.uop.prs3 connect issue_slots[21].uop.prs2, slots_21.io.uop.prs2 connect issue_slots[21].uop.prs1, slots_21.io.uop.prs1 connect issue_slots[21].uop.pdst, slots_21.io.uop.pdst connect issue_slots[21].uop.rxq_idx, slots_21.io.uop.rxq_idx connect issue_slots[21].uop.stq_idx, slots_21.io.uop.stq_idx connect issue_slots[21].uop.ldq_idx, slots_21.io.uop.ldq_idx connect issue_slots[21].uop.rob_idx, slots_21.io.uop.rob_idx connect issue_slots[21].uop.csr_addr, slots_21.io.uop.csr_addr connect issue_slots[21].uop.imm_packed, slots_21.io.uop.imm_packed connect issue_slots[21].uop.taken, slots_21.io.uop.taken connect issue_slots[21].uop.pc_lob, slots_21.io.uop.pc_lob connect issue_slots[21].uop.edge_inst, slots_21.io.uop.edge_inst connect issue_slots[21].uop.ftq_idx, slots_21.io.uop.ftq_idx connect issue_slots[21].uop.br_tag, slots_21.io.uop.br_tag connect issue_slots[21].uop.br_mask, slots_21.io.uop.br_mask connect issue_slots[21].uop.is_sfb, slots_21.io.uop.is_sfb connect issue_slots[21].uop.is_jal, slots_21.io.uop.is_jal connect issue_slots[21].uop.is_jalr, slots_21.io.uop.is_jalr connect issue_slots[21].uop.is_br, slots_21.io.uop.is_br connect issue_slots[21].uop.iw_p2_poisoned, slots_21.io.uop.iw_p2_poisoned connect issue_slots[21].uop.iw_p1_poisoned, slots_21.io.uop.iw_p1_poisoned connect issue_slots[21].uop.iw_state, slots_21.io.uop.iw_state connect issue_slots[21].uop.ctrl.is_std, slots_21.io.uop.ctrl.is_std connect issue_slots[21].uop.ctrl.is_sta, slots_21.io.uop.ctrl.is_sta connect issue_slots[21].uop.ctrl.is_load, slots_21.io.uop.ctrl.is_load connect issue_slots[21].uop.ctrl.csr_cmd, slots_21.io.uop.ctrl.csr_cmd connect issue_slots[21].uop.ctrl.fcn_dw, slots_21.io.uop.ctrl.fcn_dw connect issue_slots[21].uop.ctrl.op_fcn, slots_21.io.uop.ctrl.op_fcn connect issue_slots[21].uop.ctrl.imm_sel, slots_21.io.uop.ctrl.imm_sel connect issue_slots[21].uop.ctrl.op2_sel, slots_21.io.uop.ctrl.op2_sel connect issue_slots[21].uop.ctrl.op1_sel, slots_21.io.uop.ctrl.op1_sel connect issue_slots[21].uop.ctrl.br_type, slots_21.io.uop.ctrl.br_type connect issue_slots[21].uop.fu_code, slots_21.io.uop.fu_code connect issue_slots[21].uop.iq_type, slots_21.io.uop.iq_type connect issue_slots[21].uop.debug_pc, slots_21.io.uop.debug_pc connect issue_slots[21].uop.is_rvc, slots_21.io.uop.is_rvc connect issue_slots[21].uop.debug_inst, slots_21.io.uop.debug_inst connect issue_slots[21].uop.inst, slots_21.io.uop.inst connect issue_slots[21].uop.uopc, slots_21.io.uop.uopc connect issue_slots[21].out_uop.debug_tsrc, slots_21.io.out_uop.debug_tsrc connect issue_slots[21].out_uop.debug_fsrc, slots_21.io.out_uop.debug_fsrc connect issue_slots[21].out_uop.bp_xcpt_if, slots_21.io.out_uop.bp_xcpt_if connect issue_slots[21].out_uop.bp_debug_if, slots_21.io.out_uop.bp_debug_if connect issue_slots[21].out_uop.xcpt_ma_if, slots_21.io.out_uop.xcpt_ma_if connect issue_slots[21].out_uop.xcpt_ae_if, slots_21.io.out_uop.xcpt_ae_if connect issue_slots[21].out_uop.xcpt_pf_if, slots_21.io.out_uop.xcpt_pf_if connect issue_slots[21].out_uop.fp_single, slots_21.io.out_uop.fp_single connect issue_slots[21].out_uop.fp_val, slots_21.io.out_uop.fp_val connect issue_slots[21].out_uop.frs3_en, slots_21.io.out_uop.frs3_en connect issue_slots[21].out_uop.lrs2_rtype, slots_21.io.out_uop.lrs2_rtype connect issue_slots[21].out_uop.lrs1_rtype, slots_21.io.out_uop.lrs1_rtype connect issue_slots[21].out_uop.dst_rtype, slots_21.io.out_uop.dst_rtype connect issue_slots[21].out_uop.ldst_val, slots_21.io.out_uop.ldst_val connect issue_slots[21].out_uop.lrs3, slots_21.io.out_uop.lrs3 connect issue_slots[21].out_uop.lrs2, slots_21.io.out_uop.lrs2 connect issue_slots[21].out_uop.lrs1, slots_21.io.out_uop.lrs1 connect issue_slots[21].out_uop.ldst, slots_21.io.out_uop.ldst connect issue_slots[21].out_uop.ldst_is_rs1, slots_21.io.out_uop.ldst_is_rs1 connect issue_slots[21].out_uop.flush_on_commit, slots_21.io.out_uop.flush_on_commit connect issue_slots[21].out_uop.is_unique, slots_21.io.out_uop.is_unique connect issue_slots[21].out_uop.is_sys_pc2epc, slots_21.io.out_uop.is_sys_pc2epc connect issue_slots[21].out_uop.uses_stq, slots_21.io.out_uop.uses_stq connect issue_slots[21].out_uop.uses_ldq, slots_21.io.out_uop.uses_ldq connect issue_slots[21].out_uop.is_amo, slots_21.io.out_uop.is_amo connect issue_slots[21].out_uop.is_fencei, slots_21.io.out_uop.is_fencei connect issue_slots[21].out_uop.is_fence, slots_21.io.out_uop.is_fence connect issue_slots[21].out_uop.mem_signed, slots_21.io.out_uop.mem_signed connect issue_slots[21].out_uop.mem_size, slots_21.io.out_uop.mem_size connect issue_slots[21].out_uop.mem_cmd, slots_21.io.out_uop.mem_cmd connect issue_slots[21].out_uop.bypassable, slots_21.io.out_uop.bypassable connect issue_slots[21].out_uop.exc_cause, slots_21.io.out_uop.exc_cause connect issue_slots[21].out_uop.exception, slots_21.io.out_uop.exception connect issue_slots[21].out_uop.stale_pdst, slots_21.io.out_uop.stale_pdst connect issue_slots[21].out_uop.ppred_busy, slots_21.io.out_uop.ppred_busy connect issue_slots[21].out_uop.prs3_busy, slots_21.io.out_uop.prs3_busy connect issue_slots[21].out_uop.prs2_busy, slots_21.io.out_uop.prs2_busy connect issue_slots[21].out_uop.prs1_busy, slots_21.io.out_uop.prs1_busy connect issue_slots[21].out_uop.ppred, slots_21.io.out_uop.ppred connect issue_slots[21].out_uop.prs3, slots_21.io.out_uop.prs3 connect issue_slots[21].out_uop.prs2, slots_21.io.out_uop.prs2 connect issue_slots[21].out_uop.prs1, slots_21.io.out_uop.prs1 connect issue_slots[21].out_uop.pdst, slots_21.io.out_uop.pdst connect issue_slots[21].out_uop.rxq_idx, slots_21.io.out_uop.rxq_idx connect issue_slots[21].out_uop.stq_idx, slots_21.io.out_uop.stq_idx connect issue_slots[21].out_uop.ldq_idx, slots_21.io.out_uop.ldq_idx connect issue_slots[21].out_uop.rob_idx, slots_21.io.out_uop.rob_idx connect issue_slots[21].out_uop.csr_addr, slots_21.io.out_uop.csr_addr connect issue_slots[21].out_uop.imm_packed, slots_21.io.out_uop.imm_packed connect issue_slots[21].out_uop.taken, slots_21.io.out_uop.taken connect issue_slots[21].out_uop.pc_lob, slots_21.io.out_uop.pc_lob connect issue_slots[21].out_uop.edge_inst, slots_21.io.out_uop.edge_inst connect issue_slots[21].out_uop.ftq_idx, slots_21.io.out_uop.ftq_idx connect issue_slots[21].out_uop.br_tag, slots_21.io.out_uop.br_tag connect issue_slots[21].out_uop.br_mask, slots_21.io.out_uop.br_mask connect issue_slots[21].out_uop.is_sfb, slots_21.io.out_uop.is_sfb connect issue_slots[21].out_uop.is_jal, slots_21.io.out_uop.is_jal connect issue_slots[21].out_uop.is_jalr, slots_21.io.out_uop.is_jalr connect issue_slots[21].out_uop.is_br, slots_21.io.out_uop.is_br connect issue_slots[21].out_uop.iw_p2_poisoned, slots_21.io.out_uop.iw_p2_poisoned connect issue_slots[21].out_uop.iw_p1_poisoned, slots_21.io.out_uop.iw_p1_poisoned connect issue_slots[21].out_uop.iw_state, slots_21.io.out_uop.iw_state connect issue_slots[21].out_uop.ctrl.is_std, slots_21.io.out_uop.ctrl.is_std connect issue_slots[21].out_uop.ctrl.is_sta, slots_21.io.out_uop.ctrl.is_sta connect issue_slots[21].out_uop.ctrl.is_load, slots_21.io.out_uop.ctrl.is_load connect issue_slots[21].out_uop.ctrl.csr_cmd, slots_21.io.out_uop.ctrl.csr_cmd connect issue_slots[21].out_uop.ctrl.fcn_dw, slots_21.io.out_uop.ctrl.fcn_dw connect issue_slots[21].out_uop.ctrl.op_fcn, slots_21.io.out_uop.ctrl.op_fcn connect issue_slots[21].out_uop.ctrl.imm_sel, slots_21.io.out_uop.ctrl.imm_sel connect issue_slots[21].out_uop.ctrl.op2_sel, slots_21.io.out_uop.ctrl.op2_sel connect issue_slots[21].out_uop.ctrl.op1_sel, slots_21.io.out_uop.ctrl.op1_sel connect issue_slots[21].out_uop.ctrl.br_type, slots_21.io.out_uop.ctrl.br_type connect issue_slots[21].out_uop.fu_code, slots_21.io.out_uop.fu_code connect issue_slots[21].out_uop.iq_type, slots_21.io.out_uop.iq_type connect issue_slots[21].out_uop.debug_pc, slots_21.io.out_uop.debug_pc connect issue_slots[21].out_uop.is_rvc, slots_21.io.out_uop.is_rvc connect issue_slots[21].out_uop.debug_inst, slots_21.io.out_uop.debug_inst connect issue_slots[21].out_uop.inst, slots_21.io.out_uop.inst connect issue_slots[21].out_uop.uopc, slots_21.io.out_uop.uopc connect slots_21.io.in_uop.bits.debug_tsrc, issue_slots[21].in_uop.bits.debug_tsrc connect slots_21.io.in_uop.bits.debug_fsrc, issue_slots[21].in_uop.bits.debug_fsrc connect slots_21.io.in_uop.bits.bp_xcpt_if, issue_slots[21].in_uop.bits.bp_xcpt_if connect slots_21.io.in_uop.bits.bp_debug_if, issue_slots[21].in_uop.bits.bp_debug_if connect slots_21.io.in_uop.bits.xcpt_ma_if, issue_slots[21].in_uop.bits.xcpt_ma_if connect slots_21.io.in_uop.bits.xcpt_ae_if, issue_slots[21].in_uop.bits.xcpt_ae_if connect slots_21.io.in_uop.bits.xcpt_pf_if, issue_slots[21].in_uop.bits.xcpt_pf_if connect slots_21.io.in_uop.bits.fp_single, issue_slots[21].in_uop.bits.fp_single connect slots_21.io.in_uop.bits.fp_val, issue_slots[21].in_uop.bits.fp_val connect slots_21.io.in_uop.bits.frs3_en, issue_slots[21].in_uop.bits.frs3_en connect slots_21.io.in_uop.bits.lrs2_rtype, issue_slots[21].in_uop.bits.lrs2_rtype connect slots_21.io.in_uop.bits.lrs1_rtype, issue_slots[21].in_uop.bits.lrs1_rtype connect slots_21.io.in_uop.bits.dst_rtype, issue_slots[21].in_uop.bits.dst_rtype connect slots_21.io.in_uop.bits.ldst_val, issue_slots[21].in_uop.bits.ldst_val connect slots_21.io.in_uop.bits.lrs3, issue_slots[21].in_uop.bits.lrs3 connect slots_21.io.in_uop.bits.lrs2, issue_slots[21].in_uop.bits.lrs2 connect slots_21.io.in_uop.bits.lrs1, issue_slots[21].in_uop.bits.lrs1 connect slots_21.io.in_uop.bits.ldst, issue_slots[21].in_uop.bits.ldst connect slots_21.io.in_uop.bits.ldst_is_rs1, issue_slots[21].in_uop.bits.ldst_is_rs1 connect slots_21.io.in_uop.bits.flush_on_commit, issue_slots[21].in_uop.bits.flush_on_commit connect slots_21.io.in_uop.bits.is_unique, issue_slots[21].in_uop.bits.is_unique connect slots_21.io.in_uop.bits.is_sys_pc2epc, issue_slots[21].in_uop.bits.is_sys_pc2epc connect slots_21.io.in_uop.bits.uses_stq, issue_slots[21].in_uop.bits.uses_stq connect slots_21.io.in_uop.bits.uses_ldq, issue_slots[21].in_uop.bits.uses_ldq connect slots_21.io.in_uop.bits.is_amo, issue_slots[21].in_uop.bits.is_amo connect slots_21.io.in_uop.bits.is_fencei, issue_slots[21].in_uop.bits.is_fencei connect slots_21.io.in_uop.bits.is_fence, issue_slots[21].in_uop.bits.is_fence connect slots_21.io.in_uop.bits.mem_signed, issue_slots[21].in_uop.bits.mem_signed connect slots_21.io.in_uop.bits.mem_size, issue_slots[21].in_uop.bits.mem_size connect slots_21.io.in_uop.bits.mem_cmd, issue_slots[21].in_uop.bits.mem_cmd connect slots_21.io.in_uop.bits.bypassable, issue_slots[21].in_uop.bits.bypassable connect slots_21.io.in_uop.bits.exc_cause, issue_slots[21].in_uop.bits.exc_cause connect slots_21.io.in_uop.bits.exception, issue_slots[21].in_uop.bits.exception connect slots_21.io.in_uop.bits.stale_pdst, issue_slots[21].in_uop.bits.stale_pdst connect slots_21.io.in_uop.bits.ppred_busy, issue_slots[21].in_uop.bits.ppred_busy connect slots_21.io.in_uop.bits.prs3_busy, issue_slots[21].in_uop.bits.prs3_busy connect slots_21.io.in_uop.bits.prs2_busy, issue_slots[21].in_uop.bits.prs2_busy connect slots_21.io.in_uop.bits.prs1_busy, issue_slots[21].in_uop.bits.prs1_busy connect slots_21.io.in_uop.bits.ppred, issue_slots[21].in_uop.bits.ppred connect slots_21.io.in_uop.bits.prs3, issue_slots[21].in_uop.bits.prs3 connect slots_21.io.in_uop.bits.prs2, issue_slots[21].in_uop.bits.prs2 connect slots_21.io.in_uop.bits.prs1, issue_slots[21].in_uop.bits.prs1 connect slots_21.io.in_uop.bits.pdst, issue_slots[21].in_uop.bits.pdst connect slots_21.io.in_uop.bits.rxq_idx, issue_slots[21].in_uop.bits.rxq_idx connect slots_21.io.in_uop.bits.stq_idx, issue_slots[21].in_uop.bits.stq_idx connect slots_21.io.in_uop.bits.ldq_idx, issue_slots[21].in_uop.bits.ldq_idx connect slots_21.io.in_uop.bits.rob_idx, issue_slots[21].in_uop.bits.rob_idx connect slots_21.io.in_uop.bits.csr_addr, issue_slots[21].in_uop.bits.csr_addr connect slots_21.io.in_uop.bits.imm_packed, issue_slots[21].in_uop.bits.imm_packed connect slots_21.io.in_uop.bits.taken, issue_slots[21].in_uop.bits.taken connect slots_21.io.in_uop.bits.pc_lob, issue_slots[21].in_uop.bits.pc_lob connect slots_21.io.in_uop.bits.edge_inst, issue_slots[21].in_uop.bits.edge_inst connect slots_21.io.in_uop.bits.ftq_idx, issue_slots[21].in_uop.bits.ftq_idx connect slots_21.io.in_uop.bits.br_tag, issue_slots[21].in_uop.bits.br_tag connect slots_21.io.in_uop.bits.br_mask, issue_slots[21].in_uop.bits.br_mask connect slots_21.io.in_uop.bits.is_sfb, issue_slots[21].in_uop.bits.is_sfb connect slots_21.io.in_uop.bits.is_jal, issue_slots[21].in_uop.bits.is_jal connect slots_21.io.in_uop.bits.is_jalr, issue_slots[21].in_uop.bits.is_jalr connect slots_21.io.in_uop.bits.is_br, issue_slots[21].in_uop.bits.is_br connect slots_21.io.in_uop.bits.iw_p2_poisoned, issue_slots[21].in_uop.bits.iw_p2_poisoned connect slots_21.io.in_uop.bits.iw_p1_poisoned, issue_slots[21].in_uop.bits.iw_p1_poisoned connect slots_21.io.in_uop.bits.iw_state, issue_slots[21].in_uop.bits.iw_state connect slots_21.io.in_uop.bits.ctrl.is_std, issue_slots[21].in_uop.bits.ctrl.is_std connect slots_21.io.in_uop.bits.ctrl.is_sta, issue_slots[21].in_uop.bits.ctrl.is_sta connect slots_21.io.in_uop.bits.ctrl.is_load, issue_slots[21].in_uop.bits.ctrl.is_load connect slots_21.io.in_uop.bits.ctrl.csr_cmd, issue_slots[21].in_uop.bits.ctrl.csr_cmd connect slots_21.io.in_uop.bits.ctrl.fcn_dw, issue_slots[21].in_uop.bits.ctrl.fcn_dw connect slots_21.io.in_uop.bits.ctrl.op_fcn, issue_slots[21].in_uop.bits.ctrl.op_fcn connect slots_21.io.in_uop.bits.ctrl.imm_sel, issue_slots[21].in_uop.bits.ctrl.imm_sel connect slots_21.io.in_uop.bits.ctrl.op2_sel, issue_slots[21].in_uop.bits.ctrl.op2_sel connect slots_21.io.in_uop.bits.ctrl.op1_sel, issue_slots[21].in_uop.bits.ctrl.op1_sel connect slots_21.io.in_uop.bits.ctrl.br_type, issue_slots[21].in_uop.bits.ctrl.br_type connect slots_21.io.in_uop.bits.fu_code, issue_slots[21].in_uop.bits.fu_code connect slots_21.io.in_uop.bits.iq_type, issue_slots[21].in_uop.bits.iq_type connect slots_21.io.in_uop.bits.debug_pc, issue_slots[21].in_uop.bits.debug_pc connect slots_21.io.in_uop.bits.is_rvc, issue_slots[21].in_uop.bits.is_rvc connect slots_21.io.in_uop.bits.debug_inst, issue_slots[21].in_uop.bits.debug_inst connect slots_21.io.in_uop.bits.inst, issue_slots[21].in_uop.bits.inst connect slots_21.io.in_uop.bits.uopc, issue_slots[21].in_uop.bits.uopc connect slots_21.io.in_uop.valid, issue_slots[21].in_uop.valid connect slots_21.io.spec_ld_wakeup[0].bits, issue_slots[21].spec_ld_wakeup[0].bits connect slots_21.io.spec_ld_wakeup[0].valid, issue_slots[21].spec_ld_wakeup[0].valid connect slots_21.io.pred_wakeup_port.bits, issue_slots[21].pred_wakeup_port.bits connect slots_21.io.pred_wakeup_port.valid, issue_slots[21].pred_wakeup_port.valid connect slots_21.io.wakeup_ports[0].bits.poisoned, issue_slots[21].wakeup_ports[0].bits.poisoned connect slots_21.io.wakeup_ports[0].bits.pdst, issue_slots[21].wakeup_ports[0].bits.pdst connect slots_21.io.wakeup_ports[0].valid, issue_slots[21].wakeup_ports[0].valid connect slots_21.io.wakeup_ports[1].bits.poisoned, issue_slots[21].wakeup_ports[1].bits.poisoned connect slots_21.io.wakeup_ports[1].bits.pdst, issue_slots[21].wakeup_ports[1].bits.pdst connect slots_21.io.wakeup_ports[1].valid, issue_slots[21].wakeup_ports[1].valid connect slots_21.io.wakeup_ports[2].bits.poisoned, issue_slots[21].wakeup_ports[2].bits.poisoned connect slots_21.io.wakeup_ports[2].bits.pdst, issue_slots[21].wakeup_ports[2].bits.pdst connect slots_21.io.wakeup_ports[2].valid, issue_slots[21].wakeup_ports[2].valid connect slots_21.io.wakeup_ports[3].bits.poisoned, issue_slots[21].wakeup_ports[3].bits.poisoned connect slots_21.io.wakeup_ports[3].bits.pdst, issue_slots[21].wakeup_ports[3].bits.pdst connect slots_21.io.wakeup_ports[3].valid, issue_slots[21].wakeup_ports[3].valid connect slots_21.io.wakeup_ports[4].bits.poisoned, issue_slots[21].wakeup_ports[4].bits.poisoned connect slots_21.io.wakeup_ports[4].bits.pdst, issue_slots[21].wakeup_ports[4].bits.pdst connect slots_21.io.wakeup_ports[4].valid, issue_slots[21].wakeup_ports[4].valid connect slots_21.io.wakeup_ports[5].bits.poisoned, issue_slots[21].wakeup_ports[5].bits.poisoned connect slots_21.io.wakeup_ports[5].bits.pdst, issue_slots[21].wakeup_ports[5].bits.pdst connect slots_21.io.wakeup_ports[5].valid, issue_slots[21].wakeup_ports[5].valid connect slots_21.io.wakeup_ports[6].bits.poisoned, issue_slots[21].wakeup_ports[6].bits.poisoned connect slots_21.io.wakeup_ports[6].bits.pdst, issue_slots[21].wakeup_ports[6].bits.pdst connect slots_21.io.wakeup_ports[6].valid, issue_slots[21].wakeup_ports[6].valid connect slots_21.io.ldspec_miss, issue_slots[21].ldspec_miss connect slots_21.io.clear, issue_slots[21].clear connect slots_21.io.kill, issue_slots[21].kill connect slots_21.io.brupdate.b2.target_offset, issue_slots[21].brupdate.b2.target_offset connect slots_21.io.brupdate.b2.jalr_target, issue_slots[21].brupdate.b2.jalr_target connect slots_21.io.brupdate.b2.pc_sel, issue_slots[21].brupdate.b2.pc_sel connect slots_21.io.brupdate.b2.cfi_type, issue_slots[21].brupdate.b2.cfi_type connect slots_21.io.brupdate.b2.taken, issue_slots[21].brupdate.b2.taken connect slots_21.io.brupdate.b2.mispredict, issue_slots[21].brupdate.b2.mispredict connect slots_21.io.brupdate.b2.valid, issue_slots[21].brupdate.b2.valid connect slots_21.io.brupdate.b2.uop.debug_tsrc, issue_slots[21].brupdate.b2.uop.debug_tsrc connect slots_21.io.brupdate.b2.uop.debug_fsrc, issue_slots[21].brupdate.b2.uop.debug_fsrc connect slots_21.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[21].brupdate.b2.uop.bp_xcpt_if connect slots_21.io.brupdate.b2.uop.bp_debug_if, issue_slots[21].brupdate.b2.uop.bp_debug_if connect slots_21.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[21].brupdate.b2.uop.xcpt_ma_if connect slots_21.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[21].brupdate.b2.uop.xcpt_ae_if connect slots_21.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[21].brupdate.b2.uop.xcpt_pf_if connect slots_21.io.brupdate.b2.uop.fp_single, issue_slots[21].brupdate.b2.uop.fp_single connect slots_21.io.brupdate.b2.uop.fp_val, issue_slots[21].brupdate.b2.uop.fp_val connect slots_21.io.brupdate.b2.uop.frs3_en, issue_slots[21].brupdate.b2.uop.frs3_en connect slots_21.io.brupdate.b2.uop.lrs2_rtype, issue_slots[21].brupdate.b2.uop.lrs2_rtype connect slots_21.io.brupdate.b2.uop.lrs1_rtype, issue_slots[21].brupdate.b2.uop.lrs1_rtype connect slots_21.io.brupdate.b2.uop.dst_rtype, issue_slots[21].brupdate.b2.uop.dst_rtype connect slots_21.io.brupdate.b2.uop.ldst_val, issue_slots[21].brupdate.b2.uop.ldst_val connect slots_21.io.brupdate.b2.uop.lrs3, issue_slots[21].brupdate.b2.uop.lrs3 connect slots_21.io.brupdate.b2.uop.lrs2, issue_slots[21].brupdate.b2.uop.lrs2 connect slots_21.io.brupdate.b2.uop.lrs1, issue_slots[21].brupdate.b2.uop.lrs1 connect slots_21.io.brupdate.b2.uop.ldst, issue_slots[21].brupdate.b2.uop.ldst connect slots_21.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[21].brupdate.b2.uop.ldst_is_rs1 connect slots_21.io.brupdate.b2.uop.flush_on_commit, issue_slots[21].brupdate.b2.uop.flush_on_commit connect slots_21.io.brupdate.b2.uop.is_unique, issue_slots[21].brupdate.b2.uop.is_unique connect slots_21.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[21].brupdate.b2.uop.is_sys_pc2epc connect slots_21.io.brupdate.b2.uop.uses_stq, issue_slots[21].brupdate.b2.uop.uses_stq connect slots_21.io.brupdate.b2.uop.uses_ldq, issue_slots[21].brupdate.b2.uop.uses_ldq connect slots_21.io.brupdate.b2.uop.is_amo, issue_slots[21].brupdate.b2.uop.is_amo connect slots_21.io.brupdate.b2.uop.is_fencei, issue_slots[21].brupdate.b2.uop.is_fencei connect slots_21.io.brupdate.b2.uop.is_fence, issue_slots[21].brupdate.b2.uop.is_fence connect slots_21.io.brupdate.b2.uop.mem_signed, issue_slots[21].brupdate.b2.uop.mem_signed connect slots_21.io.brupdate.b2.uop.mem_size, issue_slots[21].brupdate.b2.uop.mem_size connect slots_21.io.brupdate.b2.uop.mem_cmd, issue_slots[21].brupdate.b2.uop.mem_cmd connect slots_21.io.brupdate.b2.uop.bypassable, issue_slots[21].brupdate.b2.uop.bypassable connect slots_21.io.brupdate.b2.uop.exc_cause, issue_slots[21].brupdate.b2.uop.exc_cause connect slots_21.io.brupdate.b2.uop.exception, issue_slots[21].brupdate.b2.uop.exception connect slots_21.io.brupdate.b2.uop.stale_pdst, issue_slots[21].brupdate.b2.uop.stale_pdst connect slots_21.io.brupdate.b2.uop.ppred_busy, issue_slots[21].brupdate.b2.uop.ppred_busy connect slots_21.io.brupdate.b2.uop.prs3_busy, issue_slots[21].brupdate.b2.uop.prs3_busy connect slots_21.io.brupdate.b2.uop.prs2_busy, issue_slots[21].brupdate.b2.uop.prs2_busy connect slots_21.io.brupdate.b2.uop.prs1_busy, issue_slots[21].brupdate.b2.uop.prs1_busy connect slots_21.io.brupdate.b2.uop.ppred, issue_slots[21].brupdate.b2.uop.ppred connect slots_21.io.brupdate.b2.uop.prs3, issue_slots[21].brupdate.b2.uop.prs3 connect slots_21.io.brupdate.b2.uop.prs2, issue_slots[21].brupdate.b2.uop.prs2 connect slots_21.io.brupdate.b2.uop.prs1, issue_slots[21].brupdate.b2.uop.prs1 connect slots_21.io.brupdate.b2.uop.pdst, issue_slots[21].brupdate.b2.uop.pdst connect slots_21.io.brupdate.b2.uop.rxq_idx, issue_slots[21].brupdate.b2.uop.rxq_idx connect slots_21.io.brupdate.b2.uop.stq_idx, issue_slots[21].brupdate.b2.uop.stq_idx connect slots_21.io.brupdate.b2.uop.ldq_idx, issue_slots[21].brupdate.b2.uop.ldq_idx connect slots_21.io.brupdate.b2.uop.rob_idx, issue_slots[21].brupdate.b2.uop.rob_idx connect slots_21.io.brupdate.b2.uop.csr_addr, issue_slots[21].brupdate.b2.uop.csr_addr connect slots_21.io.brupdate.b2.uop.imm_packed, issue_slots[21].brupdate.b2.uop.imm_packed connect slots_21.io.brupdate.b2.uop.taken, issue_slots[21].brupdate.b2.uop.taken connect slots_21.io.brupdate.b2.uop.pc_lob, issue_slots[21].brupdate.b2.uop.pc_lob connect slots_21.io.brupdate.b2.uop.edge_inst, issue_slots[21].brupdate.b2.uop.edge_inst connect slots_21.io.brupdate.b2.uop.ftq_idx, issue_slots[21].brupdate.b2.uop.ftq_idx connect slots_21.io.brupdate.b2.uop.br_tag, issue_slots[21].brupdate.b2.uop.br_tag connect slots_21.io.brupdate.b2.uop.br_mask, issue_slots[21].brupdate.b2.uop.br_mask connect slots_21.io.brupdate.b2.uop.is_sfb, issue_slots[21].brupdate.b2.uop.is_sfb connect slots_21.io.brupdate.b2.uop.is_jal, issue_slots[21].brupdate.b2.uop.is_jal connect slots_21.io.brupdate.b2.uop.is_jalr, issue_slots[21].brupdate.b2.uop.is_jalr connect slots_21.io.brupdate.b2.uop.is_br, issue_slots[21].brupdate.b2.uop.is_br connect slots_21.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[21].brupdate.b2.uop.iw_p2_poisoned connect slots_21.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[21].brupdate.b2.uop.iw_p1_poisoned connect slots_21.io.brupdate.b2.uop.iw_state, issue_slots[21].brupdate.b2.uop.iw_state connect slots_21.io.brupdate.b2.uop.ctrl.is_std, issue_slots[21].brupdate.b2.uop.ctrl.is_std connect slots_21.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[21].brupdate.b2.uop.ctrl.is_sta connect slots_21.io.brupdate.b2.uop.ctrl.is_load, issue_slots[21].brupdate.b2.uop.ctrl.is_load connect slots_21.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[21].brupdate.b2.uop.ctrl.csr_cmd connect slots_21.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[21].brupdate.b2.uop.ctrl.fcn_dw connect slots_21.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[21].brupdate.b2.uop.ctrl.op_fcn connect slots_21.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[21].brupdate.b2.uop.ctrl.imm_sel connect slots_21.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[21].brupdate.b2.uop.ctrl.op2_sel connect slots_21.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[21].brupdate.b2.uop.ctrl.op1_sel connect slots_21.io.brupdate.b2.uop.ctrl.br_type, issue_slots[21].brupdate.b2.uop.ctrl.br_type connect slots_21.io.brupdate.b2.uop.fu_code, issue_slots[21].brupdate.b2.uop.fu_code connect slots_21.io.brupdate.b2.uop.iq_type, issue_slots[21].brupdate.b2.uop.iq_type connect slots_21.io.brupdate.b2.uop.debug_pc, issue_slots[21].brupdate.b2.uop.debug_pc connect slots_21.io.brupdate.b2.uop.is_rvc, issue_slots[21].brupdate.b2.uop.is_rvc connect slots_21.io.brupdate.b2.uop.debug_inst, issue_slots[21].brupdate.b2.uop.debug_inst connect slots_21.io.brupdate.b2.uop.inst, issue_slots[21].brupdate.b2.uop.inst connect slots_21.io.brupdate.b2.uop.uopc, issue_slots[21].brupdate.b2.uop.uopc connect slots_21.io.brupdate.b1.mispredict_mask, issue_slots[21].brupdate.b1.mispredict_mask connect slots_21.io.brupdate.b1.resolve_mask, issue_slots[21].brupdate.b1.resolve_mask connect slots_21.io.grant, issue_slots[21].grant connect issue_slots[21].request_hp, slots_21.io.request_hp connect issue_slots[21].request, slots_21.io.request connect issue_slots[21].will_be_valid, slots_21.io.will_be_valid connect issue_slots[21].valid, slots_21.io.valid connect issue_slots[22].debug.state, slots_22.io.debug.state connect issue_slots[22].debug.ppred, slots_22.io.debug.ppred connect issue_slots[22].debug.p3, slots_22.io.debug.p3 connect issue_slots[22].debug.p2, slots_22.io.debug.p2 connect issue_slots[22].debug.p1, slots_22.io.debug.p1 connect issue_slots[22].uop.debug_tsrc, slots_22.io.uop.debug_tsrc connect issue_slots[22].uop.debug_fsrc, slots_22.io.uop.debug_fsrc connect issue_slots[22].uop.bp_xcpt_if, slots_22.io.uop.bp_xcpt_if connect issue_slots[22].uop.bp_debug_if, slots_22.io.uop.bp_debug_if connect issue_slots[22].uop.xcpt_ma_if, slots_22.io.uop.xcpt_ma_if connect issue_slots[22].uop.xcpt_ae_if, slots_22.io.uop.xcpt_ae_if connect issue_slots[22].uop.xcpt_pf_if, slots_22.io.uop.xcpt_pf_if connect issue_slots[22].uop.fp_single, slots_22.io.uop.fp_single connect issue_slots[22].uop.fp_val, slots_22.io.uop.fp_val connect issue_slots[22].uop.frs3_en, slots_22.io.uop.frs3_en connect issue_slots[22].uop.lrs2_rtype, slots_22.io.uop.lrs2_rtype connect issue_slots[22].uop.lrs1_rtype, slots_22.io.uop.lrs1_rtype connect issue_slots[22].uop.dst_rtype, slots_22.io.uop.dst_rtype connect issue_slots[22].uop.ldst_val, slots_22.io.uop.ldst_val connect issue_slots[22].uop.lrs3, slots_22.io.uop.lrs3 connect issue_slots[22].uop.lrs2, slots_22.io.uop.lrs2 connect issue_slots[22].uop.lrs1, slots_22.io.uop.lrs1 connect issue_slots[22].uop.ldst, slots_22.io.uop.ldst connect issue_slots[22].uop.ldst_is_rs1, slots_22.io.uop.ldst_is_rs1 connect issue_slots[22].uop.flush_on_commit, slots_22.io.uop.flush_on_commit connect issue_slots[22].uop.is_unique, slots_22.io.uop.is_unique connect issue_slots[22].uop.is_sys_pc2epc, slots_22.io.uop.is_sys_pc2epc connect issue_slots[22].uop.uses_stq, slots_22.io.uop.uses_stq connect issue_slots[22].uop.uses_ldq, slots_22.io.uop.uses_ldq connect issue_slots[22].uop.is_amo, slots_22.io.uop.is_amo connect issue_slots[22].uop.is_fencei, slots_22.io.uop.is_fencei connect issue_slots[22].uop.is_fence, slots_22.io.uop.is_fence connect issue_slots[22].uop.mem_signed, slots_22.io.uop.mem_signed connect issue_slots[22].uop.mem_size, slots_22.io.uop.mem_size connect issue_slots[22].uop.mem_cmd, slots_22.io.uop.mem_cmd connect issue_slots[22].uop.bypassable, slots_22.io.uop.bypassable connect issue_slots[22].uop.exc_cause, slots_22.io.uop.exc_cause connect issue_slots[22].uop.exception, slots_22.io.uop.exception connect issue_slots[22].uop.stale_pdst, slots_22.io.uop.stale_pdst connect issue_slots[22].uop.ppred_busy, slots_22.io.uop.ppred_busy connect issue_slots[22].uop.prs3_busy, slots_22.io.uop.prs3_busy connect issue_slots[22].uop.prs2_busy, slots_22.io.uop.prs2_busy connect issue_slots[22].uop.prs1_busy, slots_22.io.uop.prs1_busy connect issue_slots[22].uop.ppred, slots_22.io.uop.ppred connect issue_slots[22].uop.prs3, slots_22.io.uop.prs3 connect issue_slots[22].uop.prs2, slots_22.io.uop.prs2 connect issue_slots[22].uop.prs1, slots_22.io.uop.prs1 connect issue_slots[22].uop.pdst, slots_22.io.uop.pdst connect issue_slots[22].uop.rxq_idx, slots_22.io.uop.rxq_idx connect issue_slots[22].uop.stq_idx, slots_22.io.uop.stq_idx connect issue_slots[22].uop.ldq_idx, slots_22.io.uop.ldq_idx connect issue_slots[22].uop.rob_idx, slots_22.io.uop.rob_idx connect issue_slots[22].uop.csr_addr, slots_22.io.uop.csr_addr connect issue_slots[22].uop.imm_packed, slots_22.io.uop.imm_packed connect issue_slots[22].uop.taken, slots_22.io.uop.taken connect issue_slots[22].uop.pc_lob, slots_22.io.uop.pc_lob connect issue_slots[22].uop.edge_inst, slots_22.io.uop.edge_inst connect issue_slots[22].uop.ftq_idx, slots_22.io.uop.ftq_idx connect issue_slots[22].uop.br_tag, slots_22.io.uop.br_tag connect issue_slots[22].uop.br_mask, slots_22.io.uop.br_mask connect issue_slots[22].uop.is_sfb, slots_22.io.uop.is_sfb connect issue_slots[22].uop.is_jal, slots_22.io.uop.is_jal connect issue_slots[22].uop.is_jalr, slots_22.io.uop.is_jalr connect issue_slots[22].uop.is_br, slots_22.io.uop.is_br connect issue_slots[22].uop.iw_p2_poisoned, slots_22.io.uop.iw_p2_poisoned connect issue_slots[22].uop.iw_p1_poisoned, slots_22.io.uop.iw_p1_poisoned connect issue_slots[22].uop.iw_state, slots_22.io.uop.iw_state connect issue_slots[22].uop.ctrl.is_std, slots_22.io.uop.ctrl.is_std connect issue_slots[22].uop.ctrl.is_sta, slots_22.io.uop.ctrl.is_sta connect issue_slots[22].uop.ctrl.is_load, slots_22.io.uop.ctrl.is_load connect issue_slots[22].uop.ctrl.csr_cmd, slots_22.io.uop.ctrl.csr_cmd connect issue_slots[22].uop.ctrl.fcn_dw, slots_22.io.uop.ctrl.fcn_dw connect issue_slots[22].uop.ctrl.op_fcn, slots_22.io.uop.ctrl.op_fcn connect issue_slots[22].uop.ctrl.imm_sel, slots_22.io.uop.ctrl.imm_sel connect issue_slots[22].uop.ctrl.op2_sel, slots_22.io.uop.ctrl.op2_sel connect issue_slots[22].uop.ctrl.op1_sel, slots_22.io.uop.ctrl.op1_sel connect issue_slots[22].uop.ctrl.br_type, slots_22.io.uop.ctrl.br_type connect issue_slots[22].uop.fu_code, slots_22.io.uop.fu_code connect issue_slots[22].uop.iq_type, slots_22.io.uop.iq_type connect issue_slots[22].uop.debug_pc, slots_22.io.uop.debug_pc connect issue_slots[22].uop.is_rvc, slots_22.io.uop.is_rvc connect issue_slots[22].uop.debug_inst, slots_22.io.uop.debug_inst connect issue_slots[22].uop.inst, slots_22.io.uop.inst connect issue_slots[22].uop.uopc, slots_22.io.uop.uopc connect issue_slots[22].out_uop.debug_tsrc, slots_22.io.out_uop.debug_tsrc connect issue_slots[22].out_uop.debug_fsrc, slots_22.io.out_uop.debug_fsrc connect issue_slots[22].out_uop.bp_xcpt_if, slots_22.io.out_uop.bp_xcpt_if connect issue_slots[22].out_uop.bp_debug_if, slots_22.io.out_uop.bp_debug_if connect issue_slots[22].out_uop.xcpt_ma_if, slots_22.io.out_uop.xcpt_ma_if connect issue_slots[22].out_uop.xcpt_ae_if, slots_22.io.out_uop.xcpt_ae_if connect issue_slots[22].out_uop.xcpt_pf_if, slots_22.io.out_uop.xcpt_pf_if connect issue_slots[22].out_uop.fp_single, slots_22.io.out_uop.fp_single connect issue_slots[22].out_uop.fp_val, slots_22.io.out_uop.fp_val connect issue_slots[22].out_uop.frs3_en, slots_22.io.out_uop.frs3_en connect issue_slots[22].out_uop.lrs2_rtype, slots_22.io.out_uop.lrs2_rtype connect issue_slots[22].out_uop.lrs1_rtype, slots_22.io.out_uop.lrs1_rtype connect issue_slots[22].out_uop.dst_rtype, slots_22.io.out_uop.dst_rtype connect issue_slots[22].out_uop.ldst_val, slots_22.io.out_uop.ldst_val connect issue_slots[22].out_uop.lrs3, slots_22.io.out_uop.lrs3 connect issue_slots[22].out_uop.lrs2, slots_22.io.out_uop.lrs2 connect issue_slots[22].out_uop.lrs1, slots_22.io.out_uop.lrs1 connect issue_slots[22].out_uop.ldst, slots_22.io.out_uop.ldst connect issue_slots[22].out_uop.ldst_is_rs1, slots_22.io.out_uop.ldst_is_rs1 connect issue_slots[22].out_uop.flush_on_commit, slots_22.io.out_uop.flush_on_commit connect issue_slots[22].out_uop.is_unique, slots_22.io.out_uop.is_unique connect issue_slots[22].out_uop.is_sys_pc2epc, slots_22.io.out_uop.is_sys_pc2epc connect issue_slots[22].out_uop.uses_stq, slots_22.io.out_uop.uses_stq connect issue_slots[22].out_uop.uses_ldq, slots_22.io.out_uop.uses_ldq connect issue_slots[22].out_uop.is_amo, slots_22.io.out_uop.is_amo connect issue_slots[22].out_uop.is_fencei, slots_22.io.out_uop.is_fencei connect issue_slots[22].out_uop.is_fence, slots_22.io.out_uop.is_fence connect issue_slots[22].out_uop.mem_signed, slots_22.io.out_uop.mem_signed connect issue_slots[22].out_uop.mem_size, slots_22.io.out_uop.mem_size connect issue_slots[22].out_uop.mem_cmd, slots_22.io.out_uop.mem_cmd connect issue_slots[22].out_uop.bypassable, slots_22.io.out_uop.bypassable connect issue_slots[22].out_uop.exc_cause, slots_22.io.out_uop.exc_cause connect issue_slots[22].out_uop.exception, slots_22.io.out_uop.exception connect issue_slots[22].out_uop.stale_pdst, slots_22.io.out_uop.stale_pdst connect issue_slots[22].out_uop.ppred_busy, slots_22.io.out_uop.ppred_busy connect issue_slots[22].out_uop.prs3_busy, slots_22.io.out_uop.prs3_busy connect issue_slots[22].out_uop.prs2_busy, slots_22.io.out_uop.prs2_busy connect issue_slots[22].out_uop.prs1_busy, slots_22.io.out_uop.prs1_busy connect issue_slots[22].out_uop.ppred, slots_22.io.out_uop.ppred connect issue_slots[22].out_uop.prs3, slots_22.io.out_uop.prs3 connect issue_slots[22].out_uop.prs2, slots_22.io.out_uop.prs2 connect issue_slots[22].out_uop.prs1, slots_22.io.out_uop.prs1 connect issue_slots[22].out_uop.pdst, slots_22.io.out_uop.pdst connect issue_slots[22].out_uop.rxq_idx, slots_22.io.out_uop.rxq_idx connect issue_slots[22].out_uop.stq_idx, slots_22.io.out_uop.stq_idx connect issue_slots[22].out_uop.ldq_idx, slots_22.io.out_uop.ldq_idx connect issue_slots[22].out_uop.rob_idx, slots_22.io.out_uop.rob_idx connect issue_slots[22].out_uop.csr_addr, slots_22.io.out_uop.csr_addr connect issue_slots[22].out_uop.imm_packed, slots_22.io.out_uop.imm_packed connect issue_slots[22].out_uop.taken, slots_22.io.out_uop.taken connect issue_slots[22].out_uop.pc_lob, slots_22.io.out_uop.pc_lob connect issue_slots[22].out_uop.edge_inst, slots_22.io.out_uop.edge_inst connect issue_slots[22].out_uop.ftq_idx, slots_22.io.out_uop.ftq_idx connect issue_slots[22].out_uop.br_tag, slots_22.io.out_uop.br_tag connect issue_slots[22].out_uop.br_mask, slots_22.io.out_uop.br_mask connect issue_slots[22].out_uop.is_sfb, slots_22.io.out_uop.is_sfb connect issue_slots[22].out_uop.is_jal, slots_22.io.out_uop.is_jal connect issue_slots[22].out_uop.is_jalr, slots_22.io.out_uop.is_jalr connect issue_slots[22].out_uop.is_br, slots_22.io.out_uop.is_br connect issue_slots[22].out_uop.iw_p2_poisoned, slots_22.io.out_uop.iw_p2_poisoned connect issue_slots[22].out_uop.iw_p1_poisoned, slots_22.io.out_uop.iw_p1_poisoned connect issue_slots[22].out_uop.iw_state, slots_22.io.out_uop.iw_state connect issue_slots[22].out_uop.ctrl.is_std, slots_22.io.out_uop.ctrl.is_std connect issue_slots[22].out_uop.ctrl.is_sta, slots_22.io.out_uop.ctrl.is_sta connect issue_slots[22].out_uop.ctrl.is_load, slots_22.io.out_uop.ctrl.is_load connect issue_slots[22].out_uop.ctrl.csr_cmd, slots_22.io.out_uop.ctrl.csr_cmd connect issue_slots[22].out_uop.ctrl.fcn_dw, slots_22.io.out_uop.ctrl.fcn_dw connect issue_slots[22].out_uop.ctrl.op_fcn, slots_22.io.out_uop.ctrl.op_fcn connect issue_slots[22].out_uop.ctrl.imm_sel, slots_22.io.out_uop.ctrl.imm_sel connect issue_slots[22].out_uop.ctrl.op2_sel, slots_22.io.out_uop.ctrl.op2_sel connect issue_slots[22].out_uop.ctrl.op1_sel, slots_22.io.out_uop.ctrl.op1_sel connect issue_slots[22].out_uop.ctrl.br_type, slots_22.io.out_uop.ctrl.br_type connect issue_slots[22].out_uop.fu_code, slots_22.io.out_uop.fu_code connect issue_slots[22].out_uop.iq_type, slots_22.io.out_uop.iq_type connect issue_slots[22].out_uop.debug_pc, slots_22.io.out_uop.debug_pc connect issue_slots[22].out_uop.is_rvc, slots_22.io.out_uop.is_rvc connect issue_slots[22].out_uop.debug_inst, slots_22.io.out_uop.debug_inst connect issue_slots[22].out_uop.inst, slots_22.io.out_uop.inst connect issue_slots[22].out_uop.uopc, slots_22.io.out_uop.uopc connect slots_22.io.in_uop.bits.debug_tsrc, issue_slots[22].in_uop.bits.debug_tsrc connect slots_22.io.in_uop.bits.debug_fsrc, issue_slots[22].in_uop.bits.debug_fsrc connect slots_22.io.in_uop.bits.bp_xcpt_if, issue_slots[22].in_uop.bits.bp_xcpt_if connect slots_22.io.in_uop.bits.bp_debug_if, issue_slots[22].in_uop.bits.bp_debug_if connect slots_22.io.in_uop.bits.xcpt_ma_if, issue_slots[22].in_uop.bits.xcpt_ma_if connect slots_22.io.in_uop.bits.xcpt_ae_if, issue_slots[22].in_uop.bits.xcpt_ae_if connect slots_22.io.in_uop.bits.xcpt_pf_if, issue_slots[22].in_uop.bits.xcpt_pf_if connect slots_22.io.in_uop.bits.fp_single, issue_slots[22].in_uop.bits.fp_single connect slots_22.io.in_uop.bits.fp_val, issue_slots[22].in_uop.bits.fp_val connect slots_22.io.in_uop.bits.frs3_en, issue_slots[22].in_uop.bits.frs3_en connect slots_22.io.in_uop.bits.lrs2_rtype, issue_slots[22].in_uop.bits.lrs2_rtype connect slots_22.io.in_uop.bits.lrs1_rtype, issue_slots[22].in_uop.bits.lrs1_rtype connect slots_22.io.in_uop.bits.dst_rtype, issue_slots[22].in_uop.bits.dst_rtype connect slots_22.io.in_uop.bits.ldst_val, issue_slots[22].in_uop.bits.ldst_val connect slots_22.io.in_uop.bits.lrs3, issue_slots[22].in_uop.bits.lrs3 connect slots_22.io.in_uop.bits.lrs2, issue_slots[22].in_uop.bits.lrs2 connect slots_22.io.in_uop.bits.lrs1, issue_slots[22].in_uop.bits.lrs1 connect slots_22.io.in_uop.bits.ldst, issue_slots[22].in_uop.bits.ldst connect slots_22.io.in_uop.bits.ldst_is_rs1, issue_slots[22].in_uop.bits.ldst_is_rs1 connect slots_22.io.in_uop.bits.flush_on_commit, issue_slots[22].in_uop.bits.flush_on_commit connect slots_22.io.in_uop.bits.is_unique, issue_slots[22].in_uop.bits.is_unique connect slots_22.io.in_uop.bits.is_sys_pc2epc, issue_slots[22].in_uop.bits.is_sys_pc2epc connect slots_22.io.in_uop.bits.uses_stq, issue_slots[22].in_uop.bits.uses_stq connect slots_22.io.in_uop.bits.uses_ldq, issue_slots[22].in_uop.bits.uses_ldq connect slots_22.io.in_uop.bits.is_amo, issue_slots[22].in_uop.bits.is_amo connect slots_22.io.in_uop.bits.is_fencei, issue_slots[22].in_uop.bits.is_fencei connect slots_22.io.in_uop.bits.is_fence, issue_slots[22].in_uop.bits.is_fence connect slots_22.io.in_uop.bits.mem_signed, issue_slots[22].in_uop.bits.mem_signed connect slots_22.io.in_uop.bits.mem_size, issue_slots[22].in_uop.bits.mem_size connect slots_22.io.in_uop.bits.mem_cmd, issue_slots[22].in_uop.bits.mem_cmd connect slots_22.io.in_uop.bits.bypassable, issue_slots[22].in_uop.bits.bypassable connect slots_22.io.in_uop.bits.exc_cause, issue_slots[22].in_uop.bits.exc_cause connect slots_22.io.in_uop.bits.exception, issue_slots[22].in_uop.bits.exception connect slots_22.io.in_uop.bits.stale_pdst, issue_slots[22].in_uop.bits.stale_pdst connect slots_22.io.in_uop.bits.ppred_busy, issue_slots[22].in_uop.bits.ppred_busy connect slots_22.io.in_uop.bits.prs3_busy, issue_slots[22].in_uop.bits.prs3_busy connect slots_22.io.in_uop.bits.prs2_busy, issue_slots[22].in_uop.bits.prs2_busy connect slots_22.io.in_uop.bits.prs1_busy, issue_slots[22].in_uop.bits.prs1_busy connect slots_22.io.in_uop.bits.ppred, issue_slots[22].in_uop.bits.ppred connect slots_22.io.in_uop.bits.prs3, issue_slots[22].in_uop.bits.prs3 connect slots_22.io.in_uop.bits.prs2, issue_slots[22].in_uop.bits.prs2 connect slots_22.io.in_uop.bits.prs1, issue_slots[22].in_uop.bits.prs1 connect slots_22.io.in_uop.bits.pdst, issue_slots[22].in_uop.bits.pdst connect slots_22.io.in_uop.bits.rxq_idx, issue_slots[22].in_uop.bits.rxq_idx connect slots_22.io.in_uop.bits.stq_idx, issue_slots[22].in_uop.bits.stq_idx connect slots_22.io.in_uop.bits.ldq_idx, issue_slots[22].in_uop.bits.ldq_idx connect slots_22.io.in_uop.bits.rob_idx, issue_slots[22].in_uop.bits.rob_idx connect slots_22.io.in_uop.bits.csr_addr, issue_slots[22].in_uop.bits.csr_addr connect slots_22.io.in_uop.bits.imm_packed, issue_slots[22].in_uop.bits.imm_packed connect slots_22.io.in_uop.bits.taken, issue_slots[22].in_uop.bits.taken connect slots_22.io.in_uop.bits.pc_lob, issue_slots[22].in_uop.bits.pc_lob connect slots_22.io.in_uop.bits.edge_inst, issue_slots[22].in_uop.bits.edge_inst connect slots_22.io.in_uop.bits.ftq_idx, issue_slots[22].in_uop.bits.ftq_idx connect slots_22.io.in_uop.bits.br_tag, issue_slots[22].in_uop.bits.br_tag connect slots_22.io.in_uop.bits.br_mask, issue_slots[22].in_uop.bits.br_mask connect slots_22.io.in_uop.bits.is_sfb, issue_slots[22].in_uop.bits.is_sfb connect slots_22.io.in_uop.bits.is_jal, issue_slots[22].in_uop.bits.is_jal connect slots_22.io.in_uop.bits.is_jalr, issue_slots[22].in_uop.bits.is_jalr connect slots_22.io.in_uop.bits.is_br, issue_slots[22].in_uop.bits.is_br connect slots_22.io.in_uop.bits.iw_p2_poisoned, issue_slots[22].in_uop.bits.iw_p2_poisoned connect slots_22.io.in_uop.bits.iw_p1_poisoned, issue_slots[22].in_uop.bits.iw_p1_poisoned connect slots_22.io.in_uop.bits.iw_state, issue_slots[22].in_uop.bits.iw_state connect slots_22.io.in_uop.bits.ctrl.is_std, issue_slots[22].in_uop.bits.ctrl.is_std connect slots_22.io.in_uop.bits.ctrl.is_sta, issue_slots[22].in_uop.bits.ctrl.is_sta connect slots_22.io.in_uop.bits.ctrl.is_load, issue_slots[22].in_uop.bits.ctrl.is_load connect slots_22.io.in_uop.bits.ctrl.csr_cmd, issue_slots[22].in_uop.bits.ctrl.csr_cmd connect slots_22.io.in_uop.bits.ctrl.fcn_dw, issue_slots[22].in_uop.bits.ctrl.fcn_dw connect slots_22.io.in_uop.bits.ctrl.op_fcn, issue_slots[22].in_uop.bits.ctrl.op_fcn connect slots_22.io.in_uop.bits.ctrl.imm_sel, issue_slots[22].in_uop.bits.ctrl.imm_sel connect slots_22.io.in_uop.bits.ctrl.op2_sel, issue_slots[22].in_uop.bits.ctrl.op2_sel connect slots_22.io.in_uop.bits.ctrl.op1_sel, issue_slots[22].in_uop.bits.ctrl.op1_sel connect slots_22.io.in_uop.bits.ctrl.br_type, issue_slots[22].in_uop.bits.ctrl.br_type connect slots_22.io.in_uop.bits.fu_code, issue_slots[22].in_uop.bits.fu_code connect slots_22.io.in_uop.bits.iq_type, issue_slots[22].in_uop.bits.iq_type connect slots_22.io.in_uop.bits.debug_pc, issue_slots[22].in_uop.bits.debug_pc connect slots_22.io.in_uop.bits.is_rvc, issue_slots[22].in_uop.bits.is_rvc connect slots_22.io.in_uop.bits.debug_inst, issue_slots[22].in_uop.bits.debug_inst connect slots_22.io.in_uop.bits.inst, issue_slots[22].in_uop.bits.inst connect slots_22.io.in_uop.bits.uopc, issue_slots[22].in_uop.bits.uopc connect slots_22.io.in_uop.valid, issue_slots[22].in_uop.valid connect slots_22.io.spec_ld_wakeup[0].bits, issue_slots[22].spec_ld_wakeup[0].bits connect slots_22.io.spec_ld_wakeup[0].valid, issue_slots[22].spec_ld_wakeup[0].valid connect slots_22.io.pred_wakeup_port.bits, issue_slots[22].pred_wakeup_port.bits connect slots_22.io.pred_wakeup_port.valid, issue_slots[22].pred_wakeup_port.valid connect slots_22.io.wakeup_ports[0].bits.poisoned, issue_slots[22].wakeup_ports[0].bits.poisoned connect slots_22.io.wakeup_ports[0].bits.pdst, issue_slots[22].wakeup_ports[0].bits.pdst connect slots_22.io.wakeup_ports[0].valid, issue_slots[22].wakeup_ports[0].valid connect slots_22.io.wakeup_ports[1].bits.poisoned, issue_slots[22].wakeup_ports[1].bits.poisoned connect slots_22.io.wakeup_ports[1].bits.pdst, issue_slots[22].wakeup_ports[1].bits.pdst connect slots_22.io.wakeup_ports[1].valid, issue_slots[22].wakeup_ports[1].valid connect slots_22.io.wakeup_ports[2].bits.poisoned, issue_slots[22].wakeup_ports[2].bits.poisoned connect slots_22.io.wakeup_ports[2].bits.pdst, issue_slots[22].wakeup_ports[2].bits.pdst connect slots_22.io.wakeup_ports[2].valid, issue_slots[22].wakeup_ports[2].valid connect slots_22.io.wakeup_ports[3].bits.poisoned, issue_slots[22].wakeup_ports[3].bits.poisoned connect slots_22.io.wakeup_ports[3].bits.pdst, issue_slots[22].wakeup_ports[3].bits.pdst connect slots_22.io.wakeup_ports[3].valid, issue_slots[22].wakeup_ports[3].valid connect slots_22.io.wakeup_ports[4].bits.poisoned, issue_slots[22].wakeup_ports[4].bits.poisoned connect slots_22.io.wakeup_ports[4].bits.pdst, issue_slots[22].wakeup_ports[4].bits.pdst connect slots_22.io.wakeup_ports[4].valid, issue_slots[22].wakeup_ports[4].valid connect slots_22.io.wakeup_ports[5].bits.poisoned, issue_slots[22].wakeup_ports[5].bits.poisoned connect slots_22.io.wakeup_ports[5].bits.pdst, issue_slots[22].wakeup_ports[5].bits.pdst connect slots_22.io.wakeup_ports[5].valid, issue_slots[22].wakeup_ports[5].valid connect slots_22.io.wakeup_ports[6].bits.poisoned, issue_slots[22].wakeup_ports[6].bits.poisoned connect slots_22.io.wakeup_ports[6].bits.pdst, issue_slots[22].wakeup_ports[6].bits.pdst connect slots_22.io.wakeup_ports[6].valid, issue_slots[22].wakeup_ports[6].valid connect slots_22.io.ldspec_miss, issue_slots[22].ldspec_miss connect slots_22.io.clear, issue_slots[22].clear connect slots_22.io.kill, issue_slots[22].kill connect slots_22.io.brupdate.b2.target_offset, issue_slots[22].brupdate.b2.target_offset connect slots_22.io.brupdate.b2.jalr_target, issue_slots[22].brupdate.b2.jalr_target connect slots_22.io.brupdate.b2.pc_sel, issue_slots[22].brupdate.b2.pc_sel connect slots_22.io.brupdate.b2.cfi_type, issue_slots[22].brupdate.b2.cfi_type connect slots_22.io.brupdate.b2.taken, issue_slots[22].brupdate.b2.taken connect slots_22.io.brupdate.b2.mispredict, issue_slots[22].brupdate.b2.mispredict connect slots_22.io.brupdate.b2.valid, issue_slots[22].brupdate.b2.valid connect slots_22.io.brupdate.b2.uop.debug_tsrc, issue_slots[22].brupdate.b2.uop.debug_tsrc connect slots_22.io.brupdate.b2.uop.debug_fsrc, issue_slots[22].brupdate.b2.uop.debug_fsrc connect slots_22.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[22].brupdate.b2.uop.bp_xcpt_if connect slots_22.io.brupdate.b2.uop.bp_debug_if, issue_slots[22].brupdate.b2.uop.bp_debug_if connect slots_22.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[22].brupdate.b2.uop.xcpt_ma_if connect slots_22.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[22].brupdate.b2.uop.xcpt_ae_if connect slots_22.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[22].brupdate.b2.uop.xcpt_pf_if connect slots_22.io.brupdate.b2.uop.fp_single, issue_slots[22].brupdate.b2.uop.fp_single connect slots_22.io.brupdate.b2.uop.fp_val, issue_slots[22].brupdate.b2.uop.fp_val connect slots_22.io.brupdate.b2.uop.frs3_en, issue_slots[22].brupdate.b2.uop.frs3_en connect slots_22.io.brupdate.b2.uop.lrs2_rtype, issue_slots[22].brupdate.b2.uop.lrs2_rtype connect slots_22.io.brupdate.b2.uop.lrs1_rtype, issue_slots[22].brupdate.b2.uop.lrs1_rtype connect slots_22.io.brupdate.b2.uop.dst_rtype, issue_slots[22].brupdate.b2.uop.dst_rtype connect slots_22.io.brupdate.b2.uop.ldst_val, issue_slots[22].brupdate.b2.uop.ldst_val connect slots_22.io.brupdate.b2.uop.lrs3, issue_slots[22].brupdate.b2.uop.lrs3 connect slots_22.io.brupdate.b2.uop.lrs2, issue_slots[22].brupdate.b2.uop.lrs2 connect slots_22.io.brupdate.b2.uop.lrs1, issue_slots[22].brupdate.b2.uop.lrs1 connect slots_22.io.brupdate.b2.uop.ldst, issue_slots[22].brupdate.b2.uop.ldst connect slots_22.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[22].brupdate.b2.uop.ldst_is_rs1 connect slots_22.io.brupdate.b2.uop.flush_on_commit, issue_slots[22].brupdate.b2.uop.flush_on_commit connect slots_22.io.brupdate.b2.uop.is_unique, issue_slots[22].brupdate.b2.uop.is_unique connect slots_22.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[22].brupdate.b2.uop.is_sys_pc2epc connect slots_22.io.brupdate.b2.uop.uses_stq, issue_slots[22].brupdate.b2.uop.uses_stq connect slots_22.io.brupdate.b2.uop.uses_ldq, issue_slots[22].brupdate.b2.uop.uses_ldq connect slots_22.io.brupdate.b2.uop.is_amo, issue_slots[22].brupdate.b2.uop.is_amo connect slots_22.io.brupdate.b2.uop.is_fencei, issue_slots[22].brupdate.b2.uop.is_fencei connect slots_22.io.brupdate.b2.uop.is_fence, issue_slots[22].brupdate.b2.uop.is_fence connect slots_22.io.brupdate.b2.uop.mem_signed, issue_slots[22].brupdate.b2.uop.mem_signed connect slots_22.io.brupdate.b2.uop.mem_size, issue_slots[22].brupdate.b2.uop.mem_size connect slots_22.io.brupdate.b2.uop.mem_cmd, issue_slots[22].brupdate.b2.uop.mem_cmd connect slots_22.io.brupdate.b2.uop.bypassable, issue_slots[22].brupdate.b2.uop.bypassable connect slots_22.io.brupdate.b2.uop.exc_cause, issue_slots[22].brupdate.b2.uop.exc_cause connect slots_22.io.brupdate.b2.uop.exception, issue_slots[22].brupdate.b2.uop.exception connect slots_22.io.brupdate.b2.uop.stale_pdst, issue_slots[22].brupdate.b2.uop.stale_pdst connect slots_22.io.brupdate.b2.uop.ppred_busy, issue_slots[22].brupdate.b2.uop.ppred_busy connect slots_22.io.brupdate.b2.uop.prs3_busy, issue_slots[22].brupdate.b2.uop.prs3_busy connect slots_22.io.brupdate.b2.uop.prs2_busy, issue_slots[22].brupdate.b2.uop.prs2_busy connect slots_22.io.brupdate.b2.uop.prs1_busy, issue_slots[22].brupdate.b2.uop.prs1_busy connect slots_22.io.brupdate.b2.uop.ppred, issue_slots[22].brupdate.b2.uop.ppred connect slots_22.io.brupdate.b2.uop.prs3, issue_slots[22].brupdate.b2.uop.prs3 connect slots_22.io.brupdate.b2.uop.prs2, issue_slots[22].brupdate.b2.uop.prs2 connect slots_22.io.brupdate.b2.uop.prs1, issue_slots[22].brupdate.b2.uop.prs1 connect slots_22.io.brupdate.b2.uop.pdst, issue_slots[22].brupdate.b2.uop.pdst connect slots_22.io.brupdate.b2.uop.rxq_idx, issue_slots[22].brupdate.b2.uop.rxq_idx connect slots_22.io.brupdate.b2.uop.stq_idx, issue_slots[22].brupdate.b2.uop.stq_idx connect slots_22.io.brupdate.b2.uop.ldq_idx, issue_slots[22].brupdate.b2.uop.ldq_idx connect slots_22.io.brupdate.b2.uop.rob_idx, issue_slots[22].brupdate.b2.uop.rob_idx connect slots_22.io.brupdate.b2.uop.csr_addr, issue_slots[22].brupdate.b2.uop.csr_addr connect slots_22.io.brupdate.b2.uop.imm_packed, issue_slots[22].brupdate.b2.uop.imm_packed connect slots_22.io.brupdate.b2.uop.taken, issue_slots[22].brupdate.b2.uop.taken connect slots_22.io.brupdate.b2.uop.pc_lob, issue_slots[22].brupdate.b2.uop.pc_lob connect slots_22.io.brupdate.b2.uop.edge_inst, issue_slots[22].brupdate.b2.uop.edge_inst connect slots_22.io.brupdate.b2.uop.ftq_idx, issue_slots[22].brupdate.b2.uop.ftq_idx connect slots_22.io.brupdate.b2.uop.br_tag, issue_slots[22].brupdate.b2.uop.br_tag connect slots_22.io.brupdate.b2.uop.br_mask, issue_slots[22].brupdate.b2.uop.br_mask connect slots_22.io.brupdate.b2.uop.is_sfb, issue_slots[22].brupdate.b2.uop.is_sfb connect slots_22.io.brupdate.b2.uop.is_jal, issue_slots[22].brupdate.b2.uop.is_jal connect slots_22.io.brupdate.b2.uop.is_jalr, issue_slots[22].brupdate.b2.uop.is_jalr connect slots_22.io.brupdate.b2.uop.is_br, issue_slots[22].brupdate.b2.uop.is_br connect slots_22.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[22].brupdate.b2.uop.iw_p2_poisoned connect slots_22.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[22].brupdate.b2.uop.iw_p1_poisoned connect slots_22.io.brupdate.b2.uop.iw_state, issue_slots[22].brupdate.b2.uop.iw_state connect slots_22.io.brupdate.b2.uop.ctrl.is_std, issue_slots[22].brupdate.b2.uop.ctrl.is_std connect slots_22.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[22].brupdate.b2.uop.ctrl.is_sta connect slots_22.io.brupdate.b2.uop.ctrl.is_load, issue_slots[22].brupdate.b2.uop.ctrl.is_load connect slots_22.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[22].brupdate.b2.uop.ctrl.csr_cmd connect slots_22.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[22].brupdate.b2.uop.ctrl.fcn_dw connect slots_22.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[22].brupdate.b2.uop.ctrl.op_fcn connect slots_22.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[22].brupdate.b2.uop.ctrl.imm_sel connect slots_22.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[22].brupdate.b2.uop.ctrl.op2_sel connect slots_22.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[22].brupdate.b2.uop.ctrl.op1_sel connect slots_22.io.brupdate.b2.uop.ctrl.br_type, issue_slots[22].brupdate.b2.uop.ctrl.br_type connect slots_22.io.brupdate.b2.uop.fu_code, issue_slots[22].brupdate.b2.uop.fu_code connect slots_22.io.brupdate.b2.uop.iq_type, issue_slots[22].brupdate.b2.uop.iq_type connect slots_22.io.brupdate.b2.uop.debug_pc, issue_slots[22].brupdate.b2.uop.debug_pc connect slots_22.io.brupdate.b2.uop.is_rvc, issue_slots[22].brupdate.b2.uop.is_rvc connect slots_22.io.brupdate.b2.uop.debug_inst, issue_slots[22].brupdate.b2.uop.debug_inst connect slots_22.io.brupdate.b2.uop.inst, issue_slots[22].brupdate.b2.uop.inst connect slots_22.io.brupdate.b2.uop.uopc, issue_slots[22].brupdate.b2.uop.uopc connect slots_22.io.brupdate.b1.mispredict_mask, issue_slots[22].brupdate.b1.mispredict_mask connect slots_22.io.brupdate.b1.resolve_mask, issue_slots[22].brupdate.b1.resolve_mask connect slots_22.io.grant, issue_slots[22].grant connect issue_slots[22].request_hp, slots_22.io.request_hp connect issue_slots[22].request, slots_22.io.request connect issue_slots[22].will_be_valid, slots_22.io.will_be_valid connect issue_slots[22].valid, slots_22.io.valid connect issue_slots[23].debug.state, slots_23.io.debug.state connect issue_slots[23].debug.ppred, slots_23.io.debug.ppred connect issue_slots[23].debug.p3, slots_23.io.debug.p3 connect issue_slots[23].debug.p2, slots_23.io.debug.p2 connect issue_slots[23].debug.p1, slots_23.io.debug.p1 connect issue_slots[23].uop.debug_tsrc, slots_23.io.uop.debug_tsrc connect issue_slots[23].uop.debug_fsrc, slots_23.io.uop.debug_fsrc connect issue_slots[23].uop.bp_xcpt_if, slots_23.io.uop.bp_xcpt_if connect issue_slots[23].uop.bp_debug_if, slots_23.io.uop.bp_debug_if connect issue_slots[23].uop.xcpt_ma_if, slots_23.io.uop.xcpt_ma_if connect issue_slots[23].uop.xcpt_ae_if, slots_23.io.uop.xcpt_ae_if connect issue_slots[23].uop.xcpt_pf_if, slots_23.io.uop.xcpt_pf_if connect issue_slots[23].uop.fp_single, slots_23.io.uop.fp_single connect issue_slots[23].uop.fp_val, slots_23.io.uop.fp_val connect issue_slots[23].uop.frs3_en, slots_23.io.uop.frs3_en connect issue_slots[23].uop.lrs2_rtype, slots_23.io.uop.lrs2_rtype connect issue_slots[23].uop.lrs1_rtype, slots_23.io.uop.lrs1_rtype connect issue_slots[23].uop.dst_rtype, slots_23.io.uop.dst_rtype connect issue_slots[23].uop.ldst_val, slots_23.io.uop.ldst_val connect issue_slots[23].uop.lrs3, slots_23.io.uop.lrs3 connect issue_slots[23].uop.lrs2, slots_23.io.uop.lrs2 connect issue_slots[23].uop.lrs1, slots_23.io.uop.lrs1 connect issue_slots[23].uop.ldst, slots_23.io.uop.ldst connect issue_slots[23].uop.ldst_is_rs1, slots_23.io.uop.ldst_is_rs1 connect issue_slots[23].uop.flush_on_commit, slots_23.io.uop.flush_on_commit connect issue_slots[23].uop.is_unique, slots_23.io.uop.is_unique connect issue_slots[23].uop.is_sys_pc2epc, slots_23.io.uop.is_sys_pc2epc connect issue_slots[23].uop.uses_stq, slots_23.io.uop.uses_stq connect issue_slots[23].uop.uses_ldq, slots_23.io.uop.uses_ldq connect issue_slots[23].uop.is_amo, slots_23.io.uop.is_amo connect issue_slots[23].uop.is_fencei, slots_23.io.uop.is_fencei connect issue_slots[23].uop.is_fence, slots_23.io.uop.is_fence connect issue_slots[23].uop.mem_signed, slots_23.io.uop.mem_signed connect issue_slots[23].uop.mem_size, slots_23.io.uop.mem_size connect issue_slots[23].uop.mem_cmd, slots_23.io.uop.mem_cmd connect issue_slots[23].uop.bypassable, slots_23.io.uop.bypassable connect issue_slots[23].uop.exc_cause, slots_23.io.uop.exc_cause connect issue_slots[23].uop.exception, slots_23.io.uop.exception connect issue_slots[23].uop.stale_pdst, slots_23.io.uop.stale_pdst connect issue_slots[23].uop.ppred_busy, slots_23.io.uop.ppred_busy connect issue_slots[23].uop.prs3_busy, slots_23.io.uop.prs3_busy connect issue_slots[23].uop.prs2_busy, slots_23.io.uop.prs2_busy connect issue_slots[23].uop.prs1_busy, slots_23.io.uop.prs1_busy connect issue_slots[23].uop.ppred, slots_23.io.uop.ppred connect issue_slots[23].uop.prs3, slots_23.io.uop.prs3 connect issue_slots[23].uop.prs2, slots_23.io.uop.prs2 connect issue_slots[23].uop.prs1, slots_23.io.uop.prs1 connect issue_slots[23].uop.pdst, slots_23.io.uop.pdst connect issue_slots[23].uop.rxq_idx, slots_23.io.uop.rxq_idx connect issue_slots[23].uop.stq_idx, slots_23.io.uop.stq_idx connect issue_slots[23].uop.ldq_idx, slots_23.io.uop.ldq_idx connect issue_slots[23].uop.rob_idx, slots_23.io.uop.rob_idx connect issue_slots[23].uop.csr_addr, slots_23.io.uop.csr_addr connect issue_slots[23].uop.imm_packed, slots_23.io.uop.imm_packed connect issue_slots[23].uop.taken, slots_23.io.uop.taken connect issue_slots[23].uop.pc_lob, slots_23.io.uop.pc_lob connect issue_slots[23].uop.edge_inst, slots_23.io.uop.edge_inst connect issue_slots[23].uop.ftq_idx, slots_23.io.uop.ftq_idx connect issue_slots[23].uop.br_tag, slots_23.io.uop.br_tag connect issue_slots[23].uop.br_mask, slots_23.io.uop.br_mask connect issue_slots[23].uop.is_sfb, slots_23.io.uop.is_sfb connect issue_slots[23].uop.is_jal, slots_23.io.uop.is_jal connect issue_slots[23].uop.is_jalr, slots_23.io.uop.is_jalr connect issue_slots[23].uop.is_br, slots_23.io.uop.is_br connect issue_slots[23].uop.iw_p2_poisoned, slots_23.io.uop.iw_p2_poisoned connect issue_slots[23].uop.iw_p1_poisoned, slots_23.io.uop.iw_p1_poisoned connect issue_slots[23].uop.iw_state, slots_23.io.uop.iw_state connect issue_slots[23].uop.ctrl.is_std, slots_23.io.uop.ctrl.is_std connect issue_slots[23].uop.ctrl.is_sta, slots_23.io.uop.ctrl.is_sta connect issue_slots[23].uop.ctrl.is_load, slots_23.io.uop.ctrl.is_load connect issue_slots[23].uop.ctrl.csr_cmd, slots_23.io.uop.ctrl.csr_cmd connect issue_slots[23].uop.ctrl.fcn_dw, slots_23.io.uop.ctrl.fcn_dw connect issue_slots[23].uop.ctrl.op_fcn, slots_23.io.uop.ctrl.op_fcn connect issue_slots[23].uop.ctrl.imm_sel, slots_23.io.uop.ctrl.imm_sel connect issue_slots[23].uop.ctrl.op2_sel, slots_23.io.uop.ctrl.op2_sel connect issue_slots[23].uop.ctrl.op1_sel, slots_23.io.uop.ctrl.op1_sel connect issue_slots[23].uop.ctrl.br_type, slots_23.io.uop.ctrl.br_type connect issue_slots[23].uop.fu_code, slots_23.io.uop.fu_code connect issue_slots[23].uop.iq_type, slots_23.io.uop.iq_type connect issue_slots[23].uop.debug_pc, slots_23.io.uop.debug_pc connect issue_slots[23].uop.is_rvc, slots_23.io.uop.is_rvc connect issue_slots[23].uop.debug_inst, slots_23.io.uop.debug_inst connect issue_slots[23].uop.inst, slots_23.io.uop.inst connect issue_slots[23].uop.uopc, slots_23.io.uop.uopc connect issue_slots[23].out_uop.debug_tsrc, slots_23.io.out_uop.debug_tsrc connect issue_slots[23].out_uop.debug_fsrc, slots_23.io.out_uop.debug_fsrc connect issue_slots[23].out_uop.bp_xcpt_if, slots_23.io.out_uop.bp_xcpt_if connect issue_slots[23].out_uop.bp_debug_if, slots_23.io.out_uop.bp_debug_if connect issue_slots[23].out_uop.xcpt_ma_if, slots_23.io.out_uop.xcpt_ma_if connect issue_slots[23].out_uop.xcpt_ae_if, slots_23.io.out_uop.xcpt_ae_if connect issue_slots[23].out_uop.xcpt_pf_if, slots_23.io.out_uop.xcpt_pf_if connect issue_slots[23].out_uop.fp_single, slots_23.io.out_uop.fp_single connect issue_slots[23].out_uop.fp_val, slots_23.io.out_uop.fp_val connect issue_slots[23].out_uop.frs3_en, slots_23.io.out_uop.frs3_en connect issue_slots[23].out_uop.lrs2_rtype, slots_23.io.out_uop.lrs2_rtype connect issue_slots[23].out_uop.lrs1_rtype, slots_23.io.out_uop.lrs1_rtype connect issue_slots[23].out_uop.dst_rtype, slots_23.io.out_uop.dst_rtype connect issue_slots[23].out_uop.ldst_val, slots_23.io.out_uop.ldst_val connect issue_slots[23].out_uop.lrs3, slots_23.io.out_uop.lrs3 connect issue_slots[23].out_uop.lrs2, slots_23.io.out_uop.lrs2 connect issue_slots[23].out_uop.lrs1, slots_23.io.out_uop.lrs1 connect issue_slots[23].out_uop.ldst, slots_23.io.out_uop.ldst connect issue_slots[23].out_uop.ldst_is_rs1, slots_23.io.out_uop.ldst_is_rs1 connect issue_slots[23].out_uop.flush_on_commit, slots_23.io.out_uop.flush_on_commit connect issue_slots[23].out_uop.is_unique, slots_23.io.out_uop.is_unique connect issue_slots[23].out_uop.is_sys_pc2epc, slots_23.io.out_uop.is_sys_pc2epc connect issue_slots[23].out_uop.uses_stq, slots_23.io.out_uop.uses_stq connect issue_slots[23].out_uop.uses_ldq, slots_23.io.out_uop.uses_ldq connect issue_slots[23].out_uop.is_amo, slots_23.io.out_uop.is_amo connect issue_slots[23].out_uop.is_fencei, slots_23.io.out_uop.is_fencei connect issue_slots[23].out_uop.is_fence, slots_23.io.out_uop.is_fence connect issue_slots[23].out_uop.mem_signed, slots_23.io.out_uop.mem_signed connect issue_slots[23].out_uop.mem_size, slots_23.io.out_uop.mem_size connect issue_slots[23].out_uop.mem_cmd, slots_23.io.out_uop.mem_cmd connect issue_slots[23].out_uop.bypassable, slots_23.io.out_uop.bypassable connect issue_slots[23].out_uop.exc_cause, slots_23.io.out_uop.exc_cause connect issue_slots[23].out_uop.exception, slots_23.io.out_uop.exception connect issue_slots[23].out_uop.stale_pdst, slots_23.io.out_uop.stale_pdst connect issue_slots[23].out_uop.ppred_busy, slots_23.io.out_uop.ppred_busy connect issue_slots[23].out_uop.prs3_busy, slots_23.io.out_uop.prs3_busy connect issue_slots[23].out_uop.prs2_busy, slots_23.io.out_uop.prs2_busy connect issue_slots[23].out_uop.prs1_busy, slots_23.io.out_uop.prs1_busy connect issue_slots[23].out_uop.ppred, slots_23.io.out_uop.ppred connect issue_slots[23].out_uop.prs3, slots_23.io.out_uop.prs3 connect issue_slots[23].out_uop.prs2, slots_23.io.out_uop.prs2 connect issue_slots[23].out_uop.prs1, slots_23.io.out_uop.prs1 connect issue_slots[23].out_uop.pdst, slots_23.io.out_uop.pdst connect issue_slots[23].out_uop.rxq_idx, slots_23.io.out_uop.rxq_idx connect issue_slots[23].out_uop.stq_idx, slots_23.io.out_uop.stq_idx connect issue_slots[23].out_uop.ldq_idx, slots_23.io.out_uop.ldq_idx connect issue_slots[23].out_uop.rob_idx, slots_23.io.out_uop.rob_idx connect issue_slots[23].out_uop.csr_addr, slots_23.io.out_uop.csr_addr connect issue_slots[23].out_uop.imm_packed, slots_23.io.out_uop.imm_packed connect issue_slots[23].out_uop.taken, slots_23.io.out_uop.taken connect issue_slots[23].out_uop.pc_lob, slots_23.io.out_uop.pc_lob connect issue_slots[23].out_uop.edge_inst, slots_23.io.out_uop.edge_inst connect issue_slots[23].out_uop.ftq_idx, slots_23.io.out_uop.ftq_idx connect issue_slots[23].out_uop.br_tag, slots_23.io.out_uop.br_tag connect issue_slots[23].out_uop.br_mask, slots_23.io.out_uop.br_mask connect issue_slots[23].out_uop.is_sfb, slots_23.io.out_uop.is_sfb connect issue_slots[23].out_uop.is_jal, slots_23.io.out_uop.is_jal connect issue_slots[23].out_uop.is_jalr, slots_23.io.out_uop.is_jalr connect issue_slots[23].out_uop.is_br, slots_23.io.out_uop.is_br connect issue_slots[23].out_uop.iw_p2_poisoned, slots_23.io.out_uop.iw_p2_poisoned connect issue_slots[23].out_uop.iw_p1_poisoned, slots_23.io.out_uop.iw_p1_poisoned connect issue_slots[23].out_uop.iw_state, slots_23.io.out_uop.iw_state connect issue_slots[23].out_uop.ctrl.is_std, slots_23.io.out_uop.ctrl.is_std connect issue_slots[23].out_uop.ctrl.is_sta, slots_23.io.out_uop.ctrl.is_sta connect issue_slots[23].out_uop.ctrl.is_load, slots_23.io.out_uop.ctrl.is_load connect issue_slots[23].out_uop.ctrl.csr_cmd, slots_23.io.out_uop.ctrl.csr_cmd connect issue_slots[23].out_uop.ctrl.fcn_dw, slots_23.io.out_uop.ctrl.fcn_dw connect issue_slots[23].out_uop.ctrl.op_fcn, slots_23.io.out_uop.ctrl.op_fcn connect issue_slots[23].out_uop.ctrl.imm_sel, slots_23.io.out_uop.ctrl.imm_sel connect issue_slots[23].out_uop.ctrl.op2_sel, slots_23.io.out_uop.ctrl.op2_sel connect issue_slots[23].out_uop.ctrl.op1_sel, slots_23.io.out_uop.ctrl.op1_sel connect issue_slots[23].out_uop.ctrl.br_type, slots_23.io.out_uop.ctrl.br_type connect issue_slots[23].out_uop.fu_code, slots_23.io.out_uop.fu_code connect issue_slots[23].out_uop.iq_type, slots_23.io.out_uop.iq_type connect issue_slots[23].out_uop.debug_pc, slots_23.io.out_uop.debug_pc connect issue_slots[23].out_uop.is_rvc, slots_23.io.out_uop.is_rvc connect issue_slots[23].out_uop.debug_inst, slots_23.io.out_uop.debug_inst connect issue_slots[23].out_uop.inst, slots_23.io.out_uop.inst connect issue_slots[23].out_uop.uopc, slots_23.io.out_uop.uopc connect slots_23.io.in_uop.bits.debug_tsrc, issue_slots[23].in_uop.bits.debug_tsrc connect slots_23.io.in_uop.bits.debug_fsrc, issue_slots[23].in_uop.bits.debug_fsrc connect slots_23.io.in_uop.bits.bp_xcpt_if, issue_slots[23].in_uop.bits.bp_xcpt_if connect slots_23.io.in_uop.bits.bp_debug_if, issue_slots[23].in_uop.bits.bp_debug_if connect slots_23.io.in_uop.bits.xcpt_ma_if, issue_slots[23].in_uop.bits.xcpt_ma_if connect slots_23.io.in_uop.bits.xcpt_ae_if, issue_slots[23].in_uop.bits.xcpt_ae_if connect slots_23.io.in_uop.bits.xcpt_pf_if, issue_slots[23].in_uop.bits.xcpt_pf_if connect slots_23.io.in_uop.bits.fp_single, issue_slots[23].in_uop.bits.fp_single connect slots_23.io.in_uop.bits.fp_val, issue_slots[23].in_uop.bits.fp_val connect slots_23.io.in_uop.bits.frs3_en, issue_slots[23].in_uop.bits.frs3_en connect slots_23.io.in_uop.bits.lrs2_rtype, issue_slots[23].in_uop.bits.lrs2_rtype connect slots_23.io.in_uop.bits.lrs1_rtype, issue_slots[23].in_uop.bits.lrs1_rtype connect slots_23.io.in_uop.bits.dst_rtype, issue_slots[23].in_uop.bits.dst_rtype connect slots_23.io.in_uop.bits.ldst_val, issue_slots[23].in_uop.bits.ldst_val connect slots_23.io.in_uop.bits.lrs3, issue_slots[23].in_uop.bits.lrs3 connect slots_23.io.in_uop.bits.lrs2, issue_slots[23].in_uop.bits.lrs2 connect slots_23.io.in_uop.bits.lrs1, issue_slots[23].in_uop.bits.lrs1 connect slots_23.io.in_uop.bits.ldst, issue_slots[23].in_uop.bits.ldst connect slots_23.io.in_uop.bits.ldst_is_rs1, issue_slots[23].in_uop.bits.ldst_is_rs1 connect slots_23.io.in_uop.bits.flush_on_commit, issue_slots[23].in_uop.bits.flush_on_commit connect slots_23.io.in_uop.bits.is_unique, issue_slots[23].in_uop.bits.is_unique connect slots_23.io.in_uop.bits.is_sys_pc2epc, issue_slots[23].in_uop.bits.is_sys_pc2epc connect slots_23.io.in_uop.bits.uses_stq, issue_slots[23].in_uop.bits.uses_stq connect slots_23.io.in_uop.bits.uses_ldq, issue_slots[23].in_uop.bits.uses_ldq connect slots_23.io.in_uop.bits.is_amo, issue_slots[23].in_uop.bits.is_amo connect slots_23.io.in_uop.bits.is_fencei, issue_slots[23].in_uop.bits.is_fencei connect slots_23.io.in_uop.bits.is_fence, issue_slots[23].in_uop.bits.is_fence connect slots_23.io.in_uop.bits.mem_signed, issue_slots[23].in_uop.bits.mem_signed connect slots_23.io.in_uop.bits.mem_size, issue_slots[23].in_uop.bits.mem_size connect slots_23.io.in_uop.bits.mem_cmd, issue_slots[23].in_uop.bits.mem_cmd connect slots_23.io.in_uop.bits.bypassable, issue_slots[23].in_uop.bits.bypassable connect slots_23.io.in_uop.bits.exc_cause, issue_slots[23].in_uop.bits.exc_cause connect slots_23.io.in_uop.bits.exception, issue_slots[23].in_uop.bits.exception connect slots_23.io.in_uop.bits.stale_pdst, issue_slots[23].in_uop.bits.stale_pdst connect slots_23.io.in_uop.bits.ppred_busy, issue_slots[23].in_uop.bits.ppred_busy connect slots_23.io.in_uop.bits.prs3_busy, issue_slots[23].in_uop.bits.prs3_busy connect slots_23.io.in_uop.bits.prs2_busy, issue_slots[23].in_uop.bits.prs2_busy connect slots_23.io.in_uop.bits.prs1_busy, issue_slots[23].in_uop.bits.prs1_busy connect slots_23.io.in_uop.bits.ppred, issue_slots[23].in_uop.bits.ppred connect slots_23.io.in_uop.bits.prs3, issue_slots[23].in_uop.bits.prs3 connect slots_23.io.in_uop.bits.prs2, issue_slots[23].in_uop.bits.prs2 connect slots_23.io.in_uop.bits.prs1, issue_slots[23].in_uop.bits.prs1 connect slots_23.io.in_uop.bits.pdst, issue_slots[23].in_uop.bits.pdst connect slots_23.io.in_uop.bits.rxq_idx, issue_slots[23].in_uop.bits.rxq_idx connect slots_23.io.in_uop.bits.stq_idx, issue_slots[23].in_uop.bits.stq_idx connect slots_23.io.in_uop.bits.ldq_idx, issue_slots[23].in_uop.bits.ldq_idx connect slots_23.io.in_uop.bits.rob_idx, issue_slots[23].in_uop.bits.rob_idx connect slots_23.io.in_uop.bits.csr_addr, issue_slots[23].in_uop.bits.csr_addr connect slots_23.io.in_uop.bits.imm_packed, issue_slots[23].in_uop.bits.imm_packed connect slots_23.io.in_uop.bits.taken, issue_slots[23].in_uop.bits.taken connect slots_23.io.in_uop.bits.pc_lob, issue_slots[23].in_uop.bits.pc_lob connect slots_23.io.in_uop.bits.edge_inst, issue_slots[23].in_uop.bits.edge_inst connect slots_23.io.in_uop.bits.ftq_idx, issue_slots[23].in_uop.bits.ftq_idx connect slots_23.io.in_uop.bits.br_tag, issue_slots[23].in_uop.bits.br_tag connect slots_23.io.in_uop.bits.br_mask, issue_slots[23].in_uop.bits.br_mask connect slots_23.io.in_uop.bits.is_sfb, issue_slots[23].in_uop.bits.is_sfb connect slots_23.io.in_uop.bits.is_jal, issue_slots[23].in_uop.bits.is_jal connect slots_23.io.in_uop.bits.is_jalr, issue_slots[23].in_uop.bits.is_jalr connect slots_23.io.in_uop.bits.is_br, issue_slots[23].in_uop.bits.is_br connect slots_23.io.in_uop.bits.iw_p2_poisoned, issue_slots[23].in_uop.bits.iw_p2_poisoned connect slots_23.io.in_uop.bits.iw_p1_poisoned, issue_slots[23].in_uop.bits.iw_p1_poisoned connect slots_23.io.in_uop.bits.iw_state, issue_slots[23].in_uop.bits.iw_state connect slots_23.io.in_uop.bits.ctrl.is_std, issue_slots[23].in_uop.bits.ctrl.is_std connect slots_23.io.in_uop.bits.ctrl.is_sta, issue_slots[23].in_uop.bits.ctrl.is_sta connect slots_23.io.in_uop.bits.ctrl.is_load, issue_slots[23].in_uop.bits.ctrl.is_load connect slots_23.io.in_uop.bits.ctrl.csr_cmd, issue_slots[23].in_uop.bits.ctrl.csr_cmd connect slots_23.io.in_uop.bits.ctrl.fcn_dw, issue_slots[23].in_uop.bits.ctrl.fcn_dw connect slots_23.io.in_uop.bits.ctrl.op_fcn, issue_slots[23].in_uop.bits.ctrl.op_fcn connect slots_23.io.in_uop.bits.ctrl.imm_sel, issue_slots[23].in_uop.bits.ctrl.imm_sel connect slots_23.io.in_uop.bits.ctrl.op2_sel, issue_slots[23].in_uop.bits.ctrl.op2_sel connect slots_23.io.in_uop.bits.ctrl.op1_sel, issue_slots[23].in_uop.bits.ctrl.op1_sel connect slots_23.io.in_uop.bits.ctrl.br_type, issue_slots[23].in_uop.bits.ctrl.br_type connect slots_23.io.in_uop.bits.fu_code, issue_slots[23].in_uop.bits.fu_code connect slots_23.io.in_uop.bits.iq_type, issue_slots[23].in_uop.bits.iq_type connect slots_23.io.in_uop.bits.debug_pc, issue_slots[23].in_uop.bits.debug_pc connect slots_23.io.in_uop.bits.is_rvc, issue_slots[23].in_uop.bits.is_rvc connect slots_23.io.in_uop.bits.debug_inst, issue_slots[23].in_uop.bits.debug_inst connect slots_23.io.in_uop.bits.inst, issue_slots[23].in_uop.bits.inst connect slots_23.io.in_uop.bits.uopc, issue_slots[23].in_uop.bits.uopc connect slots_23.io.in_uop.valid, issue_slots[23].in_uop.valid connect slots_23.io.spec_ld_wakeup[0].bits, issue_slots[23].spec_ld_wakeup[0].bits connect slots_23.io.spec_ld_wakeup[0].valid, issue_slots[23].spec_ld_wakeup[0].valid connect slots_23.io.pred_wakeup_port.bits, issue_slots[23].pred_wakeup_port.bits connect slots_23.io.pred_wakeup_port.valid, issue_slots[23].pred_wakeup_port.valid connect slots_23.io.wakeup_ports[0].bits.poisoned, issue_slots[23].wakeup_ports[0].bits.poisoned connect slots_23.io.wakeup_ports[0].bits.pdst, issue_slots[23].wakeup_ports[0].bits.pdst connect slots_23.io.wakeup_ports[0].valid, issue_slots[23].wakeup_ports[0].valid connect slots_23.io.wakeup_ports[1].bits.poisoned, issue_slots[23].wakeup_ports[1].bits.poisoned connect slots_23.io.wakeup_ports[1].bits.pdst, issue_slots[23].wakeup_ports[1].bits.pdst connect slots_23.io.wakeup_ports[1].valid, issue_slots[23].wakeup_ports[1].valid connect slots_23.io.wakeup_ports[2].bits.poisoned, issue_slots[23].wakeup_ports[2].bits.poisoned connect slots_23.io.wakeup_ports[2].bits.pdst, issue_slots[23].wakeup_ports[2].bits.pdst connect slots_23.io.wakeup_ports[2].valid, issue_slots[23].wakeup_ports[2].valid connect slots_23.io.wakeup_ports[3].bits.poisoned, issue_slots[23].wakeup_ports[3].bits.poisoned connect slots_23.io.wakeup_ports[3].bits.pdst, issue_slots[23].wakeup_ports[3].bits.pdst connect slots_23.io.wakeup_ports[3].valid, issue_slots[23].wakeup_ports[3].valid connect slots_23.io.wakeup_ports[4].bits.poisoned, issue_slots[23].wakeup_ports[4].bits.poisoned connect slots_23.io.wakeup_ports[4].bits.pdst, issue_slots[23].wakeup_ports[4].bits.pdst connect slots_23.io.wakeup_ports[4].valid, issue_slots[23].wakeup_ports[4].valid connect slots_23.io.wakeup_ports[5].bits.poisoned, issue_slots[23].wakeup_ports[5].bits.poisoned connect slots_23.io.wakeup_ports[5].bits.pdst, issue_slots[23].wakeup_ports[5].bits.pdst connect slots_23.io.wakeup_ports[5].valid, issue_slots[23].wakeup_ports[5].valid connect slots_23.io.wakeup_ports[6].bits.poisoned, issue_slots[23].wakeup_ports[6].bits.poisoned connect slots_23.io.wakeup_ports[6].bits.pdst, issue_slots[23].wakeup_ports[6].bits.pdst connect slots_23.io.wakeup_ports[6].valid, issue_slots[23].wakeup_ports[6].valid connect slots_23.io.ldspec_miss, issue_slots[23].ldspec_miss connect slots_23.io.clear, issue_slots[23].clear connect slots_23.io.kill, issue_slots[23].kill connect slots_23.io.brupdate.b2.target_offset, issue_slots[23].brupdate.b2.target_offset connect slots_23.io.brupdate.b2.jalr_target, issue_slots[23].brupdate.b2.jalr_target connect slots_23.io.brupdate.b2.pc_sel, issue_slots[23].brupdate.b2.pc_sel connect slots_23.io.brupdate.b2.cfi_type, issue_slots[23].brupdate.b2.cfi_type connect slots_23.io.brupdate.b2.taken, issue_slots[23].brupdate.b2.taken connect slots_23.io.brupdate.b2.mispredict, issue_slots[23].brupdate.b2.mispredict connect slots_23.io.brupdate.b2.valid, issue_slots[23].brupdate.b2.valid connect slots_23.io.brupdate.b2.uop.debug_tsrc, issue_slots[23].brupdate.b2.uop.debug_tsrc connect slots_23.io.brupdate.b2.uop.debug_fsrc, issue_slots[23].brupdate.b2.uop.debug_fsrc connect slots_23.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[23].brupdate.b2.uop.bp_xcpt_if connect slots_23.io.brupdate.b2.uop.bp_debug_if, issue_slots[23].brupdate.b2.uop.bp_debug_if connect slots_23.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[23].brupdate.b2.uop.xcpt_ma_if connect slots_23.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[23].brupdate.b2.uop.xcpt_ae_if connect slots_23.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[23].brupdate.b2.uop.xcpt_pf_if connect slots_23.io.brupdate.b2.uop.fp_single, issue_slots[23].brupdate.b2.uop.fp_single connect slots_23.io.brupdate.b2.uop.fp_val, issue_slots[23].brupdate.b2.uop.fp_val connect slots_23.io.brupdate.b2.uop.frs3_en, issue_slots[23].brupdate.b2.uop.frs3_en connect slots_23.io.brupdate.b2.uop.lrs2_rtype, issue_slots[23].brupdate.b2.uop.lrs2_rtype connect slots_23.io.brupdate.b2.uop.lrs1_rtype, issue_slots[23].brupdate.b2.uop.lrs1_rtype connect slots_23.io.brupdate.b2.uop.dst_rtype, issue_slots[23].brupdate.b2.uop.dst_rtype connect slots_23.io.brupdate.b2.uop.ldst_val, issue_slots[23].brupdate.b2.uop.ldst_val connect slots_23.io.brupdate.b2.uop.lrs3, issue_slots[23].brupdate.b2.uop.lrs3 connect slots_23.io.brupdate.b2.uop.lrs2, issue_slots[23].brupdate.b2.uop.lrs2 connect slots_23.io.brupdate.b2.uop.lrs1, issue_slots[23].brupdate.b2.uop.lrs1 connect slots_23.io.brupdate.b2.uop.ldst, issue_slots[23].brupdate.b2.uop.ldst connect slots_23.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[23].brupdate.b2.uop.ldst_is_rs1 connect slots_23.io.brupdate.b2.uop.flush_on_commit, issue_slots[23].brupdate.b2.uop.flush_on_commit connect slots_23.io.brupdate.b2.uop.is_unique, issue_slots[23].brupdate.b2.uop.is_unique connect slots_23.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[23].brupdate.b2.uop.is_sys_pc2epc connect slots_23.io.brupdate.b2.uop.uses_stq, issue_slots[23].brupdate.b2.uop.uses_stq connect slots_23.io.brupdate.b2.uop.uses_ldq, issue_slots[23].brupdate.b2.uop.uses_ldq connect slots_23.io.brupdate.b2.uop.is_amo, issue_slots[23].brupdate.b2.uop.is_amo connect slots_23.io.brupdate.b2.uop.is_fencei, issue_slots[23].brupdate.b2.uop.is_fencei connect slots_23.io.brupdate.b2.uop.is_fence, issue_slots[23].brupdate.b2.uop.is_fence connect slots_23.io.brupdate.b2.uop.mem_signed, issue_slots[23].brupdate.b2.uop.mem_signed connect slots_23.io.brupdate.b2.uop.mem_size, issue_slots[23].brupdate.b2.uop.mem_size connect slots_23.io.brupdate.b2.uop.mem_cmd, issue_slots[23].brupdate.b2.uop.mem_cmd connect slots_23.io.brupdate.b2.uop.bypassable, issue_slots[23].brupdate.b2.uop.bypassable connect slots_23.io.brupdate.b2.uop.exc_cause, issue_slots[23].brupdate.b2.uop.exc_cause connect slots_23.io.brupdate.b2.uop.exception, issue_slots[23].brupdate.b2.uop.exception connect slots_23.io.brupdate.b2.uop.stale_pdst, issue_slots[23].brupdate.b2.uop.stale_pdst connect slots_23.io.brupdate.b2.uop.ppred_busy, issue_slots[23].brupdate.b2.uop.ppred_busy connect slots_23.io.brupdate.b2.uop.prs3_busy, issue_slots[23].brupdate.b2.uop.prs3_busy connect slots_23.io.brupdate.b2.uop.prs2_busy, issue_slots[23].brupdate.b2.uop.prs2_busy connect slots_23.io.brupdate.b2.uop.prs1_busy, issue_slots[23].brupdate.b2.uop.prs1_busy connect slots_23.io.brupdate.b2.uop.ppred, issue_slots[23].brupdate.b2.uop.ppred connect slots_23.io.brupdate.b2.uop.prs3, issue_slots[23].brupdate.b2.uop.prs3 connect slots_23.io.brupdate.b2.uop.prs2, issue_slots[23].brupdate.b2.uop.prs2 connect slots_23.io.brupdate.b2.uop.prs1, issue_slots[23].brupdate.b2.uop.prs1 connect slots_23.io.brupdate.b2.uop.pdst, issue_slots[23].brupdate.b2.uop.pdst connect slots_23.io.brupdate.b2.uop.rxq_idx, issue_slots[23].brupdate.b2.uop.rxq_idx connect slots_23.io.brupdate.b2.uop.stq_idx, issue_slots[23].brupdate.b2.uop.stq_idx connect slots_23.io.brupdate.b2.uop.ldq_idx, issue_slots[23].brupdate.b2.uop.ldq_idx connect slots_23.io.brupdate.b2.uop.rob_idx, issue_slots[23].brupdate.b2.uop.rob_idx connect slots_23.io.brupdate.b2.uop.csr_addr, issue_slots[23].brupdate.b2.uop.csr_addr connect slots_23.io.brupdate.b2.uop.imm_packed, issue_slots[23].brupdate.b2.uop.imm_packed connect slots_23.io.brupdate.b2.uop.taken, issue_slots[23].brupdate.b2.uop.taken connect slots_23.io.brupdate.b2.uop.pc_lob, issue_slots[23].brupdate.b2.uop.pc_lob connect slots_23.io.brupdate.b2.uop.edge_inst, issue_slots[23].brupdate.b2.uop.edge_inst connect slots_23.io.brupdate.b2.uop.ftq_idx, issue_slots[23].brupdate.b2.uop.ftq_idx connect slots_23.io.brupdate.b2.uop.br_tag, issue_slots[23].brupdate.b2.uop.br_tag connect slots_23.io.brupdate.b2.uop.br_mask, issue_slots[23].brupdate.b2.uop.br_mask connect slots_23.io.brupdate.b2.uop.is_sfb, issue_slots[23].brupdate.b2.uop.is_sfb connect slots_23.io.brupdate.b2.uop.is_jal, issue_slots[23].brupdate.b2.uop.is_jal connect slots_23.io.brupdate.b2.uop.is_jalr, issue_slots[23].brupdate.b2.uop.is_jalr connect slots_23.io.brupdate.b2.uop.is_br, issue_slots[23].brupdate.b2.uop.is_br connect slots_23.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[23].brupdate.b2.uop.iw_p2_poisoned connect slots_23.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[23].brupdate.b2.uop.iw_p1_poisoned connect slots_23.io.brupdate.b2.uop.iw_state, issue_slots[23].brupdate.b2.uop.iw_state connect slots_23.io.brupdate.b2.uop.ctrl.is_std, issue_slots[23].brupdate.b2.uop.ctrl.is_std connect slots_23.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[23].brupdate.b2.uop.ctrl.is_sta connect slots_23.io.brupdate.b2.uop.ctrl.is_load, issue_slots[23].brupdate.b2.uop.ctrl.is_load connect slots_23.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[23].brupdate.b2.uop.ctrl.csr_cmd connect slots_23.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[23].brupdate.b2.uop.ctrl.fcn_dw connect slots_23.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[23].brupdate.b2.uop.ctrl.op_fcn connect slots_23.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[23].brupdate.b2.uop.ctrl.imm_sel connect slots_23.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[23].brupdate.b2.uop.ctrl.op2_sel connect slots_23.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[23].brupdate.b2.uop.ctrl.op1_sel connect slots_23.io.brupdate.b2.uop.ctrl.br_type, issue_slots[23].brupdate.b2.uop.ctrl.br_type connect slots_23.io.brupdate.b2.uop.fu_code, issue_slots[23].brupdate.b2.uop.fu_code connect slots_23.io.brupdate.b2.uop.iq_type, issue_slots[23].brupdate.b2.uop.iq_type connect slots_23.io.brupdate.b2.uop.debug_pc, issue_slots[23].brupdate.b2.uop.debug_pc connect slots_23.io.brupdate.b2.uop.is_rvc, issue_slots[23].brupdate.b2.uop.is_rvc connect slots_23.io.brupdate.b2.uop.debug_inst, issue_slots[23].brupdate.b2.uop.debug_inst connect slots_23.io.brupdate.b2.uop.inst, issue_slots[23].brupdate.b2.uop.inst connect slots_23.io.brupdate.b2.uop.uopc, issue_slots[23].brupdate.b2.uop.uopc connect slots_23.io.brupdate.b1.mispredict_mask, issue_slots[23].brupdate.b1.mispredict_mask connect slots_23.io.brupdate.b1.resolve_mask, issue_slots[23].brupdate.b1.resolve_mask connect slots_23.io.grant, issue_slots[23].grant connect issue_slots[23].request_hp, slots_23.io.request_hp connect issue_slots[23].request, slots_23.io.request connect issue_slots[23].will_be_valid, slots_23.io.will_be_valid connect issue_slots[23].valid, slots_23.io.valid connect issue_slots[24].debug.state, slots_24.io.debug.state connect issue_slots[24].debug.ppred, slots_24.io.debug.ppred connect issue_slots[24].debug.p3, slots_24.io.debug.p3 connect issue_slots[24].debug.p2, slots_24.io.debug.p2 connect issue_slots[24].debug.p1, slots_24.io.debug.p1 connect issue_slots[24].uop.debug_tsrc, slots_24.io.uop.debug_tsrc connect issue_slots[24].uop.debug_fsrc, slots_24.io.uop.debug_fsrc connect issue_slots[24].uop.bp_xcpt_if, slots_24.io.uop.bp_xcpt_if connect issue_slots[24].uop.bp_debug_if, slots_24.io.uop.bp_debug_if connect issue_slots[24].uop.xcpt_ma_if, slots_24.io.uop.xcpt_ma_if connect issue_slots[24].uop.xcpt_ae_if, slots_24.io.uop.xcpt_ae_if connect issue_slots[24].uop.xcpt_pf_if, slots_24.io.uop.xcpt_pf_if connect issue_slots[24].uop.fp_single, slots_24.io.uop.fp_single connect issue_slots[24].uop.fp_val, slots_24.io.uop.fp_val connect issue_slots[24].uop.frs3_en, slots_24.io.uop.frs3_en connect issue_slots[24].uop.lrs2_rtype, slots_24.io.uop.lrs2_rtype connect issue_slots[24].uop.lrs1_rtype, slots_24.io.uop.lrs1_rtype connect issue_slots[24].uop.dst_rtype, slots_24.io.uop.dst_rtype connect issue_slots[24].uop.ldst_val, slots_24.io.uop.ldst_val connect issue_slots[24].uop.lrs3, slots_24.io.uop.lrs3 connect issue_slots[24].uop.lrs2, slots_24.io.uop.lrs2 connect issue_slots[24].uop.lrs1, slots_24.io.uop.lrs1 connect issue_slots[24].uop.ldst, slots_24.io.uop.ldst connect issue_slots[24].uop.ldst_is_rs1, slots_24.io.uop.ldst_is_rs1 connect issue_slots[24].uop.flush_on_commit, slots_24.io.uop.flush_on_commit connect issue_slots[24].uop.is_unique, slots_24.io.uop.is_unique connect issue_slots[24].uop.is_sys_pc2epc, slots_24.io.uop.is_sys_pc2epc connect issue_slots[24].uop.uses_stq, slots_24.io.uop.uses_stq connect issue_slots[24].uop.uses_ldq, slots_24.io.uop.uses_ldq connect issue_slots[24].uop.is_amo, slots_24.io.uop.is_amo connect issue_slots[24].uop.is_fencei, slots_24.io.uop.is_fencei connect issue_slots[24].uop.is_fence, slots_24.io.uop.is_fence connect issue_slots[24].uop.mem_signed, slots_24.io.uop.mem_signed connect issue_slots[24].uop.mem_size, slots_24.io.uop.mem_size connect issue_slots[24].uop.mem_cmd, slots_24.io.uop.mem_cmd connect issue_slots[24].uop.bypassable, slots_24.io.uop.bypassable connect issue_slots[24].uop.exc_cause, slots_24.io.uop.exc_cause connect issue_slots[24].uop.exception, slots_24.io.uop.exception connect issue_slots[24].uop.stale_pdst, slots_24.io.uop.stale_pdst connect issue_slots[24].uop.ppred_busy, slots_24.io.uop.ppred_busy connect issue_slots[24].uop.prs3_busy, slots_24.io.uop.prs3_busy connect issue_slots[24].uop.prs2_busy, slots_24.io.uop.prs2_busy connect issue_slots[24].uop.prs1_busy, slots_24.io.uop.prs1_busy connect issue_slots[24].uop.ppred, slots_24.io.uop.ppred connect issue_slots[24].uop.prs3, slots_24.io.uop.prs3 connect issue_slots[24].uop.prs2, slots_24.io.uop.prs2 connect issue_slots[24].uop.prs1, slots_24.io.uop.prs1 connect issue_slots[24].uop.pdst, slots_24.io.uop.pdst connect issue_slots[24].uop.rxq_idx, slots_24.io.uop.rxq_idx connect issue_slots[24].uop.stq_idx, slots_24.io.uop.stq_idx connect issue_slots[24].uop.ldq_idx, slots_24.io.uop.ldq_idx connect issue_slots[24].uop.rob_idx, slots_24.io.uop.rob_idx connect issue_slots[24].uop.csr_addr, slots_24.io.uop.csr_addr connect issue_slots[24].uop.imm_packed, slots_24.io.uop.imm_packed connect issue_slots[24].uop.taken, slots_24.io.uop.taken connect issue_slots[24].uop.pc_lob, slots_24.io.uop.pc_lob connect issue_slots[24].uop.edge_inst, slots_24.io.uop.edge_inst connect issue_slots[24].uop.ftq_idx, slots_24.io.uop.ftq_idx connect issue_slots[24].uop.br_tag, slots_24.io.uop.br_tag connect issue_slots[24].uop.br_mask, slots_24.io.uop.br_mask connect issue_slots[24].uop.is_sfb, slots_24.io.uop.is_sfb connect issue_slots[24].uop.is_jal, slots_24.io.uop.is_jal connect issue_slots[24].uop.is_jalr, slots_24.io.uop.is_jalr connect issue_slots[24].uop.is_br, slots_24.io.uop.is_br connect issue_slots[24].uop.iw_p2_poisoned, slots_24.io.uop.iw_p2_poisoned connect issue_slots[24].uop.iw_p1_poisoned, slots_24.io.uop.iw_p1_poisoned connect issue_slots[24].uop.iw_state, slots_24.io.uop.iw_state connect issue_slots[24].uop.ctrl.is_std, slots_24.io.uop.ctrl.is_std connect issue_slots[24].uop.ctrl.is_sta, slots_24.io.uop.ctrl.is_sta connect issue_slots[24].uop.ctrl.is_load, slots_24.io.uop.ctrl.is_load connect issue_slots[24].uop.ctrl.csr_cmd, slots_24.io.uop.ctrl.csr_cmd connect issue_slots[24].uop.ctrl.fcn_dw, slots_24.io.uop.ctrl.fcn_dw connect issue_slots[24].uop.ctrl.op_fcn, slots_24.io.uop.ctrl.op_fcn connect issue_slots[24].uop.ctrl.imm_sel, slots_24.io.uop.ctrl.imm_sel connect issue_slots[24].uop.ctrl.op2_sel, slots_24.io.uop.ctrl.op2_sel connect issue_slots[24].uop.ctrl.op1_sel, slots_24.io.uop.ctrl.op1_sel connect issue_slots[24].uop.ctrl.br_type, slots_24.io.uop.ctrl.br_type connect issue_slots[24].uop.fu_code, slots_24.io.uop.fu_code connect issue_slots[24].uop.iq_type, slots_24.io.uop.iq_type connect issue_slots[24].uop.debug_pc, slots_24.io.uop.debug_pc connect issue_slots[24].uop.is_rvc, slots_24.io.uop.is_rvc connect issue_slots[24].uop.debug_inst, slots_24.io.uop.debug_inst connect issue_slots[24].uop.inst, slots_24.io.uop.inst connect issue_slots[24].uop.uopc, slots_24.io.uop.uopc connect issue_slots[24].out_uop.debug_tsrc, slots_24.io.out_uop.debug_tsrc connect issue_slots[24].out_uop.debug_fsrc, slots_24.io.out_uop.debug_fsrc connect issue_slots[24].out_uop.bp_xcpt_if, slots_24.io.out_uop.bp_xcpt_if connect issue_slots[24].out_uop.bp_debug_if, slots_24.io.out_uop.bp_debug_if connect issue_slots[24].out_uop.xcpt_ma_if, slots_24.io.out_uop.xcpt_ma_if connect issue_slots[24].out_uop.xcpt_ae_if, slots_24.io.out_uop.xcpt_ae_if connect issue_slots[24].out_uop.xcpt_pf_if, slots_24.io.out_uop.xcpt_pf_if connect issue_slots[24].out_uop.fp_single, slots_24.io.out_uop.fp_single connect issue_slots[24].out_uop.fp_val, slots_24.io.out_uop.fp_val connect issue_slots[24].out_uop.frs3_en, slots_24.io.out_uop.frs3_en connect issue_slots[24].out_uop.lrs2_rtype, slots_24.io.out_uop.lrs2_rtype connect issue_slots[24].out_uop.lrs1_rtype, slots_24.io.out_uop.lrs1_rtype connect issue_slots[24].out_uop.dst_rtype, slots_24.io.out_uop.dst_rtype connect issue_slots[24].out_uop.ldst_val, slots_24.io.out_uop.ldst_val connect issue_slots[24].out_uop.lrs3, slots_24.io.out_uop.lrs3 connect issue_slots[24].out_uop.lrs2, slots_24.io.out_uop.lrs2 connect issue_slots[24].out_uop.lrs1, slots_24.io.out_uop.lrs1 connect issue_slots[24].out_uop.ldst, slots_24.io.out_uop.ldst connect issue_slots[24].out_uop.ldst_is_rs1, slots_24.io.out_uop.ldst_is_rs1 connect issue_slots[24].out_uop.flush_on_commit, slots_24.io.out_uop.flush_on_commit connect issue_slots[24].out_uop.is_unique, slots_24.io.out_uop.is_unique connect issue_slots[24].out_uop.is_sys_pc2epc, slots_24.io.out_uop.is_sys_pc2epc connect issue_slots[24].out_uop.uses_stq, slots_24.io.out_uop.uses_stq connect issue_slots[24].out_uop.uses_ldq, slots_24.io.out_uop.uses_ldq connect issue_slots[24].out_uop.is_amo, slots_24.io.out_uop.is_amo connect issue_slots[24].out_uop.is_fencei, slots_24.io.out_uop.is_fencei connect issue_slots[24].out_uop.is_fence, slots_24.io.out_uop.is_fence connect issue_slots[24].out_uop.mem_signed, slots_24.io.out_uop.mem_signed connect issue_slots[24].out_uop.mem_size, slots_24.io.out_uop.mem_size connect issue_slots[24].out_uop.mem_cmd, slots_24.io.out_uop.mem_cmd connect issue_slots[24].out_uop.bypassable, slots_24.io.out_uop.bypassable connect issue_slots[24].out_uop.exc_cause, slots_24.io.out_uop.exc_cause connect issue_slots[24].out_uop.exception, slots_24.io.out_uop.exception connect issue_slots[24].out_uop.stale_pdst, slots_24.io.out_uop.stale_pdst connect issue_slots[24].out_uop.ppred_busy, slots_24.io.out_uop.ppred_busy connect issue_slots[24].out_uop.prs3_busy, slots_24.io.out_uop.prs3_busy connect issue_slots[24].out_uop.prs2_busy, slots_24.io.out_uop.prs2_busy connect issue_slots[24].out_uop.prs1_busy, slots_24.io.out_uop.prs1_busy connect issue_slots[24].out_uop.ppred, slots_24.io.out_uop.ppred connect issue_slots[24].out_uop.prs3, slots_24.io.out_uop.prs3 connect issue_slots[24].out_uop.prs2, slots_24.io.out_uop.prs2 connect issue_slots[24].out_uop.prs1, slots_24.io.out_uop.prs1 connect issue_slots[24].out_uop.pdst, slots_24.io.out_uop.pdst connect issue_slots[24].out_uop.rxq_idx, slots_24.io.out_uop.rxq_idx connect issue_slots[24].out_uop.stq_idx, slots_24.io.out_uop.stq_idx connect issue_slots[24].out_uop.ldq_idx, slots_24.io.out_uop.ldq_idx connect issue_slots[24].out_uop.rob_idx, slots_24.io.out_uop.rob_idx connect issue_slots[24].out_uop.csr_addr, slots_24.io.out_uop.csr_addr connect issue_slots[24].out_uop.imm_packed, slots_24.io.out_uop.imm_packed connect issue_slots[24].out_uop.taken, slots_24.io.out_uop.taken connect issue_slots[24].out_uop.pc_lob, slots_24.io.out_uop.pc_lob connect issue_slots[24].out_uop.edge_inst, slots_24.io.out_uop.edge_inst connect issue_slots[24].out_uop.ftq_idx, slots_24.io.out_uop.ftq_idx connect issue_slots[24].out_uop.br_tag, slots_24.io.out_uop.br_tag connect issue_slots[24].out_uop.br_mask, slots_24.io.out_uop.br_mask connect issue_slots[24].out_uop.is_sfb, slots_24.io.out_uop.is_sfb connect issue_slots[24].out_uop.is_jal, slots_24.io.out_uop.is_jal connect issue_slots[24].out_uop.is_jalr, slots_24.io.out_uop.is_jalr connect issue_slots[24].out_uop.is_br, slots_24.io.out_uop.is_br connect issue_slots[24].out_uop.iw_p2_poisoned, slots_24.io.out_uop.iw_p2_poisoned connect issue_slots[24].out_uop.iw_p1_poisoned, slots_24.io.out_uop.iw_p1_poisoned connect issue_slots[24].out_uop.iw_state, slots_24.io.out_uop.iw_state connect issue_slots[24].out_uop.ctrl.is_std, slots_24.io.out_uop.ctrl.is_std connect issue_slots[24].out_uop.ctrl.is_sta, slots_24.io.out_uop.ctrl.is_sta connect issue_slots[24].out_uop.ctrl.is_load, slots_24.io.out_uop.ctrl.is_load connect issue_slots[24].out_uop.ctrl.csr_cmd, slots_24.io.out_uop.ctrl.csr_cmd connect issue_slots[24].out_uop.ctrl.fcn_dw, slots_24.io.out_uop.ctrl.fcn_dw connect issue_slots[24].out_uop.ctrl.op_fcn, slots_24.io.out_uop.ctrl.op_fcn connect issue_slots[24].out_uop.ctrl.imm_sel, slots_24.io.out_uop.ctrl.imm_sel connect issue_slots[24].out_uop.ctrl.op2_sel, slots_24.io.out_uop.ctrl.op2_sel connect issue_slots[24].out_uop.ctrl.op1_sel, slots_24.io.out_uop.ctrl.op1_sel connect issue_slots[24].out_uop.ctrl.br_type, slots_24.io.out_uop.ctrl.br_type connect issue_slots[24].out_uop.fu_code, slots_24.io.out_uop.fu_code connect issue_slots[24].out_uop.iq_type, slots_24.io.out_uop.iq_type connect issue_slots[24].out_uop.debug_pc, slots_24.io.out_uop.debug_pc connect issue_slots[24].out_uop.is_rvc, slots_24.io.out_uop.is_rvc connect issue_slots[24].out_uop.debug_inst, slots_24.io.out_uop.debug_inst connect issue_slots[24].out_uop.inst, slots_24.io.out_uop.inst connect issue_slots[24].out_uop.uopc, slots_24.io.out_uop.uopc connect slots_24.io.in_uop.bits.debug_tsrc, issue_slots[24].in_uop.bits.debug_tsrc connect slots_24.io.in_uop.bits.debug_fsrc, issue_slots[24].in_uop.bits.debug_fsrc connect slots_24.io.in_uop.bits.bp_xcpt_if, issue_slots[24].in_uop.bits.bp_xcpt_if connect slots_24.io.in_uop.bits.bp_debug_if, issue_slots[24].in_uop.bits.bp_debug_if connect slots_24.io.in_uop.bits.xcpt_ma_if, issue_slots[24].in_uop.bits.xcpt_ma_if connect slots_24.io.in_uop.bits.xcpt_ae_if, issue_slots[24].in_uop.bits.xcpt_ae_if connect slots_24.io.in_uop.bits.xcpt_pf_if, issue_slots[24].in_uop.bits.xcpt_pf_if connect slots_24.io.in_uop.bits.fp_single, issue_slots[24].in_uop.bits.fp_single connect slots_24.io.in_uop.bits.fp_val, issue_slots[24].in_uop.bits.fp_val connect slots_24.io.in_uop.bits.frs3_en, issue_slots[24].in_uop.bits.frs3_en connect slots_24.io.in_uop.bits.lrs2_rtype, issue_slots[24].in_uop.bits.lrs2_rtype connect slots_24.io.in_uop.bits.lrs1_rtype, issue_slots[24].in_uop.bits.lrs1_rtype connect slots_24.io.in_uop.bits.dst_rtype, issue_slots[24].in_uop.bits.dst_rtype connect slots_24.io.in_uop.bits.ldst_val, issue_slots[24].in_uop.bits.ldst_val connect slots_24.io.in_uop.bits.lrs3, issue_slots[24].in_uop.bits.lrs3 connect slots_24.io.in_uop.bits.lrs2, issue_slots[24].in_uop.bits.lrs2 connect slots_24.io.in_uop.bits.lrs1, issue_slots[24].in_uop.bits.lrs1 connect slots_24.io.in_uop.bits.ldst, issue_slots[24].in_uop.bits.ldst connect slots_24.io.in_uop.bits.ldst_is_rs1, issue_slots[24].in_uop.bits.ldst_is_rs1 connect slots_24.io.in_uop.bits.flush_on_commit, issue_slots[24].in_uop.bits.flush_on_commit connect slots_24.io.in_uop.bits.is_unique, issue_slots[24].in_uop.bits.is_unique connect slots_24.io.in_uop.bits.is_sys_pc2epc, issue_slots[24].in_uop.bits.is_sys_pc2epc connect slots_24.io.in_uop.bits.uses_stq, issue_slots[24].in_uop.bits.uses_stq connect slots_24.io.in_uop.bits.uses_ldq, issue_slots[24].in_uop.bits.uses_ldq connect slots_24.io.in_uop.bits.is_amo, issue_slots[24].in_uop.bits.is_amo connect slots_24.io.in_uop.bits.is_fencei, issue_slots[24].in_uop.bits.is_fencei connect slots_24.io.in_uop.bits.is_fence, issue_slots[24].in_uop.bits.is_fence connect slots_24.io.in_uop.bits.mem_signed, issue_slots[24].in_uop.bits.mem_signed connect slots_24.io.in_uop.bits.mem_size, issue_slots[24].in_uop.bits.mem_size connect slots_24.io.in_uop.bits.mem_cmd, issue_slots[24].in_uop.bits.mem_cmd connect slots_24.io.in_uop.bits.bypassable, issue_slots[24].in_uop.bits.bypassable connect slots_24.io.in_uop.bits.exc_cause, issue_slots[24].in_uop.bits.exc_cause connect slots_24.io.in_uop.bits.exception, issue_slots[24].in_uop.bits.exception connect slots_24.io.in_uop.bits.stale_pdst, issue_slots[24].in_uop.bits.stale_pdst connect slots_24.io.in_uop.bits.ppred_busy, issue_slots[24].in_uop.bits.ppred_busy connect slots_24.io.in_uop.bits.prs3_busy, issue_slots[24].in_uop.bits.prs3_busy connect slots_24.io.in_uop.bits.prs2_busy, issue_slots[24].in_uop.bits.prs2_busy connect slots_24.io.in_uop.bits.prs1_busy, issue_slots[24].in_uop.bits.prs1_busy connect slots_24.io.in_uop.bits.ppred, issue_slots[24].in_uop.bits.ppred connect slots_24.io.in_uop.bits.prs3, issue_slots[24].in_uop.bits.prs3 connect slots_24.io.in_uop.bits.prs2, issue_slots[24].in_uop.bits.prs2 connect slots_24.io.in_uop.bits.prs1, issue_slots[24].in_uop.bits.prs1 connect slots_24.io.in_uop.bits.pdst, issue_slots[24].in_uop.bits.pdst connect slots_24.io.in_uop.bits.rxq_idx, issue_slots[24].in_uop.bits.rxq_idx connect slots_24.io.in_uop.bits.stq_idx, issue_slots[24].in_uop.bits.stq_idx connect slots_24.io.in_uop.bits.ldq_idx, issue_slots[24].in_uop.bits.ldq_idx connect slots_24.io.in_uop.bits.rob_idx, issue_slots[24].in_uop.bits.rob_idx connect slots_24.io.in_uop.bits.csr_addr, issue_slots[24].in_uop.bits.csr_addr connect slots_24.io.in_uop.bits.imm_packed, issue_slots[24].in_uop.bits.imm_packed connect slots_24.io.in_uop.bits.taken, issue_slots[24].in_uop.bits.taken connect slots_24.io.in_uop.bits.pc_lob, issue_slots[24].in_uop.bits.pc_lob connect slots_24.io.in_uop.bits.edge_inst, issue_slots[24].in_uop.bits.edge_inst connect slots_24.io.in_uop.bits.ftq_idx, issue_slots[24].in_uop.bits.ftq_idx connect slots_24.io.in_uop.bits.br_tag, issue_slots[24].in_uop.bits.br_tag connect slots_24.io.in_uop.bits.br_mask, issue_slots[24].in_uop.bits.br_mask connect slots_24.io.in_uop.bits.is_sfb, issue_slots[24].in_uop.bits.is_sfb connect slots_24.io.in_uop.bits.is_jal, issue_slots[24].in_uop.bits.is_jal connect slots_24.io.in_uop.bits.is_jalr, issue_slots[24].in_uop.bits.is_jalr connect slots_24.io.in_uop.bits.is_br, issue_slots[24].in_uop.bits.is_br connect slots_24.io.in_uop.bits.iw_p2_poisoned, issue_slots[24].in_uop.bits.iw_p2_poisoned connect slots_24.io.in_uop.bits.iw_p1_poisoned, issue_slots[24].in_uop.bits.iw_p1_poisoned connect slots_24.io.in_uop.bits.iw_state, issue_slots[24].in_uop.bits.iw_state connect slots_24.io.in_uop.bits.ctrl.is_std, issue_slots[24].in_uop.bits.ctrl.is_std connect slots_24.io.in_uop.bits.ctrl.is_sta, issue_slots[24].in_uop.bits.ctrl.is_sta connect slots_24.io.in_uop.bits.ctrl.is_load, issue_slots[24].in_uop.bits.ctrl.is_load connect slots_24.io.in_uop.bits.ctrl.csr_cmd, issue_slots[24].in_uop.bits.ctrl.csr_cmd connect slots_24.io.in_uop.bits.ctrl.fcn_dw, issue_slots[24].in_uop.bits.ctrl.fcn_dw connect slots_24.io.in_uop.bits.ctrl.op_fcn, issue_slots[24].in_uop.bits.ctrl.op_fcn connect slots_24.io.in_uop.bits.ctrl.imm_sel, issue_slots[24].in_uop.bits.ctrl.imm_sel connect slots_24.io.in_uop.bits.ctrl.op2_sel, issue_slots[24].in_uop.bits.ctrl.op2_sel connect slots_24.io.in_uop.bits.ctrl.op1_sel, issue_slots[24].in_uop.bits.ctrl.op1_sel connect slots_24.io.in_uop.bits.ctrl.br_type, issue_slots[24].in_uop.bits.ctrl.br_type connect slots_24.io.in_uop.bits.fu_code, issue_slots[24].in_uop.bits.fu_code connect slots_24.io.in_uop.bits.iq_type, issue_slots[24].in_uop.bits.iq_type connect slots_24.io.in_uop.bits.debug_pc, issue_slots[24].in_uop.bits.debug_pc connect slots_24.io.in_uop.bits.is_rvc, issue_slots[24].in_uop.bits.is_rvc connect slots_24.io.in_uop.bits.debug_inst, issue_slots[24].in_uop.bits.debug_inst connect slots_24.io.in_uop.bits.inst, issue_slots[24].in_uop.bits.inst connect slots_24.io.in_uop.bits.uopc, issue_slots[24].in_uop.bits.uopc connect slots_24.io.in_uop.valid, issue_slots[24].in_uop.valid connect slots_24.io.spec_ld_wakeup[0].bits, issue_slots[24].spec_ld_wakeup[0].bits connect slots_24.io.spec_ld_wakeup[0].valid, issue_slots[24].spec_ld_wakeup[0].valid connect slots_24.io.pred_wakeup_port.bits, issue_slots[24].pred_wakeup_port.bits connect slots_24.io.pred_wakeup_port.valid, issue_slots[24].pred_wakeup_port.valid connect slots_24.io.wakeup_ports[0].bits.poisoned, issue_slots[24].wakeup_ports[0].bits.poisoned connect slots_24.io.wakeup_ports[0].bits.pdst, issue_slots[24].wakeup_ports[0].bits.pdst connect slots_24.io.wakeup_ports[0].valid, issue_slots[24].wakeup_ports[0].valid connect slots_24.io.wakeup_ports[1].bits.poisoned, issue_slots[24].wakeup_ports[1].bits.poisoned connect slots_24.io.wakeup_ports[1].bits.pdst, issue_slots[24].wakeup_ports[1].bits.pdst connect slots_24.io.wakeup_ports[1].valid, issue_slots[24].wakeup_ports[1].valid connect slots_24.io.wakeup_ports[2].bits.poisoned, issue_slots[24].wakeup_ports[2].bits.poisoned connect slots_24.io.wakeup_ports[2].bits.pdst, issue_slots[24].wakeup_ports[2].bits.pdst connect slots_24.io.wakeup_ports[2].valid, issue_slots[24].wakeup_ports[2].valid connect slots_24.io.wakeup_ports[3].bits.poisoned, issue_slots[24].wakeup_ports[3].bits.poisoned connect slots_24.io.wakeup_ports[3].bits.pdst, issue_slots[24].wakeup_ports[3].bits.pdst connect slots_24.io.wakeup_ports[3].valid, issue_slots[24].wakeup_ports[3].valid connect slots_24.io.wakeup_ports[4].bits.poisoned, issue_slots[24].wakeup_ports[4].bits.poisoned connect slots_24.io.wakeup_ports[4].bits.pdst, issue_slots[24].wakeup_ports[4].bits.pdst connect slots_24.io.wakeup_ports[4].valid, issue_slots[24].wakeup_ports[4].valid connect slots_24.io.wakeup_ports[5].bits.poisoned, issue_slots[24].wakeup_ports[5].bits.poisoned connect slots_24.io.wakeup_ports[5].bits.pdst, issue_slots[24].wakeup_ports[5].bits.pdst connect slots_24.io.wakeup_ports[5].valid, issue_slots[24].wakeup_ports[5].valid connect slots_24.io.wakeup_ports[6].bits.poisoned, issue_slots[24].wakeup_ports[6].bits.poisoned connect slots_24.io.wakeup_ports[6].bits.pdst, issue_slots[24].wakeup_ports[6].bits.pdst connect slots_24.io.wakeup_ports[6].valid, issue_slots[24].wakeup_ports[6].valid connect slots_24.io.ldspec_miss, issue_slots[24].ldspec_miss connect slots_24.io.clear, issue_slots[24].clear connect slots_24.io.kill, issue_slots[24].kill connect slots_24.io.brupdate.b2.target_offset, issue_slots[24].brupdate.b2.target_offset connect slots_24.io.brupdate.b2.jalr_target, issue_slots[24].brupdate.b2.jalr_target connect slots_24.io.brupdate.b2.pc_sel, issue_slots[24].brupdate.b2.pc_sel connect slots_24.io.brupdate.b2.cfi_type, issue_slots[24].brupdate.b2.cfi_type connect slots_24.io.brupdate.b2.taken, issue_slots[24].brupdate.b2.taken connect slots_24.io.brupdate.b2.mispredict, issue_slots[24].brupdate.b2.mispredict connect slots_24.io.brupdate.b2.valid, issue_slots[24].brupdate.b2.valid connect slots_24.io.brupdate.b2.uop.debug_tsrc, issue_slots[24].brupdate.b2.uop.debug_tsrc connect slots_24.io.brupdate.b2.uop.debug_fsrc, issue_slots[24].brupdate.b2.uop.debug_fsrc connect slots_24.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[24].brupdate.b2.uop.bp_xcpt_if connect slots_24.io.brupdate.b2.uop.bp_debug_if, issue_slots[24].brupdate.b2.uop.bp_debug_if connect slots_24.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[24].brupdate.b2.uop.xcpt_ma_if connect slots_24.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[24].brupdate.b2.uop.xcpt_ae_if connect slots_24.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[24].brupdate.b2.uop.xcpt_pf_if connect slots_24.io.brupdate.b2.uop.fp_single, issue_slots[24].brupdate.b2.uop.fp_single connect slots_24.io.brupdate.b2.uop.fp_val, issue_slots[24].brupdate.b2.uop.fp_val connect slots_24.io.brupdate.b2.uop.frs3_en, issue_slots[24].brupdate.b2.uop.frs3_en connect slots_24.io.brupdate.b2.uop.lrs2_rtype, issue_slots[24].brupdate.b2.uop.lrs2_rtype connect slots_24.io.brupdate.b2.uop.lrs1_rtype, issue_slots[24].brupdate.b2.uop.lrs1_rtype connect slots_24.io.brupdate.b2.uop.dst_rtype, issue_slots[24].brupdate.b2.uop.dst_rtype connect slots_24.io.brupdate.b2.uop.ldst_val, issue_slots[24].brupdate.b2.uop.ldst_val connect slots_24.io.brupdate.b2.uop.lrs3, issue_slots[24].brupdate.b2.uop.lrs3 connect slots_24.io.brupdate.b2.uop.lrs2, issue_slots[24].brupdate.b2.uop.lrs2 connect slots_24.io.brupdate.b2.uop.lrs1, issue_slots[24].brupdate.b2.uop.lrs1 connect slots_24.io.brupdate.b2.uop.ldst, issue_slots[24].brupdate.b2.uop.ldst connect slots_24.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[24].brupdate.b2.uop.ldst_is_rs1 connect slots_24.io.brupdate.b2.uop.flush_on_commit, issue_slots[24].brupdate.b2.uop.flush_on_commit connect slots_24.io.brupdate.b2.uop.is_unique, issue_slots[24].brupdate.b2.uop.is_unique connect slots_24.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[24].brupdate.b2.uop.is_sys_pc2epc connect slots_24.io.brupdate.b2.uop.uses_stq, issue_slots[24].brupdate.b2.uop.uses_stq connect slots_24.io.brupdate.b2.uop.uses_ldq, issue_slots[24].brupdate.b2.uop.uses_ldq connect slots_24.io.brupdate.b2.uop.is_amo, issue_slots[24].brupdate.b2.uop.is_amo connect slots_24.io.brupdate.b2.uop.is_fencei, issue_slots[24].brupdate.b2.uop.is_fencei connect slots_24.io.brupdate.b2.uop.is_fence, issue_slots[24].brupdate.b2.uop.is_fence connect slots_24.io.brupdate.b2.uop.mem_signed, issue_slots[24].brupdate.b2.uop.mem_signed connect slots_24.io.brupdate.b2.uop.mem_size, issue_slots[24].brupdate.b2.uop.mem_size connect slots_24.io.brupdate.b2.uop.mem_cmd, issue_slots[24].brupdate.b2.uop.mem_cmd connect slots_24.io.brupdate.b2.uop.bypassable, issue_slots[24].brupdate.b2.uop.bypassable connect slots_24.io.brupdate.b2.uop.exc_cause, issue_slots[24].brupdate.b2.uop.exc_cause connect slots_24.io.brupdate.b2.uop.exception, issue_slots[24].brupdate.b2.uop.exception connect slots_24.io.brupdate.b2.uop.stale_pdst, issue_slots[24].brupdate.b2.uop.stale_pdst connect slots_24.io.brupdate.b2.uop.ppred_busy, issue_slots[24].brupdate.b2.uop.ppred_busy connect slots_24.io.brupdate.b2.uop.prs3_busy, issue_slots[24].brupdate.b2.uop.prs3_busy connect slots_24.io.brupdate.b2.uop.prs2_busy, issue_slots[24].brupdate.b2.uop.prs2_busy connect slots_24.io.brupdate.b2.uop.prs1_busy, issue_slots[24].brupdate.b2.uop.prs1_busy connect slots_24.io.brupdate.b2.uop.ppred, issue_slots[24].brupdate.b2.uop.ppred connect slots_24.io.brupdate.b2.uop.prs3, issue_slots[24].brupdate.b2.uop.prs3 connect slots_24.io.brupdate.b2.uop.prs2, issue_slots[24].brupdate.b2.uop.prs2 connect slots_24.io.brupdate.b2.uop.prs1, issue_slots[24].brupdate.b2.uop.prs1 connect slots_24.io.brupdate.b2.uop.pdst, issue_slots[24].brupdate.b2.uop.pdst connect slots_24.io.brupdate.b2.uop.rxq_idx, issue_slots[24].brupdate.b2.uop.rxq_idx connect slots_24.io.brupdate.b2.uop.stq_idx, issue_slots[24].brupdate.b2.uop.stq_idx connect slots_24.io.brupdate.b2.uop.ldq_idx, issue_slots[24].brupdate.b2.uop.ldq_idx connect slots_24.io.brupdate.b2.uop.rob_idx, issue_slots[24].brupdate.b2.uop.rob_idx connect slots_24.io.brupdate.b2.uop.csr_addr, issue_slots[24].brupdate.b2.uop.csr_addr connect slots_24.io.brupdate.b2.uop.imm_packed, issue_slots[24].brupdate.b2.uop.imm_packed connect slots_24.io.brupdate.b2.uop.taken, issue_slots[24].brupdate.b2.uop.taken connect slots_24.io.brupdate.b2.uop.pc_lob, issue_slots[24].brupdate.b2.uop.pc_lob connect slots_24.io.brupdate.b2.uop.edge_inst, issue_slots[24].brupdate.b2.uop.edge_inst connect slots_24.io.brupdate.b2.uop.ftq_idx, issue_slots[24].brupdate.b2.uop.ftq_idx connect slots_24.io.brupdate.b2.uop.br_tag, issue_slots[24].brupdate.b2.uop.br_tag connect slots_24.io.brupdate.b2.uop.br_mask, issue_slots[24].brupdate.b2.uop.br_mask connect slots_24.io.brupdate.b2.uop.is_sfb, issue_slots[24].brupdate.b2.uop.is_sfb connect slots_24.io.brupdate.b2.uop.is_jal, issue_slots[24].brupdate.b2.uop.is_jal connect slots_24.io.brupdate.b2.uop.is_jalr, issue_slots[24].brupdate.b2.uop.is_jalr connect slots_24.io.brupdate.b2.uop.is_br, issue_slots[24].brupdate.b2.uop.is_br connect slots_24.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[24].brupdate.b2.uop.iw_p2_poisoned connect slots_24.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[24].brupdate.b2.uop.iw_p1_poisoned connect slots_24.io.brupdate.b2.uop.iw_state, issue_slots[24].brupdate.b2.uop.iw_state connect slots_24.io.brupdate.b2.uop.ctrl.is_std, issue_slots[24].brupdate.b2.uop.ctrl.is_std connect slots_24.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[24].brupdate.b2.uop.ctrl.is_sta connect slots_24.io.brupdate.b2.uop.ctrl.is_load, issue_slots[24].brupdate.b2.uop.ctrl.is_load connect slots_24.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[24].brupdate.b2.uop.ctrl.csr_cmd connect slots_24.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[24].brupdate.b2.uop.ctrl.fcn_dw connect slots_24.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[24].brupdate.b2.uop.ctrl.op_fcn connect slots_24.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[24].brupdate.b2.uop.ctrl.imm_sel connect slots_24.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[24].brupdate.b2.uop.ctrl.op2_sel connect slots_24.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[24].brupdate.b2.uop.ctrl.op1_sel connect slots_24.io.brupdate.b2.uop.ctrl.br_type, issue_slots[24].brupdate.b2.uop.ctrl.br_type connect slots_24.io.brupdate.b2.uop.fu_code, issue_slots[24].brupdate.b2.uop.fu_code connect slots_24.io.brupdate.b2.uop.iq_type, issue_slots[24].brupdate.b2.uop.iq_type connect slots_24.io.brupdate.b2.uop.debug_pc, issue_slots[24].brupdate.b2.uop.debug_pc connect slots_24.io.brupdate.b2.uop.is_rvc, issue_slots[24].brupdate.b2.uop.is_rvc connect slots_24.io.brupdate.b2.uop.debug_inst, issue_slots[24].brupdate.b2.uop.debug_inst connect slots_24.io.brupdate.b2.uop.inst, issue_slots[24].brupdate.b2.uop.inst connect slots_24.io.brupdate.b2.uop.uopc, issue_slots[24].brupdate.b2.uop.uopc connect slots_24.io.brupdate.b1.mispredict_mask, issue_slots[24].brupdate.b1.mispredict_mask connect slots_24.io.brupdate.b1.resolve_mask, issue_slots[24].brupdate.b1.resolve_mask connect slots_24.io.grant, issue_slots[24].grant connect issue_slots[24].request_hp, slots_24.io.request_hp connect issue_slots[24].request, slots_24.io.request connect issue_slots[24].will_be_valid, slots_24.io.will_be_valid connect issue_slots[24].valid, slots_24.io.valid connect issue_slots[25].debug.state, slots_25.io.debug.state connect issue_slots[25].debug.ppred, slots_25.io.debug.ppred connect issue_slots[25].debug.p3, slots_25.io.debug.p3 connect issue_slots[25].debug.p2, slots_25.io.debug.p2 connect issue_slots[25].debug.p1, slots_25.io.debug.p1 connect issue_slots[25].uop.debug_tsrc, slots_25.io.uop.debug_tsrc connect issue_slots[25].uop.debug_fsrc, slots_25.io.uop.debug_fsrc connect issue_slots[25].uop.bp_xcpt_if, slots_25.io.uop.bp_xcpt_if connect issue_slots[25].uop.bp_debug_if, slots_25.io.uop.bp_debug_if connect issue_slots[25].uop.xcpt_ma_if, slots_25.io.uop.xcpt_ma_if connect issue_slots[25].uop.xcpt_ae_if, slots_25.io.uop.xcpt_ae_if connect issue_slots[25].uop.xcpt_pf_if, slots_25.io.uop.xcpt_pf_if connect issue_slots[25].uop.fp_single, slots_25.io.uop.fp_single connect issue_slots[25].uop.fp_val, slots_25.io.uop.fp_val connect issue_slots[25].uop.frs3_en, slots_25.io.uop.frs3_en connect issue_slots[25].uop.lrs2_rtype, slots_25.io.uop.lrs2_rtype connect issue_slots[25].uop.lrs1_rtype, slots_25.io.uop.lrs1_rtype connect issue_slots[25].uop.dst_rtype, slots_25.io.uop.dst_rtype connect issue_slots[25].uop.ldst_val, slots_25.io.uop.ldst_val connect issue_slots[25].uop.lrs3, slots_25.io.uop.lrs3 connect issue_slots[25].uop.lrs2, slots_25.io.uop.lrs2 connect issue_slots[25].uop.lrs1, slots_25.io.uop.lrs1 connect issue_slots[25].uop.ldst, slots_25.io.uop.ldst connect issue_slots[25].uop.ldst_is_rs1, slots_25.io.uop.ldst_is_rs1 connect issue_slots[25].uop.flush_on_commit, slots_25.io.uop.flush_on_commit connect issue_slots[25].uop.is_unique, slots_25.io.uop.is_unique connect issue_slots[25].uop.is_sys_pc2epc, slots_25.io.uop.is_sys_pc2epc connect issue_slots[25].uop.uses_stq, slots_25.io.uop.uses_stq connect issue_slots[25].uop.uses_ldq, slots_25.io.uop.uses_ldq connect issue_slots[25].uop.is_amo, slots_25.io.uop.is_amo connect issue_slots[25].uop.is_fencei, slots_25.io.uop.is_fencei connect issue_slots[25].uop.is_fence, slots_25.io.uop.is_fence connect issue_slots[25].uop.mem_signed, slots_25.io.uop.mem_signed connect issue_slots[25].uop.mem_size, slots_25.io.uop.mem_size connect issue_slots[25].uop.mem_cmd, slots_25.io.uop.mem_cmd connect issue_slots[25].uop.bypassable, slots_25.io.uop.bypassable connect issue_slots[25].uop.exc_cause, slots_25.io.uop.exc_cause connect issue_slots[25].uop.exception, slots_25.io.uop.exception connect issue_slots[25].uop.stale_pdst, slots_25.io.uop.stale_pdst connect issue_slots[25].uop.ppred_busy, slots_25.io.uop.ppred_busy connect issue_slots[25].uop.prs3_busy, slots_25.io.uop.prs3_busy connect issue_slots[25].uop.prs2_busy, slots_25.io.uop.prs2_busy connect issue_slots[25].uop.prs1_busy, slots_25.io.uop.prs1_busy connect issue_slots[25].uop.ppred, slots_25.io.uop.ppred connect issue_slots[25].uop.prs3, slots_25.io.uop.prs3 connect issue_slots[25].uop.prs2, slots_25.io.uop.prs2 connect issue_slots[25].uop.prs1, slots_25.io.uop.prs1 connect issue_slots[25].uop.pdst, slots_25.io.uop.pdst connect issue_slots[25].uop.rxq_idx, slots_25.io.uop.rxq_idx connect issue_slots[25].uop.stq_idx, slots_25.io.uop.stq_idx connect issue_slots[25].uop.ldq_idx, slots_25.io.uop.ldq_idx connect issue_slots[25].uop.rob_idx, slots_25.io.uop.rob_idx connect issue_slots[25].uop.csr_addr, slots_25.io.uop.csr_addr connect issue_slots[25].uop.imm_packed, slots_25.io.uop.imm_packed connect issue_slots[25].uop.taken, slots_25.io.uop.taken connect issue_slots[25].uop.pc_lob, slots_25.io.uop.pc_lob connect issue_slots[25].uop.edge_inst, slots_25.io.uop.edge_inst connect issue_slots[25].uop.ftq_idx, slots_25.io.uop.ftq_idx connect issue_slots[25].uop.br_tag, slots_25.io.uop.br_tag connect issue_slots[25].uop.br_mask, slots_25.io.uop.br_mask connect issue_slots[25].uop.is_sfb, slots_25.io.uop.is_sfb connect issue_slots[25].uop.is_jal, slots_25.io.uop.is_jal connect issue_slots[25].uop.is_jalr, slots_25.io.uop.is_jalr connect issue_slots[25].uop.is_br, slots_25.io.uop.is_br connect issue_slots[25].uop.iw_p2_poisoned, slots_25.io.uop.iw_p2_poisoned connect issue_slots[25].uop.iw_p1_poisoned, slots_25.io.uop.iw_p1_poisoned connect issue_slots[25].uop.iw_state, slots_25.io.uop.iw_state connect issue_slots[25].uop.ctrl.is_std, slots_25.io.uop.ctrl.is_std connect issue_slots[25].uop.ctrl.is_sta, slots_25.io.uop.ctrl.is_sta connect issue_slots[25].uop.ctrl.is_load, slots_25.io.uop.ctrl.is_load connect issue_slots[25].uop.ctrl.csr_cmd, slots_25.io.uop.ctrl.csr_cmd connect issue_slots[25].uop.ctrl.fcn_dw, slots_25.io.uop.ctrl.fcn_dw connect issue_slots[25].uop.ctrl.op_fcn, slots_25.io.uop.ctrl.op_fcn connect issue_slots[25].uop.ctrl.imm_sel, slots_25.io.uop.ctrl.imm_sel connect issue_slots[25].uop.ctrl.op2_sel, slots_25.io.uop.ctrl.op2_sel connect issue_slots[25].uop.ctrl.op1_sel, slots_25.io.uop.ctrl.op1_sel connect issue_slots[25].uop.ctrl.br_type, slots_25.io.uop.ctrl.br_type connect issue_slots[25].uop.fu_code, slots_25.io.uop.fu_code connect issue_slots[25].uop.iq_type, slots_25.io.uop.iq_type connect issue_slots[25].uop.debug_pc, slots_25.io.uop.debug_pc connect issue_slots[25].uop.is_rvc, slots_25.io.uop.is_rvc connect issue_slots[25].uop.debug_inst, slots_25.io.uop.debug_inst connect issue_slots[25].uop.inst, slots_25.io.uop.inst connect issue_slots[25].uop.uopc, slots_25.io.uop.uopc connect issue_slots[25].out_uop.debug_tsrc, slots_25.io.out_uop.debug_tsrc connect issue_slots[25].out_uop.debug_fsrc, slots_25.io.out_uop.debug_fsrc connect issue_slots[25].out_uop.bp_xcpt_if, slots_25.io.out_uop.bp_xcpt_if connect issue_slots[25].out_uop.bp_debug_if, slots_25.io.out_uop.bp_debug_if connect issue_slots[25].out_uop.xcpt_ma_if, slots_25.io.out_uop.xcpt_ma_if connect issue_slots[25].out_uop.xcpt_ae_if, slots_25.io.out_uop.xcpt_ae_if connect issue_slots[25].out_uop.xcpt_pf_if, slots_25.io.out_uop.xcpt_pf_if connect issue_slots[25].out_uop.fp_single, slots_25.io.out_uop.fp_single connect issue_slots[25].out_uop.fp_val, slots_25.io.out_uop.fp_val connect issue_slots[25].out_uop.frs3_en, slots_25.io.out_uop.frs3_en connect issue_slots[25].out_uop.lrs2_rtype, slots_25.io.out_uop.lrs2_rtype connect issue_slots[25].out_uop.lrs1_rtype, slots_25.io.out_uop.lrs1_rtype connect issue_slots[25].out_uop.dst_rtype, slots_25.io.out_uop.dst_rtype connect issue_slots[25].out_uop.ldst_val, slots_25.io.out_uop.ldst_val connect issue_slots[25].out_uop.lrs3, slots_25.io.out_uop.lrs3 connect issue_slots[25].out_uop.lrs2, slots_25.io.out_uop.lrs2 connect issue_slots[25].out_uop.lrs1, slots_25.io.out_uop.lrs1 connect issue_slots[25].out_uop.ldst, slots_25.io.out_uop.ldst connect issue_slots[25].out_uop.ldst_is_rs1, slots_25.io.out_uop.ldst_is_rs1 connect issue_slots[25].out_uop.flush_on_commit, slots_25.io.out_uop.flush_on_commit connect issue_slots[25].out_uop.is_unique, slots_25.io.out_uop.is_unique connect issue_slots[25].out_uop.is_sys_pc2epc, slots_25.io.out_uop.is_sys_pc2epc connect issue_slots[25].out_uop.uses_stq, slots_25.io.out_uop.uses_stq connect issue_slots[25].out_uop.uses_ldq, slots_25.io.out_uop.uses_ldq connect issue_slots[25].out_uop.is_amo, slots_25.io.out_uop.is_amo connect issue_slots[25].out_uop.is_fencei, slots_25.io.out_uop.is_fencei connect issue_slots[25].out_uop.is_fence, slots_25.io.out_uop.is_fence connect issue_slots[25].out_uop.mem_signed, slots_25.io.out_uop.mem_signed connect issue_slots[25].out_uop.mem_size, slots_25.io.out_uop.mem_size connect issue_slots[25].out_uop.mem_cmd, slots_25.io.out_uop.mem_cmd connect issue_slots[25].out_uop.bypassable, slots_25.io.out_uop.bypassable connect issue_slots[25].out_uop.exc_cause, slots_25.io.out_uop.exc_cause connect issue_slots[25].out_uop.exception, slots_25.io.out_uop.exception connect issue_slots[25].out_uop.stale_pdst, slots_25.io.out_uop.stale_pdst connect issue_slots[25].out_uop.ppred_busy, slots_25.io.out_uop.ppred_busy connect issue_slots[25].out_uop.prs3_busy, slots_25.io.out_uop.prs3_busy connect issue_slots[25].out_uop.prs2_busy, slots_25.io.out_uop.prs2_busy connect issue_slots[25].out_uop.prs1_busy, slots_25.io.out_uop.prs1_busy connect issue_slots[25].out_uop.ppred, slots_25.io.out_uop.ppred connect issue_slots[25].out_uop.prs3, slots_25.io.out_uop.prs3 connect issue_slots[25].out_uop.prs2, slots_25.io.out_uop.prs2 connect issue_slots[25].out_uop.prs1, slots_25.io.out_uop.prs1 connect issue_slots[25].out_uop.pdst, slots_25.io.out_uop.pdst connect issue_slots[25].out_uop.rxq_idx, slots_25.io.out_uop.rxq_idx connect issue_slots[25].out_uop.stq_idx, slots_25.io.out_uop.stq_idx connect issue_slots[25].out_uop.ldq_idx, slots_25.io.out_uop.ldq_idx connect issue_slots[25].out_uop.rob_idx, slots_25.io.out_uop.rob_idx connect issue_slots[25].out_uop.csr_addr, slots_25.io.out_uop.csr_addr connect issue_slots[25].out_uop.imm_packed, slots_25.io.out_uop.imm_packed connect issue_slots[25].out_uop.taken, slots_25.io.out_uop.taken connect issue_slots[25].out_uop.pc_lob, slots_25.io.out_uop.pc_lob connect issue_slots[25].out_uop.edge_inst, slots_25.io.out_uop.edge_inst connect issue_slots[25].out_uop.ftq_idx, slots_25.io.out_uop.ftq_idx connect issue_slots[25].out_uop.br_tag, slots_25.io.out_uop.br_tag connect issue_slots[25].out_uop.br_mask, slots_25.io.out_uop.br_mask connect issue_slots[25].out_uop.is_sfb, slots_25.io.out_uop.is_sfb connect issue_slots[25].out_uop.is_jal, slots_25.io.out_uop.is_jal connect issue_slots[25].out_uop.is_jalr, slots_25.io.out_uop.is_jalr connect issue_slots[25].out_uop.is_br, slots_25.io.out_uop.is_br connect issue_slots[25].out_uop.iw_p2_poisoned, slots_25.io.out_uop.iw_p2_poisoned connect issue_slots[25].out_uop.iw_p1_poisoned, slots_25.io.out_uop.iw_p1_poisoned connect issue_slots[25].out_uop.iw_state, slots_25.io.out_uop.iw_state connect issue_slots[25].out_uop.ctrl.is_std, slots_25.io.out_uop.ctrl.is_std connect issue_slots[25].out_uop.ctrl.is_sta, slots_25.io.out_uop.ctrl.is_sta connect issue_slots[25].out_uop.ctrl.is_load, slots_25.io.out_uop.ctrl.is_load connect issue_slots[25].out_uop.ctrl.csr_cmd, slots_25.io.out_uop.ctrl.csr_cmd connect issue_slots[25].out_uop.ctrl.fcn_dw, slots_25.io.out_uop.ctrl.fcn_dw connect issue_slots[25].out_uop.ctrl.op_fcn, slots_25.io.out_uop.ctrl.op_fcn connect issue_slots[25].out_uop.ctrl.imm_sel, slots_25.io.out_uop.ctrl.imm_sel connect issue_slots[25].out_uop.ctrl.op2_sel, slots_25.io.out_uop.ctrl.op2_sel connect issue_slots[25].out_uop.ctrl.op1_sel, slots_25.io.out_uop.ctrl.op1_sel connect issue_slots[25].out_uop.ctrl.br_type, slots_25.io.out_uop.ctrl.br_type connect issue_slots[25].out_uop.fu_code, slots_25.io.out_uop.fu_code connect issue_slots[25].out_uop.iq_type, slots_25.io.out_uop.iq_type connect issue_slots[25].out_uop.debug_pc, slots_25.io.out_uop.debug_pc connect issue_slots[25].out_uop.is_rvc, slots_25.io.out_uop.is_rvc connect issue_slots[25].out_uop.debug_inst, slots_25.io.out_uop.debug_inst connect issue_slots[25].out_uop.inst, slots_25.io.out_uop.inst connect issue_slots[25].out_uop.uopc, slots_25.io.out_uop.uopc connect slots_25.io.in_uop.bits.debug_tsrc, issue_slots[25].in_uop.bits.debug_tsrc connect slots_25.io.in_uop.bits.debug_fsrc, issue_slots[25].in_uop.bits.debug_fsrc connect slots_25.io.in_uop.bits.bp_xcpt_if, issue_slots[25].in_uop.bits.bp_xcpt_if connect slots_25.io.in_uop.bits.bp_debug_if, issue_slots[25].in_uop.bits.bp_debug_if connect slots_25.io.in_uop.bits.xcpt_ma_if, issue_slots[25].in_uop.bits.xcpt_ma_if connect slots_25.io.in_uop.bits.xcpt_ae_if, issue_slots[25].in_uop.bits.xcpt_ae_if connect slots_25.io.in_uop.bits.xcpt_pf_if, issue_slots[25].in_uop.bits.xcpt_pf_if connect slots_25.io.in_uop.bits.fp_single, issue_slots[25].in_uop.bits.fp_single connect slots_25.io.in_uop.bits.fp_val, issue_slots[25].in_uop.bits.fp_val connect slots_25.io.in_uop.bits.frs3_en, issue_slots[25].in_uop.bits.frs3_en connect slots_25.io.in_uop.bits.lrs2_rtype, issue_slots[25].in_uop.bits.lrs2_rtype connect slots_25.io.in_uop.bits.lrs1_rtype, issue_slots[25].in_uop.bits.lrs1_rtype connect slots_25.io.in_uop.bits.dst_rtype, issue_slots[25].in_uop.bits.dst_rtype connect slots_25.io.in_uop.bits.ldst_val, issue_slots[25].in_uop.bits.ldst_val connect slots_25.io.in_uop.bits.lrs3, issue_slots[25].in_uop.bits.lrs3 connect slots_25.io.in_uop.bits.lrs2, issue_slots[25].in_uop.bits.lrs2 connect slots_25.io.in_uop.bits.lrs1, issue_slots[25].in_uop.bits.lrs1 connect slots_25.io.in_uop.bits.ldst, issue_slots[25].in_uop.bits.ldst connect slots_25.io.in_uop.bits.ldst_is_rs1, issue_slots[25].in_uop.bits.ldst_is_rs1 connect slots_25.io.in_uop.bits.flush_on_commit, issue_slots[25].in_uop.bits.flush_on_commit connect slots_25.io.in_uop.bits.is_unique, issue_slots[25].in_uop.bits.is_unique connect slots_25.io.in_uop.bits.is_sys_pc2epc, issue_slots[25].in_uop.bits.is_sys_pc2epc connect slots_25.io.in_uop.bits.uses_stq, issue_slots[25].in_uop.bits.uses_stq connect slots_25.io.in_uop.bits.uses_ldq, issue_slots[25].in_uop.bits.uses_ldq connect slots_25.io.in_uop.bits.is_amo, issue_slots[25].in_uop.bits.is_amo connect slots_25.io.in_uop.bits.is_fencei, issue_slots[25].in_uop.bits.is_fencei connect slots_25.io.in_uop.bits.is_fence, issue_slots[25].in_uop.bits.is_fence connect slots_25.io.in_uop.bits.mem_signed, issue_slots[25].in_uop.bits.mem_signed connect slots_25.io.in_uop.bits.mem_size, issue_slots[25].in_uop.bits.mem_size connect slots_25.io.in_uop.bits.mem_cmd, issue_slots[25].in_uop.bits.mem_cmd connect slots_25.io.in_uop.bits.bypassable, issue_slots[25].in_uop.bits.bypassable connect slots_25.io.in_uop.bits.exc_cause, issue_slots[25].in_uop.bits.exc_cause connect slots_25.io.in_uop.bits.exception, issue_slots[25].in_uop.bits.exception connect slots_25.io.in_uop.bits.stale_pdst, issue_slots[25].in_uop.bits.stale_pdst connect slots_25.io.in_uop.bits.ppred_busy, issue_slots[25].in_uop.bits.ppred_busy connect slots_25.io.in_uop.bits.prs3_busy, issue_slots[25].in_uop.bits.prs3_busy connect slots_25.io.in_uop.bits.prs2_busy, issue_slots[25].in_uop.bits.prs2_busy connect slots_25.io.in_uop.bits.prs1_busy, issue_slots[25].in_uop.bits.prs1_busy connect slots_25.io.in_uop.bits.ppred, issue_slots[25].in_uop.bits.ppred connect slots_25.io.in_uop.bits.prs3, issue_slots[25].in_uop.bits.prs3 connect slots_25.io.in_uop.bits.prs2, issue_slots[25].in_uop.bits.prs2 connect slots_25.io.in_uop.bits.prs1, issue_slots[25].in_uop.bits.prs1 connect slots_25.io.in_uop.bits.pdst, issue_slots[25].in_uop.bits.pdst connect slots_25.io.in_uop.bits.rxq_idx, issue_slots[25].in_uop.bits.rxq_idx connect slots_25.io.in_uop.bits.stq_idx, issue_slots[25].in_uop.bits.stq_idx connect slots_25.io.in_uop.bits.ldq_idx, issue_slots[25].in_uop.bits.ldq_idx connect slots_25.io.in_uop.bits.rob_idx, issue_slots[25].in_uop.bits.rob_idx connect slots_25.io.in_uop.bits.csr_addr, issue_slots[25].in_uop.bits.csr_addr connect slots_25.io.in_uop.bits.imm_packed, issue_slots[25].in_uop.bits.imm_packed connect slots_25.io.in_uop.bits.taken, issue_slots[25].in_uop.bits.taken connect slots_25.io.in_uop.bits.pc_lob, issue_slots[25].in_uop.bits.pc_lob connect slots_25.io.in_uop.bits.edge_inst, issue_slots[25].in_uop.bits.edge_inst connect slots_25.io.in_uop.bits.ftq_idx, issue_slots[25].in_uop.bits.ftq_idx connect slots_25.io.in_uop.bits.br_tag, issue_slots[25].in_uop.bits.br_tag connect slots_25.io.in_uop.bits.br_mask, issue_slots[25].in_uop.bits.br_mask connect slots_25.io.in_uop.bits.is_sfb, issue_slots[25].in_uop.bits.is_sfb connect slots_25.io.in_uop.bits.is_jal, issue_slots[25].in_uop.bits.is_jal connect slots_25.io.in_uop.bits.is_jalr, issue_slots[25].in_uop.bits.is_jalr connect slots_25.io.in_uop.bits.is_br, issue_slots[25].in_uop.bits.is_br connect slots_25.io.in_uop.bits.iw_p2_poisoned, issue_slots[25].in_uop.bits.iw_p2_poisoned connect slots_25.io.in_uop.bits.iw_p1_poisoned, issue_slots[25].in_uop.bits.iw_p1_poisoned connect slots_25.io.in_uop.bits.iw_state, issue_slots[25].in_uop.bits.iw_state connect slots_25.io.in_uop.bits.ctrl.is_std, issue_slots[25].in_uop.bits.ctrl.is_std connect slots_25.io.in_uop.bits.ctrl.is_sta, issue_slots[25].in_uop.bits.ctrl.is_sta connect slots_25.io.in_uop.bits.ctrl.is_load, issue_slots[25].in_uop.bits.ctrl.is_load connect slots_25.io.in_uop.bits.ctrl.csr_cmd, issue_slots[25].in_uop.bits.ctrl.csr_cmd connect slots_25.io.in_uop.bits.ctrl.fcn_dw, issue_slots[25].in_uop.bits.ctrl.fcn_dw connect slots_25.io.in_uop.bits.ctrl.op_fcn, issue_slots[25].in_uop.bits.ctrl.op_fcn connect slots_25.io.in_uop.bits.ctrl.imm_sel, issue_slots[25].in_uop.bits.ctrl.imm_sel connect slots_25.io.in_uop.bits.ctrl.op2_sel, issue_slots[25].in_uop.bits.ctrl.op2_sel connect slots_25.io.in_uop.bits.ctrl.op1_sel, issue_slots[25].in_uop.bits.ctrl.op1_sel connect slots_25.io.in_uop.bits.ctrl.br_type, issue_slots[25].in_uop.bits.ctrl.br_type connect slots_25.io.in_uop.bits.fu_code, issue_slots[25].in_uop.bits.fu_code connect slots_25.io.in_uop.bits.iq_type, issue_slots[25].in_uop.bits.iq_type connect slots_25.io.in_uop.bits.debug_pc, issue_slots[25].in_uop.bits.debug_pc connect slots_25.io.in_uop.bits.is_rvc, issue_slots[25].in_uop.bits.is_rvc connect slots_25.io.in_uop.bits.debug_inst, issue_slots[25].in_uop.bits.debug_inst connect slots_25.io.in_uop.bits.inst, issue_slots[25].in_uop.bits.inst connect slots_25.io.in_uop.bits.uopc, issue_slots[25].in_uop.bits.uopc connect slots_25.io.in_uop.valid, issue_slots[25].in_uop.valid connect slots_25.io.spec_ld_wakeup[0].bits, issue_slots[25].spec_ld_wakeup[0].bits connect slots_25.io.spec_ld_wakeup[0].valid, issue_slots[25].spec_ld_wakeup[0].valid connect slots_25.io.pred_wakeup_port.bits, issue_slots[25].pred_wakeup_port.bits connect slots_25.io.pred_wakeup_port.valid, issue_slots[25].pred_wakeup_port.valid connect slots_25.io.wakeup_ports[0].bits.poisoned, issue_slots[25].wakeup_ports[0].bits.poisoned connect slots_25.io.wakeup_ports[0].bits.pdst, issue_slots[25].wakeup_ports[0].bits.pdst connect slots_25.io.wakeup_ports[0].valid, issue_slots[25].wakeup_ports[0].valid connect slots_25.io.wakeup_ports[1].bits.poisoned, issue_slots[25].wakeup_ports[1].bits.poisoned connect slots_25.io.wakeup_ports[1].bits.pdst, issue_slots[25].wakeup_ports[1].bits.pdst connect slots_25.io.wakeup_ports[1].valid, issue_slots[25].wakeup_ports[1].valid connect slots_25.io.wakeup_ports[2].bits.poisoned, issue_slots[25].wakeup_ports[2].bits.poisoned connect slots_25.io.wakeup_ports[2].bits.pdst, issue_slots[25].wakeup_ports[2].bits.pdst connect slots_25.io.wakeup_ports[2].valid, issue_slots[25].wakeup_ports[2].valid connect slots_25.io.wakeup_ports[3].bits.poisoned, issue_slots[25].wakeup_ports[3].bits.poisoned connect slots_25.io.wakeup_ports[3].bits.pdst, issue_slots[25].wakeup_ports[3].bits.pdst connect slots_25.io.wakeup_ports[3].valid, issue_slots[25].wakeup_ports[3].valid connect slots_25.io.wakeup_ports[4].bits.poisoned, issue_slots[25].wakeup_ports[4].bits.poisoned connect slots_25.io.wakeup_ports[4].bits.pdst, issue_slots[25].wakeup_ports[4].bits.pdst connect slots_25.io.wakeup_ports[4].valid, issue_slots[25].wakeup_ports[4].valid connect slots_25.io.wakeup_ports[5].bits.poisoned, issue_slots[25].wakeup_ports[5].bits.poisoned connect slots_25.io.wakeup_ports[5].bits.pdst, issue_slots[25].wakeup_ports[5].bits.pdst connect slots_25.io.wakeup_ports[5].valid, issue_slots[25].wakeup_ports[5].valid connect slots_25.io.wakeup_ports[6].bits.poisoned, issue_slots[25].wakeup_ports[6].bits.poisoned connect slots_25.io.wakeup_ports[6].bits.pdst, issue_slots[25].wakeup_ports[6].bits.pdst connect slots_25.io.wakeup_ports[6].valid, issue_slots[25].wakeup_ports[6].valid connect slots_25.io.ldspec_miss, issue_slots[25].ldspec_miss connect slots_25.io.clear, issue_slots[25].clear connect slots_25.io.kill, issue_slots[25].kill connect slots_25.io.brupdate.b2.target_offset, issue_slots[25].brupdate.b2.target_offset connect slots_25.io.brupdate.b2.jalr_target, issue_slots[25].brupdate.b2.jalr_target connect slots_25.io.brupdate.b2.pc_sel, issue_slots[25].brupdate.b2.pc_sel connect slots_25.io.brupdate.b2.cfi_type, issue_slots[25].brupdate.b2.cfi_type connect slots_25.io.brupdate.b2.taken, issue_slots[25].brupdate.b2.taken connect slots_25.io.brupdate.b2.mispredict, issue_slots[25].brupdate.b2.mispredict connect slots_25.io.brupdate.b2.valid, issue_slots[25].brupdate.b2.valid connect slots_25.io.brupdate.b2.uop.debug_tsrc, issue_slots[25].brupdate.b2.uop.debug_tsrc connect slots_25.io.brupdate.b2.uop.debug_fsrc, issue_slots[25].brupdate.b2.uop.debug_fsrc connect slots_25.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[25].brupdate.b2.uop.bp_xcpt_if connect slots_25.io.brupdate.b2.uop.bp_debug_if, issue_slots[25].brupdate.b2.uop.bp_debug_if connect slots_25.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[25].brupdate.b2.uop.xcpt_ma_if connect slots_25.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[25].brupdate.b2.uop.xcpt_ae_if connect slots_25.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[25].brupdate.b2.uop.xcpt_pf_if connect slots_25.io.brupdate.b2.uop.fp_single, issue_slots[25].brupdate.b2.uop.fp_single connect slots_25.io.brupdate.b2.uop.fp_val, issue_slots[25].brupdate.b2.uop.fp_val connect slots_25.io.brupdate.b2.uop.frs3_en, issue_slots[25].brupdate.b2.uop.frs3_en connect slots_25.io.brupdate.b2.uop.lrs2_rtype, issue_slots[25].brupdate.b2.uop.lrs2_rtype connect slots_25.io.brupdate.b2.uop.lrs1_rtype, issue_slots[25].brupdate.b2.uop.lrs1_rtype connect slots_25.io.brupdate.b2.uop.dst_rtype, issue_slots[25].brupdate.b2.uop.dst_rtype connect slots_25.io.brupdate.b2.uop.ldst_val, issue_slots[25].brupdate.b2.uop.ldst_val connect slots_25.io.brupdate.b2.uop.lrs3, issue_slots[25].brupdate.b2.uop.lrs3 connect slots_25.io.brupdate.b2.uop.lrs2, issue_slots[25].brupdate.b2.uop.lrs2 connect slots_25.io.brupdate.b2.uop.lrs1, issue_slots[25].brupdate.b2.uop.lrs1 connect slots_25.io.brupdate.b2.uop.ldst, issue_slots[25].brupdate.b2.uop.ldst connect slots_25.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[25].brupdate.b2.uop.ldst_is_rs1 connect slots_25.io.brupdate.b2.uop.flush_on_commit, issue_slots[25].brupdate.b2.uop.flush_on_commit connect slots_25.io.brupdate.b2.uop.is_unique, issue_slots[25].brupdate.b2.uop.is_unique connect slots_25.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[25].brupdate.b2.uop.is_sys_pc2epc connect slots_25.io.brupdate.b2.uop.uses_stq, issue_slots[25].brupdate.b2.uop.uses_stq connect slots_25.io.brupdate.b2.uop.uses_ldq, issue_slots[25].brupdate.b2.uop.uses_ldq connect slots_25.io.brupdate.b2.uop.is_amo, issue_slots[25].brupdate.b2.uop.is_amo connect slots_25.io.brupdate.b2.uop.is_fencei, issue_slots[25].brupdate.b2.uop.is_fencei connect slots_25.io.brupdate.b2.uop.is_fence, issue_slots[25].brupdate.b2.uop.is_fence connect slots_25.io.brupdate.b2.uop.mem_signed, issue_slots[25].brupdate.b2.uop.mem_signed connect slots_25.io.brupdate.b2.uop.mem_size, issue_slots[25].brupdate.b2.uop.mem_size connect slots_25.io.brupdate.b2.uop.mem_cmd, issue_slots[25].brupdate.b2.uop.mem_cmd connect slots_25.io.brupdate.b2.uop.bypassable, issue_slots[25].brupdate.b2.uop.bypassable connect slots_25.io.brupdate.b2.uop.exc_cause, issue_slots[25].brupdate.b2.uop.exc_cause connect slots_25.io.brupdate.b2.uop.exception, issue_slots[25].brupdate.b2.uop.exception connect slots_25.io.brupdate.b2.uop.stale_pdst, issue_slots[25].brupdate.b2.uop.stale_pdst connect slots_25.io.brupdate.b2.uop.ppred_busy, issue_slots[25].brupdate.b2.uop.ppred_busy connect slots_25.io.brupdate.b2.uop.prs3_busy, issue_slots[25].brupdate.b2.uop.prs3_busy connect slots_25.io.brupdate.b2.uop.prs2_busy, issue_slots[25].brupdate.b2.uop.prs2_busy connect slots_25.io.brupdate.b2.uop.prs1_busy, issue_slots[25].brupdate.b2.uop.prs1_busy connect slots_25.io.brupdate.b2.uop.ppred, issue_slots[25].brupdate.b2.uop.ppred connect slots_25.io.brupdate.b2.uop.prs3, issue_slots[25].brupdate.b2.uop.prs3 connect slots_25.io.brupdate.b2.uop.prs2, issue_slots[25].brupdate.b2.uop.prs2 connect slots_25.io.brupdate.b2.uop.prs1, issue_slots[25].brupdate.b2.uop.prs1 connect slots_25.io.brupdate.b2.uop.pdst, issue_slots[25].brupdate.b2.uop.pdst connect slots_25.io.brupdate.b2.uop.rxq_idx, issue_slots[25].brupdate.b2.uop.rxq_idx connect slots_25.io.brupdate.b2.uop.stq_idx, issue_slots[25].brupdate.b2.uop.stq_idx connect slots_25.io.brupdate.b2.uop.ldq_idx, issue_slots[25].brupdate.b2.uop.ldq_idx connect slots_25.io.brupdate.b2.uop.rob_idx, issue_slots[25].brupdate.b2.uop.rob_idx connect slots_25.io.brupdate.b2.uop.csr_addr, issue_slots[25].brupdate.b2.uop.csr_addr connect slots_25.io.brupdate.b2.uop.imm_packed, issue_slots[25].brupdate.b2.uop.imm_packed connect slots_25.io.brupdate.b2.uop.taken, issue_slots[25].brupdate.b2.uop.taken connect slots_25.io.brupdate.b2.uop.pc_lob, issue_slots[25].brupdate.b2.uop.pc_lob connect slots_25.io.brupdate.b2.uop.edge_inst, issue_slots[25].brupdate.b2.uop.edge_inst connect slots_25.io.brupdate.b2.uop.ftq_idx, issue_slots[25].brupdate.b2.uop.ftq_idx connect slots_25.io.brupdate.b2.uop.br_tag, issue_slots[25].brupdate.b2.uop.br_tag connect slots_25.io.brupdate.b2.uop.br_mask, issue_slots[25].brupdate.b2.uop.br_mask connect slots_25.io.brupdate.b2.uop.is_sfb, issue_slots[25].brupdate.b2.uop.is_sfb connect slots_25.io.brupdate.b2.uop.is_jal, issue_slots[25].brupdate.b2.uop.is_jal connect slots_25.io.brupdate.b2.uop.is_jalr, issue_slots[25].brupdate.b2.uop.is_jalr connect slots_25.io.brupdate.b2.uop.is_br, issue_slots[25].brupdate.b2.uop.is_br connect slots_25.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[25].brupdate.b2.uop.iw_p2_poisoned connect slots_25.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[25].brupdate.b2.uop.iw_p1_poisoned connect slots_25.io.brupdate.b2.uop.iw_state, issue_slots[25].brupdate.b2.uop.iw_state connect slots_25.io.brupdate.b2.uop.ctrl.is_std, issue_slots[25].brupdate.b2.uop.ctrl.is_std connect slots_25.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[25].brupdate.b2.uop.ctrl.is_sta connect slots_25.io.brupdate.b2.uop.ctrl.is_load, issue_slots[25].brupdate.b2.uop.ctrl.is_load connect slots_25.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[25].brupdate.b2.uop.ctrl.csr_cmd connect slots_25.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[25].brupdate.b2.uop.ctrl.fcn_dw connect slots_25.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[25].brupdate.b2.uop.ctrl.op_fcn connect slots_25.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[25].brupdate.b2.uop.ctrl.imm_sel connect slots_25.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[25].brupdate.b2.uop.ctrl.op2_sel connect slots_25.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[25].brupdate.b2.uop.ctrl.op1_sel connect slots_25.io.brupdate.b2.uop.ctrl.br_type, issue_slots[25].brupdate.b2.uop.ctrl.br_type connect slots_25.io.brupdate.b2.uop.fu_code, issue_slots[25].brupdate.b2.uop.fu_code connect slots_25.io.brupdate.b2.uop.iq_type, issue_slots[25].brupdate.b2.uop.iq_type connect slots_25.io.brupdate.b2.uop.debug_pc, issue_slots[25].brupdate.b2.uop.debug_pc connect slots_25.io.brupdate.b2.uop.is_rvc, issue_slots[25].brupdate.b2.uop.is_rvc connect slots_25.io.brupdate.b2.uop.debug_inst, issue_slots[25].brupdate.b2.uop.debug_inst connect slots_25.io.brupdate.b2.uop.inst, issue_slots[25].brupdate.b2.uop.inst connect slots_25.io.brupdate.b2.uop.uopc, issue_slots[25].brupdate.b2.uop.uopc connect slots_25.io.brupdate.b1.mispredict_mask, issue_slots[25].brupdate.b1.mispredict_mask connect slots_25.io.brupdate.b1.resolve_mask, issue_slots[25].brupdate.b1.resolve_mask connect slots_25.io.grant, issue_slots[25].grant connect issue_slots[25].request_hp, slots_25.io.request_hp connect issue_slots[25].request, slots_25.io.request connect issue_slots[25].will_be_valid, slots_25.io.will_be_valid connect issue_slots[25].valid, slots_25.io.valid connect issue_slots[26].debug.state, slots_26.io.debug.state connect issue_slots[26].debug.ppred, slots_26.io.debug.ppred connect issue_slots[26].debug.p3, slots_26.io.debug.p3 connect issue_slots[26].debug.p2, slots_26.io.debug.p2 connect issue_slots[26].debug.p1, slots_26.io.debug.p1 connect issue_slots[26].uop.debug_tsrc, slots_26.io.uop.debug_tsrc connect issue_slots[26].uop.debug_fsrc, slots_26.io.uop.debug_fsrc connect issue_slots[26].uop.bp_xcpt_if, slots_26.io.uop.bp_xcpt_if connect issue_slots[26].uop.bp_debug_if, slots_26.io.uop.bp_debug_if connect issue_slots[26].uop.xcpt_ma_if, slots_26.io.uop.xcpt_ma_if connect issue_slots[26].uop.xcpt_ae_if, slots_26.io.uop.xcpt_ae_if connect issue_slots[26].uop.xcpt_pf_if, slots_26.io.uop.xcpt_pf_if connect issue_slots[26].uop.fp_single, slots_26.io.uop.fp_single connect issue_slots[26].uop.fp_val, slots_26.io.uop.fp_val connect issue_slots[26].uop.frs3_en, slots_26.io.uop.frs3_en connect issue_slots[26].uop.lrs2_rtype, slots_26.io.uop.lrs2_rtype connect issue_slots[26].uop.lrs1_rtype, slots_26.io.uop.lrs1_rtype connect issue_slots[26].uop.dst_rtype, slots_26.io.uop.dst_rtype connect issue_slots[26].uop.ldst_val, slots_26.io.uop.ldst_val connect issue_slots[26].uop.lrs3, slots_26.io.uop.lrs3 connect issue_slots[26].uop.lrs2, slots_26.io.uop.lrs2 connect issue_slots[26].uop.lrs1, slots_26.io.uop.lrs1 connect issue_slots[26].uop.ldst, slots_26.io.uop.ldst connect issue_slots[26].uop.ldst_is_rs1, slots_26.io.uop.ldst_is_rs1 connect issue_slots[26].uop.flush_on_commit, slots_26.io.uop.flush_on_commit connect issue_slots[26].uop.is_unique, slots_26.io.uop.is_unique connect issue_slots[26].uop.is_sys_pc2epc, slots_26.io.uop.is_sys_pc2epc connect issue_slots[26].uop.uses_stq, slots_26.io.uop.uses_stq connect issue_slots[26].uop.uses_ldq, slots_26.io.uop.uses_ldq connect issue_slots[26].uop.is_amo, slots_26.io.uop.is_amo connect issue_slots[26].uop.is_fencei, slots_26.io.uop.is_fencei connect issue_slots[26].uop.is_fence, slots_26.io.uop.is_fence connect issue_slots[26].uop.mem_signed, slots_26.io.uop.mem_signed connect issue_slots[26].uop.mem_size, slots_26.io.uop.mem_size connect issue_slots[26].uop.mem_cmd, slots_26.io.uop.mem_cmd connect issue_slots[26].uop.bypassable, slots_26.io.uop.bypassable connect issue_slots[26].uop.exc_cause, slots_26.io.uop.exc_cause connect issue_slots[26].uop.exception, slots_26.io.uop.exception connect issue_slots[26].uop.stale_pdst, slots_26.io.uop.stale_pdst connect issue_slots[26].uop.ppred_busy, slots_26.io.uop.ppred_busy connect issue_slots[26].uop.prs3_busy, slots_26.io.uop.prs3_busy connect issue_slots[26].uop.prs2_busy, slots_26.io.uop.prs2_busy connect issue_slots[26].uop.prs1_busy, slots_26.io.uop.prs1_busy connect issue_slots[26].uop.ppred, slots_26.io.uop.ppred connect issue_slots[26].uop.prs3, slots_26.io.uop.prs3 connect issue_slots[26].uop.prs2, slots_26.io.uop.prs2 connect issue_slots[26].uop.prs1, slots_26.io.uop.prs1 connect issue_slots[26].uop.pdst, slots_26.io.uop.pdst connect issue_slots[26].uop.rxq_idx, slots_26.io.uop.rxq_idx connect issue_slots[26].uop.stq_idx, slots_26.io.uop.stq_idx connect issue_slots[26].uop.ldq_idx, slots_26.io.uop.ldq_idx connect issue_slots[26].uop.rob_idx, slots_26.io.uop.rob_idx connect issue_slots[26].uop.csr_addr, slots_26.io.uop.csr_addr connect issue_slots[26].uop.imm_packed, slots_26.io.uop.imm_packed connect issue_slots[26].uop.taken, slots_26.io.uop.taken connect issue_slots[26].uop.pc_lob, slots_26.io.uop.pc_lob connect issue_slots[26].uop.edge_inst, slots_26.io.uop.edge_inst connect issue_slots[26].uop.ftq_idx, slots_26.io.uop.ftq_idx connect issue_slots[26].uop.br_tag, slots_26.io.uop.br_tag connect issue_slots[26].uop.br_mask, slots_26.io.uop.br_mask connect issue_slots[26].uop.is_sfb, slots_26.io.uop.is_sfb connect issue_slots[26].uop.is_jal, slots_26.io.uop.is_jal connect issue_slots[26].uop.is_jalr, slots_26.io.uop.is_jalr connect issue_slots[26].uop.is_br, slots_26.io.uop.is_br connect issue_slots[26].uop.iw_p2_poisoned, slots_26.io.uop.iw_p2_poisoned connect issue_slots[26].uop.iw_p1_poisoned, slots_26.io.uop.iw_p1_poisoned connect issue_slots[26].uop.iw_state, slots_26.io.uop.iw_state connect issue_slots[26].uop.ctrl.is_std, slots_26.io.uop.ctrl.is_std connect issue_slots[26].uop.ctrl.is_sta, slots_26.io.uop.ctrl.is_sta connect issue_slots[26].uop.ctrl.is_load, slots_26.io.uop.ctrl.is_load connect issue_slots[26].uop.ctrl.csr_cmd, slots_26.io.uop.ctrl.csr_cmd connect issue_slots[26].uop.ctrl.fcn_dw, slots_26.io.uop.ctrl.fcn_dw connect issue_slots[26].uop.ctrl.op_fcn, slots_26.io.uop.ctrl.op_fcn connect issue_slots[26].uop.ctrl.imm_sel, slots_26.io.uop.ctrl.imm_sel connect issue_slots[26].uop.ctrl.op2_sel, slots_26.io.uop.ctrl.op2_sel connect issue_slots[26].uop.ctrl.op1_sel, slots_26.io.uop.ctrl.op1_sel connect issue_slots[26].uop.ctrl.br_type, slots_26.io.uop.ctrl.br_type connect issue_slots[26].uop.fu_code, slots_26.io.uop.fu_code connect issue_slots[26].uop.iq_type, slots_26.io.uop.iq_type connect issue_slots[26].uop.debug_pc, slots_26.io.uop.debug_pc connect issue_slots[26].uop.is_rvc, slots_26.io.uop.is_rvc connect issue_slots[26].uop.debug_inst, slots_26.io.uop.debug_inst connect issue_slots[26].uop.inst, slots_26.io.uop.inst connect issue_slots[26].uop.uopc, slots_26.io.uop.uopc connect issue_slots[26].out_uop.debug_tsrc, slots_26.io.out_uop.debug_tsrc connect issue_slots[26].out_uop.debug_fsrc, slots_26.io.out_uop.debug_fsrc connect issue_slots[26].out_uop.bp_xcpt_if, slots_26.io.out_uop.bp_xcpt_if connect issue_slots[26].out_uop.bp_debug_if, slots_26.io.out_uop.bp_debug_if connect issue_slots[26].out_uop.xcpt_ma_if, slots_26.io.out_uop.xcpt_ma_if connect issue_slots[26].out_uop.xcpt_ae_if, slots_26.io.out_uop.xcpt_ae_if connect issue_slots[26].out_uop.xcpt_pf_if, slots_26.io.out_uop.xcpt_pf_if connect issue_slots[26].out_uop.fp_single, slots_26.io.out_uop.fp_single connect issue_slots[26].out_uop.fp_val, slots_26.io.out_uop.fp_val connect issue_slots[26].out_uop.frs3_en, slots_26.io.out_uop.frs3_en connect issue_slots[26].out_uop.lrs2_rtype, slots_26.io.out_uop.lrs2_rtype connect issue_slots[26].out_uop.lrs1_rtype, slots_26.io.out_uop.lrs1_rtype connect issue_slots[26].out_uop.dst_rtype, slots_26.io.out_uop.dst_rtype connect issue_slots[26].out_uop.ldst_val, slots_26.io.out_uop.ldst_val connect issue_slots[26].out_uop.lrs3, slots_26.io.out_uop.lrs3 connect issue_slots[26].out_uop.lrs2, slots_26.io.out_uop.lrs2 connect issue_slots[26].out_uop.lrs1, slots_26.io.out_uop.lrs1 connect issue_slots[26].out_uop.ldst, slots_26.io.out_uop.ldst connect issue_slots[26].out_uop.ldst_is_rs1, slots_26.io.out_uop.ldst_is_rs1 connect issue_slots[26].out_uop.flush_on_commit, slots_26.io.out_uop.flush_on_commit connect issue_slots[26].out_uop.is_unique, slots_26.io.out_uop.is_unique connect issue_slots[26].out_uop.is_sys_pc2epc, slots_26.io.out_uop.is_sys_pc2epc connect issue_slots[26].out_uop.uses_stq, slots_26.io.out_uop.uses_stq connect issue_slots[26].out_uop.uses_ldq, slots_26.io.out_uop.uses_ldq connect issue_slots[26].out_uop.is_amo, slots_26.io.out_uop.is_amo connect issue_slots[26].out_uop.is_fencei, slots_26.io.out_uop.is_fencei connect issue_slots[26].out_uop.is_fence, slots_26.io.out_uop.is_fence connect issue_slots[26].out_uop.mem_signed, slots_26.io.out_uop.mem_signed connect issue_slots[26].out_uop.mem_size, slots_26.io.out_uop.mem_size connect issue_slots[26].out_uop.mem_cmd, slots_26.io.out_uop.mem_cmd connect issue_slots[26].out_uop.bypassable, slots_26.io.out_uop.bypassable connect issue_slots[26].out_uop.exc_cause, slots_26.io.out_uop.exc_cause connect issue_slots[26].out_uop.exception, slots_26.io.out_uop.exception connect issue_slots[26].out_uop.stale_pdst, slots_26.io.out_uop.stale_pdst connect issue_slots[26].out_uop.ppred_busy, slots_26.io.out_uop.ppred_busy connect issue_slots[26].out_uop.prs3_busy, slots_26.io.out_uop.prs3_busy connect issue_slots[26].out_uop.prs2_busy, slots_26.io.out_uop.prs2_busy connect issue_slots[26].out_uop.prs1_busy, slots_26.io.out_uop.prs1_busy connect issue_slots[26].out_uop.ppred, slots_26.io.out_uop.ppred connect issue_slots[26].out_uop.prs3, slots_26.io.out_uop.prs3 connect issue_slots[26].out_uop.prs2, slots_26.io.out_uop.prs2 connect issue_slots[26].out_uop.prs1, slots_26.io.out_uop.prs1 connect issue_slots[26].out_uop.pdst, slots_26.io.out_uop.pdst connect issue_slots[26].out_uop.rxq_idx, slots_26.io.out_uop.rxq_idx connect issue_slots[26].out_uop.stq_idx, slots_26.io.out_uop.stq_idx connect issue_slots[26].out_uop.ldq_idx, slots_26.io.out_uop.ldq_idx connect issue_slots[26].out_uop.rob_idx, slots_26.io.out_uop.rob_idx connect issue_slots[26].out_uop.csr_addr, slots_26.io.out_uop.csr_addr connect issue_slots[26].out_uop.imm_packed, slots_26.io.out_uop.imm_packed connect issue_slots[26].out_uop.taken, slots_26.io.out_uop.taken connect issue_slots[26].out_uop.pc_lob, slots_26.io.out_uop.pc_lob connect issue_slots[26].out_uop.edge_inst, slots_26.io.out_uop.edge_inst connect issue_slots[26].out_uop.ftq_idx, slots_26.io.out_uop.ftq_idx connect issue_slots[26].out_uop.br_tag, slots_26.io.out_uop.br_tag connect issue_slots[26].out_uop.br_mask, slots_26.io.out_uop.br_mask connect issue_slots[26].out_uop.is_sfb, slots_26.io.out_uop.is_sfb connect issue_slots[26].out_uop.is_jal, slots_26.io.out_uop.is_jal connect issue_slots[26].out_uop.is_jalr, slots_26.io.out_uop.is_jalr connect issue_slots[26].out_uop.is_br, slots_26.io.out_uop.is_br connect issue_slots[26].out_uop.iw_p2_poisoned, slots_26.io.out_uop.iw_p2_poisoned connect issue_slots[26].out_uop.iw_p1_poisoned, slots_26.io.out_uop.iw_p1_poisoned connect issue_slots[26].out_uop.iw_state, slots_26.io.out_uop.iw_state connect issue_slots[26].out_uop.ctrl.is_std, slots_26.io.out_uop.ctrl.is_std connect issue_slots[26].out_uop.ctrl.is_sta, slots_26.io.out_uop.ctrl.is_sta connect issue_slots[26].out_uop.ctrl.is_load, slots_26.io.out_uop.ctrl.is_load connect issue_slots[26].out_uop.ctrl.csr_cmd, slots_26.io.out_uop.ctrl.csr_cmd connect issue_slots[26].out_uop.ctrl.fcn_dw, slots_26.io.out_uop.ctrl.fcn_dw connect issue_slots[26].out_uop.ctrl.op_fcn, slots_26.io.out_uop.ctrl.op_fcn connect issue_slots[26].out_uop.ctrl.imm_sel, slots_26.io.out_uop.ctrl.imm_sel connect issue_slots[26].out_uop.ctrl.op2_sel, slots_26.io.out_uop.ctrl.op2_sel connect issue_slots[26].out_uop.ctrl.op1_sel, slots_26.io.out_uop.ctrl.op1_sel connect issue_slots[26].out_uop.ctrl.br_type, slots_26.io.out_uop.ctrl.br_type connect issue_slots[26].out_uop.fu_code, slots_26.io.out_uop.fu_code connect issue_slots[26].out_uop.iq_type, slots_26.io.out_uop.iq_type connect issue_slots[26].out_uop.debug_pc, slots_26.io.out_uop.debug_pc connect issue_slots[26].out_uop.is_rvc, slots_26.io.out_uop.is_rvc connect issue_slots[26].out_uop.debug_inst, slots_26.io.out_uop.debug_inst connect issue_slots[26].out_uop.inst, slots_26.io.out_uop.inst connect issue_slots[26].out_uop.uopc, slots_26.io.out_uop.uopc connect slots_26.io.in_uop.bits.debug_tsrc, issue_slots[26].in_uop.bits.debug_tsrc connect slots_26.io.in_uop.bits.debug_fsrc, issue_slots[26].in_uop.bits.debug_fsrc connect slots_26.io.in_uop.bits.bp_xcpt_if, issue_slots[26].in_uop.bits.bp_xcpt_if connect slots_26.io.in_uop.bits.bp_debug_if, issue_slots[26].in_uop.bits.bp_debug_if connect slots_26.io.in_uop.bits.xcpt_ma_if, issue_slots[26].in_uop.bits.xcpt_ma_if connect slots_26.io.in_uop.bits.xcpt_ae_if, issue_slots[26].in_uop.bits.xcpt_ae_if connect slots_26.io.in_uop.bits.xcpt_pf_if, issue_slots[26].in_uop.bits.xcpt_pf_if connect slots_26.io.in_uop.bits.fp_single, issue_slots[26].in_uop.bits.fp_single connect slots_26.io.in_uop.bits.fp_val, issue_slots[26].in_uop.bits.fp_val connect slots_26.io.in_uop.bits.frs3_en, issue_slots[26].in_uop.bits.frs3_en connect slots_26.io.in_uop.bits.lrs2_rtype, issue_slots[26].in_uop.bits.lrs2_rtype connect slots_26.io.in_uop.bits.lrs1_rtype, issue_slots[26].in_uop.bits.lrs1_rtype connect slots_26.io.in_uop.bits.dst_rtype, issue_slots[26].in_uop.bits.dst_rtype connect slots_26.io.in_uop.bits.ldst_val, issue_slots[26].in_uop.bits.ldst_val connect slots_26.io.in_uop.bits.lrs3, issue_slots[26].in_uop.bits.lrs3 connect slots_26.io.in_uop.bits.lrs2, issue_slots[26].in_uop.bits.lrs2 connect slots_26.io.in_uop.bits.lrs1, issue_slots[26].in_uop.bits.lrs1 connect slots_26.io.in_uop.bits.ldst, issue_slots[26].in_uop.bits.ldst connect slots_26.io.in_uop.bits.ldst_is_rs1, issue_slots[26].in_uop.bits.ldst_is_rs1 connect slots_26.io.in_uop.bits.flush_on_commit, issue_slots[26].in_uop.bits.flush_on_commit connect slots_26.io.in_uop.bits.is_unique, issue_slots[26].in_uop.bits.is_unique connect slots_26.io.in_uop.bits.is_sys_pc2epc, issue_slots[26].in_uop.bits.is_sys_pc2epc connect slots_26.io.in_uop.bits.uses_stq, issue_slots[26].in_uop.bits.uses_stq connect slots_26.io.in_uop.bits.uses_ldq, issue_slots[26].in_uop.bits.uses_ldq connect slots_26.io.in_uop.bits.is_amo, issue_slots[26].in_uop.bits.is_amo connect slots_26.io.in_uop.bits.is_fencei, issue_slots[26].in_uop.bits.is_fencei connect slots_26.io.in_uop.bits.is_fence, issue_slots[26].in_uop.bits.is_fence connect slots_26.io.in_uop.bits.mem_signed, issue_slots[26].in_uop.bits.mem_signed connect slots_26.io.in_uop.bits.mem_size, issue_slots[26].in_uop.bits.mem_size connect slots_26.io.in_uop.bits.mem_cmd, issue_slots[26].in_uop.bits.mem_cmd connect slots_26.io.in_uop.bits.bypassable, issue_slots[26].in_uop.bits.bypassable connect slots_26.io.in_uop.bits.exc_cause, issue_slots[26].in_uop.bits.exc_cause connect slots_26.io.in_uop.bits.exception, issue_slots[26].in_uop.bits.exception connect slots_26.io.in_uop.bits.stale_pdst, issue_slots[26].in_uop.bits.stale_pdst connect slots_26.io.in_uop.bits.ppred_busy, issue_slots[26].in_uop.bits.ppred_busy connect slots_26.io.in_uop.bits.prs3_busy, issue_slots[26].in_uop.bits.prs3_busy connect slots_26.io.in_uop.bits.prs2_busy, issue_slots[26].in_uop.bits.prs2_busy connect slots_26.io.in_uop.bits.prs1_busy, issue_slots[26].in_uop.bits.prs1_busy connect slots_26.io.in_uop.bits.ppred, issue_slots[26].in_uop.bits.ppred connect slots_26.io.in_uop.bits.prs3, issue_slots[26].in_uop.bits.prs3 connect slots_26.io.in_uop.bits.prs2, issue_slots[26].in_uop.bits.prs2 connect slots_26.io.in_uop.bits.prs1, issue_slots[26].in_uop.bits.prs1 connect slots_26.io.in_uop.bits.pdst, issue_slots[26].in_uop.bits.pdst connect slots_26.io.in_uop.bits.rxq_idx, issue_slots[26].in_uop.bits.rxq_idx connect slots_26.io.in_uop.bits.stq_idx, issue_slots[26].in_uop.bits.stq_idx connect slots_26.io.in_uop.bits.ldq_idx, issue_slots[26].in_uop.bits.ldq_idx connect slots_26.io.in_uop.bits.rob_idx, issue_slots[26].in_uop.bits.rob_idx connect slots_26.io.in_uop.bits.csr_addr, issue_slots[26].in_uop.bits.csr_addr connect slots_26.io.in_uop.bits.imm_packed, issue_slots[26].in_uop.bits.imm_packed connect slots_26.io.in_uop.bits.taken, issue_slots[26].in_uop.bits.taken connect slots_26.io.in_uop.bits.pc_lob, issue_slots[26].in_uop.bits.pc_lob connect slots_26.io.in_uop.bits.edge_inst, issue_slots[26].in_uop.bits.edge_inst connect slots_26.io.in_uop.bits.ftq_idx, issue_slots[26].in_uop.bits.ftq_idx connect slots_26.io.in_uop.bits.br_tag, issue_slots[26].in_uop.bits.br_tag connect slots_26.io.in_uop.bits.br_mask, issue_slots[26].in_uop.bits.br_mask connect slots_26.io.in_uop.bits.is_sfb, issue_slots[26].in_uop.bits.is_sfb connect slots_26.io.in_uop.bits.is_jal, issue_slots[26].in_uop.bits.is_jal connect slots_26.io.in_uop.bits.is_jalr, issue_slots[26].in_uop.bits.is_jalr connect slots_26.io.in_uop.bits.is_br, issue_slots[26].in_uop.bits.is_br connect slots_26.io.in_uop.bits.iw_p2_poisoned, issue_slots[26].in_uop.bits.iw_p2_poisoned connect slots_26.io.in_uop.bits.iw_p1_poisoned, issue_slots[26].in_uop.bits.iw_p1_poisoned connect slots_26.io.in_uop.bits.iw_state, issue_slots[26].in_uop.bits.iw_state connect slots_26.io.in_uop.bits.ctrl.is_std, issue_slots[26].in_uop.bits.ctrl.is_std connect slots_26.io.in_uop.bits.ctrl.is_sta, issue_slots[26].in_uop.bits.ctrl.is_sta connect slots_26.io.in_uop.bits.ctrl.is_load, issue_slots[26].in_uop.bits.ctrl.is_load connect slots_26.io.in_uop.bits.ctrl.csr_cmd, issue_slots[26].in_uop.bits.ctrl.csr_cmd connect slots_26.io.in_uop.bits.ctrl.fcn_dw, issue_slots[26].in_uop.bits.ctrl.fcn_dw connect slots_26.io.in_uop.bits.ctrl.op_fcn, issue_slots[26].in_uop.bits.ctrl.op_fcn connect slots_26.io.in_uop.bits.ctrl.imm_sel, issue_slots[26].in_uop.bits.ctrl.imm_sel connect slots_26.io.in_uop.bits.ctrl.op2_sel, issue_slots[26].in_uop.bits.ctrl.op2_sel connect slots_26.io.in_uop.bits.ctrl.op1_sel, issue_slots[26].in_uop.bits.ctrl.op1_sel connect slots_26.io.in_uop.bits.ctrl.br_type, issue_slots[26].in_uop.bits.ctrl.br_type connect slots_26.io.in_uop.bits.fu_code, issue_slots[26].in_uop.bits.fu_code connect slots_26.io.in_uop.bits.iq_type, issue_slots[26].in_uop.bits.iq_type connect slots_26.io.in_uop.bits.debug_pc, issue_slots[26].in_uop.bits.debug_pc connect slots_26.io.in_uop.bits.is_rvc, issue_slots[26].in_uop.bits.is_rvc connect slots_26.io.in_uop.bits.debug_inst, issue_slots[26].in_uop.bits.debug_inst connect slots_26.io.in_uop.bits.inst, issue_slots[26].in_uop.bits.inst connect slots_26.io.in_uop.bits.uopc, issue_slots[26].in_uop.bits.uopc connect slots_26.io.in_uop.valid, issue_slots[26].in_uop.valid connect slots_26.io.spec_ld_wakeup[0].bits, issue_slots[26].spec_ld_wakeup[0].bits connect slots_26.io.spec_ld_wakeup[0].valid, issue_slots[26].spec_ld_wakeup[0].valid connect slots_26.io.pred_wakeup_port.bits, issue_slots[26].pred_wakeup_port.bits connect slots_26.io.pred_wakeup_port.valid, issue_slots[26].pred_wakeup_port.valid connect slots_26.io.wakeup_ports[0].bits.poisoned, issue_slots[26].wakeup_ports[0].bits.poisoned connect slots_26.io.wakeup_ports[0].bits.pdst, issue_slots[26].wakeup_ports[0].bits.pdst connect slots_26.io.wakeup_ports[0].valid, issue_slots[26].wakeup_ports[0].valid connect slots_26.io.wakeup_ports[1].bits.poisoned, issue_slots[26].wakeup_ports[1].bits.poisoned connect slots_26.io.wakeup_ports[1].bits.pdst, issue_slots[26].wakeup_ports[1].bits.pdst connect slots_26.io.wakeup_ports[1].valid, issue_slots[26].wakeup_ports[1].valid connect slots_26.io.wakeup_ports[2].bits.poisoned, issue_slots[26].wakeup_ports[2].bits.poisoned connect slots_26.io.wakeup_ports[2].bits.pdst, issue_slots[26].wakeup_ports[2].bits.pdst connect slots_26.io.wakeup_ports[2].valid, issue_slots[26].wakeup_ports[2].valid connect slots_26.io.wakeup_ports[3].bits.poisoned, issue_slots[26].wakeup_ports[3].bits.poisoned connect slots_26.io.wakeup_ports[3].bits.pdst, issue_slots[26].wakeup_ports[3].bits.pdst connect slots_26.io.wakeup_ports[3].valid, issue_slots[26].wakeup_ports[3].valid connect slots_26.io.wakeup_ports[4].bits.poisoned, issue_slots[26].wakeup_ports[4].bits.poisoned connect slots_26.io.wakeup_ports[4].bits.pdst, issue_slots[26].wakeup_ports[4].bits.pdst connect slots_26.io.wakeup_ports[4].valid, issue_slots[26].wakeup_ports[4].valid connect slots_26.io.wakeup_ports[5].bits.poisoned, issue_slots[26].wakeup_ports[5].bits.poisoned connect slots_26.io.wakeup_ports[5].bits.pdst, issue_slots[26].wakeup_ports[5].bits.pdst connect slots_26.io.wakeup_ports[5].valid, issue_slots[26].wakeup_ports[5].valid connect slots_26.io.wakeup_ports[6].bits.poisoned, issue_slots[26].wakeup_ports[6].bits.poisoned connect slots_26.io.wakeup_ports[6].bits.pdst, issue_slots[26].wakeup_ports[6].bits.pdst connect slots_26.io.wakeup_ports[6].valid, issue_slots[26].wakeup_ports[6].valid connect slots_26.io.ldspec_miss, issue_slots[26].ldspec_miss connect slots_26.io.clear, issue_slots[26].clear connect slots_26.io.kill, issue_slots[26].kill connect slots_26.io.brupdate.b2.target_offset, issue_slots[26].brupdate.b2.target_offset connect slots_26.io.brupdate.b2.jalr_target, issue_slots[26].brupdate.b2.jalr_target connect slots_26.io.brupdate.b2.pc_sel, issue_slots[26].brupdate.b2.pc_sel connect slots_26.io.brupdate.b2.cfi_type, issue_slots[26].brupdate.b2.cfi_type connect slots_26.io.brupdate.b2.taken, issue_slots[26].brupdate.b2.taken connect slots_26.io.brupdate.b2.mispredict, issue_slots[26].brupdate.b2.mispredict connect slots_26.io.brupdate.b2.valid, issue_slots[26].brupdate.b2.valid connect slots_26.io.brupdate.b2.uop.debug_tsrc, issue_slots[26].brupdate.b2.uop.debug_tsrc connect slots_26.io.brupdate.b2.uop.debug_fsrc, issue_slots[26].brupdate.b2.uop.debug_fsrc connect slots_26.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[26].brupdate.b2.uop.bp_xcpt_if connect slots_26.io.brupdate.b2.uop.bp_debug_if, issue_slots[26].brupdate.b2.uop.bp_debug_if connect slots_26.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[26].brupdate.b2.uop.xcpt_ma_if connect slots_26.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[26].brupdate.b2.uop.xcpt_ae_if connect slots_26.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[26].brupdate.b2.uop.xcpt_pf_if connect slots_26.io.brupdate.b2.uop.fp_single, issue_slots[26].brupdate.b2.uop.fp_single connect slots_26.io.brupdate.b2.uop.fp_val, issue_slots[26].brupdate.b2.uop.fp_val connect slots_26.io.brupdate.b2.uop.frs3_en, issue_slots[26].brupdate.b2.uop.frs3_en connect slots_26.io.brupdate.b2.uop.lrs2_rtype, issue_slots[26].brupdate.b2.uop.lrs2_rtype connect slots_26.io.brupdate.b2.uop.lrs1_rtype, issue_slots[26].brupdate.b2.uop.lrs1_rtype connect slots_26.io.brupdate.b2.uop.dst_rtype, issue_slots[26].brupdate.b2.uop.dst_rtype connect slots_26.io.brupdate.b2.uop.ldst_val, issue_slots[26].brupdate.b2.uop.ldst_val connect slots_26.io.brupdate.b2.uop.lrs3, issue_slots[26].brupdate.b2.uop.lrs3 connect slots_26.io.brupdate.b2.uop.lrs2, issue_slots[26].brupdate.b2.uop.lrs2 connect slots_26.io.brupdate.b2.uop.lrs1, issue_slots[26].brupdate.b2.uop.lrs1 connect slots_26.io.brupdate.b2.uop.ldst, issue_slots[26].brupdate.b2.uop.ldst connect slots_26.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[26].brupdate.b2.uop.ldst_is_rs1 connect slots_26.io.brupdate.b2.uop.flush_on_commit, issue_slots[26].brupdate.b2.uop.flush_on_commit connect slots_26.io.brupdate.b2.uop.is_unique, issue_slots[26].brupdate.b2.uop.is_unique connect slots_26.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[26].brupdate.b2.uop.is_sys_pc2epc connect slots_26.io.brupdate.b2.uop.uses_stq, issue_slots[26].brupdate.b2.uop.uses_stq connect slots_26.io.brupdate.b2.uop.uses_ldq, issue_slots[26].brupdate.b2.uop.uses_ldq connect slots_26.io.brupdate.b2.uop.is_amo, issue_slots[26].brupdate.b2.uop.is_amo connect slots_26.io.brupdate.b2.uop.is_fencei, issue_slots[26].brupdate.b2.uop.is_fencei connect slots_26.io.brupdate.b2.uop.is_fence, issue_slots[26].brupdate.b2.uop.is_fence connect slots_26.io.brupdate.b2.uop.mem_signed, issue_slots[26].brupdate.b2.uop.mem_signed connect slots_26.io.brupdate.b2.uop.mem_size, issue_slots[26].brupdate.b2.uop.mem_size connect slots_26.io.brupdate.b2.uop.mem_cmd, issue_slots[26].brupdate.b2.uop.mem_cmd connect slots_26.io.brupdate.b2.uop.bypassable, issue_slots[26].brupdate.b2.uop.bypassable connect slots_26.io.brupdate.b2.uop.exc_cause, issue_slots[26].brupdate.b2.uop.exc_cause connect slots_26.io.brupdate.b2.uop.exception, issue_slots[26].brupdate.b2.uop.exception connect slots_26.io.brupdate.b2.uop.stale_pdst, issue_slots[26].brupdate.b2.uop.stale_pdst connect slots_26.io.brupdate.b2.uop.ppred_busy, issue_slots[26].brupdate.b2.uop.ppred_busy connect slots_26.io.brupdate.b2.uop.prs3_busy, issue_slots[26].brupdate.b2.uop.prs3_busy connect slots_26.io.brupdate.b2.uop.prs2_busy, issue_slots[26].brupdate.b2.uop.prs2_busy connect slots_26.io.brupdate.b2.uop.prs1_busy, issue_slots[26].brupdate.b2.uop.prs1_busy connect slots_26.io.brupdate.b2.uop.ppred, issue_slots[26].brupdate.b2.uop.ppred connect slots_26.io.brupdate.b2.uop.prs3, issue_slots[26].brupdate.b2.uop.prs3 connect slots_26.io.brupdate.b2.uop.prs2, issue_slots[26].brupdate.b2.uop.prs2 connect slots_26.io.brupdate.b2.uop.prs1, issue_slots[26].brupdate.b2.uop.prs1 connect slots_26.io.brupdate.b2.uop.pdst, issue_slots[26].brupdate.b2.uop.pdst connect slots_26.io.brupdate.b2.uop.rxq_idx, issue_slots[26].brupdate.b2.uop.rxq_idx connect slots_26.io.brupdate.b2.uop.stq_idx, issue_slots[26].brupdate.b2.uop.stq_idx connect slots_26.io.brupdate.b2.uop.ldq_idx, issue_slots[26].brupdate.b2.uop.ldq_idx connect slots_26.io.brupdate.b2.uop.rob_idx, issue_slots[26].brupdate.b2.uop.rob_idx connect slots_26.io.brupdate.b2.uop.csr_addr, issue_slots[26].brupdate.b2.uop.csr_addr connect slots_26.io.brupdate.b2.uop.imm_packed, issue_slots[26].brupdate.b2.uop.imm_packed connect slots_26.io.brupdate.b2.uop.taken, issue_slots[26].brupdate.b2.uop.taken connect slots_26.io.brupdate.b2.uop.pc_lob, issue_slots[26].brupdate.b2.uop.pc_lob connect slots_26.io.brupdate.b2.uop.edge_inst, issue_slots[26].brupdate.b2.uop.edge_inst connect slots_26.io.brupdate.b2.uop.ftq_idx, issue_slots[26].brupdate.b2.uop.ftq_idx connect slots_26.io.brupdate.b2.uop.br_tag, issue_slots[26].brupdate.b2.uop.br_tag connect slots_26.io.brupdate.b2.uop.br_mask, issue_slots[26].brupdate.b2.uop.br_mask connect slots_26.io.brupdate.b2.uop.is_sfb, issue_slots[26].brupdate.b2.uop.is_sfb connect slots_26.io.brupdate.b2.uop.is_jal, issue_slots[26].brupdate.b2.uop.is_jal connect slots_26.io.brupdate.b2.uop.is_jalr, issue_slots[26].brupdate.b2.uop.is_jalr connect slots_26.io.brupdate.b2.uop.is_br, issue_slots[26].brupdate.b2.uop.is_br connect slots_26.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[26].brupdate.b2.uop.iw_p2_poisoned connect slots_26.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[26].brupdate.b2.uop.iw_p1_poisoned connect slots_26.io.brupdate.b2.uop.iw_state, issue_slots[26].brupdate.b2.uop.iw_state connect slots_26.io.brupdate.b2.uop.ctrl.is_std, issue_slots[26].brupdate.b2.uop.ctrl.is_std connect slots_26.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[26].brupdate.b2.uop.ctrl.is_sta connect slots_26.io.brupdate.b2.uop.ctrl.is_load, issue_slots[26].brupdate.b2.uop.ctrl.is_load connect slots_26.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[26].brupdate.b2.uop.ctrl.csr_cmd connect slots_26.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[26].brupdate.b2.uop.ctrl.fcn_dw connect slots_26.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[26].brupdate.b2.uop.ctrl.op_fcn connect slots_26.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[26].brupdate.b2.uop.ctrl.imm_sel connect slots_26.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[26].brupdate.b2.uop.ctrl.op2_sel connect slots_26.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[26].brupdate.b2.uop.ctrl.op1_sel connect slots_26.io.brupdate.b2.uop.ctrl.br_type, issue_slots[26].brupdate.b2.uop.ctrl.br_type connect slots_26.io.brupdate.b2.uop.fu_code, issue_slots[26].brupdate.b2.uop.fu_code connect slots_26.io.brupdate.b2.uop.iq_type, issue_slots[26].brupdate.b2.uop.iq_type connect slots_26.io.brupdate.b2.uop.debug_pc, issue_slots[26].brupdate.b2.uop.debug_pc connect slots_26.io.brupdate.b2.uop.is_rvc, issue_slots[26].brupdate.b2.uop.is_rvc connect slots_26.io.brupdate.b2.uop.debug_inst, issue_slots[26].brupdate.b2.uop.debug_inst connect slots_26.io.brupdate.b2.uop.inst, issue_slots[26].brupdate.b2.uop.inst connect slots_26.io.brupdate.b2.uop.uopc, issue_slots[26].brupdate.b2.uop.uopc connect slots_26.io.brupdate.b1.mispredict_mask, issue_slots[26].brupdate.b1.mispredict_mask connect slots_26.io.brupdate.b1.resolve_mask, issue_slots[26].brupdate.b1.resolve_mask connect slots_26.io.grant, issue_slots[26].grant connect issue_slots[26].request_hp, slots_26.io.request_hp connect issue_slots[26].request, slots_26.io.request connect issue_slots[26].will_be_valid, slots_26.io.will_be_valid connect issue_slots[26].valid, slots_26.io.valid connect issue_slots[27].debug.state, slots_27.io.debug.state connect issue_slots[27].debug.ppred, slots_27.io.debug.ppred connect issue_slots[27].debug.p3, slots_27.io.debug.p3 connect issue_slots[27].debug.p2, slots_27.io.debug.p2 connect issue_slots[27].debug.p1, slots_27.io.debug.p1 connect issue_slots[27].uop.debug_tsrc, slots_27.io.uop.debug_tsrc connect issue_slots[27].uop.debug_fsrc, slots_27.io.uop.debug_fsrc connect issue_slots[27].uop.bp_xcpt_if, slots_27.io.uop.bp_xcpt_if connect issue_slots[27].uop.bp_debug_if, slots_27.io.uop.bp_debug_if connect issue_slots[27].uop.xcpt_ma_if, slots_27.io.uop.xcpt_ma_if connect issue_slots[27].uop.xcpt_ae_if, slots_27.io.uop.xcpt_ae_if connect issue_slots[27].uop.xcpt_pf_if, slots_27.io.uop.xcpt_pf_if connect issue_slots[27].uop.fp_single, slots_27.io.uop.fp_single connect issue_slots[27].uop.fp_val, slots_27.io.uop.fp_val connect issue_slots[27].uop.frs3_en, slots_27.io.uop.frs3_en connect issue_slots[27].uop.lrs2_rtype, slots_27.io.uop.lrs2_rtype connect issue_slots[27].uop.lrs1_rtype, slots_27.io.uop.lrs1_rtype connect issue_slots[27].uop.dst_rtype, slots_27.io.uop.dst_rtype connect issue_slots[27].uop.ldst_val, slots_27.io.uop.ldst_val connect issue_slots[27].uop.lrs3, slots_27.io.uop.lrs3 connect issue_slots[27].uop.lrs2, slots_27.io.uop.lrs2 connect issue_slots[27].uop.lrs1, slots_27.io.uop.lrs1 connect issue_slots[27].uop.ldst, slots_27.io.uop.ldst connect issue_slots[27].uop.ldst_is_rs1, slots_27.io.uop.ldst_is_rs1 connect issue_slots[27].uop.flush_on_commit, slots_27.io.uop.flush_on_commit connect issue_slots[27].uop.is_unique, slots_27.io.uop.is_unique connect issue_slots[27].uop.is_sys_pc2epc, slots_27.io.uop.is_sys_pc2epc connect issue_slots[27].uop.uses_stq, slots_27.io.uop.uses_stq connect issue_slots[27].uop.uses_ldq, slots_27.io.uop.uses_ldq connect issue_slots[27].uop.is_amo, slots_27.io.uop.is_amo connect issue_slots[27].uop.is_fencei, slots_27.io.uop.is_fencei connect issue_slots[27].uop.is_fence, slots_27.io.uop.is_fence connect issue_slots[27].uop.mem_signed, slots_27.io.uop.mem_signed connect issue_slots[27].uop.mem_size, slots_27.io.uop.mem_size connect issue_slots[27].uop.mem_cmd, slots_27.io.uop.mem_cmd connect issue_slots[27].uop.bypassable, slots_27.io.uop.bypassable connect issue_slots[27].uop.exc_cause, slots_27.io.uop.exc_cause connect issue_slots[27].uop.exception, slots_27.io.uop.exception connect issue_slots[27].uop.stale_pdst, slots_27.io.uop.stale_pdst connect issue_slots[27].uop.ppred_busy, slots_27.io.uop.ppred_busy connect issue_slots[27].uop.prs3_busy, slots_27.io.uop.prs3_busy connect issue_slots[27].uop.prs2_busy, slots_27.io.uop.prs2_busy connect issue_slots[27].uop.prs1_busy, slots_27.io.uop.prs1_busy connect issue_slots[27].uop.ppred, slots_27.io.uop.ppred connect issue_slots[27].uop.prs3, slots_27.io.uop.prs3 connect issue_slots[27].uop.prs2, slots_27.io.uop.prs2 connect issue_slots[27].uop.prs1, slots_27.io.uop.prs1 connect issue_slots[27].uop.pdst, slots_27.io.uop.pdst connect issue_slots[27].uop.rxq_idx, slots_27.io.uop.rxq_idx connect issue_slots[27].uop.stq_idx, slots_27.io.uop.stq_idx connect issue_slots[27].uop.ldq_idx, slots_27.io.uop.ldq_idx connect issue_slots[27].uop.rob_idx, slots_27.io.uop.rob_idx connect issue_slots[27].uop.csr_addr, slots_27.io.uop.csr_addr connect issue_slots[27].uop.imm_packed, slots_27.io.uop.imm_packed connect issue_slots[27].uop.taken, slots_27.io.uop.taken connect issue_slots[27].uop.pc_lob, slots_27.io.uop.pc_lob connect issue_slots[27].uop.edge_inst, slots_27.io.uop.edge_inst connect issue_slots[27].uop.ftq_idx, slots_27.io.uop.ftq_idx connect issue_slots[27].uop.br_tag, slots_27.io.uop.br_tag connect issue_slots[27].uop.br_mask, slots_27.io.uop.br_mask connect issue_slots[27].uop.is_sfb, slots_27.io.uop.is_sfb connect issue_slots[27].uop.is_jal, slots_27.io.uop.is_jal connect issue_slots[27].uop.is_jalr, slots_27.io.uop.is_jalr connect issue_slots[27].uop.is_br, slots_27.io.uop.is_br connect issue_slots[27].uop.iw_p2_poisoned, slots_27.io.uop.iw_p2_poisoned connect issue_slots[27].uop.iw_p1_poisoned, slots_27.io.uop.iw_p1_poisoned connect issue_slots[27].uop.iw_state, slots_27.io.uop.iw_state connect issue_slots[27].uop.ctrl.is_std, slots_27.io.uop.ctrl.is_std connect issue_slots[27].uop.ctrl.is_sta, slots_27.io.uop.ctrl.is_sta connect issue_slots[27].uop.ctrl.is_load, slots_27.io.uop.ctrl.is_load connect issue_slots[27].uop.ctrl.csr_cmd, slots_27.io.uop.ctrl.csr_cmd connect issue_slots[27].uop.ctrl.fcn_dw, slots_27.io.uop.ctrl.fcn_dw connect issue_slots[27].uop.ctrl.op_fcn, slots_27.io.uop.ctrl.op_fcn connect issue_slots[27].uop.ctrl.imm_sel, slots_27.io.uop.ctrl.imm_sel connect issue_slots[27].uop.ctrl.op2_sel, slots_27.io.uop.ctrl.op2_sel connect issue_slots[27].uop.ctrl.op1_sel, slots_27.io.uop.ctrl.op1_sel connect issue_slots[27].uop.ctrl.br_type, slots_27.io.uop.ctrl.br_type connect issue_slots[27].uop.fu_code, slots_27.io.uop.fu_code connect issue_slots[27].uop.iq_type, slots_27.io.uop.iq_type connect issue_slots[27].uop.debug_pc, slots_27.io.uop.debug_pc connect issue_slots[27].uop.is_rvc, slots_27.io.uop.is_rvc connect issue_slots[27].uop.debug_inst, slots_27.io.uop.debug_inst connect issue_slots[27].uop.inst, slots_27.io.uop.inst connect issue_slots[27].uop.uopc, slots_27.io.uop.uopc connect issue_slots[27].out_uop.debug_tsrc, slots_27.io.out_uop.debug_tsrc connect issue_slots[27].out_uop.debug_fsrc, slots_27.io.out_uop.debug_fsrc connect issue_slots[27].out_uop.bp_xcpt_if, slots_27.io.out_uop.bp_xcpt_if connect issue_slots[27].out_uop.bp_debug_if, slots_27.io.out_uop.bp_debug_if connect issue_slots[27].out_uop.xcpt_ma_if, slots_27.io.out_uop.xcpt_ma_if connect issue_slots[27].out_uop.xcpt_ae_if, slots_27.io.out_uop.xcpt_ae_if connect issue_slots[27].out_uop.xcpt_pf_if, slots_27.io.out_uop.xcpt_pf_if connect issue_slots[27].out_uop.fp_single, slots_27.io.out_uop.fp_single connect issue_slots[27].out_uop.fp_val, slots_27.io.out_uop.fp_val connect issue_slots[27].out_uop.frs3_en, slots_27.io.out_uop.frs3_en connect issue_slots[27].out_uop.lrs2_rtype, slots_27.io.out_uop.lrs2_rtype connect issue_slots[27].out_uop.lrs1_rtype, slots_27.io.out_uop.lrs1_rtype connect issue_slots[27].out_uop.dst_rtype, slots_27.io.out_uop.dst_rtype connect issue_slots[27].out_uop.ldst_val, slots_27.io.out_uop.ldst_val connect issue_slots[27].out_uop.lrs3, slots_27.io.out_uop.lrs3 connect issue_slots[27].out_uop.lrs2, slots_27.io.out_uop.lrs2 connect issue_slots[27].out_uop.lrs1, slots_27.io.out_uop.lrs1 connect issue_slots[27].out_uop.ldst, slots_27.io.out_uop.ldst connect issue_slots[27].out_uop.ldst_is_rs1, slots_27.io.out_uop.ldst_is_rs1 connect issue_slots[27].out_uop.flush_on_commit, slots_27.io.out_uop.flush_on_commit connect issue_slots[27].out_uop.is_unique, slots_27.io.out_uop.is_unique connect issue_slots[27].out_uop.is_sys_pc2epc, slots_27.io.out_uop.is_sys_pc2epc connect issue_slots[27].out_uop.uses_stq, slots_27.io.out_uop.uses_stq connect issue_slots[27].out_uop.uses_ldq, slots_27.io.out_uop.uses_ldq connect issue_slots[27].out_uop.is_amo, slots_27.io.out_uop.is_amo connect issue_slots[27].out_uop.is_fencei, slots_27.io.out_uop.is_fencei connect issue_slots[27].out_uop.is_fence, slots_27.io.out_uop.is_fence connect issue_slots[27].out_uop.mem_signed, slots_27.io.out_uop.mem_signed connect issue_slots[27].out_uop.mem_size, slots_27.io.out_uop.mem_size connect issue_slots[27].out_uop.mem_cmd, slots_27.io.out_uop.mem_cmd connect issue_slots[27].out_uop.bypassable, slots_27.io.out_uop.bypassable connect issue_slots[27].out_uop.exc_cause, slots_27.io.out_uop.exc_cause connect issue_slots[27].out_uop.exception, slots_27.io.out_uop.exception connect issue_slots[27].out_uop.stale_pdst, slots_27.io.out_uop.stale_pdst connect issue_slots[27].out_uop.ppred_busy, slots_27.io.out_uop.ppred_busy connect issue_slots[27].out_uop.prs3_busy, slots_27.io.out_uop.prs3_busy connect issue_slots[27].out_uop.prs2_busy, slots_27.io.out_uop.prs2_busy connect issue_slots[27].out_uop.prs1_busy, slots_27.io.out_uop.prs1_busy connect issue_slots[27].out_uop.ppred, slots_27.io.out_uop.ppred connect issue_slots[27].out_uop.prs3, slots_27.io.out_uop.prs3 connect issue_slots[27].out_uop.prs2, slots_27.io.out_uop.prs2 connect issue_slots[27].out_uop.prs1, slots_27.io.out_uop.prs1 connect issue_slots[27].out_uop.pdst, slots_27.io.out_uop.pdst connect issue_slots[27].out_uop.rxq_idx, slots_27.io.out_uop.rxq_idx connect issue_slots[27].out_uop.stq_idx, slots_27.io.out_uop.stq_idx connect issue_slots[27].out_uop.ldq_idx, slots_27.io.out_uop.ldq_idx connect issue_slots[27].out_uop.rob_idx, slots_27.io.out_uop.rob_idx connect issue_slots[27].out_uop.csr_addr, slots_27.io.out_uop.csr_addr connect issue_slots[27].out_uop.imm_packed, slots_27.io.out_uop.imm_packed connect issue_slots[27].out_uop.taken, slots_27.io.out_uop.taken connect issue_slots[27].out_uop.pc_lob, slots_27.io.out_uop.pc_lob connect issue_slots[27].out_uop.edge_inst, slots_27.io.out_uop.edge_inst connect issue_slots[27].out_uop.ftq_idx, slots_27.io.out_uop.ftq_idx connect issue_slots[27].out_uop.br_tag, slots_27.io.out_uop.br_tag connect issue_slots[27].out_uop.br_mask, slots_27.io.out_uop.br_mask connect issue_slots[27].out_uop.is_sfb, slots_27.io.out_uop.is_sfb connect issue_slots[27].out_uop.is_jal, slots_27.io.out_uop.is_jal connect issue_slots[27].out_uop.is_jalr, slots_27.io.out_uop.is_jalr connect issue_slots[27].out_uop.is_br, slots_27.io.out_uop.is_br connect issue_slots[27].out_uop.iw_p2_poisoned, slots_27.io.out_uop.iw_p2_poisoned connect issue_slots[27].out_uop.iw_p1_poisoned, slots_27.io.out_uop.iw_p1_poisoned connect issue_slots[27].out_uop.iw_state, slots_27.io.out_uop.iw_state connect issue_slots[27].out_uop.ctrl.is_std, slots_27.io.out_uop.ctrl.is_std connect issue_slots[27].out_uop.ctrl.is_sta, slots_27.io.out_uop.ctrl.is_sta connect issue_slots[27].out_uop.ctrl.is_load, slots_27.io.out_uop.ctrl.is_load connect issue_slots[27].out_uop.ctrl.csr_cmd, slots_27.io.out_uop.ctrl.csr_cmd connect issue_slots[27].out_uop.ctrl.fcn_dw, slots_27.io.out_uop.ctrl.fcn_dw connect issue_slots[27].out_uop.ctrl.op_fcn, slots_27.io.out_uop.ctrl.op_fcn connect issue_slots[27].out_uop.ctrl.imm_sel, slots_27.io.out_uop.ctrl.imm_sel connect issue_slots[27].out_uop.ctrl.op2_sel, slots_27.io.out_uop.ctrl.op2_sel connect issue_slots[27].out_uop.ctrl.op1_sel, slots_27.io.out_uop.ctrl.op1_sel connect issue_slots[27].out_uop.ctrl.br_type, slots_27.io.out_uop.ctrl.br_type connect issue_slots[27].out_uop.fu_code, slots_27.io.out_uop.fu_code connect issue_slots[27].out_uop.iq_type, slots_27.io.out_uop.iq_type connect issue_slots[27].out_uop.debug_pc, slots_27.io.out_uop.debug_pc connect issue_slots[27].out_uop.is_rvc, slots_27.io.out_uop.is_rvc connect issue_slots[27].out_uop.debug_inst, slots_27.io.out_uop.debug_inst connect issue_slots[27].out_uop.inst, slots_27.io.out_uop.inst connect issue_slots[27].out_uop.uopc, slots_27.io.out_uop.uopc connect slots_27.io.in_uop.bits.debug_tsrc, issue_slots[27].in_uop.bits.debug_tsrc connect slots_27.io.in_uop.bits.debug_fsrc, issue_slots[27].in_uop.bits.debug_fsrc connect slots_27.io.in_uop.bits.bp_xcpt_if, issue_slots[27].in_uop.bits.bp_xcpt_if connect slots_27.io.in_uop.bits.bp_debug_if, issue_slots[27].in_uop.bits.bp_debug_if connect slots_27.io.in_uop.bits.xcpt_ma_if, issue_slots[27].in_uop.bits.xcpt_ma_if connect slots_27.io.in_uop.bits.xcpt_ae_if, issue_slots[27].in_uop.bits.xcpt_ae_if connect slots_27.io.in_uop.bits.xcpt_pf_if, issue_slots[27].in_uop.bits.xcpt_pf_if connect slots_27.io.in_uop.bits.fp_single, issue_slots[27].in_uop.bits.fp_single connect slots_27.io.in_uop.bits.fp_val, issue_slots[27].in_uop.bits.fp_val connect slots_27.io.in_uop.bits.frs3_en, issue_slots[27].in_uop.bits.frs3_en connect slots_27.io.in_uop.bits.lrs2_rtype, issue_slots[27].in_uop.bits.lrs2_rtype connect slots_27.io.in_uop.bits.lrs1_rtype, issue_slots[27].in_uop.bits.lrs1_rtype connect slots_27.io.in_uop.bits.dst_rtype, issue_slots[27].in_uop.bits.dst_rtype connect slots_27.io.in_uop.bits.ldst_val, issue_slots[27].in_uop.bits.ldst_val connect slots_27.io.in_uop.bits.lrs3, issue_slots[27].in_uop.bits.lrs3 connect slots_27.io.in_uop.bits.lrs2, issue_slots[27].in_uop.bits.lrs2 connect slots_27.io.in_uop.bits.lrs1, issue_slots[27].in_uop.bits.lrs1 connect slots_27.io.in_uop.bits.ldst, issue_slots[27].in_uop.bits.ldst connect slots_27.io.in_uop.bits.ldst_is_rs1, issue_slots[27].in_uop.bits.ldst_is_rs1 connect slots_27.io.in_uop.bits.flush_on_commit, issue_slots[27].in_uop.bits.flush_on_commit connect slots_27.io.in_uop.bits.is_unique, issue_slots[27].in_uop.bits.is_unique connect slots_27.io.in_uop.bits.is_sys_pc2epc, issue_slots[27].in_uop.bits.is_sys_pc2epc connect slots_27.io.in_uop.bits.uses_stq, issue_slots[27].in_uop.bits.uses_stq connect slots_27.io.in_uop.bits.uses_ldq, issue_slots[27].in_uop.bits.uses_ldq connect slots_27.io.in_uop.bits.is_amo, issue_slots[27].in_uop.bits.is_amo connect slots_27.io.in_uop.bits.is_fencei, issue_slots[27].in_uop.bits.is_fencei connect slots_27.io.in_uop.bits.is_fence, issue_slots[27].in_uop.bits.is_fence connect slots_27.io.in_uop.bits.mem_signed, issue_slots[27].in_uop.bits.mem_signed connect slots_27.io.in_uop.bits.mem_size, issue_slots[27].in_uop.bits.mem_size connect slots_27.io.in_uop.bits.mem_cmd, issue_slots[27].in_uop.bits.mem_cmd connect slots_27.io.in_uop.bits.bypassable, issue_slots[27].in_uop.bits.bypassable connect slots_27.io.in_uop.bits.exc_cause, issue_slots[27].in_uop.bits.exc_cause connect slots_27.io.in_uop.bits.exception, issue_slots[27].in_uop.bits.exception connect slots_27.io.in_uop.bits.stale_pdst, issue_slots[27].in_uop.bits.stale_pdst connect slots_27.io.in_uop.bits.ppred_busy, issue_slots[27].in_uop.bits.ppred_busy connect slots_27.io.in_uop.bits.prs3_busy, issue_slots[27].in_uop.bits.prs3_busy connect slots_27.io.in_uop.bits.prs2_busy, issue_slots[27].in_uop.bits.prs2_busy connect slots_27.io.in_uop.bits.prs1_busy, issue_slots[27].in_uop.bits.prs1_busy connect slots_27.io.in_uop.bits.ppred, issue_slots[27].in_uop.bits.ppred connect slots_27.io.in_uop.bits.prs3, issue_slots[27].in_uop.bits.prs3 connect slots_27.io.in_uop.bits.prs2, issue_slots[27].in_uop.bits.prs2 connect slots_27.io.in_uop.bits.prs1, issue_slots[27].in_uop.bits.prs1 connect slots_27.io.in_uop.bits.pdst, issue_slots[27].in_uop.bits.pdst connect slots_27.io.in_uop.bits.rxq_idx, issue_slots[27].in_uop.bits.rxq_idx connect slots_27.io.in_uop.bits.stq_idx, issue_slots[27].in_uop.bits.stq_idx connect slots_27.io.in_uop.bits.ldq_idx, issue_slots[27].in_uop.bits.ldq_idx connect slots_27.io.in_uop.bits.rob_idx, issue_slots[27].in_uop.bits.rob_idx connect slots_27.io.in_uop.bits.csr_addr, issue_slots[27].in_uop.bits.csr_addr connect slots_27.io.in_uop.bits.imm_packed, issue_slots[27].in_uop.bits.imm_packed connect slots_27.io.in_uop.bits.taken, issue_slots[27].in_uop.bits.taken connect slots_27.io.in_uop.bits.pc_lob, issue_slots[27].in_uop.bits.pc_lob connect slots_27.io.in_uop.bits.edge_inst, issue_slots[27].in_uop.bits.edge_inst connect slots_27.io.in_uop.bits.ftq_idx, issue_slots[27].in_uop.bits.ftq_idx connect slots_27.io.in_uop.bits.br_tag, issue_slots[27].in_uop.bits.br_tag connect slots_27.io.in_uop.bits.br_mask, issue_slots[27].in_uop.bits.br_mask connect slots_27.io.in_uop.bits.is_sfb, issue_slots[27].in_uop.bits.is_sfb connect slots_27.io.in_uop.bits.is_jal, issue_slots[27].in_uop.bits.is_jal connect slots_27.io.in_uop.bits.is_jalr, issue_slots[27].in_uop.bits.is_jalr connect slots_27.io.in_uop.bits.is_br, issue_slots[27].in_uop.bits.is_br connect slots_27.io.in_uop.bits.iw_p2_poisoned, issue_slots[27].in_uop.bits.iw_p2_poisoned connect slots_27.io.in_uop.bits.iw_p1_poisoned, issue_slots[27].in_uop.bits.iw_p1_poisoned connect slots_27.io.in_uop.bits.iw_state, issue_slots[27].in_uop.bits.iw_state connect slots_27.io.in_uop.bits.ctrl.is_std, issue_slots[27].in_uop.bits.ctrl.is_std connect slots_27.io.in_uop.bits.ctrl.is_sta, issue_slots[27].in_uop.bits.ctrl.is_sta connect slots_27.io.in_uop.bits.ctrl.is_load, issue_slots[27].in_uop.bits.ctrl.is_load connect slots_27.io.in_uop.bits.ctrl.csr_cmd, issue_slots[27].in_uop.bits.ctrl.csr_cmd connect slots_27.io.in_uop.bits.ctrl.fcn_dw, issue_slots[27].in_uop.bits.ctrl.fcn_dw connect slots_27.io.in_uop.bits.ctrl.op_fcn, issue_slots[27].in_uop.bits.ctrl.op_fcn connect slots_27.io.in_uop.bits.ctrl.imm_sel, issue_slots[27].in_uop.bits.ctrl.imm_sel connect slots_27.io.in_uop.bits.ctrl.op2_sel, issue_slots[27].in_uop.bits.ctrl.op2_sel connect slots_27.io.in_uop.bits.ctrl.op1_sel, issue_slots[27].in_uop.bits.ctrl.op1_sel connect slots_27.io.in_uop.bits.ctrl.br_type, issue_slots[27].in_uop.bits.ctrl.br_type connect slots_27.io.in_uop.bits.fu_code, issue_slots[27].in_uop.bits.fu_code connect slots_27.io.in_uop.bits.iq_type, issue_slots[27].in_uop.bits.iq_type connect slots_27.io.in_uop.bits.debug_pc, issue_slots[27].in_uop.bits.debug_pc connect slots_27.io.in_uop.bits.is_rvc, issue_slots[27].in_uop.bits.is_rvc connect slots_27.io.in_uop.bits.debug_inst, issue_slots[27].in_uop.bits.debug_inst connect slots_27.io.in_uop.bits.inst, issue_slots[27].in_uop.bits.inst connect slots_27.io.in_uop.bits.uopc, issue_slots[27].in_uop.bits.uopc connect slots_27.io.in_uop.valid, issue_slots[27].in_uop.valid connect slots_27.io.spec_ld_wakeup[0].bits, issue_slots[27].spec_ld_wakeup[0].bits connect slots_27.io.spec_ld_wakeup[0].valid, issue_slots[27].spec_ld_wakeup[0].valid connect slots_27.io.pred_wakeup_port.bits, issue_slots[27].pred_wakeup_port.bits connect slots_27.io.pred_wakeup_port.valid, issue_slots[27].pred_wakeup_port.valid connect slots_27.io.wakeup_ports[0].bits.poisoned, issue_slots[27].wakeup_ports[0].bits.poisoned connect slots_27.io.wakeup_ports[0].bits.pdst, issue_slots[27].wakeup_ports[0].bits.pdst connect slots_27.io.wakeup_ports[0].valid, issue_slots[27].wakeup_ports[0].valid connect slots_27.io.wakeup_ports[1].bits.poisoned, issue_slots[27].wakeup_ports[1].bits.poisoned connect slots_27.io.wakeup_ports[1].bits.pdst, issue_slots[27].wakeup_ports[1].bits.pdst connect slots_27.io.wakeup_ports[1].valid, issue_slots[27].wakeup_ports[1].valid connect slots_27.io.wakeup_ports[2].bits.poisoned, issue_slots[27].wakeup_ports[2].bits.poisoned connect slots_27.io.wakeup_ports[2].bits.pdst, issue_slots[27].wakeup_ports[2].bits.pdst connect slots_27.io.wakeup_ports[2].valid, issue_slots[27].wakeup_ports[2].valid connect slots_27.io.wakeup_ports[3].bits.poisoned, issue_slots[27].wakeup_ports[3].bits.poisoned connect slots_27.io.wakeup_ports[3].bits.pdst, issue_slots[27].wakeup_ports[3].bits.pdst connect slots_27.io.wakeup_ports[3].valid, issue_slots[27].wakeup_ports[3].valid connect slots_27.io.wakeup_ports[4].bits.poisoned, issue_slots[27].wakeup_ports[4].bits.poisoned connect slots_27.io.wakeup_ports[4].bits.pdst, issue_slots[27].wakeup_ports[4].bits.pdst connect slots_27.io.wakeup_ports[4].valid, issue_slots[27].wakeup_ports[4].valid connect slots_27.io.wakeup_ports[5].bits.poisoned, issue_slots[27].wakeup_ports[5].bits.poisoned connect slots_27.io.wakeup_ports[5].bits.pdst, issue_slots[27].wakeup_ports[5].bits.pdst connect slots_27.io.wakeup_ports[5].valid, issue_slots[27].wakeup_ports[5].valid connect slots_27.io.wakeup_ports[6].bits.poisoned, issue_slots[27].wakeup_ports[6].bits.poisoned connect slots_27.io.wakeup_ports[6].bits.pdst, issue_slots[27].wakeup_ports[6].bits.pdst connect slots_27.io.wakeup_ports[6].valid, issue_slots[27].wakeup_ports[6].valid connect slots_27.io.ldspec_miss, issue_slots[27].ldspec_miss connect slots_27.io.clear, issue_slots[27].clear connect slots_27.io.kill, issue_slots[27].kill connect slots_27.io.brupdate.b2.target_offset, issue_slots[27].brupdate.b2.target_offset connect slots_27.io.brupdate.b2.jalr_target, issue_slots[27].brupdate.b2.jalr_target connect slots_27.io.brupdate.b2.pc_sel, issue_slots[27].brupdate.b2.pc_sel connect slots_27.io.brupdate.b2.cfi_type, issue_slots[27].brupdate.b2.cfi_type connect slots_27.io.brupdate.b2.taken, issue_slots[27].brupdate.b2.taken connect slots_27.io.brupdate.b2.mispredict, issue_slots[27].brupdate.b2.mispredict connect slots_27.io.brupdate.b2.valid, issue_slots[27].brupdate.b2.valid connect slots_27.io.brupdate.b2.uop.debug_tsrc, issue_slots[27].brupdate.b2.uop.debug_tsrc connect slots_27.io.brupdate.b2.uop.debug_fsrc, issue_slots[27].brupdate.b2.uop.debug_fsrc connect slots_27.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[27].brupdate.b2.uop.bp_xcpt_if connect slots_27.io.brupdate.b2.uop.bp_debug_if, issue_slots[27].brupdate.b2.uop.bp_debug_if connect slots_27.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[27].brupdate.b2.uop.xcpt_ma_if connect slots_27.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[27].brupdate.b2.uop.xcpt_ae_if connect slots_27.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[27].brupdate.b2.uop.xcpt_pf_if connect slots_27.io.brupdate.b2.uop.fp_single, issue_slots[27].brupdate.b2.uop.fp_single connect slots_27.io.brupdate.b2.uop.fp_val, issue_slots[27].brupdate.b2.uop.fp_val connect slots_27.io.brupdate.b2.uop.frs3_en, issue_slots[27].brupdate.b2.uop.frs3_en connect slots_27.io.brupdate.b2.uop.lrs2_rtype, issue_slots[27].brupdate.b2.uop.lrs2_rtype connect slots_27.io.brupdate.b2.uop.lrs1_rtype, issue_slots[27].brupdate.b2.uop.lrs1_rtype connect slots_27.io.brupdate.b2.uop.dst_rtype, issue_slots[27].brupdate.b2.uop.dst_rtype connect slots_27.io.brupdate.b2.uop.ldst_val, issue_slots[27].brupdate.b2.uop.ldst_val connect slots_27.io.brupdate.b2.uop.lrs3, issue_slots[27].brupdate.b2.uop.lrs3 connect slots_27.io.brupdate.b2.uop.lrs2, issue_slots[27].brupdate.b2.uop.lrs2 connect slots_27.io.brupdate.b2.uop.lrs1, issue_slots[27].brupdate.b2.uop.lrs1 connect slots_27.io.brupdate.b2.uop.ldst, issue_slots[27].brupdate.b2.uop.ldst connect slots_27.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[27].brupdate.b2.uop.ldst_is_rs1 connect slots_27.io.brupdate.b2.uop.flush_on_commit, issue_slots[27].brupdate.b2.uop.flush_on_commit connect slots_27.io.brupdate.b2.uop.is_unique, issue_slots[27].brupdate.b2.uop.is_unique connect slots_27.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[27].brupdate.b2.uop.is_sys_pc2epc connect slots_27.io.brupdate.b2.uop.uses_stq, issue_slots[27].brupdate.b2.uop.uses_stq connect slots_27.io.brupdate.b2.uop.uses_ldq, issue_slots[27].brupdate.b2.uop.uses_ldq connect slots_27.io.brupdate.b2.uop.is_amo, issue_slots[27].brupdate.b2.uop.is_amo connect slots_27.io.brupdate.b2.uop.is_fencei, issue_slots[27].brupdate.b2.uop.is_fencei connect slots_27.io.brupdate.b2.uop.is_fence, issue_slots[27].brupdate.b2.uop.is_fence connect slots_27.io.brupdate.b2.uop.mem_signed, issue_slots[27].brupdate.b2.uop.mem_signed connect slots_27.io.brupdate.b2.uop.mem_size, issue_slots[27].brupdate.b2.uop.mem_size connect slots_27.io.brupdate.b2.uop.mem_cmd, issue_slots[27].brupdate.b2.uop.mem_cmd connect slots_27.io.brupdate.b2.uop.bypassable, issue_slots[27].brupdate.b2.uop.bypassable connect slots_27.io.brupdate.b2.uop.exc_cause, issue_slots[27].brupdate.b2.uop.exc_cause connect slots_27.io.brupdate.b2.uop.exception, issue_slots[27].brupdate.b2.uop.exception connect slots_27.io.brupdate.b2.uop.stale_pdst, issue_slots[27].brupdate.b2.uop.stale_pdst connect slots_27.io.brupdate.b2.uop.ppred_busy, issue_slots[27].brupdate.b2.uop.ppred_busy connect slots_27.io.brupdate.b2.uop.prs3_busy, issue_slots[27].brupdate.b2.uop.prs3_busy connect slots_27.io.brupdate.b2.uop.prs2_busy, issue_slots[27].brupdate.b2.uop.prs2_busy connect slots_27.io.brupdate.b2.uop.prs1_busy, issue_slots[27].brupdate.b2.uop.prs1_busy connect slots_27.io.brupdate.b2.uop.ppred, issue_slots[27].brupdate.b2.uop.ppred connect slots_27.io.brupdate.b2.uop.prs3, issue_slots[27].brupdate.b2.uop.prs3 connect slots_27.io.brupdate.b2.uop.prs2, issue_slots[27].brupdate.b2.uop.prs2 connect slots_27.io.brupdate.b2.uop.prs1, issue_slots[27].brupdate.b2.uop.prs1 connect slots_27.io.brupdate.b2.uop.pdst, issue_slots[27].brupdate.b2.uop.pdst connect slots_27.io.brupdate.b2.uop.rxq_idx, issue_slots[27].brupdate.b2.uop.rxq_idx connect slots_27.io.brupdate.b2.uop.stq_idx, issue_slots[27].brupdate.b2.uop.stq_idx connect slots_27.io.brupdate.b2.uop.ldq_idx, issue_slots[27].brupdate.b2.uop.ldq_idx connect slots_27.io.brupdate.b2.uop.rob_idx, issue_slots[27].brupdate.b2.uop.rob_idx connect slots_27.io.brupdate.b2.uop.csr_addr, issue_slots[27].brupdate.b2.uop.csr_addr connect slots_27.io.brupdate.b2.uop.imm_packed, issue_slots[27].brupdate.b2.uop.imm_packed connect slots_27.io.brupdate.b2.uop.taken, issue_slots[27].brupdate.b2.uop.taken connect slots_27.io.brupdate.b2.uop.pc_lob, issue_slots[27].brupdate.b2.uop.pc_lob connect slots_27.io.brupdate.b2.uop.edge_inst, issue_slots[27].brupdate.b2.uop.edge_inst connect slots_27.io.brupdate.b2.uop.ftq_idx, issue_slots[27].brupdate.b2.uop.ftq_idx connect slots_27.io.brupdate.b2.uop.br_tag, issue_slots[27].brupdate.b2.uop.br_tag connect slots_27.io.brupdate.b2.uop.br_mask, issue_slots[27].brupdate.b2.uop.br_mask connect slots_27.io.brupdate.b2.uop.is_sfb, issue_slots[27].brupdate.b2.uop.is_sfb connect slots_27.io.brupdate.b2.uop.is_jal, issue_slots[27].brupdate.b2.uop.is_jal connect slots_27.io.brupdate.b2.uop.is_jalr, issue_slots[27].brupdate.b2.uop.is_jalr connect slots_27.io.brupdate.b2.uop.is_br, issue_slots[27].brupdate.b2.uop.is_br connect slots_27.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[27].brupdate.b2.uop.iw_p2_poisoned connect slots_27.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[27].brupdate.b2.uop.iw_p1_poisoned connect slots_27.io.brupdate.b2.uop.iw_state, issue_slots[27].brupdate.b2.uop.iw_state connect slots_27.io.brupdate.b2.uop.ctrl.is_std, issue_slots[27].brupdate.b2.uop.ctrl.is_std connect slots_27.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[27].brupdate.b2.uop.ctrl.is_sta connect slots_27.io.brupdate.b2.uop.ctrl.is_load, issue_slots[27].brupdate.b2.uop.ctrl.is_load connect slots_27.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[27].brupdate.b2.uop.ctrl.csr_cmd connect slots_27.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[27].brupdate.b2.uop.ctrl.fcn_dw connect slots_27.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[27].brupdate.b2.uop.ctrl.op_fcn connect slots_27.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[27].brupdate.b2.uop.ctrl.imm_sel connect slots_27.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[27].brupdate.b2.uop.ctrl.op2_sel connect slots_27.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[27].brupdate.b2.uop.ctrl.op1_sel connect slots_27.io.brupdate.b2.uop.ctrl.br_type, issue_slots[27].brupdate.b2.uop.ctrl.br_type connect slots_27.io.brupdate.b2.uop.fu_code, issue_slots[27].brupdate.b2.uop.fu_code connect slots_27.io.brupdate.b2.uop.iq_type, issue_slots[27].brupdate.b2.uop.iq_type connect slots_27.io.brupdate.b2.uop.debug_pc, issue_slots[27].brupdate.b2.uop.debug_pc connect slots_27.io.brupdate.b2.uop.is_rvc, issue_slots[27].brupdate.b2.uop.is_rvc connect slots_27.io.brupdate.b2.uop.debug_inst, issue_slots[27].brupdate.b2.uop.debug_inst connect slots_27.io.brupdate.b2.uop.inst, issue_slots[27].brupdate.b2.uop.inst connect slots_27.io.brupdate.b2.uop.uopc, issue_slots[27].brupdate.b2.uop.uopc connect slots_27.io.brupdate.b1.mispredict_mask, issue_slots[27].brupdate.b1.mispredict_mask connect slots_27.io.brupdate.b1.resolve_mask, issue_slots[27].brupdate.b1.resolve_mask connect slots_27.io.grant, issue_slots[27].grant connect issue_slots[27].request_hp, slots_27.io.request_hp connect issue_slots[27].request, slots_27.io.request connect issue_slots[27].will_be_valid, slots_27.io.will_be_valid connect issue_slots[27].valid, slots_27.io.valid connect issue_slots[28].debug.state, slots_28.io.debug.state connect issue_slots[28].debug.ppred, slots_28.io.debug.ppred connect issue_slots[28].debug.p3, slots_28.io.debug.p3 connect issue_slots[28].debug.p2, slots_28.io.debug.p2 connect issue_slots[28].debug.p1, slots_28.io.debug.p1 connect issue_slots[28].uop.debug_tsrc, slots_28.io.uop.debug_tsrc connect issue_slots[28].uop.debug_fsrc, slots_28.io.uop.debug_fsrc connect issue_slots[28].uop.bp_xcpt_if, slots_28.io.uop.bp_xcpt_if connect issue_slots[28].uop.bp_debug_if, slots_28.io.uop.bp_debug_if connect issue_slots[28].uop.xcpt_ma_if, slots_28.io.uop.xcpt_ma_if connect issue_slots[28].uop.xcpt_ae_if, slots_28.io.uop.xcpt_ae_if connect issue_slots[28].uop.xcpt_pf_if, slots_28.io.uop.xcpt_pf_if connect issue_slots[28].uop.fp_single, slots_28.io.uop.fp_single connect issue_slots[28].uop.fp_val, slots_28.io.uop.fp_val connect issue_slots[28].uop.frs3_en, slots_28.io.uop.frs3_en connect issue_slots[28].uop.lrs2_rtype, slots_28.io.uop.lrs2_rtype connect issue_slots[28].uop.lrs1_rtype, slots_28.io.uop.lrs1_rtype connect issue_slots[28].uop.dst_rtype, slots_28.io.uop.dst_rtype connect issue_slots[28].uop.ldst_val, slots_28.io.uop.ldst_val connect issue_slots[28].uop.lrs3, slots_28.io.uop.lrs3 connect issue_slots[28].uop.lrs2, slots_28.io.uop.lrs2 connect issue_slots[28].uop.lrs1, slots_28.io.uop.lrs1 connect issue_slots[28].uop.ldst, slots_28.io.uop.ldst connect issue_slots[28].uop.ldst_is_rs1, slots_28.io.uop.ldst_is_rs1 connect issue_slots[28].uop.flush_on_commit, slots_28.io.uop.flush_on_commit connect issue_slots[28].uop.is_unique, slots_28.io.uop.is_unique connect issue_slots[28].uop.is_sys_pc2epc, slots_28.io.uop.is_sys_pc2epc connect issue_slots[28].uop.uses_stq, slots_28.io.uop.uses_stq connect issue_slots[28].uop.uses_ldq, slots_28.io.uop.uses_ldq connect issue_slots[28].uop.is_amo, slots_28.io.uop.is_amo connect issue_slots[28].uop.is_fencei, slots_28.io.uop.is_fencei connect issue_slots[28].uop.is_fence, slots_28.io.uop.is_fence connect issue_slots[28].uop.mem_signed, slots_28.io.uop.mem_signed connect issue_slots[28].uop.mem_size, slots_28.io.uop.mem_size connect issue_slots[28].uop.mem_cmd, slots_28.io.uop.mem_cmd connect issue_slots[28].uop.bypassable, slots_28.io.uop.bypassable connect issue_slots[28].uop.exc_cause, slots_28.io.uop.exc_cause connect issue_slots[28].uop.exception, slots_28.io.uop.exception connect issue_slots[28].uop.stale_pdst, slots_28.io.uop.stale_pdst connect issue_slots[28].uop.ppred_busy, slots_28.io.uop.ppred_busy connect issue_slots[28].uop.prs3_busy, slots_28.io.uop.prs3_busy connect issue_slots[28].uop.prs2_busy, slots_28.io.uop.prs2_busy connect issue_slots[28].uop.prs1_busy, slots_28.io.uop.prs1_busy connect issue_slots[28].uop.ppred, slots_28.io.uop.ppred connect issue_slots[28].uop.prs3, slots_28.io.uop.prs3 connect issue_slots[28].uop.prs2, slots_28.io.uop.prs2 connect issue_slots[28].uop.prs1, slots_28.io.uop.prs1 connect issue_slots[28].uop.pdst, slots_28.io.uop.pdst connect issue_slots[28].uop.rxq_idx, slots_28.io.uop.rxq_idx connect issue_slots[28].uop.stq_idx, slots_28.io.uop.stq_idx connect issue_slots[28].uop.ldq_idx, slots_28.io.uop.ldq_idx connect issue_slots[28].uop.rob_idx, slots_28.io.uop.rob_idx connect issue_slots[28].uop.csr_addr, slots_28.io.uop.csr_addr connect issue_slots[28].uop.imm_packed, slots_28.io.uop.imm_packed connect issue_slots[28].uop.taken, slots_28.io.uop.taken connect issue_slots[28].uop.pc_lob, slots_28.io.uop.pc_lob connect issue_slots[28].uop.edge_inst, slots_28.io.uop.edge_inst connect issue_slots[28].uop.ftq_idx, slots_28.io.uop.ftq_idx connect issue_slots[28].uop.br_tag, slots_28.io.uop.br_tag connect issue_slots[28].uop.br_mask, slots_28.io.uop.br_mask connect issue_slots[28].uop.is_sfb, slots_28.io.uop.is_sfb connect issue_slots[28].uop.is_jal, slots_28.io.uop.is_jal connect issue_slots[28].uop.is_jalr, slots_28.io.uop.is_jalr connect issue_slots[28].uop.is_br, slots_28.io.uop.is_br connect issue_slots[28].uop.iw_p2_poisoned, slots_28.io.uop.iw_p2_poisoned connect issue_slots[28].uop.iw_p1_poisoned, slots_28.io.uop.iw_p1_poisoned connect issue_slots[28].uop.iw_state, slots_28.io.uop.iw_state connect issue_slots[28].uop.ctrl.is_std, slots_28.io.uop.ctrl.is_std connect issue_slots[28].uop.ctrl.is_sta, slots_28.io.uop.ctrl.is_sta connect issue_slots[28].uop.ctrl.is_load, slots_28.io.uop.ctrl.is_load connect issue_slots[28].uop.ctrl.csr_cmd, slots_28.io.uop.ctrl.csr_cmd connect issue_slots[28].uop.ctrl.fcn_dw, slots_28.io.uop.ctrl.fcn_dw connect issue_slots[28].uop.ctrl.op_fcn, slots_28.io.uop.ctrl.op_fcn connect issue_slots[28].uop.ctrl.imm_sel, slots_28.io.uop.ctrl.imm_sel connect issue_slots[28].uop.ctrl.op2_sel, slots_28.io.uop.ctrl.op2_sel connect issue_slots[28].uop.ctrl.op1_sel, slots_28.io.uop.ctrl.op1_sel connect issue_slots[28].uop.ctrl.br_type, slots_28.io.uop.ctrl.br_type connect issue_slots[28].uop.fu_code, slots_28.io.uop.fu_code connect issue_slots[28].uop.iq_type, slots_28.io.uop.iq_type connect issue_slots[28].uop.debug_pc, slots_28.io.uop.debug_pc connect issue_slots[28].uop.is_rvc, slots_28.io.uop.is_rvc connect issue_slots[28].uop.debug_inst, slots_28.io.uop.debug_inst connect issue_slots[28].uop.inst, slots_28.io.uop.inst connect issue_slots[28].uop.uopc, slots_28.io.uop.uopc connect issue_slots[28].out_uop.debug_tsrc, slots_28.io.out_uop.debug_tsrc connect issue_slots[28].out_uop.debug_fsrc, slots_28.io.out_uop.debug_fsrc connect issue_slots[28].out_uop.bp_xcpt_if, slots_28.io.out_uop.bp_xcpt_if connect issue_slots[28].out_uop.bp_debug_if, slots_28.io.out_uop.bp_debug_if connect issue_slots[28].out_uop.xcpt_ma_if, slots_28.io.out_uop.xcpt_ma_if connect issue_slots[28].out_uop.xcpt_ae_if, slots_28.io.out_uop.xcpt_ae_if connect issue_slots[28].out_uop.xcpt_pf_if, slots_28.io.out_uop.xcpt_pf_if connect issue_slots[28].out_uop.fp_single, slots_28.io.out_uop.fp_single connect issue_slots[28].out_uop.fp_val, slots_28.io.out_uop.fp_val connect issue_slots[28].out_uop.frs3_en, slots_28.io.out_uop.frs3_en connect issue_slots[28].out_uop.lrs2_rtype, slots_28.io.out_uop.lrs2_rtype connect issue_slots[28].out_uop.lrs1_rtype, slots_28.io.out_uop.lrs1_rtype connect issue_slots[28].out_uop.dst_rtype, slots_28.io.out_uop.dst_rtype connect issue_slots[28].out_uop.ldst_val, slots_28.io.out_uop.ldst_val connect issue_slots[28].out_uop.lrs3, slots_28.io.out_uop.lrs3 connect issue_slots[28].out_uop.lrs2, slots_28.io.out_uop.lrs2 connect issue_slots[28].out_uop.lrs1, slots_28.io.out_uop.lrs1 connect issue_slots[28].out_uop.ldst, slots_28.io.out_uop.ldst connect issue_slots[28].out_uop.ldst_is_rs1, slots_28.io.out_uop.ldst_is_rs1 connect issue_slots[28].out_uop.flush_on_commit, slots_28.io.out_uop.flush_on_commit connect issue_slots[28].out_uop.is_unique, slots_28.io.out_uop.is_unique connect issue_slots[28].out_uop.is_sys_pc2epc, slots_28.io.out_uop.is_sys_pc2epc connect issue_slots[28].out_uop.uses_stq, slots_28.io.out_uop.uses_stq connect issue_slots[28].out_uop.uses_ldq, slots_28.io.out_uop.uses_ldq connect issue_slots[28].out_uop.is_amo, slots_28.io.out_uop.is_amo connect issue_slots[28].out_uop.is_fencei, slots_28.io.out_uop.is_fencei connect issue_slots[28].out_uop.is_fence, slots_28.io.out_uop.is_fence connect issue_slots[28].out_uop.mem_signed, slots_28.io.out_uop.mem_signed connect issue_slots[28].out_uop.mem_size, slots_28.io.out_uop.mem_size connect issue_slots[28].out_uop.mem_cmd, slots_28.io.out_uop.mem_cmd connect issue_slots[28].out_uop.bypassable, slots_28.io.out_uop.bypassable connect issue_slots[28].out_uop.exc_cause, slots_28.io.out_uop.exc_cause connect issue_slots[28].out_uop.exception, slots_28.io.out_uop.exception connect issue_slots[28].out_uop.stale_pdst, slots_28.io.out_uop.stale_pdst connect issue_slots[28].out_uop.ppred_busy, slots_28.io.out_uop.ppred_busy connect issue_slots[28].out_uop.prs3_busy, slots_28.io.out_uop.prs3_busy connect issue_slots[28].out_uop.prs2_busy, slots_28.io.out_uop.prs2_busy connect issue_slots[28].out_uop.prs1_busy, slots_28.io.out_uop.prs1_busy connect issue_slots[28].out_uop.ppred, slots_28.io.out_uop.ppred connect issue_slots[28].out_uop.prs3, slots_28.io.out_uop.prs3 connect issue_slots[28].out_uop.prs2, slots_28.io.out_uop.prs2 connect issue_slots[28].out_uop.prs1, slots_28.io.out_uop.prs1 connect issue_slots[28].out_uop.pdst, slots_28.io.out_uop.pdst connect issue_slots[28].out_uop.rxq_idx, slots_28.io.out_uop.rxq_idx connect issue_slots[28].out_uop.stq_idx, slots_28.io.out_uop.stq_idx connect issue_slots[28].out_uop.ldq_idx, slots_28.io.out_uop.ldq_idx connect issue_slots[28].out_uop.rob_idx, slots_28.io.out_uop.rob_idx connect issue_slots[28].out_uop.csr_addr, slots_28.io.out_uop.csr_addr connect issue_slots[28].out_uop.imm_packed, slots_28.io.out_uop.imm_packed connect issue_slots[28].out_uop.taken, slots_28.io.out_uop.taken connect issue_slots[28].out_uop.pc_lob, slots_28.io.out_uop.pc_lob connect issue_slots[28].out_uop.edge_inst, slots_28.io.out_uop.edge_inst connect issue_slots[28].out_uop.ftq_idx, slots_28.io.out_uop.ftq_idx connect issue_slots[28].out_uop.br_tag, slots_28.io.out_uop.br_tag connect issue_slots[28].out_uop.br_mask, slots_28.io.out_uop.br_mask connect issue_slots[28].out_uop.is_sfb, slots_28.io.out_uop.is_sfb connect issue_slots[28].out_uop.is_jal, slots_28.io.out_uop.is_jal connect issue_slots[28].out_uop.is_jalr, slots_28.io.out_uop.is_jalr connect issue_slots[28].out_uop.is_br, slots_28.io.out_uop.is_br connect issue_slots[28].out_uop.iw_p2_poisoned, slots_28.io.out_uop.iw_p2_poisoned connect issue_slots[28].out_uop.iw_p1_poisoned, slots_28.io.out_uop.iw_p1_poisoned connect issue_slots[28].out_uop.iw_state, slots_28.io.out_uop.iw_state connect issue_slots[28].out_uop.ctrl.is_std, slots_28.io.out_uop.ctrl.is_std connect issue_slots[28].out_uop.ctrl.is_sta, slots_28.io.out_uop.ctrl.is_sta connect issue_slots[28].out_uop.ctrl.is_load, slots_28.io.out_uop.ctrl.is_load connect issue_slots[28].out_uop.ctrl.csr_cmd, slots_28.io.out_uop.ctrl.csr_cmd connect issue_slots[28].out_uop.ctrl.fcn_dw, slots_28.io.out_uop.ctrl.fcn_dw connect issue_slots[28].out_uop.ctrl.op_fcn, slots_28.io.out_uop.ctrl.op_fcn connect issue_slots[28].out_uop.ctrl.imm_sel, slots_28.io.out_uop.ctrl.imm_sel connect issue_slots[28].out_uop.ctrl.op2_sel, slots_28.io.out_uop.ctrl.op2_sel connect issue_slots[28].out_uop.ctrl.op1_sel, slots_28.io.out_uop.ctrl.op1_sel connect issue_slots[28].out_uop.ctrl.br_type, slots_28.io.out_uop.ctrl.br_type connect issue_slots[28].out_uop.fu_code, slots_28.io.out_uop.fu_code connect issue_slots[28].out_uop.iq_type, slots_28.io.out_uop.iq_type connect issue_slots[28].out_uop.debug_pc, slots_28.io.out_uop.debug_pc connect issue_slots[28].out_uop.is_rvc, slots_28.io.out_uop.is_rvc connect issue_slots[28].out_uop.debug_inst, slots_28.io.out_uop.debug_inst connect issue_slots[28].out_uop.inst, slots_28.io.out_uop.inst connect issue_slots[28].out_uop.uopc, slots_28.io.out_uop.uopc connect slots_28.io.in_uop.bits.debug_tsrc, issue_slots[28].in_uop.bits.debug_tsrc connect slots_28.io.in_uop.bits.debug_fsrc, issue_slots[28].in_uop.bits.debug_fsrc connect slots_28.io.in_uop.bits.bp_xcpt_if, issue_slots[28].in_uop.bits.bp_xcpt_if connect slots_28.io.in_uop.bits.bp_debug_if, issue_slots[28].in_uop.bits.bp_debug_if connect slots_28.io.in_uop.bits.xcpt_ma_if, issue_slots[28].in_uop.bits.xcpt_ma_if connect slots_28.io.in_uop.bits.xcpt_ae_if, issue_slots[28].in_uop.bits.xcpt_ae_if connect slots_28.io.in_uop.bits.xcpt_pf_if, issue_slots[28].in_uop.bits.xcpt_pf_if connect slots_28.io.in_uop.bits.fp_single, issue_slots[28].in_uop.bits.fp_single connect slots_28.io.in_uop.bits.fp_val, issue_slots[28].in_uop.bits.fp_val connect slots_28.io.in_uop.bits.frs3_en, issue_slots[28].in_uop.bits.frs3_en connect slots_28.io.in_uop.bits.lrs2_rtype, issue_slots[28].in_uop.bits.lrs2_rtype connect slots_28.io.in_uop.bits.lrs1_rtype, issue_slots[28].in_uop.bits.lrs1_rtype connect slots_28.io.in_uop.bits.dst_rtype, issue_slots[28].in_uop.bits.dst_rtype connect slots_28.io.in_uop.bits.ldst_val, issue_slots[28].in_uop.bits.ldst_val connect slots_28.io.in_uop.bits.lrs3, issue_slots[28].in_uop.bits.lrs3 connect slots_28.io.in_uop.bits.lrs2, issue_slots[28].in_uop.bits.lrs2 connect slots_28.io.in_uop.bits.lrs1, issue_slots[28].in_uop.bits.lrs1 connect slots_28.io.in_uop.bits.ldst, issue_slots[28].in_uop.bits.ldst connect slots_28.io.in_uop.bits.ldst_is_rs1, issue_slots[28].in_uop.bits.ldst_is_rs1 connect slots_28.io.in_uop.bits.flush_on_commit, issue_slots[28].in_uop.bits.flush_on_commit connect slots_28.io.in_uop.bits.is_unique, issue_slots[28].in_uop.bits.is_unique connect slots_28.io.in_uop.bits.is_sys_pc2epc, issue_slots[28].in_uop.bits.is_sys_pc2epc connect slots_28.io.in_uop.bits.uses_stq, issue_slots[28].in_uop.bits.uses_stq connect slots_28.io.in_uop.bits.uses_ldq, issue_slots[28].in_uop.bits.uses_ldq connect slots_28.io.in_uop.bits.is_amo, issue_slots[28].in_uop.bits.is_amo connect slots_28.io.in_uop.bits.is_fencei, issue_slots[28].in_uop.bits.is_fencei connect slots_28.io.in_uop.bits.is_fence, issue_slots[28].in_uop.bits.is_fence connect slots_28.io.in_uop.bits.mem_signed, issue_slots[28].in_uop.bits.mem_signed connect slots_28.io.in_uop.bits.mem_size, issue_slots[28].in_uop.bits.mem_size connect slots_28.io.in_uop.bits.mem_cmd, issue_slots[28].in_uop.bits.mem_cmd connect slots_28.io.in_uop.bits.bypassable, issue_slots[28].in_uop.bits.bypassable connect slots_28.io.in_uop.bits.exc_cause, issue_slots[28].in_uop.bits.exc_cause connect slots_28.io.in_uop.bits.exception, issue_slots[28].in_uop.bits.exception connect slots_28.io.in_uop.bits.stale_pdst, issue_slots[28].in_uop.bits.stale_pdst connect slots_28.io.in_uop.bits.ppred_busy, issue_slots[28].in_uop.bits.ppred_busy connect slots_28.io.in_uop.bits.prs3_busy, issue_slots[28].in_uop.bits.prs3_busy connect slots_28.io.in_uop.bits.prs2_busy, issue_slots[28].in_uop.bits.prs2_busy connect slots_28.io.in_uop.bits.prs1_busy, issue_slots[28].in_uop.bits.prs1_busy connect slots_28.io.in_uop.bits.ppred, issue_slots[28].in_uop.bits.ppred connect slots_28.io.in_uop.bits.prs3, issue_slots[28].in_uop.bits.prs3 connect slots_28.io.in_uop.bits.prs2, issue_slots[28].in_uop.bits.prs2 connect slots_28.io.in_uop.bits.prs1, issue_slots[28].in_uop.bits.prs1 connect slots_28.io.in_uop.bits.pdst, issue_slots[28].in_uop.bits.pdst connect slots_28.io.in_uop.bits.rxq_idx, issue_slots[28].in_uop.bits.rxq_idx connect slots_28.io.in_uop.bits.stq_idx, issue_slots[28].in_uop.bits.stq_idx connect slots_28.io.in_uop.bits.ldq_idx, issue_slots[28].in_uop.bits.ldq_idx connect slots_28.io.in_uop.bits.rob_idx, issue_slots[28].in_uop.bits.rob_idx connect slots_28.io.in_uop.bits.csr_addr, issue_slots[28].in_uop.bits.csr_addr connect slots_28.io.in_uop.bits.imm_packed, issue_slots[28].in_uop.bits.imm_packed connect slots_28.io.in_uop.bits.taken, issue_slots[28].in_uop.bits.taken connect slots_28.io.in_uop.bits.pc_lob, issue_slots[28].in_uop.bits.pc_lob connect slots_28.io.in_uop.bits.edge_inst, issue_slots[28].in_uop.bits.edge_inst connect slots_28.io.in_uop.bits.ftq_idx, issue_slots[28].in_uop.bits.ftq_idx connect slots_28.io.in_uop.bits.br_tag, issue_slots[28].in_uop.bits.br_tag connect slots_28.io.in_uop.bits.br_mask, issue_slots[28].in_uop.bits.br_mask connect slots_28.io.in_uop.bits.is_sfb, issue_slots[28].in_uop.bits.is_sfb connect slots_28.io.in_uop.bits.is_jal, issue_slots[28].in_uop.bits.is_jal connect slots_28.io.in_uop.bits.is_jalr, issue_slots[28].in_uop.bits.is_jalr connect slots_28.io.in_uop.bits.is_br, issue_slots[28].in_uop.bits.is_br connect slots_28.io.in_uop.bits.iw_p2_poisoned, issue_slots[28].in_uop.bits.iw_p2_poisoned connect slots_28.io.in_uop.bits.iw_p1_poisoned, issue_slots[28].in_uop.bits.iw_p1_poisoned connect slots_28.io.in_uop.bits.iw_state, issue_slots[28].in_uop.bits.iw_state connect slots_28.io.in_uop.bits.ctrl.is_std, issue_slots[28].in_uop.bits.ctrl.is_std connect slots_28.io.in_uop.bits.ctrl.is_sta, issue_slots[28].in_uop.bits.ctrl.is_sta connect slots_28.io.in_uop.bits.ctrl.is_load, issue_slots[28].in_uop.bits.ctrl.is_load connect slots_28.io.in_uop.bits.ctrl.csr_cmd, issue_slots[28].in_uop.bits.ctrl.csr_cmd connect slots_28.io.in_uop.bits.ctrl.fcn_dw, issue_slots[28].in_uop.bits.ctrl.fcn_dw connect slots_28.io.in_uop.bits.ctrl.op_fcn, issue_slots[28].in_uop.bits.ctrl.op_fcn connect slots_28.io.in_uop.bits.ctrl.imm_sel, issue_slots[28].in_uop.bits.ctrl.imm_sel connect slots_28.io.in_uop.bits.ctrl.op2_sel, issue_slots[28].in_uop.bits.ctrl.op2_sel connect slots_28.io.in_uop.bits.ctrl.op1_sel, issue_slots[28].in_uop.bits.ctrl.op1_sel connect slots_28.io.in_uop.bits.ctrl.br_type, issue_slots[28].in_uop.bits.ctrl.br_type connect slots_28.io.in_uop.bits.fu_code, issue_slots[28].in_uop.bits.fu_code connect slots_28.io.in_uop.bits.iq_type, issue_slots[28].in_uop.bits.iq_type connect slots_28.io.in_uop.bits.debug_pc, issue_slots[28].in_uop.bits.debug_pc connect slots_28.io.in_uop.bits.is_rvc, issue_slots[28].in_uop.bits.is_rvc connect slots_28.io.in_uop.bits.debug_inst, issue_slots[28].in_uop.bits.debug_inst connect slots_28.io.in_uop.bits.inst, issue_slots[28].in_uop.bits.inst connect slots_28.io.in_uop.bits.uopc, issue_slots[28].in_uop.bits.uopc connect slots_28.io.in_uop.valid, issue_slots[28].in_uop.valid connect slots_28.io.spec_ld_wakeup[0].bits, issue_slots[28].spec_ld_wakeup[0].bits connect slots_28.io.spec_ld_wakeup[0].valid, issue_slots[28].spec_ld_wakeup[0].valid connect slots_28.io.pred_wakeup_port.bits, issue_slots[28].pred_wakeup_port.bits connect slots_28.io.pred_wakeup_port.valid, issue_slots[28].pred_wakeup_port.valid connect slots_28.io.wakeup_ports[0].bits.poisoned, issue_slots[28].wakeup_ports[0].bits.poisoned connect slots_28.io.wakeup_ports[0].bits.pdst, issue_slots[28].wakeup_ports[0].bits.pdst connect slots_28.io.wakeup_ports[0].valid, issue_slots[28].wakeup_ports[0].valid connect slots_28.io.wakeup_ports[1].bits.poisoned, issue_slots[28].wakeup_ports[1].bits.poisoned connect slots_28.io.wakeup_ports[1].bits.pdst, issue_slots[28].wakeup_ports[1].bits.pdst connect slots_28.io.wakeup_ports[1].valid, issue_slots[28].wakeup_ports[1].valid connect slots_28.io.wakeup_ports[2].bits.poisoned, issue_slots[28].wakeup_ports[2].bits.poisoned connect slots_28.io.wakeup_ports[2].bits.pdst, issue_slots[28].wakeup_ports[2].bits.pdst connect slots_28.io.wakeup_ports[2].valid, issue_slots[28].wakeup_ports[2].valid connect slots_28.io.wakeup_ports[3].bits.poisoned, issue_slots[28].wakeup_ports[3].bits.poisoned connect slots_28.io.wakeup_ports[3].bits.pdst, issue_slots[28].wakeup_ports[3].bits.pdst connect slots_28.io.wakeup_ports[3].valid, issue_slots[28].wakeup_ports[3].valid connect slots_28.io.wakeup_ports[4].bits.poisoned, issue_slots[28].wakeup_ports[4].bits.poisoned connect slots_28.io.wakeup_ports[4].bits.pdst, issue_slots[28].wakeup_ports[4].bits.pdst connect slots_28.io.wakeup_ports[4].valid, issue_slots[28].wakeup_ports[4].valid connect slots_28.io.wakeup_ports[5].bits.poisoned, issue_slots[28].wakeup_ports[5].bits.poisoned connect slots_28.io.wakeup_ports[5].bits.pdst, issue_slots[28].wakeup_ports[5].bits.pdst connect slots_28.io.wakeup_ports[5].valid, issue_slots[28].wakeup_ports[5].valid connect slots_28.io.wakeup_ports[6].bits.poisoned, issue_slots[28].wakeup_ports[6].bits.poisoned connect slots_28.io.wakeup_ports[6].bits.pdst, issue_slots[28].wakeup_ports[6].bits.pdst connect slots_28.io.wakeup_ports[6].valid, issue_slots[28].wakeup_ports[6].valid connect slots_28.io.ldspec_miss, issue_slots[28].ldspec_miss connect slots_28.io.clear, issue_slots[28].clear connect slots_28.io.kill, issue_slots[28].kill connect slots_28.io.brupdate.b2.target_offset, issue_slots[28].brupdate.b2.target_offset connect slots_28.io.brupdate.b2.jalr_target, issue_slots[28].brupdate.b2.jalr_target connect slots_28.io.brupdate.b2.pc_sel, issue_slots[28].brupdate.b2.pc_sel connect slots_28.io.brupdate.b2.cfi_type, issue_slots[28].brupdate.b2.cfi_type connect slots_28.io.brupdate.b2.taken, issue_slots[28].brupdate.b2.taken connect slots_28.io.brupdate.b2.mispredict, issue_slots[28].brupdate.b2.mispredict connect slots_28.io.brupdate.b2.valid, issue_slots[28].brupdate.b2.valid connect slots_28.io.brupdate.b2.uop.debug_tsrc, issue_slots[28].brupdate.b2.uop.debug_tsrc connect slots_28.io.brupdate.b2.uop.debug_fsrc, issue_slots[28].brupdate.b2.uop.debug_fsrc connect slots_28.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[28].brupdate.b2.uop.bp_xcpt_if connect slots_28.io.brupdate.b2.uop.bp_debug_if, issue_slots[28].brupdate.b2.uop.bp_debug_if connect slots_28.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[28].brupdate.b2.uop.xcpt_ma_if connect slots_28.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[28].brupdate.b2.uop.xcpt_ae_if connect slots_28.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[28].brupdate.b2.uop.xcpt_pf_if connect slots_28.io.brupdate.b2.uop.fp_single, issue_slots[28].brupdate.b2.uop.fp_single connect slots_28.io.brupdate.b2.uop.fp_val, issue_slots[28].brupdate.b2.uop.fp_val connect slots_28.io.brupdate.b2.uop.frs3_en, issue_slots[28].brupdate.b2.uop.frs3_en connect slots_28.io.brupdate.b2.uop.lrs2_rtype, issue_slots[28].brupdate.b2.uop.lrs2_rtype connect slots_28.io.brupdate.b2.uop.lrs1_rtype, issue_slots[28].brupdate.b2.uop.lrs1_rtype connect slots_28.io.brupdate.b2.uop.dst_rtype, issue_slots[28].brupdate.b2.uop.dst_rtype connect slots_28.io.brupdate.b2.uop.ldst_val, issue_slots[28].brupdate.b2.uop.ldst_val connect slots_28.io.brupdate.b2.uop.lrs3, issue_slots[28].brupdate.b2.uop.lrs3 connect slots_28.io.brupdate.b2.uop.lrs2, issue_slots[28].brupdate.b2.uop.lrs2 connect slots_28.io.brupdate.b2.uop.lrs1, issue_slots[28].brupdate.b2.uop.lrs1 connect slots_28.io.brupdate.b2.uop.ldst, issue_slots[28].brupdate.b2.uop.ldst connect slots_28.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[28].brupdate.b2.uop.ldst_is_rs1 connect slots_28.io.brupdate.b2.uop.flush_on_commit, issue_slots[28].brupdate.b2.uop.flush_on_commit connect slots_28.io.brupdate.b2.uop.is_unique, issue_slots[28].brupdate.b2.uop.is_unique connect slots_28.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[28].brupdate.b2.uop.is_sys_pc2epc connect slots_28.io.brupdate.b2.uop.uses_stq, issue_slots[28].brupdate.b2.uop.uses_stq connect slots_28.io.brupdate.b2.uop.uses_ldq, issue_slots[28].brupdate.b2.uop.uses_ldq connect slots_28.io.brupdate.b2.uop.is_amo, issue_slots[28].brupdate.b2.uop.is_amo connect slots_28.io.brupdate.b2.uop.is_fencei, issue_slots[28].brupdate.b2.uop.is_fencei connect slots_28.io.brupdate.b2.uop.is_fence, issue_slots[28].brupdate.b2.uop.is_fence connect slots_28.io.brupdate.b2.uop.mem_signed, issue_slots[28].brupdate.b2.uop.mem_signed connect slots_28.io.brupdate.b2.uop.mem_size, issue_slots[28].brupdate.b2.uop.mem_size connect slots_28.io.brupdate.b2.uop.mem_cmd, issue_slots[28].brupdate.b2.uop.mem_cmd connect slots_28.io.brupdate.b2.uop.bypassable, issue_slots[28].brupdate.b2.uop.bypassable connect slots_28.io.brupdate.b2.uop.exc_cause, issue_slots[28].brupdate.b2.uop.exc_cause connect slots_28.io.brupdate.b2.uop.exception, issue_slots[28].brupdate.b2.uop.exception connect slots_28.io.brupdate.b2.uop.stale_pdst, issue_slots[28].brupdate.b2.uop.stale_pdst connect slots_28.io.brupdate.b2.uop.ppred_busy, issue_slots[28].brupdate.b2.uop.ppred_busy connect slots_28.io.brupdate.b2.uop.prs3_busy, issue_slots[28].brupdate.b2.uop.prs3_busy connect slots_28.io.brupdate.b2.uop.prs2_busy, issue_slots[28].brupdate.b2.uop.prs2_busy connect slots_28.io.brupdate.b2.uop.prs1_busy, issue_slots[28].brupdate.b2.uop.prs1_busy connect slots_28.io.brupdate.b2.uop.ppred, issue_slots[28].brupdate.b2.uop.ppred connect slots_28.io.brupdate.b2.uop.prs3, issue_slots[28].brupdate.b2.uop.prs3 connect slots_28.io.brupdate.b2.uop.prs2, issue_slots[28].brupdate.b2.uop.prs2 connect slots_28.io.brupdate.b2.uop.prs1, issue_slots[28].brupdate.b2.uop.prs1 connect slots_28.io.brupdate.b2.uop.pdst, issue_slots[28].brupdate.b2.uop.pdst connect slots_28.io.brupdate.b2.uop.rxq_idx, issue_slots[28].brupdate.b2.uop.rxq_idx connect slots_28.io.brupdate.b2.uop.stq_idx, issue_slots[28].brupdate.b2.uop.stq_idx connect slots_28.io.brupdate.b2.uop.ldq_idx, issue_slots[28].brupdate.b2.uop.ldq_idx connect slots_28.io.brupdate.b2.uop.rob_idx, issue_slots[28].brupdate.b2.uop.rob_idx connect slots_28.io.brupdate.b2.uop.csr_addr, issue_slots[28].brupdate.b2.uop.csr_addr connect slots_28.io.brupdate.b2.uop.imm_packed, issue_slots[28].brupdate.b2.uop.imm_packed connect slots_28.io.brupdate.b2.uop.taken, issue_slots[28].brupdate.b2.uop.taken connect slots_28.io.brupdate.b2.uop.pc_lob, issue_slots[28].brupdate.b2.uop.pc_lob connect slots_28.io.brupdate.b2.uop.edge_inst, issue_slots[28].brupdate.b2.uop.edge_inst connect slots_28.io.brupdate.b2.uop.ftq_idx, issue_slots[28].brupdate.b2.uop.ftq_idx connect slots_28.io.brupdate.b2.uop.br_tag, issue_slots[28].brupdate.b2.uop.br_tag connect slots_28.io.brupdate.b2.uop.br_mask, issue_slots[28].brupdate.b2.uop.br_mask connect slots_28.io.brupdate.b2.uop.is_sfb, issue_slots[28].brupdate.b2.uop.is_sfb connect slots_28.io.brupdate.b2.uop.is_jal, issue_slots[28].brupdate.b2.uop.is_jal connect slots_28.io.brupdate.b2.uop.is_jalr, issue_slots[28].brupdate.b2.uop.is_jalr connect slots_28.io.brupdate.b2.uop.is_br, issue_slots[28].brupdate.b2.uop.is_br connect slots_28.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[28].brupdate.b2.uop.iw_p2_poisoned connect slots_28.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[28].brupdate.b2.uop.iw_p1_poisoned connect slots_28.io.brupdate.b2.uop.iw_state, issue_slots[28].brupdate.b2.uop.iw_state connect slots_28.io.brupdate.b2.uop.ctrl.is_std, issue_slots[28].brupdate.b2.uop.ctrl.is_std connect slots_28.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[28].brupdate.b2.uop.ctrl.is_sta connect slots_28.io.brupdate.b2.uop.ctrl.is_load, issue_slots[28].brupdate.b2.uop.ctrl.is_load connect slots_28.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[28].brupdate.b2.uop.ctrl.csr_cmd connect slots_28.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[28].brupdate.b2.uop.ctrl.fcn_dw connect slots_28.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[28].brupdate.b2.uop.ctrl.op_fcn connect slots_28.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[28].brupdate.b2.uop.ctrl.imm_sel connect slots_28.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[28].brupdate.b2.uop.ctrl.op2_sel connect slots_28.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[28].brupdate.b2.uop.ctrl.op1_sel connect slots_28.io.brupdate.b2.uop.ctrl.br_type, issue_slots[28].brupdate.b2.uop.ctrl.br_type connect slots_28.io.brupdate.b2.uop.fu_code, issue_slots[28].brupdate.b2.uop.fu_code connect slots_28.io.brupdate.b2.uop.iq_type, issue_slots[28].brupdate.b2.uop.iq_type connect slots_28.io.brupdate.b2.uop.debug_pc, issue_slots[28].brupdate.b2.uop.debug_pc connect slots_28.io.brupdate.b2.uop.is_rvc, issue_slots[28].brupdate.b2.uop.is_rvc connect slots_28.io.brupdate.b2.uop.debug_inst, issue_slots[28].brupdate.b2.uop.debug_inst connect slots_28.io.brupdate.b2.uop.inst, issue_slots[28].brupdate.b2.uop.inst connect slots_28.io.brupdate.b2.uop.uopc, issue_slots[28].brupdate.b2.uop.uopc connect slots_28.io.brupdate.b1.mispredict_mask, issue_slots[28].brupdate.b1.mispredict_mask connect slots_28.io.brupdate.b1.resolve_mask, issue_slots[28].brupdate.b1.resolve_mask connect slots_28.io.grant, issue_slots[28].grant connect issue_slots[28].request_hp, slots_28.io.request_hp connect issue_slots[28].request, slots_28.io.request connect issue_slots[28].will_be_valid, slots_28.io.will_be_valid connect issue_slots[28].valid, slots_28.io.valid connect issue_slots[29].debug.state, slots_29.io.debug.state connect issue_slots[29].debug.ppred, slots_29.io.debug.ppred connect issue_slots[29].debug.p3, slots_29.io.debug.p3 connect issue_slots[29].debug.p2, slots_29.io.debug.p2 connect issue_slots[29].debug.p1, slots_29.io.debug.p1 connect issue_slots[29].uop.debug_tsrc, slots_29.io.uop.debug_tsrc connect issue_slots[29].uop.debug_fsrc, slots_29.io.uop.debug_fsrc connect issue_slots[29].uop.bp_xcpt_if, slots_29.io.uop.bp_xcpt_if connect issue_slots[29].uop.bp_debug_if, slots_29.io.uop.bp_debug_if connect issue_slots[29].uop.xcpt_ma_if, slots_29.io.uop.xcpt_ma_if connect issue_slots[29].uop.xcpt_ae_if, slots_29.io.uop.xcpt_ae_if connect issue_slots[29].uop.xcpt_pf_if, slots_29.io.uop.xcpt_pf_if connect issue_slots[29].uop.fp_single, slots_29.io.uop.fp_single connect issue_slots[29].uop.fp_val, slots_29.io.uop.fp_val connect issue_slots[29].uop.frs3_en, slots_29.io.uop.frs3_en connect issue_slots[29].uop.lrs2_rtype, slots_29.io.uop.lrs2_rtype connect issue_slots[29].uop.lrs1_rtype, slots_29.io.uop.lrs1_rtype connect issue_slots[29].uop.dst_rtype, slots_29.io.uop.dst_rtype connect issue_slots[29].uop.ldst_val, slots_29.io.uop.ldst_val connect issue_slots[29].uop.lrs3, slots_29.io.uop.lrs3 connect issue_slots[29].uop.lrs2, slots_29.io.uop.lrs2 connect issue_slots[29].uop.lrs1, slots_29.io.uop.lrs1 connect issue_slots[29].uop.ldst, slots_29.io.uop.ldst connect issue_slots[29].uop.ldst_is_rs1, slots_29.io.uop.ldst_is_rs1 connect issue_slots[29].uop.flush_on_commit, slots_29.io.uop.flush_on_commit connect issue_slots[29].uop.is_unique, slots_29.io.uop.is_unique connect issue_slots[29].uop.is_sys_pc2epc, slots_29.io.uop.is_sys_pc2epc connect issue_slots[29].uop.uses_stq, slots_29.io.uop.uses_stq connect issue_slots[29].uop.uses_ldq, slots_29.io.uop.uses_ldq connect issue_slots[29].uop.is_amo, slots_29.io.uop.is_amo connect issue_slots[29].uop.is_fencei, slots_29.io.uop.is_fencei connect issue_slots[29].uop.is_fence, slots_29.io.uop.is_fence connect issue_slots[29].uop.mem_signed, slots_29.io.uop.mem_signed connect issue_slots[29].uop.mem_size, slots_29.io.uop.mem_size connect issue_slots[29].uop.mem_cmd, slots_29.io.uop.mem_cmd connect issue_slots[29].uop.bypassable, slots_29.io.uop.bypassable connect issue_slots[29].uop.exc_cause, slots_29.io.uop.exc_cause connect issue_slots[29].uop.exception, slots_29.io.uop.exception connect issue_slots[29].uop.stale_pdst, slots_29.io.uop.stale_pdst connect issue_slots[29].uop.ppred_busy, slots_29.io.uop.ppred_busy connect issue_slots[29].uop.prs3_busy, slots_29.io.uop.prs3_busy connect issue_slots[29].uop.prs2_busy, slots_29.io.uop.prs2_busy connect issue_slots[29].uop.prs1_busy, slots_29.io.uop.prs1_busy connect issue_slots[29].uop.ppred, slots_29.io.uop.ppred connect issue_slots[29].uop.prs3, slots_29.io.uop.prs3 connect issue_slots[29].uop.prs2, slots_29.io.uop.prs2 connect issue_slots[29].uop.prs1, slots_29.io.uop.prs1 connect issue_slots[29].uop.pdst, slots_29.io.uop.pdst connect issue_slots[29].uop.rxq_idx, slots_29.io.uop.rxq_idx connect issue_slots[29].uop.stq_idx, slots_29.io.uop.stq_idx connect issue_slots[29].uop.ldq_idx, slots_29.io.uop.ldq_idx connect issue_slots[29].uop.rob_idx, slots_29.io.uop.rob_idx connect issue_slots[29].uop.csr_addr, slots_29.io.uop.csr_addr connect issue_slots[29].uop.imm_packed, slots_29.io.uop.imm_packed connect issue_slots[29].uop.taken, slots_29.io.uop.taken connect issue_slots[29].uop.pc_lob, slots_29.io.uop.pc_lob connect issue_slots[29].uop.edge_inst, slots_29.io.uop.edge_inst connect issue_slots[29].uop.ftq_idx, slots_29.io.uop.ftq_idx connect issue_slots[29].uop.br_tag, slots_29.io.uop.br_tag connect issue_slots[29].uop.br_mask, slots_29.io.uop.br_mask connect issue_slots[29].uop.is_sfb, slots_29.io.uop.is_sfb connect issue_slots[29].uop.is_jal, slots_29.io.uop.is_jal connect issue_slots[29].uop.is_jalr, slots_29.io.uop.is_jalr connect issue_slots[29].uop.is_br, slots_29.io.uop.is_br connect issue_slots[29].uop.iw_p2_poisoned, slots_29.io.uop.iw_p2_poisoned connect issue_slots[29].uop.iw_p1_poisoned, slots_29.io.uop.iw_p1_poisoned connect issue_slots[29].uop.iw_state, slots_29.io.uop.iw_state connect issue_slots[29].uop.ctrl.is_std, slots_29.io.uop.ctrl.is_std connect issue_slots[29].uop.ctrl.is_sta, slots_29.io.uop.ctrl.is_sta connect issue_slots[29].uop.ctrl.is_load, slots_29.io.uop.ctrl.is_load connect issue_slots[29].uop.ctrl.csr_cmd, slots_29.io.uop.ctrl.csr_cmd connect issue_slots[29].uop.ctrl.fcn_dw, slots_29.io.uop.ctrl.fcn_dw connect issue_slots[29].uop.ctrl.op_fcn, slots_29.io.uop.ctrl.op_fcn connect issue_slots[29].uop.ctrl.imm_sel, slots_29.io.uop.ctrl.imm_sel connect issue_slots[29].uop.ctrl.op2_sel, slots_29.io.uop.ctrl.op2_sel connect issue_slots[29].uop.ctrl.op1_sel, slots_29.io.uop.ctrl.op1_sel connect issue_slots[29].uop.ctrl.br_type, slots_29.io.uop.ctrl.br_type connect issue_slots[29].uop.fu_code, slots_29.io.uop.fu_code connect issue_slots[29].uop.iq_type, slots_29.io.uop.iq_type connect issue_slots[29].uop.debug_pc, slots_29.io.uop.debug_pc connect issue_slots[29].uop.is_rvc, slots_29.io.uop.is_rvc connect issue_slots[29].uop.debug_inst, slots_29.io.uop.debug_inst connect issue_slots[29].uop.inst, slots_29.io.uop.inst connect issue_slots[29].uop.uopc, slots_29.io.uop.uopc connect issue_slots[29].out_uop.debug_tsrc, slots_29.io.out_uop.debug_tsrc connect issue_slots[29].out_uop.debug_fsrc, slots_29.io.out_uop.debug_fsrc connect issue_slots[29].out_uop.bp_xcpt_if, slots_29.io.out_uop.bp_xcpt_if connect issue_slots[29].out_uop.bp_debug_if, slots_29.io.out_uop.bp_debug_if connect issue_slots[29].out_uop.xcpt_ma_if, slots_29.io.out_uop.xcpt_ma_if connect issue_slots[29].out_uop.xcpt_ae_if, slots_29.io.out_uop.xcpt_ae_if connect issue_slots[29].out_uop.xcpt_pf_if, slots_29.io.out_uop.xcpt_pf_if connect issue_slots[29].out_uop.fp_single, slots_29.io.out_uop.fp_single connect issue_slots[29].out_uop.fp_val, slots_29.io.out_uop.fp_val connect issue_slots[29].out_uop.frs3_en, slots_29.io.out_uop.frs3_en connect issue_slots[29].out_uop.lrs2_rtype, slots_29.io.out_uop.lrs2_rtype connect issue_slots[29].out_uop.lrs1_rtype, slots_29.io.out_uop.lrs1_rtype connect issue_slots[29].out_uop.dst_rtype, slots_29.io.out_uop.dst_rtype connect issue_slots[29].out_uop.ldst_val, slots_29.io.out_uop.ldst_val connect issue_slots[29].out_uop.lrs3, slots_29.io.out_uop.lrs3 connect issue_slots[29].out_uop.lrs2, slots_29.io.out_uop.lrs2 connect issue_slots[29].out_uop.lrs1, slots_29.io.out_uop.lrs1 connect issue_slots[29].out_uop.ldst, slots_29.io.out_uop.ldst connect issue_slots[29].out_uop.ldst_is_rs1, slots_29.io.out_uop.ldst_is_rs1 connect issue_slots[29].out_uop.flush_on_commit, slots_29.io.out_uop.flush_on_commit connect issue_slots[29].out_uop.is_unique, slots_29.io.out_uop.is_unique connect issue_slots[29].out_uop.is_sys_pc2epc, slots_29.io.out_uop.is_sys_pc2epc connect issue_slots[29].out_uop.uses_stq, slots_29.io.out_uop.uses_stq connect issue_slots[29].out_uop.uses_ldq, slots_29.io.out_uop.uses_ldq connect issue_slots[29].out_uop.is_amo, slots_29.io.out_uop.is_amo connect issue_slots[29].out_uop.is_fencei, slots_29.io.out_uop.is_fencei connect issue_slots[29].out_uop.is_fence, slots_29.io.out_uop.is_fence connect issue_slots[29].out_uop.mem_signed, slots_29.io.out_uop.mem_signed connect issue_slots[29].out_uop.mem_size, slots_29.io.out_uop.mem_size connect issue_slots[29].out_uop.mem_cmd, slots_29.io.out_uop.mem_cmd connect issue_slots[29].out_uop.bypassable, slots_29.io.out_uop.bypassable connect issue_slots[29].out_uop.exc_cause, slots_29.io.out_uop.exc_cause connect issue_slots[29].out_uop.exception, slots_29.io.out_uop.exception connect issue_slots[29].out_uop.stale_pdst, slots_29.io.out_uop.stale_pdst connect issue_slots[29].out_uop.ppred_busy, slots_29.io.out_uop.ppred_busy connect issue_slots[29].out_uop.prs3_busy, slots_29.io.out_uop.prs3_busy connect issue_slots[29].out_uop.prs2_busy, slots_29.io.out_uop.prs2_busy connect issue_slots[29].out_uop.prs1_busy, slots_29.io.out_uop.prs1_busy connect issue_slots[29].out_uop.ppred, slots_29.io.out_uop.ppred connect issue_slots[29].out_uop.prs3, slots_29.io.out_uop.prs3 connect issue_slots[29].out_uop.prs2, slots_29.io.out_uop.prs2 connect issue_slots[29].out_uop.prs1, slots_29.io.out_uop.prs1 connect issue_slots[29].out_uop.pdst, slots_29.io.out_uop.pdst connect issue_slots[29].out_uop.rxq_idx, slots_29.io.out_uop.rxq_idx connect issue_slots[29].out_uop.stq_idx, slots_29.io.out_uop.stq_idx connect issue_slots[29].out_uop.ldq_idx, slots_29.io.out_uop.ldq_idx connect issue_slots[29].out_uop.rob_idx, slots_29.io.out_uop.rob_idx connect issue_slots[29].out_uop.csr_addr, slots_29.io.out_uop.csr_addr connect issue_slots[29].out_uop.imm_packed, slots_29.io.out_uop.imm_packed connect issue_slots[29].out_uop.taken, slots_29.io.out_uop.taken connect issue_slots[29].out_uop.pc_lob, slots_29.io.out_uop.pc_lob connect issue_slots[29].out_uop.edge_inst, slots_29.io.out_uop.edge_inst connect issue_slots[29].out_uop.ftq_idx, slots_29.io.out_uop.ftq_idx connect issue_slots[29].out_uop.br_tag, slots_29.io.out_uop.br_tag connect issue_slots[29].out_uop.br_mask, slots_29.io.out_uop.br_mask connect issue_slots[29].out_uop.is_sfb, slots_29.io.out_uop.is_sfb connect issue_slots[29].out_uop.is_jal, slots_29.io.out_uop.is_jal connect issue_slots[29].out_uop.is_jalr, slots_29.io.out_uop.is_jalr connect issue_slots[29].out_uop.is_br, slots_29.io.out_uop.is_br connect issue_slots[29].out_uop.iw_p2_poisoned, slots_29.io.out_uop.iw_p2_poisoned connect issue_slots[29].out_uop.iw_p1_poisoned, slots_29.io.out_uop.iw_p1_poisoned connect issue_slots[29].out_uop.iw_state, slots_29.io.out_uop.iw_state connect issue_slots[29].out_uop.ctrl.is_std, slots_29.io.out_uop.ctrl.is_std connect issue_slots[29].out_uop.ctrl.is_sta, slots_29.io.out_uop.ctrl.is_sta connect issue_slots[29].out_uop.ctrl.is_load, slots_29.io.out_uop.ctrl.is_load connect issue_slots[29].out_uop.ctrl.csr_cmd, slots_29.io.out_uop.ctrl.csr_cmd connect issue_slots[29].out_uop.ctrl.fcn_dw, slots_29.io.out_uop.ctrl.fcn_dw connect issue_slots[29].out_uop.ctrl.op_fcn, slots_29.io.out_uop.ctrl.op_fcn connect issue_slots[29].out_uop.ctrl.imm_sel, slots_29.io.out_uop.ctrl.imm_sel connect issue_slots[29].out_uop.ctrl.op2_sel, slots_29.io.out_uop.ctrl.op2_sel connect issue_slots[29].out_uop.ctrl.op1_sel, slots_29.io.out_uop.ctrl.op1_sel connect issue_slots[29].out_uop.ctrl.br_type, slots_29.io.out_uop.ctrl.br_type connect issue_slots[29].out_uop.fu_code, slots_29.io.out_uop.fu_code connect issue_slots[29].out_uop.iq_type, slots_29.io.out_uop.iq_type connect issue_slots[29].out_uop.debug_pc, slots_29.io.out_uop.debug_pc connect issue_slots[29].out_uop.is_rvc, slots_29.io.out_uop.is_rvc connect issue_slots[29].out_uop.debug_inst, slots_29.io.out_uop.debug_inst connect issue_slots[29].out_uop.inst, slots_29.io.out_uop.inst connect issue_slots[29].out_uop.uopc, slots_29.io.out_uop.uopc connect slots_29.io.in_uop.bits.debug_tsrc, issue_slots[29].in_uop.bits.debug_tsrc connect slots_29.io.in_uop.bits.debug_fsrc, issue_slots[29].in_uop.bits.debug_fsrc connect slots_29.io.in_uop.bits.bp_xcpt_if, issue_slots[29].in_uop.bits.bp_xcpt_if connect slots_29.io.in_uop.bits.bp_debug_if, issue_slots[29].in_uop.bits.bp_debug_if connect slots_29.io.in_uop.bits.xcpt_ma_if, issue_slots[29].in_uop.bits.xcpt_ma_if connect slots_29.io.in_uop.bits.xcpt_ae_if, issue_slots[29].in_uop.bits.xcpt_ae_if connect slots_29.io.in_uop.bits.xcpt_pf_if, issue_slots[29].in_uop.bits.xcpt_pf_if connect slots_29.io.in_uop.bits.fp_single, issue_slots[29].in_uop.bits.fp_single connect slots_29.io.in_uop.bits.fp_val, issue_slots[29].in_uop.bits.fp_val connect slots_29.io.in_uop.bits.frs3_en, issue_slots[29].in_uop.bits.frs3_en connect slots_29.io.in_uop.bits.lrs2_rtype, issue_slots[29].in_uop.bits.lrs2_rtype connect slots_29.io.in_uop.bits.lrs1_rtype, issue_slots[29].in_uop.bits.lrs1_rtype connect slots_29.io.in_uop.bits.dst_rtype, issue_slots[29].in_uop.bits.dst_rtype connect slots_29.io.in_uop.bits.ldst_val, issue_slots[29].in_uop.bits.ldst_val connect slots_29.io.in_uop.bits.lrs3, issue_slots[29].in_uop.bits.lrs3 connect slots_29.io.in_uop.bits.lrs2, issue_slots[29].in_uop.bits.lrs2 connect slots_29.io.in_uop.bits.lrs1, issue_slots[29].in_uop.bits.lrs1 connect slots_29.io.in_uop.bits.ldst, issue_slots[29].in_uop.bits.ldst connect slots_29.io.in_uop.bits.ldst_is_rs1, issue_slots[29].in_uop.bits.ldst_is_rs1 connect slots_29.io.in_uop.bits.flush_on_commit, issue_slots[29].in_uop.bits.flush_on_commit connect slots_29.io.in_uop.bits.is_unique, issue_slots[29].in_uop.bits.is_unique connect slots_29.io.in_uop.bits.is_sys_pc2epc, issue_slots[29].in_uop.bits.is_sys_pc2epc connect slots_29.io.in_uop.bits.uses_stq, issue_slots[29].in_uop.bits.uses_stq connect slots_29.io.in_uop.bits.uses_ldq, issue_slots[29].in_uop.bits.uses_ldq connect slots_29.io.in_uop.bits.is_amo, issue_slots[29].in_uop.bits.is_amo connect slots_29.io.in_uop.bits.is_fencei, issue_slots[29].in_uop.bits.is_fencei connect slots_29.io.in_uop.bits.is_fence, issue_slots[29].in_uop.bits.is_fence connect slots_29.io.in_uop.bits.mem_signed, issue_slots[29].in_uop.bits.mem_signed connect slots_29.io.in_uop.bits.mem_size, issue_slots[29].in_uop.bits.mem_size connect slots_29.io.in_uop.bits.mem_cmd, issue_slots[29].in_uop.bits.mem_cmd connect slots_29.io.in_uop.bits.bypassable, issue_slots[29].in_uop.bits.bypassable connect slots_29.io.in_uop.bits.exc_cause, issue_slots[29].in_uop.bits.exc_cause connect slots_29.io.in_uop.bits.exception, issue_slots[29].in_uop.bits.exception connect slots_29.io.in_uop.bits.stale_pdst, issue_slots[29].in_uop.bits.stale_pdst connect slots_29.io.in_uop.bits.ppred_busy, issue_slots[29].in_uop.bits.ppred_busy connect slots_29.io.in_uop.bits.prs3_busy, issue_slots[29].in_uop.bits.prs3_busy connect slots_29.io.in_uop.bits.prs2_busy, issue_slots[29].in_uop.bits.prs2_busy connect slots_29.io.in_uop.bits.prs1_busy, issue_slots[29].in_uop.bits.prs1_busy connect slots_29.io.in_uop.bits.ppred, issue_slots[29].in_uop.bits.ppred connect slots_29.io.in_uop.bits.prs3, issue_slots[29].in_uop.bits.prs3 connect slots_29.io.in_uop.bits.prs2, issue_slots[29].in_uop.bits.prs2 connect slots_29.io.in_uop.bits.prs1, issue_slots[29].in_uop.bits.prs1 connect slots_29.io.in_uop.bits.pdst, issue_slots[29].in_uop.bits.pdst connect slots_29.io.in_uop.bits.rxq_idx, issue_slots[29].in_uop.bits.rxq_idx connect slots_29.io.in_uop.bits.stq_idx, issue_slots[29].in_uop.bits.stq_idx connect slots_29.io.in_uop.bits.ldq_idx, issue_slots[29].in_uop.bits.ldq_idx connect slots_29.io.in_uop.bits.rob_idx, issue_slots[29].in_uop.bits.rob_idx connect slots_29.io.in_uop.bits.csr_addr, issue_slots[29].in_uop.bits.csr_addr connect slots_29.io.in_uop.bits.imm_packed, issue_slots[29].in_uop.bits.imm_packed connect slots_29.io.in_uop.bits.taken, issue_slots[29].in_uop.bits.taken connect slots_29.io.in_uop.bits.pc_lob, issue_slots[29].in_uop.bits.pc_lob connect slots_29.io.in_uop.bits.edge_inst, issue_slots[29].in_uop.bits.edge_inst connect slots_29.io.in_uop.bits.ftq_idx, issue_slots[29].in_uop.bits.ftq_idx connect slots_29.io.in_uop.bits.br_tag, issue_slots[29].in_uop.bits.br_tag connect slots_29.io.in_uop.bits.br_mask, issue_slots[29].in_uop.bits.br_mask connect slots_29.io.in_uop.bits.is_sfb, issue_slots[29].in_uop.bits.is_sfb connect slots_29.io.in_uop.bits.is_jal, issue_slots[29].in_uop.bits.is_jal connect slots_29.io.in_uop.bits.is_jalr, issue_slots[29].in_uop.bits.is_jalr connect slots_29.io.in_uop.bits.is_br, issue_slots[29].in_uop.bits.is_br connect slots_29.io.in_uop.bits.iw_p2_poisoned, issue_slots[29].in_uop.bits.iw_p2_poisoned connect slots_29.io.in_uop.bits.iw_p1_poisoned, issue_slots[29].in_uop.bits.iw_p1_poisoned connect slots_29.io.in_uop.bits.iw_state, issue_slots[29].in_uop.bits.iw_state connect slots_29.io.in_uop.bits.ctrl.is_std, issue_slots[29].in_uop.bits.ctrl.is_std connect slots_29.io.in_uop.bits.ctrl.is_sta, issue_slots[29].in_uop.bits.ctrl.is_sta connect slots_29.io.in_uop.bits.ctrl.is_load, issue_slots[29].in_uop.bits.ctrl.is_load connect slots_29.io.in_uop.bits.ctrl.csr_cmd, issue_slots[29].in_uop.bits.ctrl.csr_cmd connect slots_29.io.in_uop.bits.ctrl.fcn_dw, issue_slots[29].in_uop.bits.ctrl.fcn_dw connect slots_29.io.in_uop.bits.ctrl.op_fcn, issue_slots[29].in_uop.bits.ctrl.op_fcn connect slots_29.io.in_uop.bits.ctrl.imm_sel, issue_slots[29].in_uop.bits.ctrl.imm_sel connect slots_29.io.in_uop.bits.ctrl.op2_sel, issue_slots[29].in_uop.bits.ctrl.op2_sel connect slots_29.io.in_uop.bits.ctrl.op1_sel, issue_slots[29].in_uop.bits.ctrl.op1_sel connect slots_29.io.in_uop.bits.ctrl.br_type, issue_slots[29].in_uop.bits.ctrl.br_type connect slots_29.io.in_uop.bits.fu_code, issue_slots[29].in_uop.bits.fu_code connect slots_29.io.in_uop.bits.iq_type, issue_slots[29].in_uop.bits.iq_type connect slots_29.io.in_uop.bits.debug_pc, issue_slots[29].in_uop.bits.debug_pc connect slots_29.io.in_uop.bits.is_rvc, issue_slots[29].in_uop.bits.is_rvc connect slots_29.io.in_uop.bits.debug_inst, issue_slots[29].in_uop.bits.debug_inst connect slots_29.io.in_uop.bits.inst, issue_slots[29].in_uop.bits.inst connect slots_29.io.in_uop.bits.uopc, issue_slots[29].in_uop.bits.uopc connect slots_29.io.in_uop.valid, issue_slots[29].in_uop.valid connect slots_29.io.spec_ld_wakeup[0].bits, issue_slots[29].spec_ld_wakeup[0].bits connect slots_29.io.spec_ld_wakeup[0].valid, issue_slots[29].spec_ld_wakeup[0].valid connect slots_29.io.pred_wakeup_port.bits, issue_slots[29].pred_wakeup_port.bits connect slots_29.io.pred_wakeup_port.valid, issue_slots[29].pred_wakeup_port.valid connect slots_29.io.wakeup_ports[0].bits.poisoned, issue_slots[29].wakeup_ports[0].bits.poisoned connect slots_29.io.wakeup_ports[0].bits.pdst, issue_slots[29].wakeup_ports[0].bits.pdst connect slots_29.io.wakeup_ports[0].valid, issue_slots[29].wakeup_ports[0].valid connect slots_29.io.wakeup_ports[1].bits.poisoned, issue_slots[29].wakeup_ports[1].bits.poisoned connect slots_29.io.wakeup_ports[1].bits.pdst, issue_slots[29].wakeup_ports[1].bits.pdst connect slots_29.io.wakeup_ports[1].valid, issue_slots[29].wakeup_ports[1].valid connect slots_29.io.wakeup_ports[2].bits.poisoned, issue_slots[29].wakeup_ports[2].bits.poisoned connect slots_29.io.wakeup_ports[2].bits.pdst, issue_slots[29].wakeup_ports[2].bits.pdst connect slots_29.io.wakeup_ports[2].valid, issue_slots[29].wakeup_ports[2].valid connect slots_29.io.wakeup_ports[3].bits.poisoned, issue_slots[29].wakeup_ports[3].bits.poisoned connect slots_29.io.wakeup_ports[3].bits.pdst, issue_slots[29].wakeup_ports[3].bits.pdst connect slots_29.io.wakeup_ports[3].valid, issue_slots[29].wakeup_ports[3].valid connect slots_29.io.wakeup_ports[4].bits.poisoned, issue_slots[29].wakeup_ports[4].bits.poisoned connect slots_29.io.wakeup_ports[4].bits.pdst, issue_slots[29].wakeup_ports[4].bits.pdst connect slots_29.io.wakeup_ports[4].valid, issue_slots[29].wakeup_ports[4].valid connect slots_29.io.wakeup_ports[5].bits.poisoned, issue_slots[29].wakeup_ports[5].bits.poisoned connect slots_29.io.wakeup_ports[5].bits.pdst, issue_slots[29].wakeup_ports[5].bits.pdst connect slots_29.io.wakeup_ports[5].valid, issue_slots[29].wakeup_ports[5].valid connect slots_29.io.wakeup_ports[6].bits.poisoned, issue_slots[29].wakeup_ports[6].bits.poisoned connect slots_29.io.wakeup_ports[6].bits.pdst, issue_slots[29].wakeup_ports[6].bits.pdst connect slots_29.io.wakeup_ports[6].valid, issue_slots[29].wakeup_ports[6].valid connect slots_29.io.ldspec_miss, issue_slots[29].ldspec_miss connect slots_29.io.clear, issue_slots[29].clear connect slots_29.io.kill, issue_slots[29].kill connect slots_29.io.brupdate.b2.target_offset, issue_slots[29].brupdate.b2.target_offset connect slots_29.io.brupdate.b2.jalr_target, issue_slots[29].brupdate.b2.jalr_target connect slots_29.io.brupdate.b2.pc_sel, issue_slots[29].brupdate.b2.pc_sel connect slots_29.io.brupdate.b2.cfi_type, issue_slots[29].brupdate.b2.cfi_type connect slots_29.io.brupdate.b2.taken, issue_slots[29].brupdate.b2.taken connect slots_29.io.brupdate.b2.mispredict, issue_slots[29].brupdate.b2.mispredict connect slots_29.io.brupdate.b2.valid, issue_slots[29].brupdate.b2.valid connect slots_29.io.brupdate.b2.uop.debug_tsrc, issue_slots[29].brupdate.b2.uop.debug_tsrc connect slots_29.io.brupdate.b2.uop.debug_fsrc, issue_slots[29].brupdate.b2.uop.debug_fsrc connect slots_29.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[29].brupdate.b2.uop.bp_xcpt_if connect slots_29.io.brupdate.b2.uop.bp_debug_if, issue_slots[29].brupdate.b2.uop.bp_debug_if connect slots_29.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[29].brupdate.b2.uop.xcpt_ma_if connect slots_29.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[29].brupdate.b2.uop.xcpt_ae_if connect slots_29.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[29].brupdate.b2.uop.xcpt_pf_if connect slots_29.io.brupdate.b2.uop.fp_single, issue_slots[29].brupdate.b2.uop.fp_single connect slots_29.io.brupdate.b2.uop.fp_val, issue_slots[29].brupdate.b2.uop.fp_val connect slots_29.io.brupdate.b2.uop.frs3_en, issue_slots[29].brupdate.b2.uop.frs3_en connect slots_29.io.brupdate.b2.uop.lrs2_rtype, issue_slots[29].brupdate.b2.uop.lrs2_rtype connect slots_29.io.brupdate.b2.uop.lrs1_rtype, issue_slots[29].brupdate.b2.uop.lrs1_rtype connect slots_29.io.brupdate.b2.uop.dst_rtype, issue_slots[29].brupdate.b2.uop.dst_rtype connect slots_29.io.brupdate.b2.uop.ldst_val, issue_slots[29].brupdate.b2.uop.ldst_val connect slots_29.io.brupdate.b2.uop.lrs3, issue_slots[29].brupdate.b2.uop.lrs3 connect slots_29.io.brupdate.b2.uop.lrs2, issue_slots[29].brupdate.b2.uop.lrs2 connect slots_29.io.brupdate.b2.uop.lrs1, issue_slots[29].brupdate.b2.uop.lrs1 connect slots_29.io.brupdate.b2.uop.ldst, issue_slots[29].brupdate.b2.uop.ldst connect slots_29.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[29].brupdate.b2.uop.ldst_is_rs1 connect slots_29.io.brupdate.b2.uop.flush_on_commit, issue_slots[29].brupdate.b2.uop.flush_on_commit connect slots_29.io.brupdate.b2.uop.is_unique, issue_slots[29].brupdate.b2.uop.is_unique connect slots_29.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[29].brupdate.b2.uop.is_sys_pc2epc connect slots_29.io.brupdate.b2.uop.uses_stq, issue_slots[29].brupdate.b2.uop.uses_stq connect slots_29.io.brupdate.b2.uop.uses_ldq, issue_slots[29].brupdate.b2.uop.uses_ldq connect slots_29.io.brupdate.b2.uop.is_amo, issue_slots[29].brupdate.b2.uop.is_amo connect slots_29.io.brupdate.b2.uop.is_fencei, issue_slots[29].brupdate.b2.uop.is_fencei connect slots_29.io.brupdate.b2.uop.is_fence, issue_slots[29].brupdate.b2.uop.is_fence connect slots_29.io.brupdate.b2.uop.mem_signed, issue_slots[29].brupdate.b2.uop.mem_signed connect slots_29.io.brupdate.b2.uop.mem_size, issue_slots[29].brupdate.b2.uop.mem_size connect slots_29.io.brupdate.b2.uop.mem_cmd, issue_slots[29].brupdate.b2.uop.mem_cmd connect slots_29.io.brupdate.b2.uop.bypassable, issue_slots[29].brupdate.b2.uop.bypassable connect slots_29.io.brupdate.b2.uop.exc_cause, issue_slots[29].brupdate.b2.uop.exc_cause connect slots_29.io.brupdate.b2.uop.exception, issue_slots[29].brupdate.b2.uop.exception connect slots_29.io.brupdate.b2.uop.stale_pdst, issue_slots[29].brupdate.b2.uop.stale_pdst connect slots_29.io.brupdate.b2.uop.ppred_busy, issue_slots[29].brupdate.b2.uop.ppred_busy connect slots_29.io.brupdate.b2.uop.prs3_busy, issue_slots[29].brupdate.b2.uop.prs3_busy connect slots_29.io.brupdate.b2.uop.prs2_busy, issue_slots[29].brupdate.b2.uop.prs2_busy connect slots_29.io.brupdate.b2.uop.prs1_busy, issue_slots[29].brupdate.b2.uop.prs1_busy connect slots_29.io.brupdate.b2.uop.ppred, issue_slots[29].brupdate.b2.uop.ppred connect slots_29.io.brupdate.b2.uop.prs3, issue_slots[29].brupdate.b2.uop.prs3 connect slots_29.io.brupdate.b2.uop.prs2, issue_slots[29].brupdate.b2.uop.prs2 connect slots_29.io.brupdate.b2.uop.prs1, issue_slots[29].brupdate.b2.uop.prs1 connect slots_29.io.brupdate.b2.uop.pdst, issue_slots[29].brupdate.b2.uop.pdst connect slots_29.io.brupdate.b2.uop.rxq_idx, issue_slots[29].brupdate.b2.uop.rxq_idx connect slots_29.io.brupdate.b2.uop.stq_idx, issue_slots[29].brupdate.b2.uop.stq_idx connect slots_29.io.brupdate.b2.uop.ldq_idx, issue_slots[29].brupdate.b2.uop.ldq_idx connect slots_29.io.brupdate.b2.uop.rob_idx, issue_slots[29].brupdate.b2.uop.rob_idx connect slots_29.io.brupdate.b2.uop.csr_addr, issue_slots[29].brupdate.b2.uop.csr_addr connect slots_29.io.brupdate.b2.uop.imm_packed, issue_slots[29].brupdate.b2.uop.imm_packed connect slots_29.io.brupdate.b2.uop.taken, issue_slots[29].brupdate.b2.uop.taken connect slots_29.io.brupdate.b2.uop.pc_lob, issue_slots[29].brupdate.b2.uop.pc_lob connect slots_29.io.brupdate.b2.uop.edge_inst, issue_slots[29].brupdate.b2.uop.edge_inst connect slots_29.io.brupdate.b2.uop.ftq_idx, issue_slots[29].brupdate.b2.uop.ftq_idx connect slots_29.io.brupdate.b2.uop.br_tag, issue_slots[29].brupdate.b2.uop.br_tag connect slots_29.io.brupdate.b2.uop.br_mask, issue_slots[29].brupdate.b2.uop.br_mask connect slots_29.io.brupdate.b2.uop.is_sfb, issue_slots[29].brupdate.b2.uop.is_sfb connect slots_29.io.brupdate.b2.uop.is_jal, issue_slots[29].brupdate.b2.uop.is_jal connect slots_29.io.brupdate.b2.uop.is_jalr, issue_slots[29].brupdate.b2.uop.is_jalr connect slots_29.io.brupdate.b2.uop.is_br, issue_slots[29].brupdate.b2.uop.is_br connect slots_29.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[29].brupdate.b2.uop.iw_p2_poisoned connect slots_29.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[29].brupdate.b2.uop.iw_p1_poisoned connect slots_29.io.brupdate.b2.uop.iw_state, issue_slots[29].brupdate.b2.uop.iw_state connect slots_29.io.brupdate.b2.uop.ctrl.is_std, issue_slots[29].brupdate.b2.uop.ctrl.is_std connect slots_29.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[29].brupdate.b2.uop.ctrl.is_sta connect slots_29.io.brupdate.b2.uop.ctrl.is_load, issue_slots[29].brupdate.b2.uop.ctrl.is_load connect slots_29.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[29].brupdate.b2.uop.ctrl.csr_cmd connect slots_29.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[29].brupdate.b2.uop.ctrl.fcn_dw connect slots_29.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[29].brupdate.b2.uop.ctrl.op_fcn connect slots_29.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[29].brupdate.b2.uop.ctrl.imm_sel connect slots_29.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[29].brupdate.b2.uop.ctrl.op2_sel connect slots_29.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[29].brupdate.b2.uop.ctrl.op1_sel connect slots_29.io.brupdate.b2.uop.ctrl.br_type, issue_slots[29].brupdate.b2.uop.ctrl.br_type connect slots_29.io.brupdate.b2.uop.fu_code, issue_slots[29].brupdate.b2.uop.fu_code connect slots_29.io.brupdate.b2.uop.iq_type, issue_slots[29].brupdate.b2.uop.iq_type connect slots_29.io.brupdate.b2.uop.debug_pc, issue_slots[29].brupdate.b2.uop.debug_pc connect slots_29.io.brupdate.b2.uop.is_rvc, issue_slots[29].brupdate.b2.uop.is_rvc connect slots_29.io.brupdate.b2.uop.debug_inst, issue_slots[29].brupdate.b2.uop.debug_inst connect slots_29.io.brupdate.b2.uop.inst, issue_slots[29].brupdate.b2.uop.inst connect slots_29.io.brupdate.b2.uop.uopc, issue_slots[29].brupdate.b2.uop.uopc connect slots_29.io.brupdate.b1.mispredict_mask, issue_slots[29].brupdate.b1.mispredict_mask connect slots_29.io.brupdate.b1.resolve_mask, issue_slots[29].brupdate.b1.resolve_mask connect slots_29.io.grant, issue_slots[29].grant connect issue_slots[29].request_hp, slots_29.io.request_hp connect issue_slots[29].request, slots_29.io.request connect issue_slots[29].will_be_valid, slots_29.io.will_be_valid connect issue_slots[29].valid, slots_29.io.valid connect issue_slots[30].debug.state, slots_30.io.debug.state connect issue_slots[30].debug.ppred, slots_30.io.debug.ppred connect issue_slots[30].debug.p3, slots_30.io.debug.p3 connect issue_slots[30].debug.p2, slots_30.io.debug.p2 connect issue_slots[30].debug.p1, slots_30.io.debug.p1 connect issue_slots[30].uop.debug_tsrc, slots_30.io.uop.debug_tsrc connect issue_slots[30].uop.debug_fsrc, slots_30.io.uop.debug_fsrc connect issue_slots[30].uop.bp_xcpt_if, slots_30.io.uop.bp_xcpt_if connect issue_slots[30].uop.bp_debug_if, slots_30.io.uop.bp_debug_if connect issue_slots[30].uop.xcpt_ma_if, slots_30.io.uop.xcpt_ma_if connect issue_slots[30].uop.xcpt_ae_if, slots_30.io.uop.xcpt_ae_if connect issue_slots[30].uop.xcpt_pf_if, slots_30.io.uop.xcpt_pf_if connect issue_slots[30].uop.fp_single, slots_30.io.uop.fp_single connect issue_slots[30].uop.fp_val, slots_30.io.uop.fp_val connect issue_slots[30].uop.frs3_en, slots_30.io.uop.frs3_en connect issue_slots[30].uop.lrs2_rtype, slots_30.io.uop.lrs2_rtype connect issue_slots[30].uop.lrs1_rtype, slots_30.io.uop.lrs1_rtype connect issue_slots[30].uop.dst_rtype, slots_30.io.uop.dst_rtype connect issue_slots[30].uop.ldst_val, slots_30.io.uop.ldst_val connect issue_slots[30].uop.lrs3, slots_30.io.uop.lrs3 connect issue_slots[30].uop.lrs2, slots_30.io.uop.lrs2 connect issue_slots[30].uop.lrs1, slots_30.io.uop.lrs1 connect issue_slots[30].uop.ldst, slots_30.io.uop.ldst connect issue_slots[30].uop.ldst_is_rs1, slots_30.io.uop.ldst_is_rs1 connect issue_slots[30].uop.flush_on_commit, slots_30.io.uop.flush_on_commit connect issue_slots[30].uop.is_unique, slots_30.io.uop.is_unique connect issue_slots[30].uop.is_sys_pc2epc, slots_30.io.uop.is_sys_pc2epc connect issue_slots[30].uop.uses_stq, slots_30.io.uop.uses_stq connect issue_slots[30].uop.uses_ldq, slots_30.io.uop.uses_ldq connect issue_slots[30].uop.is_amo, slots_30.io.uop.is_amo connect issue_slots[30].uop.is_fencei, slots_30.io.uop.is_fencei connect issue_slots[30].uop.is_fence, slots_30.io.uop.is_fence connect issue_slots[30].uop.mem_signed, slots_30.io.uop.mem_signed connect issue_slots[30].uop.mem_size, slots_30.io.uop.mem_size connect issue_slots[30].uop.mem_cmd, slots_30.io.uop.mem_cmd connect issue_slots[30].uop.bypassable, slots_30.io.uop.bypassable connect issue_slots[30].uop.exc_cause, slots_30.io.uop.exc_cause connect issue_slots[30].uop.exception, slots_30.io.uop.exception connect issue_slots[30].uop.stale_pdst, slots_30.io.uop.stale_pdst connect issue_slots[30].uop.ppred_busy, slots_30.io.uop.ppred_busy connect issue_slots[30].uop.prs3_busy, slots_30.io.uop.prs3_busy connect issue_slots[30].uop.prs2_busy, slots_30.io.uop.prs2_busy connect issue_slots[30].uop.prs1_busy, slots_30.io.uop.prs1_busy connect issue_slots[30].uop.ppred, slots_30.io.uop.ppred connect issue_slots[30].uop.prs3, slots_30.io.uop.prs3 connect issue_slots[30].uop.prs2, slots_30.io.uop.prs2 connect issue_slots[30].uop.prs1, slots_30.io.uop.prs1 connect issue_slots[30].uop.pdst, slots_30.io.uop.pdst connect issue_slots[30].uop.rxq_idx, slots_30.io.uop.rxq_idx connect issue_slots[30].uop.stq_idx, slots_30.io.uop.stq_idx connect issue_slots[30].uop.ldq_idx, slots_30.io.uop.ldq_idx connect issue_slots[30].uop.rob_idx, slots_30.io.uop.rob_idx connect issue_slots[30].uop.csr_addr, slots_30.io.uop.csr_addr connect issue_slots[30].uop.imm_packed, slots_30.io.uop.imm_packed connect issue_slots[30].uop.taken, slots_30.io.uop.taken connect issue_slots[30].uop.pc_lob, slots_30.io.uop.pc_lob connect issue_slots[30].uop.edge_inst, slots_30.io.uop.edge_inst connect issue_slots[30].uop.ftq_idx, slots_30.io.uop.ftq_idx connect issue_slots[30].uop.br_tag, slots_30.io.uop.br_tag connect issue_slots[30].uop.br_mask, slots_30.io.uop.br_mask connect issue_slots[30].uop.is_sfb, slots_30.io.uop.is_sfb connect issue_slots[30].uop.is_jal, slots_30.io.uop.is_jal connect issue_slots[30].uop.is_jalr, slots_30.io.uop.is_jalr connect issue_slots[30].uop.is_br, slots_30.io.uop.is_br connect issue_slots[30].uop.iw_p2_poisoned, slots_30.io.uop.iw_p2_poisoned connect issue_slots[30].uop.iw_p1_poisoned, slots_30.io.uop.iw_p1_poisoned connect issue_slots[30].uop.iw_state, slots_30.io.uop.iw_state connect issue_slots[30].uop.ctrl.is_std, slots_30.io.uop.ctrl.is_std connect issue_slots[30].uop.ctrl.is_sta, slots_30.io.uop.ctrl.is_sta connect issue_slots[30].uop.ctrl.is_load, slots_30.io.uop.ctrl.is_load connect issue_slots[30].uop.ctrl.csr_cmd, slots_30.io.uop.ctrl.csr_cmd connect issue_slots[30].uop.ctrl.fcn_dw, slots_30.io.uop.ctrl.fcn_dw connect issue_slots[30].uop.ctrl.op_fcn, slots_30.io.uop.ctrl.op_fcn connect issue_slots[30].uop.ctrl.imm_sel, slots_30.io.uop.ctrl.imm_sel connect issue_slots[30].uop.ctrl.op2_sel, slots_30.io.uop.ctrl.op2_sel connect issue_slots[30].uop.ctrl.op1_sel, slots_30.io.uop.ctrl.op1_sel connect issue_slots[30].uop.ctrl.br_type, slots_30.io.uop.ctrl.br_type connect issue_slots[30].uop.fu_code, slots_30.io.uop.fu_code connect issue_slots[30].uop.iq_type, slots_30.io.uop.iq_type connect issue_slots[30].uop.debug_pc, slots_30.io.uop.debug_pc connect issue_slots[30].uop.is_rvc, slots_30.io.uop.is_rvc connect issue_slots[30].uop.debug_inst, slots_30.io.uop.debug_inst connect issue_slots[30].uop.inst, slots_30.io.uop.inst connect issue_slots[30].uop.uopc, slots_30.io.uop.uopc connect issue_slots[30].out_uop.debug_tsrc, slots_30.io.out_uop.debug_tsrc connect issue_slots[30].out_uop.debug_fsrc, slots_30.io.out_uop.debug_fsrc connect issue_slots[30].out_uop.bp_xcpt_if, slots_30.io.out_uop.bp_xcpt_if connect issue_slots[30].out_uop.bp_debug_if, slots_30.io.out_uop.bp_debug_if connect issue_slots[30].out_uop.xcpt_ma_if, slots_30.io.out_uop.xcpt_ma_if connect issue_slots[30].out_uop.xcpt_ae_if, slots_30.io.out_uop.xcpt_ae_if connect issue_slots[30].out_uop.xcpt_pf_if, slots_30.io.out_uop.xcpt_pf_if connect issue_slots[30].out_uop.fp_single, slots_30.io.out_uop.fp_single connect issue_slots[30].out_uop.fp_val, slots_30.io.out_uop.fp_val connect issue_slots[30].out_uop.frs3_en, slots_30.io.out_uop.frs3_en connect issue_slots[30].out_uop.lrs2_rtype, slots_30.io.out_uop.lrs2_rtype connect issue_slots[30].out_uop.lrs1_rtype, slots_30.io.out_uop.lrs1_rtype connect issue_slots[30].out_uop.dst_rtype, slots_30.io.out_uop.dst_rtype connect issue_slots[30].out_uop.ldst_val, slots_30.io.out_uop.ldst_val connect issue_slots[30].out_uop.lrs3, slots_30.io.out_uop.lrs3 connect issue_slots[30].out_uop.lrs2, slots_30.io.out_uop.lrs2 connect issue_slots[30].out_uop.lrs1, slots_30.io.out_uop.lrs1 connect issue_slots[30].out_uop.ldst, slots_30.io.out_uop.ldst connect issue_slots[30].out_uop.ldst_is_rs1, slots_30.io.out_uop.ldst_is_rs1 connect issue_slots[30].out_uop.flush_on_commit, slots_30.io.out_uop.flush_on_commit connect issue_slots[30].out_uop.is_unique, slots_30.io.out_uop.is_unique connect issue_slots[30].out_uop.is_sys_pc2epc, slots_30.io.out_uop.is_sys_pc2epc connect issue_slots[30].out_uop.uses_stq, slots_30.io.out_uop.uses_stq connect issue_slots[30].out_uop.uses_ldq, slots_30.io.out_uop.uses_ldq connect issue_slots[30].out_uop.is_amo, slots_30.io.out_uop.is_amo connect issue_slots[30].out_uop.is_fencei, slots_30.io.out_uop.is_fencei connect issue_slots[30].out_uop.is_fence, slots_30.io.out_uop.is_fence connect issue_slots[30].out_uop.mem_signed, slots_30.io.out_uop.mem_signed connect issue_slots[30].out_uop.mem_size, slots_30.io.out_uop.mem_size connect issue_slots[30].out_uop.mem_cmd, slots_30.io.out_uop.mem_cmd connect issue_slots[30].out_uop.bypassable, slots_30.io.out_uop.bypassable connect issue_slots[30].out_uop.exc_cause, slots_30.io.out_uop.exc_cause connect issue_slots[30].out_uop.exception, slots_30.io.out_uop.exception connect issue_slots[30].out_uop.stale_pdst, slots_30.io.out_uop.stale_pdst connect issue_slots[30].out_uop.ppred_busy, slots_30.io.out_uop.ppred_busy connect issue_slots[30].out_uop.prs3_busy, slots_30.io.out_uop.prs3_busy connect issue_slots[30].out_uop.prs2_busy, slots_30.io.out_uop.prs2_busy connect issue_slots[30].out_uop.prs1_busy, slots_30.io.out_uop.prs1_busy connect issue_slots[30].out_uop.ppred, slots_30.io.out_uop.ppred connect issue_slots[30].out_uop.prs3, slots_30.io.out_uop.prs3 connect issue_slots[30].out_uop.prs2, slots_30.io.out_uop.prs2 connect issue_slots[30].out_uop.prs1, slots_30.io.out_uop.prs1 connect issue_slots[30].out_uop.pdst, slots_30.io.out_uop.pdst connect issue_slots[30].out_uop.rxq_idx, slots_30.io.out_uop.rxq_idx connect issue_slots[30].out_uop.stq_idx, slots_30.io.out_uop.stq_idx connect issue_slots[30].out_uop.ldq_idx, slots_30.io.out_uop.ldq_idx connect issue_slots[30].out_uop.rob_idx, slots_30.io.out_uop.rob_idx connect issue_slots[30].out_uop.csr_addr, slots_30.io.out_uop.csr_addr connect issue_slots[30].out_uop.imm_packed, slots_30.io.out_uop.imm_packed connect issue_slots[30].out_uop.taken, slots_30.io.out_uop.taken connect issue_slots[30].out_uop.pc_lob, slots_30.io.out_uop.pc_lob connect issue_slots[30].out_uop.edge_inst, slots_30.io.out_uop.edge_inst connect issue_slots[30].out_uop.ftq_idx, slots_30.io.out_uop.ftq_idx connect issue_slots[30].out_uop.br_tag, slots_30.io.out_uop.br_tag connect issue_slots[30].out_uop.br_mask, slots_30.io.out_uop.br_mask connect issue_slots[30].out_uop.is_sfb, slots_30.io.out_uop.is_sfb connect issue_slots[30].out_uop.is_jal, slots_30.io.out_uop.is_jal connect issue_slots[30].out_uop.is_jalr, slots_30.io.out_uop.is_jalr connect issue_slots[30].out_uop.is_br, slots_30.io.out_uop.is_br connect issue_slots[30].out_uop.iw_p2_poisoned, slots_30.io.out_uop.iw_p2_poisoned connect issue_slots[30].out_uop.iw_p1_poisoned, slots_30.io.out_uop.iw_p1_poisoned connect issue_slots[30].out_uop.iw_state, slots_30.io.out_uop.iw_state connect issue_slots[30].out_uop.ctrl.is_std, slots_30.io.out_uop.ctrl.is_std connect issue_slots[30].out_uop.ctrl.is_sta, slots_30.io.out_uop.ctrl.is_sta connect issue_slots[30].out_uop.ctrl.is_load, slots_30.io.out_uop.ctrl.is_load connect issue_slots[30].out_uop.ctrl.csr_cmd, slots_30.io.out_uop.ctrl.csr_cmd connect issue_slots[30].out_uop.ctrl.fcn_dw, slots_30.io.out_uop.ctrl.fcn_dw connect issue_slots[30].out_uop.ctrl.op_fcn, slots_30.io.out_uop.ctrl.op_fcn connect issue_slots[30].out_uop.ctrl.imm_sel, slots_30.io.out_uop.ctrl.imm_sel connect issue_slots[30].out_uop.ctrl.op2_sel, slots_30.io.out_uop.ctrl.op2_sel connect issue_slots[30].out_uop.ctrl.op1_sel, slots_30.io.out_uop.ctrl.op1_sel connect issue_slots[30].out_uop.ctrl.br_type, slots_30.io.out_uop.ctrl.br_type connect issue_slots[30].out_uop.fu_code, slots_30.io.out_uop.fu_code connect issue_slots[30].out_uop.iq_type, slots_30.io.out_uop.iq_type connect issue_slots[30].out_uop.debug_pc, slots_30.io.out_uop.debug_pc connect issue_slots[30].out_uop.is_rvc, slots_30.io.out_uop.is_rvc connect issue_slots[30].out_uop.debug_inst, slots_30.io.out_uop.debug_inst connect issue_slots[30].out_uop.inst, slots_30.io.out_uop.inst connect issue_slots[30].out_uop.uopc, slots_30.io.out_uop.uopc connect slots_30.io.in_uop.bits.debug_tsrc, issue_slots[30].in_uop.bits.debug_tsrc connect slots_30.io.in_uop.bits.debug_fsrc, issue_slots[30].in_uop.bits.debug_fsrc connect slots_30.io.in_uop.bits.bp_xcpt_if, issue_slots[30].in_uop.bits.bp_xcpt_if connect slots_30.io.in_uop.bits.bp_debug_if, issue_slots[30].in_uop.bits.bp_debug_if connect slots_30.io.in_uop.bits.xcpt_ma_if, issue_slots[30].in_uop.bits.xcpt_ma_if connect slots_30.io.in_uop.bits.xcpt_ae_if, issue_slots[30].in_uop.bits.xcpt_ae_if connect slots_30.io.in_uop.bits.xcpt_pf_if, issue_slots[30].in_uop.bits.xcpt_pf_if connect slots_30.io.in_uop.bits.fp_single, issue_slots[30].in_uop.bits.fp_single connect slots_30.io.in_uop.bits.fp_val, issue_slots[30].in_uop.bits.fp_val connect slots_30.io.in_uop.bits.frs3_en, issue_slots[30].in_uop.bits.frs3_en connect slots_30.io.in_uop.bits.lrs2_rtype, issue_slots[30].in_uop.bits.lrs2_rtype connect slots_30.io.in_uop.bits.lrs1_rtype, issue_slots[30].in_uop.bits.lrs1_rtype connect slots_30.io.in_uop.bits.dst_rtype, issue_slots[30].in_uop.bits.dst_rtype connect slots_30.io.in_uop.bits.ldst_val, issue_slots[30].in_uop.bits.ldst_val connect slots_30.io.in_uop.bits.lrs3, issue_slots[30].in_uop.bits.lrs3 connect slots_30.io.in_uop.bits.lrs2, issue_slots[30].in_uop.bits.lrs2 connect slots_30.io.in_uop.bits.lrs1, issue_slots[30].in_uop.bits.lrs1 connect slots_30.io.in_uop.bits.ldst, issue_slots[30].in_uop.bits.ldst connect slots_30.io.in_uop.bits.ldst_is_rs1, issue_slots[30].in_uop.bits.ldst_is_rs1 connect slots_30.io.in_uop.bits.flush_on_commit, issue_slots[30].in_uop.bits.flush_on_commit connect slots_30.io.in_uop.bits.is_unique, issue_slots[30].in_uop.bits.is_unique connect slots_30.io.in_uop.bits.is_sys_pc2epc, issue_slots[30].in_uop.bits.is_sys_pc2epc connect slots_30.io.in_uop.bits.uses_stq, issue_slots[30].in_uop.bits.uses_stq connect slots_30.io.in_uop.bits.uses_ldq, issue_slots[30].in_uop.bits.uses_ldq connect slots_30.io.in_uop.bits.is_amo, issue_slots[30].in_uop.bits.is_amo connect slots_30.io.in_uop.bits.is_fencei, issue_slots[30].in_uop.bits.is_fencei connect slots_30.io.in_uop.bits.is_fence, issue_slots[30].in_uop.bits.is_fence connect slots_30.io.in_uop.bits.mem_signed, issue_slots[30].in_uop.bits.mem_signed connect slots_30.io.in_uop.bits.mem_size, issue_slots[30].in_uop.bits.mem_size connect slots_30.io.in_uop.bits.mem_cmd, issue_slots[30].in_uop.bits.mem_cmd connect slots_30.io.in_uop.bits.bypassable, issue_slots[30].in_uop.bits.bypassable connect slots_30.io.in_uop.bits.exc_cause, issue_slots[30].in_uop.bits.exc_cause connect slots_30.io.in_uop.bits.exception, issue_slots[30].in_uop.bits.exception connect slots_30.io.in_uop.bits.stale_pdst, issue_slots[30].in_uop.bits.stale_pdst connect slots_30.io.in_uop.bits.ppred_busy, issue_slots[30].in_uop.bits.ppred_busy connect slots_30.io.in_uop.bits.prs3_busy, issue_slots[30].in_uop.bits.prs3_busy connect slots_30.io.in_uop.bits.prs2_busy, issue_slots[30].in_uop.bits.prs2_busy connect slots_30.io.in_uop.bits.prs1_busy, issue_slots[30].in_uop.bits.prs1_busy connect slots_30.io.in_uop.bits.ppred, issue_slots[30].in_uop.bits.ppred connect slots_30.io.in_uop.bits.prs3, issue_slots[30].in_uop.bits.prs3 connect slots_30.io.in_uop.bits.prs2, issue_slots[30].in_uop.bits.prs2 connect slots_30.io.in_uop.bits.prs1, issue_slots[30].in_uop.bits.prs1 connect slots_30.io.in_uop.bits.pdst, issue_slots[30].in_uop.bits.pdst connect slots_30.io.in_uop.bits.rxq_idx, issue_slots[30].in_uop.bits.rxq_idx connect slots_30.io.in_uop.bits.stq_idx, issue_slots[30].in_uop.bits.stq_idx connect slots_30.io.in_uop.bits.ldq_idx, issue_slots[30].in_uop.bits.ldq_idx connect slots_30.io.in_uop.bits.rob_idx, issue_slots[30].in_uop.bits.rob_idx connect slots_30.io.in_uop.bits.csr_addr, issue_slots[30].in_uop.bits.csr_addr connect slots_30.io.in_uop.bits.imm_packed, issue_slots[30].in_uop.bits.imm_packed connect slots_30.io.in_uop.bits.taken, issue_slots[30].in_uop.bits.taken connect slots_30.io.in_uop.bits.pc_lob, issue_slots[30].in_uop.bits.pc_lob connect slots_30.io.in_uop.bits.edge_inst, issue_slots[30].in_uop.bits.edge_inst connect slots_30.io.in_uop.bits.ftq_idx, issue_slots[30].in_uop.bits.ftq_idx connect slots_30.io.in_uop.bits.br_tag, issue_slots[30].in_uop.bits.br_tag connect slots_30.io.in_uop.bits.br_mask, issue_slots[30].in_uop.bits.br_mask connect slots_30.io.in_uop.bits.is_sfb, issue_slots[30].in_uop.bits.is_sfb connect slots_30.io.in_uop.bits.is_jal, issue_slots[30].in_uop.bits.is_jal connect slots_30.io.in_uop.bits.is_jalr, issue_slots[30].in_uop.bits.is_jalr connect slots_30.io.in_uop.bits.is_br, issue_slots[30].in_uop.bits.is_br connect slots_30.io.in_uop.bits.iw_p2_poisoned, issue_slots[30].in_uop.bits.iw_p2_poisoned connect slots_30.io.in_uop.bits.iw_p1_poisoned, issue_slots[30].in_uop.bits.iw_p1_poisoned connect slots_30.io.in_uop.bits.iw_state, issue_slots[30].in_uop.bits.iw_state connect slots_30.io.in_uop.bits.ctrl.is_std, issue_slots[30].in_uop.bits.ctrl.is_std connect slots_30.io.in_uop.bits.ctrl.is_sta, issue_slots[30].in_uop.bits.ctrl.is_sta connect slots_30.io.in_uop.bits.ctrl.is_load, issue_slots[30].in_uop.bits.ctrl.is_load connect slots_30.io.in_uop.bits.ctrl.csr_cmd, issue_slots[30].in_uop.bits.ctrl.csr_cmd connect slots_30.io.in_uop.bits.ctrl.fcn_dw, issue_slots[30].in_uop.bits.ctrl.fcn_dw connect slots_30.io.in_uop.bits.ctrl.op_fcn, issue_slots[30].in_uop.bits.ctrl.op_fcn connect slots_30.io.in_uop.bits.ctrl.imm_sel, issue_slots[30].in_uop.bits.ctrl.imm_sel connect slots_30.io.in_uop.bits.ctrl.op2_sel, issue_slots[30].in_uop.bits.ctrl.op2_sel connect slots_30.io.in_uop.bits.ctrl.op1_sel, issue_slots[30].in_uop.bits.ctrl.op1_sel connect slots_30.io.in_uop.bits.ctrl.br_type, issue_slots[30].in_uop.bits.ctrl.br_type connect slots_30.io.in_uop.bits.fu_code, issue_slots[30].in_uop.bits.fu_code connect slots_30.io.in_uop.bits.iq_type, issue_slots[30].in_uop.bits.iq_type connect slots_30.io.in_uop.bits.debug_pc, issue_slots[30].in_uop.bits.debug_pc connect slots_30.io.in_uop.bits.is_rvc, issue_slots[30].in_uop.bits.is_rvc connect slots_30.io.in_uop.bits.debug_inst, issue_slots[30].in_uop.bits.debug_inst connect slots_30.io.in_uop.bits.inst, issue_slots[30].in_uop.bits.inst connect slots_30.io.in_uop.bits.uopc, issue_slots[30].in_uop.bits.uopc connect slots_30.io.in_uop.valid, issue_slots[30].in_uop.valid connect slots_30.io.spec_ld_wakeup[0].bits, issue_slots[30].spec_ld_wakeup[0].bits connect slots_30.io.spec_ld_wakeup[0].valid, issue_slots[30].spec_ld_wakeup[0].valid connect slots_30.io.pred_wakeup_port.bits, issue_slots[30].pred_wakeup_port.bits connect slots_30.io.pred_wakeup_port.valid, issue_slots[30].pred_wakeup_port.valid connect slots_30.io.wakeup_ports[0].bits.poisoned, issue_slots[30].wakeup_ports[0].bits.poisoned connect slots_30.io.wakeup_ports[0].bits.pdst, issue_slots[30].wakeup_ports[0].bits.pdst connect slots_30.io.wakeup_ports[0].valid, issue_slots[30].wakeup_ports[0].valid connect slots_30.io.wakeup_ports[1].bits.poisoned, issue_slots[30].wakeup_ports[1].bits.poisoned connect slots_30.io.wakeup_ports[1].bits.pdst, issue_slots[30].wakeup_ports[1].bits.pdst connect slots_30.io.wakeup_ports[1].valid, issue_slots[30].wakeup_ports[1].valid connect slots_30.io.wakeup_ports[2].bits.poisoned, issue_slots[30].wakeup_ports[2].bits.poisoned connect slots_30.io.wakeup_ports[2].bits.pdst, issue_slots[30].wakeup_ports[2].bits.pdst connect slots_30.io.wakeup_ports[2].valid, issue_slots[30].wakeup_ports[2].valid connect slots_30.io.wakeup_ports[3].bits.poisoned, issue_slots[30].wakeup_ports[3].bits.poisoned connect slots_30.io.wakeup_ports[3].bits.pdst, issue_slots[30].wakeup_ports[3].bits.pdst connect slots_30.io.wakeup_ports[3].valid, issue_slots[30].wakeup_ports[3].valid connect slots_30.io.wakeup_ports[4].bits.poisoned, issue_slots[30].wakeup_ports[4].bits.poisoned connect slots_30.io.wakeup_ports[4].bits.pdst, issue_slots[30].wakeup_ports[4].bits.pdst connect slots_30.io.wakeup_ports[4].valid, issue_slots[30].wakeup_ports[4].valid connect slots_30.io.wakeup_ports[5].bits.poisoned, issue_slots[30].wakeup_ports[5].bits.poisoned connect slots_30.io.wakeup_ports[5].bits.pdst, issue_slots[30].wakeup_ports[5].bits.pdst connect slots_30.io.wakeup_ports[5].valid, issue_slots[30].wakeup_ports[5].valid connect slots_30.io.wakeup_ports[6].bits.poisoned, issue_slots[30].wakeup_ports[6].bits.poisoned connect slots_30.io.wakeup_ports[6].bits.pdst, issue_slots[30].wakeup_ports[6].bits.pdst connect slots_30.io.wakeup_ports[6].valid, issue_slots[30].wakeup_ports[6].valid connect slots_30.io.ldspec_miss, issue_slots[30].ldspec_miss connect slots_30.io.clear, issue_slots[30].clear connect slots_30.io.kill, issue_slots[30].kill connect slots_30.io.brupdate.b2.target_offset, issue_slots[30].brupdate.b2.target_offset connect slots_30.io.brupdate.b2.jalr_target, issue_slots[30].brupdate.b2.jalr_target connect slots_30.io.brupdate.b2.pc_sel, issue_slots[30].brupdate.b2.pc_sel connect slots_30.io.brupdate.b2.cfi_type, issue_slots[30].brupdate.b2.cfi_type connect slots_30.io.brupdate.b2.taken, issue_slots[30].brupdate.b2.taken connect slots_30.io.brupdate.b2.mispredict, issue_slots[30].brupdate.b2.mispredict connect slots_30.io.brupdate.b2.valid, issue_slots[30].brupdate.b2.valid connect slots_30.io.brupdate.b2.uop.debug_tsrc, issue_slots[30].brupdate.b2.uop.debug_tsrc connect slots_30.io.brupdate.b2.uop.debug_fsrc, issue_slots[30].brupdate.b2.uop.debug_fsrc connect slots_30.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[30].brupdate.b2.uop.bp_xcpt_if connect slots_30.io.brupdate.b2.uop.bp_debug_if, issue_slots[30].brupdate.b2.uop.bp_debug_if connect slots_30.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[30].brupdate.b2.uop.xcpt_ma_if connect slots_30.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[30].brupdate.b2.uop.xcpt_ae_if connect slots_30.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[30].brupdate.b2.uop.xcpt_pf_if connect slots_30.io.brupdate.b2.uop.fp_single, issue_slots[30].brupdate.b2.uop.fp_single connect slots_30.io.brupdate.b2.uop.fp_val, issue_slots[30].brupdate.b2.uop.fp_val connect slots_30.io.brupdate.b2.uop.frs3_en, issue_slots[30].brupdate.b2.uop.frs3_en connect slots_30.io.brupdate.b2.uop.lrs2_rtype, issue_slots[30].brupdate.b2.uop.lrs2_rtype connect slots_30.io.brupdate.b2.uop.lrs1_rtype, issue_slots[30].brupdate.b2.uop.lrs1_rtype connect slots_30.io.brupdate.b2.uop.dst_rtype, issue_slots[30].brupdate.b2.uop.dst_rtype connect slots_30.io.brupdate.b2.uop.ldst_val, issue_slots[30].brupdate.b2.uop.ldst_val connect slots_30.io.brupdate.b2.uop.lrs3, issue_slots[30].brupdate.b2.uop.lrs3 connect slots_30.io.brupdate.b2.uop.lrs2, issue_slots[30].brupdate.b2.uop.lrs2 connect slots_30.io.brupdate.b2.uop.lrs1, issue_slots[30].brupdate.b2.uop.lrs1 connect slots_30.io.brupdate.b2.uop.ldst, issue_slots[30].brupdate.b2.uop.ldst connect slots_30.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[30].brupdate.b2.uop.ldst_is_rs1 connect slots_30.io.brupdate.b2.uop.flush_on_commit, issue_slots[30].brupdate.b2.uop.flush_on_commit connect slots_30.io.brupdate.b2.uop.is_unique, issue_slots[30].brupdate.b2.uop.is_unique connect slots_30.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[30].brupdate.b2.uop.is_sys_pc2epc connect slots_30.io.brupdate.b2.uop.uses_stq, issue_slots[30].brupdate.b2.uop.uses_stq connect slots_30.io.brupdate.b2.uop.uses_ldq, issue_slots[30].brupdate.b2.uop.uses_ldq connect slots_30.io.brupdate.b2.uop.is_amo, issue_slots[30].brupdate.b2.uop.is_amo connect slots_30.io.brupdate.b2.uop.is_fencei, issue_slots[30].brupdate.b2.uop.is_fencei connect slots_30.io.brupdate.b2.uop.is_fence, issue_slots[30].brupdate.b2.uop.is_fence connect slots_30.io.brupdate.b2.uop.mem_signed, issue_slots[30].brupdate.b2.uop.mem_signed connect slots_30.io.brupdate.b2.uop.mem_size, issue_slots[30].brupdate.b2.uop.mem_size connect slots_30.io.brupdate.b2.uop.mem_cmd, issue_slots[30].brupdate.b2.uop.mem_cmd connect slots_30.io.brupdate.b2.uop.bypassable, issue_slots[30].brupdate.b2.uop.bypassable connect slots_30.io.brupdate.b2.uop.exc_cause, issue_slots[30].brupdate.b2.uop.exc_cause connect slots_30.io.brupdate.b2.uop.exception, issue_slots[30].brupdate.b2.uop.exception connect slots_30.io.brupdate.b2.uop.stale_pdst, issue_slots[30].brupdate.b2.uop.stale_pdst connect slots_30.io.brupdate.b2.uop.ppred_busy, issue_slots[30].brupdate.b2.uop.ppred_busy connect slots_30.io.brupdate.b2.uop.prs3_busy, issue_slots[30].brupdate.b2.uop.prs3_busy connect slots_30.io.brupdate.b2.uop.prs2_busy, issue_slots[30].brupdate.b2.uop.prs2_busy connect slots_30.io.brupdate.b2.uop.prs1_busy, issue_slots[30].brupdate.b2.uop.prs1_busy connect slots_30.io.brupdate.b2.uop.ppred, issue_slots[30].brupdate.b2.uop.ppred connect slots_30.io.brupdate.b2.uop.prs3, issue_slots[30].brupdate.b2.uop.prs3 connect slots_30.io.brupdate.b2.uop.prs2, issue_slots[30].brupdate.b2.uop.prs2 connect slots_30.io.brupdate.b2.uop.prs1, issue_slots[30].brupdate.b2.uop.prs1 connect slots_30.io.brupdate.b2.uop.pdst, issue_slots[30].brupdate.b2.uop.pdst connect slots_30.io.brupdate.b2.uop.rxq_idx, issue_slots[30].brupdate.b2.uop.rxq_idx connect slots_30.io.brupdate.b2.uop.stq_idx, issue_slots[30].brupdate.b2.uop.stq_idx connect slots_30.io.brupdate.b2.uop.ldq_idx, issue_slots[30].brupdate.b2.uop.ldq_idx connect slots_30.io.brupdate.b2.uop.rob_idx, issue_slots[30].brupdate.b2.uop.rob_idx connect slots_30.io.brupdate.b2.uop.csr_addr, issue_slots[30].brupdate.b2.uop.csr_addr connect slots_30.io.brupdate.b2.uop.imm_packed, issue_slots[30].brupdate.b2.uop.imm_packed connect slots_30.io.brupdate.b2.uop.taken, issue_slots[30].brupdate.b2.uop.taken connect slots_30.io.brupdate.b2.uop.pc_lob, issue_slots[30].brupdate.b2.uop.pc_lob connect slots_30.io.brupdate.b2.uop.edge_inst, issue_slots[30].brupdate.b2.uop.edge_inst connect slots_30.io.brupdate.b2.uop.ftq_idx, issue_slots[30].brupdate.b2.uop.ftq_idx connect slots_30.io.brupdate.b2.uop.br_tag, issue_slots[30].brupdate.b2.uop.br_tag connect slots_30.io.brupdate.b2.uop.br_mask, issue_slots[30].brupdate.b2.uop.br_mask connect slots_30.io.brupdate.b2.uop.is_sfb, issue_slots[30].brupdate.b2.uop.is_sfb connect slots_30.io.brupdate.b2.uop.is_jal, issue_slots[30].brupdate.b2.uop.is_jal connect slots_30.io.brupdate.b2.uop.is_jalr, issue_slots[30].brupdate.b2.uop.is_jalr connect slots_30.io.brupdate.b2.uop.is_br, issue_slots[30].brupdate.b2.uop.is_br connect slots_30.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[30].brupdate.b2.uop.iw_p2_poisoned connect slots_30.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[30].brupdate.b2.uop.iw_p1_poisoned connect slots_30.io.brupdate.b2.uop.iw_state, issue_slots[30].brupdate.b2.uop.iw_state connect slots_30.io.brupdate.b2.uop.ctrl.is_std, issue_slots[30].brupdate.b2.uop.ctrl.is_std connect slots_30.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[30].brupdate.b2.uop.ctrl.is_sta connect slots_30.io.brupdate.b2.uop.ctrl.is_load, issue_slots[30].brupdate.b2.uop.ctrl.is_load connect slots_30.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[30].brupdate.b2.uop.ctrl.csr_cmd connect slots_30.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[30].brupdate.b2.uop.ctrl.fcn_dw connect slots_30.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[30].brupdate.b2.uop.ctrl.op_fcn connect slots_30.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[30].brupdate.b2.uop.ctrl.imm_sel connect slots_30.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[30].brupdate.b2.uop.ctrl.op2_sel connect slots_30.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[30].brupdate.b2.uop.ctrl.op1_sel connect slots_30.io.brupdate.b2.uop.ctrl.br_type, issue_slots[30].brupdate.b2.uop.ctrl.br_type connect slots_30.io.brupdate.b2.uop.fu_code, issue_slots[30].brupdate.b2.uop.fu_code connect slots_30.io.brupdate.b2.uop.iq_type, issue_slots[30].brupdate.b2.uop.iq_type connect slots_30.io.brupdate.b2.uop.debug_pc, issue_slots[30].brupdate.b2.uop.debug_pc connect slots_30.io.brupdate.b2.uop.is_rvc, issue_slots[30].brupdate.b2.uop.is_rvc connect slots_30.io.brupdate.b2.uop.debug_inst, issue_slots[30].brupdate.b2.uop.debug_inst connect slots_30.io.brupdate.b2.uop.inst, issue_slots[30].brupdate.b2.uop.inst connect slots_30.io.brupdate.b2.uop.uopc, issue_slots[30].brupdate.b2.uop.uopc connect slots_30.io.brupdate.b1.mispredict_mask, issue_slots[30].brupdate.b1.mispredict_mask connect slots_30.io.brupdate.b1.resolve_mask, issue_slots[30].brupdate.b1.resolve_mask connect slots_30.io.grant, issue_slots[30].grant connect issue_slots[30].request_hp, slots_30.io.request_hp connect issue_slots[30].request, slots_30.io.request connect issue_slots[30].will_be_valid, slots_30.io.will_be_valid connect issue_slots[30].valid, slots_30.io.valid connect issue_slots[31].debug.state, slots_31.io.debug.state connect issue_slots[31].debug.ppred, slots_31.io.debug.ppred connect issue_slots[31].debug.p3, slots_31.io.debug.p3 connect issue_slots[31].debug.p2, slots_31.io.debug.p2 connect issue_slots[31].debug.p1, slots_31.io.debug.p1 connect issue_slots[31].uop.debug_tsrc, slots_31.io.uop.debug_tsrc connect issue_slots[31].uop.debug_fsrc, slots_31.io.uop.debug_fsrc connect issue_slots[31].uop.bp_xcpt_if, slots_31.io.uop.bp_xcpt_if connect issue_slots[31].uop.bp_debug_if, slots_31.io.uop.bp_debug_if connect issue_slots[31].uop.xcpt_ma_if, slots_31.io.uop.xcpt_ma_if connect issue_slots[31].uop.xcpt_ae_if, slots_31.io.uop.xcpt_ae_if connect issue_slots[31].uop.xcpt_pf_if, slots_31.io.uop.xcpt_pf_if connect issue_slots[31].uop.fp_single, slots_31.io.uop.fp_single connect issue_slots[31].uop.fp_val, slots_31.io.uop.fp_val connect issue_slots[31].uop.frs3_en, slots_31.io.uop.frs3_en connect issue_slots[31].uop.lrs2_rtype, slots_31.io.uop.lrs2_rtype connect issue_slots[31].uop.lrs1_rtype, slots_31.io.uop.lrs1_rtype connect issue_slots[31].uop.dst_rtype, slots_31.io.uop.dst_rtype connect issue_slots[31].uop.ldst_val, slots_31.io.uop.ldst_val connect issue_slots[31].uop.lrs3, slots_31.io.uop.lrs3 connect issue_slots[31].uop.lrs2, slots_31.io.uop.lrs2 connect issue_slots[31].uop.lrs1, slots_31.io.uop.lrs1 connect issue_slots[31].uop.ldst, slots_31.io.uop.ldst connect issue_slots[31].uop.ldst_is_rs1, slots_31.io.uop.ldst_is_rs1 connect issue_slots[31].uop.flush_on_commit, slots_31.io.uop.flush_on_commit connect issue_slots[31].uop.is_unique, slots_31.io.uop.is_unique connect issue_slots[31].uop.is_sys_pc2epc, slots_31.io.uop.is_sys_pc2epc connect issue_slots[31].uop.uses_stq, slots_31.io.uop.uses_stq connect issue_slots[31].uop.uses_ldq, slots_31.io.uop.uses_ldq connect issue_slots[31].uop.is_amo, slots_31.io.uop.is_amo connect issue_slots[31].uop.is_fencei, slots_31.io.uop.is_fencei connect issue_slots[31].uop.is_fence, slots_31.io.uop.is_fence connect issue_slots[31].uop.mem_signed, slots_31.io.uop.mem_signed connect issue_slots[31].uop.mem_size, slots_31.io.uop.mem_size connect issue_slots[31].uop.mem_cmd, slots_31.io.uop.mem_cmd connect issue_slots[31].uop.bypassable, slots_31.io.uop.bypassable connect issue_slots[31].uop.exc_cause, slots_31.io.uop.exc_cause connect issue_slots[31].uop.exception, slots_31.io.uop.exception connect issue_slots[31].uop.stale_pdst, slots_31.io.uop.stale_pdst connect issue_slots[31].uop.ppred_busy, slots_31.io.uop.ppred_busy connect issue_slots[31].uop.prs3_busy, slots_31.io.uop.prs3_busy connect issue_slots[31].uop.prs2_busy, slots_31.io.uop.prs2_busy connect issue_slots[31].uop.prs1_busy, slots_31.io.uop.prs1_busy connect issue_slots[31].uop.ppred, slots_31.io.uop.ppred connect issue_slots[31].uop.prs3, slots_31.io.uop.prs3 connect issue_slots[31].uop.prs2, slots_31.io.uop.prs2 connect issue_slots[31].uop.prs1, slots_31.io.uop.prs1 connect issue_slots[31].uop.pdst, slots_31.io.uop.pdst connect issue_slots[31].uop.rxq_idx, slots_31.io.uop.rxq_idx connect issue_slots[31].uop.stq_idx, slots_31.io.uop.stq_idx connect issue_slots[31].uop.ldq_idx, slots_31.io.uop.ldq_idx connect issue_slots[31].uop.rob_idx, slots_31.io.uop.rob_idx connect issue_slots[31].uop.csr_addr, slots_31.io.uop.csr_addr connect issue_slots[31].uop.imm_packed, slots_31.io.uop.imm_packed connect issue_slots[31].uop.taken, slots_31.io.uop.taken connect issue_slots[31].uop.pc_lob, slots_31.io.uop.pc_lob connect issue_slots[31].uop.edge_inst, slots_31.io.uop.edge_inst connect issue_slots[31].uop.ftq_idx, slots_31.io.uop.ftq_idx connect issue_slots[31].uop.br_tag, slots_31.io.uop.br_tag connect issue_slots[31].uop.br_mask, slots_31.io.uop.br_mask connect issue_slots[31].uop.is_sfb, slots_31.io.uop.is_sfb connect issue_slots[31].uop.is_jal, slots_31.io.uop.is_jal connect issue_slots[31].uop.is_jalr, slots_31.io.uop.is_jalr connect issue_slots[31].uop.is_br, slots_31.io.uop.is_br connect issue_slots[31].uop.iw_p2_poisoned, slots_31.io.uop.iw_p2_poisoned connect issue_slots[31].uop.iw_p1_poisoned, slots_31.io.uop.iw_p1_poisoned connect issue_slots[31].uop.iw_state, slots_31.io.uop.iw_state connect issue_slots[31].uop.ctrl.is_std, slots_31.io.uop.ctrl.is_std connect issue_slots[31].uop.ctrl.is_sta, slots_31.io.uop.ctrl.is_sta connect issue_slots[31].uop.ctrl.is_load, slots_31.io.uop.ctrl.is_load connect issue_slots[31].uop.ctrl.csr_cmd, slots_31.io.uop.ctrl.csr_cmd connect issue_slots[31].uop.ctrl.fcn_dw, slots_31.io.uop.ctrl.fcn_dw connect issue_slots[31].uop.ctrl.op_fcn, slots_31.io.uop.ctrl.op_fcn connect issue_slots[31].uop.ctrl.imm_sel, slots_31.io.uop.ctrl.imm_sel connect issue_slots[31].uop.ctrl.op2_sel, slots_31.io.uop.ctrl.op2_sel connect issue_slots[31].uop.ctrl.op1_sel, slots_31.io.uop.ctrl.op1_sel connect issue_slots[31].uop.ctrl.br_type, slots_31.io.uop.ctrl.br_type connect issue_slots[31].uop.fu_code, slots_31.io.uop.fu_code connect issue_slots[31].uop.iq_type, slots_31.io.uop.iq_type connect issue_slots[31].uop.debug_pc, slots_31.io.uop.debug_pc connect issue_slots[31].uop.is_rvc, slots_31.io.uop.is_rvc connect issue_slots[31].uop.debug_inst, slots_31.io.uop.debug_inst connect issue_slots[31].uop.inst, slots_31.io.uop.inst connect issue_slots[31].uop.uopc, slots_31.io.uop.uopc connect issue_slots[31].out_uop.debug_tsrc, slots_31.io.out_uop.debug_tsrc connect issue_slots[31].out_uop.debug_fsrc, slots_31.io.out_uop.debug_fsrc connect issue_slots[31].out_uop.bp_xcpt_if, slots_31.io.out_uop.bp_xcpt_if connect issue_slots[31].out_uop.bp_debug_if, slots_31.io.out_uop.bp_debug_if connect issue_slots[31].out_uop.xcpt_ma_if, slots_31.io.out_uop.xcpt_ma_if connect issue_slots[31].out_uop.xcpt_ae_if, slots_31.io.out_uop.xcpt_ae_if connect issue_slots[31].out_uop.xcpt_pf_if, slots_31.io.out_uop.xcpt_pf_if connect issue_slots[31].out_uop.fp_single, slots_31.io.out_uop.fp_single connect issue_slots[31].out_uop.fp_val, slots_31.io.out_uop.fp_val connect issue_slots[31].out_uop.frs3_en, slots_31.io.out_uop.frs3_en connect issue_slots[31].out_uop.lrs2_rtype, slots_31.io.out_uop.lrs2_rtype connect issue_slots[31].out_uop.lrs1_rtype, slots_31.io.out_uop.lrs1_rtype connect issue_slots[31].out_uop.dst_rtype, slots_31.io.out_uop.dst_rtype connect issue_slots[31].out_uop.ldst_val, slots_31.io.out_uop.ldst_val connect issue_slots[31].out_uop.lrs3, slots_31.io.out_uop.lrs3 connect issue_slots[31].out_uop.lrs2, slots_31.io.out_uop.lrs2 connect issue_slots[31].out_uop.lrs1, slots_31.io.out_uop.lrs1 connect issue_slots[31].out_uop.ldst, slots_31.io.out_uop.ldst connect issue_slots[31].out_uop.ldst_is_rs1, slots_31.io.out_uop.ldst_is_rs1 connect issue_slots[31].out_uop.flush_on_commit, slots_31.io.out_uop.flush_on_commit connect issue_slots[31].out_uop.is_unique, slots_31.io.out_uop.is_unique connect issue_slots[31].out_uop.is_sys_pc2epc, slots_31.io.out_uop.is_sys_pc2epc connect issue_slots[31].out_uop.uses_stq, slots_31.io.out_uop.uses_stq connect issue_slots[31].out_uop.uses_ldq, slots_31.io.out_uop.uses_ldq connect issue_slots[31].out_uop.is_amo, slots_31.io.out_uop.is_amo connect issue_slots[31].out_uop.is_fencei, slots_31.io.out_uop.is_fencei connect issue_slots[31].out_uop.is_fence, slots_31.io.out_uop.is_fence connect issue_slots[31].out_uop.mem_signed, slots_31.io.out_uop.mem_signed connect issue_slots[31].out_uop.mem_size, slots_31.io.out_uop.mem_size connect issue_slots[31].out_uop.mem_cmd, slots_31.io.out_uop.mem_cmd connect issue_slots[31].out_uop.bypassable, slots_31.io.out_uop.bypassable connect issue_slots[31].out_uop.exc_cause, slots_31.io.out_uop.exc_cause connect issue_slots[31].out_uop.exception, slots_31.io.out_uop.exception connect issue_slots[31].out_uop.stale_pdst, slots_31.io.out_uop.stale_pdst connect issue_slots[31].out_uop.ppred_busy, slots_31.io.out_uop.ppred_busy connect issue_slots[31].out_uop.prs3_busy, slots_31.io.out_uop.prs3_busy connect issue_slots[31].out_uop.prs2_busy, slots_31.io.out_uop.prs2_busy connect issue_slots[31].out_uop.prs1_busy, slots_31.io.out_uop.prs1_busy connect issue_slots[31].out_uop.ppred, slots_31.io.out_uop.ppred connect issue_slots[31].out_uop.prs3, slots_31.io.out_uop.prs3 connect issue_slots[31].out_uop.prs2, slots_31.io.out_uop.prs2 connect issue_slots[31].out_uop.prs1, slots_31.io.out_uop.prs1 connect issue_slots[31].out_uop.pdst, slots_31.io.out_uop.pdst connect issue_slots[31].out_uop.rxq_idx, slots_31.io.out_uop.rxq_idx connect issue_slots[31].out_uop.stq_idx, slots_31.io.out_uop.stq_idx connect issue_slots[31].out_uop.ldq_idx, slots_31.io.out_uop.ldq_idx connect issue_slots[31].out_uop.rob_idx, slots_31.io.out_uop.rob_idx connect issue_slots[31].out_uop.csr_addr, slots_31.io.out_uop.csr_addr connect issue_slots[31].out_uop.imm_packed, slots_31.io.out_uop.imm_packed connect issue_slots[31].out_uop.taken, slots_31.io.out_uop.taken connect issue_slots[31].out_uop.pc_lob, slots_31.io.out_uop.pc_lob connect issue_slots[31].out_uop.edge_inst, slots_31.io.out_uop.edge_inst connect issue_slots[31].out_uop.ftq_idx, slots_31.io.out_uop.ftq_idx connect issue_slots[31].out_uop.br_tag, slots_31.io.out_uop.br_tag connect issue_slots[31].out_uop.br_mask, slots_31.io.out_uop.br_mask connect issue_slots[31].out_uop.is_sfb, slots_31.io.out_uop.is_sfb connect issue_slots[31].out_uop.is_jal, slots_31.io.out_uop.is_jal connect issue_slots[31].out_uop.is_jalr, slots_31.io.out_uop.is_jalr connect issue_slots[31].out_uop.is_br, slots_31.io.out_uop.is_br connect issue_slots[31].out_uop.iw_p2_poisoned, slots_31.io.out_uop.iw_p2_poisoned connect issue_slots[31].out_uop.iw_p1_poisoned, slots_31.io.out_uop.iw_p1_poisoned connect issue_slots[31].out_uop.iw_state, slots_31.io.out_uop.iw_state connect issue_slots[31].out_uop.ctrl.is_std, slots_31.io.out_uop.ctrl.is_std connect issue_slots[31].out_uop.ctrl.is_sta, slots_31.io.out_uop.ctrl.is_sta connect issue_slots[31].out_uop.ctrl.is_load, slots_31.io.out_uop.ctrl.is_load connect issue_slots[31].out_uop.ctrl.csr_cmd, slots_31.io.out_uop.ctrl.csr_cmd connect issue_slots[31].out_uop.ctrl.fcn_dw, slots_31.io.out_uop.ctrl.fcn_dw connect issue_slots[31].out_uop.ctrl.op_fcn, slots_31.io.out_uop.ctrl.op_fcn connect issue_slots[31].out_uop.ctrl.imm_sel, slots_31.io.out_uop.ctrl.imm_sel connect issue_slots[31].out_uop.ctrl.op2_sel, slots_31.io.out_uop.ctrl.op2_sel connect issue_slots[31].out_uop.ctrl.op1_sel, slots_31.io.out_uop.ctrl.op1_sel connect issue_slots[31].out_uop.ctrl.br_type, slots_31.io.out_uop.ctrl.br_type connect issue_slots[31].out_uop.fu_code, slots_31.io.out_uop.fu_code connect issue_slots[31].out_uop.iq_type, slots_31.io.out_uop.iq_type connect issue_slots[31].out_uop.debug_pc, slots_31.io.out_uop.debug_pc connect issue_slots[31].out_uop.is_rvc, slots_31.io.out_uop.is_rvc connect issue_slots[31].out_uop.debug_inst, slots_31.io.out_uop.debug_inst connect issue_slots[31].out_uop.inst, slots_31.io.out_uop.inst connect issue_slots[31].out_uop.uopc, slots_31.io.out_uop.uopc connect slots_31.io.in_uop.bits.debug_tsrc, issue_slots[31].in_uop.bits.debug_tsrc connect slots_31.io.in_uop.bits.debug_fsrc, issue_slots[31].in_uop.bits.debug_fsrc connect slots_31.io.in_uop.bits.bp_xcpt_if, issue_slots[31].in_uop.bits.bp_xcpt_if connect slots_31.io.in_uop.bits.bp_debug_if, issue_slots[31].in_uop.bits.bp_debug_if connect slots_31.io.in_uop.bits.xcpt_ma_if, issue_slots[31].in_uop.bits.xcpt_ma_if connect slots_31.io.in_uop.bits.xcpt_ae_if, issue_slots[31].in_uop.bits.xcpt_ae_if connect slots_31.io.in_uop.bits.xcpt_pf_if, issue_slots[31].in_uop.bits.xcpt_pf_if connect slots_31.io.in_uop.bits.fp_single, issue_slots[31].in_uop.bits.fp_single connect slots_31.io.in_uop.bits.fp_val, issue_slots[31].in_uop.bits.fp_val connect slots_31.io.in_uop.bits.frs3_en, issue_slots[31].in_uop.bits.frs3_en connect slots_31.io.in_uop.bits.lrs2_rtype, issue_slots[31].in_uop.bits.lrs2_rtype connect slots_31.io.in_uop.bits.lrs1_rtype, issue_slots[31].in_uop.bits.lrs1_rtype connect slots_31.io.in_uop.bits.dst_rtype, issue_slots[31].in_uop.bits.dst_rtype connect slots_31.io.in_uop.bits.ldst_val, issue_slots[31].in_uop.bits.ldst_val connect slots_31.io.in_uop.bits.lrs3, issue_slots[31].in_uop.bits.lrs3 connect slots_31.io.in_uop.bits.lrs2, issue_slots[31].in_uop.bits.lrs2 connect slots_31.io.in_uop.bits.lrs1, issue_slots[31].in_uop.bits.lrs1 connect slots_31.io.in_uop.bits.ldst, issue_slots[31].in_uop.bits.ldst connect slots_31.io.in_uop.bits.ldst_is_rs1, issue_slots[31].in_uop.bits.ldst_is_rs1 connect slots_31.io.in_uop.bits.flush_on_commit, issue_slots[31].in_uop.bits.flush_on_commit connect slots_31.io.in_uop.bits.is_unique, issue_slots[31].in_uop.bits.is_unique connect slots_31.io.in_uop.bits.is_sys_pc2epc, issue_slots[31].in_uop.bits.is_sys_pc2epc connect slots_31.io.in_uop.bits.uses_stq, issue_slots[31].in_uop.bits.uses_stq connect slots_31.io.in_uop.bits.uses_ldq, issue_slots[31].in_uop.bits.uses_ldq connect slots_31.io.in_uop.bits.is_amo, issue_slots[31].in_uop.bits.is_amo connect slots_31.io.in_uop.bits.is_fencei, issue_slots[31].in_uop.bits.is_fencei connect slots_31.io.in_uop.bits.is_fence, issue_slots[31].in_uop.bits.is_fence connect slots_31.io.in_uop.bits.mem_signed, issue_slots[31].in_uop.bits.mem_signed connect slots_31.io.in_uop.bits.mem_size, issue_slots[31].in_uop.bits.mem_size connect slots_31.io.in_uop.bits.mem_cmd, issue_slots[31].in_uop.bits.mem_cmd connect slots_31.io.in_uop.bits.bypassable, issue_slots[31].in_uop.bits.bypassable connect slots_31.io.in_uop.bits.exc_cause, issue_slots[31].in_uop.bits.exc_cause connect slots_31.io.in_uop.bits.exception, issue_slots[31].in_uop.bits.exception connect slots_31.io.in_uop.bits.stale_pdst, issue_slots[31].in_uop.bits.stale_pdst connect slots_31.io.in_uop.bits.ppred_busy, issue_slots[31].in_uop.bits.ppred_busy connect slots_31.io.in_uop.bits.prs3_busy, issue_slots[31].in_uop.bits.prs3_busy connect slots_31.io.in_uop.bits.prs2_busy, issue_slots[31].in_uop.bits.prs2_busy connect slots_31.io.in_uop.bits.prs1_busy, issue_slots[31].in_uop.bits.prs1_busy connect slots_31.io.in_uop.bits.ppred, issue_slots[31].in_uop.bits.ppred connect slots_31.io.in_uop.bits.prs3, issue_slots[31].in_uop.bits.prs3 connect slots_31.io.in_uop.bits.prs2, issue_slots[31].in_uop.bits.prs2 connect slots_31.io.in_uop.bits.prs1, issue_slots[31].in_uop.bits.prs1 connect slots_31.io.in_uop.bits.pdst, issue_slots[31].in_uop.bits.pdst connect slots_31.io.in_uop.bits.rxq_idx, issue_slots[31].in_uop.bits.rxq_idx connect slots_31.io.in_uop.bits.stq_idx, issue_slots[31].in_uop.bits.stq_idx connect slots_31.io.in_uop.bits.ldq_idx, issue_slots[31].in_uop.bits.ldq_idx connect slots_31.io.in_uop.bits.rob_idx, issue_slots[31].in_uop.bits.rob_idx connect slots_31.io.in_uop.bits.csr_addr, issue_slots[31].in_uop.bits.csr_addr connect slots_31.io.in_uop.bits.imm_packed, issue_slots[31].in_uop.bits.imm_packed connect slots_31.io.in_uop.bits.taken, issue_slots[31].in_uop.bits.taken connect slots_31.io.in_uop.bits.pc_lob, issue_slots[31].in_uop.bits.pc_lob connect slots_31.io.in_uop.bits.edge_inst, issue_slots[31].in_uop.bits.edge_inst connect slots_31.io.in_uop.bits.ftq_idx, issue_slots[31].in_uop.bits.ftq_idx connect slots_31.io.in_uop.bits.br_tag, issue_slots[31].in_uop.bits.br_tag connect slots_31.io.in_uop.bits.br_mask, issue_slots[31].in_uop.bits.br_mask connect slots_31.io.in_uop.bits.is_sfb, issue_slots[31].in_uop.bits.is_sfb connect slots_31.io.in_uop.bits.is_jal, issue_slots[31].in_uop.bits.is_jal connect slots_31.io.in_uop.bits.is_jalr, issue_slots[31].in_uop.bits.is_jalr connect slots_31.io.in_uop.bits.is_br, issue_slots[31].in_uop.bits.is_br connect slots_31.io.in_uop.bits.iw_p2_poisoned, issue_slots[31].in_uop.bits.iw_p2_poisoned connect slots_31.io.in_uop.bits.iw_p1_poisoned, issue_slots[31].in_uop.bits.iw_p1_poisoned connect slots_31.io.in_uop.bits.iw_state, issue_slots[31].in_uop.bits.iw_state connect slots_31.io.in_uop.bits.ctrl.is_std, issue_slots[31].in_uop.bits.ctrl.is_std connect slots_31.io.in_uop.bits.ctrl.is_sta, issue_slots[31].in_uop.bits.ctrl.is_sta connect slots_31.io.in_uop.bits.ctrl.is_load, issue_slots[31].in_uop.bits.ctrl.is_load connect slots_31.io.in_uop.bits.ctrl.csr_cmd, issue_slots[31].in_uop.bits.ctrl.csr_cmd connect slots_31.io.in_uop.bits.ctrl.fcn_dw, issue_slots[31].in_uop.bits.ctrl.fcn_dw connect slots_31.io.in_uop.bits.ctrl.op_fcn, issue_slots[31].in_uop.bits.ctrl.op_fcn connect slots_31.io.in_uop.bits.ctrl.imm_sel, issue_slots[31].in_uop.bits.ctrl.imm_sel connect slots_31.io.in_uop.bits.ctrl.op2_sel, issue_slots[31].in_uop.bits.ctrl.op2_sel connect slots_31.io.in_uop.bits.ctrl.op1_sel, issue_slots[31].in_uop.bits.ctrl.op1_sel connect slots_31.io.in_uop.bits.ctrl.br_type, issue_slots[31].in_uop.bits.ctrl.br_type connect slots_31.io.in_uop.bits.fu_code, issue_slots[31].in_uop.bits.fu_code connect slots_31.io.in_uop.bits.iq_type, issue_slots[31].in_uop.bits.iq_type connect slots_31.io.in_uop.bits.debug_pc, issue_slots[31].in_uop.bits.debug_pc connect slots_31.io.in_uop.bits.is_rvc, issue_slots[31].in_uop.bits.is_rvc connect slots_31.io.in_uop.bits.debug_inst, issue_slots[31].in_uop.bits.debug_inst connect slots_31.io.in_uop.bits.inst, issue_slots[31].in_uop.bits.inst connect slots_31.io.in_uop.bits.uopc, issue_slots[31].in_uop.bits.uopc connect slots_31.io.in_uop.valid, issue_slots[31].in_uop.valid connect slots_31.io.spec_ld_wakeup[0].bits, issue_slots[31].spec_ld_wakeup[0].bits connect slots_31.io.spec_ld_wakeup[0].valid, issue_slots[31].spec_ld_wakeup[0].valid connect slots_31.io.pred_wakeup_port.bits, issue_slots[31].pred_wakeup_port.bits connect slots_31.io.pred_wakeup_port.valid, issue_slots[31].pred_wakeup_port.valid connect slots_31.io.wakeup_ports[0].bits.poisoned, issue_slots[31].wakeup_ports[0].bits.poisoned connect slots_31.io.wakeup_ports[0].bits.pdst, issue_slots[31].wakeup_ports[0].bits.pdst connect slots_31.io.wakeup_ports[0].valid, issue_slots[31].wakeup_ports[0].valid connect slots_31.io.wakeup_ports[1].bits.poisoned, issue_slots[31].wakeup_ports[1].bits.poisoned connect slots_31.io.wakeup_ports[1].bits.pdst, issue_slots[31].wakeup_ports[1].bits.pdst connect slots_31.io.wakeup_ports[1].valid, issue_slots[31].wakeup_ports[1].valid connect slots_31.io.wakeup_ports[2].bits.poisoned, issue_slots[31].wakeup_ports[2].bits.poisoned connect slots_31.io.wakeup_ports[2].bits.pdst, issue_slots[31].wakeup_ports[2].bits.pdst connect slots_31.io.wakeup_ports[2].valid, issue_slots[31].wakeup_ports[2].valid connect slots_31.io.wakeup_ports[3].bits.poisoned, issue_slots[31].wakeup_ports[3].bits.poisoned connect slots_31.io.wakeup_ports[3].bits.pdst, issue_slots[31].wakeup_ports[3].bits.pdst connect slots_31.io.wakeup_ports[3].valid, issue_slots[31].wakeup_ports[3].valid connect slots_31.io.wakeup_ports[4].bits.poisoned, issue_slots[31].wakeup_ports[4].bits.poisoned connect slots_31.io.wakeup_ports[4].bits.pdst, issue_slots[31].wakeup_ports[4].bits.pdst connect slots_31.io.wakeup_ports[4].valid, issue_slots[31].wakeup_ports[4].valid connect slots_31.io.wakeup_ports[5].bits.poisoned, issue_slots[31].wakeup_ports[5].bits.poisoned connect slots_31.io.wakeup_ports[5].bits.pdst, issue_slots[31].wakeup_ports[5].bits.pdst connect slots_31.io.wakeup_ports[5].valid, issue_slots[31].wakeup_ports[5].valid connect slots_31.io.wakeup_ports[6].bits.poisoned, issue_slots[31].wakeup_ports[6].bits.poisoned connect slots_31.io.wakeup_ports[6].bits.pdst, issue_slots[31].wakeup_ports[6].bits.pdst connect slots_31.io.wakeup_ports[6].valid, issue_slots[31].wakeup_ports[6].valid connect slots_31.io.ldspec_miss, issue_slots[31].ldspec_miss connect slots_31.io.clear, issue_slots[31].clear connect slots_31.io.kill, issue_slots[31].kill connect slots_31.io.brupdate.b2.target_offset, issue_slots[31].brupdate.b2.target_offset connect slots_31.io.brupdate.b2.jalr_target, issue_slots[31].brupdate.b2.jalr_target connect slots_31.io.brupdate.b2.pc_sel, issue_slots[31].brupdate.b2.pc_sel connect slots_31.io.brupdate.b2.cfi_type, issue_slots[31].brupdate.b2.cfi_type connect slots_31.io.brupdate.b2.taken, issue_slots[31].brupdate.b2.taken connect slots_31.io.brupdate.b2.mispredict, issue_slots[31].brupdate.b2.mispredict connect slots_31.io.brupdate.b2.valid, issue_slots[31].brupdate.b2.valid connect slots_31.io.brupdate.b2.uop.debug_tsrc, issue_slots[31].brupdate.b2.uop.debug_tsrc connect slots_31.io.brupdate.b2.uop.debug_fsrc, issue_slots[31].brupdate.b2.uop.debug_fsrc connect slots_31.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[31].brupdate.b2.uop.bp_xcpt_if connect slots_31.io.brupdate.b2.uop.bp_debug_if, issue_slots[31].brupdate.b2.uop.bp_debug_if connect slots_31.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[31].brupdate.b2.uop.xcpt_ma_if connect slots_31.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[31].brupdate.b2.uop.xcpt_ae_if connect slots_31.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[31].brupdate.b2.uop.xcpt_pf_if connect slots_31.io.brupdate.b2.uop.fp_single, issue_slots[31].brupdate.b2.uop.fp_single connect slots_31.io.brupdate.b2.uop.fp_val, issue_slots[31].brupdate.b2.uop.fp_val connect slots_31.io.brupdate.b2.uop.frs3_en, issue_slots[31].brupdate.b2.uop.frs3_en connect slots_31.io.brupdate.b2.uop.lrs2_rtype, issue_slots[31].brupdate.b2.uop.lrs2_rtype connect slots_31.io.brupdate.b2.uop.lrs1_rtype, issue_slots[31].brupdate.b2.uop.lrs1_rtype connect slots_31.io.brupdate.b2.uop.dst_rtype, issue_slots[31].brupdate.b2.uop.dst_rtype connect slots_31.io.brupdate.b2.uop.ldst_val, issue_slots[31].brupdate.b2.uop.ldst_val connect slots_31.io.brupdate.b2.uop.lrs3, issue_slots[31].brupdate.b2.uop.lrs3 connect slots_31.io.brupdate.b2.uop.lrs2, issue_slots[31].brupdate.b2.uop.lrs2 connect slots_31.io.brupdate.b2.uop.lrs1, issue_slots[31].brupdate.b2.uop.lrs1 connect slots_31.io.brupdate.b2.uop.ldst, issue_slots[31].brupdate.b2.uop.ldst connect slots_31.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[31].brupdate.b2.uop.ldst_is_rs1 connect slots_31.io.brupdate.b2.uop.flush_on_commit, issue_slots[31].brupdate.b2.uop.flush_on_commit connect slots_31.io.brupdate.b2.uop.is_unique, issue_slots[31].brupdate.b2.uop.is_unique connect slots_31.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[31].brupdate.b2.uop.is_sys_pc2epc connect slots_31.io.brupdate.b2.uop.uses_stq, issue_slots[31].brupdate.b2.uop.uses_stq connect slots_31.io.brupdate.b2.uop.uses_ldq, issue_slots[31].brupdate.b2.uop.uses_ldq connect slots_31.io.brupdate.b2.uop.is_amo, issue_slots[31].brupdate.b2.uop.is_amo connect slots_31.io.brupdate.b2.uop.is_fencei, issue_slots[31].brupdate.b2.uop.is_fencei connect slots_31.io.brupdate.b2.uop.is_fence, issue_slots[31].brupdate.b2.uop.is_fence connect slots_31.io.brupdate.b2.uop.mem_signed, issue_slots[31].brupdate.b2.uop.mem_signed connect slots_31.io.brupdate.b2.uop.mem_size, issue_slots[31].brupdate.b2.uop.mem_size connect slots_31.io.brupdate.b2.uop.mem_cmd, issue_slots[31].brupdate.b2.uop.mem_cmd connect slots_31.io.brupdate.b2.uop.bypassable, issue_slots[31].brupdate.b2.uop.bypassable connect slots_31.io.brupdate.b2.uop.exc_cause, issue_slots[31].brupdate.b2.uop.exc_cause connect slots_31.io.brupdate.b2.uop.exception, issue_slots[31].brupdate.b2.uop.exception connect slots_31.io.brupdate.b2.uop.stale_pdst, issue_slots[31].brupdate.b2.uop.stale_pdst connect slots_31.io.brupdate.b2.uop.ppred_busy, issue_slots[31].brupdate.b2.uop.ppred_busy connect slots_31.io.brupdate.b2.uop.prs3_busy, issue_slots[31].brupdate.b2.uop.prs3_busy connect slots_31.io.brupdate.b2.uop.prs2_busy, issue_slots[31].brupdate.b2.uop.prs2_busy connect slots_31.io.brupdate.b2.uop.prs1_busy, issue_slots[31].brupdate.b2.uop.prs1_busy connect slots_31.io.brupdate.b2.uop.ppred, issue_slots[31].brupdate.b2.uop.ppred connect slots_31.io.brupdate.b2.uop.prs3, issue_slots[31].brupdate.b2.uop.prs3 connect slots_31.io.brupdate.b2.uop.prs2, issue_slots[31].brupdate.b2.uop.prs2 connect slots_31.io.brupdate.b2.uop.prs1, issue_slots[31].brupdate.b2.uop.prs1 connect slots_31.io.brupdate.b2.uop.pdst, issue_slots[31].brupdate.b2.uop.pdst connect slots_31.io.brupdate.b2.uop.rxq_idx, issue_slots[31].brupdate.b2.uop.rxq_idx connect slots_31.io.brupdate.b2.uop.stq_idx, issue_slots[31].brupdate.b2.uop.stq_idx connect slots_31.io.brupdate.b2.uop.ldq_idx, issue_slots[31].brupdate.b2.uop.ldq_idx connect slots_31.io.brupdate.b2.uop.rob_idx, issue_slots[31].brupdate.b2.uop.rob_idx connect slots_31.io.brupdate.b2.uop.csr_addr, issue_slots[31].brupdate.b2.uop.csr_addr connect slots_31.io.brupdate.b2.uop.imm_packed, issue_slots[31].brupdate.b2.uop.imm_packed connect slots_31.io.brupdate.b2.uop.taken, issue_slots[31].brupdate.b2.uop.taken connect slots_31.io.brupdate.b2.uop.pc_lob, issue_slots[31].brupdate.b2.uop.pc_lob connect slots_31.io.brupdate.b2.uop.edge_inst, issue_slots[31].brupdate.b2.uop.edge_inst connect slots_31.io.brupdate.b2.uop.ftq_idx, issue_slots[31].brupdate.b2.uop.ftq_idx connect slots_31.io.brupdate.b2.uop.br_tag, issue_slots[31].brupdate.b2.uop.br_tag connect slots_31.io.brupdate.b2.uop.br_mask, issue_slots[31].brupdate.b2.uop.br_mask connect slots_31.io.brupdate.b2.uop.is_sfb, issue_slots[31].brupdate.b2.uop.is_sfb connect slots_31.io.brupdate.b2.uop.is_jal, issue_slots[31].brupdate.b2.uop.is_jal connect slots_31.io.brupdate.b2.uop.is_jalr, issue_slots[31].brupdate.b2.uop.is_jalr connect slots_31.io.brupdate.b2.uop.is_br, issue_slots[31].brupdate.b2.uop.is_br connect slots_31.io.brupdate.b2.uop.iw_p2_poisoned, issue_slots[31].brupdate.b2.uop.iw_p2_poisoned connect slots_31.io.brupdate.b2.uop.iw_p1_poisoned, issue_slots[31].brupdate.b2.uop.iw_p1_poisoned connect slots_31.io.brupdate.b2.uop.iw_state, issue_slots[31].brupdate.b2.uop.iw_state connect slots_31.io.brupdate.b2.uop.ctrl.is_std, issue_slots[31].brupdate.b2.uop.ctrl.is_std connect slots_31.io.brupdate.b2.uop.ctrl.is_sta, issue_slots[31].brupdate.b2.uop.ctrl.is_sta connect slots_31.io.brupdate.b2.uop.ctrl.is_load, issue_slots[31].brupdate.b2.uop.ctrl.is_load connect slots_31.io.brupdate.b2.uop.ctrl.csr_cmd, issue_slots[31].brupdate.b2.uop.ctrl.csr_cmd connect slots_31.io.brupdate.b2.uop.ctrl.fcn_dw, issue_slots[31].brupdate.b2.uop.ctrl.fcn_dw connect slots_31.io.brupdate.b2.uop.ctrl.op_fcn, issue_slots[31].brupdate.b2.uop.ctrl.op_fcn connect slots_31.io.brupdate.b2.uop.ctrl.imm_sel, issue_slots[31].brupdate.b2.uop.ctrl.imm_sel connect slots_31.io.brupdate.b2.uop.ctrl.op2_sel, issue_slots[31].brupdate.b2.uop.ctrl.op2_sel connect slots_31.io.brupdate.b2.uop.ctrl.op1_sel, issue_slots[31].brupdate.b2.uop.ctrl.op1_sel connect slots_31.io.brupdate.b2.uop.ctrl.br_type, issue_slots[31].brupdate.b2.uop.ctrl.br_type connect slots_31.io.brupdate.b2.uop.fu_code, issue_slots[31].brupdate.b2.uop.fu_code connect slots_31.io.brupdate.b2.uop.iq_type, issue_slots[31].brupdate.b2.uop.iq_type connect slots_31.io.brupdate.b2.uop.debug_pc, issue_slots[31].brupdate.b2.uop.debug_pc connect slots_31.io.brupdate.b2.uop.is_rvc, issue_slots[31].brupdate.b2.uop.is_rvc connect slots_31.io.brupdate.b2.uop.debug_inst, issue_slots[31].brupdate.b2.uop.debug_inst connect slots_31.io.brupdate.b2.uop.inst, issue_slots[31].brupdate.b2.uop.inst connect slots_31.io.brupdate.b2.uop.uopc, issue_slots[31].brupdate.b2.uop.uopc connect slots_31.io.brupdate.b1.mispredict_mask, issue_slots[31].brupdate.b1.mispredict_mask connect slots_31.io.brupdate.b1.resolve_mask, issue_slots[31].brupdate.b1.resolve_mask connect slots_31.io.grant, issue_slots[31].grant connect issue_slots[31].request_hp, slots_31.io.request_hp connect issue_slots[31].request, slots_31.io.request connect issue_slots[31].will_be_valid, slots_31.io.will_be_valid connect issue_slots[31].valid, slots_31.io.valid connect issue_slots[0].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[0].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[0].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[0].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[0].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[0].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[0].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[0].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[0].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[0].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[0].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[0].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[0].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[0].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[0].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[0].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[0].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[0].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[0].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[0].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[0].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[0].ldspec_miss, io.ld_miss connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[0].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[0].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[0].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[0].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[0].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[0].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[0].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[0].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[0].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[0].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[0].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[0].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[0].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[0].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[0].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[0].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[0].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[0].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[0].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[0].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[0].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[0].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[0].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[0].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[0].kill, io.flush_pipeline connect issue_slots[1].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[1].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[1].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[1].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[1].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[1].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[1].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[1].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[1].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[1].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[1].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[1].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[1].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[1].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[1].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[1].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[1].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[1].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[1].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[1].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[1].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[1].ldspec_miss, io.ld_miss connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[1].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[1].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[1].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[1].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[1].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[1].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[1].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[1].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[1].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[1].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[1].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[1].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[1].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[1].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[1].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[1].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[1].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[1].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[1].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[1].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[1].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[1].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[1].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[1].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[1].kill, io.flush_pipeline connect issue_slots[2].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[2].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[2].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[2].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[2].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[2].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[2].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[2].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[2].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[2].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[2].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[2].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[2].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[2].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[2].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[2].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[2].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[2].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[2].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[2].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[2].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[2].ldspec_miss, io.ld_miss connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[2].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[2].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[2].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[2].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[2].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[2].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[2].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[2].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[2].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[2].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[2].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[2].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[2].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[2].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[2].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[2].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[2].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[2].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[2].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[2].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[2].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[2].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[2].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[2].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[2].kill, io.flush_pipeline connect issue_slots[3].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[3].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[3].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[3].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[3].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[3].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[3].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[3].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[3].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[3].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[3].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[3].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[3].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[3].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[3].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[3].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[3].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[3].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[3].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[3].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[3].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[3].ldspec_miss, io.ld_miss connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[3].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[3].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[3].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[3].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[3].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[3].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[3].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[3].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[3].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[3].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[3].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[3].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[3].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[3].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[3].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[3].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[3].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[3].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[3].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[3].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[3].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[3].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[3].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[3].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[3].kill, io.flush_pipeline connect issue_slots[4].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[4].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[4].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[4].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[4].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[4].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[4].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[4].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[4].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[4].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[4].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[4].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[4].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[4].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[4].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[4].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[4].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[4].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[4].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[4].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[4].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[4].ldspec_miss, io.ld_miss connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[4].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[4].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[4].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[4].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[4].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[4].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[4].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[4].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[4].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[4].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[4].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[4].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[4].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[4].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[4].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[4].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[4].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[4].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[4].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[4].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[4].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[4].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[4].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[4].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[4].kill, io.flush_pipeline connect issue_slots[5].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[5].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[5].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[5].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[5].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[5].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[5].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[5].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[5].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[5].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[5].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[5].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[5].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[5].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[5].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[5].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[5].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[5].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[5].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[5].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[5].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[5].ldspec_miss, io.ld_miss connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[5].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[5].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[5].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[5].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[5].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[5].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[5].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[5].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[5].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[5].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[5].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[5].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[5].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[5].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[5].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[5].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[5].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[5].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[5].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[5].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[5].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[5].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[5].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[5].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[5].kill, io.flush_pipeline connect issue_slots[6].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[6].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[6].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[6].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[6].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[6].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[6].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[6].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[6].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[6].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[6].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[6].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[6].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[6].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[6].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[6].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[6].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[6].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[6].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[6].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[6].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[6].ldspec_miss, io.ld_miss connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[6].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[6].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[6].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[6].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[6].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[6].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[6].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[6].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[6].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[6].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[6].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[6].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[6].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[6].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[6].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[6].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[6].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[6].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[6].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[6].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[6].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[6].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[6].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[6].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[6].kill, io.flush_pipeline connect issue_slots[7].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[7].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[7].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[7].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[7].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[7].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[7].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[7].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[7].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[7].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[7].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[7].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[7].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[7].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[7].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[7].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[7].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[7].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[7].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[7].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[7].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[7].ldspec_miss, io.ld_miss connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[7].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[7].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[7].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[7].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[7].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[7].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[7].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[7].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[7].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[7].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[7].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[7].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[7].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[7].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[7].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[7].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[7].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[7].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[7].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[7].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[7].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[7].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[7].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[7].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[7].kill, io.flush_pipeline connect issue_slots[8].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[8].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[8].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[8].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[8].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[8].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[8].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[8].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[8].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[8].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[8].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[8].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[8].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[8].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[8].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[8].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[8].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[8].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[8].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[8].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[8].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[8].ldspec_miss, io.ld_miss connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[8].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[8].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[8].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[8].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[8].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[8].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[8].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[8].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[8].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[8].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[8].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[8].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[8].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[8].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[8].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[8].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[8].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[8].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[8].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[8].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[8].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[8].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[8].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[8].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[8].kill, io.flush_pipeline connect issue_slots[9].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[9].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[9].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[9].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[9].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[9].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[9].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[9].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[9].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[9].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[9].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[9].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[9].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[9].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[9].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[9].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[9].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[9].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[9].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[9].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[9].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[9].ldspec_miss, io.ld_miss connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[9].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[9].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[9].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[9].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[9].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[9].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[9].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[9].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[9].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[9].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[9].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[9].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[9].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[9].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[9].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[9].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[9].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[9].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[9].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[9].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[9].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[9].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[9].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[9].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[9].kill, io.flush_pipeline connect issue_slots[10].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[10].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[10].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[10].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[10].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[10].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[10].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[10].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[10].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[10].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[10].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[10].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[10].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[10].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[10].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[10].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[10].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[10].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[10].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[10].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[10].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[10].ldspec_miss, io.ld_miss connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[10].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[10].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[10].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[10].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[10].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[10].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[10].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[10].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[10].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[10].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[10].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[10].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[10].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[10].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[10].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[10].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[10].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[10].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[10].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[10].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[10].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[10].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[10].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[10].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[10].kill, io.flush_pipeline connect issue_slots[11].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[11].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[11].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[11].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[11].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[11].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[11].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[11].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[11].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[11].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[11].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[11].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[11].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[11].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[11].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[11].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[11].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[11].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[11].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[11].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[11].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[11].ldspec_miss, io.ld_miss connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[11].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[11].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[11].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[11].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[11].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[11].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[11].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[11].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[11].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[11].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[11].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[11].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[11].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[11].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[11].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[11].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[11].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[11].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[11].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[11].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[11].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[11].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[11].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[11].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[11].kill, io.flush_pipeline connect issue_slots[12].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[12].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[12].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[12].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[12].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[12].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[12].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[12].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[12].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[12].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[12].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[12].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[12].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[12].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[12].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[12].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[12].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[12].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[12].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[12].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[12].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[12].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[12].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[12].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[12].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[12].ldspec_miss, io.ld_miss connect issue_slots[12].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[12].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[12].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[12].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[12].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[12].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[12].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[12].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[12].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[12].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[12].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[12].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[12].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[12].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[12].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[12].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[12].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[12].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[12].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[12].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[12].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[12].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[12].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[12].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[12].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[12].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[12].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[12].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[12].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[12].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[12].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[12].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[12].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[12].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[12].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[12].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[12].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[12].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[12].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[12].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[12].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[12].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[12].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[12].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[12].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[12].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[12].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[12].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[12].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[12].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[12].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[12].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[12].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[12].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[12].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[12].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[12].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[12].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[12].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[12].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[12].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[12].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[12].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[12].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[12].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[12].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[12].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[12].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[12].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[12].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[12].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[12].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[12].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[12].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[12].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[12].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[12].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[12].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[12].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[12].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[12].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[12].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[12].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[12].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[12].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[12].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[12].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[12].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[12].kill, io.flush_pipeline connect issue_slots[13].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[13].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[13].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[13].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[13].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[13].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[13].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[13].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[13].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[13].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[13].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[13].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[13].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[13].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[13].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[13].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[13].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[13].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[13].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[13].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[13].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[13].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[13].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[13].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[13].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[13].ldspec_miss, io.ld_miss connect issue_slots[13].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[13].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[13].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[13].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[13].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[13].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[13].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[13].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[13].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[13].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[13].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[13].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[13].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[13].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[13].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[13].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[13].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[13].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[13].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[13].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[13].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[13].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[13].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[13].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[13].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[13].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[13].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[13].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[13].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[13].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[13].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[13].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[13].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[13].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[13].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[13].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[13].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[13].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[13].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[13].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[13].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[13].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[13].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[13].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[13].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[13].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[13].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[13].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[13].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[13].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[13].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[13].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[13].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[13].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[13].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[13].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[13].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[13].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[13].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[13].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[13].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[13].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[13].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[13].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[13].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[13].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[13].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[13].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[13].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[13].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[13].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[13].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[13].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[13].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[13].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[13].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[13].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[13].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[13].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[13].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[13].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[13].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[13].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[13].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[13].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[13].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[13].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[13].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[13].kill, io.flush_pipeline connect issue_slots[14].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[14].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[14].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[14].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[14].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[14].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[14].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[14].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[14].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[14].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[14].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[14].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[14].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[14].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[14].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[14].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[14].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[14].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[14].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[14].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[14].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[14].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[14].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[14].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[14].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[14].ldspec_miss, io.ld_miss connect issue_slots[14].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[14].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[14].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[14].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[14].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[14].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[14].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[14].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[14].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[14].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[14].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[14].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[14].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[14].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[14].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[14].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[14].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[14].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[14].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[14].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[14].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[14].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[14].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[14].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[14].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[14].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[14].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[14].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[14].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[14].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[14].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[14].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[14].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[14].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[14].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[14].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[14].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[14].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[14].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[14].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[14].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[14].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[14].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[14].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[14].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[14].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[14].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[14].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[14].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[14].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[14].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[14].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[14].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[14].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[14].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[14].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[14].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[14].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[14].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[14].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[14].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[14].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[14].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[14].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[14].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[14].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[14].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[14].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[14].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[14].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[14].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[14].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[14].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[14].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[14].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[14].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[14].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[14].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[14].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[14].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[14].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[14].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[14].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[14].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[14].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[14].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[14].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[14].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[14].kill, io.flush_pipeline connect issue_slots[15].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[15].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[15].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[15].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[15].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[15].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[15].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[15].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[15].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[15].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[15].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[15].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[15].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[15].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[15].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[15].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[15].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[15].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[15].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[15].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[15].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[15].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[15].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[15].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[15].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[15].ldspec_miss, io.ld_miss connect issue_slots[15].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[15].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[15].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[15].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[15].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[15].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[15].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[15].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[15].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[15].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[15].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[15].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[15].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[15].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[15].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[15].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[15].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[15].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[15].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[15].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[15].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[15].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[15].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[15].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[15].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[15].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[15].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[15].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[15].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[15].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[15].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[15].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[15].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[15].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[15].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[15].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[15].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[15].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[15].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[15].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[15].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[15].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[15].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[15].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[15].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[15].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[15].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[15].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[15].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[15].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[15].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[15].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[15].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[15].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[15].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[15].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[15].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[15].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[15].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[15].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[15].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[15].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[15].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[15].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[15].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[15].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[15].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[15].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[15].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[15].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[15].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[15].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[15].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[15].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[15].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[15].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[15].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[15].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[15].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[15].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[15].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[15].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[15].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[15].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[15].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[15].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[15].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[15].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[15].kill, io.flush_pipeline connect issue_slots[16].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[16].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[16].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[16].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[16].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[16].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[16].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[16].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[16].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[16].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[16].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[16].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[16].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[16].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[16].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[16].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[16].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[16].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[16].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[16].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[16].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[16].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[16].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[16].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[16].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[16].ldspec_miss, io.ld_miss connect issue_slots[16].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[16].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[16].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[16].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[16].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[16].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[16].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[16].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[16].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[16].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[16].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[16].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[16].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[16].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[16].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[16].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[16].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[16].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[16].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[16].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[16].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[16].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[16].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[16].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[16].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[16].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[16].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[16].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[16].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[16].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[16].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[16].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[16].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[16].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[16].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[16].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[16].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[16].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[16].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[16].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[16].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[16].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[16].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[16].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[16].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[16].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[16].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[16].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[16].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[16].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[16].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[16].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[16].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[16].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[16].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[16].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[16].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[16].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[16].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[16].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[16].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[16].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[16].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[16].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[16].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[16].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[16].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[16].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[16].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[16].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[16].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[16].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[16].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[16].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[16].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[16].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[16].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[16].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[16].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[16].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[16].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[16].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[16].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[16].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[16].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[16].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[16].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[16].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[16].kill, io.flush_pipeline connect issue_slots[17].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[17].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[17].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[17].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[17].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[17].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[17].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[17].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[17].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[17].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[17].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[17].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[17].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[17].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[17].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[17].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[17].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[17].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[17].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[17].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[17].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[17].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[17].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[17].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[17].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[17].ldspec_miss, io.ld_miss connect issue_slots[17].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[17].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[17].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[17].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[17].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[17].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[17].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[17].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[17].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[17].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[17].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[17].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[17].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[17].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[17].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[17].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[17].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[17].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[17].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[17].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[17].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[17].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[17].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[17].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[17].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[17].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[17].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[17].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[17].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[17].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[17].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[17].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[17].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[17].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[17].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[17].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[17].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[17].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[17].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[17].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[17].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[17].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[17].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[17].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[17].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[17].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[17].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[17].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[17].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[17].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[17].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[17].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[17].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[17].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[17].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[17].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[17].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[17].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[17].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[17].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[17].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[17].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[17].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[17].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[17].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[17].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[17].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[17].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[17].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[17].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[17].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[17].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[17].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[17].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[17].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[17].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[17].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[17].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[17].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[17].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[17].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[17].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[17].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[17].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[17].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[17].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[17].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[17].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[17].kill, io.flush_pipeline connect issue_slots[18].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[18].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[18].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[18].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[18].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[18].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[18].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[18].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[18].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[18].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[18].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[18].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[18].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[18].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[18].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[18].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[18].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[18].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[18].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[18].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[18].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[18].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[18].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[18].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[18].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[18].ldspec_miss, io.ld_miss connect issue_slots[18].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[18].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[18].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[18].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[18].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[18].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[18].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[18].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[18].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[18].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[18].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[18].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[18].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[18].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[18].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[18].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[18].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[18].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[18].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[18].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[18].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[18].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[18].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[18].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[18].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[18].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[18].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[18].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[18].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[18].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[18].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[18].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[18].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[18].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[18].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[18].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[18].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[18].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[18].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[18].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[18].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[18].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[18].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[18].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[18].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[18].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[18].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[18].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[18].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[18].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[18].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[18].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[18].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[18].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[18].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[18].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[18].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[18].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[18].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[18].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[18].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[18].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[18].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[18].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[18].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[18].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[18].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[18].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[18].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[18].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[18].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[18].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[18].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[18].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[18].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[18].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[18].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[18].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[18].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[18].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[18].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[18].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[18].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[18].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[18].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[18].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[18].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[18].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[18].kill, io.flush_pipeline connect issue_slots[19].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[19].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[19].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[19].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[19].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[19].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[19].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[19].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[19].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[19].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[19].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[19].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[19].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[19].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[19].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[19].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[19].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[19].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[19].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[19].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[19].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[19].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[19].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[19].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[19].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[19].ldspec_miss, io.ld_miss connect issue_slots[19].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[19].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[19].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[19].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[19].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[19].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[19].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[19].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[19].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[19].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[19].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[19].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[19].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[19].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[19].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[19].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[19].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[19].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[19].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[19].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[19].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[19].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[19].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[19].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[19].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[19].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[19].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[19].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[19].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[19].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[19].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[19].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[19].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[19].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[19].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[19].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[19].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[19].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[19].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[19].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[19].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[19].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[19].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[19].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[19].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[19].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[19].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[19].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[19].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[19].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[19].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[19].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[19].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[19].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[19].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[19].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[19].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[19].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[19].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[19].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[19].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[19].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[19].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[19].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[19].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[19].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[19].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[19].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[19].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[19].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[19].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[19].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[19].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[19].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[19].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[19].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[19].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[19].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[19].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[19].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[19].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[19].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[19].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[19].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[19].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[19].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[19].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[19].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[19].kill, io.flush_pipeline connect issue_slots[20].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[20].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[20].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[20].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[20].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[20].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[20].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[20].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[20].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[20].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[20].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[20].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[20].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[20].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[20].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[20].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[20].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[20].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[20].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[20].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[20].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[20].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[20].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[20].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[20].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[20].ldspec_miss, io.ld_miss connect issue_slots[20].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[20].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[20].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[20].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[20].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[20].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[20].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[20].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[20].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[20].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[20].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[20].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[20].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[20].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[20].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[20].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[20].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[20].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[20].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[20].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[20].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[20].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[20].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[20].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[20].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[20].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[20].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[20].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[20].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[20].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[20].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[20].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[20].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[20].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[20].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[20].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[20].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[20].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[20].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[20].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[20].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[20].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[20].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[20].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[20].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[20].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[20].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[20].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[20].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[20].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[20].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[20].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[20].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[20].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[20].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[20].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[20].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[20].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[20].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[20].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[20].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[20].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[20].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[20].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[20].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[20].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[20].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[20].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[20].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[20].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[20].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[20].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[20].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[20].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[20].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[20].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[20].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[20].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[20].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[20].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[20].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[20].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[20].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[20].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[20].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[20].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[20].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[20].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[20].kill, io.flush_pipeline connect issue_slots[21].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[21].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[21].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[21].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[21].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[21].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[21].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[21].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[21].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[21].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[21].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[21].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[21].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[21].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[21].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[21].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[21].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[21].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[21].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[21].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[21].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[21].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[21].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[21].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[21].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[21].ldspec_miss, io.ld_miss connect issue_slots[21].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[21].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[21].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[21].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[21].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[21].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[21].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[21].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[21].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[21].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[21].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[21].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[21].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[21].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[21].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[21].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[21].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[21].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[21].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[21].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[21].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[21].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[21].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[21].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[21].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[21].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[21].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[21].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[21].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[21].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[21].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[21].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[21].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[21].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[21].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[21].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[21].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[21].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[21].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[21].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[21].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[21].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[21].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[21].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[21].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[21].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[21].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[21].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[21].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[21].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[21].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[21].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[21].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[21].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[21].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[21].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[21].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[21].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[21].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[21].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[21].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[21].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[21].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[21].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[21].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[21].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[21].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[21].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[21].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[21].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[21].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[21].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[21].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[21].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[21].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[21].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[21].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[21].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[21].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[21].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[21].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[21].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[21].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[21].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[21].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[21].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[21].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[21].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[21].kill, io.flush_pipeline connect issue_slots[22].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[22].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[22].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[22].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[22].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[22].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[22].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[22].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[22].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[22].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[22].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[22].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[22].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[22].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[22].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[22].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[22].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[22].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[22].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[22].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[22].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[22].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[22].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[22].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[22].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[22].ldspec_miss, io.ld_miss connect issue_slots[22].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[22].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[22].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[22].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[22].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[22].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[22].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[22].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[22].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[22].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[22].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[22].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[22].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[22].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[22].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[22].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[22].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[22].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[22].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[22].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[22].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[22].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[22].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[22].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[22].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[22].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[22].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[22].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[22].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[22].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[22].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[22].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[22].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[22].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[22].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[22].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[22].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[22].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[22].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[22].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[22].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[22].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[22].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[22].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[22].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[22].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[22].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[22].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[22].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[22].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[22].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[22].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[22].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[22].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[22].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[22].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[22].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[22].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[22].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[22].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[22].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[22].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[22].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[22].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[22].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[22].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[22].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[22].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[22].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[22].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[22].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[22].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[22].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[22].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[22].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[22].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[22].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[22].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[22].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[22].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[22].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[22].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[22].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[22].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[22].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[22].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[22].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[22].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[22].kill, io.flush_pipeline connect issue_slots[23].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[23].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[23].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[23].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[23].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[23].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[23].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[23].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[23].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[23].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[23].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[23].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[23].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[23].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[23].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[23].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[23].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[23].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[23].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[23].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[23].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[23].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[23].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[23].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[23].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[23].ldspec_miss, io.ld_miss connect issue_slots[23].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[23].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[23].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[23].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[23].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[23].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[23].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[23].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[23].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[23].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[23].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[23].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[23].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[23].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[23].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[23].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[23].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[23].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[23].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[23].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[23].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[23].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[23].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[23].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[23].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[23].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[23].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[23].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[23].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[23].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[23].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[23].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[23].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[23].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[23].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[23].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[23].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[23].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[23].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[23].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[23].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[23].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[23].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[23].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[23].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[23].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[23].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[23].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[23].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[23].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[23].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[23].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[23].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[23].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[23].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[23].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[23].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[23].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[23].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[23].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[23].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[23].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[23].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[23].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[23].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[23].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[23].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[23].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[23].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[23].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[23].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[23].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[23].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[23].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[23].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[23].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[23].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[23].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[23].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[23].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[23].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[23].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[23].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[23].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[23].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[23].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[23].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[23].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[23].kill, io.flush_pipeline connect issue_slots[24].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[24].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[24].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[24].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[24].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[24].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[24].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[24].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[24].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[24].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[24].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[24].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[24].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[24].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[24].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[24].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[24].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[24].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[24].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[24].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[24].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[24].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[24].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[24].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[24].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[24].ldspec_miss, io.ld_miss connect issue_slots[24].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[24].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[24].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[24].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[24].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[24].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[24].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[24].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[24].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[24].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[24].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[24].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[24].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[24].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[24].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[24].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[24].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[24].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[24].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[24].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[24].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[24].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[24].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[24].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[24].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[24].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[24].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[24].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[24].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[24].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[24].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[24].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[24].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[24].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[24].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[24].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[24].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[24].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[24].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[24].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[24].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[24].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[24].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[24].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[24].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[24].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[24].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[24].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[24].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[24].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[24].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[24].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[24].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[24].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[24].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[24].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[24].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[24].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[24].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[24].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[24].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[24].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[24].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[24].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[24].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[24].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[24].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[24].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[24].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[24].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[24].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[24].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[24].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[24].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[24].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[24].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[24].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[24].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[24].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[24].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[24].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[24].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[24].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[24].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[24].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[24].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[24].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[24].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[24].kill, io.flush_pipeline connect issue_slots[25].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[25].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[25].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[25].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[25].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[25].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[25].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[25].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[25].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[25].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[25].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[25].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[25].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[25].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[25].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[25].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[25].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[25].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[25].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[25].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[25].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[25].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[25].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[25].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[25].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[25].ldspec_miss, io.ld_miss connect issue_slots[25].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[25].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[25].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[25].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[25].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[25].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[25].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[25].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[25].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[25].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[25].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[25].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[25].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[25].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[25].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[25].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[25].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[25].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[25].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[25].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[25].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[25].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[25].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[25].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[25].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[25].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[25].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[25].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[25].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[25].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[25].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[25].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[25].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[25].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[25].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[25].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[25].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[25].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[25].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[25].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[25].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[25].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[25].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[25].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[25].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[25].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[25].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[25].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[25].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[25].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[25].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[25].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[25].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[25].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[25].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[25].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[25].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[25].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[25].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[25].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[25].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[25].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[25].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[25].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[25].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[25].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[25].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[25].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[25].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[25].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[25].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[25].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[25].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[25].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[25].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[25].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[25].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[25].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[25].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[25].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[25].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[25].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[25].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[25].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[25].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[25].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[25].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[25].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[25].kill, io.flush_pipeline connect issue_slots[26].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[26].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[26].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[26].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[26].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[26].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[26].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[26].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[26].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[26].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[26].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[26].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[26].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[26].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[26].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[26].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[26].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[26].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[26].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[26].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[26].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[26].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[26].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[26].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[26].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[26].ldspec_miss, io.ld_miss connect issue_slots[26].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[26].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[26].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[26].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[26].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[26].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[26].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[26].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[26].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[26].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[26].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[26].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[26].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[26].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[26].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[26].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[26].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[26].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[26].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[26].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[26].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[26].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[26].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[26].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[26].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[26].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[26].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[26].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[26].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[26].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[26].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[26].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[26].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[26].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[26].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[26].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[26].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[26].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[26].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[26].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[26].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[26].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[26].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[26].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[26].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[26].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[26].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[26].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[26].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[26].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[26].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[26].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[26].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[26].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[26].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[26].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[26].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[26].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[26].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[26].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[26].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[26].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[26].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[26].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[26].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[26].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[26].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[26].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[26].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[26].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[26].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[26].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[26].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[26].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[26].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[26].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[26].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[26].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[26].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[26].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[26].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[26].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[26].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[26].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[26].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[26].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[26].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[26].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[26].kill, io.flush_pipeline connect issue_slots[27].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[27].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[27].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[27].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[27].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[27].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[27].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[27].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[27].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[27].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[27].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[27].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[27].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[27].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[27].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[27].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[27].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[27].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[27].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[27].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[27].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[27].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[27].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[27].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[27].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[27].ldspec_miss, io.ld_miss connect issue_slots[27].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[27].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[27].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[27].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[27].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[27].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[27].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[27].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[27].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[27].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[27].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[27].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[27].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[27].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[27].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[27].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[27].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[27].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[27].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[27].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[27].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[27].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[27].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[27].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[27].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[27].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[27].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[27].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[27].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[27].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[27].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[27].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[27].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[27].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[27].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[27].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[27].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[27].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[27].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[27].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[27].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[27].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[27].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[27].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[27].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[27].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[27].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[27].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[27].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[27].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[27].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[27].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[27].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[27].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[27].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[27].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[27].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[27].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[27].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[27].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[27].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[27].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[27].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[27].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[27].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[27].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[27].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[27].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[27].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[27].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[27].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[27].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[27].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[27].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[27].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[27].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[27].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[27].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[27].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[27].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[27].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[27].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[27].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[27].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[27].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[27].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[27].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[27].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[27].kill, io.flush_pipeline connect issue_slots[28].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[28].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[28].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[28].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[28].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[28].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[28].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[28].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[28].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[28].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[28].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[28].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[28].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[28].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[28].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[28].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[28].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[28].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[28].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[28].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[28].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[28].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[28].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[28].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[28].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[28].ldspec_miss, io.ld_miss connect issue_slots[28].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[28].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[28].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[28].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[28].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[28].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[28].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[28].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[28].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[28].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[28].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[28].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[28].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[28].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[28].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[28].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[28].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[28].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[28].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[28].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[28].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[28].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[28].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[28].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[28].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[28].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[28].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[28].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[28].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[28].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[28].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[28].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[28].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[28].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[28].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[28].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[28].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[28].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[28].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[28].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[28].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[28].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[28].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[28].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[28].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[28].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[28].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[28].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[28].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[28].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[28].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[28].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[28].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[28].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[28].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[28].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[28].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[28].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[28].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[28].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[28].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[28].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[28].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[28].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[28].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[28].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[28].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[28].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[28].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[28].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[28].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[28].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[28].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[28].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[28].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[28].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[28].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[28].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[28].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[28].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[28].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[28].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[28].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[28].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[28].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[28].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[28].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[28].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[28].kill, io.flush_pipeline connect issue_slots[29].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[29].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[29].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[29].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[29].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[29].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[29].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[29].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[29].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[29].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[29].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[29].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[29].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[29].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[29].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[29].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[29].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[29].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[29].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[29].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[29].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[29].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[29].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[29].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[29].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[29].ldspec_miss, io.ld_miss connect issue_slots[29].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[29].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[29].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[29].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[29].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[29].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[29].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[29].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[29].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[29].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[29].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[29].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[29].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[29].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[29].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[29].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[29].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[29].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[29].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[29].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[29].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[29].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[29].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[29].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[29].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[29].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[29].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[29].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[29].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[29].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[29].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[29].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[29].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[29].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[29].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[29].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[29].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[29].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[29].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[29].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[29].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[29].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[29].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[29].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[29].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[29].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[29].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[29].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[29].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[29].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[29].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[29].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[29].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[29].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[29].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[29].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[29].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[29].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[29].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[29].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[29].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[29].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[29].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[29].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[29].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[29].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[29].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[29].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[29].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[29].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[29].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[29].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[29].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[29].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[29].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[29].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[29].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[29].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[29].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[29].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[29].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[29].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[29].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[29].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[29].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[29].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[29].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[29].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[29].kill, io.flush_pipeline connect issue_slots[30].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[30].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[30].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[30].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[30].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[30].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[30].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[30].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[30].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[30].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[30].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[30].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[30].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[30].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[30].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[30].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[30].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[30].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[30].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[30].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[30].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[30].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[30].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[30].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[30].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[30].ldspec_miss, io.ld_miss connect issue_slots[30].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[30].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[30].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[30].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[30].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[30].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[30].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[30].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[30].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[30].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[30].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[30].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[30].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[30].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[30].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[30].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[30].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[30].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[30].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[30].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[30].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[30].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[30].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[30].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[30].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[30].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[30].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[30].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[30].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[30].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[30].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[30].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[30].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[30].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[30].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[30].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[30].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[30].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[30].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[30].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[30].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[30].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[30].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[30].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[30].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[30].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[30].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[30].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[30].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[30].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[30].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[30].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[30].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[30].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[30].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[30].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[30].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[30].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[30].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[30].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[30].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[30].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[30].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[30].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[30].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[30].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[30].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[30].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[30].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[30].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[30].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[30].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[30].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[30].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[30].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[30].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[30].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[30].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[30].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[30].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[30].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[30].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[30].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[30].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[30].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[30].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[30].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[30].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[30].kill, io.flush_pipeline connect issue_slots[31].wakeup_ports[0].bits.poisoned, io.wakeup_ports[0].bits.poisoned connect issue_slots[31].wakeup_ports[0].bits.pdst, io.wakeup_ports[0].bits.pdst connect issue_slots[31].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[31].wakeup_ports[1].bits.poisoned, io.wakeup_ports[1].bits.poisoned connect issue_slots[31].wakeup_ports[1].bits.pdst, io.wakeup_ports[1].bits.pdst connect issue_slots[31].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[31].wakeup_ports[2].bits.poisoned, io.wakeup_ports[2].bits.poisoned connect issue_slots[31].wakeup_ports[2].bits.pdst, io.wakeup_ports[2].bits.pdst connect issue_slots[31].wakeup_ports[2].valid, io.wakeup_ports[2].valid connect issue_slots[31].wakeup_ports[3].bits.poisoned, io.wakeup_ports[3].bits.poisoned connect issue_slots[31].wakeup_ports[3].bits.pdst, io.wakeup_ports[3].bits.pdst connect issue_slots[31].wakeup_ports[3].valid, io.wakeup_ports[3].valid connect issue_slots[31].wakeup_ports[4].bits.poisoned, io.wakeup_ports[4].bits.poisoned connect issue_slots[31].wakeup_ports[4].bits.pdst, io.wakeup_ports[4].bits.pdst connect issue_slots[31].wakeup_ports[4].valid, io.wakeup_ports[4].valid connect issue_slots[31].wakeup_ports[5].bits.poisoned, io.wakeup_ports[5].bits.poisoned connect issue_slots[31].wakeup_ports[5].bits.pdst, io.wakeup_ports[5].bits.pdst connect issue_slots[31].wakeup_ports[5].valid, io.wakeup_ports[5].valid connect issue_slots[31].wakeup_ports[6].bits.poisoned, io.wakeup_ports[6].bits.poisoned connect issue_slots[31].wakeup_ports[6].bits.pdst, io.wakeup_ports[6].bits.pdst connect issue_slots[31].wakeup_ports[6].valid, io.wakeup_ports[6].valid connect issue_slots[31].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[31].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[31].spec_ld_wakeup[0].bits, io.spec_ld_wakeup[0].bits connect issue_slots[31].spec_ld_wakeup[0].valid, io.spec_ld_wakeup[0].valid connect issue_slots[31].ldspec_miss, io.ld_miss connect issue_slots[31].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[31].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[31].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[31].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[31].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[31].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[31].brupdate.b2.valid, io.brupdate.b2.valid connect issue_slots[31].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[31].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[31].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[31].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[31].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[31].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[31].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[31].brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect issue_slots[31].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[31].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[31].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[31].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[31].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[31].brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect issue_slots[31].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[31].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[31].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[31].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[31].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[31].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[31].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[31].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[31].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[31].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[31].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[31].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[31].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[31].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[31].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[31].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[31].brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect issue_slots[31].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[31].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[31].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[31].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[31].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[31].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[31].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[31].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[31].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[31].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[31].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[31].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[31].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[31].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[31].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[31].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[31].brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect issue_slots[31].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[31].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[31].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[31].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[31].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[31].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[31].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[31].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[31].brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect issue_slots[31].brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect issue_slots[31].brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect issue_slots[31].brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect issue_slots[31].brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect issue_slots[31].brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect issue_slots[31].brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect issue_slots[31].brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect issue_slots[31].brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect issue_slots[31].brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect issue_slots[31].brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect issue_slots[31].brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect issue_slots[31].brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect issue_slots[31].brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect issue_slots[31].brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect issue_slots[31].brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect issue_slots[31].brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect issue_slots[31].brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect issue_slots[31].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[31].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[31].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[31].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[31].brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect issue_slots[31].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[31].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[31].kill, io.flush_pipeline node _io_event_empty_T = or(issue_slots[0].valid, issue_slots[1].valid) node _io_event_empty_T_1 = or(_io_event_empty_T, issue_slots[2].valid) node _io_event_empty_T_2 = or(_io_event_empty_T_1, issue_slots[3].valid) node _io_event_empty_T_3 = or(_io_event_empty_T_2, issue_slots[4].valid) node _io_event_empty_T_4 = or(_io_event_empty_T_3, issue_slots[5].valid) node _io_event_empty_T_5 = or(_io_event_empty_T_4, issue_slots[6].valid) node _io_event_empty_T_6 = or(_io_event_empty_T_5, issue_slots[7].valid) node _io_event_empty_T_7 = or(_io_event_empty_T_6, issue_slots[8].valid) node _io_event_empty_T_8 = or(_io_event_empty_T_7, issue_slots[9].valid) node _io_event_empty_T_9 = or(_io_event_empty_T_8, issue_slots[10].valid) node _io_event_empty_T_10 = or(_io_event_empty_T_9, issue_slots[11].valid) node _io_event_empty_T_11 = or(_io_event_empty_T_10, issue_slots[12].valid) node _io_event_empty_T_12 = or(_io_event_empty_T_11, issue_slots[13].valid) node _io_event_empty_T_13 = or(_io_event_empty_T_12, issue_slots[14].valid) node _io_event_empty_T_14 = or(_io_event_empty_T_13, issue_slots[15].valid) node _io_event_empty_T_15 = or(_io_event_empty_T_14, issue_slots[16].valid) node _io_event_empty_T_16 = or(_io_event_empty_T_15, issue_slots[17].valid) node _io_event_empty_T_17 = or(_io_event_empty_T_16, issue_slots[18].valid) node _io_event_empty_T_18 = or(_io_event_empty_T_17, issue_slots[19].valid) node _io_event_empty_T_19 = or(_io_event_empty_T_18, issue_slots[20].valid) node _io_event_empty_T_20 = or(_io_event_empty_T_19, issue_slots[21].valid) node _io_event_empty_T_21 = or(_io_event_empty_T_20, issue_slots[22].valid) node _io_event_empty_T_22 = or(_io_event_empty_T_21, issue_slots[23].valid) node _io_event_empty_T_23 = or(_io_event_empty_T_22, issue_slots[24].valid) node _io_event_empty_T_24 = or(_io_event_empty_T_23, issue_slots[25].valid) node _io_event_empty_T_25 = or(_io_event_empty_T_24, issue_slots[26].valid) node _io_event_empty_T_26 = or(_io_event_empty_T_25, issue_slots[27].valid) node _io_event_empty_T_27 = or(_io_event_empty_T_26, issue_slots[28].valid) node _io_event_empty_T_28 = or(_io_event_empty_T_27, issue_slots[29].valid) node _io_event_empty_T_29 = or(_io_event_empty_T_28, issue_slots[30].valid) node _io_event_empty_T_30 = or(_io_event_empty_T_29, issue_slots[31].valid) node _io_event_empty_T_31 = eq(_io_event_empty_T_30, UInt<1>(0h0)) connect io.event_empty, _io_event_empty_T_31 node _count_T = add(slots_0.io.valid, slots_1.io.valid) node _count_T_1 = bits(_count_T, 1, 0) node _count_T_2 = add(slots_2.io.valid, slots_3.io.valid) node _count_T_3 = bits(_count_T_2, 1, 0) node _count_T_4 = add(_count_T_1, _count_T_3) node _count_T_5 = bits(_count_T_4, 2, 0) node _count_T_6 = add(slots_4.io.valid, slots_5.io.valid) node _count_T_7 = bits(_count_T_6, 1, 0) node _count_T_8 = add(slots_6.io.valid, slots_7.io.valid) node _count_T_9 = bits(_count_T_8, 1, 0) node _count_T_10 = add(_count_T_7, _count_T_9) node _count_T_11 = bits(_count_T_10, 2, 0) node _count_T_12 = add(_count_T_5, _count_T_11) node _count_T_13 = bits(_count_T_12, 3, 0) node _count_T_14 = add(slots_8.io.valid, slots_9.io.valid) node _count_T_15 = bits(_count_T_14, 1, 0) node _count_T_16 = add(slots_10.io.valid, slots_11.io.valid) node _count_T_17 = bits(_count_T_16, 1, 0) node _count_T_18 = add(_count_T_15, _count_T_17) node _count_T_19 = bits(_count_T_18, 2, 0) node _count_T_20 = add(slots_12.io.valid, slots_13.io.valid) node _count_T_21 = bits(_count_T_20, 1, 0) node _count_T_22 = add(slots_14.io.valid, slots_15.io.valid) node _count_T_23 = bits(_count_T_22, 1, 0) node _count_T_24 = add(_count_T_21, _count_T_23) node _count_T_25 = bits(_count_T_24, 2, 0) node _count_T_26 = add(_count_T_19, _count_T_25) node _count_T_27 = bits(_count_T_26, 3, 0) node _count_T_28 = add(_count_T_13, _count_T_27) node _count_T_29 = bits(_count_T_28, 4, 0) node _count_T_30 = add(slots_16.io.valid, slots_17.io.valid) node _count_T_31 = bits(_count_T_30, 1, 0) node _count_T_32 = add(slots_18.io.valid, slots_19.io.valid) node _count_T_33 = bits(_count_T_32, 1, 0) node _count_T_34 = add(_count_T_31, _count_T_33) node _count_T_35 = bits(_count_T_34, 2, 0) node _count_T_36 = add(slots_20.io.valid, slots_21.io.valid) node _count_T_37 = bits(_count_T_36, 1, 0) node _count_T_38 = add(slots_22.io.valid, slots_23.io.valid) node _count_T_39 = bits(_count_T_38, 1, 0) node _count_T_40 = add(_count_T_37, _count_T_39) node _count_T_41 = bits(_count_T_40, 2, 0) node _count_T_42 = add(_count_T_35, _count_T_41) node _count_T_43 = bits(_count_T_42, 3, 0) node _count_T_44 = add(slots_24.io.valid, slots_25.io.valid) node _count_T_45 = bits(_count_T_44, 1, 0) node _count_T_46 = add(slots_26.io.valid, slots_27.io.valid) node _count_T_47 = bits(_count_T_46, 1, 0) node _count_T_48 = add(_count_T_45, _count_T_47) node _count_T_49 = bits(_count_T_48, 2, 0) node _count_T_50 = add(slots_28.io.valid, slots_29.io.valid) node _count_T_51 = bits(_count_T_50, 1, 0) node _count_T_52 = add(slots_30.io.valid, slots_31.io.valid) node _count_T_53 = bits(_count_T_52, 1, 0) node _count_T_54 = add(_count_T_51, _count_T_53) node _count_T_55 = bits(_count_T_54, 2, 0) node _count_T_56 = add(_count_T_49, _count_T_55) node _count_T_57 = bits(_count_T_56, 3, 0) node _count_T_58 = add(_count_T_43, _count_T_57) node _count_T_59 = bits(_count_T_58, 4, 0) node _count_T_60 = add(_count_T_29, _count_T_59) node count = bits(_count_T_60, 5, 0) node _T_24 = add(issue_slots[0].grant, issue_slots[1].grant) node _T_25 = bits(_T_24, 1, 0) node _T_26 = add(issue_slots[2].grant, issue_slots[3].grant) node _T_27 = bits(_T_26, 1, 0) node _T_28 = add(_T_25, _T_27) node _T_29 = bits(_T_28, 2, 0) node _T_30 = add(issue_slots[4].grant, issue_slots[5].grant) node _T_31 = bits(_T_30, 1, 0) node _T_32 = add(issue_slots[6].grant, issue_slots[7].grant) node _T_33 = bits(_T_32, 1, 0) node _T_34 = add(_T_31, _T_33) node _T_35 = bits(_T_34, 2, 0) node _T_36 = add(_T_29, _T_35) node _T_37 = bits(_T_36, 3, 0) node _T_38 = add(issue_slots[8].grant, issue_slots[9].grant) node _T_39 = bits(_T_38, 1, 0) node _T_40 = add(issue_slots[10].grant, issue_slots[11].grant) node _T_41 = bits(_T_40, 1, 0) node _T_42 = add(_T_39, _T_41) node _T_43 = bits(_T_42, 2, 0) node _T_44 = add(issue_slots[12].grant, issue_slots[13].grant) node _T_45 = bits(_T_44, 1, 0) node _T_46 = add(issue_slots[14].grant, issue_slots[15].grant) node _T_47 = bits(_T_46, 1, 0) node _T_48 = add(_T_45, _T_47) node _T_49 = bits(_T_48, 2, 0) node _T_50 = add(_T_43, _T_49) node _T_51 = bits(_T_50, 3, 0) node _T_52 = add(_T_37, _T_51) node _T_53 = bits(_T_52, 4, 0) node _T_54 = add(issue_slots[16].grant, issue_slots[17].grant) node _T_55 = bits(_T_54, 1, 0) node _T_56 = add(issue_slots[18].grant, issue_slots[19].grant) node _T_57 = bits(_T_56, 1, 0) node _T_58 = add(_T_55, _T_57) node _T_59 = bits(_T_58, 2, 0) node _T_60 = add(issue_slots[20].grant, issue_slots[21].grant) node _T_61 = bits(_T_60, 1, 0) node _T_62 = add(issue_slots[22].grant, issue_slots[23].grant) node _T_63 = bits(_T_62, 1, 0) node _T_64 = add(_T_61, _T_63) node _T_65 = bits(_T_64, 2, 0) node _T_66 = add(_T_59, _T_65) node _T_67 = bits(_T_66, 3, 0) node _T_68 = add(issue_slots[24].grant, issue_slots[25].grant) node _T_69 = bits(_T_68, 1, 0) node _T_70 = add(issue_slots[26].grant, issue_slots[27].grant) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(_T_69, _T_71) node _T_73 = bits(_T_72, 2, 0) node _T_74 = add(issue_slots[28].grant, issue_slots[29].grant) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(issue_slots[30].grant, issue_slots[31].grant) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_75, _T_77) node _T_79 = bits(_T_78, 2, 0) node _T_80 = add(_T_73, _T_79) node _T_81 = bits(_T_80, 3, 0) node _T_82 = add(_T_67, _T_81) node _T_83 = bits(_T_82, 4, 0) node _T_84 = add(_T_53, _T_83) node _T_85 = bits(_T_84, 5, 0) node _T_86 = leq(_T_85, UInt<2>(0h3)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit.scala:172 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf assert(clock, _T_86, UInt<1>(0h1), "") : assert node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0)) node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0)) node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0)) node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0)) node vacants_12 = eq(issue_slots[12].valid, UInt<1>(0h0)) node vacants_13 = eq(issue_slots[13].valid, UInt<1>(0h0)) node vacants_14 = eq(issue_slots[14].valid, UInt<1>(0h0)) node vacants_15 = eq(issue_slots[15].valid, UInt<1>(0h0)) node vacants_16 = eq(issue_slots[16].valid, UInt<1>(0h0)) node vacants_17 = eq(issue_slots[17].valid, UInt<1>(0h0)) node vacants_18 = eq(issue_slots[18].valid, UInt<1>(0h0)) node vacants_19 = eq(issue_slots[19].valid, UInt<1>(0h0)) node vacants_20 = eq(issue_slots[20].valid, UInt<1>(0h0)) node vacants_21 = eq(issue_slots[21].valid, UInt<1>(0h0)) node vacants_22 = eq(issue_slots[22].valid, UInt<1>(0h0)) node vacants_23 = eq(issue_slots[23].valid, UInt<1>(0h0)) node vacants_24 = eq(issue_slots[24].valid, UInt<1>(0h0)) node vacants_25 = eq(issue_slots[25].valid, UInt<1>(0h0)) node vacants_26 = eq(issue_slots[26].valid, UInt<1>(0h0)) node vacants_27 = eq(issue_slots[27].valid, UInt<1>(0h0)) node vacants_28 = eq(issue_slots[28].valid, UInt<1>(0h0)) node vacants_29 = eq(issue_slots[29].valid, UInt<1>(0h0)) node vacants_30 = eq(issue_slots[30].valid, UInt<1>(0h0)) node vacants_31 = eq(issue_slots[31].valid, UInt<1>(0h0)) node vacants_32 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) node vacants_33 = eq(io.dis_uops[1].valid, UInt<1>(0h0)) node vacants_34 = eq(io.dis_uops[2].valid, UInt<1>(0h0)) wire _WIRE_3 : UInt<3> wire _WIRE_4 : UInt<3> wire _WIRE_5 : UInt<3> wire _WIRE_6 : UInt<3> wire _WIRE_7 : UInt<3> wire _WIRE_8 : UInt<3> wire _WIRE_9 : UInt<3> wire _WIRE_10 : UInt<3> wire _WIRE_11 : UInt<3> wire _WIRE_12 : UInt<3> wire _WIRE_13 : UInt<3> wire _WIRE_14 : UInt<3> wire _WIRE_15 : UInt<3> wire _WIRE_16 : UInt<3> wire _WIRE_17 : UInt<3> wire _WIRE_18 : UInt<3> wire _WIRE_19 : UInt<3> wire _WIRE_20 : UInt<3> wire _WIRE_21 : UInt<3> wire _WIRE_22 : UInt<3> wire _WIRE_23 : UInt<3> wire _WIRE_24 : UInt<3> wire _WIRE_25 : UInt<3> wire _WIRE_26 : UInt<3> wire _WIRE_27 : UInt<3> wire _WIRE_28 : UInt<3> wire _WIRE_29 : UInt<3> wire _WIRE_30 : UInt<3> wire _WIRE_31 : UInt<3> wire _WIRE_32 : UInt<3> wire _WIRE_33 : UInt<3> wire _WIRE_34 : UInt<3> wire _WIRE_35 : UInt<3> wire _WIRE_36 : UInt<3> wire _WIRE_37 : UInt<3> connect _WIRE_3, UInt<1>(0h0) wire next : UInt<3> connect next, _WIRE_3 node _T_90 = eq(_WIRE_3, UInt<1>(0h0)) node _T_91 = and(_T_90, vacants_0) when _T_91 : connect next, UInt<1>(0h1) else : node _T_92 = bits(_WIRE_3, 2, 2) node _T_93 = eq(_T_92, UInt<1>(0h0)) node _T_94 = and(_T_93, vacants_0) when _T_94 : node _next_T = dshl(_WIRE_3, UInt<1>(0h1)) connect next, _next_T connect _WIRE_4, next wire next_1 : UInt<3> connect next_1, _WIRE_4 node _T_95 = eq(_WIRE_4, UInt<1>(0h0)) node _T_96 = and(_T_95, vacants_1) when _T_96 : connect next_1, UInt<1>(0h1) else : node _T_97 = bits(_WIRE_4, 2, 2) node _T_98 = eq(_T_97, UInt<1>(0h0)) node _T_99 = and(_T_98, vacants_1) when _T_99 : node _next_T_1 = dshl(_WIRE_4, UInt<1>(0h1)) connect next_1, _next_T_1 connect _WIRE_5, next_1 wire next_2 : UInt<3> connect next_2, _WIRE_5 node _T_100 = eq(_WIRE_5, UInt<1>(0h0)) node _T_101 = and(_T_100, vacants_2) when _T_101 : connect next_2, UInt<1>(0h1) else : node _T_102 = bits(_WIRE_5, 2, 2) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = and(_T_103, vacants_2) when _T_104 : node _next_T_2 = dshl(_WIRE_5, UInt<1>(0h1)) connect next_2, _next_T_2 connect _WIRE_6, next_2 wire next_3 : UInt<3> connect next_3, _WIRE_6 node _T_105 = eq(_WIRE_6, UInt<1>(0h0)) node _T_106 = and(_T_105, vacants_3) when _T_106 : connect next_3, UInt<1>(0h1) else : node _T_107 = bits(_WIRE_6, 2, 2) node _T_108 = eq(_T_107, UInt<1>(0h0)) node _T_109 = and(_T_108, vacants_3) when _T_109 : node _next_T_3 = dshl(_WIRE_6, UInt<1>(0h1)) connect next_3, _next_T_3 connect _WIRE_7, next_3 wire next_4 : UInt<3> connect next_4, _WIRE_7 node _T_110 = eq(_WIRE_7, UInt<1>(0h0)) node _T_111 = and(_T_110, vacants_4) when _T_111 : connect next_4, UInt<1>(0h1) else : node _T_112 = bits(_WIRE_7, 2, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = and(_T_113, vacants_4) when _T_114 : node _next_T_4 = dshl(_WIRE_7, UInt<1>(0h1)) connect next_4, _next_T_4 connect _WIRE_8, next_4 wire next_5 : UInt<3> connect next_5, _WIRE_8 node _T_115 = eq(_WIRE_8, UInt<1>(0h0)) node _T_116 = and(_T_115, vacants_5) when _T_116 : connect next_5, UInt<1>(0h1) else : node _T_117 = bits(_WIRE_8, 2, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = and(_T_118, vacants_5) when _T_119 : node _next_T_5 = dshl(_WIRE_8, UInt<1>(0h1)) connect next_5, _next_T_5 connect _WIRE_9, next_5 wire next_6 : UInt<3> connect next_6, _WIRE_9 node _T_120 = eq(_WIRE_9, UInt<1>(0h0)) node _T_121 = and(_T_120, vacants_6) when _T_121 : connect next_6, UInt<1>(0h1) else : node _T_122 = bits(_WIRE_9, 2, 2) node _T_123 = eq(_T_122, UInt<1>(0h0)) node _T_124 = and(_T_123, vacants_6) when _T_124 : node _next_T_6 = dshl(_WIRE_9, UInt<1>(0h1)) connect next_6, _next_T_6 connect _WIRE_10, next_6 wire next_7 : UInt<3> connect next_7, _WIRE_10 node _T_125 = eq(_WIRE_10, UInt<1>(0h0)) node _T_126 = and(_T_125, vacants_7) when _T_126 : connect next_7, UInt<1>(0h1) else : node _T_127 = bits(_WIRE_10, 2, 2) node _T_128 = eq(_T_127, UInt<1>(0h0)) node _T_129 = and(_T_128, vacants_7) when _T_129 : node _next_T_7 = dshl(_WIRE_10, UInt<1>(0h1)) connect next_7, _next_T_7 connect _WIRE_11, next_7 wire next_8 : UInt<3> connect next_8, _WIRE_11 node _T_130 = eq(_WIRE_11, UInt<1>(0h0)) node _T_131 = and(_T_130, vacants_8) when _T_131 : connect next_8, UInt<1>(0h1) else : node _T_132 = bits(_WIRE_11, 2, 2) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = and(_T_133, vacants_8) when _T_134 : node _next_T_8 = dshl(_WIRE_11, UInt<1>(0h1)) connect next_8, _next_T_8 connect _WIRE_12, next_8 wire next_9 : UInt<3> connect next_9, _WIRE_12 node _T_135 = eq(_WIRE_12, UInt<1>(0h0)) node _T_136 = and(_T_135, vacants_9) when _T_136 : connect next_9, UInt<1>(0h1) else : node _T_137 = bits(_WIRE_12, 2, 2) node _T_138 = eq(_T_137, UInt<1>(0h0)) node _T_139 = and(_T_138, vacants_9) when _T_139 : node _next_T_9 = dshl(_WIRE_12, UInt<1>(0h1)) connect next_9, _next_T_9 connect _WIRE_13, next_9 wire next_10 : UInt<3> connect next_10, _WIRE_13 node _T_140 = eq(_WIRE_13, UInt<1>(0h0)) node _T_141 = and(_T_140, vacants_10) when _T_141 : connect next_10, UInt<1>(0h1) else : node _T_142 = bits(_WIRE_13, 2, 2) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = and(_T_143, vacants_10) when _T_144 : node _next_T_10 = dshl(_WIRE_13, UInt<1>(0h1)) connect next_10, _next_T_10 connect _WIRE_14, next_10 wire next_11 : UInt<3> connect next_11, _WIRE_14 node _T_145 = eq(_WIRE_14, UInt<1>(0h0)) node _T_146 = and(_T_145, vacants_11) when _T_146 : connect next_11, UInt<1>(0h1) else : node _T_147 = bits(_WIRE_14, 2, 2) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = and(_T_148, vacants_11) when _T_149 : node _next_T_11 = dshl(_WIRE_14, UInt<1>(0h1)) connect next_11, _next_T_11 connect _WIRE_15, next_11 wire next_12 : UInt<3> connect next_12, _WIRE_15 node _T_150 = eq(_WIRE_15, UInt<1>(0h0)) node _T_151 = and(_T_150, vacants_12) when _T_151 : connect next_12, UInt<1>(0h1) else : node _T_152 = bits(_WIRE_15, 2, 2) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = and(_T_153, vacants_12) when _T_154 : node _next_T_12 = dshl(_WIRE_15, UInt<1>(0h1)) connect next_12, _next_T_12 connect _WIRE_16, next_12 wire next_13 : UInt<3> connect next_13, _WIRE_16 node _T_155 = eq(_WIRE_16, UInt<1>(0h0)) node _T_156 = and(_T_155, vacants_13) when _T_156 : connect next_13, UInt<1>(0h1) else : node _T_157 = bits(_WIRE_16, 2, 2) node _T_158 = eq(_T_157, UInt<1>(0h0)) node _T_159 = and(_T_158, vacants_13) when _T_159 : node _next_T_13 = dshl(_WIRE_16, UInt<1>(0h1)) connect next_13, _next_T_13 connect _WIRE_17, next_13 wire next_14 : UInt<3> connect next_14, _WIRE_17 node _T_160 = eq(_WIRE_17, UInt<1>(0h0)) node _T_161 = and(_T_160, vacants_14) when _T_161 : connect next_14, UInt<1>(0h1) else : node _T_162 = bits(_WIRE_17, 2, 2) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = and(_T_163, vacants_14) when _T_164 : node _next_T_14 = dshl(_WIRE_17, UInt<1>(0h1)) connect next_14, _next_T_14 connect _WIRE_18, next_14 wire next_15 : UInt<3> connect next_15, _WIRE_18 node _T_165 = eq(_WIRE_18, UInt<1>(0h0)) node _T_166 = and(_T_165, vacants_15) when _T_166 : connect next_15, UInt<1>(0h1) else : node _T_167 = bits(_WIRE_18, 2, 2) node _T_168 = eq(_T_167, UInt<1>(0h0)) node _T_169 = and(_T_168, vacants_15) when _T_169 : node _next_T_15 = dshl(_WIRE_18, UInt<1>(0h1)) connect next_15, _next_T_15 connect _WIRE_19, next_15 wire next_16 : UInt<3> connect next_16, _WIRE_19 node _T_170 = eq(_WIRE_19, UInt<1>(0h0)) node _T_171 = and(_T_170, vacants_16) when _T_171 : connect next_16, UInt<1>(0h1) else : node _T_172 = bits(_WIRE_19, 2, 2) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = and(_T_173, vacants_16) when _T_174 : node _next_T_16 = dshl(_WIRE_19, UInt<1>(0h1)) connect next_16, _next_T_16 connect _WIRE_20, next_16 wire next_17 : UInt<3> connect next_17, _WIRE_20 node _T_175 = eq(_WIRE_20, UInt<1>(0h0)) node _T_176 = and(_T_175, vacants_17) when _T_176 : connect next_17, UInt<1>(0h1) else : node _T_177 = bits(_WIRE_20, 2, 2) node _T_178 = eq(_T_177, UInt<1>(0h0)) node _T_179 = and(_T_178, vacants_17) when _T_179 : node _next_T_17 = dshl(_WIRE_20, UInt<1>(0h1)) connect next_17, _next_T_17 connect _WIRE_21, next_17 wire next_18 : UInt<3> connect next_18, _WIRE_21 node _T_180 = eq(_WIRE_21, UInt<1>(0h0)) node _T_181 = and(_T_180, vacants_18) when _T_181 : connect next_18, UInt<1>(0h1) else : node _T_182 = bits(_WIRE_21, 2, 2) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = and(_T_183, vacants_18) when _T_184 : node _next_T_18 = dshl(_WIRE_21, UInt<1>(0h1)) connect next_18, _next_T_18 connect _WIRE_22, next_18 wire next_19 : UInt<3> connect next_19, _WIRE_22 node _T_185 = eq(_WIRE_22, UInt<1>(0h0)) node _T_186 = and(_T_185, vacants_19) when _T_186 : connect next_19, UInt<1>(0h1) else : node _T_187 = bits(_WIRE_22, 2, 2) node _T_188 = eq(_T_187, UInt<1>(0h0)) node _T_189 = and(_T_188, vacants_19) when _T_189 : node _next_T_19 = dshl(_WIRE_22, UInt<1>(0h1)) connect next_19, _next_T_19 connect _WIRE_23, next_19 wire next_20 : UInt<3> connect next_20, _WIRE_23 node _T_190 = eq(_WIRE_23, UInt<1>(0h0)) node _T_191 = and(_T_190, vacants_20) when _T_191 : connect next_20, UInt<1>(0h1) else : node _T_192 = bits(_WIRE_23, 2, 2) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = and(_T_193, vacants_20) when _T_194 : node _next_T_20 = dshl(_WIRE_23, UInt<1>(0h1)) connect next_20, _next_T_20 connect _WIRE_24, next_20 wire next_21 : UInt<3> connect next_21, _WIRE_24 node _T_195 = eq(_WIRE_24, UInt<1>(0h0)) node _T_196 = and(_T_195, vacants_21) when _T_196 : connect next_21, UInt<1>(0h1) else : node _T_197 = bits(_WIRE_24, 2, 2) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = and(_T_198, vacants_21) when _T_199 : node _next_T_21 = dshl(_WIRE_24, UInt<1>(0h1)) connect next_21, _next_T_21 connect _WIRE_25, next_21 wire next_22 : UInt<3> connect next_22, _WIRE_25 node _T_200 = eq(_WIRE_25, UInt<1>(0h0)) node _T_201 = and(_T_200, vacants_22) when _T_201 : connect next_22, UInt<1>(0h1) else : node _T_202 = bits(_WIRE_25, 2, 2) node _T_203 = eq(_T_202, UInt<1>(0h0)) node _T_204 = and(_T_203, vacants_22) when _T_204 : node _next_T_22 = dshl(_WIRE_25, UInt<1>(0h1)) connect next_22, _next_T_22 connect _WIRE_26, next_22 wire next_23 : UInt<3> connect next_23, _WIRE_26 node _T_205 = eq(_WIRE_26, UInt<1>(0h0)) node _T_206 = and(_T_205, vacants_23) when _T_206 : connect next_23, UInt<1>(0h1) else : node _T_207 = bits(_WIRE_26, 2, 2) node _T_208 = eq(_T_207, UInt<1>(0h0)) node _T_209 = and(_T_208, vacants_23) when _T_209 : node _next_T_23 = dshl(_WIRE_26, UInt<1>(0h1)) connect next_23, _next_T_23 connect _WIRE_27, next_23 wire next_24 : UInt<3> connect next_24, _WIRE_27 node _T_210 = eq(_WIRE_27, UInt<1>(0h0)) node _T_211 = and(_T_210, vacants_24) when _T_211 : connect next_24, UInt<1>(0h1) else : node _T_212 = bits(_WIRE_27, 2, 2) node _T_213 = eq(_T_212, UInt<1>(0h0)) node _T_214 = and(_T_213, vacants_24) when _T_214 : node _next_T_24 = dshl(_WIRE_27, UInt<1>(0h1)) connect next_24, _next_T_24 connect _WIRE_28, next_24 wire next_25 : UInt<3> connect next_25, _WIRE_28 node _T_215 = eq(_WIRE_28, UInt<1>(0h0)) node _T_216 = and(_T_215, vacants_25) when _T_216 : connect next_25, UInt<1>(0h1) else : node _T_217 = bits(_WIRE_28, 2, 2) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = and(_T_218, vacants_25) when _T_219 : node _next_T_25 = dshl(_WIRE_28, UInt<1>(0h1)) connect next_25, _next_T_25 connect _WIRE_29, next_25 wire next_26 : UInt<3> connect next_26, _WIRE_29 node _T_220 = eq(_WIRE_29, UInt<1>(0h0)) node _T_221 = and(_T_220, vacants_26) when _T_221 : connect next_26, UInt<1>(0h1) else : node _T_222 = bits(_WIRE_29, 2, 2) node _T_223 = eq(_T_222, UInt<1>(0h0)) node _T_224 = and(_T_223, vacants_26) when _T_224 : node _next_T_26 = dshl(_WIRE_29, UInt<1>(0h1)) connect next_26, _next_T_26 connect _WIRE_30, next_26 wire next_27 : UInt<3> connect next_27, _WIRE_30 node _T_225 = eq(_WIRE_30, UInt<1>(0h0)) node _T_226 = and(_T_225, vacants_27) when _T_226 : connect next_27, UInt<1>(0h1) else : node _T_227 = bits(_WIRE_30, 2, 2) node _T_228 = eq(_T_227, UInt<1>(0h0)) node _T_229 = and(_T_228, vacants_27) when _T_229 : node _next_T_27 = dshl(_WIRE_30, UInt<1>(0h1)) connect next_27, _next_T_27 connect _WIRE_31, next_27 wire next_28 : UInt<3> connect next_28, _WIRE_31 node _T_230 = eq(_WIRE_31, UInt<1>(0h0)) node _T_231 = and(_T_230, vacants_28) when _T_231 : connect next_28, UInt<1>(0h1) else : node _T_232 = bits(_WIRE_31, 2, 2) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = and(_T_233, vacants_28) when _T_234 : node _next_T_28 = dshl(_WIRE_31, UInt<1>(0h1)) connect next_28, _next_T_28 connect _WIRE_32, next_28 wire next_29 : UInt<3> connect next_29, _WIRE_32 node _T_235 = eq(_WIRE_32, UInt<1>(0h0)) node _T_236 = and(_T_235, vacants_29) when _T_236 : connect next_29, UInt<1>(0h1) else : node _T_237 = bits(_WIRE_32, 2, 2) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = and(_T_238, vacants_29) when _T_239 : node _next_T_29 = dshl(_WIRE_32, UInt<1>(0h1)) connect next_29, _next_T_29 connect _WIRE_33, next_29 wire next_30 : UInt<3> connect next_30, _WIRE_33 node _T_240 = eq(_WIRE_33, UInt<1>(0h0)) node _T_241 = and(_T_240, vacants_30) when _T_241 : connect next_30, UInt<1>(0h1) else : node _T_242 = bits(_WIRE_33, 2, 2) node _T_243 = eq(_T_242, UInt<1>(0h0)) node _T_244 = and(_T_243, vacants_30) when _T_244 : node _next_T_30 = dshl(_WIRE_33, UInt<1>(0h1)) connect next_30, _next_T_30 connect _WIRE_34, next_30 wire next_31 : UInt<3> connect next_31, _WIRE_34 node _T_245 = eq(_WIRE_34, UInt<1>(0h0)) node _T_246 = and(_T_245, vacants_31) when _T_246 : connect next_31, UInt<1>(0h1) else : node _T_247 = bits(_WIRE_34, 2, 2) node _T_248 = eq(_T_247, UInt<1>(0h0)) node _T_249 = and(_T_248, vacants_31) when _T_249 : node _next_T_31 = dshl(_WIRE_34, UInt<1>(0h1)) connect next_31, _next_T_31 connect _WIRE_35, next_31 wire next_32 : UInt<3> connect next_32, _WIRE_35 node _T_250 = eq(_WIRE_35, UInt<1>(0h0)) node _T_251 = and(_T_250, vacants_32) when _T_251 : connect next_32, UInt<1>(0h1) else : node _T_252 = bits(_WIRE_35, 2, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = and(_T_253, vacants_32) when _T_254 : node _next_T_32 = dshl(_WIRE_35, UInt<1>(0h1)) connect next_32, _next_T_32 connect _WIRE_36, next_32 wire next_33 : UInt<3> connect next_33, _WIRE_36 node _T_255 = eq(_WIRE_36, UInt<1>(0h0)) node _T_256 = and(_T_255, vacants_33) when _T_256 : connect next_33, UInt<1>(0h1) else : node _T_257 = bits(_WIRE_36, 2, 2) node _T_258 = eq(_T_257, UInt<1>(0h0)) node _T_259 = and(_T_258, vacants_33) when _T_259 : node _next_T_33 = dshl(_WIRE_36, UInt<1>(0h1)) connect next_33, _next_T_33 connect _WIRE_37, next_33 node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) node will_be_valid_32 = and(_will_be_valid_T_3, _will_be_valid_T_4) node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0)) node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5) node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0)) node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7) node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0)) node will_be_valid_33 = and(_will_be_valid_T_8, _will_be_valid_T_9) node _will_be_valid_T_10 = eq(_WIRE_2.exception, UInt<1>(0h0)) node _will_be_valid_T_11 = and(io.dis_uops[2].valid, _will_be_valid_T_10) node _will_be_valid_T_12 = eq(_WIRE_2.is_fence, UInt<1>(0h0)) node _will_be_valid_T_13 = and(_will_be_valid_T_11, _will_be_valid_T_12) node _will_be_valid_T_14 = eq(_WIRE_2.is_fencei, UInt<1>(0h0)) node will_be_valid_34 = and(_will_be_valid_T_13, _will_be_valid_T_14) connect issue_slots[0].in_uop.valid, UInt<1>(0h0) connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc node _T_260 = eq(_WIRE_4, UInt<1>(0h1)) when _T_260 : connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[1].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[1].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[1].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[1].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[1].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[1].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[1].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[1].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[1].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[1].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[1].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[1].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[1].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[1].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[1].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[1].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[1].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[1].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[1].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[1].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[1].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[1].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[1].out_uop.uopc node _T_261 = eq(_WIRE_5, UInt<2>(0h2)) when _T_261 : connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[2].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[2].out_uop.uopc node _T_262 = eq(_WIRE_6, UInt<3>(0h4)) when _T_262 : connect issue_slots[0].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[0].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[0].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[0].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[0].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[0].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[0].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[0].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[0].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[0].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[0].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[0].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[0].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[0].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[0].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[0].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[0].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[0].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[0].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[0].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[0].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[0].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[0].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[0].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _issue_slots_0_clear_T = neq(_WIRE_3, UInt<1>(0h0)) connect issue_slots[0].clear, _issue_slots_0_clear_T connect issue_slots[1].in_uop.valid, UInt<1>(0h0) connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc node _T_263 = eq(_WIRE_5, UInt<1>(0h1)) when _T_263 : connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[2].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[2].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[2].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[2].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[2].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[2].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[2].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[2].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[2].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[2].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[2].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[2].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[2].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[2].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[2].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[2].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[2].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[2].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[2].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[2].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[2].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[2].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[2].out_uop.uopc node _T_264 = eq(_WIRE_6, UInt<2>(0h2)) when _T_264 : connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _T_265 = eq(_WIRE_7, UInt<3>(0h4)) when _T_265 : connect issue_slots[1].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[1].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[1].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[1].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[1].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[1].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[1].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[1].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[1].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[1].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[1].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[1].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[1].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[1].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[1].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[1].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[1].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[1].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[1].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[1].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[1].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[1].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[1].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[1].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _issue_slots_1_clear_T = neq(_WIRE_4, UInt<1>(0h0)) connect issue_slots[1].clear, _issue_slots_1_clear_T connect issue_slots[2].in_uop.valid, UInt<1>(0h0) connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _T_266 = eq(_WIRE_6, UInt<1>(0h1)) when _T_266 : connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[3].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[3].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[3].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[3].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[3].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[3].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[3].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[3].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[3].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[3].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[3].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[3].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[3].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[3].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[3].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[3].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[3].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[3].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[3].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[3].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[3].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[3].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[3].out_uop.uopc node _T_267 = eq(_WIRE_7, UInt<2>(0h2)) when _T_267 : connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _T_268 = eq(_WIRE_8, UInt<3>(0h4)) when _T_268 : connect issue_slots[2].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[2].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[2].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[2].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[2].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[2].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[2].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[2].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[2].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[2].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[2].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[2].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[2].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[2].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[2].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[2].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[2].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[2].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[2].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[2].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[2].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[2].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[2].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[2].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _issue_slots_2_clear_T = neq(_WIRE_5, UInt<1>(0h0)) connect issue_slots[2].clear, _issue_slots_2_clear_T connect issue_slots[3].in_uop.valid, UInt<1>(0h0) connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _T_269 = eq(_WIRE_7, UInt<1>(0h1)) when _T_269 : connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[4].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[4].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[4].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[4].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[4].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[4].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[4].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[4].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[4].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[4].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[4].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[4].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[4].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[4].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[4].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[4].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[4].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[4].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[4].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[4].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[4].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[4].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[4].out_uop.uopc node _T_270 = eq(_WIRE_8, UInt<2>(0h2)) when _T_270 : connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _T_271 = eq(_WIRE_9, UInt<3>(0h4)) when _T_271 : connect issue_slots[3].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[3].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[3].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[3].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[3].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[3].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[3].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[3].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[3].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[3].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[3].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[3].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[3].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[3].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[3].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[3].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[3].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[3].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[3].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[3].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[3].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[3].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[3].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[3].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _issue_slots_3_clear_T = neq(_WIRE_6, UInt<1>(0h0)) connect issue_slots[3].clear, _issue_slots_3_clear_T connect issue_slots[4].in_uop.valid, UInt<1>(0h0) connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _T_272 = eq(_WIRE_8, UInt<1>(0h1)) when _T_272 : connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[5].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[5].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[5].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[5].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[5].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[5].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[5].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[5].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[5].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[5].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[5].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[5].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[5].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[5].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[5].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[5].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[5].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[5].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[5].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[5].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[5].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[5].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[5].out_uop.uopc node _T_273 = eq(_WIRE_9, UInt<2>(0h2)) when _T_273 : connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _T_274 = eq(_WIRE_10, UInt<3>(0h4)) when _T_274 : connect issue_slots[4].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[4].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[4].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[4].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[4].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[4].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[4].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[4].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[4].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[4].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[4].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[4].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[4].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[4].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[4].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[4].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[4].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[4].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[4].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[4].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[4].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[4].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[4].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[4].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _issue_slots_4_clear_T = neq(_WIRE_7, UInt<1>(0h0)) connect issue_slots[4].clear, _issue_slots_4_clear_T connect issue_slots[5].in_uop.valid, UInt<1>(0h0) connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _T_275 = eq(_WIRE_9, UInt<1>(0h1)) when _T_275 : connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[6].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[6].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[6].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[6].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[6].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[6].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[6].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[6].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[6].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[6].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[6].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[6].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[6].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[6].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[6].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[6].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[6].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[6].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[6].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[6].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[6].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[6].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[6].out_uop.uopc node _T_276 = eq(_WIRE_10, UInt<2>(0h2)) when _T_276 : connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _T_277 = eq(_WIRE_11, UInt<3>(0h4)) when _T_277 : connect issue_slots[5].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single connect issue_slots[5].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val connect issue_slots[5].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[5].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[5].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[5].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal connect issue_slots[5].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr connect issue_slots[5].in_uop.bits.is_br, issue_slots[8].out_uop.is_br connect issue_slots[5].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned connect issue_slots[5].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned connect issue_slots[5].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state connect issue_slots[5].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std connect issue_slots[5].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta connect issue_slots[5].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load connect issue_slots[5].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd connect issue_slots[5].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw connect issue_slots[5].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn connect issue_slots[5].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel connect issue_slots[5].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel connect issue_slots[5].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel connect issue_slots[5].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type connect issue_slots[5].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code connect issue_slots[5].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[8].out_uop.inst connect issue_slots[5].in_uop.bits.uopc, issue_slots[8].out_uop.uopc node _issue_slots_5_clear_T = neq(_WIRE_8, UInt<1>(0h0)) connect issue_slots[5].clear, _issue_slots_5_clear_T connect issue_slots[6].in_uop.valid, UInt<1>(0h0) connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _T_278 = eq(_WIRE_10, UInt<1>(0h1)) when _T_278 : connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[7].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[7].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[7].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[7].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[7].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[7].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[7].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[7].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[7].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[7].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[7].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[7].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[7].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[7].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[7].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[7].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[7].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[7].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[7].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[7].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[7].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[7].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[7].out_uop.uopc node _T_279 = eq(_WIRE_11, UInt<2>(0h2)) when _T_279 : connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[8].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[8].out_uop.uopc node _T_280 = eq(_WIRE_12, UInt<3>(0h4)) when _T_280 : connect issue_slots[6].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single connect issue_slots[6].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val connect issue_slots[6].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[6].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[6].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[6].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal connect issue_slots[6].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr connect issue_slots[6].in_uop.bits.is_br, issue_slots[9].out_uop.is_br connect issue_slots[6].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned connect issue_slots[6].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned connect issue_slots[6].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state connect issue_slots[6].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std connect issue_slots[6].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta connect issue_slots[6].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load connect issue_slots[6].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd connect issue_slots[6].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw connect issue_slots[6].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn connect issue_slots[6].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel connect issue_slots[6].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel connect issue_slots[6].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel connect issue_slots[6].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type connect issue_slots[6].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code connect issue_slots[6].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[9].out_uop.inst connect issue_slots[6].in_uop.bits.uopc, issue_slots[9].out_uop.uopc node _issue_slots_6_clear_T = neq(_WIRE_9, UInt<1>(0h0)) connect issue_slots[6].clear, _issue_slots_6_clear_T connect issue_slots[7].in_uop.valid, UInt<1>(0h0) connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr connect issue_slots[7].in_uop.bits.is_br, issue_slots[8].out_uop.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code connect issue_slots[7].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst connect issue_slots[7].in_uop.bits.uopc, issue_slots[8].out_uop.uopc node _T_281 = eq(_WIRE_11, UInt<1>(0h1)) when _T_281 : connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, issue_slots[8].out_uop.fp_single connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[8].out_uop.ldst_val connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, issue_slots[8].out_uop.bypassable connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[8].out_uop.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.is_jal, issue_slots[8].out_uop.is_jal connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[8].out_uop.is_jalr connect issue_slots[7].in_uop.bits.is_br, issue_slots[8].out_uop.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[8].out_uop.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[8].out_uop.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, issue_slots[8].out_uop.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[8].out_uop.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[8].out_uop.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[8].out_uop.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[8].out_uop.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[8].out_uop.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[8].out_uop.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[8].out_uop.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[8].out_uop.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[8].out_uop.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[8].out_uop.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, issue_slots[8].out_uop.fu_code connect issue_slots[7].in_uop.bits.iq_type, issue_slots[8].out_uop.iq_type connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst connect issue_slots[7].in_uop.bits.uopc, issue_slots[8].out_uop.uopc node _T_282 = eq(_WIRE_12, UInt<2>(0h2)) when _T_282 : connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[7].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr connect issue_slots[7].in_uop.bits.is_br, issue_slots[9].out_uop.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code connect issue_slots[7].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst connect issue_slots[7].in_uop.bits.uopc, issue_slots[9].out_uop.uopc node _T_283 = eq(_WIRE_13, UInt<3>(0h4)) when _T_283 : connect issue_slots[7].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single connect issue_slots[7].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val connect issue_slots[7].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[7].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[7].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[7].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal connect issue_slots[7].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr connect issue_slots[7].in_uop.bits.is_br, issue_slots[10].out_uop.is_br connect issue_slots[7].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned connect issue_slots[7].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned connect issue_slots[7].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state connect issue_slots[7].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std connect issue_slots[7].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta connect issue_slots[7].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load connect issue_slots[7].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd connect issue_slots[7].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw connect issue_slots[7].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn connect issue_slots[7].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel connect issue_slots[7].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel connect issue_slots[7].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel connect issue_slots[7].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type connect issue_slots[7].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code connect issue_slots[7].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[10].out_uop.inst connect issue_slots[7].in_uop.bits.uopc, issue_slots[10].out_uop.uopc node _issue_slots_7_clear_T = neq(_WIRE_10, UInt<1>(0h0)) connect issue_slots[7].clear, _issue_slots_7_clear_T connect issue_slots[8].in_uop.valid, UInt<1>(0h0) connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr connect issue_slots[8].in_uop.bits.is_br, issue_slots[9].out_uop.is_br connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned connect issue_slots[8].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type connect issue_slots[8].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code connect issue_slots[8].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst connect issue_slots[8].in_uop.bits.uopc, issue_slots[9].out_uop.uopc node _T_284 = eq(_WIRE_12, UInt<1>(0h1)) when _T_284 : connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_single, issue_slots[9].out_uop.fp_single connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[9].out_uop.ldst_val connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.bypassable, issue_slots[9].out_uop.bypassable connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[9].out_uop.csr_addr connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.is_jal, issue_slots[9].out_uop.is_jal connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[9].out_uop.is_jalr connect issue_slots[8].in_uop.bits.is_br, issue_slots[9].out_uop.is_br connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[9].out_uop.iw_p2_poisoned connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[9].out_uop.iw_p1_poisoned connect issue_slots[8].in_uop.bits.iw_state, issue_slots[9].out_uop.iw_state connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[9].out_uop.ctrl.is_std connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[9].out_uop.ctrl.is_sta connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[9].out_uop.ctrl.is_load connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[9].out_uop.ctrl.csr_cmd connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[9].out_uop.ctrl.fcn_dw connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[9].out_uop.ctrl.op_fcn connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[9].out_uop.ctrl.imm_sel connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[9].out_uop.ctrl.op2_sel connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[9].out_uop.ctrl.op1_sel connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[9].out_uop.ctrl.br_type connect issue_slots[8].in_uop.bits.fu_code, issue_slots[9].out_uop.fu_code connect issue_slots[8].in_uop.bits.iq_type, issue_slots[9].out_uop.iq_type connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst connect issue_slots[8].in_uop.bits.uopc, issue_slots[9].out_uop.uopc node _T_285 = eq(_WIRE_13, UInt<2>(0h2)) when _T_285 : connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[8].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr connect issue_slots[8].in_uop.bits.is_br, issue_slots[10].out_uop.is_br connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned connect issue_slots[8].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type connect issue_slots[8].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code connect issue_slots[8].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst connect issue_slots[8].in_uop.bits.uopc, issue_slots[10].out_uop.uopc node _T_286 = eq(_WIRE_14, UInt<3>(0h4)) when _T_286 : connect issue_slots[8].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single connect issue_slots[8].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val connect issue_slots[8].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[8].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[8].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[8].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal connect issue_slots[8].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr connect issue_slots[8].in_uop.bits.is_br, issue_slots[11].out_uop.is_br connect issue_slots[8].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned connect issue_slots[8].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned connect issue_slots[8].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state connect issue_slots[8].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std connect issue_slots[8].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta connect issue_slots[8].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load connect issue_slots[8].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd connect issue_slots[8].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw connect issue_slots[8].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn connect issue_slots[8].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel connect issue_slots[8].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel connect issue_slots[8].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel connect issue_slots[8].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type connect issue_slots[8].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code connect issue_slots[8].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[11].out_uop.inst connect issue_slots[8].in_uop.bits.uopc, issue_slots[11].out_uop.uopc node _issue_slots_8_clear_T = neq(_WIRE_11, UInt<1>(0h0)) connect issue_slots[8].clear, _issue_slots_8_clear_T connect issue_slots[9].in_uop.valid, UInt<1>(0h0) connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr connect issue_slots[9].in_uop.bits.is_br, issue_slots[10].out_uop.is_br connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned connect issue_slots[9].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type connect issue_slots[9].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code connect issue_slots[9].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst connect issue_slots[9].in_uop.bits.uopc, issue_slots[10].out_uop.uopc node _T_287 = eq(_WIRE_13, UInt<1>(0h1)) when _T_287 : connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_single, issue_slots[10].out_uop.fp_single connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[10].out_uop.ldst_val connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.bypassable, issue_slots[10].out_uop.bypassable connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[10].out_uop.csr_addr connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.is_jal, issue_slots[10].out_uop.is_jal connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[10].out_uop.is_jalr connect issue_slots[9].in_uop.bits.is_br, issue_slots[10].out_uop.is_br connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[10].out_uop.iw_p2_poisoned connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[10].out_uop.iw_p1_poisoned connect issue_slots[9].in_uop.bits.iw_state, issue_slots[10].out_uop.iw_state connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[10].out_uop.ctrl.is_std connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[10].out_uop.ctrl.is_sta connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[10].out_uop.ctrl.is_load connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[10].out_uop.ctrl.csr_cmd connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[10].out_uop.ctrl.fcn_dw connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[10].out_uop.ctrl.op_fcn connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[10].out_uop.ctrl.imm_sel connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[10].out_uop.ctrl.op2_sel connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[10].out_uop.ctrl.op1_sel connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[10].out_uop.ctrl.br_type connect issue_slots[9].in_uop.bits.fu_code, issue_slots[10].out_uop.fu_code connect issue_slots[9].in_uop.bits.iq_type, issue_slots[10].out_uop.iq_type connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst connect issue_slots[9].in_uop.bits.uopc, issue_slots[10].out_uop.uopc node _T_288 = eq(_WIRE_14, UInt<2>(0h2)) when _T_288 : connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[9].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr connect issue_slots[9].in_uop.bits.is_br, issue_slots[11].out_uop.is_br connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned connect issue_slots[9].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type connect issue_slots[9].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code connect issue_slots[9].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst connect issue_slots[9].in_uop.bits.uopc, issue_slots[11].out_uop.uopc node _T_289 = eq(_WIRE_15, UInt<3>(0h4)) when _T_289 : connect issue_slots[9].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single connect issue_slots[9].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val connect issue_slots[9].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[9].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[9].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[9].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal connect issue_slots[9].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr connect issue_slots[9].in_uop.bits.is_br, issue_slots[12].out_uop.is_br connect issue_slots[9].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned connect issue_slots[9].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned connect issue_slots[9].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state connect issue_slots[9].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std connect issue_slots[9].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta connect issue_slots[9].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load connect issue_slots[9].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd connect issue_slots[9].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw connect issue_slots[9].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn connect issue_slots[9].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel connect issue_slots[9].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel connect issue_slots[9].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel connect issue_slots[9].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type connect issue_slots[9].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code connect issue_slots[9].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[12].out_uop.inst connect issue_slots[9].in_uop.bits.uopc, issue_slots[12].out_uop.uopc node _issue_slots_9_clear_T = neq(_WIRE_12, UInt<1>(0h0)) connect issue_slots[9].clear, _issue_slots_9_clear_T connect issue_slots[10].in_uop.valid, UInt<1>(0h0) connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr connect issue_slots[10].in_uop.bits.is_br, issue_slots[11].out_uop.is_br connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned connect issue_slots[10].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type connect issue_slots[10].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code connect issue_slots[10].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst connect issue_slots[10].in_uop.bits.uopc, issue_slots[11].out_uop.uopc node _T_290 = eq(_WIRE_14, UInt<1>(0h1)) when _T_290 : connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_single, issue_slots[11].out_uop.fp_single connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[11].out_uop.ldst_val connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.bypassable, issue_slots[11].out_uop.bypassable connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[11].out_uop.csr_addr connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.is_jal, issue_slots[11].out_uop.is_jal connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[11].out_uop.is_jalr connect issue_slots[10].in_uop.bits.is_br, issue_slots[11].out_uop.is_br connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[11].out_uop.iw_p2_poisoned connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[11].out_uop.iw_p1_poisoned connect issue_slots[10].in_uop.bits.iw_state, issue_slots[11].out_uop.iw_state connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[11].out_uop.ctrl.is_std connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[11].out_uop.ctrl.is_sta connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[11].out_uop.ctrl.is_load connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[11].out_uop.ctrl.csr_cmd connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[11].out_uop.ctrl.fcn_dw connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[11].out_uop.ctrl.op_fcn connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[11].out_uop.ctrl.imm_sel connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[11].out_uop.ctrl.op2_sel connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[11].out_uop.ctrl.op1_sel connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[11].out_uop.ctrl.br_type connect issue_slots[10].in_uop.bits.fu_code, issue_slots[11].out_uop.fu_code connect issue_slots[10].in_uop.bits.iq_type, issue_slots[11].out_uop.iq_type connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst connect issue_slots[10].in_uop.bits.uopc, issue_slots[11].out_uop.uopc node _T_291 = eq(_WIRE_15, UInt<2>(0h2)) when _T_291 : connect issue_slots[10].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single connect issue_slots[10].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val connect issue_slots[10].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[10].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[10].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr connect issue_slots[10].in_uop.bits.is_br, issue_slots[12].out_uop.is_br connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned connect issue_slots[10].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type connect issue_slots[10].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code connect issue_slots[10].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[12].out_uop.inst connect issue_slots[10].in_uop.bits.uopc, issue_slots[12].out_uop.uopc node _T_292 = eq(_WIRE_16, UInt<3>(0h4)) when _T_292 : connect issue_slots[10].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single connect issue_slots[10].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val connect issue_slots[10].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[10].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[10].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[10].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal connect issue_slots[10].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr connect issue_slots[10].in_uop.bits.is_br, issue_slots[13].out_uop.is_br connect issue_slots[10].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned connect issue_slots[10].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned connect issue_slots[10].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state connect issue_slots[10].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std connect issue_slots[10].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta connect issue_slots[10].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load connect issue_slots[10].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd connect issue_slots[10].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw connect issue_slots[10].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn connect issue_slots[10].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel connect issue_slots[10].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel connect issue_slots[10].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel connect issue_slots[10].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type connect issue_slots[10].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code connect issue_slots[10].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[13].out_uop.inst connect issue_slots[10].in_uop.bits.uopc, issue_slots[13].out_uop.uopc node _issue_slots_10_clear_T = neq(_WIRE_13, UInt<1>(0h0)) connect issue_slots[10].clear, _issue_slots_10_clear_T connect issue_slots[11].in_uop.valid, UInt<1>(0h0) connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr connect issue_slots[11].in_uop.bits.is_br, issue_slots[12].out_uop.is_br connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned connect issue_slots[11].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type connect issue_slots[11].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code connect issue_slots[11].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst connect issue_slots[11].in_uop.bits.uopc, issue_slots[12].out_uop.uopc node _T_293 = eq(_WIRE_15, UInt<1>(0h1)) when _T_293 : connect issue_slots[11].in_uop.valid, issue_slots[12].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[12].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[12].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[12].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[12].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[12].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[12].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[12].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_single, issue_slots[12].out_uop.fp_single connect issue_slots[11].in_uop.bits.fp_val, issue_slots[12].out_uop.fp_val connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[12].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[12].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[12].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[12].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[12].out_uop.ldst_val connect issue_slots[11].in_uop.bits.lrs3, issue_slots[12].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[12].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[12].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[12].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[12].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[12].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[12].out_uop.is_unique connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[12].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[12].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[12].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.is_amo, issue_slots[12].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[12].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[12].out_uop.is_fence connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[12].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[12].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[12].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.bypassable, issue_slots[12].out_uop.bypassable connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[12].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[12].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[12].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[12].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[12].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[12].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[12].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[12].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[12].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[12].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[12].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[12].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[12].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[12].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[12].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[12].out_uop.rob_idx connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[12].out_uop.csr_addr connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[12].out_uop.imm_packed connect issue_slots[11].in_uop.bits.taken, issue_slots[12].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[12].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[12].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[12].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.br_tag, issue_slots[12].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[12].out_uop.br_mask connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[12].out_uop.is_sfb connect issue_slots[11].in_uop.bits.is_jal, issue_slots[12].out_uop.is_jal connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[12].out_uop.is_jalr connect issue_slots[11].in_uop.bits.is_br, issue_slots[12].out_uop.is_br connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[12].out_uop.iw_p2_poisoned connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[12].out_uop.iw_p1_poisoned connect issue_slots[11].in_uop.bits.iw_state, issue_slots[12].out_uop.iw_state connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[12].out_uop.ctrl.is_std connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[12].out_uop.ctrl.is_sta connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[12].out_uop.ctrl.is_load connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[12].out_uop.ctrl.csr_cmd connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[12].out_uop.ctrl.fcn_dw connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[12].out_uop.ctrl.op_fcn connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[12].out_uop.ctrl.imm_sel connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[12].out_uop.ctrl.op2_sel connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[12].out_uop.ctrl.op1_sel connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[12].out_uop.ctrl.br_type connect issue_slots[11].in_uop.bits.fu_code, issue_slots[12].out_uop.fu_code connect issue_slots[11].in_uop.bits.iq_type, issue_slots[12].out_uop.iq_type connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[12].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[12].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[12].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[12].out_uop.inst connect issue_slots[11].in_uop.bits.uopc, issue_slots[12].out_uop.uopc node _T_294 = eq(_WIRE_16, UInt<2>(0h2)) when _T_294 : connect issue_slots[11].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single connect issue_slots[11].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val connect issue_slots[11].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[11].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[11].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr connect issue_slots[11].in_uop.bits.is_br, issue_slots[13].out_uop.is_br connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned connect issue_slots[11].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type connect issue_slots[11].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code connect issue_slots[11].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[13].out_uop.inst connect issue_slots[11].in_uop.bits.uopc, issue_slots[13].out_uop.uopc node _T_295 = eq(_WIRE_17, UInt<3>(0h4)) when _T_295 : connect issue_slots[11].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[11].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single connect issue_slots[11].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[11].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[11].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val connect issue_slots[11].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[11].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[11].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[11].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[11].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[11].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[11].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[11].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[11].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[11].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[11].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[11].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[11].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable connect issue_slots[11].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[11].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[11].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[11].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[11].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[11].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[11].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[11].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[11].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[11].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr connect issue_slots[11].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[11].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[11].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[11].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[11].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[11].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[11].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal connect issue_slots[11].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr connect issue_slots[11].in_uop.bits.is_br, issue_slots[14].out_uop.is_br connect issue_slots[11].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned connect issue_slots[11].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned connect issue_slots[11].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state connect issue_slots[11].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std connect issue_slots[11].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta connect issue_slots[11].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load connect issue_slots[11].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd connect issue_slots[11].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw connect issue_slots[11].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn connect issue_slots[11].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel connect issue_slots[11].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel connect issue_slots[11].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel connect issue_slots[11].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type connect issue_slots[11].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code connect issue_slots[11].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type connect issue_slots[11].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[11].in_uop.bits.inst, issue_slots[14].out_uop.inst connect issue_slots[11].in_uop.bits.uopc, issue_slots[14].out_uop.uopc node _issue_slots_11_clear_T = neq(_WIRE_14, UInt<1>(0h0)) connect issue_slots[11].clear, _issue_slots_11_clear_T connect issue_slots[12].in_uop.valid, UInt<1>(0h0) connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr connect issue_slots[12].in_uop.bits.is_br, issue_slots[13].out_uop.is_br connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned connect issue_slots[12].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type connect issue_slots[12].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code connect issue_slots[12].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst connect issue_slots[12].in_uop.bits.uopc, issue_slots[13].out_uop.uopc node _T_296 = eq(_WIRE_16, UInt<1>(0h1)) when _T_296 : connect issue_slots[12].in_uop.valid, issue_slots[13].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[13].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[13].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[13].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[13].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[13].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[13].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[13].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_single, issue_slots[13].out_uop.fp_single connect issue_slots[12].in_uop.bits.fp_val, issue_slots[13].out_uop.fp_val connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[13].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[13].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[13].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[13].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[13].out_uop.ldst_val connect issue_slots[12].in_uop.bits.lrs3, issue_slots[13].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[13].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[13].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[13].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[13].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[13].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[13].out_uop.is_unique connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[13].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[13].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[13].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.is_amo, issue_slots[13].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[13].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[13].out_uop.is_fence connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[13].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[13].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[13].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.bypassable, issue_slots[13].out_uop.bypassable connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[13].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[13].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[13].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[13].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[13].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[13].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[13].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[13].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[13].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[13].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[13].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[13].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[13].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[13].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[13].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[13].out_uop.rob_idx connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[13].out_uop.csr_addr connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[13].out_uop.imm_packed connect issue_slots[12].in_uop.bits.taken, issue_slots[13].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[13].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[13].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[13].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.br_tag, issue_slots[13].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[13].out_uop.br_mask connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[13].out_uop.is_sfb connect issue_slots[12].in_uop.bits.is_jal, issue_slots[13].out_uop.is_jal connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[13].out_uop.is_jalr connect issue_slots[12].in_uop.bits.is_br, issue_slots[13].out_uop.is_br connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[13].out_uop.iw_p2_poisoned connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[13].out_uop.iw_p1_poisoned connect issue_slots[12].in_uop.bits.iw_state, issue_slots[13].out_uop.iw_state connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[13].out_uop.ctrl.is_std connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[13].out_uop.ctrl.is_sta connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[13].out_uop.ctrl.is_load connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[13].out_uop.ctrl.csr_cmd connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[13].out_uop.ctrl.fcn_dw connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[13].out_uop.ctrl.op_fcn connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[13].out_uop.ctrl.imm_sel connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[13].out_uop.ctrl.op2_sel connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[13].out_uop.ctrl.op1_sel connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[13].out_uop.ctrl.br_type connect issue_slots[12].in_uop.bits.fu_code, issue_slots[13].out_uop.fu_code connect issue_slots[12].in_uop.bits.iq_type, issue_slots[13].out_uop.iq_type connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[13].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[13].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[13].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[13].out_uop.inst connect issue_slots[12].in_uop.bits.uopc, issue_slots[13].out_uop.uopc node _T_297 = eq(_WIRE_17, UInt<2>(0h2)) when _T_297 : connect issue_slots[12].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single connect issue_slots[12].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val connect issue_slots[12].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[12].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[12].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr connect issue_slots[12].in_uop.bits.is_br, issue_slots[14].out_uop.is_br connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned connect issue_slots[12].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type connect issue_slots[12].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code connect issue_slots[12].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[14].out_uop.inst connect issue_slots[12].in_uop.bits.uopc, issue_slots[14].out_uop.uopc node _T_298 = eq(_WIRE_18, UInt<3>(0h4)) when _T_298 : connect issue_slots[12].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[12].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[12].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[12].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[12].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[12].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[12].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[12].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[12].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single connect issue_slots[12].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[12].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[12].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[12].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[12].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[12].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val connect issue_slots[12].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[12].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[12].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[12].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[12].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[12].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[12].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[12].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[12].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[12].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[12].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[12].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[12].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[12].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[12].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[12].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[12].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable connect issue_slots[12].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[12].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[12].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[12].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[12].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[12].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[12].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[12].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[12].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[12].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[12].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[12].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[12].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[12].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[12].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[12].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[12].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr connect issue_slots[12].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[12].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[12].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[12].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[12].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[12].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[12].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[12].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[12].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal connect issue_slots[12].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr connect issue_slots[12].in_uop.bits.is_br, issue_slots[15].out_uop.is_br connect issue_slots[12].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned connect issue_slots[12].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned connect issue_slots[12].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state connect issue_slots[12].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std connect issue_slots[12].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta connect issue_slots[12].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load connect issue_slots[12].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd connect issue_slots[12].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw connect issue_slots[12].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn connect issue_slots[12].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel connect issue_slots[12].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel connect issue_slots[12].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel connect issue_slots[12].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type connect issue_slots[12].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code connect issue_slots[12].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type connect issue_slots[12].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[12].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[12].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[12].in_uop.bits.inst, issue_slots[15].out_uop.inst connect issue_slots[12].in_uop.bits.uopc, issue_slots[15].out_uop.uopc node _issue_slots_12_clear_T = neq(_WIRE_15, UInt<1>(0h0)) connect issue_slots[12].clear, _issue_slots_12_clear_T connect issue_slots[13].in_uop.valid, UInt<1>(0h0) connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr connect issue_slots[13].in_uop.bits.is_br, issue_slots[14].out_uop.is_br connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned connect issue_slots[13].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type connect issue_slots[13].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code connect issue_slots[13].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst connect issue_slots[13].in_uop.bits.uopc, issue_slots[14].out_uop.uopc node _T_299 = eq(_WIRE_17, UInt<1>(0h1)) when _T_299 : connect issue_slots[13].in_uop.valid, issue_slots[14].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[14].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[14].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[14].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[14].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[14].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[14].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[14].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_single, issue_slots[14].out_uop.fp_single connect issue_slots[13].in_uop.bits.fp_val, issue_slots[14].out_uop.fp_val connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[14].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[14].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[14].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[14].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[14].out_uop.ldst_val connect issue_slots[13].in_uop.bits.lrs3, issue_slots[14].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[14].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[14].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[14].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[14].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[14].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[14].out_uop.is_unique connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[14].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[14].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[14].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.is_amo, issue_slots[14].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[14].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[14].out_uop.is_fence connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[14].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[14].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[14].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.bypassable, issue_slots[14].out_uop.bypassable connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[14].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[14].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[14].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[14].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[14].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[14].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[14].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[14].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[14].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[14].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[14].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[14].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[14].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[14].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[14].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[14].out_uop.rob_idx connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[14].out_uop.csr_addr connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[14].out_uop.imm_packed connect issue_slots[13].in_uop.bits.taken, issue_slots[14].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[14].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[14].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[14].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.br_tag, issue_slots[14].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[14].out_uop.br_mask connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[14].out_uop.is_sfb connect issue_slots[13].in_uop.bits.is_jal, issue_slots[14].out_uop.is_jal connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[14].out_uop.is_jalr connect issue_slots[13].in_uop.bits.is_br, issue_slots[14].out_uop.is_br connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[14].out_uop.iw_p2_poisoned connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[14].out_uop.iw_p1_poisoned connect issue_slots[13].in_uop.bits.iw_state, issue_slots[14].out_uop.iw_state connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[14].out_uop.ctrl.is_std connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[14].out_uop.ctrl.is_sta connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[14].out_uop.ctrl.is_load connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[14].out_uop.ctrl.csr_cmd connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[14].out_uop.ctrl.fcn_dw connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[14].out_uop.ctrl.op_fcn connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[14].out_uop.ctrl.imm_sel connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[14].out_uop.ctrl.op2_sel connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[14].out_uop.ctrl.op1_sel connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[14].out_uop.ctrl.br_type connect issue_slots[13].in_uop.bits.fu_code, issue_slots[14].out_uop.fu_code connect issue_slots[13].in_uop.bits.iq_type, issue_slots[14].out_uop.iq_type connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[14].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[14].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[14].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[14].out_uop.inst connect issue_slots[13].in_uop.bits.uopc, issue_slots[14].out_uop.uopc node _T_300 = eq(_WIRE_18, UInt<2>(0h2)) when _T_300 : connect issue_slots[13].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single connect issue_slots[13].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val connect issue_slots[13].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[13].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[13].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr connect issue_slots[13].in_uop.bits.is_br, issue_slots[15].out_uop.is_br connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned connect issue_slots[13].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type connect issue_slots[13].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code connect issue_slots[13].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[15].out_uop.inst connect issue_slots[13].in_uop.bits.uopc, issue_slots[15].out_uop.uopc node _T_301 = eq(_WIRE_19, UInt<3>(0h4)) when _T_301 : connect issue_slots[13].in_uop.valid, issue_slots[16].will_be_valid connect issue_slots[13].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc connect issue_slots[13].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc connect issue_slots[13].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if connect issue_slots[13].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if connect issue_slots[13].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if connect issue_slots[13].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if connect issue_slots[13].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if connect issue_slots[13].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single connect issue_slots[13].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val connect issue_slots[13].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en connect issue_slots[13].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype connect issue_slots[13].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype connect issue_slots[13].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype connect issue_slots[13].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val connect issue_slots[13].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 connect issue_slots[13].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 connect issue_slots[13].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 connect issue_slots[13].in_uop.bits.ldst, issue_slots[16].out_uop.ldst connect issue_slots[13].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 connect issue_slots[13].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit connect issue_slots[13].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique connect issue_slots[13].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc connect issue_slots[13].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq connect issue_slots[13].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq connect issue_slots[13].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo connect issue_slots[13].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei connect issue_slots[13].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence connect issue_slots[13].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed connect issue_slots[13].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size connect issue_slots[13].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd connect issue_slots[13].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable connect issue_slots[13].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause connect issue_slots[13].in_uop.bits.exception, issue_slots[16].out_uop.exception connect issue_slots[13].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst connect issue_slots[13].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy connect issue_slots[13].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy connect issue_slots[13].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy connect issue_slots[13].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy connect issue_slots[13].in_uop.bits.ppred, issue_slots[16].out_uop.ppred connect issue_slots[13].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 connect issue_slots[13].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 connect issue_slots[13].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 connect issue_slots[13].in_uop.bits.pdst, issue_slots[16].out_uop.pdst connect issue_slots[13].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx connect issue_slots[13].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx connect issue_slots[13].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx connect issue_slots[13].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx connect issue_slots[13].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr connect issue_slots[13].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed connect issue_slots[13].in_uop.bits.taken, issue_slots[16].out_uop.taken connect issue_slots[13].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob connect issue_slots[13].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst connect issue_slots[13].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx connect issue_slots[13].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag connect issue_slots[13].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask connect issue_slots[13].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb connect issue_slots[13].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal connect issue_slots[13].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr connect issue_slots[13].in_uop.bits.is_br, issue_slots[16].out_uop.is_br connect issue_slots[13].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned connect issue_slots[13].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned connect issue_slots[13].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state connect issue_slots[13].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std connect issue_slots[13].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta connect issue_slots[13].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load connect issue_slots[13].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd connect issue_slots[13].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw connect issue_slots[13].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn connect issue_slots[13].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel connect issue_slots[13].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel connect issue_slots[13].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel connect issue_slots[13].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type connect issue_slots[13].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code connect issue_slots[13].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type connect issue_slots[13].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc connect issue_slots[13].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc connect issue_slots[13].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst connect issue_slots[13].in_uop.bits.inst, issue_slots[16].out_uop.inst connect issue_slots[13].in_uop.bits.uopc, issue_slots[16].out_uop.uopc node _issue_slots_13_clear_T = neq(_WIRE_16, UInt<1>(0h0)) connect issue_slots[13].clear, _issue_slots_13_clear_T connect issue_slots[14].in_uop.valid, UInt<1>(0h0) connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr connect issue_slots[14].in_uop.bits.is_br, issue_slots[15].out_uop.is_br connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned connect issue_slots[14].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type connect issue_slots[14].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code connect issue_slots[14].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst connect issue_slots[14].in_uop.bits.uopc, issue_slots[15].out_uop.uopc node _T_302 = eq(_WIRE_18, UInt<1>(0h1)) when _T_302 : connect issue_slots[14].in_uop.valid, issue_slots[15].will_be_valid connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[15].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[15].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[15].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[15].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[15].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[15].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[15].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_single, issue_slots[15].out_uop.fp_single connect issue_slots[14].in_uop.bits.fp_val, issue_slots[15].out_uop.fp_val connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[15].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[15].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[15].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[15].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[15].out_uop.ldst_val connect issue_slots[14].in_uop.bits.lrs3, issue_slots[15].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[15].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[15].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[15].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[15].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[15].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[15].out_uop.is_unique connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[15].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[15].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[15].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.is_amo, issue_slots[15].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[15].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[15].out_uop.is_fence connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[15].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[15].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[15].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.bypassable, issue_slots[15].out_uop.bypassable connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[15].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[15].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[15].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[15].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[15].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[15].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[15].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[15].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[15].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[15].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[15].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[15].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[15].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[15].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[15].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[15].out_uop.rob_idx connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[15].out_uop.csr_addr connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[15].out_uop.imm_packed connect issue_slots[14].in_uop.bits.taken, issue_slots[15].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[15].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[15].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[15].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.br_tag, issue_slots[15].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[15].out_uop.br_mask connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[15].out_uop.is_sfb connect issue_slots[14].in_uop.bits.is_jal, issue_slots[15].out_uop.is_jal connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[15].out_uop.is_jalr connect issue_slots[14].in_uop.bits.is_br, issue_slots[15].out_uop.is_br connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[15].out_uop.iw_p2_poisoned connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[15].out_uop.iw_p1_poisoned connect issue_slots[14].in_uop.bits.iw_state, issue_slots[15].out_uop.iw_state connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[15].out_uop.ctrl.is_std connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[15].out_uop.ctrl.is_sta connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[15].out_uop.ctrl.is_load connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[15].out_uop.ctrl.csr_cmd connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[15].out_uop.ctrl.fcn_dw connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[15].out_uop.ctrl.op_fcn connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[15].out_uop.ctrl.imm_sel connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[15].out_uop.ctrl.op2_sel connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[15].out_uop.ctrl.op1_sel connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[15].out_uop.ctrl.br_type connect issue_slots[14].in_uop.bits.fu_code, issue_slots[15].out_uop.fu_code connect issue_slots[14].in_uop.bits.iq_type, issue_slots[15].out_uop.iq_type connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[15].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[15].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[15].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[15].out_uop.inst connect issue_slots[14].in_uop.bits.uopc, issue_slots[15].out_uop.uopc node _T_303 = eq(_WIRE_19, UInt<2>(0h2)) when _T_303 : connect issue_slots[14].in_uop.valid, issue_slots[16].will_be_valid connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single connect issue_slots[14].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val connect issue_slots[14].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[16].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[16].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[16].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[16].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed connect issue_slots[14].in_uop.bits.taken, issue_slots[16].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb connect issue_slots[14].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr connect issue_slots[14].in_uop.bits.is_br, issue_slots[16].out_uop.is_br connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned connect issue_slots[14].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type connect issue_slots[14].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code connect issue_slots[14].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[16].out_uop.inst connect issue_slots[14].in_uop.bits.uopc, issue_slots[16].out_uop.uopc node _T_304 = eq(_WIRE_20, UInt<3>(0h4)) when _T_304 : connect issue_slots[14].in_uop.valid, issue_slots[17].will_be_valid connect issue_slots[14].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc connect issue_slots[14].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc connect issue_slots[14].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if connect issue_slots[14].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if connect issue_slots[14].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if connect issue_slots[14].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if connect issue_slots[14].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if connect issue_slots[14].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single connect issue_slots[14].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val connect issue_slots[14].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en connect issue_slots[14].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype connect issue_slots[14].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype connect issue_slots[14].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype connect issue_slots[14].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val connect issue_slots[14].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 connect issue_slots[14].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 connect issue_slots[14].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 connect issue_slots[14].in_uop.bits.ldst, issue_slots[17].out_uop.ldst connect issue_slots[14].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 connect issue_slots[14].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit connect issue_slots[14].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique connect issue_slots[14].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc connect issue_slots[14].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq connect issue_slots[14].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq connect issue_slots[14].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo connect issue_slots[14].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei connect issue_slots[14].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence connect issue_slots[14].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed connect issue_slots[14].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size connect issue_slots[14].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd connect issue_slots[14].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable connect issue_slots[14].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause connect issue_slots[14].in_uop.bits.exception, issue_slots[17].out_uop.exception connect issue_slots[14].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst connect issue_slots[14].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy connect issue_slots[14].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy connect issue_slots[14].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy connect issue_slots[14].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy connect issue_slots[14].in_uop.bits.ppred, issue_slots[17].out_uop.ppred connect issue_slots[14].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 connect issue_slots[14].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 connect issue_slots[14].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 connect issue_slots[14].in_uop.bits.pdst, issue_slots[17].out_uop.pdst connect issue_slots[14].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx connect issue_slots[14].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx connect issue_slots[14].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx connect issue_slots[14].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx connect issue_slots[14].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr connect issue_slots[14].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed connect issue_slots[14].in_uop.bits.taken, issue_slots[17].out_uop.taken connect issue_slots[14].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob connect issue_slots[14].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst connect issue_slots[14].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx connect issue_slots[14].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag connect issue_slots[14].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask connect issue_slots[14].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb connect issue_slots[14].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal connect issue_slots[14].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr connect issue_slots[14].in_uop.bits.is_br, issue_slots[17].out_uop.is_br connect issue_slots[14].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned connect issue_slots[14].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned connect issue_slots[14].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state connect issue_slots[14].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std connect issue_slots[14].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta connect issue_slots[14].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load connect issue_slots[14].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd connect issue_slots[14].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw connect issue_slots[14].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn connect issue_slots[14].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel connect issue_slots[14].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel connect issue_slots[14].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel connect issue_slots[14].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type connect issue_slots[14].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code connect issue_slots[14].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type connect issue_slots[14].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc connect issue_slots[14].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc connect issue_slots[14].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst connect issue_slots[14].in_uop.bits.inst, issue_slots[17].out_uop.inst connect issue_slots[14].in_uop.bits.uopc, issue_slots[17].out_uop.uopc node _issue_slots_14_clear_T = neq(_WIRE_17, UInt<1>(0h0)) connect issue_slots[14].clear, _issue_slots_14_clear_T connect issue_slots[15].in_uop.valid, UInt<1>(0h0) connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd connect issue_slots[15].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb connect issue_slots[15].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr connect issue_slots[15].in_uop.bits.is_br, issue_slots[16].out_uop.is_br connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned connect issue_slots[15].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type connect issue_slots[15].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code connect issue_slots[15].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst connect issue_slots[15].in_uop.bits.uopc, issue_slots[16].out_uop.uopc node _T_305 = eq(_WIRE_19, UInt<1>(0h1)) when _T_305 : connect issue_slots[15].in_uop.valid, issue_slots[16].will_be_valid connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[16].out_uop.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[16].out_uop.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[16].out_uop.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[16].out_uop.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[16].out_uop.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[16].out_uop.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[16].out_uop.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_single, issue_slots[16].out_uop.fp_single connect issue_slots[15].in_uop.bits.fp_val, issue_slots[16].out_uop.fp_val connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[16].out_uop.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[16].out_uop.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[16].out_uop.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[16].out_uop.dst_rtype connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[16].out_uop.ldst_val connect issue_slots[15].in_uop.bits.lrs3, issue_slots[16].out_uop.lrs3 connect issue_slots[15].in_uop.bits.lrs2, issue_slots[16].out_uop.lrs2 connect issue_slots[15].in_uop.bits.lrs1, issue_slots[16].out_uop.lrs1 connect issue_slots[15].in_uop.bits.ldst, issue_slots[16].out_uop.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[16].out_uop.ldst_is_rs1 connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[16].out_uop.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, issue_slots[16].out_uop.is_unique connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[16].out_uop.is_sys_pc2epc connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[16].out_uop.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[16].out_uop.uses_ldq connect issue_slots[15].in_uop.bits.is_amo, issue_slots[16].out_uop.is_amo connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[16].out_uop.is_fencei connect issue_slots[15].in_uop.bits.is_fence, issue_slots[16].out_uop.is_fence connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[16].out_uop.mem_signed connect issue_slots[15].in_uop.bits.mem_size, issue_slots[16].out_uop.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[16].out_uop.mem_cmd connect issue_slots[15].in_uop.bits.bypassable, issue_slots[16].out_uop.bypassable connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[16].out_uop.exc_cause connect issue_slots[15].in_uop.bits.exception, issue_slots[16].out_uop.exception connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[16].out_uop.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[16].out_uop.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[16].out_uop.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[16].out_uop.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[16].out_uop.prs1_busy connect issue_slots[15].in_uop.bits.ppred, issue_slots[16].out_uop.ppred connect issue_slots[15].in_uop.bits.prs3, issue_slots[16].out_uop.prs3 connect issue_slots[15].in_uop.bits.prs2, issue_slots[16].out_uop.prs2 connect issue_slots[15].in_uop.bits.prs1, issue_slots[16].out_uop.prs1 connect issue_slots[15].in_uop.bits.pdst, issue_slots[16].out_uop.pdst connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[16].out_uop.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[16].out_uop.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[16].out_uop.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[16].out_uop.rob_idx connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[16].out_uop.csr_addr connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[16].out_uop.imm_packed connect issue_slots[15].in_uop.bits.taken, issue_slots[16].out_uop.taken connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[16].out_uop.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[16].out_uop.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[16].out_uop.ftq_idx connect issue_slots[15].in_uop.bits.br_tag, issue_slots[16].out_uop.br_tag connect issue_slots[15].in_uop.bits.br_mask, issue_slots[16].out_uop.br_mask connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[16].out_uop.is_sfb connect issue_slots[15].in_uop.bits.is_jal, issue_slots[16].out_uop.is_jal connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[16].out_uop.is_jalr connect issue_slots[15].in_uop.bits.is_br, issue_slots[16].out_uop.is_br connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[16].out_uop.iw_p2_poisoned connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[16].out_uop.iw_p1_poisoned connect issue_slots[15].in_uop.bits.iw_state, issue_slots[16].out_uop.iw_state connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[16].out_uop.ctrl.is_std connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[16].out_uop.ctrl.is_sta connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[16].out_uop.ctrl.is_load connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[16].out_uop.ctrl.csr_cmd connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[16].out_uop.ctrl.fcn_dw connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[16].out_uop.ctrl.op_fcn connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[16].out_uop.ctrl.imm_sel connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[16].out_uop.ctrl.op2_sel connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[16].out_uop.ctrl.op1_sel connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[16].out_uop.ctrl.br_type connect issue_slots[15].in_uop.bits.fu_code, issue_slots[16].out_uop.fu_code connect issue_slots[15].in_uop.bits.iq_type, issue_slots[16].out_uop.iq_type connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[16].out_uop.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[16].out_uop.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[16].out_uop.debug_inst connect issue_slots[15].in_uop.bits.inst, issue_slots[16].out_uop.inst connect issue_slots[15].in_uop.bits.uopc, issue_slots[16].out_uop.uopc node _T_306 = eq(_WIRE_20, UInt<2>(0h2)) when _T_306 : connect issue_slots[15].in_uop.valid, issue_slots[17].will_be_valid connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single connect issue_slots[15].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val connect issue_slots[15].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 connect issue_slots[15].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 connect issue_slots[15].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 connect issue_slots[15].in_uop.bits.ldst, issue_slots[17].out_uop.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq connect issue_slots[15].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei connect issue_slots[15].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed connect issue_slots[15].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd connect issue_slots[15].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause connect issue_slots[15].in_uop.bits.exception, issue_slots[17].out_uop.exception connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy connect issue_slots[15].in_uop.bits.ppred, issue_slots[17].out_uop.ppred connect issue_slots[15].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 connect issue_slots[15].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 connect issue_slots[15].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 connect issue_slots[15].in_uop.bits.pdst, issue_slots[17].out_uop.pdst connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed connect issue_slots[15].in_uop.bits.taken, issue_slots[17].out_uop.taken connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx connect issue_slots[15].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag connect issue_slots[15].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb connect issue_slots[15].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr connect issue_slots[15].in_uop.bits.is_br, issue_slots[17].out_uop.is_br connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned connect issue_slots[15].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type connect issue_slots[15].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code connect issue_slots[15].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst connect issue_slots[15].in_uop.bits.inst, issue_slots[17].out_uop.inst connect issue_slots[15].in_uop.bits.uopc, issue_slots[17].out_uop.uopc node _T_307 = eq(_WIRE_21, UInt<3>(0h4)) when _T_307 : connect issue_slots[15].in_uop.valid, issue_slots[18].will_be_valid connect issue_slots[15].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc connect issue_slots[15].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc connect issue_slots[15].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if connect issue_slots[15].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if connect issue_slots[15].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if connect issue_slots[15].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if connect issue_slots[15].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if connect issue_slots[15].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single connect issue_slots[15].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val connect issue_slots[15].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en connect issue_slots[15].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype connect issue_slots[15].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype connect issue_slots[15].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype connect issue_slots[15].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val connect issue_slots[15].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 connect issue_slots[15].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 connect issue_slots[15].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 connect issue_slots[15].in_uop.bits.ldst, issue_slots[18].out_uop.ldst connect issue_slots[15].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 connect issue_slots[15].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit connect issue_slots[15].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique connect issue_slots[15].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc connect issue_slots[15].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq connect issue_slots[15].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq connect issue_slots[15].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo connect issue_slots[15].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei connect issue_slots[15].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence connect issue_slots[15].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed connect issue_slots[15].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size connect issue_slots[15].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd connect issue_slots[15].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable connect issue_slots[15].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause connect issue_slots[15].in_uop.bits.exception, issue_slots[18].out_uop.exception connect issue_slots[15].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst connect issue_slots[15].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy connect issue_slots[15].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy connect issue_slots[15].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy connect issue_slots[15].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy connect issue_slots[15].in_uop.bits.ppred, issue_slots[18].out_uop.ppred connect issue_slots[15].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 connect issue_slots[15].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 connect issue_slots[15].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 connect issue_slots[15].in_uop.bits.pdst, issue_slots[18].out_uop.pdst connect issue_slots[15].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx connect issue_slots[15].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx connect issue_slots[15].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx connect issue_slots[15].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx connect issue_slots[15].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr connect issue_slots[15].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed connect issue_slots[15].in_uop.bits.taken, issue_slots[18].out_uop.taken connect issue_slots[15].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob connect issue_slots[15].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst connect issue_slots[15].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx connect issue_slots[15].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag connect issue_slots[15].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask connect issue_slots[15].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb connect issue_slots[15].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal connect issue_slots[15].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr connect issue_slots[15].in_uop.bits.is_br, issue_slots[18].out_uop.is_br connect issue_slots[15].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned connect issue_slots[15].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned connect issue_slots[15].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state connect issue_slots[15].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std connect issue_slots[15].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta connect issue_slots[15].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load connect issue_slots[15].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd connect issue_slots[15].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw connect issue_slots[15].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn connect issue_slots[15].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel connect issue_slots[15].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel connect issue_slots[15].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel connect issue_slots[15].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type connect issue_slots[15].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code connect issue_slots[15].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type connect issue_slots[15].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc connect issue_slots[15].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc connect issue_slots[15].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst connect issue_slots[15].in_uop.bits.inst, issue_slots[18].out_uop.inst connect issue_slots[15].in_uop.bits.uopc, issue_slots[18].out_uop.uopc node _issue_slots_15_clear_T = neq(_WIRE_18, UInt<1>(0h0)) connect issue_slots[15].clear, _issue_slots_15_clear_T connect issue_slots[16].in_uop.valid, UInt<1>(0h0) connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if connect issue_slots[16].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd connect issue_slots[16].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb connect issue_slots[16].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr connect issue_slots[16].in_uop.bits.is_br, issue_slots[17].out_uop.is_br connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned connect issue_slots[16].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type connect issue_slots[16].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code connect issue_slots[16].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst connect issue_slots[16].in_uop.bits.uopc, issue_slots[17].out_uop.uopc node _T_308 = eq(_WIRE_20, UInt<1>(0h1)) when _T_308 : connect issue_slots[16].in_uop.valid, issue_slots[17].will_be_valid connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[17].out_uop.debug_tsrc connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[17].out_uop.debug_fsrc connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[17].out_uop.bp_xcpt_if connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[17].out_uop.bp_debug_if connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[17].out_uop.xcpt_ma_if connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[17].out_uop.xcpt_ae_if connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[17].out_uop.xcpt_pf_if connect issue_slots[16].in_uop.bits.fp_single, issue_slots[17].out_uop.fp_single connect issue_slots[16].in_uop.bits.fp_val, issue_slots[17].out_uop.fp_val connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[17].out_uop.frs3_en connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[17].out_uop.lrs2_rtype connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[17].out_uop.lrs1_rtype connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[17].out_uop.dst_rtype connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[17].out_uop.ldst_val connect issue_slots[16].in_uop.bits.lrs3, issue_slots[17].out_uop.lrs3 connect issue_slots[16].in_uop.bits.lrs2, issue_slots[17].out_uop.lrs2 connect issue_slots[16].in_uop.bits.lrs1, issue_slots[17].out_uop.lrs1 connect issue_slots[16].in_uop.bits.ldst, issue_slots[17].out_uop.ldst connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[17].out_uop.ldst_is_rs1 connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[17].out_uop.flush_on_commit connect issue_slots[16].in_uop.bits.is_unique, issue_slots[17].out_uop.is_unique connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[17].out_uop.is_sys_pc2epc connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[17].out_uop.uses_stq connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[17].out_uop.uses_ldq connect issue_slots[16].in_uop.bits.is_amo, issue_slots[17].out_uop.is_amo connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[17].out_uop.is_fencei connect issue_slots[16].in_uop.bits.is_fence, issue_slots[17].out_uop.is_fence connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[17].out_uop.mem_signed connect issue_slots[16].in_uop.bits.mem_size, issue_slots[17].out_uop.mem_size connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[17].out_uop.mem_cmd connect issue_slots[16].in_uop.bits.bypassable, issue_slots[17].out_uop.bypassable connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[17].out_uop.exc_cause connect issue_slots[16].in_uop.bits.exception, issue_slots[17].out_uop.exception connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[17].out_uop.stale_pdst connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[17].out_uop.ppred_busy connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[17].out_uop.prs3_busy connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[17].out_uop.prs2_busy connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[17].out_uop.prs1_busy connect issue_slots[16].in_uop.bits.ppred, issue_slots[17].out_uop.ppred connect issue_slots[16].in_uop.bits.prs3, issue_slots[17].out_uop.prs3 connect issue_slots[16].in_uop.bits.prs2, issue_slots[17].out_uop.prs2 connect issue_slots[16].in_uop.bits.prs1, issue_slots[17].out_uop.prs1 connect issue_slots[16].in_uop.bits.pdst, issue_slots[17].out_uop.pdst connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[17].out_uop.rxq_idx connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[17].out_uop.stq_idx connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[17].out_uop.ldq_idx connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[17].out_uop.rob_idx connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[17].out_uop.csr_addr connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[17].out_uop.imm_packed connect issue_slots[16].in_uop.bits.taken, issue_slots[17].out_uop.taken connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[17].out_uop.pc_lob connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[17].out_uop.edge_inst connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[17].out_uop.ftq_idx connect issue_slots[16].in_uop.bits.br_tag, issue_slots[17].out_uop.br_tag connect issue_slots[16].in_uop.bits.br_mask, issue_slots[17].out_uop.br_mask connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[17].out_uop.is_sfb connect issue_slots[16].in_uop.bits.is_jal, issue_slots[17].out_uop.is_jal connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[17].out_uop.is_jalr connect issue_slots[16].in_uop.bits.is_br, issue_slots[17].out_uop.is_br connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[17].out_uop.iw_p2_poisoned connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[17].out_uop.iw_p1_poisoned connect issue_slots[16].in_uop.bits.iw_state, issue_slots[17].out_uop.iw_state connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[17].out_uop.ctrl.is_std connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[17].out_uop.ctrl.is_sta connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[17].out_uop.ctrl.is_load connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[17].out_uop.ctrl.csr_cmd connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[17].out_uop.ctrl.fcn_dw connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[17].out_uop.ctrl.op_fcn connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[17].out_uop.ctrl.imm_sel connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[17].out_uop.ctrl.op2_sel connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[17].out_uop.ctrl.op1_sel connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[17].out_uop.ctrl.br_type connect issue_slots[16].in_uop.bits.fu_code, issue_slots[17].out_uop.fu_code connect issue_slots[16].in_uop.bits.iq_type, issue_slots[17].out_uop.iq_type connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[17].out_uop.debug_pc connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[17].out_uop.is_rvc connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[17].out_uop.debug_inst connect issue_slots[16].in_uop.bits.inst, issue_slots[17].out_uop.inst connect issue_slots[16].in_uop.bits.uopc, issue_slots[17].out_uop.uopc node _T_309 = eq(_WIRE_21, UInt<2>(0h2)) when _T_309 : connect issue_slots[16].in_uop.valid, issue_slots[18].will_be_valid connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if connect issue_slots[16].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single connect issue_slots[16].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val connect issue_slots[16].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 connect issue_slots[16].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 connect issue_slots[16].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 connect issue_slots[16].in_uop.bits.ldst, issue_slots[18].out_uop.ldst connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit connect issue_slots[16].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq connect issue_slots[16].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei connect issue_slots[16].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed connect issue_slots[16].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd connect issue_slots[16].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause connect issue_slots[16].in_uop.bits.exception, issue_slots[18].out_uop.exception connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy connect issue_slots[16].in_uop.bits.ppred, issue_slots[18].out_uop.ppred connect issue_slots[16].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 connect issue_slots[16].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 connect issue_slots[16].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 connect issue_slots[16].in_uop.bits.pdst, issue_slots[18].out_uop.pdst connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed connect issue_slots[16].in_uop.bits.taken, issue_slots[18].out_uop.taken connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx connect issue_slots[16].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag connect issue_slots[16].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb connect issue_slots[16].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr connect issue_slots[16].in_uop.bits.is_br, issue_slots[18].out_uop.is_br connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned connect issue_slots[16].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type connect issue_slots[16].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code connect issue_slots[16].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst connect issue_slots[16].in_uop.bits.inst, issue_slots[18].out_uop.inst connect issue_slots[16].in_uop.bits.uopc, issue_slots[18].out_uop.uopc node _T_310 = eq(_WIRE_22, UInt<3>(0h4)) when _T_310 : connect issue_slots[16].in_uop.valid, issue_slots[19].will_be_valid connect issue_slots[16].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc connect issue_slots[16].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc connect issue_slots[16].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if connect issue_slots[16].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if connect issue_slots[16].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if connect issue_slots[16].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if connect issue_slots[16].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if connect issue_slots[16].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single connect issue_slots[16].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val connect issue_slots[16].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en connect issue_slots[16].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype connect issue_slots[16].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype connect issue_slots[16].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype connect issue_slots[16].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val connect issue_slots[16].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 connect issue_slots[16].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 connect issue_slots[16].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 connect issue_slots[16].in_uop.bits.ldst, issue_slots[19].out_uop.ldst connect issue_slots[16].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 connect issue_slots[16].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit connect issue_slots[16].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique connect issue_slots[16].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc connect issue_slots[16].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq connect issue_slots[16].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq connect issue_slots[16].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo connect issue_slots[16].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei connect issue_slots[16].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence connect issue_slots[16].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed connect issue_slots[16].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size connect issue_slots[16].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd connect issue_slots[16].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable connect issue_slots[16].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause connect issue_slots[16].in_uop.bits.exception, issue_slots[19].out_uop.exception connect issue_slots[16].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst connect issue_slots[16].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy connect issue_slots[16].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy connect issue_slots[16].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy connect issue_slots[16].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy connect issue_slots[16].in_uop.bits.ppred, issue_slots[19].out_uop.ppred connect issue_slots[16].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 connect issue_slots[16].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 connect issue_slots[16].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 connect issue_slots[16].in_uop.bits.pdst, issue_slots[19].out_uop.pdst connect issue_slots[16].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx connect issue_slots[16].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx connect issue_slots[16].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx connect issue_slots[16].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx connect issue_slots[16].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr connect issue_slots[16].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed connect issue_slots[16].in_uop.bits.taken, issue_slots[19].out_uop.taken connect issue_slots[16].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob connect issue_slots[16].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst connect issue_slots[16].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx connect issue_slots[16].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag connect issue_slots[16].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask connect issue_slots[16].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb connect issue_slots[16].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal connect issue_slots[16].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr connect issue_slots[16].in_uop.bits.is_br, issue_slots[19].out_uop.is_br connect issue_slots[16].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned connect issue_slots[16].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned connect issue_slots[16].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state connect issue_slots[16].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std connect issue_slots[16].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta connect issue_slots[16].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load connect issue_slots[16].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd connect issue_slots[16].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw connect issue_slots[16].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn connect issue_slots[16].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel connect issue_slots[16].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel connect issue_slots[16].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel connect issue_slots[16].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type connect issue_slots[16].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code connect issue_slots[16].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type connect issue_slots[16].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc connect issue_slots[16].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc connect issue_slots[16].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst connect issue_slots[16].in_uop.bits.inst, issue_slots[19].out_uop.inst connect issue_slots[16].in_uop.bits.uopc, issue_slots[19].out_uop.uopc node _issue_slots_16_clear_T = neq(_WIRE_19, UInt<1>(0h0)) connect issue_slots[16].clear, _issue_slots_16_clear_T connect issue_slots[17].in_uop.valid, UInt<1>(0h0) connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if connect issue_slots[17].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd connect issue_slots[17].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb connect issue_slots[17].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr connect issue_slots[17].in_uop.bits.is_br, issue_slots[18].out_uop.is_br connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned connect issue_slots[17].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type connect issue_slots[17].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code connect issue_slots[17].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst connect issue_slots[17].in_uop.bits.uopc, issue_slots[18].out_uop.uopc node _T_311 = eq(_WIRE_21, UInt<1>(0h1)) when _T_311 : connect issue_slots[17].in_uop.valid, issue_slots[18].will_be_valid connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[18].out_uop.debug_tsrc connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[18].out_uop.debug_fsrc connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[18].out_uop.bp_xcpt_if connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[18].out_uop.bp_debug_if connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[18].out_uop.xcpt_ma_if connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[18].out_uop.xcpt_ae_if connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[18].out_uop.xcpt_pf_if connect issue_slots[17].in_uop.bits.fp_single, issue_slots[18].out_uop.fp_single connect issue_slots[17].in_uop.bits.fp_val, issue_slots[18].out_uop.fp_val connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[18].out_uop.frs3_en connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[18].out_uop.lrs2_rtype connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[18].out_uop.lrs1_rtype connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[18].out_uop.dst_rtype connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[18].out_uop.ldst_val connect issue_slots[17].in_uop.bits.lrs3, issue_slots[18].out_uop.lrs3 connect issue_slots[17].in_uop.bits.lrs2, issue_slots[18].out_uop.lrs2 connect issue_slots[17].in_uop.bits.lrs1, issue_slots[18].out_uop.lrs1 connect issue_slots[17].in_uop.bits.ldst, issue_slots[18].out_uop.ldst connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[18].out_uop.ldst_is_rs1 connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[18].out_uop.flush_on_commit connect issue_slots[17].in_uop.bits.is_unique, issue_slots[18].out_uop.is_unique connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[18].out_uop.is_sys_pc2epc connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[18].out_uop.uses_stq connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[18].out_uop.uses_ldq connect issue_slots[17].in_uop.bits.is_amo, issue_slots[18].out_uop.is_amo connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[18].out_uop.is_fencei connect issue_slots[17].in_uop.bits.is_fence, issue_slots[18].out_uop.is_fence connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[18].out_uop.mem_signed connect issue_slots[17].in_uop.bits.mem_size, issue_slots[18].out_uop.mem_size connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[18].out_uop.mem_cmd connect issue_slots[17].in_uop.bits.bypassable, issue_slots[18].out_uop.bypassable connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[18].out_uop.exc_cause connect issue_slots[17].in_uop.bits.exception, issue_slots[18].out_uop.exception connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[18].out_uop.stale_pdst connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[18].out_uop.ppred_busy connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[18].out_uop.prs3_busy connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[18].out_uop.prs2_busy connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[18].out_uop.prs1_busy connect issue_slots[17].in_uop.bits.ppred, issue_slots[18].out_uop.ppred connect issue_slots[17].in_uop.bits.prs3, issue_slots[18].out_uop.prs3 connect issue_slots[17].in_uop.bits.prs2, issue_slots[18].out_uop.prs2 connect issue_slots[17].in_uop.bits.prs1, issue_slots[18].out_uop.prs1 connect issue_slots[17].in_uop.bits.pdst, issue_slots[18].out_uop.pdst connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[18].out_uop.rxq_idx connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[18].out_uop.stq_idx connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[18].out_uop.ldq_idx connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[18].out_uop.rob_idx connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[18].out_uop.csr_addr connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[18].out_uop.imm_packed connect issue_slots[17].in_uop.bits.taken, issue_slots[18].out_uop.taken connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[18].out_uop.pc_lob connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[18].out_uop.edge_inst connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[18].out_uop.ftq_idx connect issue_slots[17].in_uop.bits.br_tag, issue_slots[18].out_uop.br_tag connect issue_slots[17].in_uop.bits.br_mask, issue_slots[18].out_uop.br_mask connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[18].out_uop.is_sfb connect issue_slots[17].in_uop.bits.is_jal, issue_slots[18].out_uop.is_jal connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[18].out_uop.is_jalr connect issue_slots[17].in_uop.bits.is_br, issue_slots[18].out_uop.is_br connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[18].out_uop.iw_p2_poisoned connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[18].out_uop.iw_p1_poisoned connect issue_slots[17].in_uop.bits.iw_state, issue_slots[18].out_uop.iw_state connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[18].out_uop.ctrl.is_std connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[18].out_uop.ctrl.is_sta connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[18].out_uop.ctrl.is_load connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[18].out_uop.ctrl.csr_cmd connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[18].out_uop.ctrl.fcn_dw connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[18].out_uop.ctrl.op_fcn connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[18].out_uop.ctrl.imm_sel connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[18].out_uop.ctrl.op2_sel connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[18].out_uop.ctrl.op1_sel connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[18].out_uop.ctrl.br_type connect issue_slots[17].in_uop.bits.fu_code, issue_slots[18].out_uop.fu_code connect issue_slots[17].in_uop.bits.iq_type, issue_slots[18].out_uop.iq_type connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[18].out_uop.debug_pc connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[18].out_uop.is_rvc connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[18].out_uop.debug_inst connect issue_slots[17].in_uop.bits.inst, issue_slots[18].out_uop.inst connect issue_slots[17].in_uop.bits.uopc, issue_slots[18].out_uop.uopc node _T_312 = eq(_WIRE_22, UInt<2>(0h2)) when _T_312 : connect issue_slots[17].in_uop.valid, issue_slots[19].will_be_valid connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if connect issue_slots[17].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single connect issue_slots[17].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val connect issue_slots[17].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 connect issue_slots[17].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 connect issue_slots[17].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 connect issue_slots[17].in_uop.bits.ldst, issue_slots[19].out_uop.ldst connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit connect issue_slots[17].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq connect issue_slots[17].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei connect issue_slots[17].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed connect issue_slots[17].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd connect issue_slots[17].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause connect issue_slots[17].in_uop.bits.exception, issue_slots[19].out_uop.exception connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy connect issue_slots[17].in_uop.bits.ppred, issue_slots[19].out_uop.ppred connect issue_slots[17].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 connect issue_slots[17].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 connect issue_slots[17].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 connect issue_slots[17].in_uop.bits.pdst, issue_slots[19].out_uop.pdst connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed connect issue_slots[17].in_uop.bits.taken, issue_slots[19].out_uop.taken connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx connect issue_slots[17].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag connect issue_slots[17].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb connect issue_slots[17].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr connect issue_slots[17].in_uop.bits.is_br, issue_slots[19].out_uop.is_br connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned connect issue_slots[17].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type connect issue_slots[17].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code connect issue_slots[17].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst connect issue_slots[17].in_uop.bits.inst, issue_slots[19].out_uop.inst connect issue_slots[17].in_uop.bits.uopc, issue_slots[19].out_uop.uopc node _T_313 = eq(_WIRE_23, UInt<3>(0h4)) when _T_313 : connect issue_slots[17].in_uop.valid, issue_slots[20].will_be_valid connect issue_slots[17].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc connect issue_slots[17].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc connect issue_slots[17].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if connect issue_slots[17].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if connect issue_slots[17].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if connect issue_slots[17].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if connect issue_slots[17].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if connect issue_slots[17].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single connect issue_slots[17].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val connect issue_slots[17].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en connect issue_slots[17].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype connect issue_slots[17].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype connect issue_slots[17].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype connect issue_slots[17].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val connect issue_slots[17].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3 connect issue_slots[17].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2 connect issue_slots[17].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1 connect issue_slots[17].in_uop.bits.ldst, issue_slots[20].out_uop.ldst connect issue_slots[17].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1 connect issue_slots[17].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit connect issue_slots[17].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique connect issue_slots[17].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc connect issue_slots[17].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq connect issue_slots[17].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq connect issue_slots[17].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo connect issue_slots[17].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei connect issue_slots[17].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence connect issue_slots[17].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed connect issue_slots[17].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size connect issue_slots[17].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd connect issue_slots[17].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable connect issue_slots[17].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause connect issue_slots[17].in_uop.bits.exception, issue_slots[20].out_uop.exception connect issue_slots[17].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst connect issue_slots[17].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy connect issue_slots[17].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy connect issue_slots[17].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy connect issue_slots[17].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy connect issue_slots[17].in_uop.bits.ppred, issue_slots[20].out_uop.ppred connect issue_slots[17].in_uop.bits.prs3, issue_slots[20].out_uop.prs3 connect issue_slots[17].in_uop.bits.prs2, issue_slots[20].out_uop.prs2 connect issue_slots[17].in_uop.bits.prs1, issue_slots[20].out_uop.prs1 connect issue_slots[17].in_uop.bits.pdst, issue_slots[20].out_uop.pdst connect issue_slots[17].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx connect issue_slots[17].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx connect issue_slots[17].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx connect issue_slots[17].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx connect issue_slots[17].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr connect issue_slots[17].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed connect issue_slots[17].in_uop.bits.taken, issue_slots[20].out_uop.taken connect issue_slots[17].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob connect issue_slots[17].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst connect issue_slots[17].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx connect issue_slots[17].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag connect issue_slots[17].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask connect issue_slots[17].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb connect issue_slots[17].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal connect issue_slots[17].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr connect issue_slots[17].in_uop.bits.is_br, issue_slots[20].out_uop.is_br connect issue_slots[17].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned connect issue_slots[17].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned connect issue_slots[17].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state connect issue_slots[17].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std connect issue_slots[17].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta connect issue_slots[17].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load connect issue_slots[17].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd connect issue_slots[17].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw connect issue_slots[17].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn connect issue_slots[17].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel connect issue_slots[17].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel connect issue_slots[17].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel connect issue_slots[17].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type connect issue_slots[17].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code connect issue_slots[17].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type connect issue_slots[17].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc connect issue_slots[17].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc connect issue_slots[17].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst connect issue_slots[17].in_uop.bits.inst, issue_slots[20].out_uop.inst connect issue_slots[17].in_uop.bits.uopc, issue_slots[20].out_uop.uopc node _issue_slots_17_clear_T = neq(_WIRE_20, UInt<1>(0h0)) connect issue_slots[17].clear, _issue_slots_17_clear_T connect issue_slots[18].in_uop.valid, UInt<1>(0h0) connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if connect issue_slots[18].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd connect issue_slots[18].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb connect issue_slots[18].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr connect issue_slots[18].in_uop.bits.is_br, issue_slots[19].out_uop.is_br connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned connect issue_slots[18].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type connect issue_slots[18].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code connect issue_slots[18].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst connect issue_slots[18].in_uop.bits.uopc, issue_slots[19].out_uop.uopc node _T_314 = eq(_WIRE_22, UInt<1>(0h1)) when _T_314 : connect issue_slots[18].in_uop.valid, issue_slots[19].will_be_valid connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[19].out_uop.debug_tsrc connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[19].out_uop.debug_fsrc connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[19].out_uop.bp_xcpt_if connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[19].out_uop.bp_debug_if connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[19].out_uop.xcpt_ma_if connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[19].out_uop.xcpt_ae_if connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[19].out_uop.xcpt_pf_if connect issue_slots[18].in_uop.bits.fp_single, issue_slots[19].out_uop.fp_single connect issue_slots[18].in_uop.bits.fp_val, issue_slots[19].out_uop.fp_val connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[19].out_uop.frs3_en connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[19].out_uop.lrs2_rtype connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[19].out_uop.lrs1_rtype connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[19].out_uop.dst_rtype connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[19].out_uop.ldst_val connect issue_slots[18].in_uop.bits.lrs3, issue_slots[19].out_uop.lrs3 connect issue_slots[18].in_uop.bits.lrs2, issue_slots[19].out_uop.lrs2 connect issue_slots[18].in_uop.bits.lrs1, issue_slots[19].out_uop.lrs1 connect issue_slots[18].in_uop.bits.ldst, issue_slots[19].out_uop.ldst connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[19].out_uop.ldst_is_rs1 connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[19].out_uop.flush_on_commit connect issue_slots[18].in_uop.bits.is_unique, issue_slots[19].out_uop.is_unique connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[19].out_uop.is_sys_pc2epc connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[19].out_uop.uses_stq connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[19].out_uop.uses_ldq connect issue_slots[18].in_uop.bits.is_amo, issue_slots[19].out_uop.is_amo connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[19].out_uop.is_fencei connect issue_slots[18].in_uop.bits.is_fence, issue_slots[19].out_uop.is_fence connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[19].out_uop.mem_signed connect issue_slots[18].in_uop.bits.mem_size, issue_slots[19].out_uop.mem_size connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[19].out_uop.mem_cmd connect issue_slots[18].in_uop.bits.bypassable, issue_slots[19].out_uop.bypassable connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[19].out_uop.exc_cause connect issue_slots[18].in_uop.bits.exception, issue_slots[19].out_uop.exception connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[19].out_uop.stale_pdst connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[19].out_uop.ppred_busy connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[19].out_uop.prs3_busy connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[19].out_uop.prs2_busy connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[19].out_uop.prs1_busy connect issue_slots[18].in_uop.bits.ppred, issue_slots[19].out_uop.ppred connect issue_slots[18].in_uop.bits.prs3, issue_slots[19].out_uop.prs3 connect issue_slots[18].in_uop.bits.prs2, issue_slots[19].out_uop.prs2 connect issue_slots[18].in_uop.bits.prs1, issue_slots[19].out_uop.prs1 connect issue_slots[18].in_uop.bits.pdst, issue_slots[19].out_uop.pdst connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[19].out_uop.rxq_idx connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[19].out_uop.stq_idx connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[19].out_uop.ldq_idx connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[19].out_uop.rob_idx connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[19].out_uop.csr_addr connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[19].out_uop.imm_packed connect issue_slots[18].in_uop.bits.taken, issue_slots[19].out_uop.taken connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[19].out_uop.pc_lob connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[19].out_uop.edge_inst connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[19].out_uop.ftq_idx connect issue_slots[18].in_uop.bits.br_tag, issue_slots[19].out_uop.br_tag connect issue_slots[18].in_uop.bits.br_mask, issue_slots[19].out_uop.br_mask connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[19].out_uop.is_sfb connect issue_slots[18].in_uop.bits.is_jal, issue_slots[19].out_uop.is_jal connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[19].out_uop.is_jalr connect issue_slots[18].in_uop.bits.is_br, issue_slots[19].out_uop.is_br connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[19].out_uop.iw_p2_poisoned connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[19].out_uop.iw_p1_poisoned connect issue_slots[18].in_uop.bits.iw_state, issue_slots[19].out_uop.iw_state connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[19].out_uop.ctrl.is_std connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[19].out_uop.ctrl.is_sta connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[19].out_uop.ctrl.is_load connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[19].out_uop.ctrl.csr_cmd connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[19].out_uop.ctrl.fcn_dw connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[19].out_uop.ctrl.op_fcn connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[19].out_uop.ctrl.imm_sel connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[19].out_uop.ctrl.op2_sel connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[19].out_uop.ctrl.op1_sel connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[19].out_uop.ctrl.br_type connect issue_slots[18].in_uop.bits.fu_code, issue_slots[19].out_uop.fu_code connect issue_slots[18].in_uop.bits.iq_type, issue_slots[19].out_uop.iq_type connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[19].out_uop.debug_pc connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[19].out_uop.is_rvc connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[19].out_uop.debug_inst connect issue_slots[18].in_uop.bits.inst, issue_slots[19].out_uop.inst connect issue_slots[18].in_uop.bits.uopc, issue_slots[19].out_uop.uopc node _T_315 = eq(_WIRE_23, UInt<2>(0h2)) when _T_315 : connect issue_slots[18].in_uop.valid, issue_slots[20].will_be_valid connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if connect issue_slots[18].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single connect issue_slots[18].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val connect issue_slots[18].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3 connect issue_slots[18].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2 connect issue_slots[18].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1 connect issue_slots[18].in_uop.bits.ldst, issue_slots[20].out_uop.ldst connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1 connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit connect issue_slots[18].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq connect issue_slots[18].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei connect issue_slots[18].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed connect issue_slots[18].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd connect issue_slots[18].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause connect issue_slots[18].in_uop.bits.exception, issue_slots[20].out_uop.exception connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy connect issue_slots[18].in_uop.bits.ppred, issue_slots[20].out_uop.ppred connect issue_slots[18].in_uop.bits.prs3, issue_slots[20].out_uop.prs3 connect issue_slots[18].in_uop.bits.prs2, issue_slots[20].out_uop.prs2 connect issue_slots[18].in_uop.bits.prs1, issue_slots[20].out_uop.prs1 connect issue_slots[18].in_uop.bits.pdst, issue_slots[20].out_uop.pdst connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed connect issue_slots[18].in_uop.bits.taken, issue_slots[20].out_uop.taken connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx connect issue_slots[18].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag connect issue_slots[18].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb connect issue_slots[18].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr connect issue_slots[18].in_uop.bits.is_br, issue_slots[20].out_uop.is_br connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned connect issue_slots[18].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type connect issue_slots[18].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code connect issue_slots[18].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst connect issue_slots[18].in_uop.bits.inst, issue_slots[20].out_uop.inst connect issue_slots[18].in_uop.bits.uopc, issue_slots[20].out_uop.uopc node _T_316 = eq(_WIRE_24, UInt<3>(0h4)) when _T_316 : connect issue_slots[18].in_uop.valid, issue_slots[21].will_be_valid connect issue_slots[18].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc connect issue_slots[18].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc connect issue_slots[18].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if connect issue_slots[18].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if connect issue_slots[18].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if connect issue_slots[18].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if connect issue_slots[18].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if connect issue_slots[18].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single connect issue_slots[18].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val connect issue_slots[18].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en connect issue_slots[18].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype connect issue_slots[18].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype connect issue_slots[18].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype connect issue_slots[18].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val connect issue_slots[18].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3 connect issue_slots[18].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2 connect issue_slots[18].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1 connect issue_slots[18].in_uop.bits.ldst, issue_slots[21].out_uop.ldst connect issue_slots[18].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1 connect issue_slots[18].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit connect issue_slots[18].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique connect issue_slots[18].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc connect issue_slots[18].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq connect issue_slots[18].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq connect issue_slots[18].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo connect issue_slots[18].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei connect issue_slots[18].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence connect issue_slots[18].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed connect issue_slots[18].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size connect issue_slots[18].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd connect issue_slots[18].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable connect issue_slots[18].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause connect issue_slots[18].in_uop.bits.exception, issue_slots[21].out_uop.exception connect issue_slots[18].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst connect issue_slots[18].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy connect issue_slots[18].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy connect issue_slots[18].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy connect issue_slots[18].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy connect issue_slots[18].in_uop.bits.ppred, issue_slots[21].out_uop.ppred connect issue_slots[18].in_uop.bits.prs3, issue_slots[21].out_uop.prs3 connect issue_slots[18].in_uop.bits.prs2, issue_slots[21].out_uop.prs2 connect issue_slots[18].in_uop.bits.prs1, issue_slots[21].out_uop.prs1 connect issue_slots[18].in_uop.bits.pdst, issue_slots[21].out_uop.pdst connect issue_slots[18].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx connect issue_slots[18].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx connect issue_slots[18].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx connect issue_slots[18].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx connect issue_slots[18].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr connect issue_slots[18].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed connect issue_slots[18].in_uop.bits.taken, issue_slots[21].out_uop.taken connect issue_slots[18].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob connect issue_slots[18].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst connect issue_slots[18].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx connect issue_slots[18].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag connect issue_slots[18].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask connect issue_slots[18].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb connect issue_slots[18].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal connect issue_slots[18].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr connect issue_slots[18].in_uop.bits.is_br, issue_slots[21].out_uop.is_br connect issue_slots[18].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned connect issue_slots[18].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned connect issue_slots[18].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state connect issue_slots[18].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std connect issue_slots[18].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta connect issue_slots[18].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load connect issue_slots[18].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd connect issue_slots[18].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw connect issue_slots[18].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn connect issue_slots[18].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel connect issue_slots[18].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel connect issue_slots[18].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel connect issue_slots[18].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type connect issue_slots[18].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code connect issue_slots[18].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type connect issue_slots[18].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc connect issue_slots[18].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc connect issue_slots[18].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst connect issue_slots[18].in_uop.bits.inst, issue_slots[21].out_uop.inst connect issue_slots[18].in_uop.bits.uopc, issue_slots[21].out_uop.uopc node _issue_slots_18_clear_T = neq(_WIRE_21, UInt<1>(0h0)) connect issue_slots[18].clear, _issue_slots_18_clear_T connect issue_slots[19].in_uop.valid, UInt<1>(0h0) connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if connect issue_slots[19].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single connect issue_slots[19].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val connect issue_slots[19].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3 connect issue_slots[19].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2 connect issue_slots[19].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1 connect issue_slots[19].in_uop.bits.ldst, issue_slots[20].out_uop.ldst connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1 connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit connect issue_slots[19].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq connect issue_slots[19].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei connect issue_slots[19].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed connect issue_slots[19].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd connect issue_slots[19].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause connect issue_slots[19].in_uop.bits.exception, issue_slots[20].out_uop.exception connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy connect issue_slots[19].in_uop.bits.ppred, issue_slots[20].out_uop.ppred connect issue_slots[19].in_uop.bits.prs3, issue_slots[20].out_uop.prs3 connect issue_slots[19].in_uop.bits.prs2, issue_slots[20].out_uop.prs2 connect issue_slots[19].in_uop.bits.prs1, issue_slots[20].out_uop.prs1 connect issue_slots[19].in_uop.bits.pdst, issue_slots[20].out_uop.pdst connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed connect issue_slots[19].in_uop.bits.taken, issue_slots[20].out_uop.taken connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx connect issue_slots[19].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag connect issue_slots[19].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb connect issue_slots[19].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr connect issue_slots[19].in_uop.bits.is_br, issue_slots[20].out_uop.is_br connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned connect issue_slots[19].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type connect issue_slots[19].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code connect issue_slots[19].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst connect issue_slots[19].in_uop.bits.inst, issue_slots[20].out_uop.inst connect issue_slots[19].in_uop.bits.uopc, issue_slots[20].out_uop.uopc node _T_317 = eq(_WIRE_23, UInt<1>(0h1)) when _T_317 : connect issue_slots[19].in_uop.valid, issue_slots[20].will_be_valid connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[20].out_uop.debug_tsrc connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[20].out_uop.debug_fsrc connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[20].out_uop.bp_xcpt_if connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[20].out_uop.bp_debug_if connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[20].out_uop.xcpt_ma_if connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[20].out_uop.xcpt_ae_if connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[20].out_uop.xcpt_pf_if connect issue_slots[19].in_uop.bits.fp_single, issue_slots[20].out_uop.fp_single connect issue_slots[19].in_uop.bits.fp_val, issue_slots[20].out_uop.fp_val connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[20].out_uop.frs3_en connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[20].out_uop.lrs2_rtype connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[20].out_uop.lrs1_rtype connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[20].out_uop.dst_rtype connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[20].out_uop.ldst_val connect issue_slots[19].in_uop.bits.lrs3, issue_slots[20].out_uop.lrs3 connect issue_slots[19].in_uop.bits.lrs2, issue_slots[20].out_uop.lrs2 connect issue_slots[19].in_uop.bits.lrs1, issue_slots[20].out_uop.lrs1 connect issue_slots[19].in_uop.bits.ldst, issue_slots[20].out_uop.ldst connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[20].out_uop.ldst_is_rs1 connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[20].out_uop.flush_on_commit connect issue_slots[19].in_uop.bits.is_unique, issue_slots[20].out_uop.is_unique connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[20].out_uop.is_sys_pc2epc connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[20].out_uop.uses_stq connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[20].out_uop.uses_ldq connect issue_slots[19].in_uop.bits.is_amo, issue_slots[20].out_uop.is_amo connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[20].out_uop.is_fencei connect issue_slots[19].in_uop.bits.is_fence, issue_slots[20].out_uop.is_fence connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[20].out_uop.mem_signed connect issue_slots[19].in_uop.bits.mem_size, issue_slots[20].out_uop.mem_size connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[20].out_uop.mem_cmd connect issue_slots[19].in_uop.bits.bypassable, issue_slots[20].out_uop.bypassable connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[20].out_uop.exc_cause connect issue_slots[19].in_uop.bits.exception, issue_slots[20].out_uop.exception connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[20].out_uop.stale_pdst connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[20].out_uop.ppred_busy connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[20].out_uop.prs3_busy connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[20].out_uop.prs2_busy connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[20].out_uop.prs1_busy connect issue_slots[19].in_uop.bits.ppred, issue_slots[20].out_uop.ppred connect issue_slots[19].in_uop.bits.prs3, issue_slots[20].out_uop.prs3 connect issue_slots[19].in_uop.bits.prs2, issue_slots[20].out_uop.prs2 connect issue_slots[19].in_uop.bits.prs1, issue_slots[20].out_uop.prs1 connect issue_slots[19].in_uop.bits.pdst, issue_slots[20].out_uop.pdst connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[20].out_uop.rxq_idx connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[20].out_uop.stq_idx connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[20].out_uop.ldq_idx connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[20].out_uop.rob_idx connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[20].out_uop.csr_addr connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[20].out_uop.imm_packed connect issue_slots[19].in_uop.bits.taken, issue_slots[20].out_uop.taken connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[20].out_uop.pc_lob connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[20].out_uop.edge_inst connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[20].out_uop.ftq_idx connect issue_slots[19].in_uop.bits.br_tag, issue_slots[20].out_uop.br_tag connect issue_slots[19].in_uop.bits.br_mask, issue_slots[20].out_uop.br_mask connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[20].out_uop.is_sfb connect issue_slots[19].in_uop.bits.is_jal, issue_slots[20].out_uop.is_jal connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[20].out_uop.is_jalr connect issue_slots[19].in_uop.bits.is_br, issue_slots[20].out_uop.is_br connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[20].out_uop.iw_p2_poisoned connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[20].out_uop.iw_p1_poisoned connect issue_slots[19].in_uop.bits.iw_state, issue_slots[20].out_uop.iw_state connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[20].out_uop.ctrl.is_std connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[20].out_uop.ctrl.is_sta connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[20].out_uop.ctrl.is_load connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[20].out_uop.ctrl.csr_cmd connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[20].out_uop.ctrl.fcn_dw connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[20].out_uop.ctrl.op_fcn connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[20].out_uop.ctrl.imm_sel connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[20].out_uop.ctrl.op2_sel connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[20].out_uop.ctrl.op1_sel connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[20].out_uop.ctrl.br_type connect issue_slots[19].in_uop.bits.fu_code, issue_slots[20].out_uop.fu_code connect issue_slots[19].in_uop.bits.iq_type, issue_slots[20].out_uop.iq_type connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[20].out_uop.debug_pc connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[20].out_uop.is_rvc connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[20].out_uop.debug_inst connect issue_slots[19].in_uop.bits.inst, issue_slots[20].out_uop.inst connect issue_slots[19].in_uop.bits.uopc, issue_slots[20].out_uop.uopc node _T_318 = eq(_WIRE_24, UInt<2>(0h2)) when _T_318 : connect issue_slots[19].in_uop.valid, issue_slots[21].will_be_valid connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if connect issue_slots[19].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single connect issue_slots[19].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val connect issue_slots[19].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3 connect issue_slots[19].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2 connect issue_slots[19].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1 connect issue_slots[19].in_uop.bits.ldst, issue_slots[21].out_uop.ldst connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1 connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit connect issue_slots[19].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq connect issue_slots[19].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei connect issue_slots[19].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed connect issue_slots[19].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd connect issue_slots[19].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause connect issue_slots[19].in_uop.bits.exception, issue_slots[21].out_uop.exception connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy connect issue_slots[19].in_uop.bits.ppred, issue_slots[21].out_uop.ppred connect issue_slots[19].in_uop.bits.prs3, issue_slots[21].out_uop.prs3 connect issue_slots[19].in_uop.bits.prs2, issue_slots[21].out_uop.prs2 connect issue_slots[19].in_uop.bits.prs1, issue_slots[21].out_uop.prs1 connect issue_slots[19].in_uop.bits.pdst, issue_slots[21].out_uop.pdst connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed connect issue_slots[19].in_uop.bits.taken, issue_slots[21].out_uop.taken connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx connect issue_slots[19].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag connect issue_slots[19].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb connect issue_slots[19].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr connect issue_slots[19].in_uop.bits.is_br, issue_slots[21].out_uop.is_br connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned connect issue_slots[19].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type connect issue_slots[19].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code connect issue_slots[19].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst connect issue_slots[19].in_uop.bits.inst, issue_slots[21].out_uop.inst connect issue_slots[19].in_uop.bits.uopc, issue_slots[21].out_uop.uopc node _T_319 = eq(_WIRE_25, UInt<3>(0h4)) when _T_319 : connect issue_slots[19].in_uop.valid, issue_slots[22].will_be_valid connect issue_slots[19].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc connect issue_slots[19].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc connect issue_slots[19].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if connect issue_slots[19].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if connect issue_slots[19].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if connect issue_slots[19].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if connect issue_slots[19].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if connect issue_slots[19].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single connect issue_slots[19].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val connect issue_slots[19].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en connect issue_slots[19].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype connect issue_slots[19].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype connect issue_slots[19].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype connect issue_slots[19].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val connect issue_slots[19].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3 connect issue_slots[19].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2 connect issue_slots[19].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1 connect issue_slots[19].in_uop.bits.ldst, issue_slots[22].out_uop.ldst connect issue_slots[19].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1 connect issue_slots[19].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit connect issue_slots[19].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique connect issue_slots[19].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc connect issue_slots[19].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq connect issue_slots[19].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq connect issue_slots[19].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo connect issue_slots[19].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei connect issue_slots[19].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence connect issue_slots[19].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed connect issue_slots[19].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size connect issue_slots[19].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd connect issue_slots[19].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable connect issue_slots[19].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause connect issue_slots[19].in_uop.bits.exception, issue_slots[22].out_uop.exception connect issue_slots[19].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst connect issue_slots[19].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy connect issue_slots[19].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy connect issue_slots[19].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy connect issue_slots[19].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy connect issue_slots[19].in_uop.bits.ppred, issue_slots[22].out_uop.ppred connect issue_slots[19].in_uop.bits.prs3, issue_slots[22].out_uop.prs3 connect issue_slots[19].in_uop.bits.prs2, issue_slots[22].out_uop.prs2 connect issue_slots[19].in_uop.bits.prs1, issue_slots[22].out_uop.prs1 connect issue_slots[19].in_uop.bits.pdst, issue_slots[22].out_uop.pdst connect issue_slots[19].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx connect issue_slots[19].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx connect issue_slots[19].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx connect issue_slots[19].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx connect issue_slots[19].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr connect issue_slots[19].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed connect issue_slots[19].in_uop.bits.taken, issue_slots[22].out_uop.taken connect issue_slots[19].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob connect issue_slots[19].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst connect issue_slots[19].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx connect issue_slots[19].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag connect issue_slots[19].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask connect issue_slots[19].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb connect issue_slots[19].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal connect issue_slots[19].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr connect issue_slots[19].in_uop.bits.is_br, issue_slots[22].out_uop.is_br connect issue_slots[19].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned connect issue_slots[19].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned connect issue_slots[19].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state connect issue_slots[19].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std connect issue_slots[19].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta connect issue_slots[19].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load connect issue_slots[19].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd connect issue_slots[19].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw connect issue_slots[19].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn connect issue_slots[19].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel connect issue_slots[19].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel connect issue_slots[19].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel connect issue_slots[19].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type connect issue_slots[19].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code connect issue_slots[19].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type connect issue_slots[19].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc connect issue_slots[19].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc connect issue_slots[19].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst connect issue_slots[19].in_uop.bits.inst, issue_slots[22].out_uop.inst connect issue_slots[19].in_uop.bits.uopc, issue_slots[22].out_uop.uopc node _issue_slots_19_clear_T = neq(_WIRE_22, UInt<1>(0h0)) connect issue_slots[19].clear, _issue_slots_19_clear_T connect issue_slots[20].in_uop.valid, UInt<1>(0h0) connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if connect issue_slots[20].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single connect issue_slots[20].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val connect issue_slots[20].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3 connect issue_slots[20].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2 connect issue_slots[20].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1 connect issue_slots[20].in_uop.bits.ldst, issue_slots[21].out_uop.ldst connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1 connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit connect issue_slots[20].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq connect issue_slots[20].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei connect issue_slots[20].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed connect issue_slots[20].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd connect issue_slots[20].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause connect issue_slots[20].in_uop.bits.exception, issue_slots[21].out_uop.exception connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy connect issue_slots[20].in_uop.bits.ppred, issue_slots[21].out_uop.ppred connect issue_slots[20].in_uop.bits.prs3, issue_slots[21].out_uop.prs3 connect issue_slots[20].in_uop.bits.prs2, issue_slots[21].out_uop.prs2 connect issue_slots[20].in_uop.bits.prs1, issue_slots[21].out_uop.prs1 connect issue_slots[20].in_uop.bits.pdst, issue_slots[21].out_uop.pdst connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed connect issue_slots[20].in_uop.bits.taken, issue_slots[21].out_uop.taken connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx connect issue_slots[20].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag connect issue_slots[20].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb connect issue_slots[20].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr connect issue_slots[20].in_uop.bits.is_br, issue_slots[21].out_uop.is_br connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned connect issue_slots[20].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type connect issue_slots[20].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code connect issue_slots[20].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst connect issue_slots[20].in_uop.bits.inst, issue_slots[21].out_uop.inst connect issue_slots[20].in_uop.bits.uopc, issue_slots[21].out_uop.uopc node _T_320 = eq(_WIRE_24, UInt<1>(0h1)) when _T_320 : connect issue_slots[20].in_uop.valid, issue_slots[21].will_be_valid connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[21].out_uop.debug_tsrc connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[21].out_uop.debug_fsrc connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[21].out_uop.bp_xcpt_if connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[21].out_uop.bp_debug_if connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[21].out_uop.xcpt_ma_if connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[21].out_uop.xcpt_ae_if connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[21].out_uop.xcpt_pf_if connect issue_slots[20].in_uop.bits.fp_single, issue_slots[21].out_uop.fp_single connect issue_slots[20].in_uop.bits.fp_val, issue_slots[21].out_uop.fp_val connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[21].out_uop.frs3_en connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[21].out_uop.lrs2_rtype connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[21].out_uop.lrs1_rtype connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[21].out_uop.dst_rtype connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[21].out_uop.ldst_val connect issue_slots[20].in_uop.bits.lrs3, issue_slots[21].out_uop.lrs3 connect issue_slots[20].in_uop.bits.lrs2, issue_slots[21].out_uop.lrs2 connect issue_slots[20].in_uop.bits.lrs1, issue_slots[21].out_uop.lrs1 connect issue_slots[20].in_uop.bits.ldst, issue_slots[21].out_uop.ldst connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[21].out_uop.ldst_is_rs1 connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[21].out_uop.flush_on_commit connect issue_slots[20].in_uop.bits.is_unique, issue_slots[21].out_uop.is_unique connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[21].out_uop.is_sys_pc2epc connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[21].out_uop.uses_stq connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[21].out_uop.uses_ldq connect issue_slots[20].in_uop.bits.is_amo, issue_slots[21].out_uop.is_amo connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[21].out_uop.is_fencei connect issue_slots[20].in_uop.bits.is_fence, issue_slots[21].out_uop.is_fence connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[21].out_uop.mem_signed connect issue_slots[20].in_uop.bits.mem_size, issue_slots[21].out_uop.mem_size connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[21].out_uop.mem_cmd connect issue_slots[20].in_uop.bits.bypassable, issue_slots[21].out_uop.bypassable connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[21].out_uop.exc_cause connect issue_slots[20].in_uop.bits.exception, issue_slots[21].out_uop.exception connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[21].out_uop.stale_pdst connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[21].out_uop.ppred_busy connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[21].out_uop.prs3_busy connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[21].out_uop.prs2_busy connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[21].out_uop.prs1_busy connect issue_slots[20].in_uop.bits.ppred, issue_slots[21].out_uop.ppred connect issue_slots[20].in_uop.bits.prs3, issue_slots[21].out_uop.prs3 connect issue_slots[20].in_uop.bits.prs2, issue_slots[21].out_uop.prs2 connect issue_slots[20].in_uop.bits.prs1, issue_slots[21].out_uop.prs1 connect issue_slots[20].in_uop.bits.pdst, issue_slots[21].out_uop.pdst connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[21].out_uop.rxq_idx connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[21].out_uop.stq_idx connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[21].out_uop.ldq_idx connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[21].out_uop.rob_idx connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[21].out_uop.csr_addr connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[21].out_uop.imm_packed connect issue_slots[20].in_uop.bits.taken, issue_slots[21].out_uop.taken connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[21].out_uop.pc_lob connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[21].out_uop.edge_inst connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[21].out_uop.ftq_idx connect issue_slots[20].in_uop.bits.br_tag, issue_slots[21].out_uop.br_tag connect issue_slots[20].in_uop.bits.br_mask, issue_slots[21].out_uop.br_mask connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[21].out_uop.is_sfb connect issue_slots[20].in_uop.bits.is_jal, issue_slots[21].out_uop.is_jal connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[21].out_uop.is_jalr connect issue_slots[20].in_uop.bits.is_br, issue_slots[21].out_uop.is_br connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[21].out_uop.iw_p2_poisoned connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[21].out_uop.iw_p1_poisoned connect issue_slots[20].in_uop.bits.iw_state, issue_slots[21].out_uop.iw_state connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[21].out_uop.ctrl.is_std connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[21].out_uop.ctrl.is_sta connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[21].out_uop.ctrl.is_load connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[21].out_uop.ctrl.csr_cmd connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[21].out_uop.ctrl.fcn_dw connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[21].out_uop.ctrl.op_fcn connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[21].out_uop.ctrl.imm_sel connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[21].out_uop.ctrl.op2_sel connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[21].out_uop.ctrl.op1_sel connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[21].out_uop.ctrl.br_type connect issue_slots[20].in_uop.bits.fu_code, issue_slots[21].out_uop.fu_code connect issue_slots[20].in_uop.bits.iq_type, issue_slots[21].out_uop.iq_type connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[21].out_uop.debug_pc connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[21].out_uop.is_rvc connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[21].out_uop.debug_inst connect issue_slots[20].in_uop.bits.inst, issue_slots[21].out_uop.inst connect issue_slots[20].in_uop.bits.uopc, issue_slots[21].out_uop.uopc node _T_321 = eq(_WIRE_25, UInt<2>(0h2)) when _T_321 : connect issue_slots[20].in_uop.valid, issue_slots[22].will_be_valid connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if connect issue_slots[20].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single connect issue_slots[20].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val connect issue_slots[20].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3 connect issue_slots[20].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2 connect issue_slots[20].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1 connect issue_slots[20].in_uop.bits.ldst, issue_slots[22].out_uop.ldst connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1 connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit connect issue_slots[20].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq connect issue_slots[20].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei connect issue_slots[20].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed connect issue_slots[20].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd connect issue_slots[20].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause connect issue_slots[20].in_uop.bits.exception, issue_slots[22].out_uop.exception connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy connect issue_slots[20].in_uop.bits.ppred, issue_slots[22].out_uop.ppred connect issue_slots[20].in_uop.bits.prs3, issue_slots[22].out_uop.prs3 connect issue_slots[20].in_uop.bits.prs2, issue_slots[22].out_uop.prs2 connect issue_slots[20].in_uop.bits.prs1, issue_slots[22].out_uop.prs1 connect issue_slots[20].in_uop.bits.pdst, issue_slots[22].out_uop.pdst connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed connect issue_slots[20].in_uop.bits.taken, issue_slots[22].out_uop.taken connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx connect issue_slots[20].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag connect issue_slots[20].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb connect issue_slots[20].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr connect issue_slots[20].in_uop.bits.is_br, issue_slots[22].out_uop.is_br connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned connect issue_slots[20].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type connect issue_slots[20].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code connect issue_slots[20].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst connect issue_slots[20].in_uop.bits.inst, issue_slots[22].out_uop.inst connect issue_slots[20].in_uop.bits.uopc, issue_slots[22].out_uop.uopc node _T_322 = eq(_WIRE_26, UInt<3>(0h4)) when _T_322 : connect issue_slots[20].in_uop.valid, issue_slots[23].will_be_valid connect issue_slots[20].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc connect issue_slots[20].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc connect issue_slots[20].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if connect issue_slots[20].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if connect issue_slots[20].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if connect issue_slots[20].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if connect issue_slots[20].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if connect issue_slots[20].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single connect issue_slots[20].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val connect issue_slots[20].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en connect issue_slots[20].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype connect issue_slots[20].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype connect issue_slots[20].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype connect issue_slots[20].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val connect issue_slots[20].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3 connect issue_slots[20].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2 connect issue_slots[20].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1 connect issue_slots[20].in_uop.bits.ldst, issue_slots[23].out_uop.ldst connect issue_slots[20].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1 connect issue_slots[20].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit connect issue_slots[20].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique connect issue_slots[20].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc connect issue_slots[20].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq connect issue_slots[20].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq connect issue_slots[20].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo connect issue_slots[20].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei connect issue_slots[20].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence connect issue_slots[20].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed connect issue_slots[20].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size connect issue_slots[20].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd connect issue_slots[20].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable connect issue_slots[20].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause connect issue_slots[20].in_uop.bits.exception, issue_slots[23].out_uop.exception connect issue_slots[20].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst connect issue_slots[20].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy connect issue_slots[20].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy connect issue_slots[20].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy connect issue_slots[20].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy connect issue_slots[20].in_uop.bits.ppred, issue_slots[23].out_uop.ppred connect issue_slots[20].in_uop.bits.prs3, issue_slots[23].out_uop.prs3 connect issue_slots[20].in_uop.bits.prs2, issue_slots[23].out_uop.prs2 connect issue_slots[20].in_uop.bits.prs1, issue_slots[23].out_uop.prs1 connect issue_slots[20].in_uop.bits.pdst, issue_slots[23].out_uop.pdst connect issue_slots[20].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx connect issue_slots[20].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx connect issue_slots[20].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx connect issue_slots[20].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx connect issue_slots[20].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr connect issue_slots[20].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed connect issue_slots[20].in_uop.bits.taken, issue_slots[23].out_uop.taken connect issue_slots[20].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob connect issue_slots[20].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst connect issue_slots[20].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx connect issue_slots[20].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag connect issue_slots[20].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask connect issue_slots[20].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb connect issue_slots[20].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal connect issue_slots[20].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr connect issue_slots[20].in_uop.bits.is_br, issue_slots[23].out_uop.is_br connect issue_slots[20].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned connect issue_slots[20].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned connect issue_slots[20].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state connect issue_slots[20].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std connect issue_slots[20].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta connect issue_slots[20].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load connect issue_slots[20].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd connect issue_slots[20].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw connect issue_slots[20].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn connect issue_slots[20].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel connect issue_slots[20].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel connect issue_slots[20].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel connect issue_slots[20].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type connect issue_slots[20].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code connect issue_slots[20].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type connect issue_slots[20].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc connect issue_slots[20].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc connect issue_slots[20].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst connect issue_slots[20].in_uop.bits.inst, issue_slots[23].out_uop.inst connect issue_slots[20].in_uop.bits.uopc, issue_slots[23].out_uop.uopc node _issue_slots_20_clear_T = neq(_WIRE_23, UInt<1>(0h0)) connect issue_slots[20].clear, _issue_slots_20_clear_T connect issue_slots[21].in_uop.valid, UInt<1>(0h0) connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if connect issue_slots[21].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single connect issue_slots[21].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val connect issue_slots[21].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3 connect issue_slots[21].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2 connect issue_slots[21].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1 connect issue_slots[21].in_uop.bits.ldst, issue_slots[22].out_uop.ldst connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1 connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit connect issue_slots[21].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq connect issue_slots[21].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei connect issue_slots[21].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed connect issue_slots[21].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd connect issue_slots[21].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause connect issue_slots[21].in_uop.bits.exception, issue_slots[22].out_uop.exception connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy connect issue_slots[21].in_uop.bits.ppred, issue_slots[22].out_uop.ppred connect issue_slots[21].in_uop.bits.prs3, issue_slots[22].out_uop.prs3 connect issue_slots[21].in_uop.bits.prs2, issue_slots[22].out_uop.prs2 connect issue_slots[21].in_uop.bits.prs1, issue_slots[22].out_uop.prs1 connect issue_slots[21].in_uop.bits.pdst, issue_slots[22].out_uop.pdst connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed connect issue_slots[21].in_uop.bits.taken, issue_slots[22].out_uop.taken connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx connect issue_slots[21].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag connect issue_slots[21].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb connect issue_slots[21].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr connect issue_slots[21].in_uop.bits.is_br, issue_slots[22].out_uop.is_br connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned connect issue_slots[21].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type connect issue_slots[21].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code connect issue_slots[21].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst connect issue_slots[21].in_uop.bits.inst, issue_slots[22].out_uop.inst connect issue_slots[21].in_uop.bits.uopc, issue_slots[22].out_uop.uopc node _T_323 = eq(_WIRE_25, UInt<1>(0h1)) when _T_323 : connect issue_slots[21].in_uop.valid, issue_slots[22].will_be_valid connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[22].out_uop.debug_tsrc connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[22].out_uop.debug_fsrc connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[22].out_uop.bp_xcpt_if connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[22].out_uop.bp_debug_if connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[22].out_uop.xcpt_ma_if connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[22].out_uop.xcpt_ae_if connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[22].out_uop.xcpt_pf_if connect issue_slots[21].in_uop.bits.fp_single, issue_slots[22].out_uop.fp_single connect issue_slots[21].in_uop.bits.fp_val, issue_slots[22].out_uop.fp_val connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[22].out_uop.frs3_en connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[22].out_uop.lrs2_rtype connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[22].out_uop.lrs1_rtype connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[22].out_uop.dst_rtype connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[22].out_uop.ldst_val connect issue_slots[21].in_uop.bits.lrs3, issue_slots[22].out_uop.lrs3 connect issue_slots[21].in_uop.bits.lrs2, issue_slots[22].out_uop.lrs2 connect issue_slots[21].in_uop.bits.lrs1, issue_slots[22].out_uop.lrs1 connect issue_slots[21].in_uop.bits.ldst, issue_slots[22].out_uop.ldst connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[22].out_uop.ldst_is_rs1 connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[22].out_uop.flush_on_commit connect issue_slots[21].in_uop.bits.is_unique, issue_slots[22].out_uop.is_unique connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[22].out_uop.is_sys_pc2epc connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[22].out_uop.uses_stq connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[22].out_uop.uses_ldq connect issue_slots[21].in_uop.bits.is_amo, issue_slots[22].out_uop.is_amo connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[22].out_uop.is_fencei connect issue_slots[21].in_uop.bits.is_fence, issue_slots[22].out_uop.is_fence connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[22].out_uop.mem_signed connect issue_slots[21].in_uop.bits.mem_size, issue_slots[22].out_uop.mem_size connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[22].out_uop.mem_cmd connect issue_slots[21].in_uop.bits.bypassable, issue_slots[22].out_uop.bypassable connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[22].out_uop.exc_cause connect issue_slots[21].in_uop.bits.exception, issue_slots[22].out_uop.exception connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[22].out_uop.stale_pdst connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[22].out_uop.ppred_busy connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[22].out_uop.prs3_busy connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[22].out_uop.prs2_busy connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[22].out_uop.prs1_busy connect issue_slots[21].in_uop.bits.ppred, issue_slots[22].out_uop.ppred connect issue_slots[21].in_uop.bits.prs3, issue_slots[22].out_uop.prs3 connect issue_slots[21].in_uop.bits.prs2, issue_slots[22].out_uop.prs2 connect issue_slots[21].in_uop.bits.prs1, issue_slots[22].out_uop.prs1 connect issue_slots[21].in_uop.bits.pdst, issue_slots[22].out_uop.pdst connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[22].out_uop.rxq_idx connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[22].out_uop.stq_idx connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[22].out_uop.ldq_idx connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[22].out_uop.rob_idx connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[22].out_uop.csr_addr connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[22].out_uop.imm_packed connect issue_slots[21].in_uop.bits.taken, issue_slots[22].out_uop.taken connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[22].out_uop.pc_lob connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[22].out_uop.edge_inst connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[22].out_uop.ftq_idx connect issue_slots[21].in_uop.bits.br_tag, issue_slots[22].out_uop.br_tag connect issue_slots[21].in_uop.bits.br_mask, issue_slots[22].out_uop.br_mask connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[22].out_uop.is_sfb connect issue_slots[21].in_uop.bits.is_jal, issue_slots[22].out_uop.is_jal connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[22].out_uop.is_jalr connect issue_slots[21].in_uop.bits.is_br, issue_slots[22].out_uop.is_br connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[22].out_uop.iw_p2_poisoned connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[22].out_uop.iw_p1_poisoned connect issue_slots[21].in_uop.bits.iw_state, issue_slots[22].out_uop.iw_state connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[22].out_uop.ctrl.is_std connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[22].out_uop.ctrl.is_sta connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[22].out_uop.ctrl.is_load connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[22].out_uop.ctrl.csr_cmd connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[22].out_uop.ctrl.fcn_dw connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[22].out_uop.ctrl.op_fcn connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[22].out_uop.ctrl.imm_sel connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[22].out_uop.ctrl.op2_sel connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[22].out_uop.ctrl.op1_sel connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[22].out_uop.ctrl.br_type connect issue_slots[21].in_uop.bits.fu_code, issue_slots[22].out_uop.fu_code connect issue_slots[21].in_uop.bits.iq_type, issue_slots[22].out_uop.iq_type connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[22].out_uop.debug_pc connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[22].out_uop.is_rvc connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[22].out_uop.debug_inst connect issue_slots[21].in_uop.bits.inst, issue_slots[22].out_uop.inst connect issue_slots[21].in_uop.bits.uopc, issue_slots[22].out_uop.uopc node _T_324 = eq(_WIRE_26, UInt<2>(0h2)) when _T_324 : connect issue_slots[21].in_uop.valid, issue_slots[23].will_be_valid connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if connect issue_slots[21].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single connect issue_slots[21].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val connect issue_slots[21].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3 connect issue_slots[21].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2 connect issue_slots[21].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1 connect issue_slots[21].in_uop.bits.ldst, issue_slots[23].out_uop.ldst connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1 connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit connect issue_slots[21].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq connect issue_slots[21].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei connect issue_slots[21].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed connect issue_slots[21].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd connect issue_slots[21].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause connect issue_slots[21].in_uop.bits.exception, issue_slots[23].out_uop.exception connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy connect issue_slots[21].in_uop.bits.ppred, issue_slots[23].out_uop.ppred connect issue_slots[21].in_uop.bits.prs3, issue_slots[23].out_uop.prs3 connect issue_slots[21].in_uop.bits.prs2, issue_slots[23].out_uop.prs2 connect issue_slots[21].in_uop.bits.prs1, issue_slots[23].out_uop.prs1 connect issue_slots[21].in_uop.bits.pdst, issue_slots[23].out_uop.pdst connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed connect issue_slots[21].in_uop.bits.taken, issue_slots[23].out_uop.taken connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx connect issue_slots[21].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag connect issue_slots[21].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb connect issue_slots[21].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr connect issue_slots[21].in_uop.bits.is_br, issue_slots[23].out_uop.is_br connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned connect issue_slots[21].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type connect issue_slots[21].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code connect issue_slots[21].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst connect issue_slots[21].in_uop.bits.inst, issue_slots[23].out_uop.inst connect issue_slots[21].in_uop.bits.uopc, issue_slots[23].out_uop.uopc node _T_325 = eq(_WIRE_27, UInt<3>(0h4)) when _T_325 : connect issue_slots[21].in_uop.valid, issue_slots[24].will_be_valid connect issue_slots[21].in_uop.bits.debug_tsrc, issue_slots[24].out_uop.debug_tsrc connect issue_slots[21].in_uop.bits.debug_fsrc, issue_slots[24].out_uop.debug_fsrc connect issue_slots[21].in_uop.bits.bp_xcpt_if, issue_slots[24].out_uop.bp_xcpt_if connect issue_slots[21].in_uop.bits.bp_debug_if, issue_slots[24].out_uop.bp_debug_if connect issue_slots[21].in_uop.bits.xcpt_ma_if, issue_slots[24].out_uop.xcpt_ma_if connect issue_slots[21].in_uop.bits.xcpt_ae_if, issue_slots[24].out_uop.xcpt_ae_if connect issue_slots[21].in_uop.bits.xcpt_pf_if, issue_slots[24].out_uop.xcpt_pf_if connect issue_slots[21].in_uop.bits.fp_single, issue_slots[24].out_uop.fp_single connect issue_slots[21].in_uop.bits.fp_val, issue_slots[24].out_uop.fp_val connect issue_slots[21].in_uop.bits.frs3_en, issue_slots[24].out_uop.frs3_en connect issue_slots[21].in_uop.bits.lrs2_rtype, issue_slots[24].out_uop.lrs2_rtype connect issue_slots[21].in_uop.bits.lrs1_rtype, issue_slots[24].out_uop.lrs1_rtype connect issue_slots[21].in_uop.bits.dst_rtype, issue_slots[24].out_uop.dst_rtype connect issue_slots[21].in_uop.bits.ldst_val, issue_slots[24].out_uop.ldst_val connect issue_slots[21].in_uop.bits.lrs3, issue_slots[24].out_uop.lrs3 connect issue_slots[21].in_uop.bits.lrs2, issue_slots[24].out_uop.lrs2 connect issue_slots[21].in_uop.bits.lrs1, issue_slots[24].out_uop.lrs1 connect issue_slots[21].in_uop.bits.ldst, issue_slots[24].out_uop.ldst connect issue_slots[21].in_uop.bits.ldst_is_rs1, issue_slots[24].out_uop.ldst_is_rs1 connect issue_slots[21].in_uop.bits.flush_on_commit, issue_slots[24].out_uop.flush_on_commit connect issue_slots[21].in_uop.bits.is_unique, issue_slots[24].out_uop.is_unique connect issue_slots[21].in_uop.bits.is_sys_pc2epc, issue_slots[24].out_uop.is_sys_pc2epc connect issue_slots[21].in_uop.bits.uses_stq, issue_slots[24].out_uop.uses_stq connect issue_slots[21].in_uop.bits.uses_ldq, issue_slots[24].out_uop.uses_ldq connect issue_slots[21].in_uop.bits.is_amo, issue_slots[24].out_uop.is_amo connect issue_slots[21].in_uop.bits.is_fencei, issue_slots[24].out_uop.is_fencei connect issue_slots[21].in_uop.bits.is_fence, issue_slots[24].out_uop.is_fence connect issue_slots[21].in_uop.bits.mem_signed, issue_slots[24].out_uop.mem_signed connect issue_slots[21].in_uop.bits.mem_size, issue_slots[24].out_uop.mem_size connect issue_slots[21].in_uop.bits.mem_cmd, issue_slots[24].out_uop.mem_cmd connect issue_slots[21].in_uop.bits.bypassable, issue_slots[24].out_uop.bypassable connect issue_slots[21].in_uop.bits.exc_cause, issue_slots[24].out_uop.exc_cause connect issue_slots[21].in_uop.bits.exception, issue_slots[24].out_uop.exception connect issue_slots[21].in_uop.bits.stale_pdst, issue_slots[24].out_uop.stale_pdst connect issue_slots[21].in_uop.bits.ppred_busy, issue_slots[24].out_uop.ppred_busy connect issue_slots[21].in_uop.bits.prs3_busy, issue_slots[24].out_uop.prs3_busy connect issue_slots[21].in_uop.bits.prs2_busy, issue_slots[24].out_uop.prs2_busy connect issue_slots[21].in_uop.bits.prs1_busy, issue_slots[24].out_uop.prs1_busy connect issue_slots[21].in_uop.bits.ppred, issue_slots[24].out_uop.ppred connect issue_slots[21].in_uop.bits.prs3, issue_slots[24].out_uop.prs3 connect issue_slots[21].in_uop.bits.prs2, issue_slots[24].out_uop.prs2 connect issue_slots[21].in_uop.bits.prs1, issue_slots[24].out_uop.prs1 connect issue_slots[21].in_uop.bits.pdst, issue_slots[24].out_uop.pdst connect issue_slots[21].in_uop.bits.rxq_idx, issue_slots[24].out_uop.rxq_idx connect issue_slots[21].in_uop.bits.stq_idx, issue_slots[24].out_uop.stq_idx connect issue_slots[21].in_uop.bits.ldq_idx, issue_slots[24].out_uop.ldq_idx connect issue_slots[21].in_uop.bits.rob_idx, issue_slots[24].out_uop.rob_idx connect issue_slots[21].in_uop.bits.csr_addr, issue_slots[24].out_uop.csr_addr connect issue_slots[21].in_uop.bits.imm_packed, issue_slots[24].out_uop.imm_packed connect issue_slots[21].in_uop.bits.taken, issue_slots[24].out_uop.taken connect issue_slots[21].in_uop.bits.pc_lob, issue_slots[24].out_uop.pc_lob connect issue_slots[21].in_uop.bits.edge_inst, issue_slots[24].out_uop.edge_inst connect issue_slots[21].in_uop.bits.ftq_idx, issue_slots[24].out_uop.ftq_idx connect issue_slots[21].in_uop.bits.br_tag, issue_slots[24].out_uop.br_tag connect issue_slots[21].in_uop.bits.br_mask, issue_slots[24].out_uop.br_mask connect issue_slots[21].in_uop.bits.is_sfb, issue_slots[24].out_uop.is_sfb connect issue_slots[21].in_uop.bits.is_jal, issue_slots[24].out_uop.is_jal connect issue_slots[21].in_uop.bits.is_jalr, issue_slots[24].out_uop.is_jalr connect issue_slots[21].in_uop.bits.is_br, issue_slots[24].out_uop.is_br connect issue_slots[21].in_uop.bits.iw_p2_poisoned, issue_slots[24].out_uop.iw_p2_poisoned connect issue_slots[21].in_uop.bits.iw_p1_poisoned, issue_slots[24].out_uop.iw_p1_poisoned connect issue_slots[21].in_uop.bits.iw_state, issue_slots[24].out_uop.iw_state connect issue_slots[21].in_uop.bits.ctrl.is_std, issue_slots[24].out_uop.ctrl.is_std connect issue_slots[21].in_uop.bits.ctrl.is_sta, issue_slots[24].out_uop.ctrl.is_sta connect issue_slots[21].in_uop.bits.ctrl.is_load, issue_slots[24].out_uop.ctrl.is_load connect issue_slots[21].in_uop.bits.ctrl.csr_cmd, issue_slots[24].out_uop.ctrl.csr_cmd connect issue_slots[21].in_uop.bits.ctrl.fcn_dw, issue_slots[24].out_uop.ctrl.fcn_dw connect issue_slots[21].in_uop.bits.ctrl.op_fcn, issue_slots[24].out_uop.ctrl.op_fcn connect issue_slots[21].in_uop.bits.ctrl.imm_sel, issue_slots[24].out_uop.ctrl.imm_sel connect issue_slots[21].in_uop.bits.ctrl.op2_sel, issue_slots[24].out_uop.ctrl.op2_sel connect issue_slots[21].in_uop.bits.ctrl.op1_sel, issue_slots[24].out_uop.ctrl.op1_sel connect issue_slots[21].in_uop.bits.ctrl.br_type, issue_slots[24].out_uop.ctrl.br_type connect issue_slots[21].in_uop.bits.fu_code, issue_slots[24].out_uop.fu_code connect issue_slots[21].in_uop.bits.iq_type, issue_slots[24].out_uop.iq_type connect issue_slots[21].in_uop.bits.debug_pc, issue_slots[24].out_uop.debug_pc connect issue_slots[21].in_uop.bits.is_rvc, issue_slots[24].out_uop.is_rvc connect issue_slots[21].in_uop.bits.debug_inst, issue_slots[24].out_uop.debug_inst connect issue_slots[21].in_uop.bits.inst, issue_slots[24].out_uop.inst connect issue_slots[21].in_uop.bits.uopc, issue_slots[24].out_uop.uopc node _issue_slots_21_clear_T = neq(_WIRE_24, UInt<1>(0h0)) connect issue_slots[21].clear, _issue_slots_21_clear_T connect issue_slots[22].in_uop.valid, UInt<1>(0h0) connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if connect issue_slots[22].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single connect issue_slots[22].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val connect issue_slots[22].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3 connect issue_slots[22].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2 connect issue_slots[22].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1 connect issue_slots[22].in_uop.bits.ldst, issue_slots[23].out_uop.ldst connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1 connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit connect issue_slots[22].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq connect issue_slots[22].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei connect issue_slots[22].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed connect issue_slots[22].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd connect issue_slots[22].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause connect issue_slots[22].in_uop.bits.exception, issue_slots[23].out_uop.exception connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy connect issue_slots[22].in_uop.bits.ppred, issue_slots[23].out_uop.ppred connect issue_slots[22].in_uop.bits.prs3, issue_slots[23].out_uop.prs3 connect issue_slots[22].in_uop.bits.prs2, issue_slots[23].out_uop.prs2 connect issue_slots[22].in_uop.bits.prs1, issue_slots[23].out_uop.prs1 connect issue_slots[22].in_uop.bits.pdst, issue_slots[23].out_uop.pdst connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed connect issue_slots[22].in_uop.bits.taken, issue_slots[23].out_uop.taken connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx connect issue_slots[22].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag connect issue_slots[22].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb connect issue_slots[22].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr connect issue_slots[22].in_uop.bits.is_br, issue_slots[23].out_uop.is_br connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned connect issue_slots[22].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type connect issue_slots[22].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code connect issue_slots[22].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst connect issue_slots[22].in_uop.bits.inst, issue_slots[23].out_uop.inst connect issue_slots[22].in_uop.bits.uopc, issue_slots[23].out_uop.uopc node _T_326 = eq(_WIRE_26, UInt<1>(0h1)) when _T_326 : connect issue_slots[22].in_uop.valid, issue_slots[23].will_be_valid connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[23].out_uop.debug_tsrc connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[23].out_uop.debug_fsrc connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[23].out_uop.bp_xcpt_if connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[23].out_uop.bp_debug_if connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[23].out_uop.xcpt_ma_if connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[23].out_uop.xcpt_ae_if connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[23].out_uop.xcpt_pf_if connect issue_slots[22].in_uop.bits.fp_single, issue_slots[23].out_uop.fp_single connect issue_slots[22].in_uop.bits.fp_val, issue_slots[23].out_uop.fp_val connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[23].out_uop.frs3_en connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[23].out_uop.lrs2_rtype connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[23].out_uop.lrs1_rtype connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[23].out_uop.dst_rtype connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[23].out_uop.ldst_val connect issue_slots[22].in_uop.bits.lrs3, issue_slots[23].out_uop.lrs3 connect issue_slots[22].in_uop.bits.lrs2, issue_slots[23].out_uop.lrs2 connect issue_slots[22].in_uop.bits.lrs1, issue_slots[23].out_uop.lrs1 connect issue_slots[22].in_uop.bits.ldst, issue_slots[23].out_uop.ldst connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[23].out_uop.ldst_is_rs1 connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[23].out_uop.flush_on_commit connect issue_slots[22].in_uop.bits.is_unique, issue_slots[23].out_uop.is_unique connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[23].out_uop.is_sys_pc2epc connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[23].out_uop.uses_stq connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[23].out_uop.uses_ldq connect issue_slots[22].in_uop.bits.is_amo, issue_slots[23].out_uop.is_amo connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[23].out_uop.is_fencei connect issue_slots[22].in_uop.bits.is_fence, issue_slots[23].out_uop.is_fence connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[23].out_uop.mem_signed connect issue_slots[22].in_uop.bits.mem_size, issue_slots[23].out_uop.mem_size connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[23].out_uop.mem_cmd connect issue_slots[22].in_uop.bits.bypassable, issue_slots[23].out_uop.bypassable connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[23].out_uop.exc_cause connect issue_slots[22].in_uop.bits.exception, issue_slots[23].out_uop.exception connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[23].out_uop.stale_pdst connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[23].out_uop.ppred_busy connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[23].out_uop.prs3_busy connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[23].out_uop.prs2_busy connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[23].out_uop.prs1_busy connect issue_slots[22].in_uop.bits.ppred, issue_slots[23].out_uop.ppred connect issue_slots[22].in_uop.bits.prs3, issue_slots[23].out_uop.prs3 connect issue_slots[22].in_uop.bits.prs2, issue_slots[23].out_uop.prs2 connect issue_slots[22].in_uop.bits.prs1, issue_slots[23].out_uop.prs1 connect issue_slots[22].in_uop.bits.pdst, issue_slots[23].out_uop.pdst connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[23].out_uop.rxq_idx connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[23].out_uop.stq_idx connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[23].out_uop.ldq_idx connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[23].out_uop.rob_idx connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[23].out_uop.csr_addr connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[23].out_uop.imm_packed connect issue_slots[22].in_uop.bits.taken, issue_slots[23].out_uop.taken connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[23].out_uop.pc_lob connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[23].out_uop.edge_inst connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[23].out_uop.ftq_idx connect issue_slots[22].in_uop.bits.br_tag, issue_slots[23].out_uop.br_tag connect issue_slots[22].in_uop.bits.br_mask, issue_slots[23].out_uop.br_mask connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[23].out_uop.is_sfb connect issue_slots[22].in_uop.bits.is_jal, issue_slots[23].out_uop.is_jal connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[23].out_uop.is_jalr connect issue_slots[22].in_uop.bits.is_br, issue_slots[23].out_uop.is_br connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[23].out_uop.iw_p2_poisoned connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[23].out_uop.iw_p1_poisoned connect issue_slots[22].in_uop.bits.iw_state, issue_slots[23].out_uop.iw_state connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[23].out_uop.ctrl.is_std connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[23].out_uop.ctrl.is_sta connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[23].out_uop.ctrl.is_load connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[23].out_uop.ctrl.csr_cmd connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[23].out_uop.ctrl.fcn_dw connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[23].out_uop.ctrl.op_fcn connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[23].out_uop.ctrl.imm_sel connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[23].out_uop.ctrl.op2_sel connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[23].out_uop.ctrl.op1_sel connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[23].out_uop.ctrl.br_type connect issue_slots[22].in_uop.bits.fu_code, issue_slots[23].out_uop.fu_code connect issue_slots[22].in_uop.bits.iq_type, issue_slots[23].out_uop.iq_type connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[23].out_uop.debug_pc connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[23].out_uop.is_rvc connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[23].out_uop.debug_inst connect issue_slots[22].in_uop.bits.inst, issue_slots[23].out_uop.inst connect issue_slots[22].in_uop.bits.uopc, issue_slots[23].out_uop.uopc node _T_327 = eq(_WIRE_27, UInt<2>(0h2)) when _T_327 : connect issue_slots[22].in_uop.valid, issue_slots[24].will_be_valid connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[24].out_uop.debug_tsrc connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[24].out_uop.debug_fsrc connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[24].out_uop.bp_xcpt_if connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[24].out_uop.bp_debug_if connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[24].out_uop.xcpt_ma_if connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[24].out_uop.xcpt_ae_if connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[24].out_uop.xcpt_pf_if connect issue_slots[22].in_uop.bits.fp_single, issue_slots[24].out_uop.fp_single connect issue_slots[22].in_uop.bits.fp_val, issue_slots[24].out_uop.fp_val connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[24].out_uop.frs3_en connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[24].out_uop.lrs2_rtype connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[24].out_uop.lrs1_rtype connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[24].out_uop.dst_rtype connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[24].out_uop.ldst_val connect issue_slots[22].in_uop.bits.lrs3, issue_slots[24].out_uop.lrs3 connect issue_slots[22].in_uop.bits.lrs2, issue_slots[24].out_uop.lrs2 connect issue_slots[22].in_uop.bits.lrs1, issue_slots[24].out_uop.lrs1 connect issue_slots[22].in_uop.bits.ldst, issue_slots[24].out_uop.ldst connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[24].out_uop.ldst_is_rs1 connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[24].out_uop.flush_on_commit connect issue_slots[22].in_uop.bits.is_unique, issue_slots[24].out_uop.is_unique connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[24].out_uop.is_sys_pc2epc connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[24].out_uop.uses_stq connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[24].out_uop.uses_ldq connect issue_slots[22].in_uop.bits.is_amo, issue_slots[24].out_uop.is_amo connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[24].out_uop.is_fencei connect issue_slots[22].in_uop.bits.is_fence, issue_slots[24].out_uop.is_fence connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[24].out_uop.mem_signed connect issue_slots[22].in_uop.bits.mem_size, issue_slots[24].out_uop.mem_size connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[24].out_uop.mem_cmd connect issue_slots[22].in_uop.bits.bypassable, issue_slots[24].out_uop.bypassable connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[24].out_uop.exc_cause connect issue_slots[22].in_uop.bits.exception, issue_slots[24].out_uop.exception connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[24].out_uop.stale_pdst connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[24].out_uop.ppred_busy connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[24].out_uop.prs3_busy connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[24].out_uop.prs2_busy connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[24].out_uop.prs1_busy connect issue_slots[22].in_uop.bits.ppred, issue_slots[24].out_uop.ppred connect issue_slots[22].in_uop.bits.prs3, issue_slots[24].out_uop.prs3 connect issue_slots[22].in_uop.bits.prs2, issue_slots[24].out_uop.prs2 connect issue_slots[22].in_uop.bits.prs1, issue_slots[24].out_uop.prs1 connect issue_slots[22].in_uop.bits.pdst, issue_slots[24].out_uop.pdst connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[24].out_uop.rxq_idx connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[24].out_uop.stq_idx connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[24].out_uop.ldq_idx connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[24].out_uop.rob_idx connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[24].out_uop.csr_addr connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[24].out_uop.imm_packed connect issue_slots[22].in_uop.bits.taken, issue_slots[24].out_uop.taken connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[24].out_uop.pc_lob connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[24].out_uop.edge_inst connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[24].out_uop.ftq_idx connect issue_slots[22].in_uop.bits.br_tag, issue_slots[24].out_uop.br_tag connect issue_slots[22].in_uop.bits.br_mask, issue_slots[24].out_uop.br_mask connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[24].out_uop.is_sfb connect issue_slots[22].in_uop.bits.is_jal, issue_slots[24].out_uop.is_jal connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[24].out_uop.is_jalr connect issue_slots[22].in_uop.bits.is_br, issue_slots[24].out_uop.is_br connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[24].out_uop.iw_p2_poisoned connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[24].out_uop.iw_p1_poisoned connect issue_slots[22].in_uop.bits.iw_state, issue_slots[24].out_uop.iw_state connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[24].out_uop.ctrl.is_std connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[24].out_uop.ctrl.is_sta connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[24].out_uop.ctrl.is_load connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[24].out_uop.ctrl.csr_cmd connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[24].out_uop.ctrl.fcn_dw connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[24].out_uop.ctrl.op_fcn connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[24].out_uop.ctrl.imm_sel connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[24].out_uop.ctrl.op2_sel connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[24].out_uop.ctrl.op1_sel connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[24].out_uop.ctrl.br_type connect issue_slots[22].in_uop.bits.fu_code, issue_slots[24].out_uop.fu_code connect issue_slots[22].in_uop.bits.iq_type, issue_slots[24].out_uop.iq_type connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[24].out_uop.debug_pc connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[24].out_uop.is_rvc connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[24].out_uop.debug_inst connect issue_slots[22].in_uop.bits.inst, issue_slots[24].out_uop.inst connect issue_slots[22].in_uop.bits.uopc, issue_slots[24].out_uop.uopc node _T_328 = eq(_WIRE_28, UInt<3>(0h4)) when _T_328 : connect issue_slots[22].in_uop.valid, issue_slots[25].will_be_valid connect issue_slots[22].in_uop.bits.debug_tsrc, issue_slots[25].out_uop.debug_tsrc connect issue_slots[22].in_uop.bits.debug_fsrc, issue_slots[25].out_uop.debug_fsrc connect issue_slots[22].in_uop.bits.bp_xcpt_if, issue_slots[25].out_uop.bp_xcpt_if connect issue_slots[22].in_uop.bits.bp_debug_if, issue_slots[25].out_uop.bp_debug_if connect issue_slots[22].in_uop.bits.xcpt_ma_if, issue_slots[25].out_uop.xcpt_ma_if connect issue_slots[22].in_uop.bits.xcpt_ae_if, issue_slots[25].out_uop.xcpt_ae_if connect issue_slots[22].in_uop.bits.xcpt_pf_if, issue_slots[25].out_uop.xcpt_pf_if connect issue_slots[22].in_uop.bits.fp_single, issue_slots[25].out_uop.fp_single connect issue_slots[22].in_uop.bits.fp_val, issue_slots[25].out_uop.fp_val connect issue_slots[22].in_uop.bits.frs3_en, issue_slots[25].out_uop.frs3_en connect issue_slots[22].in_uop.bits.lrs2_rtype, issue_slots[25].out_uop.lrs2_rtype connect issue_slots[22].in_uop.bits.lrs1_rtype, issue_slots[25].out_uop.lrs1_rtype connect issue_slots[22].in_uop.bits.dst_rtype, issue_slots[25].out_uop.dst_rtype connect issue_slots[22].in_uop.bits.ldst_val, issue_slots[25].out_uop.ldst_val connect issue_slots[22].in_uop.bits.lrs3, issue_slots[25].out_uop.lrs3 connect issue_slots[22].in_uop.bits.lrs2, issue_slots[25].out_uop.lrs2 connect issue_slots[22].in_uop.bits.lrs1, issue_slots[25].out_uop.lrs1 connect issue_slots[22].in_uop.bits.ldst, issue_slots[25].out_uop.ldst connect issue_slots[22].in_uop.bits.ldst_is_rs1, issue_slots[25].out_uop.ldst_is_rs1 connect issue_slots[22].in_uop.bits.flush_on_commit, issue_slots[25].out_uop.flush_on_commit connect issue_slots[22].in_uop.bits.is_unique, issue_slots[25].out_uop.is_unique connect issue_slots[22].in_uop.bits.is_sys_pc2epc, issue_slots[25].out_uop.is_sys_pc2epc connect issue_slots[22].in_uop.bits.uses_stq, issue_slots[25].out_uop.uses_stq connect issue_slots[22].in_uop.bits.uses_ldq, issue_slots[25].out_uop.uses_ldq connect issue_slots[22].in_uop.bits.is_amo, issue_slots[25].out_uop.is_amo connect issue_slots[22].in_uop.bits.is_fencei, issue_slots[25].out_uop.is_fencei connect issue_slots[22].in_uop.bits.is_fence, issue_slots[25].out_uop.is_fence connect issue_slots[22].in_uop.bits.mem_signed, issue_slots[25].out_uop.mem_signed connect issue_slots[22].in_uop.bits.mem_size, issue_slots[25].out_uop.mem_size connect issue_slots[22].in_uop.bits.mem_cmd, issue_slots[25].out_uop.mem_cmd connect issue_slots[22].in_uop.bits.bypassable, issue_slots[25].out_uop.bypassable connect issue_slots[22].in_uop.bits.exc_cause, issue_slots[25].out_uop.exc_cause connect issue_slots[22].in_uop.bits.exception, issue_slots[25].out_uop.exception connect issue_slots[22].in_uop.bits.stale_pdst, issue_slots[25].out_uop.stale_pdst connect issue_slots[22].in_uop.bits.ppred_busy, issue_slots[25].out_uop.ppred_busy connect issue_slots[22].in_uop.bits.prs3_busy, issue_slots[25].out_uop.prs3_busy connect issue_slots[22].in_uop.bits.prs2_busy, issue_slots[25].out_uop.prs2_busy connect issue_slots[22].in_uop.bits.prs1_busy, issue_slots[25].out_uop.prs1_busy connect issue_slots[22].in_uop.bits.ppred, issue_slots[25].out_uop.ppred connect issue_slots[22].in_uop.bits.prs3, issue_slots[25].out_uop.prs3 connect issue_slots[22].in_uop.bits.prs2, issue_slots[25].out_uop.prs2 connect issue_slots[22].in_uop.bits.prs1, issue_slots[25].out_uop.prs1 connect issue_slots[22].in_uop.bits.pdst, issue_slots[25].out_uop.pdst connect issue_slots[22].in_uop.bits.rxq_idx, issue_slots[25].out_uop.rxq_idx connect issue_slots[22].in_uop.bits.stq_idx, issue_slots[25].out_uop.stq_idx connect issue_slots[22].in_uop.bits.ldq_idx, issue_slots[25].out_uop.ldq_idx connect issue_slots[22].in_uop.bits.rob_idx, issue_slots[25].out_uop.rob_idx connect issue_slots[22].in_uop.bits.csr_addr, issue_slots[25].out_uop.csr_addr connect issue_slots[22].in_uop.bits.imm_packed, issue_slots[25].out_uop.imm_packed connect issue_slots[22].in_uop.bits.taken, issue_slots[25].out_uop.taken connect issue_slots[22].in_uop.bits.pc_lob, issue_slots[25].out_uop.pc_lob connect issue_slots[22].in_uop.bits.edge_inst, issue_slots[25].out_uop.edge_inst connect issue_slots[22].in_uop.bits.ftq_idx, issue_slots[25].out_uop.ftq_idx connect issue_slots[22].in_uop.bits.br_tag, issue_slots[25].out_uop.br_tag connect issue_slots[22].in_uop.bits.br_mask, issue_slots[25].out_uop.br_mask connect issue_slots[22].in_uop.bits.is_sfb, issue_slots[25].out_uop.is_sfb connect issue_slots[22].in_uop.bits.is_jal, issue_slots[25].out_uop.is_jal connect issue_slots[22].in_uop.bits.is_jalr, issue_slots[25].out_uop.is_jalr connect issue_slots[22].in_uop.bits.is_br, issue_slots[25].out_uop.is_br connect issue_slots[22].in_uop.bits.iw_p2_poisoned, issue_slots[25].out_uop.iw_p2_poisoned connect issue_slots[22].in_uop.bits.iw_p1_poisoned, issue_slots[25].out_uop.iw_p1_poisoned connect issue_slots[22].in_uop.bits.iw_state, issue_slots[25].out_uop.iw_state connect issue_slots[22].in_uop.bits.ctrl.is_std, issue_slots[25].out_uop.ctrl.is_std connect issue_slots[22].in_uop.bits.ctrl.is_sta, issue_slots[25].out_uop.ctrl.is_sta connect issue_slots[22].in_uop.bits.ctrl.is_load, issue_slots[25].out_uop.ctrl.is_load connect issue_slots[22].in_uop.bits.ctrl.csr_cmd, issue_slots[25].out_uop.ctrl.csr_cmd connect issue_slots[22].in_uop.bits.ctrl.fcn_dw, issue_slots[25].out_uop.ctrl.fcn_dw connect issue_slots[22].in_uop.bits.ctrl.op_fcn, issue_slots[25].out_uop.ctrl.op_fcn connect issue_slots[22].in_uop.bits.ctrl.imm_sel, issue_slots[25].out_uop.ctrl.imm_sel connect issue_slots[22].in_uop.bits.ctrl.op2_sel, issue_slots[25].out_uop.ctrl.op2_sel connect issue_slots[22].in_uop.bits.ctrl.op1_sel, issue_slots[25].out_uop.ctrl.op1_sel connect issue_slots[22].in_uop.bits.ctrl.br_type, issue_slots[25].out_uop.ctrl.br_type connect issue_slots[22].in_uop.bits.fu_code, issue_slots[25].out_uop.fu_code connect issue_slots[22].in_uop.bits.iq_type, issue_slots[25].out_uop.iq_type connect issue_slots[22].in_uop.bits.debug_pc, issue_slots[25].out_uop.debug_pc connect issue_slots[22].in_uop.bits.is_rvc, issue_slots[25].out_uop.is_rvc connect issue_slots[22].in_uop.bits.debug_inst, issue_slots[25].out_uop.debug_inst connect issue_slots[22].in_uop.bits.inst, issue_slots[25].out_uop.inst connect issue_slots[22].in_uop.bits.uopc, issue_slots[25].out_uop.uopc node _issue_slots_22_clear_T = neq(_WIRE_25, UInt<1>(0h0)) connect issue_slots[22].clear, _issue_slots_22_clear_T connect issue_slots[23].in_uop.valid, UInt<1>(0h0) connect issue_slots[23].in_uop.bits.debug_tsrc, issue_slots[24].out_uop.debug_tsrc connect issue_slots[23].in_uop.bits.debug_fsrc, issue_slots[24].out_uop.debug_fsrc connect issue_slots[23].in_uop.bits.bp_xcpt_if, issue_slots[24].out_uop.bp_xcpt_if connect issue_slots[23].in_uop.bits.bp_debug_if, issue_slots[24].out_uop.bp_debug_if connect issue_slots[23].in_uop.bits.xcpt_ma_if, issue_slots[24].out_uop.xcpt_ma_if connect issue_slots[23].in_uop.bits.xcpt_ae_if, issue_slots[24].out_uop.xcpt_ae_if connect issue_slots[23].in_uop.bits.xcpt_pf_if, issue_slots[24].out_uop.xcpt_pf_if connect issue_slots[23].in_uop.bits.fp_single, issue_slots[24].out_uop.fp_single connect issue_slots[23].in_uop.bits.fp_val, issue_slots[24].out_uop.fp_val connect issue_slots[23].in_uop.bits.frs3_en, issue_slots[24].out_uop.frs3_en connect issue_slots[23].in_uop.bits.lrs2_rtype, issue_slots[24].out_uop.lrs2_rtype connect issue_slots[23].in_uop.bits.lrs1_rtype, issue_slots[24].out_uop.lrs1_rtype connect issue_slots[23].in_uop.bits.dst_rtype, issue_slots[24].out_uop.dst_rtype connect issue_slots[23].in_uop.bits.ldst_val, issue_slots[24].out_uop.ldst_val connect issue_slots[23].in_uop.bits.lrs3, issue_slots[24].out_uop.lrs3 connect issue_slots[23].in_uop.bits.lrs2, issue_slots[24].out_uop.lrs2 connect issue_slots[23].in_uop.bits.lrs1, issue_slots[24].out_uop.lrs1 connect issue_slots[23].in_uop.bits.ldst, issue_slots[24].out_uop.ldst connect issue_slots[23].in_uop.bits.ldst_is_rs1, issue_slots[24].out_uop.ldst_is_rs1 connect issue_slots[23].in_uop.bits.flush_on_commit, issue_slots[24].out_uop.flush_on_commit connect issue_slots[23].in_uop.bits.is_unique, issue_slots[24].out_uop.is_unique connect issue_slots[23].in_uop.bits.is_sys_pc2epc, issue_slots[24].out_uop.is_sys_pc2epc connect issue_slots[23].in_uop.bits.uses_stq, issue_slots[24].out_uop.uses_stq connect issue_slots[23].in_uop.bits.uses_ldq, issue_slots[24].out_uop.uses_ldq connect issue_slots[23].in_uop.bits.is_amo, issue_slots[24].out_uop.is_amo connect issue_slots[23].in_uop.bits.is_fencei, issue_slots[24].out_uop.is_fencei connect issue_slots[23].in_uop.bits.is_fence, issue_slots[24].out_uop.is_fence connect issue_slots[23].in_uop.bits.mem_signed, issue_slots[24].out_uop.mem_signed connect issue_slots[23].in_uop.bits.mem_size, issue_slots[24].out_uop.mem_size connect issue_slots[23].in_uop.bits.mem_cmd, issue_slots[24].out_uop.mem_cmd connect issue_slots[23].in_uop.bits.bypassable, issue_slots[24].out_uop.bypassable connect issue_slots[23].in_uop.bits.exc_cause, issue_slots[24].out_uop.exc_cause connect issue_slots[23].in_uop.bits.exception, issue_slots[24].out_uop.exception connect issue_slots[23].in_uop.bits.stale_pdst, issue_slots[24].out_uop.stale_pdst connect issue_slots[23].in_uop.bits.ppred_busy, issue_slots[24].out_uop.ppred_busy connect issue_slots[23].in_uop.bits.prs3_busy, issue_slots[24].out_uop.prs3_busy connect issue_slots[23].in_uop.bits.prs2_busy, issue_slots[24].out_uop.prs2_busy connect issue_slots[23].in_uop.bits.prs1_busy, issue_slots[24].out_uop.prs1_busy connect issue_slots[23].in_uop.bits.ppred, issue_slots[24].out_uop.ppred connect issue_slots[23].in_uop.bits.prs3, issue_slots[24].out_uop.prs3 connect issue_slots[23].in_uop.bits.prs2, issue_slots[24].out_uop.prs2 connect issue_slots[23].in_uop.bits.prs1, issue_slots[24].out_uop.prs1 connect issue_slots[23].in_uop.bits.pdst, issue_slots[24].out_uop.pdst connect issue_slots[23].in_uop.bits.rxq_idx, issue_slots[24].out_uop.rxq_idx connect issue_slots[23].in_uop.bits.stq_idx, issue_slots[24].out_uop.stq_idx connect issue_slots[23].in_uop.bits.ldq_idx, issue_slots[24].out_uop.ldq_idx connect issue_slots[23].in_uop.bits.rob_idx, issue_slots[24].out_uop.rob_idx connect issue_slots[23].in_uop.bits.csr_addr, issue_slots[24].out_uop.csr_addr connect issue_slots[23].in_uop.bits.imm_packed, issue_slots[24].out_uop.imm_packed connect issue_slots[23].in_uop.bits.taken, issue_slots[24].out_uop.taken connect issue_slots[23].in_uop.bits.pc_lob, issue_slots[24].out_uop.pc_lob connect issue_slots[23].in_uop.bits.edge_inst, issue_slots[24].out_uop.edge_inst connect issue_slots[23].in_uop.bits.ftq_idx, issue_slots[24].out_uop.ftq_idx connect issue_slots[23].in_uop.bits.br_tag, issue_slots[24].out_uop.br_tag connect issue_slots[23].in_uop.bits.br_mask, issue_slots[24].out_uop.br_mask connect issue_slots[23].in_uop.bits.is_sfb, issue_slots[24].out_uop.is_sfb connect issue_slots[23].in_uop.bits.is_jal, issue_slots[24].out_uop.is_jal connect issue_slots[23].in_uop.bits.is_jalr, issue_slots[24].out_uop.is_jalr connect issue_slots[23].in_uop.bits.is_br, issue_slots[24].out_uop.is_br connect issue_slots[23].in_uop.bits.iw_p2_poisoned, issue_slots[24].out_uop.iw_p2_poisoned connect issue_slots[23].in_uop.bits.iw_p1_poisoned, issue_slots[24].out_uop.iw_p1_poisoned connect issue_slots[23].in_uop.bits.iw_state, issue_slots[24].out_uop.iw_state connect issue_slots[23].in_uop.bits.ctrl.is_std, issue_slots[24].out_uop.ctrl.is_std connect issue_slots[23].in_uop.bits.ctrl.is_sta, issue_slots[24].out_uop.ctrl.is_sta connect issue_slots[23].in_uop.bits.ctrl.is_load, issue_slots[24].out_uop.ctrl.is_load connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, issue_slots[24].out_uop.ctrl.csr_cmd connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, issue_slots[24].out_uop.ctrl.fcn_dw connect issue_slots[23].in_uop.bits.ctrl.op_fcn, issue_slots[24].out_uop.ctrl.op_fcn connect issue_slots[23].in_uop.bits.ctrl.imm_sel, issue_slots[24].out_uop.ctrl.imm_sel connect issue_slots[23].in_uop.bits.ctrl.op2_sel, issue_slots[24].out_uop.ctrl.op2_sel connect issue_slots[23].in_uop.bits.ctrl.op1_sel, issue_slots[24].out_uop.ctrl.op1_sel connect issue_slots[23].in_uop.bits.ctrl.br_type, issue_slots[24].out_uop.ctrl.br_type connect issue_slots[23].in_uop.bits.fu_code, issue_slots[24].out_uop.fu_code connect issue_slots[23].in_uop.bits.iq_type, issue_slots[24].out_uop.iq_type connect issue_slots[23].in_uop.bits.debug_pc, issue_slots[24].out_uop.debug_pc connect issue_slots[23].in_uop.bits.is_rvc, issue_slots[24].out_uop.is_rvc connect issue_slots[23].in_uop.bits.debug_inst, issue_slots[24].out_uop.debug_inst connect issue_slots[23].in_uop.bits.inst, issue_slots[24].out_uop.inst connect issue_slots[23].in_uop.bits.uopc, issue_slots[24].out_uop.uopc node _T_329 = eq(_WIRE_27, UInt<1>(0h1)) when _T_329 : connect issue_slots[23].in_uop.valid, issue_slots[24].will_be_valid connect issue_slots[23].in_uop.bits.debug_tsrc, issue_slots[24].out_uop.debug_tsrc connect issue_slots[23].in_uop.bits.debug_fsrc, issue_slots[24].out_uop.debug_fsrc connect issue_slots[23].in_uop.bits.bp_xcpt_if, issue_slots[24].out_uop.bp_xcpt_if connect issue_slots[23].in_uop.bits.bp_debug_if, issue_slots[24].out_uop.bp_debug_if connect issue_slots[23].in_uop.bits.xcpt_ma_if, issue_slots[24].out_uop.xcpt_ma_if connect issue_slots[23].in_uop.bits.xcpt_ae_if, issue_slots[24].out_uop.xcpt_ae_if connect issue_slots[23].in_uop.bits.xcpt_pf_if, issue_slots[24].out_uop.xcpt_pf_if connect issue_slots[23].in_uop.bits.fp_single, issue_slots[24].out_uop.fp_single connect issue_slots[23].in_uop.bits.fp_val, issue_slots[24].out_uop.fp_val connect issue_slots[23].in_uop.bits.frs3_en, issue_slots[24].out_uop.frs3_en connect issue_slots[23].in_uop.bits.lrs2_rtype, issue_slots[24].out_uop.lrs2_rtype connect issue_slots[23].in_uop.bits.lrs1_rtype, issue_slots[24].out_uop.lrs1_rtype connect issue_slots[23].in_uop.bits.dst_rtype, issue_slots[24].out_uop.dst_rtype connect issue_slots[23].in_uop.bits.ldst_val, issue_slots[24].out_uop.ldst_val connect issue_slots[23].in_uop.bits.lrs3, issue_slots[24].out_uop.lrs3 connect issue_slots[23].in_uop.bits.lrs2, issue_slots[24].out_uop.lrs2 connect issue_slots[23].in_uop.bits.lrs1, issue_slots[24].out_uop.lrs1 connect issue_slots[23].in_uop.bits.ldst, issue_slots[24].out_uop.ldst connect issue_slots[23].in_uop.bits.ldst_is_rs1, issue_slots[24].out_uop.ldst_is_rs1 connect issue_slots[23].in_uop.bits.flush_on_commit, issue_slots[24].out_uop.flush_on_commit connect issue_slots[23].in_uop.bits.is_unique, issue_slots[24].out_uop.is_unique connect issue_slots[23].in_uop.bits.is_sys_pc2epc, issue_slots[24].out_uop.is_sys_pc2epc connect issue_slots[23].in_uop.bits.uses_stq, issue_slots[24].out_uop.uses_stq connect issue_slots[23].in_uop.bits.uses_ldq, issue_slots[24].out_uop.uses_ldq connect issue_slots[23].in_uop.bits.is_amo, issue_slots[24].out_uop.is_amo connect issue_slots[23].in_uop.bits.is_fencei, issue_slots[24].out_uop.is_fencei connect issue_slots[23].in_uop.bits.is_fence, issue_slots[24].out_uop.is_fence connect issue_slots[23].in_uop.bits.mem_signed, issue_slots[24].out_uop.mem_signed connect issue_slots[23].in_uop.bits.mem_size, issue_slots[24].out_uop.mem_size connect issue_slots[23].in_uop.bits.mem_cmd, issue_slots[24].out_uop.mem_cmd connect issue_slots[23].in_uop.bits.bypassable, issue_slots[24].out_uop.bypassable connect issue_slots[23].in_uop.bits.exc_cause, issue_slots[24].out_uop.exc_cause connect issue_slots[23].in_uop.bits.exception, issue_slots[24].out_uop.exception connect issue_slots[23].in_uop.bits.stale_pdst, issue_slots[24].out_uop.stale_pdst connect issue_slots[23].in_uop.bits.ppred_busy, issue_slots[24].out_uop.ppred_busy connect issue_slots[23].in_uop.bits.prs3_busy, issue_slots[24].out_uop.prs3_busy connect issue_slots[23].in_uop.bits.prs2_busy, issue_slots[24].out_uop.prs2_busy connect issue_slots[23].in_uop.bits.prs1_busy, issue_slots[24].out_uop.prs1_busy connect issue_slots[23].in_uop.bits.ppred, issue_slots[24].out_uop.ppred connect issue_slots[23].in_uop.bits.prs3, issue_slots[24].out_uop.prs3 connect issue_slots[23].in_uop.bits.prs2, issue_slots[24].out_uop.prs2 connect issue_slots[23].in_uop.bits.prs1, issue_slots[24].out_uop.prs1 connect issue_slots[23].in_uop.bits.pdst, issue_slots[24].out_uop.pdst connect issue_slots[23].in_uop.bits.rxq_idx, issue_slots[24].out_uop.rxq_idx connect issue_slots[23].in_uop.bits.stq_idx, issue_slots[24].out_uop.stq_idx connect issue_slots[23].in_uop.bits.ldq_idx, issue_slots[24].out_uop.ldq_idx connect issue_slots[23].in_uop.bits.rob_idx, issue_slots[24].out_uop.rob_idx connect issue_slots[23].in_uop.bits.csr_addr, issue_slots[24].out_uop.csr_addr connect issue_slots[23].in_uop.bits.imm_packed, issue_slots[24].out_uop.imm_packed connect issue_slots[23].in_uop.bits.taken, issue_slots[24].out_uop.taken connect issue_slots[23].in_uop.bits.pc_lob, issue_slots[24].out_uop.pc_lob connect issue_slots[23].in_uop.bits.edge_inst, issue_slots[24].out_uop.edge_inst connect issue_slots[23].in_uop.bits.ftq_idx, issue_slots[24].out_uop.ftq_idx connect issue_slots[23].in_uop.bits.br_tag, issue_slots[24].out_uop.br_tag connect issue_slots[23].in_uop.bits.br_mask, issue_slots[24].out_uop.br_mask connect issue_slots[23].in_uop.bits.is_sfb, issue_slots[24].out_uop.is_sfb connect issue_slots[23].in_uop.bits.is_jal, issue_slots[24].out_uop.is_jal connect issue_slots[23].in_uop.bits.is_jalr, issue_slots[24].out_uop.is_jalr connect issue_slots[23].in_uop.bits.is_br, issue_slots[24].out_uop.is_br connect issue_slots[23].in_uop.bits.iw_p2_poisoned, issue_slots[24].out_uop.iw_p2_poisoned connect issue_slots[23].in_uop.bits.iw_p1_poisoned, issue_slots[24].out_uop.iw_p1_poisoned connect issue_slots[23].in_uop.bits.iw_state, issue_slots[24].out_uop.iw_state connect issue_slots[23].in_uop.bits.ctrl.is_std, issue_slots[24].out_uop.ctrl.is_std connect issue_slots[23].in_uop.bits.ctrl.is_sta, issue_slots[24].out_uop.ctrl.is_sta connect issue_slots[23].in_uop.bits.ctrl.is_load, issue_slots[24].out_uop.ctrl.is_load connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, issue_slots[24].out_uop.ctrl.csr_cmd connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, issue_slots[24].out_uop.ctrl.fcn_dw connect issue_slots[23].in_uop.bits.ctrl.op_fcn, issue_slots[24].out_uop.ctrl.op_fcn connect issue_slots[23].in_uop.bits.ctrl.imm_sel, issue_slots[24].out_uop.ctrl.imm_sel connect issue_slots[23].in_uop.bits.ctrl.op2_sel, issue_slots[24].out_uop.ctrl.op2_sel connect issue_slots[23].in_uop.bits.ctrl.op1_sel, issue_slots[24].out_uop.ctrl.op1_sel connect issue_slots[23].in_uop.bits.ctrl.br_type, issue_slots[24].out_uop.ctrl.br_type connect issue_slots[23].in_uop.bits.fu_code, issue_slots[24].out_uop.fu_code connect issue_slots[23].in_uop.bits.iq_type, issue_slots[24].out_uop.iq_type connect issue_slots[23].in_uop.bits.debug_pc, issue_slots[24].out_uop.debug_pc connect issue_slots[23].in_uop.bits.is_rvc, issue_slots[24].out_uop.is_rvc connect issue_slots[23].in_uop.bits.debug_inst, issue_slots[24].out_uop.debug_inst connect issue_slots[23].in_uop.bits.inst, issue_slots[24].out_uop.inst connect issue_slots[23].in_uop.bits.uopc, issue_slots[24].out_uop.uopc node _T_330 = eq(_WIRE_28, UInt<2>(0h2)) when _T_330 : connect issue_slots[23].in_uop.valid, issue_slots[25].will_be_valid connect issue_slots[23].in_uop.bits.debug_tsrc, issue_slots[25].out_uop.debug_tsrc connect issue_slots[23].in_uop.bits.debug_fsrc, issue_slots[25].out_uop.debug_fsrc connect issue_slots[23].in_uop.bits.bp_xcpt_if, issue_slots[25].out_uop.bp_xcpt_if connect issue_slots[23].in_uop.bits.bp_debug_if, issue_slots[25].out_uop.bp_debug_if connect issue_slots[23].in_uop.bits.xcpt_ma_if, issue_slots[25].out_uop.xcpt_ma_if connect issue_slots[23].in_uop.bits.xcpt_ae_if, issue_slots[25].out_uop.xcpt_ae_if connect issue_slots[23].in_uop.bits.xcpt_pf_if, issue_slots[25].out_uop.xcpt_pf_if connect issue_slots[23].in_uop.bits.fp_single, issue_slots[25].out_uop.fp_single connect issue_slots[23].in_uop.bits.fp_val, issue_slots[25].out_uop.fp_val connect issue_slots[23].in_uop.bits.frs3_en, issue_slots[25].out_uop.frs3_en connect issue_slots[23].in_uop.bits.lrs2_rtype, issue_slots[25].out_uop.lrs2_rtype connect issue_slots[23].in_uop.bits.lrs1_rtype, issue_slots[25].out_uop.lrs1_rtype connect issue_slots[23].in_uop.bits.dst_rtype, issue_slots[25].out_uop.dst_rtype connect issue_slots[23].in_uop.bits.ldst_val, issue_slots[25].out_uop.ldst_val connect issue_slots[23].in_uop.bits.lrs3, issue_slots[25].out_uop.lrs3 connect issue_slots[23].in_uop.bits.lrs2, issue_slots[25].out_uop.lrs2 connect issue_slots[23].in_uop.bits.lrs1, issue_slots[25].out_uop.lrs1 connect issue_slots[23].in_uop.bits.ldst, issue_slots[25].out_uop.ldst connect issue_slots[23].in_uop.bits.ldst_is_rs1, issue_slots[25].out_uop.ldst_is_rs1 connect issue_slots[23].in_uop.bits.flush_on_commit, issue_slots[25].out_uop.flush_on_commit connect issue_slots[23].in_uop.bits.is_unique, issue_slots[25].out_uop.is_unique connect issue_slots[23].in_uop.bits.is_sys_pc2epc, issue_slots[25].out_uop.is_sys_pc2epc connect issue_slots[23].in_uop.bits.uses_stq, issue_slots[25].out_uop.uses_stq connect issue_slots[23].in_uop.bits.uses_ldq, issue_slots[25].out_uop.uses_ldq connect issue_slots[23].in_uop.bits.is_amo, issue_slots[25].out_uop.is_amo connect issue_slots[23].in_uop.bits.is_fencei, issue_slots[25].out_uop.is_fencei connect issue_slots[23].in_uop.bits.is_fence, issue_slots[25].out_uop.is_fence connect issue_slots[23].in_uop.bits.mem_signed, issue_slots[25].out_uop.mem_signed connect issue_slots[23].in_uop.bits.mem_size, issue_slots[25].out_uop.mem_size connect issue_slots[23].in_uop.bits.mem_cmd, issue_slots[25].out_uop.mem_cmd connect issue_slots[23].in_uop.bits.bypassable, issue_slots[25].out_uop.bypassable connect issue_slots[23].in_uop.bits.exc_cause, issue_slots[25].out_uop.exc_cause connect issue_slots[23].in_uop.bits.exception, issue_slots[25].out_uop.exception connect issue_slots[23].in_uop.bits.stale_pdst, issue_slots[25].out_uop.stale_pdst connect issue_slots[23].in_uop.bits.ppred_busy, issue_slots[25].out_uop.ppred_busy connect issue_slots[23].in_uop.bits.prs3_busy, issue_slots[25].out_uop.prs3_busy connect issue_slots[23].in_uop.bits.prs2_busy, issue_slots[25].out_uop.prs2_busy connect issue_slots[23].in_uop.bits.prs1_busy, issue_slots[25].out_uop.prs1_busy connect issue_slots[23].in_uop.bits.ppred, issue_slots[25].out_uop.ppred connect issue_slots[23].in_uop.bits.prs3, issue_slots[25].out_uop.prs3 connect issue_slots[23].in_uop.bits.prs2, issue_slots[25].out_uop.prs2 connect issue_slots[23].in_uop.bits.prs1, issue_slots[25].out_uop.prs1 connect issue_slots[23].in_uop.bits.pdst, issue_slots[25].out_uop.pdst connect issue_slots[23].in_uop.bits.rxq_idx, issue_slots[25].out_uop.rxq_idx connect issue_slots[23].in_uop.bits.stq_idx, issue_slots[25].out_uop.stq_idx connect issue_slots[23].in_uop.bits.ldq_idx, issue_slots[25].out_uop.ldq_idx connect issue_slots[23].in_uop.bits.rob_idx, issue_slots[25].out_uop.rob_idx connect issue_slots[23].in_uop.bits.csr_addr, issue_slots[25].out_uop.csr_addr connect issue_slots[23].in_uop.bits.imm_packed, issue_slots[25].out_uop.imm_packed connect issue_slots[23].in_uop.bits.taken, issue_slots[25].out_uop.taken connect issue_slots[23].in_uop.bits.pc_lob, issue_slots[25].out_uop.pc_lob connect issue_slots[23].in_uop.bits.edge_inst, issue_slots[25].out_uop.edge_inst connect issue_slots[23].in_uop.bits.ftq_idx, issue_slots[25].out_uop.ftq_idx connect issue_slots[23].in_uop.bits.br_tag, issue_slots[25].out_uop.br_tag connect issue_slots[23].in_uop.bits.br_mask, issue_slots[25].out_uop.br_mask connect issue_slots[23].in_uop.bits.is_sfb, issue_slots[25].out_uop.is_sfb connect issue_slots[23].in_uop.bits.is_jal, issue_slots[25].out_uop.is_jal connect issue_slots[23].in_uop.bits.is_jalr, issue_slots[25].out_uop.is_jalr connect issue_slots[23].in_uop.bits.is_br, issue_slots[25].out_uop.is_br connect issue_slots[23].in_uop.bits.iw_p2_poisoned, issue_slots[25].out_uop.iw_p2_poisoned connect issue_slots[23].in_uop.bits.iw_p1_poisoned, issue_slots[25].out_uop.iw_p1_poisoned connect issue_slots[23].in_uop.bits.iw_state, issue_slots[25].out_uop.iw_state connect issue_slots[23].in_uop.bits.ctrl.is_std, issue_slots[25].out_uop.ctrl.is_std connect issue_slots[23].in_uop.bits.ctrl.is_sta, issue_slots[25].out_uop.ctrl.is_sta connect issue_slots[23].in_uop.bits.ctrl.is_load, issue_slots[25].out_uop.ctrl.is_load connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, issue_slots[25].out_uop.ctrl.csr_cmd connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, issue_slots[25].out_uop.ctrl.fcn_dw connect issue_slots[23].in_uop.bits.ctrl.op_fcn, issue_slots[25].out_uop.ctrl.op_fcn connect issue_slots[23].in_uop.bits.ctrl.imm_sel, issue_slots[25].out_uop.ctrl.imm_sel connect issue_slots[23].in_uop.bits.ctrl.op2_sel, issue_slots[25].out_uop.ctrl.op2_sel connect issue_slots[23].in_uop.bits.ctrl.op1_sel, issue_slots[25].out_uop.ctrl.op1_sel connect issue_slots[23].in_uop.bits.ctrl.br_type, issue_slots[25].out_uop.ctrl.br_type connect issue_slots[23].in_uop.bits.fu_code, issue_slots[25].out_uop.fu_code connect issue_slots[23].in_uop.bits.iq_type, issue_slots[25].out_uop.iq_type connect issue_slots[23].in_uop.bits.debug_pc, issue_slots[25].out_uop.debug_pc connect issue_slots[23].in_uop.bits.is_rvc, issue_slots[25].out_uop.is_rvc connect issue_slots[23].in_uop.bits.debug_inst, issue_slots[25].out_uop.debug_inst connect issue_slots[23].in_uop.bits.inst, issue_slots[25].out_uop.inst connect issue_slots[23].in_uop.bits.uopc, issue_slots[25].out_uop.uopc node _T_331 = eq(_WIRE_29, UInt<3>(0h4)) when _T_331 : connect issue_slots[23].in_uop.valid, issue_slots[26].will_be_valid connect issue_slots[23].in_uop.bits.debug_tsrc, issue_slots[26].out_uop.debug_tsrc connect issue_slots[23].in_uop.bits.debug_fsrc, issue_slots[26].out_uop.debug_fsrc connect issue_slots[23].in_uop.bits.bp_xcpt_if, issue_slots[26].out_uop.bp_xcpt_if connect issue_slots[23].in_uop.bits.bp_debug_if, issue_slots[26].out_uop.bp_debug_if connect issue_slots[23].in_uop.bits.xcpt_ma_if, issue_slots[26].out_uop.xcpt_ma_if connect issue_slots[23].in_uop.bits.xcpt_ae_if, issue_slots[26].out_uop.xcpt_ae_if connect issue_slots[23].in_uop.bits.xcpt_pf_if, issue_slots[26].out_uop.xcpt_pf_if connect issue_slots[23].in_uop.bits.fp_single, issue_slots[26].out_uop.fp_single connect issue_slots[23].in_uop.bits.fp_val, issue_slots[26].out_uop.fp_val connect issue_slots[23].in_uop.bits.frs3_en, issue_slots[26].out_uop.frs3_en connect issue_slots[23].in_uop.bits.lrs2_rtype, issue_slots[26].out_uop.lrs2_rtype connect issue_slots[23].in_uop.bits.lrs1_rtype, issue_slots[26].out_uop.lrs1_rtype connect issue_slots[23].in_uop.bits.dst_rtype, issue_slots[26].out_uop.dst_rtype connect issue_slots[23].in_uop.bits.ldst_val, issue_slots[26].out_uop.ldst_val connect issue_slots[23].in_uop.bits.lrs3, issue_slots[26].out_uop.lrs3 connect issue_slots[23].in_uop.bits.lrs2, issue_slots[26].out_uop.lrs2 connect issue_slots[23].in_uop.bits.lrs1, issue_slots[26].out_uop.lrs1 connect issue_slots[23].in_uop.bits.ldst, issue_slots[26].out_uop.ldst connect issue_slots[23].in_uop.bits.ldst_is_rs1, issue_slots[26].out_uop.ldst_is_rs1 connect issue_slots[23].in_uop.bits.flush_on_commit, issue_slots[26].out_uop.flush_on_commit connect issue_slots[23].in_uop.bits.is_unique, issue_slots[26].out_uop.is_unique connect issue_slots[23].in_uop.bits.is_sys_pc2epc, issue_slots[26].out_uop.is_sys_pc2epc connect issue_slots[23].in_uop.bits.uses_stq, issue_slots[26].out_uop.uses_stq connect issue_slots[23].in_uop.bits.uses_ldq, issue_slots[26].out_uop.uses_ldq connect issue_slots[23].in_uop.bits.is_amo, issue_slots[26].out_uop.is_amo connect issue_slots[23].in_uop.bits.is_fencei, issue_slots[26].out_uop.is_fencei connect issue_slots[23].in_uop.bits.is_fence, issue_slots[26].out_uop.is_fence connect issue_slots[23].in_uop.bits.mem_signed, issue_slots[26].out_uop.mem_signed connect issue_slots[23].in_uop.bits.mem_size, issue_slots[26].out_uop.mem_size connect issue_slots[23].in_uop.bits.mem_cmd, issue_slots[26].out_uop.mem_cmd connect issue_slots[23].in_uop.bits.bypassable, issue_slots[26].out_uop.bypassable connect issue_slots[23].in_uop.bits.exc_cause, issue_slots[26].out_uop.exc_cause connect issue_slots[23].in_uop.bits.exception, issue_slots[26].out_uop.exception connect issue_slots[23].in_uop.bits.stale_pdst, issue_slots[26].out_uop.stale_pdst connect issue_slots[23].in_uop.bits.ppred_busy, issue_slots[26].out_uop.ppred_busy connect issue_slots[23].in_uop.bits.prs3_busy, issue_slots[26].out_uop.prs3_busy connect issue_slots[23].in_uop.bits.prs2_busy, issue_slots[26].out_uop.prs2_busy connect issue_slots[23].in_uop.bits.prs1_busy, issue_slots[26].out_uop.prs1_busy connect issue_slots[23].in_uop.bits.ppred, issue_slots[26].out_uop.ppred connect issue_slots[23].in_uop.bits.prs3, issue_slots[26].out_uop.prs3 connect issue_slots[23].in_uop.bits.prs2, issue_slots[26].out_uop.prs2 connect issue_slots[23].in_uop.bits.prs1, issue_slots[26].out_uop.prs1 connect issue_slots[23].in_uop.bits.pdst, issue_slots[26].out_uop.pdst connect issue_slots[23].in_uop.bits.rxq_idx, issue_slots[26].out_uop.rxq_idx connect issue_slots[23].in_uop.bits.stq_idx, issue_slots[26].out_uop.stq_idx connect issue_slots[23].in_uop.bits.ldq_idx, issue_slots[26].out_uop.ldq_idx connect issue_slots[23].in_uop.bits.rob_idx, issue_slots[26].out_uop.rob_idx connect issue_slots[23].in_uop.bits.csr_addr, issue_slots[26].out_uop.csr_addr connect issue_slots[23].in_uop.bits.imm_packed, issue_slots[26].out_uop.imm_packed connect issue_slots[23].in_uop.bits.taken, issue_slots[26].out_uop.taken connect issue_slots[23].in_uop.bits.pc_lob, issue_slots[26].out_uop.pc_lob connect issue_slots[23].in_uop.bits.edge_inst, issue_slots[26].out_uop.edge_inst connect issue_slots[23].in_uop.bits.ftq_idx, issue_slots[26].out_uop.ftq_idx connect issue_slots[23].in_uop.bits.br_tag, issue_slots[26].out_uop.br_tag connect issue_slots[23].in_uop.bits.br_mask, issue_slots[26].out_uop.br_mask connect issue_slots[23].in_uop.bits.is_sfb, issue_slots[26].out_uop.is_sfb connect issue_slots[23].in_uop.bits.is_jal, issue_slots[26].out_uop.is_jal connect issue_slots[23].in_uop.bits.is_jalr, issue_slots[26].out_uop.is_jalr connect issue_slots[23].in_uop.bits.is_br, issue_slots[26].out_uop.is_br connect issue_slots[23].in_uop.bits.iw_p2_poisoned, issue_slots[26].out_uop.iw_p2_poisoned connect issue_slots[23].in_uop.bits.iw_p1_poisoned, issue_slots[26].out_uop.iw_p1_poisoned connect issue_slots[23].in_uop.bits.iw_state, issue_slots[26].out_uop.iw_state connect issue_slots[23].in_uop.bits.ctrl.is_std, issue_slots[26].out_uop.ctrl.is_std connect issue_slots[23].in_uop.bits.ctrl.is_sta, issue_slots[26].out_uop.ctrl.is_sta connect issue_slots[23].in_uop.bits.ctrl.is_load, issue_slots[26].out_uop.ctrl.is_load connect issue_slots[23].in_uop.bits.ctrl.csr_cmd, issue_slots[26].out_uop.ctrl.csr_cmd connect issue_slots[23].in_uop.bits.ctrl.fcn_dw, issue_slots[26].out_uop.ctrl.fcn_dw connect issue_slots[23].in_uop.bits.ctrl.op_fcn, issue_slots[26].out_uop.ctrl.op_fcn connect issue_slots[23].in_uop.bits.ctrl.imm_sel, issue_slots[26].out_uop.ctrl.imm_sel connect issue_slots[23].in_uop.bits.ctrl.op2_sel, issue_slots[26].out_uop.ctrl.op2_sel connect issue_slots[23].in_uop.bits.ctrl.op1_sel, issue_slots[26].out_uop.ctrl.op1_sel connect issue_slots[23].in_uop.bits.ctrl.br_type, issue_slots[26].out_uop.ctrl.br_type connect issue_slots[23].in_uop.bits.fu_code, issue_slots[26].out_uop.fu_code connect issue_slots[23].in_uop.bits.iq_type, issue_slots[26].out_uop.iq_type connect issue_slots[23].in_uop.bits.debug_pc, issue_slots[26].out_uop.debug_pc connect issue_slots[23].in_uop.bits.is_rvc, issue_slots[26].out_uop.is_rvc connect issue_slots[23].in_uop.bits.debug_inst, issue_slots[26].out_uop.debug_inst connect issue_slots[23].in_uop.bits.inst, issue_slots[26].out_uop.inst connect issue_slots[23].in_uop.bits.uopc, issue_slots[26].out_uop.uopc node _issue_slots_23_clear_T = neq(_WIRE_26, UInt<1>(0h0)) connect issue_slots[23].clear, _issue_slots_23_clear_T connect issue_slots[24].in_uop.valid, UInt<1>(0h0) connect issue_slots[24].in_uop.bits.debug_tsrc, issue_slots[25].out_uop.debug_tsrc connect issue_slots[24].in_uop.bits.debug_fsrc, issue_slots[25].out_uop.debug_fsrc connect issue_slots[24].in_uop.bits.bp_xcpt_if, issue_slots[25].out_uop.bp_xcpt_if connect issue_slots[24].in_uop.bits.bp_debug_if, issue_slots[25].out_uop.bp_debug_if connect issue_slots[24].in_uop.bits.xcpt_ma_if, issue_slots[25].out_uop.xcpt_ma_if connect issue_slots[24].in_uop.bits.xcpt_ae_if, issue_slots[25].out_uop.xcpt_ae_if connect issue_slots[24].in_uop.bits.xcpt_pf_if, issue_slots[25].out_uop.xcpt_pf_if connect issue_slots[24].in_uop.bits.fp_single, issue_slots[25].out_uop.fp_single connect issue_slots[24].in_uop.bits.fp_val, issue_slots[25].out_uop.fp_val connect issue_slots[24].in_uop.bits.frs3_en, issue_slots[25].out_uop.frs3_en connect issue_slots[24].in_uop.bits.lrs2_rtype, issue_slots[25].out_uop.lrs2_rtype connect issue_slots[24].in_uop.bits.lrs1_rtype, issue_slots[25].out_uop.lrs1_rtype connect issue_slots[24].in_uop.bits.dst_rtype, issue_slots[25].out_uop.dst_rtype connect issue_slots[24].in_uop.bits.ldst_val, issue_slots[25].out_uop.ldst_val connect issue_slots[24].in_uop.bits.lrs3, issue_slots[25].out_uop.lrs3 connect issue_slots[24].in_uop.bits.lrs2, issue_slots[25].out_uop.lrs2 connect issue_slots[24].in_uop.bits.lrs1, issue_slots[25].out_uop.lrs1 connect issue_slots[24].in_uop.bits.ldst, issue_slots[25].out_uop.ldst connect issue_slots[24].in_uop.bits.ldst_is_rs1, issue_slots[25].out_uop.ldst_is_rs1 connect issue_slots[24].in_uop.bits.flush_on_commit, issue_slots[25].out_uop.flush_on_commit connect issue_slots[24].in_uop.bits.is_unique, issue_slots[25].out_uop.is_unique connect issue_slots[24].in_uop.bits.is_sys_pc2epc, issue_slots[25].out_uop.is_sys_pc2epc connect issue_slots[24].in_uop.bits.uses_stq, issue_slots[25].out_uop.uses_stq connect issue_slots[24].in_uop.bits.uses_ldq, issue_slots[25].out_uop.uses_ldq connect issue_slots[24].in_uop.bits.is_amo, issue_slots[25].out_uop.is_amo connect issue_slots[24].in_uop.bits.is_fencei, issue_slots[25].out_uop.is_fencei connect issue_slots[24].in_uop.bits.is_fence, issue_slots[25].out_uop.is_fence connect issue_slots[24].in_uop.bits.mem_signed, issue_slots[25].out_uop.mem_signed connect issue_slots[24].in_uop.bits.mem_size, issue_slots[25].out_uop.mem_size connect issue_slots[24].in_uop.bits.mem_cmd, issue_slots[25].out_uop.mem_cmd connect issue_slots[24].in_uop.bits.bypassable, issue_slots[25].out_uop.bypassable connect issue_slots[24].in_uop.bits.exc_cause, issue_slots[25].out_uop.exc_cause connect issue_slots[24].in_uop.bits.exception, issue_slots[25].out_uop.exception connect issue_slots[24].in_uop.bits.stale_pdst, issue_slots[25].out_uop.stale_pdst connect issue_slots[24].in_uop.bits.ppred_busy, issue_slots[25].out_uop.ppred_busy connect issue_slots[24].in_uop.bits.prs3_busy, issue_slots[25].out_uop.prs3_busy connect issue_slots[24].in_uop.bits.prs2_busy, issue_slots[25].out_uop.prs2_busy connect issue_slots[24].in_uop.bits.prs1_busy, issue_slots[25].out_uop.prs1_busy connect issue_slots[24].in_uop.bits.ppred, issue_slots[25].out_uop.ppred connect issue_slots[24].in_uop.bits.prs3, issue_slots[25].out_uop.prs3 connect issue_slots[24].in_uop.bits.prs2, issue_slots[25].out_uop.prs2 connect issue_slots[24].in_uop.bits.prs1, issue_slots[25].out_uop.prs1 connect issue_slots[24].in_uop.bits.pdst, issue_slots[25].out_uop.pdst connect issue_slots[24].in_uop.bits.rxq_idx, issue_slots[25].out_uop.rxq_idx connect issue_slots[24].in_uop.bits.stq_idx, issue_slots[25].out_uop.stq_idx connect issue_slots[24].in_uop.bits.ldq_idx, issue_slots[25].out_uop.ldq_idx connect issue_slots[24].in_uop.bits.rob_idx, issue_slots[25].out_uop.rob_idx connect issue_slots[24].in_uop.bits.csr_addr, issue_slots[25].out_uop.csr_addr connect issue_slots[24].in_uop.bits.imm_packed, issue_slots[25].out_uop.imm_packed connect issue_slots[24].in_uop.bits.taken, issue_slots[25].out_uop.taken connect issue_slots[24].in_uop.bits.pc_lob, issue_slots[25].out_uop.pc_lob connect issue_slots[24].in_uop.bits.edge_inst, issue_slots[25].out_uop.edge_inst connect issue_slots[24].in_uop.bits.ftq_idx, issue_slots[25].out_uop.ftq_idx connect issue_slots[24].in_uop.bits.br_tag, issue_slots[25].out_uop.br_tag connect issue_slots[24].in_uop.bits.br_mask, issue_slots[25].out_uop.br_mask connect issue_slots[24].in_uop.bits.is_sfb, issue_slots[25].out_uop.is_sfb connect issue_slots[24].in_uop.bits.is_jal, issue_slots[25].out_uop.is_jal connect issue_slots[24].in_uop.bits.is_jalr, issue_slots[25].out_uop.is_jalr connect issue_slots[24].in_uop.bits.is_br, issue_slots[25].out_uop.is_br connect issue_slots[24].in_uop.bits.iw_p2_poisoned, issue_slots[25].out_uop.iw_p2_poisoned connect issue_slots[24].in_uop.bits.iw_p1_poisoned, issue_slots[25].out_uop.iw_p1_poisoned connect issue_slots[24].in_uop.bits.iw_state, issue_slots[25].out_uop.iw_state connect issue_slots[24].in_uop.bits.ctrl.is_std, issue_slots[25].out_uop.ctrl.is_std connect issue_slots[24].in_uop.bits.ctrl.is_sta, issue_slots[25].out_uop.ctrl.is_sta connect issue_slots[24].in_uop.bits.ctrl.is_load, issue_slots[25].out_uop.ctrl.is_load connect issue_slots[24].in_uop.bits.ctrl.csr_cmd, issue_slots[25].out_uop.ctrl.csr_cmd connect issue_slots[24].in_uop.bits.ctrl.fcn_dw, issue_slots[25].out_uop.ctrl.fcn_dw connect issue_slots[24].in_uop.bits.ctrl.op_fcn, issue_slots[25].out_uop.ctrl.op_fcn connect issue_slots[24].in_uop.bits.ctrl.imm_sel, issue_slots[25].out_uop.ctrl.imm_sel connect issue_slots[24].in_uop.bits.ctrl.op2_sel, issue_slots[25].out_uop.ctrl.op2_sel connect issue_slots[24].in_uop.bits.ctrl.op1_sel, issue_slots[25].out_uop.ctrl.op1_sel connect issue_slots[24].in_uop.bits.ctrl.br_type, issue_slots[25].out_uop.ctrl.br_type connect issue_slots[24].in_uop.bits.fu_code, issue_slots[25].out_uop.fu_code connect issue_slots[24].in_uop.bits.iq_type, issue_slots[25].out_uop.iq_type connect issue_slots[24].in_uop.bits.debug_pc, issue_slots[25].out_uop.debug_pc connect issue_slots[24].in_uop.bits.is_rvc, issue_slots[25].out_uop.is_rvc connect issue_slots[24].in_uop.bits.debug_inst, issue_slots[25].out_uop.debug_inst connect issue_slots[24].in_uop.bits.inst, issue_slots[25].out_uop.inst connect issue_slots[24].in_uop.bits.uopc, issue_slots[25].out_uop.uopc node _T_332 = eq(_WIRE_28, UInt<1>(0h1)) when _T_332 : connect issue_slots[24].in_uop.valid, issue_slots[25].will_be_valid connect issue_slots[24].in_uop.bits.debug_tsrc, issue_slots[25].out_uop.debug_tsrc connect issue_slots[24].in_uop.bits.debug_fsrc, issue_slots[25].out_uop.debug_fsrc connect issue_slots[24].in_uop.bits.bp_xcpt_if, issue_slots[25].out_uop.bp_xcpt_if connect issue_slots[24].in_uop.bits.bp_debug_if, issue_slots[25].out_uop.bp_debug_if connect issue_slots[24].in_uop.bits.xcpt_ma_if, issue_slots[25].out_uop.xcpt_ma_if connect issue_slots[24].in_uop.bits.xcpt_ae_if, issue_slots[25].out_uop.xcpt_ae_if connect issue_slots[24].in_uop.bits.xcpt_pf_if, issue_slots[25].out_uop.xcpt_pf_if connect issue_slots[24].in_uop.bits.fp_single, issue_slots[25].out_uop.fp_single connect issue_slots[24].in_uop.bits.fp_val, issue_slots[25].out_uop.fp_val connect issue_slots[24].in_uop.bits.frs3_en, issue_slots[25].out_uop.frs3_en connect issue_slots[24].in_uop.bits.lrs2_rtype, issue_slots[25].out_uop.lrs2_rtype connect issue_slots[24].in_uop.bits.lrs1_rtype, issue_slots[25].out_uop.lrs1_rtype connect issue_slots[24].in_uop.bits.dst_rtype, issue_slots[25].out_uop.dst_rtype connect issue_slots[24].in_uop.bits.ldst_val, issue_slots[25].out_uop.ldst_val connect issue_slots[24].in_uop.bits.lrs3, issue_slots[25].out_uop.lrs3 connect issue_slots[24].in_uop.bits.lrs2, issue_slots[25].out_uop.lrs2 connect issue_slots[24].in_uop.bits.lrs1, issue_slots[25].out_uop.lrs1 connect issue_slots[24].in_uop.bits.ldst, issue_slots[25].out_uop.ldst connect issue_slots[24].in_uop.bits.ldst_is_rs1, issue_slots[25].out_uop.ldst_is_rs1 connect issue_slots[24].in_uop.bits.flush_on_commit, issue_slots[25].out_uop.flush_on_commit connect issue_slots[24].in_uop.bits.is_unique, issue_slots[25].out_uop.is_unique connect issue_slots[24].in_uop.bits.is_sys_pc2epc, issue_slots[25].out_uop.is_sys_pc2epc connect issue_slots[24].in_uop.bits.uses_stq, issue_slots[25].out_uop.uses_stq connect issue_slots[24].in_uop.bits.uses_ldq, issue_slots[25].out_uop.uses_ldq connect issue_slots[24].in_uop.bits.is_amo, issue_slots[25].out_uop.is_amo connect issue_slots[24].in_uop.bits.is_fencei, issue_slots[25].out_uop.is_fencei connect issue_slots[24].in_uop.bits.is_fence, issue_slots[25].out_uop.is_fence connect issue_slots[24].in_uop.bits.mem_signed, issue_slots[25].out_uop.mem_signed connect issue_slots[24].in_uop.bits.mem_size, issue_slots[25].out_uop.mem_size connect issue_slots[24].in_uop.bits.mem_cmd, issue_slots[25].out_uop.mem_cmd connect issue_slots[24].in_uop.bits.bypassable, issue_slots[25].out_uop.bypassable connect issue_slots[24].in_uop.bits.exc_cause, issue_slots[25].out_uop.exc_cause connect issue_slots[24].in_uop.bits.exception, issue_slots[25].out_uop.exception connect issue_slots[24].in_uop.bits.stale_pdst, issue_slots[25].out_uop.stale_pdst connect issue_slots[24].in_uop.bits.ppred_busy, issue_slots[25].out_uop.ppred_busy connect issue_slots[24].in_uop.bits.prs3_busy, issue_slots[25].out_uop.prs3_busy connect issue_slots[24].in_uop.bits.prs2_busy, issue_slots[25].out_uop.prs2_busy connect issue_slots[24].in_uop.bits.prs1_busy, issue_slots[25].out_uop.prs1_busy connect issue_slots[24].in_uop.bits.ppred, issue_slots[25].out_uop.ppred connect issue_slots[24].in_uop.bits.prs3, issue_slots[25].out_uop.prs3 connect issue_slots[24].in_uop.bits.prs2, issue_slots[25].out_uop.prs2 connect issue_slots[24].in_uop.bits.prs1, issue_slots[25].out_uop.prs1 connect issue_slots[24].in_uop.bits.pdst, issue_slots[25].out_uop.pdst connect issue_slots[24].in_uop.bits.rxq_idx, issue_slots[25].out_uop.rxq_idx connect issue_slots[24].in_uop.bits.stq_idx, issue_slots[25].out_uop.stq_idx connect issue_slots[24].in_uop.bits.ldq_idx, issue_slots[25].out_uop.ldq_idx connect issue_slots[24].in_uop.bits.rob_idx, issue_slots[25].out_uop.rob_idx connect issue_slots[24].in_uop.bits.csr_addr, issue_slots[25].out_uop.csr_addr connect issue_slots[24].in_uop.bits.imm_packed, issue_slots[25].out_uop.imm_packed connect issue_slots[24].in_uop.bits.taken, issue_slots[25].out_uop.taken connect issue_slots[24].in_uop.bits.pc_lob, issue_slots[25].out_uop.pc_lob connect issue_slots[24].in_uop.bits.edge_inst, issue_slots[25].out_uop.edge_inst connect issue_slots[24].in_uop.bits.ftq_idx, issue_slots[25].out_uop.ftq_idx connect issue_slots[24].in_uop.bits.br_tag, issue_slots[25].out_uop.br_tag connect issue_slots[24].in_uop.bits.br_mask, issue_slots[25].out_uop.br_mask connect issue_slots[24].in_uop.bits.is_sfb, issue_slots[25].out_uop.is_sfb connect issue_slots[24].in_uop.bits.is_jal, issue_slots[25].out_uop.is_jal connect issue_slots[24].in_uop.bits.is_jalr, issue_slots[25].out_uop.is_jalr connect issue_slots[24].in_uop.bits.is_br, issue_slots[25].out_uop.is_br connect issue_slots[24].in_uop.bits.iw_p2_poisoned, issue_slots[25].out_uop.iw_p2_poisoned connect issue_slots[24].in_uop.bits.iw_p1_poisoned, issue_slots[25].out_uop.iw_p1_poisoned connect issue_slots[24].in_uop.bits.iw_state, issue_slots[25].out_uop.iw_state connect issue_slots[24].in_uop.bits.ctrl.is_std, issue_slots[25].out_uop.ctrl.is_std connect issue_slots[24].in_uop.bits.ctrl.is_sta, issue_slots[25].out_uop.ctrl.is_sta connect issue_slots[24].in_uop.bits.ctrl.is_load, issue_slots[25].out_uop.ctrl.is_load connect issue_slots[24].in_uop.bits.ctrl.csr_cmd, issue_slots[25].out_uop.ctrl.csr_cmd connect issue_slots[24].in_uop.bits.ctrl.fcn_dw, issue_slots[25].out_uop.ctrl.fcn_dw connect issue_slots[24].in_uop.bits.ctrl.op_fcn, issue_slots[25].out_uop.ctrl.op_fcn connect issue_slots[24].in_uop.bits.ctrl.imm_sel, issue_slots[25].out_uop.ctrl.imm_sel connect issue_slots[24].in_uop.bits.ctrl.op2_sel, issue_slots[25].out_uop.ctrl.op2_sel connect issue_slots[24].in_uop.bits.ctrl.op1_sel, issue_slots[25].out_uop.ctrl.op1_sel connect issue_slots[24].in_uop.bits.ctrl.br_type, issue_slots[25].out_uop.ctrl.br_type connect issue_slots[24].in_uop.bits.fu_code, issue_slots[25].out_uop.fu_code connect issue_slots[24].in_uop.bits.iq_type, issue_slots[25].out_uop.iq_type connect issue_slots[24].in_uop.bits.debug_pc, issue_slots[25].out_uop.debug_pc connect issue_slots[24].in_uop.bits.is_rvc, issue_slots[25].out_uop.is_rvc connect issue_slots[24].in_uop.bits.debug_inst, issue_slots[25].out_uop.debug_inst connect issue_slots[24].in_uop.bits.inst, issue_slots[25].out_uop.inst connect issue_slots[24].in_uop.bits.uopc, issue_slots[25].out_uop.uopc node _T_333 = eq(_WIRE_29, UInt<2>(0h2)) when _T_333 : connect issue_slots[24].in_uop.valid, issue_slots[26].will_be_valid connect issue_slots[24].in_uop.bits.debug_tsrc, issue_slots[26].out_uop.debug_tsrc connect issue_slots[24].in_uop.bits.debug_fsrc, issue_slots[26].out_uop.debug_fsrc connect issue_slots[24].in_uop.bits.bp_xcpt_if, issue_slots[26].out_uop.bp_xcpt_if connect issue_slots[24].in_uop.bits.bp_debug_if, issue_slots[26].out_uop.bp_debug_if connect issue_slots[24].in_uop.bits.xcpt_ma_if, issue_slots[26].out_uop.xcpt_ma_if connect issue_slots[24].in_uop.bits.xcpt_ae_if, issue_slots[26].out_uop.xcpt_ae_if connect issue_slots[24].in_uop.bits.xcpt_pf_if, issue_slots[26].out_uop.xcpt_pf_if connect issue_slots[24].in_uop.bits.fp_single, issue_slots[26].out_uop.fp_single connect issue_slots[24].in_uop.bits.fp_val, issue_slots[26].out_uop.fp_val connect issue_slots[24].in_uop.bits.frs3_en, issue_slots[26].out_uop.frs3_en connect issue_slots[24].in_uop.bits.lrs2_rtype, issue_slots[26].out_uop.lrs2_rtype connect issue_slots[24].in_uop.bits.lrs1_rtype, issue_slots[26].out_uop.lrs1_rtype connect issue_slots[24].in_uop.bits.dst_rtype, issue_slots[26].out_uop.dst_rtype connect issue_slots[24].in_uop.bits.ldst_val, issue_slots[26].out_uop.ldst_val connect issue_slots[24].in_uop.bits.lrs3, issue_slots[26].out_uop.lrs3 connect issue_slots[24].in_uop.bits.lrs2, issue_slots[26].out_uop.lrs2 connect issue_slots[24].in_uop.bits.lrs1, issue_slots[26].out_uop.lrs1 connect issue_slots[24].in_uop.bits.ldst, issue_slots[26].out_uop.ldst connect issue_slots[24].in_uop.bits.ldst_is_rs1, issue_slots[26].out_uop.ldst_is_rs1 connect issue_slots[24].in_uop.bits.flush_on_commit, issue_slots[26].out_uop.flush_on_commit connect issue_slots[24].in_uop.bits.is_unique, issue_slots[26].out_uop.is_unique connect issue_slots[24].in_uop.bits.is_sys_pc2epc, issue_slots[26].out_uop.is_sys_pc2epc connect issue_slots[24].in_uop.bits.uses_stq, issue_slots[26].out_uop.uses_stq connect issue_slots[24].in_uop.bits.uses_ldq, issue_slots[26].out_uop.uses_ldq connect issue_slots[24].in_uop.bits.is_amo, issue_slots[26].out_uop.is_amo connect issue_slots[24].in_uop.bits.is_fencei, issue_slots[26].out_uop.is_fencei connect issue_slots[24].in_uop.bits.is_fence, issue_slots[26].out_uop.is_fence connect issue_slots[24].in_uop.bits.mem_signed, issue_slots[26].out_uop.mem_signed connect issue_slots[24].in_uop.bits.mem_size, issue_slots[26].out_uop.mem_size connect issue_slots[24].in_uop.bits.mem_cmd, issue_slots[26].out_uop.mem_cmd connect issue_slots[24].in_uop.bits.bypassable, issue_slots[26].out_uop.bypassable connect issue_slots[24].in_uop.bits.exc_cause, issue_slots[26].out_uop.exc_cause connect issue_slots[24].in_uop.bits.exception, issue_slots[26].out_uop.exception connect issue_slots[24].in_uop.bits.stale_pdst, issue_slots[26].out_uop.stale_pdst connect issue_slots[24].in_uop.bits.ppred_busy, issue_slots[26].out_uop.ppred_busy connect issue_slots[24].in_uop.bits.prs3_busy, issue_slots[26].out_uop.prs3_busy connect issue_slots[24].in_uop.bits.prs2_busy, issue_slots[26].out_uop.prs2_busy connect issue_slots[24].in_uop.bits.prs1_busy, issue_slots[26].out_uop.prs1_busy connect issue_slots[24].in_uop.bits.ppred, issue_slots[26].out_uop.ppred connect issue_slots[24].in_uop.bits.prs3, issue_slots[26].out_uop.prs3 connect issue_slots[24].in_uop.bits.prs2, issue_slots[26].out_uop.prs2 connect issue_slots[24].in_uop.bits.prs1, issue_slots[26].out_uop.prs1 connect issue_slots[24].in_uop.bits.pdst, issue_slots[26].out_uop.pdst connect issue_slots[24].in_uop.bits.rxq_idx, issue_slots[26].out_uop.rxq_idx connect issue_slots[24].in_uop.bits.stq_idx, issue_slots[26].out_uop.stq_idx connect issue_slots[24].in_uop.bits.ldq_idx, issue_slots[26].out_uop.ldq_idx connect issue_slots[24].in_uop.bits.rob_idx, issue_slots[26].out_uop.rob_idx connect issue_slots[24].in_uop.bits.csr_addr, issue_slots[26].out_uop.csr_addr connect issue_slots[24].in_uop.bits.imm_packed, issue_slots[26].out_uop.imm_packed connect issue_slots[24].in_uop.bits.taken, issue_slots[26].out_uop.taken connect issue_slots[24].in_uop.bits.pc_lob, issue_slots[26].out_uop.pc_lob connect issue_slots[24].in_uop.bits.edge_inst, issue_slots[26].out_uop.edge_inst connect issue_slots[24].in_uop.bits.ftq_idx, issue_slots[26].out_uop.ftq_idx connect issue_slots[24].in_uop.bits.br_tag, issue_slots[26].out_uop.br_tag connect issue_slots[24].in_uop.bits.br_mask, issue_slots[26].out_uop.br_mask connect issue_slots[24].in_uop.bits.is_sfb, issue_slots[26].out_uop.is_sfb connect issue_slots[24].in_uop.bits.is_jal, issue_slots[26].out_uop.is_jal connect issue_slots[24].in_uop.bits.is_jalr, issue_slots[26].out_uop.is_jalr connect issue_slots[24].in_uop.bits.is_br, issue_slots[26].out_uop.is_br connect issue_slots[24].in_uop.bits.iw_p2_poisoned, issue_slots[26].out_uop.iw_p2_poisoned connect issue_slots[24].in_uop.bits.iw_p1_poisoned, issue_slots[26].out_uop.iw_p1_poisoned connect issue_slots[24].in_uop.bits.iw_state, issue_slots[26].out_uop.iw_state connect issue_slots[24].in_uop.bits.ctrl.is_std, issue_slots[26].out_uop.ctrl.is_std connect issue_slots[24].in_uop.bits.ctrl.is_sta, issue_slots[26].out_uop.ctrl.is_sta connect issue_slots[24].in_uop.bits.ctrl.is_load, issue_slots[26].out_uop.ctrl.is_load connect issue_slots[24].in_uop.bits.ctrl.csr_cmd, issue_slots[26].out_uop.ctrl.csr_cmd connect issue_slots[24].in_uop.bits.ctrl.fcn_dw, issue_slots[26].out_uop.ctrl.fcn_dw connect issue_slots[24].in_uop.bits.ctrl.op_fcn, issue_slots[26].out_uop.ctrl.op_fcn connect issue_slots[24].in_uop.bits.ctrl.imm_sel, issue_slots[26].out_uop.ctrl.imm_sel connect issue_slots[24].in_uop.bits.ctrl.op2_sel, issue_slots[26].out_uop.ctrl.op2_sel connect issue_slots[24].in_uop.bits.ctrl.op1_sel, issue_slots[26].out_uop.ctrl.op1_sel connect issue_slots[24].in_uop.bits.ctrl.br_type, issue_slots[26].out_uop.ctrl.br_type connect issue_slots[24].in_uop.bits.fu_code, issue_slots[26].out_uop.fu_code connect issue_slots[24].in_uop.bits.iq_type, issue_slots[26].out_uop.iq_type connect issue_slots[24].in_uop.bits.debug_pc, issue_slots[26].out_uop.debug_pc connect issue_slots[24].in_uop.bits.is_rvc, issue_slots[26].out_uop.is_rvc connect issue_slots[24].in_uop.bits.debug_inst, issue_slots[26].out_uop.debug_inst connect issue_slots[24].in_uop.bits.inst, issue_slots[26].out_uop.inst connect issue_slots[24].in_uop.bits.uopc, issue_slots[26].out_uop.uopc node _T_334 = eq(_WIRE_30, UInt<3>(0h4)) when _T_334 : connect issue_slots[24].in_uop.valid, issue_slots[27].will_be_valid connect issue_slots[24].in_uop.bits.debug_tsrc, issue_slots[27].out_uop.debug_tsrc connect issue_slots[24].in_uop.bits.debug_fsrc, issue_slots[27].out_uop.debug_fsrc connect issue_slots[24].in_uop.bits.bp_xcpt_if, issue_slots[27].out_uop.bp_xcpt_if connect issue_slots[24].in_uop.bits.bp_debug_if, issue_slots[27].out_uop.bp_debug_if connect issue_slots[24].in_uop.bits.xcpt_ma_if, issue_slots[27].out_uop.xcpt_ma_if connect issue_slots[24].in_uop.bits.xcpt_ae_if, issue_slots[27].out_uop.xcpt_ae_if connect issue_slots[24].in_uop.bits.xcpt_pf_if, issue_slots[27].out_uop.xcpt_pf_if connect issue_slots[24].in_uop.bits.fp_single, issue_slots[27].out_uop.fp_single connect issue_slots[24].in_uop.bits.fp_val, issue_slots[27].out_uop.fp_val connect issue_slots[24].in_uop.bits.frs3_en, issue_slots[27].out_uop.frs3_en connect issue_slots[24].in_uop.bits.lrs2_rtype, issue_slots[27].out_uop.lrs2_rtype connect issue_slots[24].in_uop.bits.lrs1_rtype, issue_slots[27].out_uop.lrs1_rtype connect issue_slots[24].in_uop.bits.dst_rtype, issue_slots[27].out_uop.dst_rtype connect issue_slots[24].in_uop.bits.ldst_val, issue_slots[27].out_uop.ldst_val connect issue_slots[24].in_uop.bits.lrs3, issue_slots[27].out_uop.lrs3 connect issue_slots[24].in_uop.bits.lrs2, issue_slots[27].out_uop.lrs2 connect issue_slots[24].in_uop.bits.lrs1, issue_slots[27].out_uop.lrs1 connect issue_slots[24].in_uop.bits.ldst, issue_slots[27].out_uop.ldst connect issue_slots[24].in_uop.bits.ldst_is_rs1, issue_slots[27].out_uop.ldst_is_rs1 connect issue_slots[24].in_uop.bits.flush_on_commit, issue_slots[27].out_uop.flush_on_commit connect issue_slots[24].in_uop.bits.is_unique, issue_slots[27].out_uop.is_unique connect issue_slots[24].in_uop.bits.is_sys_pc2epc, issue_slots[27].out_uop.is_sys_pc2epc connect issue_slots[24].in_uop.bits.uses_stq, issue_slots[27].out_uop.uses_stq connect issue_slots[24].in_uop.bits.uses_ldq, issue_slots[27].out_uop.uses_ldq connect issue_slots[24].in_uop.bits.is_amo, issue_slots[27].out_uop.is_amo connect issue_slots[24].in_uop.bits.is_fencei, issue_slots[27].out_uop.is_fencei connect issue_slots[24].in_uop.bits.is_fence, issue_slots[27].out_uop.is_fence connect issue_slots[24].in_uop.bits.mem_signed, issue_slots[27].out_uop.mem_signed connect issue_slots[24].in_uop.bits.mem_size, issue_slots[27].out_uop.mem_size connect issue_slots[24].in_uop.bits.mem_cmd, issue_slots[27].out_uop.mem_cmd connect issue_slots[24].in_uop.bits.bypassable, issue_slots[27].out_uop.bypassable connect issue_slots[24].in_uop.bits.exc_cause, issue_slots[27].out_uop.exc_cause connect issue_slots[24].in_uop.bits.exception, issue_slots[27].out_uop.exception connect issue_slots[24].in_uop.bits.stale_pdst, issue_slots[27].out_uop.stale_pdst connect issue_slots[24].in_uop.bits.ppred_busy, issue_slots[27].out_uop.ppred_busy connect issue_slots[24].in_uop.bits.prs3_busy, issue_slots[27].out_uop.prs3_busy connect issue_slots[24].in_uop.bits.prs2_busy, issue_slots[27].out_uop.prs2_busy connect issue_slots[24].in_uop.bits.prs1_busy, issue_slots[27].out_uop.prs1_busy connect issue_slots[24].in_uop.bits.ppred, issue_slots[27].out_uop.ppred connect issue_slots[24].in_uop.bits.prs3, issue_slots[27].out_uop.prs3 connect issue_slots[24].in_uop.bits.prs2, issue_slots[27].out_uop.prs2 connect issue_slots[24].in_uop.bits.prs1, issue_slots[27].out_uop.prs1 connect issue_slots[24].in_uop.bits.pdst, issue_slots[27].out_uop.pdst connect issue_slots[24].in_uop.bits.rxq_idx, issue_slots[27].out_uop.rxq_idx connect issue_slots[24].in_uop.bits.stq_idx, issue_slots[27].out_uop.stq_idx connect issue_slots[24].in_uop.bits.ldq_idx, issue_slots[27].out_uop.ldq_idx connect issue_slots[24].in_uop.bits.rob_idx, issue_slots[27].out_uop.rob_idx connect issue_slots[24].in_uop.bits.csr_addr, issue_slots[27].out_uop.csr_addr connect issue_slots[24].in_uop.bits.imm_packed, issue_slots[27].out_uop.imm_packed connect issue_slots[24].in_uop.bits.taken, issue_slots[27].out_uop.taken connect issue_slots[24].in_uop.bits.pc_lob, issue_slots[27].out_uop.pc_lob connect issue_slots[24].in_uop.bits.edge_inst, issue_slots[27].out_uop.edge_inst connect issue_slots[24].in_uop.bits.ftq_idx, issue_slots[27].out_uop.ftq_idx connect issue_slots[24].in_uop.bits.br_tag, issue_slots[27].out_uop.br_tag connect issue_slots[24].in_uop.bits.br_mask, issue_slots[27].out_uop.br_mask connect issue_slots[24].in_uop.bits.is_sfb, issue_slots[27].out_uop.is_sfb connect issue_slots[24].in_uop.bits.is_jal, issue_slots[27].out_uop.is_jal connect issue_slots[24].in_uop.bits.is_jalr, issue_slots[27].out_uop.is_jalr connect issue_slots[24].in_uop.bits.is_br, issue_slots[27].out_uop.is_br connect issue_slots[24].in_uop.bits.iw_p2_poisoned, issue_slots[27].out_uop.iw_p2_poisoned connect issue_slots[24].in_uop.bits.iw_p1_poisoned, issue_slots[27].out_uop.iw_p1_poisoned connect issue_slots[24].in_uop.bits.iw_state, issue_slots[27].out_uop.iw_state connect issue_slots[24].in_uop.bits.ctrl.is_std, issue_slots[27].out_uop.ctrl.is_std connect issue_slots[24].in_uop.bits.ctrl.is_sta, issue_slots[27].out_uop.ctrl.is_sta connect issue_slots[24].in_uop.bits.ctrl.is_load, issue_slots[27].out_uop.ctrl.is_load connect issue_slots[24].in_uop.bits.ctrl.csr_cmd, issue_slots[27].out_uop.ctrl.csr_cmd connect issue_slots[24].in_uop.bits.ctrl.fcn_dw, issue_slots[27].out_uop.ctrl.fcn_dw connect issue_slots[24].in_uop.bits.ctrl.op_fcn, issue_slots[27].out_uop.ctrl.op_fcn connect issue_slots[24].in_uop.bits.ctrl.imm_sel, issue_slots[27].out_uop.ctrl.imm_sel connect issue_slots[24].in_uop.bits.ctrl.op2_sel, issue_slots[27].out_uop.ctrl.op2_sel connect issue_slots[24].in_uop.bits.ctrl.op1_sel, issue_slots[27].out_uop.ctrl.op1_sel connect issue_slots[24].in_uop.bits.ctrl.br_type, issue_slots[27].out_uop.ctrl.br_type connect issue_slots[24].in_uop.bits.fu_code, issue_slots[27].out_uop.fu_code connect issue_slots[24].in_uop.bits.iq_type, issue_slots[27].out_uop.iq_type connect issue_slots[24].in_uop.bits.debug_pc, issue_slots[27].out_uop.debug_pc connect issue_slots[24].in_uop.bits.is_rvc, issue_slots[27].out_uop.is_rvc connect issue_slots[24].in_uop.bits.debug_inst, issue_slots[27].out_uop.debug_inst connect issue_slots[24].in_uop.bits.inst, issue_slots[27].out_uop.inst connect issue_slots[24].in_uop.bits.uopc, issue_slots[27].out_uop.uopc node _issue_slots_24_clear_T = neq(_WIRE_27, UInt<1>(0h0)) connect issue_slots[24].clear, _issue_slots_24_clear_T connect issue_slots[25].in_uop.valid, UInt<1>(0h0) connect issue_slots[25].in_uop.bits.debug_tsrc, issue_slots[26].out_uop.debug_tsrc connect issue_slots[25].in_uop.bits.debug_fsrc, issue_slots[26].out_uop.debug_fsrc connect issue_slots[25].in_uop.bits.bp_xcpt_if, issue_slots[26].out_uop.bp_xcpt_if connect issue_slots[25].in_uop.bits.bp_debug_if, issue_slots[26].out_uop.bp_debug_if connect issue_slots[25].in_uop.bits.xcpt_ma_if, issue_slots[26].out_uop.xcpt_ma_if connect issue_slots[25].in_uop.bits.xcpt_ae_if, issue_slots[26].out_uop.xcpt_ae_if connect issue_slots[25].in_uop.bits.xcpt_pf_if, issue_slots[26].out_uop.xcpt_pf_if connect issue_slots[25].in_uop.bits.fp_single, issue_slots[26].out_uop.fp_single connect issue_slots[25].in_uop.bits.fp_val, issue_slots[26].out_uop.fp_val connect issue_slots[25].in_uop.bits.frs3_en, issue_slots[26].out_uop.frs3_en connect issue_slots[25].in_uop.bits.lrs2_rtype, issue_slots[26].out_uop.lrs2_rtype connect issue_slots[25].in_uop.bits.lrs1_rtype, issue_slots[26].out_uop.lrs1_rtype connect issue_slots[25].in_uop.bits.dst_rtype, issue_slots[26].out_uop.dst_rtype connect issue_slots[25].in_uop.bits.ldst_val, issue_slots[26].out_uop.ldst_val connect issue_slots[25].in_uop.bits.lrs3, issue_slots[26].out_uop.lrs3 connect issue_slots[25].in_uop.bits.lrs2, issue_slots[26].out_uop.lrs2 connect issue_slots[25].in_uop.bits.lrs1, issue_slots[26].out_uop.lrs1 connect issue_slots[25].in_uop.bits.ldst, issue_slots[26].out_uop.ldst connect issue_slots[25].in_uop.bits.ldst_is_rs1, issue_slots[26].out_uop.ldst_is_rs1 connect issue_slots[25].in_uop.bits.flush_on_commit, issue_slots[26].out_uop.flush_on_commit connect issue_slots[25].in_uop.bits.is_unique, issue_slots[26].out_uop.is_unique connect issue_slots[25].in_uop.bits.is_sys_pc2epc, issue_slots[26].out_uop.is_sys_pc2epc connect issue_slots[25].in_uop.bits.uses_stq, issue_slots[26].out_uop.uses_stq connect issue_slots[25].in_uop.bits.uses_ldq, issue_slots[26].out_uop.uses_ldq connect issue_slots[25].in_uop.bits.is_amo, issue_slots[26].out_uop.is_amo connect issue_slots[25].in_uop.bits.is_fencei, issue_slots[26].out_uop.is_fencei connect issue_slots[25].in_uop.bits.is_fence, issue_slots[26].out_uop.is_fence connect issue_slots[25].in_uop.bits.mem_signed, issue_slots[26].out_uop.mem_signed connect issue_slots[25].in_uop.bits.mem_size, issue_slots[26].out_uop.mem_size connect issue_slots[25].in_uop.bits.mem_cmd, issue_slots[26].out_uop.mem_cmd connect issue_slots[25].in_uop.bits.bypassable, issue_slots[26].out_uop.bypassable connect issue_slots[25].in_uop.bits.exc_cause, issue_slots[26].out_uop.exc_cause connect issue_slots[25].in_uop.bits.exception, issue_slots[26].out_uop.exception connect issue_slots[25].in_uop.bits.stale_pdst, issue_slots[26].out_uop.stale_pdst connect issue_slots[25].in_uop.bits.ppred_busy, issue_slots[26].out_uop.ppred_busy connect issue_slots[25].in_uop.bits.prs3_busy, issue_slots[26].out_uop.prs3_busy connect issue_slots[25].in_uop.bits.prs2_busy, issue_slots[26].out_uop.prs2_busy connect issue_slots[25].in_uop.bits.prs1_busy, issue_slots[26].out_uop.prs1_busy connect issue_slots[25].in_uop.bits.ppred, issue_slots[26].out_uop.ppred connect issue_slots[25].in_uop.bits.prs3, issue_slots[26].out_uop.prs3 connect issue_slots[25].in_uop.bits.prs2, issue_slots[26].out_uop.prs2 connect issue_slots[25].in_uop.bits.prs1, issue_slots[26].out_uop.prs1 connect issue_slots[25].in_uop.bits.pdst, issue_slots[26].out_uop.pdst connect issue_slots[25].in_uop.bits.rxq_idx, issue_slots[26].out_uop.rxq_idx connect issue_slots[25].in_uop.bits.stq_idx, issue_slots[26].out_uop.stq_idx connect issue_slots[25].in_uop.bits.ldq_idx, issue_slots[26].out_uop.ldq_idx connect issue_slots[25].in_uop.bits.rob_idx, issue_slots[26].out_uop.rob_idx connect issue_slots[25].in_uop.bits.csr_addr, issue_slots[26].out_uop.csr_addr connect issue_slots[25].in_uop.bits.imm_packed, issue_slots[26].out_uop.imm_packed connect issue_slots[25].in_uop.bits.taken, issue_slots[26].out_uop.taken connect issue_slots[25].in_uop.bits.pc_lob, issue_slots[26].out_uop.pc_lob connect issue_slots[25].in_uop.bits.edge_inst, issue_slots[26].out_uop.edge_inst connect issue_slots[25].in_uop.bits.ftq_idx, issue_slots[26].out_uop.ftq_idx connect issue_slots[25].in_uop.bits.br_tag, issue_slots[26].out_uop.br_tag connect issue_slots[25].in_uop.bits.br_mask, issue_slots[26].out_uop.br_mask connect issue_slots[25].in_uop.bits.is_sfb, issue_slots[26].out_uop.is_sfb connect issue_slots[25].in_uop.bits.is_jal, issue_slots[26].out_uop.is_jal connect issue_slots[25].in_uop.bits.is_jalr, issue_slots[26].out_uop.is_jalr connect issue_slots[25].in_uop.bits.is_br, issue_slots[26].out_uop.is_br connect issue_slots[25].in_uop.bits.iw_p2_poisoned, issue_slots[26].out_uop.iw_p2_poisoned connect issue_slots[25].in_uop.bits.iw_p1_poisoned, issue_slots[26].out_uop.iw_p1_poisoned connect issue_slots[25].in_uop.bits.iw_state, issue_slots[26].out_uop.iw_state connect issue_slots[25].in_uop.bits.ctrl.is_std, issue_slots[26].out_uop.ctrl.is_std connect issue_slots[25].in_uop.bits.ctrl.is_sta, issue_slots[26].out_uop.ctrl.is_sta connect issue_slots[25].in_uop.bits.ctrl.is_load, issue_slots[26].out_uop.ctrl.is_load connect issue_slots[25].in_uop.bits.ctrl.csr_cmd, issue_slots[26].out_uop.ctrl.csr_cmd connect issue_slots[25].in_uop.bits.ctrl.fcn_dw, issue_slots[26].out_uop.ctrl.fcn_dw connect issue_slots[25].in_uop.bits.ctrl.op_fcn, issue_slots[26].out_uop.ctrl.op_fcn connect issue_slots[25].in_uop.bits.ctrl.imm_sel, issue_slots[26].out_uop.ctrl.imm_sel connect issue_slots[25].in_uop.bits.ctrl.op2_sel, issue_slots[26].out_uop.ctrl.op2_sel connect issue_slots[25].in_uop.bits.ctrl.op1_sel, issue_slots[26].out_uop.ctrl.op1_sel connect issue_slots[25].in_uop.bits.ctrl.br_type, issue_slots[26].out_uop.ctrl.br_type connect issue_slots[25].in_uop.bits.fu_code, issue_slots[26].out_uop.fu_code connect issue_slots[25].in_uop.bits.iq_type, issue_slots[26].out_uop.iq_type connect issue_slots[25].in_uop.bits.debug_pc, issue_slots[26].out_uop.debug_pc connect issue_slots[25].in_uop.bits.is_rvc, issue_slots[26].out_uop.is_rvc connect issue_slots[25].in_uop.bits.debug_inst, issue_slots[26].out_uop.debug_inst connect issue_slots[25].in_uop.bits.inst, issue_slots[26].out_uop.inst connect issue_slots[25].in_uop.bits.uopc, issue_slots[26].out_uop.uopc node _T_335 = eq(_WIRE_29, UInt<1>(0h1)) when _T_335 : connect issue_slots[25].in_uop.valid, issue_slots[26].will_be_valid connect issue_slots[25].in_uop.bits.debug_tsrc, issue_slots[26].out_uop.debug_tsrc connect issue_slots[25].in_uop.bits.debug_fsrc, issue_slots[26].out_uop.debug_fsrc connect issue_slots[25].in_uop.bits.bp_xcpt_if, issue_slots[26].out_uop.bp_xcpt_if connect issue_slots[25].in_uop.bits.bp_debug_if, issue_slots[26].out_uop.bp_debug_if connect issue_slots[25].in_uop.bits.xcpt_ma_if, issue_slots[26].out_uop.xcpt_ma_if connect issue_slots[25].in_uop.bits.xcpt_ae_if, issue_slots[26].out_uop.xcpt_ae_if connect issue_slots[25].in_uop.bits.xcpt_pf_if, issue_slots[26].out_uop.xcpt_pf_if connect issue_slots[25].in_uop.bits.fp_single, issue_slots[26].out_uop.fp_single connect issue_slots[25].in_uop.bits.fp_val, issue_slots[26].out_uop.fp_val connect issue_slots[25].in_uop.bits.frs3_en, issue_slots[26].out_uop.frs3_en connect issue_slots[25].in_uop.bits.lrs2_rtype, issue_slots[26].out_uop.lrs2_rtype connect issue_slots[25].in_uop.bits.lrs1_rtype, issue_slots[26].out_uop.lrs1_rtype connect issue_slots[25].in_uop.bits.dst_rtype, issue_slots[26].out_uop.dst_rtype connect issue_slots[25].in_uop.bits.ldst_val, issue_slots[26].out_uop.ldst_val connect issue_slots[25].in_uop.bits.lrs3, issue_slots[26].out_uop.lrs3 connect issue_slots[25].in_uop.bits.lrs2, issue_slots[26].out_uop.lrs2 connect issue_slots[25].in_uop.bits.lrs1, issue_slots[26].out_uop.lrs1 connect issue_slots[25].in_uop.bits.ldst, issue_slots[26].out_uop.ldst connect issue_slots[25].in_uop.bits.ldst_is_rs1, issue_slots[26].out_uop.ldst_is_rs1 connect issue_slots[25].in_uop.bits.flush_on_commit, issue_slots[26].out_uop.flush_on_commit connect issue_slots[25].in_uop.bits.is_unique, issue_slots[26].out_uop.is_unique connect issue_slots[25].in_uop.bits.is_sys_pc2epc, issue_slots[26].out_uop.is_sys_pc2epc connect issue_slots[25].in_uop.bits.uses_stq, issue_slots[26].out_uop.uses_stq connect issue_slots[25].in_uop.bits.uses_ldq, issue_slots[26].out_uop.uses_ldq connect issue_slots[25].in_uop.bits.is_amo, issue_slots[26].out_uop.is_amo connect issue_slots[25].in_uop.bits.is_fencei, issue_slots[26].out_uop.is_fencei connect issue_slots[25].in_uop.bits.is_fence, issue_slots[26].out_uop.is_fence connect issue_slots[25].in_uop.bits.mem_signed, issue_slots[26].out_uop.mem_signed connect issue_slots[25].in_uop.bits.mem_size, issue_slots[26].out_uop.mem_size connect issue_slots[25].in_uop.bits.mem_cmd, issue_slots[26].out_uop.mem_cmd connect issue_slots[25].in_uop.bits.bypassable, issue_slots[26].out_uop.bypassable connect issue_slots[25].in_uop.bits.exc_cause, issue_slots[26].out_uop.exc_cause connect issue_slots[25].in_uop.bits.exception, issue_slots[26].out_uop.exception connect issue_slots[25].in_uop.bits.stale_pdst, issue_slots[26].out_uop.stale_pdst connect issue_slots[25].in_uop.bits.ppred_busy, issue_slots[26].out_uop.ppred_busy connect issue_slots[25].in_uop.bits.prs3_busy, issue_slots[26].out_uop.prs3_busy connect issue_slots[25].in_uop.bits.prs2_busy, issue_slots[26].out_uop.prs2_busy connect issue_slots[25].in_uop.bits.prs1_busy, issue_slots[26].out_uop.prs1_busy connect issue_slots[25].in_uop.bits.ppred, issue_slots[26].out_uop.ppred connect issue_slots[25].in_uop.bits.prs3, issue_slots[26].out_uop.prs3 connect issue_slots[25].in_uop.bits.prs2, issue_slots[26].out_uop.prs2 connect issue_slots[25].in_uop.bits.prs1, issue_slots[26].out_uop.prs1 connect issue_slots[25].in_uop.bits.pdst, issue_slots[26].out_uop.pdst connect issue_slots[25].in_uop.bits.rxq_idx, issue_slots[26].out_uop.rxq_idx connect issue_slots[25].in_uop.bits.stq_idx, issue_slots[26].out_uop.stq_idx connect issue_slots[25].in_uop.bits.ldq_idx, issue_slots[26].out_uop.ldq_idx connect issue_slots[25].in_uop.bits.rob_idx, issue_slots[26].out_uop.rob_idx connect issue_slots[25].in_uop.bits.csr_addr, issue_slots[26].out_uop.csr_addr connect issue_slots[25].in_uop.bits.imm_packed, issue_slots[26].out_uop.imm_packed connect issue_slots[25].in_uop.bits.taken, issue_slots[26].out_uop.taken connect issue_slots[25].in_uop.bits.pc_lob, issue_slots[26].out_uop.pc_lob connect issue_slots[25].in_uop.bits.edge_inst, issue_slots[26].out_uop.edge_inst connect issue_slots[25].in_uop.bits.ftq_idx, issue_slots[26].out_uop.ftq_idx connect issue_slots[25].in_uop.bits.br_tag, issue_slots[26].out_uop.br_tag connect issue_slots[25].in_uop.bits.br_mask, issue_slots[26].out_uop.br_mask connect issue_slots[25].in_uop.bits.is_sfb, issue_slots[26].out_uop.is_sfb connect issue_slots[25].in_uop.bits.is_jal, issue_slots[26].out_uop.is_jal connect issue_slots[25].in_uop.bits.is_jalr, issue_slots[26].out_uop.is_jalr connect issue_slots[25].in_uop.bits.is_br, issue_slots[26].out_uop.is_br connect issue_slots[25].in_uop.bits.iw_p2_poisoned, issue_slots[26].out_uop.iw_p2_poisoned connect issue_slots[25].in_uop.bits.iw_p1_poisoned, issue_slots[26].out_uop.iw_p1_poisoned connect issue_slots[25].in_uop.bits.iw_state, issue_slots[26].out_uop.iw_state connect issue_slots[25].in_uop.bits.ctrl.is_std, issue_slots[26].out_uop.ctrl.is_std connect issue_slots[25].in_uop.bits.ctrl.is_sta, issue_slots[26].out_uop.ctrl.is_sta connect issue_slots[25].in_uop.bits.ctrl.is_load, issue_slots[26].out_uop.ctrl.is_load connect issue_slots[25].in_uop.bits.ctrl.csr_cmd, issue_slots[26].out_uop.ctrl.csr_cmd connect issue_slots[25].in_uop.bits.ctrl.fcn_dw, issue_slots[26].out_uop.ctrl.fcn_dw connect issue_slots[25].in_uop.bits.ctrl.op_fcn, issue_slots[26].out_uop.ctrl.op_fcn connect issue_slots[25].in_uop.bits.ctrl.imm_sel, issue_slots[26].out_uop.ctrl.imm_sel connect issue_slots[25].in_uop.bits.ctrl.op2_sel, issue_slots[26].out_uop.ctrl.op2_sel connect issue_slots[25].in_uop.bits.ctrl.op1_sel, issue_slots[26].out_uop.ctrl.op1_sel connect issue_slots[25].in_uop.bits.ctrl.br_type, issue_slots[26].out_uop.ctrl.br_type connect issue_slots[25].in_uop.bits.fu_code, issue_slots[26].out_uop.fu_code connect issue_slots[25].in_uop.bits.iq_type, issue_slots[26].out_uop.iq_type connect issue_slots[25].in_uop.bits.debug_pc, issue_slots[26].out_uop.debug_pc connect issue_slots[25].in_uop.bits.is_rvc, issue_slots[26].out_uop.is_rvc connect issue_slots[25].in_uop.bits.debug_inst, issue_slots[26].out_uop.debug_inst connect issue_slots[25].in_uop.bits.inst, issue_slots[26].out_uop.inst connect issue_slots[25].in_uop.bits.uopc, issue_slots[26].out_uop.uopc node _T_336 = eq(_WIRE_30, UInt<2>(0h2)) when _T_336 : connect issue_slots[25].in_uop.valid, issue_slots[27].will_be_valid connect issue_slots[25].in_uop.bits.debug_tsrc, issue_slots[27].out_uop.debug_tsrc connect issue_slots[25].in_uop.bits.debug_fsrc, issue_slots[27].out_uop.debug_fsrc connect issue_slots[25].in_uop.bits.bp_xcpt_if, issue_slots[27].out_uop.bp_xcpt_if connect issue_slots[25].in_uop.bits.bp_debug_if, issue_slots[27].out_uop.bp_debug_if connect issue_slots[25].in_uop.bits.xcpt_ma_if, issue_slots[27].out_uop.xcpt_ma_if connect issue_slots[25].in_uop.bits.xcpt_ae_if, issue_slots[27].out_uop.xcpt_ae_if connect issue_slots[25].in_uop.bits.xcpt_pf_if, issue_slots[27].out_uop.xcpt_pf_if connect issue_slots[25].in_uop.bits.fp_single, issue_slots[27].out_uop.fp_single connect issue_slots[25].in_uop.bits.fp_val, issue_slots[27].out_uop.fp_val connect issue_slots[25].in_uop.bits.frs3_en, issue_slots[27].out_uop.frs3_en connect issue_slots[25].in_uop.bits.lrs2_rtype, issue_slots[27].out_uop.lrs2_rtype connect issue_slots[25].in_uop.bits.lrs1_rtype, issue_slots[27].out_uop.lrs1_rtype connect issue_slots[25].in_uop.bits.dst_rtype, issue_slots[27].out_uop.dst_rtype connect issue_slots[25].in_uop.bits.ldst_val, issue_slots[27].out_uop.ldst_val connect issue_slots[25].in_uop.bits.lrs3, issue_slots[27].out_uop.lrs3 connect issue_slots[25].in_uop.bits.lrs2, issue_slots[27].out_uop.lrs2 connect issue_slots[25].in_uop.bits.lrs1, issue_slots[27].out_uop.lrs1 connect issue_slots[25].in_uop.bits.ldst, issue_slots[27].out_uop.ldst connect issue_slots[25].in_uop.bits.ldst_is_rs1, issue_slots[27].out_uop.ldst_is_rs1 connect issue_slots[25].in_uop.bits.flush_on_commit, issue_slots[27].out_uop.flush_on_commit connect issue_slots[25].in_uop.bits.is_unique, issue_slots[27].out_uop.is_unique connect issue_slots[25].in_uop.bits.is_sys_pc2epc, issue_slots[27].out_uop.is_sys_pc2epc connect issue_slots[25].in_uop.bits.uses_stq, issue_slots[27].out_uop.uses_stq connect issue_slots[25].in_uop.bits.uses_ldq, issue_slots[27].out_uop.uses_ldq connect issue_slots[25].in_uop.bits.is_amo, issue_slots[27].out_uop.is_amo connect issue_slots[25].in_uop.bits.is_fencei, issue_slots[27].out_uop.is_fencei connect issue_slots[25].in_uop.bits.is_fence, issue_slots[27].out_uop.is_fence connect issue_slots[25].in_uop.bits.mem_signed, issue_slots[27].out_uop.mem_signed connect issue_slots[25].in_uop.bits.mem_size, issue_slots[27].out_uop.mem_size connect issue_slots[25].in_uop.bits.mem_cmd, issue_slots[27].out_uop.mem_cmd connect issue_slots[25].in_uop.bits.bypassable, issue_slots[27].out_uop.bypassable connect issue_slots[25].in_uop.bits.exc_cause, issue_slots[27].out_uop.exc_cause connect issue_slots[25].in_uop.bits.exception, issue_slots[27].out_uop.exception connect issue_slots[25].in_uop.bits.stale_pdst, issue_slots[27].out_uop.stale_pdst connect issue_slots[25].in_uop.bits.ppred_busy, issue_slots[27].out_uop.ppred_busy connect issue_slots[25].in_uop.bits.prs3_busy, issue_slots[27].out_uop.prs3_busy connect issue_slots[25].in_uop.bits.prs2_busy, issue_slots[27].out_uop.prs2_busy connect issue_slots[25].in_uop.bits.prs1_busy, issue_slots[27].out_uop.prs1_busy connect issue_slots[25].in_uop.bits.ppred, issue_slots[27].out_uop.ppred connect issue_slots[25].in_uop.bits.prs3, issue_slots[27].out_uop.prs3 connect issue_slots[25].in_uop.bits.prs2, issue_slots[27].out_uop.prs2 connect issue_slots[25].in_uop.bits.prs1, issue_slots[27].out_uop.prs1 connect issue_slots[25].in_uop.bits.pdst, issue_slots[27].out_uop.pdst connect issue_slots[25].in_uop.bits.rxq_idx, issue_slots[27].out_uop.rxq_idx connect issue_slots[25].in_uop.bits.stq_idx, issue_slots[27].out_uop.stq_idx connect issue_slots[25].in_uop.bits.ldq_idx, issue_slots[27].out_uop.ldq_idx connect issue_slots[25].in_uop.bits.rob_idx, issue_slots[27].out_uop.rob_idx connect issue_slots[25].in_uop.bits.csr_addr, issue_slots[27].out_uop.csr_addr connect issue_slots[25].in_uop.bits.imm_packed, issue_slots[27].out_uop.imm_packed connect issue_slots[25].in_uop.bits.taken, issue_slots[27].out_uop.taken connect issue_slots[25].in_uop.bits.pc_lob, issue_slots[27].out_uop.pc_lob connect issue_slots[25].in_uop.bits.edge_inst, issue_slots[27].out_uop.edge_inst connect issue_slots[25].in_uop.bits.ftq_idx, issue_slots[27].out_uop.ftq_idx connect issue_slots[25].in_uop.bits.br_tag, issue_slots[27].out_uop.br_tag connect issue_slots[25].in_uop.bits.br_mask, issue_slots[27].out_uop.br_mask connect issue_slots[25].in_uop.bits.is_sfb, issue_slots[27].out_uop.is_sfb connect issue_slots[25].in_uop.bits.is_jal, issue_slots[27].out_uop.is_jal connect issue_slots[25].in_uop.bits.is_jalr, issue_slots[27].out_uop.is_jalr connect issue_slots[25].in_uop.bits.is_br, issue_slots[27].out_uop.is_br connect issue_slots[25].in_uop.bits.iw_p2_poisoned, issue_slots[27].out_uop.iw_p2_poisoned connect issue_slots[25].in_uop.bits.iw_p1_poisoned, issue_slots[27].out_uop.iw_p1_poisoned connect issue_slots[25].in_uop.bits.iw_state, issue_slots[27].out_uop.iw_state connect issue_slots[25].in_uop.bits.ctrl.is_std, issue_slots[27].out_uop.ctrl.is_std connect issue_slots[25].in_uop.bits.ctrl.is_sta, issue_slots[27].out_uop.ctrl.is_sta connect issue_slots[25].in_uop.bits.ctrl.is_load, issue_slots[27].out_uop.ctrl.is_load connect issue_slots[25].in_uop.bits.ctrl.csr_cmd, issue_slots[27].out_uop.ctrl.csr_cmd connect issue_slots[25].in_uop.bits.ctrl.fcn_dw, issue_slots[27].out_uop.ctrl.fcn_dw connect issue_slots[25].in_uop.bits.ctrl.op_fcn, issue_slots[27].out_uop.ctrl.op_fcn connect issue_slots[25].in_uop.bits.ctrl.imm_sel, issue_slots[27].out_uop.ctrl.imm_sel connect issue_slots[25].in_uop.bits.ctrl.op2_sel, issue_slots[27].out_uop.ctrl.op2_sel connect issue_slots[25].in_uop.bits.ctrl.op1_sel, issue_slots[27].out_uop.ctrl.op1_sel connect issue_slots[25].in_uop.bits.ctrl.br_type, issue_slots[27].out_uop.ctrl.br_type connect issue_slots[25].in_uop.bits.fu_code, issue_slots[27].out_uop.fu_code connect issue_slots[25].in_uop.bits.iq_type, issue_slots[27].out_uop.iq_type connect issue_slots[25].in_uop.bits.debug_pc, issue_slots[27].out_uop.debug_pc connect issue_slots[25].in_uop.bits.is_rvc, issue_slots[27].out_uop.is_rvc connect issue_slots[25].in_uop.bits.debug_inst, issue_slots[27].out_uop.debug_inst connect issue_slots[25].in_uop.bits.inst, issue_slots[27].out_uop.inst connect issue_slots[25].in_uop.bits.uopc, issue_slots[27].out_uop.uopc node _T_337 = eq(_WIRE_31, UInt<3>(0h4)) when _T_337 : connect issue_slots[25].in_uop.valid, issue_slots[28].will_be_valid connect issue_slots[25].in_uop.bits.debug_tsrc, issue_slots[28].out_uop.debug_tsrc connect issue_slots[25].in_uop.bits.debug_fsrc, issue_slots[28].out_uop.debug_fsrc connect issue_slots[25].in_uop.bits.bp_xcpt_if, issue_slots[28].out_uop.bp_xcpt_if connect issue_slots[25].in_uop.bits.bp_debug_if, issue_slots[28].out_uop.bp_debug_if connect issue_slots[25].in_uop.bits.xcpt_ma_if, issue_slots[28].out_uop.xcpt_ma_if connect issue_slots[25].in_uop.bits.xcpt_ae_if, issue_slots[28].out_uop.xcpt_ae_if connect issue_slots[25].in_uop.bits.xcpt_pf_if, issue_slots[28].out_uop.xcpt_pf_if connect issue_slots[25].in_uop.bits.fp_single, issue_slots[28].out_uop.fp_single connect issue_slots[25].in_uop.bits.fp_val, issue_slots[28].out_uop.fp_val connect issue_slots[25].in_uop.bits.frs3_en, issue_slots[28].out_uop.frs3_en connect issue_slots[25].in_uop.bits.lrs2_rtype, issue_slots[28].out_uop.lrs2_rtype connect issue_slots[25].in_uop.bits.lrs1_rtype, issue_slots[28].out_uop.lrs1_rtype connect issue_slots[25].in_uop.bits.dst_rtype, issue_slots[28].out_uop.dst_rtype connect issue_slots[25].in_uop.bits.ldst_val, issue_slots[28].out_uop.ldst_val connect issue_slots[25].in_uop.bits.lrs3, issue_slots[28].out_uop.lrs3 connect issue_slots[25].in_uop.bits.lrs2, issue_slots[28].out_uop.lrs2 connect issue_slots[25].in_uop.bits.lrs1, issue_slots[28].out_uop.lrs1 connect issue_slots[25].in_uop.bits.ldst, issue_slots[28].out_uop.ldst connect issue_slots[25].in_uop.bits.ldst_is_rs1, issue_slots[28].out_uop.ldst_is_rs1 connect issue_slots[25].in_uop.bits.flush_on_commit, issue_slots[28].out_uop.flush_on_commit connect issue_slots[25].in_uop.bits.is_unique, issue_slots[28].out_uop.is_unique connect issue_slots[25].in_uop.bits.is_sys_pc2epc, issue_slots[28].out_uop.is_sys_pc2epc connect issue_slots[25].in_uop.bits.uses_stq, issue_slots[28].out_uop.uses_stq connect issue_slots[25].in_uop.bits.uses_ldq, issue_slots[28].out_uop.uses_ldq connect issue_slots[25].in_uop.bits.is_amo, issue_slots[28].out_uop.is_amo connect issue_slots[25].in_uop.bits.is_fencei, issue_slots[28].out_uop.is_fencei connect issue_slots[25].in_uop.bits.is_fence, issue_slots[28].out_uop.is_fence connect issue_slots[25].in_uop.bits.mem_signed, issue_slots[28].out_uop.mem_signed connect issue_slots[25].in_uop.bits.mem_size, issue_slots[28].out_uop.mem_size connect issue_slots[25].in_uop.bits.mem_cmd, issue_slots[28].out_uop.mem_cmd connect issue_slots[25].in_uop.bits.bypassable, issue_slots[28].out_uop.bypassable connect issue_slots[25].in_uop.bits.exc_cause, issue_slots[28].out_uop.exc_cause connect issue_slots[25].in_uop.bits.exception, issue_slots[28].out_uop.exception connect issue_slots[25].in_uop.bits.stale_pdst, issue_slots[28].out_uop.stale_pdst connect issue_slots[25].in_uop.bits.ppred_busy, issue_slots[28].out_uop.ppred_busy connect issue_slots[25].in_uop.bits.prs3_busy, issue_slots[28].out_uop.prs3_busy connect issue_slots[25].in_uop.bits.prs2_busy, issue_slots[28].out_uop.prs2_busy connect issue_slots[25].in_uop.bits.prs1_busy, issue_slots[28].out_uop.prs1_busy connect issue_slots[25].in_uop.bits.ppred, issue_slots[28].out_uop.ppred connect issue_slots[25].in_uop.bits.prs3, issue_slots[28].out_uop.prs3 connect issue_slots[25].in_uop.bits.prs2, issue_slots[28].out_uop.prs2 connect issue_slots[25].in_uop.bits.prs1, issue_slots[28].out_uop.prs1 connect issue_slots[25].in_uop.bits.pdst, issue_slots[28].out_uop.pdst connect issue_slots[25].in_uop.bits.rxq_idx, issue_slots[28].out_uop.rxq_idx connect issue_slots[25].in_uop.bits.stq_idx, issue_slots[28].out_uop.stq_idx connect issue_slots[25].in_uop.bits.ldq_idx, issue_slots[28].out_uop.ldq_idx connect issue_slots[25].in_uop.bits.rob_idx, issue_slots[28].out_uop.rob_idx connect issue_slots[25].in_uop.bits.csr_addr, issue_slots[28].out_uop.csr_addr connect issue_slots[25].in_uop.bits.imm_packed, issue_slots[28].out_uop.imm_packed connect issue_slots[25].in_uop.bits.taken, issue_slots[28].out_uop.taken connect issue_slots[25].in_uop.bits.pc_lob, issue_slots[28].out_uop.pc_lob connect issue_slots[25].in_uop.bits.edge_inst, issue_slots[28].out_uop.edge_inst connect issue_slots[25].in_uop.bits.ftq_idx, issue_slots[28].out_uop.ftq_idx connect issue_slots[25].in_uop.bits.br_tag, issue_slots[28].out_uop.br_tag connect issue_slots[25].in_uop.bits.br_mask, issue_slots[28].out_uop.br_mask connect issue_slots[25].in_uop.bits.is_sfb, issue_slots[28].out_uop.is_sfb connect issue_slots[25].in_uop.bits.is_jal, issue_slots[28].out_uop.is_jal connect issue_slots[25].in_uop.bits.is_jalr, issue_slots[28].out_uop.is_jalr connect issue_slots[25].in_uop.bits.is_br, issue_slots[28].out_uop.is_br connect issue_slots[25].in_uop.bits.iw_p2_poisoned, issue_slots[28].out_uop.iw_p2_poisoned connect issue_slots[25].in_uop.bits.iw_p1_poisoned, issue_slots[28].out_uop.iw_p1_poisoned connect issue_slots[25].in_uop.bits.iw_state, issue_slots[28].out_uop.iw_state connect issue_slots[25].in_uop.bits.ctrl.is_std, issue_slots[28].out_uop.ctrl.is_std connect issue_slots[25].in_uop.bits.ctrl.is_sta, issue_slots[28].out_uop.ctrl.is_sta connect issue_slots[25].in_uop.bits.ctrl.is_load, issue_slots[28].out_uop.ctrl.is_load connect issue_slots[25].in_uop.bits.ctrl.csr_cmd, issue_slots[28].out_uop.ctrl.csr_cmd connect issue_slots[25].in_uop.bits.ctrl.fcn_dw, issue_slots[28].out_uop.ctrl.fcn_dw connect issue_slots[25].in_uop.bits.ctrl.op_fcn, issue_slots[28].out_uop.ctrl.op_fcn connect issue_slots[25].in_uop.bits.ctrl.imm_sel, issue_slots[28].out_uop.ctrl.imm_sel connect issue_slots[25].in_uop.bits.ctrl.op2_sel, issue_slots[28].out_uop.ctrl.op2_sel connect issue_slots[25].in_uop.bits.ctrl.op1_sel, issue_slots[28].out_uop.ctrl.op1_sel connect issue_slots[25].in_uop.bits.ctrl.br_type, issue_slots[28].out_uop.ctrl.br_type connect issue_slots[25].in_uop.bits.fu_code, issue_slots[28].out_uop.fu_code connect issue_slots[25].in_uop.bits.iq_type, issue_slots[28].out_uop.iq_type connect issue_slots[25].in_uop.bits.debug_pc, issue_slots[28].out_uop.debug_pc connect issue_slots[25].in_uop.bits.is_rvc, issue_slots[28].out_uop.is_rvc connect issue_slots[25].in_uop.bits.debug_inst, issue_slots[28].out_uop.debug_inst connect issue_slots[25].in_uop.bits.inst, issue_slots[28].out_uop.inst connect issue_slots[25].in_uop.bits.uopc, issue_slots[28].out_uop.uopc node _issue_slots_25_clear_T = neq(_WIRE_28, UInt<1>(0h0)) connect issue_slots[25].clear, _issue_slots_25_clear_T connect issue_slots[26].in_uop.valid, UInt<1>(0h0) connect issue_slots[26].in_uop.bits.debug_tsrc, issue_slots[27].out_uop.debug_tsrc connect issue_slots[26].in_uop.bits.debug_fsrc, issue_slots[27].out_uop.debug_fsrc connect issue_slots[26].in_uop.bits.bp_xcpt_if, issue_slots[27].out_uop.bp_xcpt_if connect issue_slots[26].in_uop.bits.bp_debug_if, issue_slots[27].out_uop.bp_debug_if connect issue_slots[26].in_uop.bits.xcpt_ma_if, issue_slots[27].out_uop.xcpt_ma_if connect issue_slots[26].in_uop.bits.xcpt_ae_if, issue_slots[27].out_uop.xcpt_ae_if connect issue_slots[26].in_uop.bits.xcpt_pf_if, issue_slots[27].out_uop.xcpt_pf_if connect issue_slots[26].in_uop.bits.fp_single, issue_slots[27].out_uop.fp_single connect issue_slots[26].in_uop.bits.fp_val, issue_slots[27].out_uop.fp_val connect issue_slots[26].in_uop.bits.frs3_en, issue_slots[27].out_uop.frs3_en connect issue_slots[26].in_uop.bits.lrs2_rtype, issue_slots[27].out_uop.lrs2_rtype connect issue_slots[26].in_uop.bits.lrs1_rtype, issue_slots[27].out_uop.lrs1_rtype connect issue_slots[26].in_uop.bits.dst_rtype, issue_slots[27].out_uop.dst_rtype connect issue_slots[26].in_uop.bits.ldst_val, issue_slots[27].out_uop.ldst_val connect issue_slots[26].in_uop.bits.lrs3, issue_slots[27].out_uop.lrs3 connect issue_slots[26].in_uop.bits.lrs2, issue_slots[27].out_uop.lrs2 connect issue_slots[26].in_uop.bits.lrs1, issue_slots[27].out_uop.lrs1 connect issue_slots[26].in_uop.bits.ldst, issue_slots[27].out_uop.ldst connect issue_slots[26].in_uop.bits.ldst_is_rs1, issue_slots[27].out_uop.ldst_is_rs1 connect issue_slots[26].in_uop.bits.flush_on_commit, issue_slots[27].out_uop.flush_on_commit connect issue_slots[26].in_uop.bits.is_unique, issue_slots[27].out_uop.is_unique connect issue_slots[26].in_uop.bits.is_sys_pc2epc, issue_slots[27].out_uop.is_sys_pc2epc connect issue_slots[26].in_uop.bits.uses_stq, issue_slots[27].out_uop.uses_stq connect issue_slots[26].in_uop.bits.uses_ldq, issue_slots[27].out_uop.uses_ldq connect issue_slots[26].in_uop.bits.is_amo, issue_slots[27].out_uop.is_amo connect issue_slots[26].in_uop.bits.is_fencei, issue_slots[27].out_uop.is_fencei connect issue_slots[26].in_uop.bits.is_fence, issue_slots[27].out_uop.is_fence connect issue_slots[26].in_uop.bits.mem_signed, issue_slots[27].out_uop.mem_signed connect issue_slots[26].in_uop.bits.mem_size, issue_slots[27].out_uop.mem_size connect issue_slots[26].in_uop.bits.mem_cmd, issue_slots[27].out_uop.mem_cmd connect issue_slots[26].in_uop.bits.bypassable, issue_slots[27].out_uop.bypassable connect issue_slots[26].in_uop.bits.exc_cause, issue_slots[27].out_uop.exc_cause connect issue_slots[26].in_uop.bits.exception, issue_slots[27].out_uop.exception connect issue_slots[26].in_uop.bits.stale_pdst, issue_slots[27].out_uop.stale_pdst connect issue_slots[26].in_uop.bits.ppred_busy, issue_slots[27].out_uop.ppred_busy connect issue_slots[26].in_uop.bits.prs3_busy, issue_slots[27].out_uop.prs3_busy connect issue_slots[26].in_uop.bits.prs2_busy, issue_slots[27].out_uop.prs2_busy connect issue_slots[26].in_uop.bits.prs1_busy, issue_slots[27].out_uop.prs1_busy connect issue_slots[26].in_uop.bits.ppred, issue_slots[27].out_uop.ppred connect issue_slots[26].in_uop.bits.prs3, issue_slots[27].out_uop.prs3 connect issue_slots[26].in_uop.bits.prs2, issue_slots[27].out_uop.prs2 connect issue_slots[26].in_uop.bits.prs1, issue_slots[27].out_uop.prs1 connect issue_slots[26].in_uop.bits.pdst, issue_slots[27].out_uop.pdst connect issue_slots[26].in_uop.bits.rxq_idx, issue_slots[27].out_uop.rxq_idx connect issue_slots[26].in_uop.bits.stq_idx, issue_slots[27].out_uop.stq_idx connect issue_slots[26].in_uop.bits.ldq_idx, issue_slots[27].out_uop.ldq_idx connect issue_slots[26].in_uop.bits.rob_idx, issue_slots[27].out_uop.rob_idx connect issue_slots[26].in_uop.bits.csr_addr, issue_slots[27].out_uop.csr_addr connect issue_slots[26].in_uop.bits.imm_packed, issue_slots[27].out_uop.imm_packed connect issue_slots[26].in_uop.bits.taken, issue_slots[27].out_uop.taken connect issue_slots[26].in_uop.bits.pc_lob, issue_slots[27].out_uop.pc_lob connect issue_slots[26].in_uop.bits.edge_inst, issue_slots[27].out_uop.edge_inst connect issue_slots[26].in_uop.bits.ftq_idx, issue_slots[27].out_uop.ftq_idx connect issue_slots[26].in_uop.bits.br_tag, issue_slots[27].out_uop.br_tag connect issue_slots[26].in_uop.bits.br_mask, issue_slots[27].out_uop.br_mask connect issue_slots[26].in_uop.bits.is_sfb, issue_slots[27].out_uop.is_sfb connect issue_slots[26].in_uop.bits.is_jal, issue_slots[27].out_uop.is_jal connect issue_slots[26].in_uop.bits.is_jalr, issue_slots[27].out_uop.is_jalr connect issue_slots[26].in_uop.bits.is_br, issue_slots[27].out_uop.is_br connect issue_slots[26].in_uop.bits.iw_p2_poisoned, issue_slots[27].out_uop.iw_p2_poisoned connect issue_slots[26].in_uop.bits.iw_p1_poisoned, issue_slots[27].out_uop.iw_p1_poisoned connect issue_slots[26].in_uop.bits.iw_state, issue_slots[27].out_uop.iw_state connect issue_slots[26].in_uop.bits.ctrl.is_std, issue_slots[27].out_uop.ctrl.is_std connect issue_slots[26].in_uop.bits.ctrl.is_sta, issue_slots[27].out_uop.ctrl.is_sta connect issue_slots[26].in_uop.bits.ctrl.is_load, issue_slots[27].out_uop.ctrl.is_load connect issue_slots[26].in_uop.bits.ctrl.csr_cmd, issue_slots[27].out_uop.ctrl.csr_cmd connect issue_slots[26].in_uop.bits.ctrl.fcn_dw, issue_slots[27].out_uop.ctrl.fcn_dw connect issue_slots[26].in_uop.bits.ctrl.op_fcn, issue_slots[27].out_uop.ctrl.op_fcn connect issue_slots[26].in_uop.bits.ctrl.imm_sel, issue_slots[27].out_uop.ctrl.imm_sel connect issue_slots[26].in_uop.bits.ctrl.op2_sel, issue_slots[27].out_uop.ctrl.op2_sel connect issue_slots[26].in_uop.bits.ctrl.op1_sel, issue_slots[27].out_uop.ctrl.op1_sel connect issue_slots[26].in_uop.bits.ctrl.br_type, issue_slots[27].out_uop.ctrl.br_type connect issue_slots[26].in_uop.bits.fu_code, issue_slots[27].out_uop.fu_code connect issue_slots[26].in_uop.bits.iq_type, issue_slots[27].out_uop.iq_type connect issue_slots[26].in_uop.bits.debug_pc, issue_slots[27].out_uop.debug_pc connect issue_slots[26].in_uop.bits.is_rvc, issue_slots[27].out_uop.is_rvc connect issue_slots[26].in_uop.bits.debug_inst, issue_slots[27].out_uop.debug_inst connect issue_slots[26].in_uop.bits.inst, issue_slots[27].out_uop.inst connect issue_slots[26].in_uop.bits.uopc, issue_slots[27].out_uop.uopc node _T_338 = eq(_WIRE_30, UInt<1>(0h1)) when _T_338 : connect issue_slots[26].in_uop.valid, issue_slots[27].will_be_valid connect issue_slots[26].in_uop.bits.debug_tsrc, issue_slots[27].out_uop.debug_tsrc connect issue_slots[26].in_uop.bits.debug_fsrc, issue_slots[27].out_uop.debug_fsrc connect issue_slots[26].in_uop.bits.bp_xcpt_if, issue_slots[27].out_uop.bp_xcpt_if connect issue_slots[26].in_uop.bits.bp_debug_if, issue_slots[27].out_uop.bp_debug_if connect issue_slots[26].in_uop.bits.xcpt_ma_if, issue_slots[27].out_uop.xcpt_ma_if connect issue_slots[26].in_uop.bits.xcpt_ae_if, issue_slots[27].out_uop.xcpt_ae_if connect issue_slots[26].in_uop.bits.xcpt_pf_if, issue_slots[27].out_uop.xcpt_pf_if connect issue_slots[26].in_uop.bits.fp_single, issue_slots[27].out_uop.fp_single connect issue_slots[26].in_uop.bits.fp_val, issue_slots[27].out_uop.fp_val connect issue_slots[26].in_uop.bits.frs3_en, issue_slots[27].out_uop.frs3_en connect issue_slots[26].in_uop.bits.lrs2_rtype, issue_slots[27].out_uop.lrs2_rtype connect issue_slots[26].in_uop.bits.lrs1_rtype, issue_slots[27].out_uop.lrs1_rtype connect issue_slots[26].in_uop.bits.dst_rtype, issue_slots[27].out_uop.dst_rtype connect issue_slots[26].in_uop.bits.ldst_val, issue_slots[27].out_uop.ldst_val connect issue_slots[26].in_uop.bits.lrs3, issue_slots[27].out_uop.lrs3 connect issue_slots[26].in_uop.bits.lrs2, issue_slots[27].out_uop.lrs2 connect issue_slots[26].in_uop.bits.lrs1, issue_slots[27].out_uop.lrs1 connect issue_slots[26].in_uop.bits.ldst, issue_slots[27].out_uop.ldst connect issue_slots[26].in_uop.bits.ldst_is_rs1, issue_slots[27].out_uop.ldst_is_rs1 connect issue_slots[26].in_uop.bits.flush_on_commit, issue_slots[27].out_uop.flush_on_commit connect issue_slots[26].in_uop.bits.is_unique, issue_slots[27].out_uop.is_unique connect issue_slots[26].in_uop.bits.is_sys_pc2epc, issue_slots[27].out_uop.is_sys_pc2epc connect issue_slots[26].in_uop.bits.uses_stq, issue_slots[27].out_uop.uses_stq connect issue_slots[26].in_uop.bits.uses_ldq, issue_slots[27].out_uop.uses_ldq connect issue_slots[26].in_uop.bits.is_amo, issue_slots[27].out_uop.is_amo connect issue_slots[26].in_uop.bits.is_fencei, issue_slots[27].out_uop.is_fencei connect issue_slots[26].in_uop.bits.is_fence, issue_slots[27].out_uop.is_fence connect issue_slots[26].in_uop.bits.mem_signed, issue_slots[27].out_uop.mem_signed connect issue_slots[26].in_uop.bits.mem_size, issue_slots[27].out_uop.mem_size connect issue_slots[26].in_uop.bits.mem_cmd, issue_slots[27].out_uop.mem_cmd connect issue_slots[26].in_uop.bits.bypassable, issue_slots[27].out_uop.bypassable connect issue_slots[26].in_uop.bits.exc_cause, issue_slots[27].out_uop.exc_cause connect issue_slots[26].in_uop.bits.exception, issue_slots[27].out_uop.exception connect issue_slots[26].in_uop.bits.stale_pdst, issue_slots[27].out_uop.stale_pdst connect issue_slots[26].in_uop.bits.ppred_busy, issue_slots[27].out_uop.ppred_busy connect issue_slots[26].in_uop.bits.prs3_busy, issue_slots[27].out_uop.prs3_busy connect issue_slots[26].in_uop.bits.prs2_busy, issue_slots[27].out_uop.prs2_busy connect issue_slots[26].in_uop.bits.prs1_busy, issue_slots[27].out_uop.prs1_busy connect issue_slots[26].in_uop.bits.ppred, issue_slots[27].out_uop.ppred connect issue_slots[26].in_uop.bits.prs3, issue_slots[27].out_uop.prs3 connect issue_slots[26].in_uop.bits.prs2, issue_slots[27].out_uop.prs2 connect issue_slots[26].in_uop.bits.prs1, issue_slots[27].out_uop.prs1 connect issue_slots[26].in_uop.bits.pdst, issue_slots[27].out_uop.pdst connect issue_slots[26].in_uop.bits.rxq_idx, issue_slots[27].out_uop.rxq_idx connect issue_slots[26].in_uop.bits.stq_idx, issue_slots[27].out_uop.stq_idx connect issue_slots[26].in_uop.bits.ldq_idx, issue_slots[27].out_uop.ldq_idx connect issue_slots[26].in_uop.bits.rob_idx, issue_slots[27].out_uop.rob_idx connect issue_slots[26].in_uop.bits.csr_addr, issue_slots[27].out_uop.csr_addr connect issue_slots[26].in_uop.bits.imm_packed, issue_slots[27].out_uop.imm_packed connect issue_slots[26].in_uop.bits.taken, issue_slots[27].out_uop.taken connect issue_slots[26].in_uop.bits.pc_lob, issue_slots[27].out_uop.pc_lob connect issue_slots[26].in_uop.bits.edge_inst, issue_slots[27].out_uop.edge_inst connect issue_slots[26].in_uop.bits.ftq_idx, issue_slots[27].out_uop.ftq_idx connect issue_slots[26].in_uop.bits.br_tag, issue_slots[27].out_uop.br_tag connect issue_slots[26].in_uop.bits.br_mask, issue_slots[27].out_uop.br_mask connect issue_slots[26].in_uop.bits.is_sfb, issue_slots[27].out_uop.is_sfb connect issue_slots[26].in_uop.bits.is_jal, issue_slots[27].out_uop.is_jal connect issue_slots[26].in_uop.bits.is_jalr, issue_slots[27].out_uop.is_jalr connect issue_slots[26].in_uop.bits.is_br, issue_slots[27].out_uop.is_br connect issue_slots[26].in_uop.bits.iw_p2_poisoned, issue_slots[27].out_uop.iw_p2_poisoned connect issue_slots[26].in_uop.bits.iw_p1_poisoned, issue_slots[27].out_uop.iw_p1_poisoned connect issue_slots[26].in_uop.bits.iw_state, issue_slots[27].out_uop.iw_state connect issue_slots[26].in_uop.bits.ctrl.is_std, issue_slots[27].out_uop.ctrl.is_std connect issue_slots[26].in_uop.bits.ctrl.is_sta, issue_slots[27].out_uop.ctrl.is_sta connect issue_slots[26].in_uop.bits.ctrl.is_load, issue_slots[27].out_uop.ctrl.is_load connect issue_slots[26].in_uop.bits.ctrl.csr_cmd, issue_slots[27].out_uop.ctrl.csr_cmd connect issue_slots[26].in_uop.bits.ctrl.fcn_dw, issue_slots[27].out_uop.ctrl.fcn_dw connect issue_slots[26].in_uop.bits.ctrl.op_fcn, issue_slots[27].out_uop.ctrl.op_fcn connect issue_slots[26].in_uop.bits.ctrl.imm_sel, issue_slots[27].out_uop.ctrl.imm_sel connect issue_slots[26].in_uop.bits.ctrl.op2_sel, issue_slots[27].out_uop.ctrl.op2_sel connect issue_slots[26].in_uop.bits.ctrl.op1_sel, issue_slots[27].out_uop.ctrl.op1_sel connect issue_slots[26].in_uop.bits.ctrl.br_type, issue_slots[27].out_uop.ctrl.br_type connect issue_slots[26].in_uop.bits.fu_code, issue_slots[27].out_uop.fu_code connect issue_slots[26].in_uop.bits.iq_type, issue_slots[27].out_uop.iq_type connect issue_slots[26].in_uop.bits.debug_pc, issue_slots[27].out_uop.debug_pc connect issue_slots[26].in_uop.bits.is_rvc, issue_slots[27].out_uop.is_rvc connect issue_slots[26].in_uop.bits.debug_inst, issue_slots[27].out_uop.debug_inst connect issue_slots[26].in_uop.bits.inst, issue_slots[27].out_uop.inst connect issue_slots[26].in_uop.bits.uopc, issue_slots[27].out_uop.uopc node _T_339 = eq(_WIRE_31, UInt<2>(0h2)) when _T_339 : connect issue_slots[26].in_uop.valid, issue_slots[28].will_be_valid connect issue_slots[26].in_uop.bits.debug_tsrc, issue_slots[28].out_uop.debug_tsrc connect issue_slots[26].in_uop.bits.debug_fsrc, issue_slots[28].out_uop.debug_fsrc connect issue_slots[26].in_uop.bits.bp_xcpt_if, issue_slots[28].out_uop.bp_xcpt_if connect issue_slots[26].in_uop.bits.bp_debug_if, issue_slots[28].out_uop.bp_debug_if connect issue_slots[26].in_uop.bits.xcpt_ma_if, issue_slots[28].out_uop.xcpt_ma_if connect issue_slots[26].in_uop.bits.xcpt_ae_if, issue_slots[28].out_uop.xcpt_ae_if connect issue_slots[26].in_uop.bits.xcpt_pf_if, issue_slots[28].out_uop.xcpt_pf_if connect issue_slots[26].in_uop.bits.fp_single, issue_slots[28].out_uop.fp_single connect issue_slots[26].in_uop.bits.fp_val, issue_slots[28].out_uop.fp_val connect issue_slots[26].in_uop.bits.frs3_en, issue_slots[28].out_uop.frs3_en connect issue_slots[26].in_uop.bits.lrs2_rtype, issue_slots[28].out_uop.lrs2_rtype connect issue_slots[26].in_uop.bits.lrs1_rtype, issue_slots[28].out_uop.lrs1_rtype connect issue_slots[26].in_uop.bits.dst_rtype, issue_slots[28].out_uop.dst_rtype connect issue_slots[26].in_uop.bits.ldst_val, issue_slots[28].out_uop.ldst_val connect issue_slots[26].in_uop.bits.lrs3, issue_slots[28].out_uop.lrs3 connect issue_slots[26].in_uop.bits.lrs2, issue_slots[28].out_uop.lrs2 connect issue_slots[26].in_uop.bits.lrs1, issue_slots[28].out_uop.lrs1 connect issue_slots[26].in_uop.bits.ldst, issue_slots[28].out_uop.ldst connect issue_slots[26].in_uop.bits.ldst_is_rs1, issue_slots[28].out_uop.ldst_is_rs1 connect issue_slots[26].in_uop.bits.flush_on_commit, issue_slots[28].out_uop.flush_on_commit connect issue_slots[26].in_uop.bits.is_unique, issue_slots[28].out_uop.is_unique connect issue_slots[26].in_uop.bits.is_sys_pc2epc, issue_slots[28].out_uop.is_sys_pc2epc connect issue_slots[26].in_uop.bits.uses_stq, issue_slots[28].out_uop.uses_stq connect issue_slots[26].in_uop.bits.uses_ldq, issue_slots[28].out_uop.uses_ldq connect issue_slots[26].in_uop.bits.is_amo, issue_slots[28].out_uop.is_amo connect issue_slots[26].in_uop.bits.is_fencei, issue_slots[28].out_uop.is_fencei connect issue_slots[26].in_uop.bits.is_fence, issue_slots[28].out_uop.is_fence connect issue_slots[26].in_uop.bits.mem_signed, issue_slots[28].out_uop.mem_signed connect issue_slots[26].in_uop.bits.mem_size, issue_slots[28].out_uop.mem_size connect issue_slots[26].in_uop.bits.mem_cmd, issue_slots[28].out_uop.mem_cmd connect issue_slots[26].in_uop.bits.bypassable, issue_slots[28].out_uop.bypassable connect issue_slots[26].in_uop.bits.exc_cause, issue_slots[28].out_uop.exc_cause connect issue_slots[26].in_uop.bits.exception, issue_slots[28].out_uop.exception connect issue_slots[26].in_uop.bits.stale_pdst, issue_slots[28].out_uop.stale_pdst connect issue_slots[26].in_uop.bits.ppred_busy, issue_slots[28].out_uop.ppred_busy connect issue_slots[26].in_uop.bits.prs3_busy, issue_slots[28].out_uop.prs3_busy connect issue_slots[26].in_uop.bits.prs2_busy, issue_slots[28].out_uop.prs2_busy connect issue_slots[26].in_uop.bits.prs1_busy, issue_slots[28].out_uop.prs1_busy connect issue_slots[26].in_uop.bits.ppred, issue_slots[28].out_uop.ppred connect issue_slots[26].in_uop.bits.prs3, issue_slots[28].out_uop.prs3 connect issue_slots[26].in_uop.bits.prs2, issue_slots[28].out_uop.prs2 connect issue_slots[26].in_uop.bits.prs1, issue_slots[28].out_uop.prs1 connect issue_slots[26].in_uop.bits.pdst, issue_slots[28].out_uop.pdst connect issue_slots[26].in_uop.bits.rxq_idx, issue_slots[28].out_uop.rxq_idx connect issue_slots[26].in_uop.bits.stq_idx, issue_slots[28].out_uop.stq_idx connect issue_slots[26].in_uop.bits.ldq_idx, issue_slots[28].out_uop.ldq_idx connect issue_slots[26].in_uop.bits.rob_idx, issue_slots[28].out_uop.rob_idx connect issue_slots[26].in_uop.bits.csr_addr, issue_slots[28].out_uop.csr_addr connect issue_slots[26].in_uop.bits.imm_packed, issue_slots[28].out_uop.imm_packed connect issue_slots[26].in_uop.bits.taken, issue_slots[28].out_uop.taken connect issue_slots[26].in_uop.bits.pc_lob, issue_slots[28].out_uop.pc_lob connect issue_slots[26].in_uop.bits.edge_inst, issue_slots[28].out_uop.edge_inst connect issue_slots[26].in_uop.bits.ftq_idx, issue_slots[28].out_uop.ftq_idx connect issue_slots[26].in_uop.bits.br_tag, issue_slots[28].out_uop.br_tag connect issue_slots[26].in_uop.bits.br_mask, issue_slots[28].out_uop.br_mask connect issue_slots[26].in_uop.bits.is_sfb, issue_slots[28].out_uop.is_sfb connect issue_slots[26].in_uop.bits.is_jal, issue_slots[28].out_uop.is_jal connect issue_slots[26].in_uop.bits.is_jalr, issue_slots[28].out_uop.is_jalr connect issue_slots[26].in_uop.bits.is_br, issue_slots[28].out_uop.is_br connect issue_slots[26].in_uop.bits.iw_p2_poisoned, issue_slots[28].out_uop.iw_p2_poisoned connect issue_slots[26].in_uop.bits.iw_p1_poisoned, issue_slots[28].out_uop.iw_p1_poisoned connect issue_slots[26].in_uop.bits.iw_state, issue_slots[28].out_uop.iw_state connect issue_slots[26].in_uop.bits.ctrl.is_std, issue_slots[28].out_uop.ctrl.is_std connect issue_slots[26].in_uop.bits.ctrl.is_sta, issue_slots[28].out_uop.ctrl.is_sta connect issue_slots[26].in_uop.bits.ctrl.is_load, issue_slots[28].out_uop.ctrl.is_load connect issue_slots[26].in_uop.bits.ctrl.csr_cmd, issue_slots[28].out_uop.ctrl.csr_cmd connect issue_slots[26].in_uop.bits.ctrl.fcn_dw, issue_slots[28].out_uop.ctrl.fcn_dw connect issue_slots[26].in_uop.bits.ctrl.op_fcn, issue_slots[28].out_uop.ctrl.op_fcn connect issue_slots[26].in_uop.bits.ctrl.imm_sel, issue_slots[28].out_uop.ctrl.imm_sel connect issue_slots[26].in_uop.bits.ctrl.op2_sel, issue_slots[28].out_uop.ctrl.op2_sel connect issue_slots[26].in_uop.bits.ctrl.op1_sel, issue_slots[28].out_uop.ctrl.op1_sel connect issue_slots[26].in_uop.bits.ctrl.br_type, issue_slots[28].out_uop.ctrl.br_type connect issue_slots[26].in_uop.bits.fu_code, issue_slots[28].out_uop.fu_code connect issue_slots[26].in_uop.bits.iq_type, issue_slots[28].out_uop.iq_type connect issue_slots[26].in_uop.bits.debug_pc, issue_slots[28].out_uop.debug_pc connect issue_slots[26].in_uop.bits.is_rvc, issue_slots[28].out_uop.is_rvc connect issue_slots[26].in_uop.bits.debug_inst, issue_slots[28].out_uop.debug_inst connect issue_slots[26].in_uop.bits.inst, issue_slots[28].out_uop.inst connect issue_slots[26].in_uop.bits.uopc, issue_slots[28].out_uop.uopc node _T_340 = eq(_WIRE_32, UInt<3>(0h4)) when _T_340 : connect issue_slots[26].in_uop.valid, issue_slots[29].will_be_valid connect issue_slots[26].in_uop.bits.debug_tsrc, issue_slots[29].out_uop.debug_tsrc connect issue_slots[26].in_uop.bits.debug_fsrc, issue_slots[29].out_uop.debug_fsrc connect issue_slots[26].in_uop.bits.bp_xcpt_if, issue_slots[29].out_uop.bp_xcpt_if connect issue_slots[26].in_uop.bits.bp_debug_if, issue_slots[29].out_uop.bp_debug_if connect issue_slots[26].in_uop.bits.xcpt_ma_if, issue_slots[29].out_uop.xcpt_ma_if connect issue_slots[26].in_uop.bits.xcpt_ae_if, issue_slots[29].out_uop.xcpt_ae_if connect issue_slots[26].in_uop.bits.xcpt_pf_if, issue_slots[29].out_uop.xcpt_pf_if connect issue_slots[26].in_uop.bits.fp_single, issue_slots[29].out_uop.fp_single connect issue_slots[26].in_uop.bits.fp_val, issue_slots[29].out_uop.fp_val connect issue_slots[26].in_uop.bits.frs3_en, issue_slots[29].out_uop.frs3_en connect issue_slots[26].in_uop.bits.lrs2_rtype, issue_slots[29].out_uop.lrs2_rtype connect issue_slots[26].in_uop.bits.lrs1_rtype, issue_slots[29].out_uop.lrs1_rtype connect issue_slots[26].in_uop.bits.dst_rtype, issue_slots[29].out_uop.dst_rtype connect issue_slots[26].in_uop.bits.ldst_val, issue_slots[29].out_uop.ldst_val connect issue_slots[26].in_uop.bits.lrs3, issue_slots[29].out_uop.lrs3 connect issue_slots[26].in_uop.bits.lrs2, issue_slots[29].out_uop.lrs2 connect issue_slots[26].in_uop.bits.lrs1, issue_slots[29].out_uop.lrs1 connect issue_slots[26].in_uop.bits.ldst, issue_slots[29].out_uop.ldst connect issue_slots[26].in_uop.bits.ldst_is_rs1, issue_slots[29].out_uop.ldst_is_rs1 connect issue_slots[26].in_uop.bits.flush_on_commit, issue_slots[29].out_uop.flush_on_commit connect issue_slots[26].in_uop.bits.is_unique, issue_slots[29].out_uop.is_unique connect issue_slots[26].in_uop.bits.is_sys_pc2epc, issue_slots[29].out_uop.is_sys_pc2epc connect issue_slots[26].in_uop.bits.uses_stq, issue_slots[29].out_uop.uses_stq connect issue_slots[26].in_uop.bits.uses_ldq, issue_slots[29].out_uop.uses_ldq connect issue_slots[26].in_uop.bits.is_amo, issue_slots[29].out_uop.is_amo connect issue_slots[26].in_uop.bits.is_fencei, issue_slots[29].out_uop.is_fencei connect issue_slots[26].in_uop.bits.is_fence, issue_slots[29].out_uop.is_fence connect issue_slots[26].in_uop.bits.mem_signed, issue_slots[29].out_uop.mem_signed connect issue_slots[26].in_uop.bits.mem_size, issue_slots[29].out_uop.mem_size connect issue_slots[26].in_uop.bits.mem_cmd, issue_slots[29].out_uop.mem_cmd connect issue_slots[26].in_uop.bits.bypassable, issue_slots[29].out_uop.bypassable connect issue_slots[26].in_uop.bits.exc_cause, issue_slots[29].out_uop.exc_cause connect issue_slots[26].in_uop.bits.exception, issue_slots[29].out_uop.exception connect issue_slots[26].in_uop.bits.stale_pdst, issue_slots[29].out_uop.stale_pdst connect issue_slots[26].in_uop.bits.ppred_busy, issue_slots[29].out_uop.ppred_busy connect issue_slots[26].in_uop.bits.prs3_busy, issue_slots[29].out_uop.prs3_busy connect issue_slots[26].in_uop.bits.prs2_busy, issue_slots[29].out_uop.prs2_busy connect issue_slots[26].in_uop.bits.prs1_busy, issue_slots[29].out_uop.prs1_busy connect issue_slots[26].in_uop.bits.ppred, issue_slots[29].out_uop.ppred connect issue_slots[26].in_uop.bits.prs3, issue_slots[29].out_uop.prs3 connect issue_slots[26].in_uop.bits.prs2, issue_slots[29].out_uop.prs2 connect issue_slots[26].in_uop.bits.prs1, issue_slots[29].out_uop.prs1 connect issue_slots[26].in_uop.bits.pdst, issue_slots[29].out_uop.pdst connect issue_slots[26].in_uop.bits.rxq_idx, issue_slots[29].out_uop.rxq_idx connect issue_slots[26].in_uop.bits.stq_idx, issue_slots[29].out_uop.stq_idx connect issue_slots[26].in_uop.bits.ldq_idx, issue_slots[29].out_uop.ldq_idx connect issue_slots[26].in_uop.bits.rob_idx, issue_slots[29].out_uop.rob_idx connect issue_slots[26].in_uop.bits.csr_addr, issue_slots[29].out_uop.csr_addr connect issue_slots[26].in_uop.bits.imm_packed, issue_slots[29].out_uop.imm_packed connect issue_slots[26].in_uop.bits.taken, issue_slots[29].out_uop.taken connect issue_slots[26].in_uop.bits.pc_lob, issue_slots[29].out_uop.pc_lob connect issue_slots[26].in_uop.bits.edge_inst, issue_slots[29].out_uop.edge_inst connect issue_slots[26].in_uop.bits.ftq_idx, issue_slots[29].out_uop.ftq_idx connect issue_slots[26].in_uop.bits.br_tag, issue_slots[29].out_uop.br_tag connect issue_slots[26].in_uop.bits.br_mask, issue_slots[29].out_uop.br_mask connect issue_slots[26].in_uop.bits.is_sfb, issue_slots[29].out_uop.is_sfb connect issue_slots[26].in_uop.bits.is_jal, issue_slots[29].out_uop.is_jal connect issue_slots[26].in_uop.bits.is_jalr, issue_slots[29].out_uop.is_jalr connect issue_slots[26].in_uop.bits.is_br, issue_slots[29].out_uop.is_br connect issue_slots[26].in_uop.bits.iw_p2_poisoned, issue_slots[29].out_uop.iw_p2_poisoned connect issue_slots[26].in_uop.bits.iw_p1_poisoned, issue_slots[29].out_uop.iw_p1_poisoned connect issue_slots[26].in_uop.bits.iw_state, issue_slots[29].out_uop.iw_state connect issue_slots[26].in_uop.bits.ctrl.is_std, issue_slots[29].out_uop.ctrl.is_std connect issue_slots[26].in_uop.bits.ctrl.is_sta, issue_slots[29].out_uop.ctrl.is_sta connect issue_slots[26].in_uop.bits.ctrl.is_load, issue_slots[29].out_uop.ctrl.is_load connect issue_slots[26].in_uop.bits.ctrl.csr_cmd, issue_slots[29].out_uop.ctrl.csr_cmd connect issue_slots[26].in_uop.bits.ctrl.fcn_dw, issue_slots[29].out_uop.ctrl.fcn_dw connect issue_slots[26].in_uop.bits.ctrl.op_fcn, issue_slots[29].out_uop.ctrl.op_fcn connect issue_slots[26].in_uop.bits.ctrl.imm_sel, issue_slots[29].out_uop.ctrl.imm_sel connect issue_slots[26].in_uop.bits.ctrl.op2_sel, issue_slots[29].out_uop.ctrl.op2_sel connect issue_slots[26].in_uop.bits.ctrl.op1_sel, issue_slots[29].out_uop.ctrl.op1_sel connect issue_slots[26].in_uop.bits.ctrl.br_type, issue_slots[29].out_uop.ctrl.br_type connect issue_slots[26].in_uop.bits.fu_code, issue_slots[29].out_uop.fu_code connect issue_slots[26].in_uop.bits.iq_type, issue_slots[29].out_uop.iq_type connect issue_slots[26].in_uop.bits.debug_pc, issue_slots[29].out_uop.debug_pc connect issue_slots[26].in_uop.bits.is_rvc, issue_slots[29].out_uop.is_rvc connect issue_slots[26].in_uop.bits.debug_inst, issue_slots[29].out_uop.debug_inst connect issue_slots[26].in_uop.bits.inst, issue_slots[29].out_uop.inst connect issue_slots[26].in_uop.bits.uopc, issue_slots[29].out_uop.uopc node _issue_slots_26_clear_T = neq(_WIRE_29, UInt<1>(0h0)) connect issue_slots[26].clear, _issue_slots_26_clear_T connect issue_slots[27].in_uop.valid, UInt<1>(0h0) connect issue_slots[27].in_uop.bits.debug_tsrc, issue_slots[28].out_uop.debug_tsrc connect issue_slots[27].in_uop.bits.debug_fsrc, issue_slots[28].out_uop.debug_fsrc connect issue_slots[27].in_uop.bits.bp_xcpt_if, issue_slots[28].out_uop.bp_xcpt_if connect issue_slots[27].in_uop.bits.bp_debug_if, issue_slots[28].out_uop.bp_debug_if connect issue_slots[27].in_uop.bits.xcpt_ma_if, issue_slots[28].out_uop.xcpt_ma_if connect issue_slots[27].in_uop.bits.xcpt_ae_if, issue_slots[28].out_uop.xcpt_ae_if connect issue_slots[27].in_uop.bits.xcpt_pf_if, issue_slots[28].out_uop.xcpt_pf_if connect issue_slots[27].in_uop.bits.fp_single, issue_slots[28].out_uop.fp_single connect issue_slots[27].in_uop.bits.fp_val, issue_slots[28].out_uop.fp_val connect issue_slots[27].in_uop.bits.frs3_en, issue_slots[28].out_uop.frs3_en connect issue_slots[27].in_uop.bits.lrs2_rtype, issue_slots[28].out_uop.lrs2_rtype connect issue_slots[27].in_uop.bits.lrs1_rtype, issue_slots[28].out_uop.lrs1_rtype connect issue_slots[27].in_uop.bits.dst_rtype, issue_slots[28].out_uop.dst_rtype connect issue_slots[27].in_uop.bits.ldst_val, issue_slots[28].out_uop.ldst_val connect issue_slots[27].in_uop.bits.lrs3, issue_slots[28].out_uop.lrs3 connect issue_slots[27].in_uop.bits.lrs2, issue_slots[28].out_uop.lrs2 connect issue_slots[27].in_uop.bits.lrs1, issue_slots[28].out_uop.lrs1 connect issue_slots[27].in_uop.bits.ldst, issue_slots[28].out_uop.ldst connect issue_slots[27].in_uop.bits.ldst_is_rs1, issue_slots[28].out_uop.ldst_is_rs1 connect issue_slots[27].in_uop.bits.flush_on_commit, issue_slots[28].out_uop.flush_on_commit connect issue_slots[27].in_uop.bits.is_unique, issue_slots[28].out_uop.is_unique connect issue_slots[27].in_uop.bits.is_sys_pc2epc, issue_slots[28].out_uop.is_sys_pc2epc connect issue_slots[27].in_uop.bits.uses_stq, issue_slots[28].out_uop.uses_stq connect issue_slots[27].in_uop.bits.uses_ldq, issue_slots[28].out_uop.uses_ldq connect issue_slots[27].in_uop.bits.is_amo, issue_slots[28].out_uop.is_amo connect issue_slots[27].in_uop.bits.is_fencei, issue_slots[28].out_uop.is_fencei connect issue_slots[27].in_uop.bits.is_fence, issue_slots[28].out_uop.is_fence connect issue_slots[27].in_uop.bits.mem_signed, issue_slots[28].out_uop.mem_signed connect issue_slots[27].in_uop.bits.mem_size, issue_slots[28].out_uop.mem_size connect issue_slots[27].in_uop.bits.mem_cmd, issue_slots[28].out_uop.mem_cmd connect issue_slots[27].in_uop.bits.bypassable, issue_slots[28].out_uop.bypassable connect issue_slots[27].in_uop.bits.exc_cause, issue_slots[28].out_uop.exc_cause connect issue_slots[27].in_uop.bits.exception, issue_slots[28].out_uop.exception connect issue_slots[27].in_uop.bits.stale_pdst, issue_slots[28].out_uop.stale_pdst connect issue_slots[27].in_uop.bits.ppred_busy, issue_slots[28].out_uop.ppred_busy connect issue_slots[27].in_uop.bits.prs3_busy, issue_slots[28].out_uop.prs3_busy connect issue_slots[27].in_uop.bits.prs2_busy, issue_slots[28].out_uop.prs2_busy connect issue_slots[27].in_uop.bits.prs1_busy, issue_slots[28].out_uop.prs1_busy connect issue_slots[27].in_uop.bits.ppred, issue_slots[28].out_uop.ppred connect issue_slots[27].in_uop.bits.prs3, issue_slots[28].out_uop.prs3 connect issue_slots[27].in_uop.bits.prs2, issue_slots[28].out_uop.prs2 connect issue_slots[27].in_uop.bits.prs1, issue_slots[28].out_uop.prs1 connect issue_slots[27].in_uop.bits.pdst, issue_slots[28].out_uop.pdst connect issue_slots[27].in_uop.bits.rxq_idx, issue_slots[28].out_uop.rxq_idx connect issue_slots[27].in_uop.bits.stq_idx, issue_slots[28].out_uop.stq_idx connect issue_slots[27].in_uop.bits.ldq_idx, issue_slots[28].out_uop.ldq_idx connect issue_slots[27].in_uop.bits.rob_idx, issue_slots[28].out_uop.rob_idx connect issue_slots[27].in_uop.bits.csr_addr, issue_slots[28].out_uop.csr_addr connect issue_slots[27].in_uop.bits.imm_packed, issue_slots[28].out_uop.imm_packed connect issue_slots[27].in_uop.bits.taken, issue_slots[28].out_uop.taken connect issue_slots[27].in_uop.bits.pc_lob, issue_slots[28].out_uop.pc_lob connect issue_slots[27].in_uop.bits.edge_inst, issue_slots[28].out_uop.edge_inst connect issue_slots[27].in_uop.bits.ftq_idx, issue_slots[28].out_uop.ftq_idx connect issue_slots[27].in_uop.bits.br_tag, issue_slots[28].out_uop.br_tag connect issue_slots[27].in_uop.bits.br_mask, issue_slots[28].out_uop.br_mask connect issue_slots[27].in_uop.bits.is_sfb, issue_slots[28].out_uop.is_sfb connect issue_slots[27].in_uop.bits.is_jal, issue_slots[28].out_uop.is_jal connect issue_slots[27].in_uop.bits.is_jalr, issue_slots[28].out_uop.is_jalr connect issue_slots[27].in_uop.bits.is_br, issue_slots[28].out_uop.is_br connect issue_slots[27].in_uop.bits.iw_p2_poisoned, issue_slots[28].out_uop.iw_p2_poisoned connect issue_slots[27].in_uop.bits.iw_p1_poisoned, issue_slots[28].out_uop.iw_p1_poisoned connect issue_slots[27].in_uop.bits.iw_state, issue_slots[28].out_uop.iw_state connect issue_slots[27].in_uop.bits.ctrl.is_std, issue_slots[28].out_uop.ctrl.is_std connect issue_slots[27].in_uop.bits.ctrl.is_sta, issue_slots[28].out_uop.ctrl.is_sta connect issue_slots[27].in_uop.bits.ctrl.is_load, issue_slots[28].out_uop.ctrl.is_load connect issue_slots[27].in_uop.bits.ctrl.csr_cmd, issue_slots[28].out_uop.ctrl.csr_cmd connect issue_slots[27].in_uop.bits.ctrl.fcn_dw, issue_slots[28].out_uop.ctrl.fcn_dw connect issue_slots[27].in_uop.bits.ctrl.op_fcn, issue_slots[28].out_uop.ctrl.op_fcn connect issue_slots[27].in_uop.bits.ctrl.imm_sel, issue_slots[28].out_uop.ctrl.imm_sel connect issue_slots[27].in_uop.bits.ctrl.op2_sel, issue_slots[28].out_uop.ctrl.op2_sel connect issue_slots[27].in_uop.bits.ctrl.op1_sel, issue_slots[28].out_uop.ctrl.op1_sel connect issue_slots[27].in_uop.bits.ctrl.br_type, issue_slots[28].out_uop.ctrl.br_type connect issue_slots[27].in_uop.bits.fu_code, issue_slots[28].out_uop.fu_code connect issue_slots[27].in_uop.bits.iq_type, issue_slots[28].out_uop.iq_type connect issue_slots[27].in_uop.bits.debug_pc, issue_slots[28].out_uop.debug_pc connect issue_slots[27].in_uop.bits.is_rvc, issue_slots[28].out_uop.is_rvc connect issue_slots[27].in_uop.bits.debug_inst, issue_slots[28].out_uop.debug_inst connect issue_slots[27].in_uop.bits.inst, issue_slots[28].out_uop.inst connect issue_slots[27].in_uop.bits.uopc, issue_slots[28].out_uop.uopc node _T_341 = eq(_WIRE_31, UInt<1>(0h1)) when _T_341 : connect issue_slots[27].in_uop.valid, issue_slots[28].will_be_valid connect issue_slots[27].in_uop.bits.debug_tsrc, issue_slots[28].out_uop.debug_tsrc connect issue_slots[27].in_uop.bits.debug_fsrc, issue_slots[28].out_uop.debug_fsrc connect issue_slots[27].in_uop.bits.bp_xcpt_if, issue_slots[28].out_uop.bp_xcpt_if connect issue_slots[27].in_uop.bits.bp_debug_if, issue_slots[28].out_uop.bp_debug_if connect issue_slots[27].in_uop.bits.xcpt_ma_if, issue_slots[28].out_uop.xcpt_ma_if connect issue_slots[27].in_uop.bits.xcpt_ae_if, issue_slots[28].out_uop.xcpt_ae_if connect issue_slots[27].in_uop.bits.xcpt_pf_if, issue_slots[28].out_uop.xcpt_pf_if connect issue_slots[27].in_uop.bits.fp_single, issue_slots[28].out_uop.fp_single connect issue_slots[27].in_uop.bits.fp_val, issue_slots[28].out_uop.fp_val connect issue_slots[27].in_uop.bits.frs3_en, issue_slots[28].out_uop.frs3_en connect issue_slots[27].in_uop.bits.lrs2_rtype, issue_slots[28].out_uop.lrs2_rtype connect issue_slots[27].in_uop.bits.lrs1_rtype, issue_slots[28].out_uop.lrs1_rtype connect issue_slots[27].in_uop.bits.dst_rtype, issue_slots[28].out_uop.dst_rtype connect issue_slots[27].in_uop.bits.ldst_val, issue_slots[28].out_uop.ldst_val connect issue_slots[27].in_uop.bits.lrs3, issue_slots[28].out_uop.lrs3 connect issue_slots[27].in_uop.bits.lrs2, issue_slots[28].out_uop.lrs2 connect issue_slots[27].in_uop.bits.lrs1, issue_slots[28].out_uop.lrs1 connect issue_slots[27].in_uop.bits.ldst, issue_slots[28].out_uop.ldst connect issue_slots[27].in_uop.bits.ldst_is_rs1, issue_slots[28].out_uop.ldst_is_rs1 connect issue_slots[27].in_uop.bits.flush_on_commit, issue_slots[28].out_uop.flush_on_commit connect issue_slots[27].in_uop.bits.is_unique, issue_slots[28].out_uop.is_unique connect issue_slots[27].in_uop.bits.is_sys_pc2epc, issue_slots[28].out_uop.is_sys_pc2epc connect issue_slots[27].in_uop.bits.uses_stq, issue_slots[28].out_uop.uses_stq connect issue_slots[27].in_uop.bits.uses_ldq, issue_slots[28].out_uop.uses_ldq connect issue_slots[27].in_uop.bits.is_amo, issue_slots[28].out_uop.is_amo connect issue_slots[27].in_uop.bits.is_fencei, issue_slots[28].out_uop.is_fencei connect issue_slots[27].in_uop.bits.is_fence, issue_slots[28].out_uop.is_fence connect issue_slots[27].in_uop.bits.mem_signed, issue_slots[28].out_uop.mem_signed connect issue_slots[27].in_uop.bits.mem_size, issue_slots[28].out_uop.mem_size connect issue_slots[27].in_uop.bits.mem_cmd, issue_slots[28].out_uop.mem_cmd connect issue_slots[27].in_uop.bits.bypassable, issue_slots[28].out_uop.bypassable connect issue_slots[27].in_uop.bits.exc_cause, issue_slots[28].out_uop.exc_cause connect issue_slots[27].in_uop.bits.exception, issue_slots[28].out_uop.exception connect issue_slots[27].in_uop.bits.stale_pdst, issue_slots[28].out_uop.stale_pdst connect issue_slots[27].in_uop.bits.ppred_busy, issue_slots[28].out_uop.ppred_busy connect issue_slots[27].in_uop.bits.prs3_busy, issue_slots[28].out_uop.prs3_busy connect issue_slots[27].in_uop.bits.prs2_busy, issue_slots[28].out_uop.prs2_busy connect issue_slots[27].in_uop.bits.prs1_busy, issue_slots[28].out_uop.prs1_busy connect issue_slots[27].in_uop.bits.ppred, issue_slots[28].out_uop.ppred connect issue_slots[27].in_uop.bits.prs3, issue_slots[28].out_uop.prs3 connect issue_slots[27].in_uop.bits.prs2, issue_slots[28].out_uop.prs2 connect issue_slots[27].in_uop.bits.prs1, issue_slots[28].out_uop.prs1 connect issue_slots[27].in_uop.bits.pdst, issue_slots[28].out_uop.pdst connect issue_slots[27].in_uop.bits.rxq_idx, issue_slots[28].out_uop.rxq_idx connect issue_slots[27].in_uop.bits.stq_idx, issue_slots[28].out_uop.stq_idx connect issue_slots[27].in_uop.bits.ldq_idx, issue_slots[28].out_uop.ldq_idx connect issue_slots[27].in_uop.bits.rob_idx, issue_slots[28].out_uop.rob_idx connect issue_slots[27].in_uop.bits.csr_addr, issue_slots[28].out_uop.csr_addr connect issue_slots[27].in_uop.bits.imm_packed, issue_slots[28].out_uop.imm_packed connect issue_slots[27].in_uop.bits.taken, issue_slots[28].out_uop.taken connect issue_slots[27].in_uop.bits.pc_lob, issue_slots[28].out_uop.pc_lob connect issue_slots[27].in_uop.bits.edge_inst, issue_slots[28].out_uop.edge_inst connect issue_slots[27].in_uop.bits.ftq_idx, issue_slots[28].out_uop.ftq_idx connect issue_slots[27].in_uop.bits.br_tag, issue_slots[28].out_uop.br_tag connect issue_slots[27].in_uop.bits.br_mask, issue_slots[28].out_uop.br_mask connect issue_slots[27].in_uop.bits.is_sfb, issue_slots[28].out_uop.is_sfb connect issue_slots[27].in_uop.bits.is_jal, issue_slots[28].out_uop.is_jal connect issue_slots[27].in_uop.bits.is_jalr, issue_slots[28].out_uop.is_jalr connect issue_slots[27].in_uop.bits.is_br, issue_slots[28].out_uop.is_br connect issue_slots[27].in_uop.bits.iw_p2_poisoned, issue_slots[28].out_uop.iw_p2_poisoned connect issue_slots[27].in_uop.bits.iw_p1_poisoned, issue_slots[28].out_uop.iw_p1_poisoned connect issue_slots[27].in_uop.bits.iw_state, issue_slots[28].out_uop.iw_state connect issue_slots[27].in_uop.bits.ctrl.is_std, issue_slots[28].out_uop.ctrl.is_std connect issue_slots[27].in_uop.bits.ctrl.is_sta, issue_slots[28].out_uop.ctrl.is_sta connect issue_slots[27].in_uop.bits.ctrl.is_load, issue_slots[28].out_uop.ctrl.is_load connect issue_slots[27].in_uop.bits.ctrl.csr_cmd, issue_slots[28].out_uop.ctrl.csr_cmd connect issue_slots[27].in_uop.bits.ctrl.fcn_dw, issue_slots[28].out_uop.ctrl.fcn_dw connect issue_slots[27].in_uop.bits.ctrl.op_fcn, issue_slots[28].out_uop.ctrl.op_fcn connect issue_slots[27].in_uop.bits.ctrl.imm_sel, issue_slots[28].out_uop.ctrl.imm_sel connect issue_slots[27].in_uop.bits.ctrl.op2_sel, issue_slots[28].out_uop.ctrl.op2_sel connect issue_slots[27].in_uop.bits.ctrl.op1_sel, issue_slots[28].out_uop.ctrl.op1_sel connect issue_slots[27].in_uop.bits.ctrl.br_type, issue_slots[28].out_uop.ctrl.br_type connect issue_slots[27].in_uop.bits.fu_code, issue_slots[28].out_uop.fu_code connect issue_slots[27].in_uop.bits.iq_type, issue_slots[28].out_uop.iq_type connect issue_slots[27].in_uop.bits.debug_pc, issue_slots[28].out_uop.debug_pc connect issue_slots[27].in_uop.bits.is_rvc, issue_slots[28].out_uop.is_rvc connect issue_slots[27].in_uop.bits.debug_inst, issue_slots[28].out_uop.debug_inst connect issue_slots[27].in_uop.bits.inst, issue_slots[28].out_uop.inst connect issue_slots[27].in_uop.bits.uopc, issue_slots[28].out_uop.uopc node _T_342 = eq(_WIRE_32, UInt<2>(0h2)) when _T_342 : connect issue_slots[27].in_uop.valid, issue_slots[29].will_be_valid connect issue_slots[27].in_uop.bits.debug_tsrc, issue_slots[29].out_uop.debug_tsrc connect issue_slots[27].in_uop.bits.debug_fsrc, issue_slots[29].out_uop.debug_fsrc connect issue_slots[27].in_uop.bits.bp_xcpt_if, issue_slots[29].out_uop.bp_xcpt_if connect issue_slots[27].in_uop.bits.bp_debug_if, issue_slots[29].out_uop.bp_debug_if connect issue_slots[27].in_uop.bits.xcpt_ma_if, issue_slots[29].out_uop.xcpt_ma_if connect issue_slots[27].in_uop.bits.xcpt_ae_if, issue_slots[29].out_uop.xcpt_ae_if connect issue_slots[27].in_uop.bits.xcpt_pf_if, issue_slots[29].out_uop.xcpt_pf_if connect issue_slots[27].in_uop.bits.fp_single, issue_slots[29].out_uop.fp_single connect issue_slots[27].in_uop.bits.fp_val, issue_slots[29].out_uop.fp_val connect issue_slots[27].in_uop.bits.frs3_en, issue_slots[29].out_uop.frs3_en connect issue_slots[27].in_uop.bits.lrs2_rtype, issue_slots[29].out_uop.lrs2_rtype connect issue_slots[27].in_uop.bits.lrs1_rtype, issue_slots[29].out_uop.lrs1_rtype connect issue_slots[27].in_uop.bits.dst_rtype, issue_slots[29].out_uop.dst_rtype connect issue_slots[27].in_uop.bits.ldst_val, issue_slots[29].out_uop.ldst_val connect issue_slots[27].in_uop.bits.lrs3, issue_slots[29].out_uop.lrs3 connect issue_slots[27].in_uop.bits.lrs2, issue_slots[29].out_uop.lrs2 connect issue_slots[27].in_uop.bits.lrs1, issue_slots[29].out_uop.lrs1 connect issue_slots[27].in_uop.bits.ldst, issue_slots[29].out_uop.ldst connect issue_slots[27].in_uop.bits.ldst_is_rs1, issue_slots[29].out_uop.ldst_is_rs1 connect issue_slots[27].in_uop.bits.flush_on_commit, issue_slots[29].out_uop.flush_on_commit connect issue_slots[27].in_uop.bits.is_unique, issue_slots[29].out_uop.is_unique connect issue_slots[27].in_uop.bits.is_sys_pc2epc, issue_slots[29].out_uop.is_sys_pc2epc connect issue_slots[27].in_uop.bits.uses_stq, issue_slots[29].out_uop.uses_stq connect issue_slots[27].in_uop.bits.uses_ldq, issue_slots[29].out_uop.uses_ldq connect issue_slots[27].in_uop.bits.is_amo, issue_slots[29].out_uop.is_amo connect issue_slots[27].in_uop.bits.is_fencei, issue_slots[29].out_uop.is_fencei connect issue_slots[27].in_uop.bits.is_fence, issue_slots[29].out_uop.is_fence connect issue_slots[27].in_uop.bits.mem_signed, issue_slots[29].out_uop.mem_signed connect issue_slots[27].in_uop.bits.mem_size, issue_slots[29].out_uop.mem_size connect issue_slots[27].in_uop.bits.mem_cmd, issue_slots[29].out_uop.mem_cmd connect issue_slots[27].in_uop.bits.bypassable, issue_slots[29].out_uop.bypassable connect issue_slots[27].in_uop.bits.exc_cause, issue_slots[29].out_uop.exc_cause connect issue_slots[27].in_uop.bits.exception, issue_slots[29].out_uop.exception connect issue_slots[27].in_uop.bits.stale_pdst, issue_slots[29].out_uop.stale_pdst connect issue_slots[27].in_uop.bits.ppred_busy, issue_slots[29].out_uop.ppred_busy connect issue_slots[27].in_uop.bits.prs3_busy, issue_slots[29].out_uop.prs3_busy connect issue_slots[27].in_uop.bits.prs2_busy, issue_slots[29].out_uop.prs2_busy connect issue_slots[27].in_uop.bits.prs1_busy, issue_slots[29].out_uop.prs1_busy connect issue_slots[27].in_uop.bits.ppred, issue_slots[29].out_uop.ppred connect issue_slots[27].in_uop.bits.prs3, issue_slots[29].out_uop.prs3 connect issue_slots[27].in_uop.bits.prs2, issue_slots[29].out_uop.prs2 connect issue_slots[27].in_uop.bits.prs1, issue_slots[29].out_uop.prs1 connect issue_slots[27].in_uop.bits.pdst, issue_slots[29].out_uop.pdst connect issue_slots[27].in_uop.bits.rxq_idx, issue_slots[29].out_uop.rxq_idx connect issue_slots[27].in_uop.bits.stq_idx, issue_slots[29].out_uop.stq_idx connect issue_slots[27].in_uop.bits.ldq_idx, issue_slots[29].out_uop.ldq_idx connect issue_slots[27].in_uop.bits.rob_idx, issue_slots[29].out_uop.rob_idx connect issue_slots[27].in_uop.bits.csr_addr, issue_slots[29].out_uop.csr_addr connect issue_slots[27].in_uop.bits.imm_packed, issue_slots[29].out_uop.imm_packed connect issue_slots[27].in_uop.bits.taken, issue_slots[29].out_uop.taken connect issue_slots[27].in_uop.bits.pc_lob, issue_slots[29].out_uop.pc_lob connect issue_slots[27].in_uop.bits.edge_inst, issue_slots[29].out_uop.edge_inst connect issue_slots[27].in_uop.bits.ftq_idx, issue_slots[29].out_uop.ftq_idx connect issue_slots[27].in_uop.bits.br_tag, issue_slots[29].out_uop.br_tag connect issue_slots[27].in_uop.bits.br_mask, issue_slots[29].out_uop.br_mask connect issue_slots[27].in_uop.bits.is_sfb, issue_slots[29].out_uop.is_sfb connect issue_slots[27].in_uop.bits.is_jal, issue_slots[29].out_uop.is_jal connect issue_slots[27].in_uop.bits.is_jalr, issue_slots[29].out_uop.is_jalr connect issue_slots[27].in_uop.bits.is_br, issue_slots[29].out_uop.is_br connect issue_slots[27].in_uop.bits.iw_p2_poisoned, issue_slots[29].out_uop.iw_p2_poisoned connect issue_slots[27].in_uop.bits.iw_p1_poisoned, issue_slots[29].out_uop.iw_p1_poisoned connect issue_slots[27].in_uop.bits.iw_state, issue_slots[29].out_uop.iw_state connect issue_slots[27].in_uop.bits.ctrl.is_std, issue_slots[29].out_uop.ctrl.is_std connect issue_slots[27].in_uop.bits.ctrl.is_sta, issue_slots[29].out_uop.ctrl.is_sta connect issue_slots[27].in_uop.bits.ctrl.is_load, issue_slots[29].out_uop.ctrl.is_load connect issue_slots[27].in_uop.bits.ctrl.csr_cmd, issue_slots[29].out_uop.ctrl.csr_cmd connect issue_slots[27].in_uop.bits.ctrl.fcn_dw, issue_slots[29].out_uop.ctrl.fcn_dw connect issue_slots[27].in_uop.bits.ctrl.op_fcn, issue_slots[29].out_uop.ctrl.op_fcn connect issue_slots[27].in_uop.bits.ctrl.imm_sel, issue_slots[29].out_uop.ctrl.imm_sel connect issue_slots[27].in_uop.bits.ctrl.op2_sel, issue_slots[29].out_uop.ctrl.op2_sel connect issue_slots[27].in_uop.bits.ctrl.op1_sel, issue_slots[29].out_uop.ctrl.op1_sel connect issue_slots[27].in_uop.bits.ctrl.br_type, issue_slots[29].out_uop.ctrl.br_type connect issue_slots[27].in_uop.bits.fu_code, issue_slots[29].out_uop.fu_code connect issue_slots[27].in_uop.bits.iq_type, issue_slots[29].out_uop.iq_type connect issue_slots[27].in_uop.bits.debug_pc, issue_slots[29].out_uop.debug_pc connect issue_slots[27].in_uop.bits.is_rvc, issue_slots[29].out_uop.is_rvc connect issue_slots[27].in_uop.bits.debug_inst, issue_slots[29].out_uop.debug_inst connect issue_slots[27].in_uop.bits.inst, issue_slots[29].out_uop.inst connect issue_slots[27].in_uop.bits.uopc, issue_slots[29].out_uop.uopc node _T_343 = eq(_WIRE_33, UInt<3>(0h4)) when _T_343 : connect issue_slots[27].in_uop.valid, issue_slots[30].will_be_valid connect issue_slots[27].in_uop.bits.debug_tsrc, issue_slots[30].out_uop.debug_tsrc connect issue_slots[27].in_uop.bits.debug_fsrc, issue_slots[30].out_uop.debug_fsrc connect issue_slots[27].in_uop.bits.bp_xcpt_if, issue_slots[30].out_uop.bp_xcpt_if connect issue_slots[27].in_uop.bits.bp_debug_if, issue_slots[30].out_uop.bp_debug_if connect issue_slots[27].in_uop.bits.xcpt_ma_if, issue_slots[30].out_uop.xcpt_ma_if connect issue_slots[27].in_uop.bits.xcpt_ae_if, issue_slots[30].out_uop.xcpt_ae_if connect issue_slots[27].in_uop.bits.xcpt_pf_if, issue_slots[30].out_uop.xcpt_pf_if connect issue_slots[27].in_uop.bits.fp_single, issue_slots[30].out_uop.fp_single connect issue_slots[27].in_uop.bits.fp_val, issue_slots[30].out_uop.fp_val connect issue_slots[27].in_uop.bits.frs3_en, issue_slots[30].out_uop.frs3_en connect issue_slots[27].in_uop.bits.lrs2_rtype, issue_slots[30].out_uop.lrs2_rtype connect issue_slots[27].in_uop.bits.lrs1_rtype, issue_slots[30].out_uop.lrs1_rtype connect issue_slots[27].in_uop.bits.dst_rtype, issue_slots[30].out_uop.dst_rtype connect issue_slots[27].in_uop.bits.ldst_val, issue_slots[30].out_uop.ldst_val connect issue_slots[27].in_uop.bits.lrs3, issue_slots[30].out_uop.lrs3 connect issue_slots[27].in_uop.bits.lrs2, issue_slots[30].out_uop.lrs2 connect issue_slots[27].in_uop.bits.lrs1, issue_slots[30].out_uop.lrs1 connect issue_slots[27].in_uop.bits.ldst, issue_slots[30].out_uop.ldst connect issue_slots[27].in_uop.bits.ldst_is_rs1, issue_slots[30].out_uop.ldst_is_rs1 connect issue_slots[27].in_uop.bits.flush_on_commit, issue_slots[30].out_uop.flush_on_commit connect issue_slots[27].in_uop.bits.is_unique, issue_slots[30].out_uop.is_unique connect issue_slots[27].in_uop.bits.is_sys_pc2epc, issue_slots[30].out_uop.is_sys_pc2epc connect issue_slots[27].in_uop.bits.uses_stq, issue_slots[30].out_uop.uses_stq connect issue_slots[27].in_uop.bits.uses_ldq, issue_slots[30].out_uop.uses_ldq connect issue_slots[27].in_uop.bits.is_amo, issue_slots[30].out_uop.is_amo connect issue_slots[27].in_uop.bits.is_fencei, issue_slots[30].out_uop.is_fencei connect issue_slots[27].in_uop.bits.is_fence, issue_slots[30].out_uop.is_fence connect issue_slots[27].in_uop.bits.mem_signed, issue_slots[30].out_uop.mem_signed connect issue_slots[27].in_uop.bits.mem_size, issue_slots[30].out_uop.mem_size connect issue_slots[27].in_uop.bits.mem_cmd, issue_slots[30].out_uop.mem_cmd connect issue_slots[27].in_uop.bits.bypassable, issue_slots[30].out_uop.bypassable connect issue_slots[27].in_uop.bits.exc_cause, issue_slots[30].out_uop.exc_cause connect issue_slots[27].in_uop.bits.exception, issue_slots[30].out_uop.exception connect issue_slots[27].in_uop.bits.stale_pdst, issue_slots[30].out_uop.stale_pdst connect issue_slots[27].in_uop.bits.ppred_busy, issue_slots[30].out_uop.ppred_busy connect issue_slots[27].in_uop.bits.prs3_busy, issue_slots[30].out_uop.prs3_busy connect issue_slots[27].in_uop.bits.prs2_busy, issue_slots[30].out_uop.prs2_busy connect issue_slots[27].in_uop.bits.prs1_busy, issue_slots[30].out_uop.prs1_busy connect issue_slots[27].in_uop.bits.ppred, issue_slots[30].out_uop.ppred connect issue_slots[27].in_uop.bits.prs3, issue_slots[30].out_uop.prs3 connect issue_slots[27].in_uop.bits.prs2, issue_slots[30].out_uop.prs2 connect issue_slots[27].in_uop.bits.prs1, issue_slots[30].out_uop.prs1 connect issue_slots[27].in_uop.bits.pdst, issue_slots[30].out_uop.pdst connect issue_slots[27].in_uop.bits.rxq_idx, issue_slots[30].out_uop.rxq_idx connect issue_slots[27].in_uop.bits.stq_idx, issue_slots[30].out_uop.stq_idx connect issue_slots[27].in_uop.bits.ldq_idx, issue_slots[30].out_uop.ldq_idx connect issue_slots[27].in_uop.bits.rob_idx, issue_slots[30].out_uop.rob_idx connect issue_slots[27].in_uop.bits.csr_addr, issue_slots[30].out_uop.csr_addr connect issue_slots[27].in_uop.bits.imm_packed, issue_slots[30].out_uop.imm_packed connect issue_slots[27].in_uop.bits.taken, issue_slots[30].out_uop.taken connect issue_slots[27].in_uop.bits.pc_lob, issue_slots[30].out_uop.pc_lob connect issue_slots[27].in_uop.bits.edge_inst, issue_slots[30].out_uop.edge_inst connect issue_slots[27].in_uop.bits.ftq_idx, issue_slots[30].out_uop.ftq_idx connect issue_slots[27].in_uop.bits.br_tag, issue_slots[30].out_uop.br_tag connect issue_slots[27].in_uop.bits.br_mask, issue_slots[30].out_uop.br_mask connect issue_slots[27].in_uop.bits.is_sfb, issue_slots[30].out_uop.is_sfb connect issue_slots[27].in_uop.bits.is_jal, issue_slots[30].out_uop.is_jal connect issue_slots[27].in_uop.bits.is_jalr, issue_slots[30].out_uop.is_jalr connect issue_slots[27].in_uop.bits.is_br, issue_slots[30].out_uop.is_br connect issue_slots[27].in_uop.bits.iw_p2_poisoned, issue_slots[30].out_uop.iw_p2_poisoned connect issue_slots[27].in_uop.bits.iw_p1_poisoned, issue_slots[30].out_uop.iw_p1_poisoned connect issue_slots[27].in_uop.bits.iw_state, issue_slots[30].out_uop.iw_state connect issue_slots[27].in_uop.bits.ctrl.is_std, issue_slots[30].out_uop.ctrl.is_std connect issue_slots[27].in_uop.bits.ctrl.is_sta, issue_slots[30].out_uop.ctrl.is_sta connect issue_slots[27].in_uop.bits.ctrl.is_load, issue_slots[30].out_uop.ctrl.is_load connect issue_slots[27].in_uop.bits.ctrl.csr_cmd, issue_slots[30].out_uop.ctrl.csr_cmd connect issue_slots[27].in_uop.bits.ctrl.fcn_dw, issue_slots[30].out_uop.ctrl.fcn_dw connect issue_slots[27].in_uop.bits.ctrl.op_fcn, issue_slots[30].out_uop.ctrl.op_fcn connect issue_slots[27].in_uop.bits.ctrl.imm_sel, issue_slots[30].out_uop.ctrl.imm_sel connect issue_slots[27].in_uop.bits.ctrl.op2_sel, issue_slots[30].out_uop.ctrl.op2_sel connect issue_slots[27].in_uop.bits.ctrl.op1_sel, issue_slots[30].out_uop.ctrl.op1_sel connect issue_slots[27].in_uop.bits.ctrl.br_type, issue_slots[30].out_uop.ctrl.br_type connect issue_slots[27].in_uop.bits.fu_code, issue_slots[30].out_uop.fu_code connect issue_slots[27].in_uop.bits.iq_type, issue_slots[30].out_uop.iq_type connect issue_slots[27].in_uop.bits.debug_pc, issue_slots[30].out_uop.debug_pc connect issue_slots[27].in_uop.bits.is_rvc, issue_slots[30].out_uop.is_rvc connect issue_slots[27].in_uop.bits.debug_inst, issue_slots[30].out_uop.debug_inst connect issue_slots[27].in_uop.bits.inst, issue_slots[30].out_uop.inst connect issue_slots[27].in_uop.bits.uopc, issue_slots[30].out_uop.uopc node _issue_slots_27_clear_T = neq(_WIRE_30, UInt<1>(0h0)) connect issue_slots[27].clear, _issue_slots_27_clear_T connect issue_slots[28].in_uop.valid, UInt<1>(0h0) connect issue_slots[28].in_uop.bits.debug_tsrc, issue_slots[29].out_uop.debug_tsrc connect issue_slots[28].in_uop.bits.debug_fsrc, issue_slots[29].out_uop.debug_fsrc connect issue_slots[28].in_uop.bits.bp_xcpt_if, issue_slots[29].out_uop.bp_xcpt_if connect issue_slots[28].in_uop.bits.bp_debug_if, issue_slots[29].out_uop.bp_debug_if connect issue_slots[28].in_uop.bits.xcpt_ma_if, issue_slots[29].out_uop.xcpt_ma_if connect issue_slots[28].in_uop.bits.xcpt_ae_if, issue_slots[29].out_uop.xcpt_ae_if connect issue_slots[28].in_uop.bits.xcpt_pf_if, issue_slots[29].out_uop.xcpt_pf_if connect issue_slots[28].in_uop.bits.fp_single, issue_slots[29].out_uop.fp_single connect issue_slots[28].in_uop.bits.fp_val, issue_slots[29].out_uop.fp_val connect issue_slots[28].in_uop.bits.frs3_en, issue_slots[29].out_uop.frs3_en connect issue_slots[28].in_uop.bits.lrs2_rtype, issue_slots[29].out_uop.lrs2_rtype connect issue_slots[28].in_uop.bits.lrs1_rtype, issue_slots[29].out_uop.lrs1_rtype connect issue_slots[28].in_uop.bits.dst_rtype, issue_slots[29].out_uop.dst_rtype connect issue_slots[28].in_uop.bits.ldst_val, issue_slots[29].out_uop.ldst_val connect issue_slots[28].in_uop.bits.lrs3, issue_slots[29].out_uop.lrs3 connect issue_slots[28].in_uop.bits.lrs2, issue_slots[29].out_uop.lrs2 connect issue_slots[28].in_uop.bits.lrs1, issue_slots[29].out_uop.lrs1 connect issue_slots[28].in_uop.bits.ldst, issue_slots[29].out_uop.ldst connect issue_slots[28].in_uop.bits.ldst_is_rs1, issue_slots[29].out_uop.ldst_is_rs1 connect issue_slots[28].in_uop.bits.flush_on_commit, issue_slots[29].out_uop.flush_on_commit connect issue_slots[28].in_uop.bits.is_unique, issue_slots[29].out_uop.is_unique connect issue_slots[28].in_uop.bits.is_sys_pc2epc, issue_slots[29].out_uop.is_sys_pc2epc connect issue_slots[28].in_uop.bits.uses_stq, issue_slots[29].out_uop.uses_stq connect issue_slots[28].in_uop.bits.uses_ldq, issue_slots[29].out_uop.uses_ldq connect issue_slots[28].in_uop.bits.is_amo, issue_slots[29].out_uop.is_amo connect issue_slots[28].in_uop.bits.is_fencei, issue_slots[29].out_uop.is_fencei connect issue_slots[28].in_uop.bits.is_fence, issue_slots[29].out_uop.is_fence connect issue_slots[28].in_uop.bits.mem_signed, issue_slots[29].out_uop.mem_signed connect issue_slots[28].in_uop.bits.mem_size, issue_slots[29].out_uop.mem_size connect issue_slots[28].in_uop.bits.mem_cmd, issue_slots[29].out_uop.mem_cmd connect issue_slots[28].in_uop.bits.bypassable, issue_slots[29].out_uop.bypassable connect issue_slots[28].in_uop.bits.exc_cause, issue_slots[29].out_uop.exc_cause connect issue_slots[28].in_uop.bits.exception, issue_slots[29].out_uop.exception connect issue_slots[28].in_uop.bits.stale_pdst, issue_slots[29].out_uop.stale_pdst connect issue_slots[28].in_uop.bits.ppred_busy, issue_slots[29].out_uop.ppred_busy connect issue_slots[28].in_uop.bits.prs3_busy, issue_slots[29].out_uop.prs3_busy connect issue_slots[28].in_uop.bits.prs2_busy, issue_slots[29].out_uop.prs2_busy connect issue_slots[28].in_uop.bits.prs1_busy, issue_slots[29].out_uop.prs1_busy connect issue_slots[28].in_uop.bits.ppred, issue_slots[29].out_uop.ppred connect issue_slots[28].in_uop.bits.prs3, issue_slots[29].out_uop.prs3 connect issue_slots[28].in_uop.bits.prs2, issue_slots[29].out_uop.prs2 connect issue_slots[28].in_uop.bits.prs1, issue_slots[29].out_uop.prs1 connect issue_slots[28].in_uop.bits.pdst, issue_slots[29].out_uop.pdst connect issue_slots[28].in_uop.bits.rxq_idx, issue_slots[29].out_uop.rxq_idx connect issue_slots[28].in_uop.bits.stq_idx, issue_slots[29].out_uop.stq_idx connect issue_slots[28].in_uop.bits.ldq_idx, issue_slots[29].out_uop.ldq_idx connect issue_slots[28].in_uop.bits.rob_idx, issue_slots[29].out_uop.rob_idx connect issue_slots[28].in_uop.bits.csr_addr, issue_slots[29].out_uop.csr_addr connect issue_slots[28].in_uop.bits.imm_packed, issue_slots[29].out_uop.imm_packed connect issue_slots[28].in_uop.bits.taken, issue_slots[29].out_uop.taken connect issue_slots[28].in_uop.bits.pc_lob, issue_slots[29].out_uop.pc_lob connect issue_slots[28].in_uop.bits.edge_inst, issue_slots[29].out_uop.edge_inst connect issue_slots[28].in_uop.bits.ftq_idx, issue_slots[29].out_uop.ftq_idx connect issue_slots[28].in_uop.bits.br_tag, issue_slots[29].out_uop.br_tag connect issue_slots[28].in_uop.bits.br_mask, issue_slots[29].out_uop.br_mask connect issue_slots[28].in_uop.bits.is_sfb, issue_slots[29].out_uop.is_sfb connect issue_slots[28].in_uop.bits.is_jal, issue_slots[29].out_uop.is_jal connect issue_slots[28].in_uop.bits.is_jalr, issue_slots[29].out_uop.is_jalr connect issue_slots[28].in_uop.bits.is_br, issue_slots[29].out_uop.is_br connect issue_slots[28].in_uop.bits.iw_p2_poisoned, issue_slots[29].out_uop.iw_p2_poisoned connect issue_slots[28].in_uop.bits.iw_p1_poisoned, issue_slots[29].out_uop.iw_p1_poisoned connect issue_slots[28].in_uop.bits.iw_state, issue_slots[29].out_uop.iw_state connect issue_slots[28].in_uop.bits.ctrl.is_std, issue_slots[29].out_uop.ctrl.is_std connect issue_slots[28].in_uop.bits.ctrl.is_sta, issue_slots[29].out_uop.ctrl.is_sta connect issue_slots[28].in_uop.bits.ctrl.is_load, issue_slots[29].out_uop.ctrl.is_load connect issue_slots[28].in_uop.bits.ctrl.csr_cmd, issue_slots[29].out_uop.ctrl.csr_cmd connect issue_slots[28].in_uop.bits.ctrl.fcn_dw, issue_slots[29].out_uop.ctrl.fcn_dw connect issue_slots[28].in_uop.bits.ctrl.op_fcn, issue_slots[29].out_uop.ctrl.op_fcn connect issue_slots[28].in_uop.bits.ctrl.imm_sel, issue_slots[29].out_uop.ctrl.imm_sel connect issue_slots[28].in_uop.bits.ctrl.op2_sel, issue_slots[29].out_uop.ctrl.op2_sel connect issue_slots[28].in_uop.bits.ctrl.op1_sel, issue_slots[29].out_uop.ctrl.op1_sel connect issue_slots[28].in_uop.bits.ctrl.br_type, issue_slots[29].out_uop.ctrl.br_type connect issue_slots[28].in_uop.bits.fu_code, issue_slots[29].out_uop.fu_code connect issue_slots[28].in_uop.bits.iq_type, issue_slots[29].out_uop.iq_type connect issue_slots[28].in_uop.bits.debug_pc, issue_slots[29].out_uop.debug_pc connect issue_slots[28].in_uop.bits.is_rvc, issue_slots[29].out_uop.is_rvc connect issue_slots[28].in_uop.bits.debug_inst, issue_slots[29].out_uop.debug_inst connect issue_slots[28].in_uop.bits.inst, issue_slots[29].out_uop.inst connect issue_slots[28].in_uop.bits.uopc, issue_slots[29].out_uop.uopc node _T_344 = eq(_WIRE_32, UInt<1>(0h1)) when _T_344 : connect issue_slots[28].in_uop.valid, issue_slots[29].will_be_valid connect issue_slots[28].in_uop.bits.debug_tsrc, issue_slots[29].out_uop.debug_tsrc connect issue_slots[28].in_uop.bits.debug_fsrc, issue_slots[29].out_uop.debug_fsrc connect issue_slots[28].in_uop.bits.bp_xcpt_if, issue_slots[29].out_uop.bp_xcpt_if connect issue_slots[28].in_uop.bits.bp_debug_if, issue_slots[29].out_uop.bp_debug_if connect issue_slots[28].in_uop.bits.xcpt_ma_if, issue_slots[29].out_uop.xcpt_ma_if connect issue_slots[28].in_uop.bits.xcpt_ae_if, issue_slots[29].out_uop.xcpt_ae_if connect issue_slots[28].in_uop.bits.xcpt_pf_if, issue_slots[29].out_uop.xcpt_pf_if connect issue_slots[28].in_uop.bits.fp_single, issue_slots[29].out_uop.fp_single connect issue_slots[28].in_uop.bits.fp_val, issue_slots[29].out_uop.fp_val connect issue_slots[28].in_uop.bits.frs3_en, issue_slots[29].out_uop.frs3_en connect issue_slots[28].in_uop.bits.lrs2_rtype, issue_slots[29].out_uop.lrs2_rtype connect issue_slots[28].in_uop.bits.lrs1_rtype, issue_slots[29].out_uop.lrs1_rtype connect issue_slots[28].in_uop.bits.dst_rtype, issue_slots[29].out_uop.dst_rtype connect issue_slots[28].in_uop.bits.ldst_val, issue_slots[29].out_uop.ldst_val connect issue_slots[28].in_uop.bits.lrs3, issue_slots[29].out_uop.lrs3 connect issue_slots[28].in_uop.bits.lrs2, issue_slots[29].out_uop.lrs2 connect issue_slots[28].in_uop.bits.lrs1, issue_slots[29].out_uop.lrs1 connect issue_slots[28].in_uop.bits.ldst, issue_slots[29].out_uop.ldst connect issue_slots[28].in_uop.bits.ldst_is_rs1, issue_slots[29].out_uop.ldst_is_rs1 connect issue_slots[28].in_uop.bits.flush_on_commit, issue_slots[29].out_uop.flush_on_commit connect issue_slots[28].in_uop.bits.is_unique, issue_slots[29].out_uop.is_unique connect issue_slots[28].in_uop.bits.is_sys_pc2epc, issue_slots[29].out_uop.is_sys_pc2epc connect issue_slots[28].in_uop.bits.uses_stq, issue_slots[29].out_uop.uses_stq connect issue_slots[28].in_uop.bits.uses_ldq, issue_slots[29].out_uop.uses_ldq connect issue_slots[28].in_uop.bits.is_amo, issue_slots[29].out_uop.is_amo connect issue_slots[28].in_uop.bits.is_fencei, issue_slots[29].out_uop.is_fencei connect issue_slots[28].in_uop.bits.is_fence, issue_slots[29].out_uop.is_fence connect issue_slots[28].in_uop.bits.mem_signed, issue_slots[29].out_uop.mem_signed connect issue_slots[28].in_uop.bits.mem_size, issue_slots[29].out_uop.mem_size connect issue_slots[28].in_uop.bits.mem_cmd, issue_slots[29].out_uop.mem_cmd connect issue_slots[28].in_uop.bits.bypassable, issue_slots[29].out_uop.bypassable connect issue_slots[28].in_uop.bits.exc_cause, issue_slots[29].out_uop.exc_cause connect issue_slots[28].in_uop.bits.exception, issue_slots[29].out_uop.exception connect issue_slots[28].in_uop.bits.stale_pdst, issue_slots[29].out_uop.stale_pdst connect issue_slots[28].in_uop.bits.ppred_busy, issue_slots[29].out_uop.ppred_busy connect issue_slots[28].in_uop.bits.prs3_busy, issue_slots[29].out_uop.prs3_busy connect issue_slots[28].in_uop.bits.prs2_busy, issue_slots[29].out_uop.prs2_busy connect issue_slots[28].in_uop.bits.prs1_busy, issue_slots[29].out_uop.prs1_busy connect issue_slots[28].in_uop.bits.ppred, issue_slots[29].out_uop.ppred connect issue_slots[28].in_uop.bits.prs3, issue_slots[29].out_uop.prs3 connect issue_slots[28].in_uop.bits.prs2, issue_slots[29].out_uop.prs2 connect issue_slots[28].in_uop.bits.prs1, issue_slots[29].out_uop.prs1 connect issue_slots[28].in_uop.bits.pdst, issue_slots[29].out_uop.pdst connect issue_slots[28].in_uop.bits.rxq_idx, issue_slots[29].out_uop.rxq_idx connect issue_slots[28].in_uop.bits.stq_idx, issue_slots[29].out_uop.stq_idx connect issue_slots[28].in_uop.bits.ldq_idx, issue_slots[29].out_uop.ldq_idx connect issue_slots[28].in_uop.bits.rob_idx, issue_slots[29].out_uop.rob_idx connect issue_slots[28].in_uop.bits.csr_addr, issue_slots[29].out_uop.csr_addr connect issue_slots[28].in_uop.bits.imm_packed, issue_slots[29].out_uop.imm_packed connect issue_slots[28].in_uop.bits.taken, issue_slots[29].out_uop.taken connect issue_slots[28].in_uop.bits.pc_lob, issue_slots[29].out_uop.pc_lob connect issue_slots[28].in_uop.bits.edge_inst, issue_slots[29].out_uop.edge_inst connect issue_slots[28].in_uop.bits.ftq_idx, issue_slots[29].out_uop.ftq_idx connect issue_slots[28].in_uop.bits.br_tag, issue_slots[29].out_uop.br_tag connect issue_slots[28].in_uop.bits.br_mask, issue_slots[29].out_uop.br_mask connect issue_slots[28].in_uop.bits.is_sfb, issue_slots[29].out_uop.is_sfb connect issue_slots[28].in_uop.bits.is_jal, issue_slots[29].out_uop.is_jal connect issue_slots[28].in_uop.bits.is_jalr, issue_slots[29].out_uop.is_jalr connect issue_slots[28].in_uop.bits.is_br, issue_slots[29].out_uop.is_br connect issue_slots[28].in_uop.bits.iw_p2_poisoned, issue_slots[29].out_uop.iw_p2_poisoned connect issue_slots[28].in_uop.bits.iw_p1_poisoned, issue_slots[29].out_uop.iw_p1_poisoned connect issue_slots[28].in_uop.bits.iw_state, issue_slots[29].out_uop.iw_state connect issue_slots[28].in_uop.bits.ctrl.is_std, issue_slots[29].out_uop.ctrl.is_std connect issue_slots[28].in_uop.bits.ctrl.is_sta, issue_slots[29].out_uop.ctrl.is_sta connect issue_slots[28].in_uop.bits.ctrl.is_load, issue_slots[29].out_uop.ctrl.is_load connect issue_slots[28].in_uop.bits.ctrl.csr_cmd, issue_slots[29].out_uop.ctrl.csr_cmd connect issue_slots[28].in_uop.bits.ctrl.fcn_dw, issue_slots[29].out_uop.ctrl.fcn_dw connect issue_slots[28].in_uop.bits.ctrl.op_fcn, issue_slots[29].out_uop.ctrl.op_fcn connect issue_slots[28].in_uop.bits.ctrl.imm_sel, issue_slots[29].out_uop.ctrl.imm_sel connect issue_slots[28].in_uop.bits.ctrl.op2_sel, issue_slots[29].out_uop.ctrl.op2_sel connect issue_slots[28].in_uop.bits.ctrl.op1_sel, issue_slots[29].out_uop.ctrl.op1_sel connect issue_slots[28].in_uop.bits.ctrl.br_type, issue_slots[29].out_uop.ctrl.br_type connect issue_slots[28].in_uop.bits.fu_code, issue_slots[29].out_uop.fu_code connect issue_slots[28].in_uop.bits.iq_type, issue_slots[29].out_uop.iq_type connect issue_slots[28].in_uop.bits.debug_pc, issue_slots[29].out_uop.debug_pc connect issue_slots[28].in_uop.bits.is_rvc, issue_slots[29].out_uop.is_rvc connect issue_slots[28].in_uop.bits.debug_inst, issue_slots[29].out_uop.debug_inst connect issue_slots[28].in_uop.bits.inst, issue_slots[29].out_uop.inst connect issue_slots[28].in_uop.bits.uopc, issue_slots[29].out_uop.uopc node _T_345 = eq(_WIRE_33, UInt<2>(0h2)) when _T_345 : connect issue_slots[28].in_uop.valid, issue_slots[30].will_be_valid connect issue_slots[28].in_uop.bits.debug_tsrc, issue_slots[30].out_uop.debug_tsrc connect issue_slots[28].in_uop.bits.debug_fsrc, issue_slots[30].out_uop.debug_fsrc connect issue_slots[28].in_uop.bits.bp_xcpt_if, issue_slots[30].out_uop.bp_xcpt_if connect issue_slots[28].in_uop.bits.bp_debug_if, issue_slots[30].out_uop.bp_debug_if connect issue_slots[28].in_uop.bits.xcpt_ma_if, issue_slots[30].out_uop.xcpt_ma_if connect issue_slots[28].in_uop.bits.xcpt_ae_if, issue_slots[30].out_uop.xcpt_ae_if connect issue_slots[28].in_uop.bits.xcpt_pf_if, issue_slots[30].out_uop.xcpt_pf_if connect issue_slots[28].in_uop.bits.fp_single, issue_slots[30].out_uop.fp_single connect issue_slots[28].in_uop.bits.fp_val, issue_slots[30].out_uop.fp_val connect issue_slots[28].in_uop.bits.frs3_en, issue_slots[30].out_uop.frs3_en connect issue_slots[28].in_uop.bits.lrs2_rtype, issue_slots[30].out_uop.lrs2_rtype connect issue_slots[28].in_uop.bits.lrs1_rtype, issue_slots[30].out_uop.lrs1_rtype connect issue_slots[28].in_uop.bits.dst_rtype, issue_slots[30].out_uop.dst_rtype connect issue_slots[28].in_uop.bits.ldst_val, issue_slots[30].out_uop.ldst_val connect issue_slots[28].in_uop.bits.lrs3, issue_slots[30].out_uop.lrs3 connect issue_slots[28].in_uop.bits.lrs2, issue_slots[30].out_uop.lrs2 connect issue_slots[28].in_uop.bits.lrs1, issue_slots[30].out_uop.lrs1 connect issue_slots[28].in_uop.bits.ldst, issue_slots[30].out_uop.ldst connect issue_slots[28].in_uop.bits.ldst_is_rs1, issue_slots[30].out_uop.ldst_is_rs1 connect issue_slots[28].in_uop.bits.flush_on_commit, issue_slots[30].out_uop.flush_on_commit connect issue_slots[28].in_uop.bits.is_unique, issue_slots[30].out_uop.is_unique connect issue_slots[28].in_uop.bits.is_sys_pc2epc, issue_slots[30].out_uop.is_sys_pc2epc connect issue_slots[28].in_uop.bits.uses_stq, issue_slots[30].out_uop.uses_stq connect issue_slots[28].in_uop.bits.uses_ldq, issue_slots[30].out_uop.uses_ldq connect issue_slots[28].in_uop.bits.is_amo, issue_slots[30].out_uop.is_amo connect issue_slots[28].in_uop.bits.is_fencei, issue_slots[30].out_uop.is_fencei connect issue_slots[28].in_uop.bits.is_fence, issue_slots[30].out_uop.is_fence connect issue_slots[28].in_uop.bits.mem_signed, issue_slots[30].out_uop.mem_signed connect issue_slots[28].in_uop.bits.mem_size, issue_slots[30].out_uop.mem_size connect issue_slots[28].in_uop.bits.mem_cmd, issue_slots[30].out_uop.mem_cmd connect issue_slots[28].in_uop.bits.bypassable, issue_slots[30].out_uop.bypassable connect issue_slots[28].in_uop.bits.exc_cause, issue_slots[30].out_uop.exc_cause connect issue_slots[28].in_uop.bits.exception, issue_slots[30].out_uop.exception connect issue_slots[28].in_uop.bits.stale_pdst, issue_slots[30].out_uop.stale_pdst connect issue_slots[28].in_uop.bits.ppred_busy, issue_slots[30].out_uop.ppred_busy connect issue_slots[28].in_uop.bits.prs3_busy, issue_slots[30].out_uop.prs3_busy connect issue_slots[28].in_uop.bits.prs2_busy, issue_slots[30].out_uop.prs2_busy connect issue_slots[28].in_uop.bits.prs1_busy, issue_slots[30].out_uop.prs1_busy connect issue_slots[28].in_uop.bits.ppred, issue_slots[30].out_uop.ppred connect issue_slots[28].in_uop.bits.prs3, issue_slots[30].out_uop.prs3 connect issue_slots[28].in_uop.bits.prs2, issue_slots[30].out_uop.prs2 connect issue_slots[28].in_uop.bits.prs1, issue_slots[30].out_uop.prs1 connect issue_slots[28].in_uop.bits.pdst, issue_slots[30].out_uop.pdst connect issue_slots[28].in_uop.bits.rxq_idx, issue_slots[30].out_uop.rxq_idx connect issue_slots[28].in_uop.bits.stq_idx, issue_slots[30].out_uop.stq_idx connect issue_slots[28].in_uop.bits.ldq_idx, issue_slots[30].out_uop.ldq_idx connect issue_slots[28].in_uop.bits.rob_idx, issue_slots[30].out_uop.rob_idx connect issue_slots[28].in_uop.bits.csr_addr, issue_slots[30].out_uop.csr_addr connect issue_slots[28].in_uop.bits.imm_packed, issue_slots[30].out_uop.imm_packed connect issue_slots[28].in_uop.bits.taken, issue_slots[30].out_uop.taken connect issue_slots[28].in_uop.bits.pc_lob, issue_slots[30].out_uop.pc_lob connect issue_slots[28].in_uop.bits.edge_inst, issue_slots[30].out_uop.edge_inst connect issue_slots[28].in_uop.bits.ftq_idx, issue_slots[30].out_uop.ftq_idx connect issue_slots[28].in_uop.bits.br_tag, issue_slots[30].out_uop.br_tag connect issue_slots[28].in_uop.bits.br_mask, issue_slots[30].out_uop.br_mask connect issue_slots[28].in_uop.bits.is_sfb, issue_slots[30].out_uop.is_sfb connect issue_slots[28].in_uop.bits.is_jal, issue_slots[30].out_uop.is_jal connect issue_slots[28].in_uop.bits.is_jalr, issue_slots[30].out_uop.is_jalr connect issue_slots[28].in_uop.bits.is_br, issue_slots[30].out_uop.is_br connect issue_slots[28].in_uop.bits.iw_p2_poisoned, issue_slots[30].out_uop.iw_p2_poisoned connect issue_slots[28].in_uop.bits.iw_p1_poisoned, issue_slots[30].out_uop.iw_p1_poisoned connect issue_slots[28].in_uop.bits.iw_state, issue_slots[30].out_uop.iw_state connect issue_slots[28].in_uop.bits.ctrl.is_std, issue_slots[30].out_uop.ctrl.is_std connect issue_slots[28].in_uop.bits.ctrl.is_sta, issue_slots[30].out_uop.ctrl.is_sta connect issue_slots[28].in_uop.bits.ctrl.is_load, issue_slots[30].out_uop.ctrl.is_load connect issue_slots[28].in_uop.bits.ctrl.csr_cmd, issue_slots[30].out_uop.ctrl.csr_cmd connect issue_slots[28].in_uop.bits.ctrl.fcn_dw, issue_slots[30].out_uop.ctrl.fcn_dw connect issue_slots[28].in_uop.bits.ctrl.op_fcn, issue_slots[30].out_uop.ctrl.op_fcn connect issue_slots[28].in_uop.bits.ctrl.imm_sel, issue_slots[30].out_uop.ctrl.imm_sel connect issue_slots[28].in_uop.bits.ctrl.op2_sel, issue_slots[30].out_uop.ctrl.op2_sel connect issue_slots[28].in_uop.bits.ctrl.op1_sel, issue_slots[30].out_uop.ctrl.op1_sel connect issue_slots[28].in_uop.bits.ctrl.br_type, issue_slots[30].out_uop.ctrl.br_type connect issue_slots[28].in_uop.bits.fu_code, issue_slots[30].out_uop.fu_code connect issue_slots[28].in_uop.bits.iq_type, issue_slots[30].out_uop.iq_type connect issue_slots[28].in_uop.bits.debug_pc, issue_slots[30].out_uop.debug_pc connect issue_slots[28].in_uop.bits.is_rvc, issue_slots[30].out_uop.is_rvc connect issue_slots[28].in_uop.bits.debug_inst, issue_slots[30].out_uop.debug_inst connect issue_slots[28].in_uop.bits.inst, issue_slots[30].out_uop.inst connect issue_slots[28].in_uop.bits.uopc, issue_slots[30].out_uop.uopc node _T_346 = eq(_WIRE_34, UInt<3>(0h4)) when _T_346 : connect issue_slots[28].in_uop.valid, issue_slots[31].will_be_valid connect issue_slots[28].in_uop.bits.debug_tsrc, issue_slots[31].out_uop.debug_tsrc connect issue_slots[28].in_uop.bits.debug_fsrc, issue_slots[31].out_uop.debug_fsrc connect issue_slots[28].in_uop.bits.bp_xcpt_if, issue_slots[31].out_uop.bp_xcpt_if connect issue_slots[28].in_uop.bits.bp_debug_if, issue_slots[31].out_uop.bp_debug_if connect issue_slots[28].in_uop.bits.xcpt_ma_if, issue_slots[31].out_uop.xcpt_ma_if connect issue_slots[28].in_uop.bits.xcpt_ae_if, issue_slots[31].out_uop.xcpt_ae_if connect issue_slots[28].in_uop.bits.xcpt_pf_if, issue_slots[31].out_uop.xcpt_pf_if connect issue_slots[28].in_uop.bits.fp_single, issue_slots[31].out_uop.fp_single connect issue_slots[28].in_uop.bits.fp_val, issue_slots[31].out_uop.fp_val connect issue_slots[28].in_uop.bits.frs3_en, issue_slots[31].out_uop.frs3_en connect issue_slots[28].in_uop.bits.lrs2_rtype, issue_slots[31].out_uop.lrs2_rtype connect issue_slots[28].in_uop.bits.lrs1_rtype, issue_slots[31].out_uop.lrs1_rtype connect issue_slots[28].in_uop.bits.dst_rtype, issue_slots[31].out_uop.dst_rtype connect issue_slots[28].in_uop.bits.ldst_val, issue_slots[31].out_uop.ldst_val connect issue_slots[28].in_uop.bits.lrs3, issue_slots[31].out_uop.lrs3 connect issue_slots[28].in_uop.bits.lrs2, issue_slots[31].out_uop.lrs2 connect issue_slots[28].in_uop.bits.lrs1, issue_slots[31].out_uop.lrs1 connect issue_slots[28].in_uop.bits.ldst, issue_slots[31].out_uop.ldst connect issue_slots[28].in_uop.bits.ldst_is_rs1, issue_slots[31].out_uop.ldst_is_rs1 connect issue_slots[28].in_uop.bits.flush_on_commit, issue_slots[31].out_uop.flush_on_commit connect issue_slots[28].in_uop.bits.is_unique, issue_slots[31].out_uop.is_unique connect issue_slots[28].in_uop.bits.is_sys_pc2epc, issue_slots[31].out_uop.is_sys_pc2epc connect issue_slots[28].in_uop.bits.uses_stq, issue_slots[31].out_uop.uses_stq connect issue_slots[28].in_uop.bits.uses_ldq, issue_slots[31].out_uop.uses_ldq connect issue_slots[28].in_uop.bits.is_amo, issue_slots[31].out_uop.is_amo connect issue_slots[28].in_uop.bits.is_fencei, issue_slots[31].out_uop.is_fencei connect issue_slots[28].in_uop.bits.is_fence, issue_slots[31].out_uop.is_fence connect issue_slots[28].in_uop.bits.mem_signed, issue_slots[31].out_uop.mem_signed connect issue_slots[28].in_uop.bits.mem_size, issue_slots[31].out_uop.mem_size connect issue_slots[28].in_uop.bits.mem_cmd, issue_slots[31].out_uop.mem_cmd connect issue_slots[28].in_uop.bits.bypassable, issue_slots[31].out_uop.bypassable connect issue_slots[28].in_uop.bits.exc_cause, issue_slots[31].out_uop.exc_cause connect issue_slots[28].in_uop.bits.exception, issue_slots[31].out_uop.exception connect issue_slots[28].in_uop.bits.stale_pdst, issue_slots[31].out_uop.stale_pdst connect issue_slots[28].in_uop.bits.ppred_busy, issue_slots[31].out_uop.ppred_busy connect issue_slots[28].in_uop.bits.prs3_busy, issue_slots[31].out_uop.prs3_busy connect issue_slots[28].in_uop.bits.prs2_busy, issue_slots[31].out_uop.prs2_busy connect issue_slots[28].in_uop.bits.prs1_busy, issue_slots[31].out_uop.prs1_busy connect issue_slots[28].in_uop.bits.ppred, issue_slots[31].out_uop.ppred connect issue_slots[28].in_uop.bits.prs3, issue_slots[31].out_uop.prs3 connect issue_slots[28].in_uop.bits.prs2, issue_slots[31].out_uop.prs2 connect issue_slots[28].in_uop.bits.prs1, issue_slots[31].out_uop.prs1 connect issue_slots[28].in_uop.bits.pdst, issue_slots[31].out_uop.pdst connect issue_slots[28].in_uop.bits.rxq_idx, issue_slots[31].out_uop.rxq_idx connect issue_slots[28].in_uop.bits.stq_idx, issue_slots[31].out_uop.stq_idx connect issue_slots[28].in_uop.bits.ldq_idx, issue_slots[31].out_uop.ldq_idx connect issue_slots[28].in_uop.bits.rob_idx, issue_slots[31].out_uop.rob_idx connect issue_slots[28].in_uop.bits.csr_addr, issue_slots[31].out_uop.csr_addr connect issue_slots[28].in_uop.bits.imm_packed, issue_slots[31].out_uop.imm_packed connect issue_slots[28].in_uop.bits.taken, issue_slots[31].out_uop.taken connect issue_slots[28].in_uop.bits.pc_lob, issue_slots[31].out_uop.pc_lob connect issue_slots[28].in_uop.bits.edge_inst, issue_slots[31].out_uop.edge_inst connect issue_slots[28].in_uop.bits.ftq_idx, issue_slots[31].out_uop.ftq_idx connect issue_slots[28].in_uop.bits.br_tag, issue_slots[31].out_uop.br_tag connect issue_slots[28].in_uop.bits.br_mask, issue_slots[31].out_uop.br_mask connect issue_slots[28].in_uop.bits.is_sfb, issue_slots[31].out_uop.is_sfb connect issue_slots[28].in_uop.bits.is_jal, issue_slots[31].out_uop.is_jal connect issue_slots[28].in_uop.bits.is_jalr, issue_slots[31].out_uop.is_jalr connect issue_slots[28].in_uop.bits.is_br, issue_slots[31].out_uop.is_br connect issue_slots[28].in_uop.bits.iw_p2_poisoned, issue_slots[31].out_uop.iw_p2_poisoned connect issue_slots[28].in_uop.bits.iw_p1_poisoned, issue_slots[31].out_uop.iw_p1_poisoned connect issue_slots[28].in_uop.bits.iw_state, issue_slots[31].out_uop.iw_state connect issue_slots[28].in_uop.bits.ctrl.is_std, issue_slots[31].out_uop.ctrl.is_std connect issue_slots[28].in_uop.bits.ctrl.is_sta, issue_slots[31].out_uop.ctrl.is_sta connect issue_slots[28].in_uop.bits.ctrl.is_load, issue_slots[31].out_uop.ctrl.is_load connect issue_slots[28].in_uop.bits.ctrl.csr_cmd, issue_slots[31].out_uop.ctrl.csr_cmd connect issue_slots[28].in_uop.bits.ctrl.fcn_dw, issue_slots[31].out_uop.ctrl.fcn_dw connect issue_slots[28].in_uop.bits.ctrl.op_fcn, issue_slots[31].out_uop.ctrl.op_fcn connect issue_slots[28].in_uop.bits.ctrl.imm_sel, issue_slots[31].out_uop.ctrl.imm_sel connect issue_slots[28].in_uop.bits.ctrl.op2_sel, issue_slots[31].out_uop.ctrl.op2_sel connect issue_slots[28].in_uop.bits.ctrl.op1_sel, issue_slots[31].out_uop.ctrl.op1_sel connect issue_slots[28].in_uop.bits.ctrl.br_type, issue_slots[31].out_uop.ctrl.br_type connect issue_slots[28].in_uop.bits.fu_code, issue_slots[31].out_uop.fu_code connect issue_slots[28].in_uop.bits.iq_type, issue_slots[31].out_uop.iq_type connect issue_slots[28].in_uop.bits.debug_pc, issue_slots[31].out_uop.debug_pc connect issue_slots[28].in_uop.bits.is_rvc, issue_slots[31].out_uop.is_rvc connect issue_slots[28].in_uop.bits.debug_inst, issue_slots[31].out_uop.debug_inst connect issue_slots[28].in_uop.bits.inst, issue_slots[31].out_uop.inst connect issue_slots[28].in_uop.bits.uopc, issue_slots[31].out_uop.uopc node _issue_slots_28_clear_T = neq(_WIRE_31, UInt<1>(0h0)) connect issue_slots[28].clear, _issue_slots_28_clear_T connect issue_slots[29].in_uop.valid, UInt<1>(0h0) connect issue_slots[29].in_uop.bits.debug_tsrc, issue_slots[30].out_uop.debug_tsrc connect issue_slots[29].in_uop.bits.debug_fsrc, issue_slots[30].out_uop.debug_fsrc connect issue_slots[29].in_uop.bits.bp_xcpt_if, issue_slots[30].out_uop.bp_xcpt_if connect issue_slots[29].in_uop.bits.bp_debug_if, issue_slots[30].out_uop.bp_debug_if connect issue_slots[29].in_uop.bits.xcpt_ma_if, issue_slots[30].out_uop.xcpt_ma_if connect issue_slots[29].in_uop.bits.xcpt_ae_if, issue_slots[30].out_uop.xcpt_ae_if connect issue_slots[29].in_uop.bits.xcpt_pf_if, issue_slots[30].out_uop.xcpt_pf_if connect issue_slots[29].in_uop.bits.fp_single, issue_slots[30].out_uop.fp_single connect issue_slots[29].in_uop.bits.fp_val, issue_slots[30].out_uop.fp_val connect issue_slots[29].in_uop.bits.frs3_en, issue_slots[30].out_uop.frs3_en connect issue_slots[29].in_uop.bits.lrs2_rtype, issue_slots[30].out_uop.lrs2_rtype connect issue_slots[29].in_uop.bits.lrs1_rtype, issue_slots[30].out_uop.lrs1_rtype connect issue_slots[29].in_uop.bits.dst_rtype, issue_slots[30].out_uop.dst_rtype connect issue_slots[29].in_uop.bits.ldst_val, issue_slots[30].out_uop.ldst_val connect issue_slots[29].in_uop.bits.lrs3, issue_slots[30].out_uop.lrs3 connect issue_slots[29].in_uop.bits.lrs2, issue_slots[30].out_uop.lrs2 connect issue_slots[29].in_uop.bits.lrs1, issue_slots[30].out_uop.lrs1 connect issue_slots[29].in_uop.bits.ldst, issue_slots[30].out_uop.ldst connect issue_slots[29].in_uop.bits.ldst_is_rs1, issue_slots[30].out_uop.ldst_is_rs1 connect issue_slots[29].in_uop.bits.flush_on_commit, issue_slots[30].out_uop.flush_on_commit connect issue_slots[29].in_uop.bits.is_unique, issue_slots[30].out_uop.is_unique connect issue_slots[29].in_uop.bits.is_sys_pc2epc, issue_slots[30].out_uop.is_sys_pc2epc connect issue_slots[29].in_uop.bits.uses_stq, issue_slots[30].out_uop.uses_stq connect issue_slots[29].in_uop.bits.uses_ldq, issue_slots[30].out_uop.uses_ldq connect issue_slots[29].in_uop.bits.is_amo, issue_slots[30].out_uop.is_amo connect issue_slots[29].in_uop.bits.is_fencei, issue_slots[30].out_uop.is_fencei connect issue_slots[29].in_uop.bits.is_fence, issue_slots[30].out_uop.is_fence connect issue_slots[29].in_uop.bits.mem_signed, issue_slots[30].out_uop.mem_signed connect issue_slots[29].in_uop.bits.mem_size, issue_slots[30].out_uop.mem_size connect issue_slots[29].in_uop.bits.mem_cmd, issue_slots[30].out_uop.mem_cmd connect issue_slots[29].in_uop.bits.bypassable, issue_slots[30].out_uop.bypassable connect issue_slots[29].in_uop.bits.exc_cause, issue_slots[30].out_uop.exc_cause connect issue_slots[29].in_uop.bits.exception, issue_slots[30].out_uop.exception connect issue_slots[29].in_uop.bits.stale_pdst, issue_slots[30].out_uop.stale_pdst connect issue_slots[29].in_uop.bits.ppred_busy, issue_slots[30].out_uop.ppred_busy connect issue_slots[29].in_uop.bits.prs3_busy, issue_slots[30].out_uop.prs3_busy connect issue_slots[29].in_uop.bits.prs2_busy, issue_slots[30].out_uop.prs2_busy connect issue_slots[29].in_uop.bits.prs1_busy, issue_slots[30].out_uop.prs1_busy connect issue_slots[29].in_uop.bits.ppred, issue_slots[30].out_uop.ppred connect issue_slots[29].in_uop.bits.prs3, issue_slots[30].out_uop.prs3 connect issue_slots[29].in_uop.bits.prs2, issue_slots[30].out_uop.prs2 connect issue_slots[29].in_uop.bits.prs1, issue_slots[30].out_uop.prs1 connect issue_slots[29].in_uop.bits.pdst, issue_slots[30].out_uop.pdst connect issue_slots[29].in_uop.bits.rxq_idx, issue_slots[30].out_uop.rxq_idx connect issue_slots[29].in_uop.bits.stq_idx, issue_slots[30].out_uop.stq_idx connect issue_slots[29].in_uop.bits.ldq_idx, issue_slots[30].out_uop.ldq_idx connect issue_slots[29].in_uop.bits.rob_idx, issue_slots[30].out_uop.rob_idx connect issue_slots[29].in_uop.bits.csr_addr, issue_slots[30].out_uop.csr_addr connect issue_slots[29].in_uop.bits.imm_packed, issue_slots[30].out_uop.imm_packed connect issue_slots[29].in_uop.bits.taken, issue_slots[30].out_uop.taken connect issue_slots[29].in_uop.bits.pc_lob, issue_slots[30].out_uop.pc_lob connect issue_slots[29].in_uop.bits.edge_inst, issue_slots[30].out_uop.edge_inst connect issue_slots[29].in_uop.bits.ftq_idx, issue_slots[30].out_uop.ftq_idx connect issue_slots[29].in_uop.bits.br_tag, issue_slots[30].out_uop.br_tag connect issue_slots[29].in_uop.bits.br_mask, issue_slots[30].out_uop.br_mask connect issue_slots[29].in_uop.bits.is_sfb, issue_slots[30].out_uop.is_sfb connect issue_slots[29].in_uop.bits.is_jal, issue_slots[30].out_uop.is_jal connect issue_slots[29].in_uop.bits.is_jalr, issue_slots[30].out_uop.is_jalr connect issue_slots[29].in_uop.bits.is_br, issue_slots[30].out_uop.is_br connect issue_slots[29].in_uop.bits.iw_p2_poisoned, issue_slots[30].out_uop.iw_p2_poisoned connect issue_slots[29].in_uop.bits.iw_p1_poisoned, issue_slots[30].out_uop.iw_p1_poisoned connect issue_slots[29].in_uop.bits.iw_state, issue_slots[30].out_uop.iw_state connect issue_slots[29].in_uop.bits.ctrl.is_std, issue_slots[30].out_uop.ctrl.is_std connect issue_slots[29].in_uop.bits.ctrl.is_sta, issue_slots[30].out_uop.ctrl.is_sta connect issue_slots[29].in_uop.bits.ctrl.is_load, issue_slots[30].out_uop.ctrl.is_load connect issue_slots[29].in_uop.bits.ctrl.csr_cmd, issue_slots[30].out_uop.ctrl.csr_cmd connect issue_slots[29].in_uop.bits.ctrl.fcn_dw, issue_slots[30].out_uop.ctrl.fcn_dw connect issue_slots[29].in_uop.bits.ctrl.op_fcn, issue_slots[30].out_uop.ctrl.op_fcn connect issue_slots[29].in_uop.bits.ctrl.imm_sel, issue_slots[30].out_uop.ctrl.imm_sel connect issue_slots[29].in_uop.bits.ctrl.op2_sel, issue_slots[30].out_uop.ctrl.op2_sel connect issue_slots[29].in_uop.bits.ctrl.op1_sel, issue_slots[30].out_uop.ctrl.op1_sel connect issue_slots[29].in_uop.bits.ctrl.br_type, issue_slots[30].out_uop.ctrl.br_type connect issue_slots[29].in_uop.bits.fu_code, issue_slots[30].out_uop.fu_code connect issue_slots[29].in_uop.bits.iq_type, issue_slots[30].out_uop.iq_type connect issue_slots[29].in_uop.bits.debug_pc, issue_slots[30].out_uop.debug_pc connect issue_slots[29].in_uop.bits.is_rvc, issue_slots[30].out_uop.is_rvc connect issue_slots[29].in_uop.bits.debug_inst, issue_slots[30].out_uop.debug_inst connect issue_slots[29].in_uop.bits.inst, issue_slots[30].out_uop.inst connect issue_slots[29].in_uop.bits.uopc, issue_slots[30].out_uop.uopc node _T_347 = eq(_WIRE_33, UInt<1>(0h1)) when _T_347 : connect issue_slots[29].in_uop.valid, issue_slots[30].will_be_valid connect issue_slots[29].in_uop.bits.debug_tsrc, issue_slots[30].out_uop.debug_tsrc connect issue_slots[29].in_uop.bits.debug_fsrc, issue_slots[30].out_uop.debug_fsrc connect issue_slots[29].in_uop.bits.bp_xcpt_if, issue_slots[30].out_uop.bp_xcpt_if connect issue_slots[29].in_uop.bits.bp_debug_if, issue_slots[30].out_uop.bp_debug_if connect issue_slots[29].in_uop.bits.xcpt_ma_if, issue_slots[30].out_uop.xcpt_ma_if connect issue_slots[29].in_uop.bits.xcpt_ae_if, issue_slots[30].out_uop.xcpt_ae_if connect issue_slots[29].in_uop.bits.xcpt_pf_if, issue_slots[30].out_uop.xcpt_pf_if connect issue_slots[29].in_uop.bits.fp_single, issue_slots[30].out_uop.fp_single connect issue_slots[29].in_uop.bits.fp_val, issue_slots[30].out_uop.fp_val connect issue_slots[29].in_uop.bits.frs3_en, issue_slots[30].out_uop.frs3_en connect issue_slots[29].in_uop.bits.lrs2_rtype, issue_slots[30].out_uop.lrs2_rtype connect issue_slots[29].in_uop.bits.lrs1_rtype, issue_slots[30].out_uop.lrs1_rtype connect issue_slots[29].in_uop.bits.dst_rtype, issue_slots[30].out_uop.dst_rtype connect issue_slots[29].in_uop.bits.ldst_val, issue_slots[30].out_uop.ldst_val connect issue_slots[29].in_uop.bits.lrs3, issue_slots[30].out_uop.lrs3 connect issue_slots[29].in_uop.bits.lrs2, issue_slots[30].out_uop.lrs2 connect issue_slots[29].in_uop.bits.lrs1, issue_slots[30].out_uop.lrs1 connect issue_slots[29].in_uop.bits.ldst, issue_slots[30].out_uop.ldst connect issue_slots[29].in_uop.bits.ldst_is_rs1, issue_slots[30].out_uop.ldst_is_rs1 connect issue_slots[29].in_uop.bits.flush_on_commit, issue_slots[30].out_uop.flush_on_commit connect issue_slots[29].in_uop.bits.is_unique, issue_slots[30].out_uop.is_unique connect issue_slots[29].in_uop.bits.is_sys_pc2epc, issue_slots[30].out_uop.is_sys_pc2epc connect issue_slots[29].in_uop.bits.uses_stq, issue_slots[30].out_uop.uses_stq connect issue_slots[29].in_uop.bits.uses_ldq, issue_slots[30].out_uop.uses_ldq connect issue_slots[29].in_uop.bits.is_amo, issue_slots[30].out_uop.is_amo connect issue_slots[29].in_uop.bits.is_fencei, issue_slots[30].out_uop.is_fencei connect issue_slots[29].in_uop.bits.is_fence, issue_slots[30].out_uop.is_fence connect issue_slots[29].in_uop.bits.mem_signed, issue_slots[30].out_uop.mem_signed connect issue_slots[29].in_uop.bits.mem_size, issue_slots[30].out_uop.mem_size connect issue_slots[29].in_uop.bits.mem_cmd, issue_slots[30].out_uop.mem_cmd connect issue_slots[29].in_uop.bits.bypassable, issue_slots[30].out_uop.bypassable connect issue_slots[29].in_uop.bits.exc_cause, issue_slots[30].out_uop.exc_cause connect issue_slots[29].in_uop.bits.exception, issue_slots[30].out_uop.exception connect issue_slots[29].in_uop.bits.stale_pdst, issue_slots[30].out_uop.stale_pdst connect issue_slots[29].in_uop.bits.ppred_busy, issue_slots[30].out_uop.ppred_busy connect issue_slots[29].in_uop.bits.prs3_busy, issue_slots[30].out_uop.prs3_busy connect issue_slots[29].in_uop.bits.prs2_busy, issue_slots[30].out_uop.prs2_busy connect issue_slots[29].in_uop.bits.prs1_busy, issue_slots[30].out_uop.prs1_busy connect issue_slots[29].in_uop.bits.ppred, issue_slots[30].out_uop.ppred connect issue_slots[29].in_uop.bits.prs3, issue_slots[30].out_uop.prs3 connect issue_slots[29].in_uop.bits.prs2, issue_slots[30].out_uop.prs2 connect issue_slots[29].in_uop.bits.prs1, issue_slots[30].out_uop.prs1 connect issue_slots[29].in_uop.bits.pdst, issue_slots[30].out_uop.pdst connect issue_slots[29].in_uop.bits.rxq_idx, issue_slots[30].out_uop.rxq_idx connect issue_slots[29].in_uop.bits.stq_idx, issue_slots[30].out_uop.stq_idx connect issue_slots[29].in_uop.bits.ldq_idx, issue_slots[30].out_uop.ldq_idx connect issue_slots[29].in_uop.bits.rob_idx, issue_slots[30].out_uop.rob_idx connect issue_slots[29].in_uop.bits.csr_addr, issue_slots[30].out_uop.csr_addr connect issue_slots[29].in_uop.bits.imm_packed, issue_slots[30].out_uop.imm_packed connect issue_slots[29].in_uop.bits.taken, issue_slots[30].out_uop.taken connect issue_slots[29].in_uop.bits.pc_lob, issue_slots[30].out_uop.pc_lob connect issue_slots[29].in_uop.bits.edge_inst, issue_slots[30].out_uop.edge_inst connect issue_slots[29].in_uop.bits.ftq_idx, issue_slots[30].out_uop.ftq_idx connect issue_slots[29].in_uop.bits.br_tag, issue_slots[30].out_uop.br_tag connect issue_slots[29].in_uop.bits.br_mask, issue_slots[30].out_uop.br_mask connect issue_slots[29].in_uop.bits.is_sfb, issue_slots[30].out_uop.is_sfb connect issue_slots[29].in_uop.bits.is_jal, issue_slots[30].out_uop.is_jal connect issue_slots[29].in_uop.bits.is_jalr, issue_slots[30].out_uop.is_jalr connect issue_slots[29].in_uop.bits.is_br, issue_slots[30].out_uop.is_br connect issue_slots[29].in_uop.bits.iw_p2_poisoned, issue_slots[30].out_uop.iw_p2_poisoned connect issue_slots[29].in_uop.bits.iw_p1_poisoned, issue_slots[30].out_uop.iw_p1_poisoned connect issue_slots[29].in_uop.bits.iw_state, issue_slots[30].out_uop.iw_state connect issue_slots[29].in_uop.bits.ctrl.is_std, issue_slots[30].out_uop.ctrl.is_std connect issue_slots[29].in_uop.bits.ctrl.is_sta, issue_slots[30].out_uop.ctrl.is_sta connect issue_slots[29].in_uop.bits.ctrl.is_load, issue_slots[30].out_uop.ctrl.is_load connect issue_slots[29].in_uop.bits.ctrl.csr_cmd, issue_slots[30].out_uop.ctrl.csr_cmd connect issue_slots[29].in_uop.bits.ctrl.fcn_dw, issue_slots[30].out_uop.ctrl.fcn_dw connect issue_slots[29].in_uop.bits.ctrl.op_fcn, issue_slots[30].out_uop.ctrl.op_fcn connect issue_slots[29].in_uop.bits.ctrl.imm_sel, issue_slots[30].out_uop.ctrl.imm_sel connect issue_slots[29].in_uop.bits.ctrl.op2_sel, issue_slots[30].out_uop.ctrl.op2_sel connect issue_slots[29].in_uop.bits.ctrl.op1_sel, issue_slots[30].out_uop.ctrl.op1_sel connect issue_slots[29].in_uop.bits.ctrl.br_type, issue_slots[30].out_uop.ctrl.br_type connect issue_slots[29].in_uop.bits.fu_code, issue_slots[30].out_uop.fu_code connect issue_slots[29].in_uop.bits.iq_type, issue_slots[30].out_uop.iq_type connect issue_slots[29].in_uop.bits.debug_pc, issue_slots[30].out_uop.debug_pc connect issue_slots[29].in_uop.bits.is_rvc, issue_slots[30].out_uop.is_rvc connect issue_slots[29].in_uop.bits.debug_inst, issue_slots[30].out_uop.debug_inst connect issue_slots[29].in_uop.bits.inst, issue_slots[30].out_uop.inst connect issue_slots[29].in_uop.bits.uopc, issue_slots[30].out_uop.uopc node _T_348 = eq(_WIRE_34, UInt<2>(0h2)) when _T_348 : connect issue_slots[29].in_uop.valid, issue_slots[31].will_be_valid connect issue_slots[29].in_uop.bits.debug_tsrc, issue_slots[31].out_uop.debug_tsrc connect issue_slots[29].in_uop.bits.debug_fsrc, issue_slots[31].out_uop.debug_fsrc connect issue_slots[29].in_uop.bits.bp_xcpt_if, issue_slots[31].out_uop.bp_xcpt_if connect issue_slots[29].in_uop.bits.bp_debug_if, issue_slots[31].out_uop.bp_debug_if connect issue_slots[29].in_uop.bits.xcpt_ma_if, issue_slots[31].out_uop.xcpt_ma_if connect issue_slots[29].in_uop.bits.xcpt_ae_if, issue_slots[31].out_uop.xcpt_ae_if connect issue_slots[29].in_uop.bits.xcpt_pf_if, issue_slots[31].out_uop.xcpt_pf_if connect issue_slots[29].in_uop.bits.fp_single, issue_slots[31].out_uop.fp_single connect issue_slots[29].in_uop.bits.fp_val, issue_slots[31].out_uop.fp_val connect issue_slots[29].in_uop.bits.frs3_en, issue_slots[31].out_uop.frs3_en connect issue_slots[29].in_uop.bits.lrs2_rtype, issue_slots[31].out_uop.lrs2_rtype connect issue_slots[29].in_uop.bits.lrs1_rtype, issue_slots[31].out_uop.lrs1_rtype connect issue_slots[29].in_uop.bits.dst_rtype, issue_slots[31].out_uop.dst_rtype connect issue_slots[29].in_uop.bits.ldst_val, issue_slots[31].out_uop.ldst_val connect issue_slots[29].in_uop.bits.lrs3, issue_slots[31].out_uop.lrs3 connect issue_slots[29].in_uop.bits.lrs2, issue_slots[31].out_uop.lrs2 connect issue_slots[29].in_uop.bits.lrs1, issue_slots[31].out_uop.lrs1 connect issue_slots[29].in_uop.bits.ldst, issue_slots[31].out_uop.ldst connect issue_slots[29].in_uop.bits.ldst_is_rs1, issue_slots[31].out_uop.ldst_is_rs1 connect issue_slots[29].in_uop.bits.flush_on_commit, issue_slots[31].out_uop.flush_on_commit connect issue_slots[29].in_uop.bits.is_unique, issue_slots[31].out_uop.is_unique connect issue_slots[29].in_uop.bits.is_sys_pc2epc, issue_slots[31].out_uop.is_sys_pc2epc connect issue_slots[29].in_uop.bits.uses_stq, issue_slots[31].out_uop.uses_stq connect issue_slots[29].in_uop.bits.uses_ldq, issue_slots[31].out_uop.uses_ldq connect issue_slots[29].in_uop.bits.is_amo, issue_slots[31].out_uop.is_amo connect issue_slots[29].in_uop.bits.is_fencei, issue_slots[31].out_uop.is_fencei connect issue_slots[29].in_uop.bits.is_fence, issue_slots[31].out_uop.is_fence connect issue_slots[29].in_uop.bits.mem_signed, issue_slots[31].out_uop.mem_signed connect issue_slots[29].in_uop.bits.mem_size, issue_slots[31].out_uop.mem_size connect issue_slots[29].in_uop.bits.mem_cmd, issue_slots[31].out_uop.mem_cmd connect issue_slots[29].in_uop.bits.bypassable, issue_slots[31].out_uop.bypassable connect issue_slots[29].in_uop.bits.exc_cause, issue_slots[31].out_uop.exc_cause connect issue_slots[29].in_uop.bits.exception, issue_slots[31].out_uop.exception connect issue_slots[29].in_uop.bits.stale_pdst, issue_slots[31].out_uop.stale_pdst connect issue_slots[29].in_uop.bits.ppred_busy, issue_slots[31].out_uop.ppred_busy connect issue_slots[29].in_uop.bits.prs3_busy, issue_slots[31].out_uop.prs3_busy connect issue_slots[29].in_uop.bits.prs2_busy, issue_slots[31].out_uop.prs2_busy connect issue_slots[29].in_uop.bits.prs1_busy, issue_slots[31].out_uop.prs1_busy connect issue_slots[29].in_uop.bits.ppred, issue_slots[31].out_uop.ppred connect issue_slots[29].in_uop.bits.prs3, issue_slots[31].out_uop.prs3 connect issue_slots[29].in_uop.bits.prs2, issue_slots[31].out_uop.prs2 connect issue_slots[29].in_uop.bits.prs1, issue_slots[31].out_uop.prs1 connect issue_slots[29].in_uop.bits.pdst, issue_slots[31].out_uop.pdst connect issue_slots[29].in_uop.bits.rxq_idx, issue_slots[31].out_uop.rxq_idx connect issue_slots[29].in_uop.bits.stq_idx, issue_slots[31].out_uop.stq_idx connect issue_slots[29].in_uop.bits.ldq_idx, issue_slots[31].out_uop.ldq_idx connect issue_slots[29].in_uop.bits.rob_idx, issue_slots[31].out_uop.rob_idx connect issue_slots[29].in_uop.bits.csr_addr, issue_slots[31].out_uop.csr_addr connect issue_slots[29].in_uop.bits.imm_packed, issue_slots[31].out_uop.imm_packed connect issue_slots[29].in_uop.bits.taken, issue_slots[31].out_uop.taken connect issue_slots[29].in_uop.bits.pc_lob, issue_slots[31].out_uop.pc_lob connect issue_slots[29].in_uop.bits.edge_inst, issue_slots[31].out_uop.edge_inst connect issue_slots[29].in_uop.bits.ftq_idx, issue_slots[31].out_uop.ftq_idx connect issue_slots[29].in_uop.bits.br_tag, issue_slots[31].out_uop.br_tag connect issue_slots[29].in_uop.bits.br_mask, issue_slots[31].out_uop.br_mask connect issue_slots[29].in_uop.bits.is_sfb, issue_slots[31].out_uop.is_sfb connect issue_slots[29].in_uop.bits.is_jal, issue_slots[31].out_uop.is_jal connect issue_slots[29].in_uop.bits.is_jalr, issue_slots[31].out_uop.is_jalr connect issue_slots[29].in_uop.bits.is_br, issue_slots[31].out_uop.is_br connect issue_slots[29].in_uop.bits.iw_p2_poisoned, issue_slots[31].out_uop.iw_p2_poisoned connect issue_slots[29].in_uop.bits.iw_p1_poisoned, issue_slots[31].out_uop.iw_p1_poisoned connect issue_slots[29].in_uop.bits.iw_state, issue_slots[31].out_uop.iw_state connect issue_slots[29].in_uop.bits.ctrl.is_std, issue_slots[31].out_uop.ctrl.is_std connect issue_slots[29].in_uop.bits.ctrl.is_sta, issue_slots[31].out_uop.ctrl.is_sta connect issue_slots[29].in_uop.bits.ctrl.is_load, issue_slots[31].out_uop.ctrl.is_load connect issue_slots[29].in_uop.bits.ctrl.csr_cmd, issue_slots[31].out_uop.ctrl.csr_cmd connect issue_slots[29].in_uop.bits.ctrl.fcn_dw, issue_slots[31].out_uop.ctrl.fcn_dw connect issue_slots[29].in_uop.bits.ctrl.op_fcn, issue_slots[31].out_uop.ctrl.op_fcn connect issue_slots[29].in_uop.bits.ctrl.imm_sel, issue_slots[31].out_uop.ctrl.imm_sel connect issue_slots[29].in_uop.bits.ctrl.op2_sel, issue_slots[31].out_uop.ctrl.op2_sel connect issue_slots[29].in_uop.bits.ctrl.op1_sel, issue_slots[31].out_uop.ctrl.op1_sel connect issue_slots[29].in_uop.bits.ctrl.br_type, issue_slots[31].out_uop.ctrl.br_type connect issue_slots[29].in_uop.bits.fu_code, issue_slots[31].out_uop.fu_code connect issue_slots[29].in_uop.bits.iq_type, issue_slots[31].out_uop.iq_type connect issue_slots[29].in_uop.bits.debug_pc, issue_slots[31].out_uop.debug_pc connect issue_slots[29].in_uop.bits.is_rvc, issue_slots[31].out_uop.is_rvc connect issue_slots[29].in_uop.bits.debug_inst, issue_slots[31].out_uop.debug_inst connect issue_slots[29].in_uop.bits.inst, issue_slots[31].out_uop.inst connect issue_slots[29].in_uop.bits.uopc, issue_slots[31].out_uop.uopc node _T_349 = eq(_WIRE_35, UInt<3>(0h4)) when _T_349 : connect issue_slots[29].in_uop.valid, will_be_valid_32 connect issue_slots[29].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[29].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[29].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[29].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[29].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[29].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[29].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[29].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[29].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[29].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[29].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[29].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[29].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[29].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[29].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[29].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[29].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[29].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[29].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[29].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[29].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[29].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[29].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[29].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[29].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[29].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[29].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[29].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[29].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[29].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[29].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[29].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[29].in_uop.bits.exception, _WIRE.exception connect issue_slots[29].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[29].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[29].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[29].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[29].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[29].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[29].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[29].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[29].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[29].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[29].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[29].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[29].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[29].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[29].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[29].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[29].in_uop.bits.taken, _WIRE.taken connect issue_slots[29].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[29].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[29].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[29].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[29].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[29].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[29].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[29].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[29].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[29].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[29].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[29].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[29].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[29].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[29].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[29].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[29].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[29].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[29].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[29].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[29].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[29].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[29].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[29].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[29].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[29].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[29].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[29].in_uop.bits.inst, _WIRE.inst connect issue_slots[29].in_uop.bits.uopc, _WIRE.uopc node _issue_slots_29_clear_T = neq(_WIRE_32, UInt<1>(0h0)) connect issue_slots[29].clear, _issue_slots_29_clear_T connect issue_slots[30].in_uop.valid, UInt<1>(0h0) connect issue_slots[30].in_uop.bits.debug_tsrc, issue_slots[31].out_uop.debug_tsrc connect issue_slots[30].in_uop.bits.debug_fsrc, issue_slots[31].out_uop.debug_fsrc connect issue_slots[30].in_uop.bits.bp_xcpt_if, issue_slots[31].out_uop.bp_xcpt_if connect issue_slots[30].in_uop.bits.bp_debug_if, issue_slots[31].out_uop.bp_debug_if connect issue_slots[30].in_uop.bits.xcpt_ma_if, issue_slots[31].out_uop.xcpt_ma_if connect issue_slots[30].in_uop.bits.xcpt_ae_if, issue_slots[31].out_uop.xcpt_ae_if connect issue_slots[30].in_uop.bits.xcpt_pf_if, issue_slots[31].out_uop.xcpt_pf_if connect issue_slots[30].in_uop.bits.fp_single, issue_slots[31].out_uop.fp_single connect issue_slots[30].in_uop.bits.fp_val, issue_slots[31].out_uop.fp_val connect issue_slots[30].in_uop.bits.frs3_en, issue_slots[31].out_uop.frs3_en connect issue_slots[30].in_uop.bits.lrs2_rtype, issue_slots[31].out_uop.lrs2_rtype connect issue_slots[30].in_uop.bits.lrs1_rtype, issue_slots[31].out_uop.lrs1_rtype connect issue_slots[30].in_uop.bits.dst_rtype, issue_slots[31].out_uop.dst_rtype connect issue_slots[30].in_uop.bits.ldst_val, issue_slots[31].out_uop.ldst_val connect issue_slots[30].in_uop.bits.lrs3, issue_slots[31].out_uop.lrs3 connect issue_slots[30].in_uop.bits.lrs2, issue_slots[31].out_uop.lrs2 connect issue_slots[30].in_uop.bits.lrs1, issue_slots[31].out_uop.lrs1 connect issue_slots[30].in_uop.bits.ldst, issue_slots[31].out_uop.ldst connect issue_slots[30].in_uop.bits.ldst_is_rs1, issue_slots[31].out_uop.ldst_is_rs1 connect issue_slots[30].in_uop.bits.flush_on_commit, issue_slots[31].out_uop.flush_on_commit connect issue_slots[30].in_uop.bits.is_unique, issue_slots[31].out_uop.is_unique connect issue_slots[30].in_uop.bits.is_sys_pc2epc, issue_slots[31].out_uop.is_sys_pc2epc connect issue_slots[30].in_uop.bits.uses_stq, issue_slots[31].out_uop.uses_stq connect issue_slots[30].in_uop.bits.uses_ldq, issue_slots[31].out_uop.uses_ldq connect issue_slots[30].in_uop.bits.is_amo, issue_slots[31].out_uop.is_amo connect issue_slots[30].in_uop.bits.is_fencei, issue_slots[31].out_uop.is_fencei connect issue_slots[30].in_uop.bits.is_fence, issue_slots[31].out_uop.is_fence connect issue_slots[30].in_uop.bits.mem_signed, issue_slots[31].out_uop.mem_signed connect issue_slots[30].in_uop.bits.mem_size, issue_slots[31].out_uop.mem_size connect issue_slots[30].in_uop.bits.mem_cmd, issue_slots[31].out_uop.mem_cmd connect issue_slots[30].in_uop.bits.bypassable, issue_slots[31].out_uop.bypassable connect issue_slots[30].in_uop.bits.exc_cause, issue_slots[31].out_uop.exc_cause connect issue_slots[30].in_uop.bits.exception, issue_slots[31].out_uop.exception connect issue_slots[30].in_uop.bits.stale_pdst, issue_slots[31].out_uop.stale_pdst connect issue_slots[30].in_uop.bits.ppred_busy, issue_slots[31].out_uop.ppred_busy connect issue_slots[30].in_uop.bits.prs3_busy, issue_slots[31].out_uop.prs3_busy connect issue_slots[30].in_uop.bits.prs2_busy, issue_slots[31].out_uop.prs2_busy connect issue_slots[30].in_uop.bits.prs1_busy, issue_slots[31].out_uop.prs1_busy connect issue_slots[30].in_uop.bits.ppred, issue_slots[31].out_uop.ppred connect issue_slots[30].in_uop.bits.prs3, issue_slots[31].out_uop.prs3 connect issue_slots[30].in_uop.bits.prs2, issue_slots[31].out_uop.prs2 connect issue_slots[30].in_uop.bits.prs1, issue_slots[31].out_uop.prs1 connect issue_slots[30].in_uop.bits.pdst, issue_slots[31].out_uop.pdst connect issue_slots[30].in_uop.bits.rxq_idx, issue_slots[31].out_uop.rxq_idx connect issue_slots[30].in_uop.bits.stq_idx, issue_slots[31].out_uop.stq_idx connect issue_slots[30].in_uop.bits.ldq_idx, issue_slots[31].out_uop.ldq_idx connect issue_slots[30].in_uop.bits.rob_idx, issue_slots[31].out_uop.rob_idx connect issue_slots[30].in_uop.bits.csr_addr, issue_slots[31].out_uop.csr_addr connect issue_slots[30].in_uop.bits.imm_packed, issue_slots[31].out_uop.imm_packed connect issue_slots[30].in_uop.bits.taken, issue_slots[31].out_uop.taken connect issue_slots[30].in_uop.bits.pc_lob, issue_slots[31].out_uop.pc_lob connect issue_slots[30].in_uop.bits.edge_inst, issue_slots[31].out_uop.edge_inst connect issue_slots[30].in_uop.bits.ftq_idx, issue_slots[31].out_uop.ftq_idx connect issue_slots[30].in_uop.bits.br_tag, issue_slots[31].out_uop.br_tag connect issue_slots[30].in_uop.bits.br_mask, issue_slots[31].out_uop.br_mask connect issue_slots[30].in_uop.bits.is_sfb, issue_slots[31].out_uop.is_sfb connect issue_slots[30].in_uop.bits.is_jal, issue_slots[31].out_uop.is_jal connect issue_slots[30].in_uop.bits.is_jalr, issue_slots[31].out_uop.is_jalr connect issue_slots[30].in_uop.bits.is_br, issue_slots[31].out_uop.is_br connect issue_slots[30].in_uop.bits.iw_p2_poisoned, issue_slots[31].out_uop.iw_p2_poisoned connect issue_slots[30].in_uop.bits.iw_p1_poisoned, issue_slots[31].out_uop.iw_p1_poisoned connect issue_slots[30].in_uop.bits.iw_state, issue_slots[31].out_uop.iw_state connect issue_slots[30].in_uop.bits.ctrl.is_std, issue_slots[31].out_uop.ctrl.is_std connect issue_slots[30].in_uop.bits.ctrl.is_sta, issue_slots[31].out_uop.ctrl.is_sta connect issue_slots[30].in_uop.bits.ctrl.is_load, issue_slots[31].out_uop.ctrl.is_load connect issue_slots[30].in_uop.bits.ctrl.csr_cmd, issue_slots[31].out_uop.ctrl.csr_cmd connect issue_slots[30].in_uop.bits.ctrl.fcn_dw, issue_slots[31].out_uop.ctrl.fcn_dw connect issue_slots[30].in_uop.bits.ctrl.op_fcn, issue_slots[31].out_uop.ctrl.op_fcn connect issue_slots[30].in_uop.bits.ctrl.imm_sel, issue_slots[31].out_uop.ctrl.imm_sel connect issue_slots[30].in_uop.bits.ctrl.op2_sel, issue_slots[31].out_uop.ctrl.op2_sel connect issue_slots[30].in_uop.bits.ctrl.op1_sel, issue_slots[31].out_uop.ctrl.op1_sel connect issue_slots[30].in_uop.bits.ctrl.br_type, issue_slots[31].out_uop.ctrl.br_type connect issue_slots[30].in_uop.bits.fu_code, issue_slots[31].out_uop.fu_code connect issue_slots[30].in_uop.bits.iq_type, issue_slots[31].out_uop.iq_type connect issue_slots[30].in_uop.bits.debug_pc, issue_slots[31].out_uop.debug_pc connect issue_slots[30].in_uop.bits.is_rvc, issue_slots[31].out_uop.is_rvc connect issue_slots[30].in_uop.bits.debug_inst, issue_slots[31].out_uop.debug_inst connect issue_slots[30].in_uop.bits.inst, issue_slots[31].out_uop.inst connect issue_slots[30].in_uop.bits.uopc, issue_slots[31].out_uop.uopc node _T_350 = eq(_WIRE_34, UInt<1>(0h1)) when _T_350 : connect issue_slots[30].in_uop.valid, issue_slots[31].will_be_valid connect issue_slots[30].in_uop.bits.debug_tsrc, issue_slots[31].out_uop.debug_tsrc connect issue_slots[30].in_uop.bits.debug_fsrc, issue_slots[31].out_uop.debug_fsrc connect issue_slots[30].in_uop.bits.bp_xcpt_if, issue_slots[31].out_uop.bp_xcpt_if connect issue_slots[30].in_uop.bits.bp_debug_if, issue_slots[31].out_uop.bp_debug_if connect issue_slots[30].in_uop.bits.xcpt_ma_if, issue_slots[31].out_uop.xcpt_ma_if connect issue_slots[30].in_uop.bits.xcpt_ae_if, issue_slots[31].out_uop.xcpt_ae_if connect issue_slots[30].in_uop.bits.xcpt_pf_if, issue_slots[31].out_uop.xcpt_pf_if connect issue_slots[30].in_uop.bits.fp_single, issue_slots[31].out_uop.fp_single connect issue_slots[30].in_uop.bits.fp_val, issue_slots[31].out_uop.fp_val connect issue_slots[30].in_uop.bits.frs3_en, issue_slots[31].out_uop.frs3_en connect issue_slots[30].in_uop.bits.lrs2_rtype, issue_slots[31].out_uop.lrs2_rtype connect issue_slots[30].in_uop.bits.lrs1_rtype, issue_slots[31].out_uop.lrs1_rtype connect issue_slots[30].in_uop.bits.dst_rtype, issue_slots[31].out_uop.dst_rtype connect issue_slots[30].in_uop.bits.ldst_val, issue_slots[31].out_uop.ldst_val connect issue_slots[30].in_uop.bits.lrs3, issue_slots[31].out_uop.lrs3 connect issue_slots[30].in_uop.bits.lrs2, issue_slots[31].out_uop.lrs2 connect issue_slots[30].in_uop.bits.lrs1, issue_slots[31].out_uop.lrs1 connect issue_slots[30].in_uop.bits.ldst, issue_slots[31].out_uop.ldst connect issue_slots[30].in_uop.bits.ldst_is_rs1, issue_slots[31].out_uop.ldst_is_rs1 connect issue_slots[30].in_uop.bits.flush_on_commit, issue_slots[31].out_uop.flush_on_commit connect issue_slots[30].in_uop.bits.is_unique, issue_slots[31].out_uop.is_unique connect issue_slots[30].in_uop.bits.is_sys_pc2epc, issue_slots[31].out_uop.is_sys_pc2epc connect issue_slots[30].in_uop.bits.uses_stq, issue_slots[31].out_uop.uses_stq connect issue_slots[30].in_uop.bits.uses_ldq, issue_slots[31].out_uop.uses_ldq connect issue_slots[30].in_uop.bits.is_amo, issue_slots[31].out_uop.is_amo connect issue_slots[30].in_uop.bits.is_fencei, issue_slots[31].out_uop.is_fencei connect issue_slots[30].in_uop.bits.is_fence, issue_slots[31].out_uop.is_fence connect issue_slots[30].in_uop.bits.mem_signed, issue_slots[31].out_uop.mem_signed connect issue_slots[30].in_uop.bits.mem_size, issue_slots[31].out_uop.mem_size connect issue_slots[30].in_uop.bits.mem_cmd, issue_slots[31].out_uop.mem_cmd connect issue_slots[30].in_uop.bits.bypassable, issue_slots[31].out_uop.bypassable connect issue_slots[30].in_uop.bits.exc_cause, issue_slots[31].out_uop.exc_cause connect issue_slots[30].in_uop.bits.exception, issue_slots[31].out_uop.exception connect issue_slots[30].in_uop.bits.stale_pdst, issue_slots[31].out_uop.stale_pdst connect issue_slots[30].in_uop.bits.ppred_busy, issue_slots[31].out_uop.ppred_busy connect issue_slots[30].in_uop.bits.prs3_busy, issue_slots[31].out_uop.prs3_busy connect issue_slots[30].in_uop.bits.prs2_busy, issue_slots[31].out_uop.prs2_busy connect issue_slots[30].in_uop.bits.prs1_busy, issue_slots[31].out_uop.prs1_busy connect issue_slots[30].in_uop.bits.ppred, issue_slots[31].out_uop.ppred connect issue_slots[30].in_uop.bits.prs3, issue_slots[31].out_uop.prs3 connect issue_slots[30].in_uop.bits.prs2, issue_slots[31].out_uop.prs2 connect issue_slots[30].in_uop.bits.prs1, issue_slots[31].out_uop.prs1 connect issue_slots[30].in_uop.bits.pdst, issue_slots[31].out_uop.pdst connect issue_slots[30].in_uop.bits.rxq_idx, issue_slots[31].out_uop.rxq_idx connect issue_slots[30].in_uop.bits.stq_idx, issue_slots[31].out_uop.stq_idx connect issue_slots[30].in_uop.bits.ldq_idx, issue_slots[31].out_uop.ldq_idx connect issue_slots[30].in_uop.bits.rob_idx, issue_slots[31].out_uop.rob_idx connect issue_slots[30].in_uop.bits.csr_addr, issue_slots[31].out_uop.csr_addr connect issue_slots[30].in_uop.bits.imm_packed, issue_slots[31].out_uop.imm_packed connect issue_slots[30].in_uop.bits.taken, issue_slots[31].out_uop.taken connect issue_slots[30].in_uop.bits.pc_lob, issue_slots[31].out_uop.pc_lob connect issue_slots[30].in_uop.bits.edge_inst, issue_slots[31].out_uop.edge_inst connect issue_slots[30].in_uop.bits.ftq_idx, issue_slots[31].out_uop.ftq_idx connect issue_slots[30].in_uop.bits.br_tag, issue_slots[31].out_uop.br_tag connect issue_slots[30].in_uop.bits.br_mask, issue_slots[31].out_uop.br_mask connect issue_slots[30].in_uop.bits.is_sfb, issue_slots[31].out_uop.is_sfb connect issue_slots[30].in_uop.bits.is_jal, issue_slots[31].out_uop.is_jal connect issue_slots[30].in_uop.bits.is_jalr, issue_slots[31].out_uop.is_jalr connect issue_slots[30].in_uop.bits.is_br, issue_slots[31].out_uop.is_br connect issue_slots[30].in_uop.bits.iw_p2_poisoned, issue_slots[31].out_uop.iw_p2_poisoned connect issue_slots[30].in_uop.bits.iw_p1_poisoned, issue_slots[31].out_uop.iw_p1_poisoned connect issue_slots[30].in_uop.bits.iw_state, issue_slots[31].out_uop.iw_state connect issue_slots[30].in_uop.bits.ctrl.is_std, issue_slots[31].out_uop.ctrl.is_std connect issue_slots[30].in_uop.bits.ctrl.is_sta, issue_slots[31].out_uop.ctrl.is_sta connect issue_slots[30].in_uop.bits.ctrl.is_load, issue_slots[31].out_uop.ctrl.is_load connect issue_slots[30].in_uop.bits.ctrl.csr_cmd, issue_slots[31].out_uop.ctrl.csr_cmd connect issue_slots[30].in_uop.bits.ctrl.fcn_dw, issue_slots[31].out_uop.ctrl.fcn_dw connect issue_slots[30].in_uop.bits.ctrl.op_fcn, issue_slots[31].out_uop.ctrl.op_fcn connect issue_slots[30].in_uop.bits.ctrl.imm_sel, issue_slots[31].out_uop.ctrl.imm_sel connect issue_slots[30].in_uop.bits.ctrl.op2_sel, issue_slots[31].out_uop.ctrl.op2_sel connect issue_slots[30].in_uop.bits.ctrl.op1_sel, issue_slots[31].out_uop.ctrl.op1_sel connect issue_slots[30].in_uop.bits.ctrl.br_type, issue_slots[31].out_uop.ctrl.br_type connect issue_slots[30].in_uop.bits.fu_code, issue_slots[31].out_uop.fu_code connect issue_slots[30].in_uop.bits.iq_type, issue_slots[31].out_uop.iq_type connect issue_slots[30].in_uop.bits.debug_pc, issue_slots[31].out_uop.debug_pc connect issue_slots[30].in_uop.bits.is_rvc, issue_slots[31].out_uop.is_rvc connect issue_slots[30].in_uop.bits.debug_inst, issue_slots[31].out_uop.debug_inst connect issue_slots[30].in_uop.bits.inst, issue_slots[31].out_uop.inst connect issue_slots[30].in_uop.bits.uopc, issue_slots[31].out_uop.uopc node _T_351 = eq(_WIRE_35, UInt<2>(0h2)) when _T_351 : connect issue_slots[30].in_uop.valid, will_be_valid_32 connect issue_slots[30].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[30].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[30].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[30].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[30].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[30].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[30].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[30].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[30].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[30].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[30].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[30].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[30].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[30].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[30].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[30].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[30].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[30].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[30].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[30].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[30].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[30].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[30].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[30].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[30].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[30].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[30].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[30].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[30].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[30].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[30].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[30].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[30].in_uop.bits.exception, _WIRE.exception connect issue_slots[30].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[30].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[30].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[30].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[30].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[30].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[30].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[30].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[30].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[30].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[30].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[30].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[30].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[30].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[30].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[30].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[30].in_uop.bits.taken, _WIRE.taken connect issue_slots[30].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[30].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[30].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[30].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[30].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[30].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[30].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[30].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[30].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[30].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[30].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[30].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[30].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[30].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[30].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[30].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[30].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[30].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[30].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[30].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[30].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[30].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[30].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[30].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[30].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[30].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[30].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[30].in_uop.bits.inst, _WIRE.inst connect issue_slots[30].in_uop.bits.uopc, _WIRE.uopc node _T_352 = eq(_WIRE_36, UInt<3>(0h4)) when _T_352 : connect issue_slots[30].in_uop.valid, will_be_valid_33 connect issue_slots[30].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[30].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[30].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[30].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[30].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[30].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[30].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[30].in_uop.bits.fp_single, _WIRE_1.fp_single connect issue_slots[30].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[30].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[30].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[30].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[30].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[30].in_uop.bits.ldst_val, _WIRE_1.ldst_val connect issue_slots[30].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[30].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[30].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[30].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[30].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[30].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[30].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[30].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[30].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[30].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[30].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[30].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[30].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[30].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[30].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[30].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[30].in_uop.bits.bypassable, _WIRE_1.bypassable connect issue_slots[30].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[30].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[30].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[30].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[30].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[30].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[30].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[30].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[30].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[30].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[30].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[30].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[30].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[30].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[30].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[30].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[30].in_uop.bits.csr_addr, _WIRE_1.csr_addr connect issue_slots[30].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[30].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[30].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[30].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[30].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[30].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[30].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[30].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[30].in_uop.bits.is_jal, _WIRE_1.is_jal connect issue_slots[30].in_uop.bits.is_jalr, _WIRE_1.is_jalr connect issue_slots[30].in_uop.bits.is_br, _WIRE_1.is_br connect issue_slots[30].in_uop.bits.iw_p2_poisoned, _WIRE_1.iw_p2_poisoned connect issue_slots[30].in_uop.bits.iw_p1_poisoned, _WIRE_1.iw_p1_poisoned connect issue_slots[30].in_uop.bits.iw_state, _WIRE_1.iw_state connect issue_slots[30].in_uop.bits.ctrl.is_std, _WIRE_1.ctrl.is_std connect issue_slots[30].in_uop.bits.ctrl.is_sta, _WIRE_1.ctrl.is_sta connect issue_slots[30].in_uop.bits.ctrl.is_load, _WIRE_1.ctrl.is_load connect issue_slots[30].in_uop.bits.ctrl.csr_cmd, _WIRE_1.ctrl.csr_cmd connect issue_slots[30].in_uop.bits.ctrl.fcn_dw, _WIRE_1.ctrl.fcn_dw connect issue_slots[30].in_uop.bits.ctrl.op_fcn, _WIRE_1.ctrl.op_fcn connect issue_slots[30].in_uop.bits.ctrl.imm_sel, _WIRE_1.ctrl.imm_sel connect issue_slots[30].in_uop.bits.ctrl.op2_sel, _WIRE_1.ctrl.op2_sel connect issue_slots[30].in_uop.bits.ctrl.op1_sel, _WIRE_1.ctrl.op1_sel connect issue_slots[30].in_uop.bits.ctrl.br_type, _WIRE_1.ctrl.br_type connect issue_slots[30].in_uop.bits.fu_code, _WIRE_1.fu_code connect issue_slots[30].in_uop.bits.iq_type, _WIRE_1.iq_type connect issue_slots[30].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[30].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[30].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[30].in_uop.bits.inst, _WIRE_1.inst connect issue_slots[30].in_uop.bits.uopc, _WIRE_1.uopc node _issue_slots_30_clear_T = neq(_WIRE_33, UInt<1>(0h0)) connect issue_slots[30].clear, _issue_slots_30_clear_T connect issue_slots[31].in_uop.valid, UInt<1>(0h0) connect issue_slots[31].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[31].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[31].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[31].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[31].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[31].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[31].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[31].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[31].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[31].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[31].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[31].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[31].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[31].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[31].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[31].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[31].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[31].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[31].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[31].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[31].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[31].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[31].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[31].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[31].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[31].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[31].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[31].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[31].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[31].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[31].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[31].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[31].in_uop.bits.exception, _WIRE.exception connect issue_slots[31].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[31].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[31].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[31].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[31].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[31].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[31].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[31].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[31].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[31].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[31].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[31].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[31].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[31].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[31].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[31].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[31].in_uop.bits.taken, _WIRE.taken connect issue_slots[31].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[31].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[31].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[31].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[31].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[31].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[31].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[31].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[31].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[31].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[31].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[31].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[31].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[31].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[31].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[31].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[31].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[31].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[31].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[31].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[31].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[31].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[31].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[31].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[31].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[31].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[31].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[31].in_uop.bits.inst, _WIRE.inst connect issue_slots[31].in_uop.bits.uopc, _WIRE.uopc node _T_353 = eq(_WIRE_35, UInt<1>(0h1)) when _T_353 : connect issue_slots[31].in_uop.valid, will_be_valid_32 connect issue_slots[31].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[31].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[31].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[31].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[31].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[31].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[31].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[31].in_uop.bits.fp_single, _WIRE.fp_single connect issue_slots[31].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[31].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[31].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[31].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[31].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[31].in_uop.bits.ldst_val, _WIRE.ldst_val connect issue_slots[31].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[31].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[31].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[31].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[31].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[31].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[31].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[31].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[31].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[31].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[31].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[31].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[31].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[31].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[31].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[31].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[31].in_uop.bits.bypassable, _WIRE.bypassable connect issue_slots[31].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[31].in_uop.bits.exception, _WIRE.exception connect issue_slots[31].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[31].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[31].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[31].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[31].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[31].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[31].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[31].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[31].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[31].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[31].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[31].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[31].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[31].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[31].in_uop.bits.csr_addr, _WIRE.csr_addr connect issue_slots[31].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[31].in_uop.bits.taken, _WIRE.taken connect issue_slots[31].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[31].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[31].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[31].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[31].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[31].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[31].in_uop.bits.is_jal, _WIRE.is_jal connect issue_slots[31].in_uop.bits.is_jalr, _WIRE.is_jalr connect issue_slots[31].in_uop.bits.is_br, _WIRE.is_br connect issue_slots[31].in_uop.bits.iw_p2_poisoned, _WIRE.iw_p2_poisoned connect issue_slots[31].in_uop.bits.iw_p1_poisoned, _WIRE.iw_p1_poisoned connect issue_slots[31].in_uop.bits.iw_state, _WIRE.iw_state connect issue_slots[31].in_uop.bits.ctrl.is_std, _WIRE.ctrl.is_std connect issue_slots[31].in_uop.bits.ctrl.is_sta, _WIRE.ctrl.is_sta connect issue_slots[31].in_uop.bits.ctrl.is_load, _WIRE.ctrl.is_load connect issue_slots[31].in_uop.bits.ctrl.csr_cmd, _WIRE.ctrl.csr_cmd connect issue_slots[31].in_uop.bits.ctrl.fcn_dw, _WIRE.ctrl.fcn_dw connect issue_slots[31].in_uop.bits.ctrl.op_fcn, _WIRE.ctrl.op_fcn connect issue_slots[31].in_uop.bits.ctrl.imm_sel, _WIRE.ctrl.imm_sel connect issue_slots[31].in_uop.bits.ctrl.op2_sel, _WIRE.ctrl.op2_sel connect issue_slots[31].in_uop.bits.ctrl.op1_sel, _WIRE.ctrl.op1_sel connect issue_slots[31].in_uop.bits.ctrl.br_type, _WIRE.ctrl.br_type connect issue_slots[31].in_uop.bits.fu_code, _WIRE.fu_code connect issue_slots[31].in_uop.bits.iq_type, _WIRE.iq_type connect issue_slots[31].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[31].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[31].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[31].in_uop.bits.inst, _WIRE.inst connect issue_slots[31].in_uop.bits.uopc, _WIRE.uopc node _T_354 = eq(_WIRE_36, UInt<2>(0h2)) when _T_354 : connect issue_slots[31].in_uop.valid, will_be_valid_33 connect issue_slots[31].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[31].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[31].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[31].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[31].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[31].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[31].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[31].in_uop.bits.fp_single, _WIRE_1.fp_single connect issue_slots[31].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[31].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[31].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[31].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[31].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[31].in_uop.bits.ldst_val, _WIRE_1.ldst_val connect issue_slots[31].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[31].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[31].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[31].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[31].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[31].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[31].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[31].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[31].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[31].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[31].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[31].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[31].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[31].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[31].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[31].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[31].in_uop.bits.bypassable, _WIRE_1.bypassable connect issue_slots[31].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[31].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[31].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[31].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[31].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[31].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[31].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[31].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[31].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[31].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[31].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[31].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[31].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[31].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[31].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[31].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[31].in_uop.bits.csr_addr, _WIRE_1.csr_addr connect issue_slots[31].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[31].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[31].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[31].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[31].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[31].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[31].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[31].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[31].in_uop.bits.is_jal, _WIRE_1.is_jal connect issue_slots[31].in_uop.bits.is_jalr, _WIRE_1.is_jalr connect issue_slots[31].in_uop.bits.is_br, _WIRE_1.is_br connect issue_slots[31].in_uop.bits.iw_p2_poisoned, _WIRE_1.iw_p2_poisoned connect issue_slots[31].in_uop.bits.iw_p1_poisoned, _WIRE_1.iw_p1_poisoned connect issue_slots[31].in_uop.bits.iw_state, _WIRE_1.iw_state connect issue_slots[31].in_uop.bits.ctrl.is_std, _WIRE_1.ctrl.is_std connect issue_slots[31].in_uop.bits.ctrl.is_sta, _WIRE_1.ctrl.is_sta connect issue_slots[31].in_uop.bits.ctrl.is_load, _WIRE_1.ctrl.is_load connect issue_slots[31].in_uop.bits.ctrl.csr_cmd, _WIRE_1.ctrl.csr_cmd connect issue_slots[31].in_uop.bits.ctrl.fcn_dw, _WIRE_1.ctrl.fcn_dw connect issue_slots[31].in_uop.bits.ctrl.op_fcn, _WIRE_1.ctrl.op_fcn connect issue_slots[31].in_uop.bits.ctrl.imm_sel, _WIRE_1.ctrl.imm_sel connect issue_slots[31].in_uop.bits.ctrl.op2_sel, _WIRE_1.ctrl.op2_sel connect issue_slots[31].in_uop.bits.ctrl.op1_sel, _WIRE_1.ctrl.op1_sel connect issue_slots[31].in_uop.bits.ctrl.br_type, _WIRE_1.ctrl.br_type connect issue_slots[31].in_uop.bits.fu_code, _WIRE_1.fu_code connect issue_slots[31].in_uop.bits.iq_type, _WIRE_1.iq_type connect issue_slots[31].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[31].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[31].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[31].in_uop.bits.inst, _WIRE_1.inst connect issue_slots[31].in_uop.bits.uopc, _WIRE_1.uopc node _T_355 = eq(_WIRE_37, UInt<3>(0h4)) when _T_355 : connect issue_slots[31].in_uop.valid, will_be_valid_34 connect issue_slots[31].in_uop.bits.debug_tsrc, _WIRE_2.debug_tsrc connect issue_slots[31].in_uop.bits.debug_fsrc, _WIRE_2.debug_fsrc connect issue_slots[31].in_uop.bits.bp_xcpt_if, _WIRE_2.bp_xcpt_if connect issue_slots[31].in_uop.bits.bp_debug_if, _WIRE_2.bp_debug_if connect issue_slots[31].in_uop.bits.xcpt_ma_if, _WIRE_2.xcpt_ma_if connect issue_slots[31].in_uop.bits.xcpt_ae_if, _WIRE_2.xcpt_ae_if connect issue_slots[31].in_uop.bits.xcpt_pf_if, _WIRE_2.xcpt_pf_if connect issue_slots[31].in_uop.bits.fp_single, _WIRE_2.fp_single connect issue_slots[31].in_uop.bits.fp_val, _WIRE_2.fp_val connect issue_slots[31].in_uop.bits.frs3_en, _WIRE_2.frs3_en connect issue_slots[31].in_uop.bits.lrs2_rtype, _WIRE_2.lrs2_rtype connect issue_slots[31].in_uop.bits.lrs1_rtype, _WIRE_2.lrs1_rtype connect issue_slots[31].in_uop.bits.dst_rtype, _WIRE_2.dst_rtype connect issue_slots[31].in_uop.bits.ldst_val, _WIRE_2.ldst_val connect issue_slots[31].in_uop.bits.lrs3, _WIRE_2.lrs3 connect issue_slots[31].in_uop.bits.lrs2, _WIRE_2.lrs2 connect issue_slots[31].in_uop.bits.lrs1, _WIRE_2.lrs1 connect issue_slots[31].in_uop.bits.ldst, _WIRE_2.ldst connect issue_slots[31].in_uop.bits.ldst_is_rs1, _WIRE_2.ldst_is_rs1 connect issue_slots[31].in_uop.bits.flush_on_commit, _WIRE_2.flush_on_commit connect issue_slots[31].in_uop.bits.is_unique, _WIRE_2.is_unique connect issue_slots[31].in_uop.bits.is_sys_pc2epc, _WIRE_2.is_sys_pc2epc connect issue_slots[31].in_uop.bits.uses_stq, _WIRE_2.uses_stq connect issue_slots[31].in_uop.bits.uses_ldq, _WIRE_2.uses_ldq connect issue_slots[31].in_uop.bits.is_amo, _WIRE_2.is_amo connect issue_slots[31].in_uop.bits.is_fencei, _WIRE_2.is_fencei connect issue_slots[31].in_uop.bits.is_fence, _WIRE_2.is_fence connect issue_slots[31].in_uop.bits.mem_signed, _WIRE_2.mem_signed connect issue_slots[31].in_uop.bits.mem_size, _WIRE_2.mem_size connect issue_slots[31].in_uop.bits.mem_cmd, _WIRE_2.mem_cmd connect issue_slots[31].in_uop.bits.bypassable, _WIRE_2.bypassable connect issue_slots[31].in_uop.bits.exc_cause, _WIRE_2.exc_cause connect issue_slots[31].in_uop.bits.exception, _WIRE_2.exception connect issue_slots[31].in_uop.bits.stale_pdst, _WIRE_2.stale_pdst connect issue_slots[31].in_uop.bits.ppred_busy, _WIRE_2.ppred_busy connect issue_slots[31].in_uop.bits.prs3_busy, _WIRE_2.prs3_busy connect issue_slots[31].in_uop.bits.prs2_busy, _WIRE_2.prs2_busy connect issue_slots[31].in_uop.bits.prs1_busy, _WIRE_2.prs1_busy connect issue_slots[31].in_uop.bits.ppred, _WIRE_2.ppred connect issue_slots[31].in_uop.bits.prs3, _WIRE_2.prs3 connect issue_slots[31].in_uop.bits.prs2, _WIRE_2.prs2 connect issue_slots[31].in_uop.bits.prs1, _WIRE_2.prs1 connect issue_slots[31].in_uop.bits.pdst, _WIRE_2.pdst connect issue_slots[31].in_uop.bits.rxq_idx, _WIRE_2.rxq_idx connect issue_slots[31].in_uop.bits.stq_idx, _WIRE_2.stq_idx connect issue_slots[31].in_uop.bits.ldq_idx, _WIRE_2.ldq_idx connect issue_slots[31].in_uop.bits.rob_idx, _WIRE_2.rob_idx connect issue_slots[31].in_uop.bits.csr_addr, _WIRE_2.csr_addr connect issue_slots[31].in_uop.bits.imm_packed, _WIRE_2.imm_packed connect issue_slots[31].in_uop.bits.taken, _WIRE_2.taken connect issue_slots[31].in_uop.bits.pc_lob, _WIRE_2.pc_lob connect issue_slots[31].in_uop.bits.edge_inst, _WIRE_2.edge_inst connect issue_slots[31].in_uop.bits.ftq_idx, _WIRE_2.ftq_idx connect issue_slots[31].in_uop.bits.br_tag, _WIRE_2.br_tag connect issue_slots[31].in_uop.bits.br_mask, _WIRE_2.br_mask connect issue_slots[31].in_uop.bits.is_sfb, _WIRE_2.is_sfb connect issue_slots[31].in_uop.bits.is_jal, _WIRE_2.is_jal connect issue_slots[31].in_uop.bits.is_jalr, _WIRE_2.is_jalr connect issue_slots[31].in_uop.bits.is_br, _WIRE_2.is_br connect issue_slots[31].in_uop.bits.iw_p2_poisoned, _WIRE_2.iw_p2_poisoned connect issue_slots[31].in_uop.bits.iw_p1_poisoned, _WIRE_2.iw_p1_poisoned connect issue_slots[31].in_uop.bits.iw_state, _WIRE_2.iw_state connect issue_slots[31].in_uop.bits.ctrl.is_std, _WIRE_2.ctrl.is_std connect issue_slots[31].in_uop.bits.ctrl.is_sta, _WIRE_2.ctrl.is_sta connect issue_slots[31].in_uop.bits.ctrl.is_load, _WIRE_2.ctrl.is_load connect issue_slots[31].in_uop.bits.ctrl.csr_cmd, _WIRE_2.ctrl.csr_cmd connect issue_slots[31].in_uop.bits.ctrl.fcn_dw, _WIRE_2.ctrl.fcn_dw connect issue_slots[31].in_uop.bits.ctrl.op_fcn, _WIRE_2.ctrl.op_fcn connect issue_slots[31].in_uop.bits.ctrl.imm_sel, _WIRE_2.ctrl.imm_sel connect issue_slots[31].in_uop.bits.ctrl.op2_sel, _WIRE_2.ctrl.op2_sel connect issue_slots[31].in_uop.bits.ctrl.op1_sel, _WIRE_2.ctrl.op1_sel connect issue_slots[31].in_uop.bits.ctrl.br_type, _WIRE_2.ctrl.br_type connect issue_slots[31].in_uop.bits.fu_code, _WIRE_2.fu_code connect issue_slots[31].in_uop.bits.iq_type, _WIRE_2.iq_type connect issue_slots[31].in_uop.bits.debug_pc, _WIRE_2.debug_pc connect issue_slots[31].in_uop.bits.is_rvc, _WIRE_2.is_rvc connect issue_slots[31].in_uop.bits.debug_inst, _WIRE_2.debug_inst connect issue_slots[31].in_uop.bits.inst, _WIRE_2.inst connect issue_slots[31].in_uop.bits.uopc, _WIRE_2.uopc node _issue_slots_31_clear_T = neq(_WIRE_34, UInt<1>(0h0)) connect issue_slots[31].clear, _issue_slots_31_clear_T node _will_be_available_T = eq(issue_slots[0].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_1 = or(_will_be_available_T, issue_slots[0].clear) node _will_be_available_T_2 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0)) node will_be_available_0 = and(_will_be_available_T_1, _will_be_available_T_2) node _will_be_available_T_3 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_4 = or(_will_be_available_T_3, issue_slots[1].clear) node _will_be_available_T_5 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0)) node will_be_available_1 = and(_will_be_available_T_4, _will_be_available_T_5) node _will_be_available_T_6 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_7 = or(_will_be_available_T_6, issue_slots[2].clear) node _will_be_available_T_8 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0)) node will_be_available_2 = and(_will_be_available_T_7, _will_be_available_T_8) node _will_be_available_T_9 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_10 = or(_will_be_available_T_9, issue_slots[3].clear) node _will_be_available_T_11 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0)) node will_be_available_3 = and(_will_be_available_T_10, _will_be_available_T_11) node _will_be_available_T_12 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_13 = or(_will_be_available_T_12, issue_slots[4].clear) node _will_be_available_T_14 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0)) node will_be_available_4 = and(_will_be_available_T_13, _will_be_available_T_14) node _will_be_available_T_15 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_16 = or(_will_be_available_T_15, issue_slots[5].clear) node _will_be_available_T_17 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0)) node will_be_available_5 = and(_will_be_available_T_16, _will_be_available_T_17) node _will_be_available_T_18 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_19 = or(_will_be_available_T_18, issue_slots[6].clear) node _will_be_available_T_20 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0)) node will_be_available_6 = and(_will_be_available_T_19, _will_be_available_T_20) node _will_be_available_T_21 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_22 = or(_will_be_available_T_21, issue_slots[7].clear) node _will_be_available_T_23 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0)) node will_be_available_7 = and(_will_be_available_T_22, _will_be_available_T_23) node _will_be_available_T_24 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_25 = or(_will_be_available_T_24, issue_slots[8].clear) node _will_be_available_T_26 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0)) node will_be_available_8 = and(_will_be_available_T_25, _will_be_available_T_26) node _will_be_available_T_27 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_28 = or(_will_be_available_T_27, issue_slots[9].clear) node _will_be_available_T_29 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0)) node will_be_available_9 = and(_will_be_available_T_28, _will_be_available_T_29) node _will_be_available_T_30 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_31 = or(_will_be_available_T_30, issue_slots[10].clear) node _will_be_available_T_32 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0)) node will_be_available_10 = and(_will_be_available_T_31, _will_be_available_T_32) node _will_be_available_T_33 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_34 = or(_will_be_available_T_33, issue_slots[11].clear) node _will_be_available_T_35 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0)) node will_be_available_11 = and(_will_be_available_T_34, _will_be_available_T_35) node _will_be_available_T_36 = eq(issue_slots[12].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_37 = or(_will_be_available_T_36, issue_slots[12].clear) node _will_be_available_T_38 = eq(issue_slots[12].in_uop.valid, UInt<1>(0h0)) node will_be_available_12 = and(_will_be_available_T_37, _will_be_available_T_38) node _will_be_available_T_39 = eq(issue_slots[13].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_40 = or(_will_be_available_T_39, issue_slots[13].clear) node _will_be_available_T_41 = eq(issue_slots[13].in_uop.valid, UInt<1>(0h0)) node will_be_available_13 = and(_will_be_available_T_40, _will_be_available_T_41) node _will_be_available_T_42 = eq(issue_slots[14].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_43 = or(_will_be_available_T_42, issue_slots[14].clear) node _will_be_available_T_44 = eq(issue_slots[14].in_uop.valid, UInt<1>(0h0)) node will_be_available_14 = and(_will_be_available_T_43, _will_be_available_T_44) node _will_be_available_T_45 = eq(issue_slots[15].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_46 = or(_will_be_available_T_45, issue_slots[15].clear) node _will_be_available_T_47 = eq(issue_slots[15].in_uop.valid, UInt<1>(0h0)) node will_be_available_15 = and(_will_be_available_T_46, _will_be_available_T_47) node _will_be_available_T_48 = eq(issue_slots[16].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_49 = or(_will_be_available_T_48, issue_slots[16].clear) node _will_be_available_T_50 = eq(issue_slots[16].in_uop.valid, UInt<1>(0h0)) node will_be_available_16 = and(_will_be_available_T_49, _will_be_available_T_50) node _will_be_available_T_51 = eq(issue_slots[17].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_52 = or(_will_be_available_T_51, issue_slots[17].clear) node _will_be_available_T_53 = eq(issue_slots[17].in_uop.valid, UInt<1>(0h0)) node will_be_available_17 = and(_will_be_available_T_52, _will_be_available_T_53) node _will_be_available_T_54 = eq(issue_slots[18].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_55 = or(_will_be_available_T_54, issue_slots[18].clear) node _will_be_available_T_56 = eq(issue_slots[18].in_uop.valid, UInt<1>(0h0)) node will_be_available_18 = and(_will_be_available_T_55, _will_be_available_T_56) node _will_be_available_T_57 = eq(issue_slots[19].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_58 = or(_will_be_available_T_57, issue_slots[19].clear) node _will_be_available_T_59 = eq(issue_slots[19].in_uop.valid, UInt<1>(0h0)) node will_be_available_19 = and(_will_be_available_T_58, _will_be_available_T_59) node _will_be_available_T_60 = eq(issue_slots[20].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_61 = or(_will_be_available_T_60, issue_slots[20].clear) node _will_be_available_T_62 = eq(issue_slots[20].in_uop.valid, UInt<1>(0h0)) node will_be_available_20 = and(_will_be_available_T_61, _will_be_available_T_62) node _will_be_available_T_63 = eq(issue_slots[21].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_64 = or(_will_be_available_T_63, issue_slots[21].clear) node _will_be_available_T_65 = eq(issue_slots[21].in_uop.valid, UInt<1>(0h0)) node will_be_available_21 = and(_will_be_available_T_64, _will_be_available_T_65) node _will_be_available_T_66 = eq(issue_slots[22].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_67 = or(_will_be_available_T_66, issue_slots[22].clear) node _will_be_available_T_68 = eq(issue_slots[22].in_uop.valid, UInt<1>(0h0)) node will_be_available_22 = and(_will_be_available_T_67, _will_be_available_T_68) node _will_be_available_T_69 = eq(issue_slots[23].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_70 = or(_will_be_available_T_69, issue_slots[23].clear) node _will_be_available_T_71 = eq(issue_slots[23].in_uop.valid, UInt<1>(0h0)) node will_be_available_23 = and(_will_be_available_T_70, _will_be_available_T_71) node _will_be_available_T_72 = eq(issue_slots[24].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_73 = or(_will_be_available_T_72, issue_slots[24].clear) node _will_be_available_T_74 = eq(issue_slots[24].in_uop.valid, UInt<1>(0h0)) node will_be_available_24 = and(_will_be_available_T_73, _will_be_available_T_74) node _will_be_available_T_75 = eq(issue_slots[25].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_76 = or(_will_be_available_T_75, issue_slots[25].clear) node _will_be_available_T_77 = eq(issue_slots[25].in_uop.valid, UInt<1>(0h0)) node will_be_available_25 = and(_will_be_available_T_76, _will_be_available_T_77) node _will_be_available_T_78 = eq(issue_slots[26].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_79 = or(_will_be_available_T_78, issue_slots[26].clear) node _will_be_available_T_80 = eq(issue_slots[26].in_uop.valid, UInt<1>(0h0)) node will_be_available_26 = and(_will_be_available_T_79, _will_be_available_T_80) node _will_be_available_T_81 = eq(issue_slots[27].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_82 = or(_will_be_available_T_81, issue_slots[27].clear) node _will_be_available_T_83 = eq(issue_slots[27].in_uop.valid, UInt<1>(0h0)) node will_be_available_27 = and(_will_be_available_T_82, _will_be_available_T_83) node _will_be_available_T_84 = eq(issue_slots[28].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_85 = or(_will_be_available_T_84, issue_slots[28].clear) node _will_be_available_T_86 = eq(issue_slots[28].in_uop.valid, UInt<1>(0h0)) node will_be_available_28 = and(_will_be_available_T_85, _will_be_available_T_86) node _will_be_available_T_87 = eq(issue_slots[29].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_88 = or(_will_be_available_T_87, issue_slots[29].clear) node _will_be_available_T_89 = eq(issue_slots[29].in_uop.valid, UInt<1>(0h0)) node will_be_available_29 = and(_will_be_available_T_88, _will_be_available_T_89) node _will_be_available_T_90 = eq(issue_slots[30].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_91 = or(_will_be_available_T_90, issue_slots[30].clear) node _will_be_available_T_92 = eq(issue_slots[30].in_uop.valid, UInt<1>(0h0)) node will_be_available_30 = and(_will_be_available_T_91, _will_be_available_T_92) node _will_be_available_T_93 = eq(issue_slots[31].will_be_valid, UInt<1>(0h0)) node _will_be_available_T_94 = or(_will_be_available_T_93, issue_slots[31].clear) node _will_be_available_T_95 = eq(issue_slots[31].in_uop.valid, UInt<1>(0h0)) node will_be_available_31 = and(_will_be_available_T_94, _will_be_available_T_95) node _num_available_T = add(will_be_available_0, will_be_available_1) node _num_available_T_1 = bits(_num_available_T, 1, 0) node _num_available_T_2 = add(will_be_available_2, will_be_available_3) node _num_available_T_3 = bits(_num_available_T_2, 1, 0) node _num_available_T_4 = add(_num_available_T_1, _num_available_T_3) node _num_available_T_5 = bits(_num_available_T_4, 2, 0) node _num_available_T_6 = add(will_be_available_4, will_be_available_5) node _num_available_T_7 = bits(_num_available_T_6, 1, 0) node _num_available_T_8 = add(will_be_available_6, will_be_available_7) node _num_available_T_9 = bits(_num_available_T_8, 1, 0) node _num_available_T_10 = add(_num_available_T_7, _num_available_T_9) node _num_available_T_11 = bits(_num_available_T_10, 2, 0) node _num_available_T_12 = add(_num_available_T_5, _num_available_T_11) node _num_available_T_13 = bits(_num_available_T_12, 3, 0) node _num_available_T_14 = add(will_be_available_8, will_be_available_9) node _num_available_T_15 = bits(_num_available_T_14, 1, 0) node _num_available_T_16 = add(will_be_available_10, will_be_available_11) node _num_available_T_17 = bits(_num_available_T_16, 1, 0) node _num_available_T_18 = add(_num_available_T_15, _num_available_T_17) node _num_available_T_19 = bits(_num_available_T_18, 2, 0) node _num_available_T_20 = add(will_be_available_12, will_be_available_13) node _num_available_T_21 = bits(_num_available_T_20, 1, 0) node _num_available_T_22 = add(will_be_available_14, will_be_available_15) node _num_available_T_23 = bits(_num_available_T_22, 1, 0) node _num_available_T_24 = add(_num_available_T_21, _num_available_T_23) node _num_available_T_25 = bits(_num_available_T_24, 2, 0) node _num_available_T_26 = add(_num_available_T_19, _num_available_T_25) node _num_available_T_27 = bits(_num_available_T_26, 3, 0) node _num_available_T_28 = add(_num_available_T_13, _num_available_T_27) node _num_available_T_29 = bits(_num_available_T_28, 4, 0) node _num_available_T_30 = add(will_be_available_16, will_be_available_17) node _num_available_T_31 = bits(_num_available_T_30, 1, 0) node _num_available_T_32 = add(will_be_available_18, will_be_available_19) node _num_available_T_33 = bits(_num_available_T_32, 1, 0) node _num_available_T_34 = add(_num_available_T_31, _num_available_T_33) node _num_available_T_35 = bits(_num_available_T_34, 2, 0) node _num_available_T_36 = add(will_be_available_20, will_be_available_21) node _num_available_T_37 = bits(_num_available_T_36, 1, 0) node _num_available_T_38 = add(will_be_available_22, will_be_available_23) node _num_available_T_39 = bits(_num_available_T_38, 1, 0) node _num_available_T_40 = add(_num_available_T_37, _num_available_T_39) node _num_available_T_41 = bits(_num_available_T_40, 2, 0) node _num_available_T_42 = add(_num_available_T_35, _num_available_T_41) node _num_available_T_43 = bits(_num_available_T_42, 3, 0) node _num_available_T_44 = add(will_be_available_24, will_be_available_25) node _num_available_T_45 = bits(_num_available_T_44, 1, 0) node _num_available_T_46 = add(will_be_available_26, will_be_available_27) node _num_available_T_47 = bits(_num_available_T_46, 1, 0) node _num_available_T_48 = add(_num_available_T_45, _num_available_T_47) node _num_available_T_49 = bits(_num_available_T_48, 2, 0) node _num_available_T_50 = add(will_be_available_28, will_be_available_29) node _num_available_T_51 = bits(_num_available_T_50, 1, 0) node _num_available_T_52 = add(will_be_available_30, will_be_available_31) node _num_available_T_53 = bits(_num_available_T_52, 1, 0) node _num_available_T_54 = add(_num_available_T_51, _num_available_T_53) node _num_available_T_55 = bits(_num_available_T_54, 2, 0) node _num_available_T_56 = add(_num_available_T_49, _num_available_T_55) node _num_available_T_57 = bits(_num_available_T_56, 3, 0) node _num_available_T_58 = add(_num_available_T_43, _num_available_T_57) node _num_available_T_59 = bits(_num_available_T_58, 4, 0) node _num_available_T_60 = add(_num_available_T_29, _num_available_T_59) node num_available = bits(_num_available_T_60, 5, 0) node _io_dis_uops_0_ready_T = gt(num_available, UInt<1>(0h0)) reg io_dis_uops_0_ready_REG : UInt<1>, clock connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG node _io_dis_uops_1_ready_T = gt(num_available, UInt<1>(0h1)) reg io_dis_uops_1_ready_REG : UInt<1>, clock connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG node _io_dis_uops_2_ready_T = gt(num_available, UInt<2>(0h2)) reg io_dis_uops_2_ready_REG : UInt<1>, clock connect io_dis_uops_2_ready_REG, _io_dis_uops_2_ready_T connect io.dis_uops[2].ready, io_dis_uops_2_ready_REG connect io.iss_valids[0], UInt<1>(0h0) wire io_iss_uops_0_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate io_iss_uops_0_uop.debug_tsrc invalidate io_iss_uops_0_uop.debug_fsrc invalidate io_iss_uops_0_uop.bp_xcpt_if invalidate io_iss_uops_0_uop.bp_debug_if invalidate io_iss_uops_0_uop.xcpt_ma_if invalidate io_iss_uops_0_uop.xcpt_ae_if invalidate io_iss_uops_0_uop.xcpt_pf_if invalidate io_iss_uops_0_uop.fp_single invalidate io_iss_uops_0_uop.fp_val invalidate io_iss_uops_0_uop.frs3_en invalidate io_iss_uops_0_uop.lrs2_rtype invalidate io_iss_uops_0_uop.lrs1_rtype invalidate io_iss_uops_0_uop.dst_rtype invalidate io_iss_uops_0_uop.ldst_val invalidate io_iss_uops_0_uop.lrs3 invalidate io_iss_uops_0_uop.lrs2 invalidate io_iss_uops_0_uop.lrs1 invalidate io_iss_uops_0_uop.ldst invalidate io_iss_uops_0_uop.ldst_is_rs1 invalidate io_iss_uops_0_uop.flush_on_commit invalidate io_iss_uops_0_uop.is_unique invalidate io_iss_uops_0_uop.is_sys_pc2epc invalidate io_iss_uops_0_uop.uses_stq invalidate io_iss_uops_0_uop.uses_ldq invalidate io_iss_uops_0_uop.is_amo invalidate io_iss_uops_0_uop.is_fencei invalidate io_iss_uops_0_uop.is_fence invalidate io_iss_uops_0_uop.mem_signed invalidate io_iss_uops_0_uop.mem_size invalidate io_iss_uops_0_uop.mem_cmd invalidate io_iss_uops_0_uop.bypassable invalidate io_iss_uops_0_uop.exc_cause invalidate io_iss_uops_0_uop.exception invalidate io_iss_uops_0_uop.stale_pdst invalidate io_iss_uops_0_uop.ppred_busy invalidate io_iss_uops_0_uop.prs3_busy invalidate io_iss_uops_0_uop.prs2_busy invalidate io_iss_uops_0_uop.prs1_busy invalidate io_iss_uops_0_uop.ppred invalidate io_iss_uops_0_uop.prs3 invalidate io_iss_uops_0_uop.prs2 invalidate io_iss_uops_0_uop.prs1 invalidate io_iss_uops_0_uop.pdst invalidate io_iss_uops_0_uop.rxq_idx invalidate io_iss_uops_0_uop.stq_idx invalidate io_iss_uops_0_uop.ldq_idx invalidate io_iss_uops_0_uop.rob_idx invalidate io_iss_uops_0_uop.csr_addr invalidate io_iss_uops_0_uop.imm_packed invalidate io_iss_uops_0_uop.taken invalidate io_iss_uops_0_uop.pc_lob invalidate io_iss_uops_0_uop.edge_inst invalidate io_iss_uops_0_uop.ftq_idx invalidate io_iss_uops_0_uop.br_tag invalidate io_iss_uops_0_uop.br_mask invalidate io_iss_uops_0_uop.is_sfb invalidate io_iss_uops_0_uop.is_jal invalidate io_iss_uops_0_uop.is_jalr invalidate io_iss_uops_0_uop.is_br invalidate io_iss_uops_0_uop.iw_p2_poisoned invalidate io_iss_uops_0_uop.iw_p1_poisoned invalidate io_iss_uops_0_uop.iw_state invalidate io_iss_uops_0_uop.ctrl.is_std invalidate io_iss_uops_0_uop.ctrl.is_sta invalidate io_iss_uops_0_uop.ctrl.is_load invalidate io_iss_uops_0_uop.ctrl.csr_cmd invalidate io_iss_uops_0_uop.ctrl.fcn_dw invalidate io_iss_uops_0_uop.ctrl.op_fcn invalidate io_iss_uops_0_uop.ctrl.imm_sel invalidate io_iss_uops_0_uop.ctrl.op2_sel invalidate io_iss_uops_0_uop.ctrl.op1_sel invalidate io_iss_uops_0_uop.ctrl.br_type invalidate io_iss_uops_0_uop.fu_code invalidate io_iss_uops_0_uop.iq_type invalidate io_iss_uops_0_uop.debug_pc invalidate io_iss_uops_0_uop.is_rvc invalidate io_iss_uops_0_uop.debug_inst invalidate io_iss_uops_0_uop.inst invalidate io_iss_uops_0_uop.uopc connect io_iss_uops_0_uop.uopc, UInt<7>(0h0) connect io_iss_uops_0_uop.bypassable, UInt<1>(0h0) connect io_iss_uops_0_uop.fp_val, UInt<1>(0h0) connect io_iss_uops_0_uop.uses_stq, UInt<1>(0h0) connect io_iss_uops_0_uop.uses_ldq, UInt<1>(0h0) connect io_iss_uops_0_uop.pdst, UInt<1>(0h0) connect io_iss_uops_0_uop.dst_rtype, UInt<2>(0h2) wire io_iss_uops_0_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate io_iss_uops_0_cs.is_std invalidate io_iss_uops_0_cs.is_sta invalidate io_iss_uops_0_cs.is_load invalidate io_iss_uops_0_cs.csr_cmd invalidate io_iss_uops_0_cs.fcn_dw invalidate io_iss_uops_0_cs.op_fcn invalidate io_iss_uops_0_cs.imm_sel invalidate io_iss_uops_0_cs.op2_sel invalidate io_iss_uops_0_cs.op1_sel invalidate io_iss_uops_0_cs.br_type connect io_iss_uops_0_cs.br_type, UInt<4>(0h0) connect io_iss_uops_0_cs.csr_cmd, UInt<3>(0h0) connect io_iss_uops_0_cs.is_load, UInt<1>(0h0) connect io_iss_uops_0_cs.is_sta, UInt<1>(0h0) connect io_iss_uops_0_cs.is_std, UInt<1>(0h0) connect io_iss_uops_0_uop.ctrl, io_iss_uops_0_cs connect io.iss_uops[0], io_iss_uops_0_uop connect io.iss_uops[0].prs1, UInt<1>(0h0) connect io.iss_uops[0].prs2, UInt<1>(0h0) connect io.iss_uops[0].prs3, UInt<1>(0h0) connect io.iss_uops[0].lrs1_rtype, UInt<2>(0h2) connect io.iss_uops[0].lrs2_rtype, UInt<2>(0h2) connect io.iss_valids[1], UInt<1>(0h0) wire io_iss_uops_1_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate io_iss_uops_1_uop.debug_tsrc invalidate io_iss_uops_1_uop.debug_fsrc invalidate io_iss_uops_1_uop.bp_xcpt_if invalidate io_iss_uops_1_uop.bp_debug_if invalidate io_iss_uops_1_uop.xcpt_ma_if invalidate io_iss_uops_1_uop.xcpt_ae_if invalidate io_iss_uops_1_uop.xcpt_pf_if invalidate io_iss_uops_1_uop.fp_single invalidate io_iss_uops_1_uop.fp_val invalidate io_iss_uops_1_uop.frs3_en invalidate io_iss_uops_1_uop.lrs2_rtype invalidate io_iss_uops_1_uop.lrs1_rtype invalidate io_iss_uops_1_uop.dst_rtype invalidate io_iss_uops_1_uop.ldst_val invalidate io_iss_uops_1_uop.lrs3 invalidate io_iss_uops_1_uop.lrs2 invalidate io_iss_uops_1_uop.lrs1 invalidate io_iss_uops_1_uop.ldst invalidate io_iss_uops_1_uop.ldst_is_rs1 invalidate io_iss_uops_1_uop.flush_on_commit invalidate io_iss_uops_1_uop.is_unique invalidate io_iss_uops_1_uop.is_sys_pc2epc invalidate io_iss_uops_1_uop.uses_stq invalidate io_iss_uops_1_uop.uses_ldq invalidate io_iss_uops_1_uop.is_amo invalidate io_iss_uops_1_uop.is_fencei invalidate io_iss_uops_1_uop.is_fence invalidate io_iss_uops_1_uop.mem_signed invalidate io_iss_uops_1_uop.mem_size invalidate io_iss_uops_1_uop.mem_cmd invalidate io_iss_uops_1_uop.bypassable invalidate io_iss_uops_1_uop.exc_cause invalidate io_iss_uops_1_uop.exception invalidate io_iss_uops_1_uop.stale_pdst invalidate io_iss_uops_1_uop.ppred_busy invalidate io_iss_uops_1_uop.prs3_busy invalidate io_iss_uops_1_uop.prs2_busy invalidate io_iss_uops_1_uop.prs1_busy invalidate io_iss_uops_1_uop.ppred invalidate io_iss_uops_1_uop.prs3 invalidate io_iss_uops_1_uop.prs2 invalidate io_iss_uops_1_uop.prs1 invalidate io_iss_uops_1_uop.pdst invalidate io_iss_uops_1_uop.rxq_idx invalidate io_iss_uops_1_uop.stq_idx invalidate io_iss_uops_1_uop.ldq_idx invalidate io_iss_uops_1_uop.rob_idx invalidate io_iss_uops_1_uop.csr_addr invalidate io_iss_uops_1_uop.imm_packed invalidate io_iss_uops_1_uop.taken invalidate io_iss_uops_1_uop.pc_lob invalidate io_iss_uops_1_uop.edge_inst invalidate io_iss_uops_1_uop.ftq_idx invalidate io_iss_uops_1_uop.br_tag invalidate io_iss_uops_1_uop.br_mask invalidate io_iss_uops_1_uop.is_sfb invalidate io_iss_uops_1_uop.is_jal invalidate io_iss_uops_1_uop.is_jalr invalidate io_iss_uops_1_uop.is_br invalidate io_iss_uops_1_uop.iw_p2_poisoned invalidate io_iss_uops_1_uop.iw_p1_poisoned invalidate io_iss_uops_1_uop.iw_state invalidate io_iss_uops_1_uop.ctrl.is_std invalidate io_iss_uops_1_uop.ctrl.is_sta invalidate io_iss_uops_1_uop.ctrl.is_load invalidate io_iss_uops_1_uop.ctrl.csr_cmd invalidate io_iss_uops_1_uop.ctrl.fcn_dw invalidate io_iss_uops_1_uop.ctrl.op_fcn invalidate io_iss_uops_1_uop.ctrl.imm_sel invalidate io_iss_uops_1_uop.ctrl.op2_sel invalidate io_iss_uops_1_uop.ctrl.op1_sel invalidate io_iss_uops_1_uop.ctrl.br_type invalidate io_iss_uops_1_uop.fu_code invalidate io_iss_uops_1_uop.iq_type invalidate io_iss_uops_1_uop.debug_pc invalidate io_iss_uops_1_uop.is_rvc invalidate io_iss_uops_1_uop.debug_inst invalidate io_iss_uops_1_uop.inst invalidate io_iss_uops_1_uop.uopc connect io_iss_uops_1_uop.uopc, UInt<7>(0h0) connect io_iss_uops_1_uop.bypassable, UInt<1>(0h0) connect io_iss_uops_1_uop.fp_val, UInt<1>(0h0) connect io_iss_uops_1_uop.uses_stq, UInt<1>(0h0) connect io_iss_uops_1_uop.uses_ldq, UInt<1>(0h0) connect io_iss_uops_1_uop.pdst, UInt<1>(0h0) connect io_iss_uops_1_uop.dst_rtype, UInt<2>(0h2) wire io_iss_uops_1_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate io_iss_uops_1_cs.is_std invalidate io_iss_uops_1_cs.is_sta invalidate io_iss_uops_1_cs.is_load invalidate io_iss_uops_1_cs.csr_cmd invalidate io_iss_uops_1_cs.fcn_dw invalidate io_iss_uops_1_cs.op_fcn invalidate io_iss_uops_1_cs.imm_sel invalidate io_iss_uops_1_cs.op2_sel invalidate io_iss_uops_1_cs.op1_sel invalidate io_iss_uops_1_cs.br_type connect io_iss_uops_1_cs.br_type, UInt<4>(0h0) connect io_iss_uops_1_cs.csr_cmd, UInt<3>(0h0) connect io_iss_uops_1_cs.is_load, UInt<1>(0h0) connect io_iss_uops_1_cs.is_sta, UInt<1>(0h0) connect io_iss_uops_1_cs.is_std, UInt<1>(0h0) connect io_iss_uops_1_uop.ctrl, io_iss_uops_1_cs connect io.iss_uops[1], io_iss_uops_1_uop connect io.iss_uops[1].prs1, UInt<1>(0h0) connect io.iss_uops[1].prs2, UInt<1>(0h0) connect io.iss_uops[1].prs3, UInt<1>(0h0) connect io.iss_uops[1].lrs1_rtype, UInt<2>(0h2) connect io.iss_uops[1].lrs2_rtype, UInt<2>(0h2) connect io.iss_valids[2], UInt<1>(0h0) wire io_iss_uops_2_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate io_iss_uops_2_uop.debug_tsrc invalidate io_iss_uops_2_uop.debug_fsrc invalidate io_iss_uops_2_uop.bp_xcpt_if invalidate io_iss_uops_2_uop.bp_debug_if invalidate io_iss_uops_2_uop.xcpt_ma_if invalidate io_iss_uops_2_uop.xcpt_ae_if invalidate io_iss_uops_2_uop.xcpt_pf_if invalidate io_iss_uops_2_uop.fp_single invalidate io_iss_uops_2_uop.fp_val invalidate io_iss_uops_2_uop.frs3_en invalidate io_iss_uops_2_uop.lrs2_rtype invalidate io_iss_uops_2_uop.lrs1_rtype invalidate io_iss_uops_2_uop.dst_rtype invalidate io_iss_uops_2_uop.ldst_val invalidate io_iss_uops_2_uop.lrs3 invalidate io_iss_uops_2_uop.lrs2 invalidate io_iss_uops_2_uop.lrs1 invalidate io_iss_uops_2_uop.ldst invalidate io_iss_uops_2_uop.ldst_is_rs1 invalidate io_iss_uops_2_uop.flush_on_commit invalidate io_iss_uops_2_uop.is_unique invalidate io_iss_uops_2_uop.is_sys_pc2epc invalidate io_iss_uops_2_uop.uses_stq invalidate io_iss_uops_2_uop.uses_ldq invalidate io_iss_uops_2_uop.is_amo invalidate io_iss_uops_2_uop.is_fencei invalidate io_iss_uops_2_uop.is_fence invalidate io_iss_uops_2_uop.mem_signed invalidate io_iss_uops_2_uop.mem_size invalidate io_iss_uops_2_uop.mem_cmd invalidate io_iss_uops_2_uop.bypassable invalidate io_iss_uops_2_uop.exc_cause invalidate io_iss_uops_2_uop.exception invalidate io_iss_uops_2_uop.stale_pdst invalidate io_iss_uops_2_uop.ppred_busy invalidate io_iss_uops_2_uop.prs3_busy invalidate io_iss_uops_2_uop.prs2_busy invalidate io_iss_uops_2_uop.prs1_busy invalidate io_iss_uops_2_uop.ppred invalidate io_iss_uops_2_uop.prs3 invalidate io_iss_uops_2_uop.prs2 invalidate io_iss_uops_2_uop.prs1 invalidate io_iss_uops_2_uop.pdst invalidate io_iss_uops_2_uop.rxq_idx invalidate io_iss_uops_2_uop.stq_idx invalidate io_iss_uops_2_uop.ldq_idx invalidate io_iss_uops_2_uop.rob_idx invalidate io_iss_uops_2_uop.csr_addr invalidate io_iss_uops_2_uop.imm_packed invalidate io_iss_uops_2_uop.taken invalidate io_iss_uops_2_uop.pc_lob invalidate io_iss_uops_2_uop.edge_inst invalidate io_iss_uops_2_uop.ftq_idx invalidate io_iss_uops_2_uop.br_tag invalidate io_iss_uops_2_uop.br_mask invalidate io_iss_uops_2_uop.is_sfb invalidate io_iss_uops_2_uop.is_jal invalidate io_iss_uops_2_uop.is_jalr invalidate io_iss_uops_2_uop.is_br invalidate io_iss_uops_2_uop.iw_p2_poisoned invalidate io_iss_uops_2_uop.iw_p1_poisoned invalidate io_iss_uops_2_uop.iw_state invalidate io_iss_uops_2_uop.ctrl.is_std invalidate io_iss_uops_2_uop.ctrl.is_sta invalidate io_iss_uops_2_uop.ctrl.is_load invalidate io_iss_uops_2_uop.ctrl.csr_cmd invalidate io_iss_uops_2_uop.ctrl.fcn_dw invalidate io_iss_uops_2_uop.ctrl.op_fcn invalidate io_iss_uops_2_uop.ctrl.imm_sel invalidate io_iss_uops_2_uop.ctrl.op2_sel invalidate io_iss_uops_2_uop.ctrl.op1_sel invalidate io_iss_uops_2_uop.ctrl.br_type invalidate io_iss_uops_2_uop.fu_code invalidate io_iss_uops_2_uop.iq_type invalidate io_iss_uops_2_uop.debug_pc invalidate io_iss_uops_2_uop.is_rvc invalidate io_iss_uops_2_uop.debug_inst invalidate io_iss_uops_2_uop.inst invalidate io_iss_uops_2_uop.uopc connect io_iss_uops_2_uop.uopc, UInt<7>(0h0) connect io_iss_uops_2_uop.bypassable, UInt<1>(0h0) connect io_iss_uops_2_uop.fp_val, UInt<1>(0h0) connect io_iss_uops_2_uop.uses_stq, UInt<1>(0h0) connect io_iss_uops_2_uop.uses_ldq, UInt<1>(0h0) connect io_iss_uops_2_uop.pdst, UInt<1>(0h0) connect io_iss_uops_2_uop.dst_rtype, UInt<2>(0h2) wire io_iss_uops_2_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate io_iss_uops_2_cs.is_std invalidate io_iss_uops_2_cs.is_sta invalidate io_iss_uops_2_cs.is_load invalidate io_iss_uops_2_cs.csr_cmd invalidate io_iss_uops_2_cs.fcn_dw invalidate io_iss_uops_2_cs.op_fcn invalidate io_iss_uops_2_cs.imm_sel invalidate io_iss_uops_2_cs.op2_sel invalidate io_iss_uops_2_cs.op1_sel invalidate io_iss_uops_2_cs.br_type connect io_iss_uops_2_cs.br_type, UInt<4>(0h0) connect io_iss_uops_2_cs.csr_cmd, UInt<3>(0h0) connect io_iss_uops_2_cs.is_load, UInt<1>(0h0) connect io_iss_uops_2_cs.is_sta, UInt<1>(0h0) connect io_iss_uops_2_cs.is_std, UInt<1>(0h0) connect io_iss_uops_2_uop.ctrl, io_iss_uops_2_cs connect io.iss_uops[2], io_iss_uops_2_uop connect io.iss_uops[2].prs1, UInt<1>(0h0) connect io.iss_uops[2].prs2, UInt<1>(0h0) connect io.iss_uops[2].prs3, UInt<1>(0h0) connect io.iss_uops[2].lrs1_rtype, UInt<2>(0h2) connect io.iss_uops[2].lrs2_rtype, UInt<2>(0h2) connect issue_slots[0].grant, UInt<1>(0h0) node _can_allocate_T = and(issue_slots[0].uop.fu_code, io.fu_types[0]) node can_allocate = neq(_can_allocate_T, UInt<1>(0h0)) node _T_356 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = and(issue_slots[0].request, _T_356) node _T_358 = and(_T_357, can_allocate) node _T_359 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) when _T_360 : connect issue_slots[0].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[0].uop node _T_361 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = and(issue_slots[0].request, _T_361) node _T_363 = and(_T_362, can_allocate) node _T_364 = or(_T_363, UInt<1>(0h0)) node _T_365 = and(issue_slots[0].request, can_allocate) node _T_366 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(_T_367, UInt<1>(0h0)) node _can_allocate_T_1 = and(issue_slots[0].uop.fu_code, io.fu_types[1]) node can_allocate_1 = neq(_can_allocate_T_1, UInt<1>(0h0)) node _T_369 = eq(_T_368, UInt<1>(0h0)) node _T_370 = and(issue_slots[0].request, _T_369) node _T_371 = and(_T_370, can_allocate_1) node _T_372 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_373 = and(_T_371, _T_372) when _T_373 : connect issue_slots[0].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[0].uop node _T_374 = eq(_T_368, UInt<1>(0h0)) node _T_375 = and(issue_slots[0].request, _T_374) node _T_376 = and(_T_375, can_allocate_1) node _T_377 = or(_T_376, UInt<1>(0h0)) node _T_378 = and(issue_slots[0].request, can_allocate_1) node _T_379 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = and(_T_378, _T_379) node _T_381 = or(_T_380, _T_368) node _can_allocate_T_2 = and(issue_slots[0].uop.fu_code, io.fu_types[2]) node can_allocate_2 = neq(_can_allocate_T_2, UInt<1>(0h0)) node _T_382 = eq(_T_381, UInt<1>(0h0)) node _T_383 = and(issue_slots[0].request, _T_382) node _T_384 = and(_T_383, can_allocate_2) node _T_385 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = and(_T_384, _T_385) when _T_386 : connect issue_slots[0].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[0].uop node _T_387 = eq(_T_381, UInt<1>(0h0)) node _T_388 = and(issue_slots[0].request, _T_387) node _T_389 = and(_T_388, can_allocate_2) node _T_390 = or(_T_389, UInt<1>(0h0)) node _T_391 = and(issue_slots[0].request, can_allocate_2) node _T_392 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_393 = and(_T_391, _T_392) node _T_394 = or(_T_393, _T_381) connect issue_slots[1].grant, UInt<1>(0h0) node _can_allocate_T_3 = and(issue_slots[1].uop.fu_code, io.fu_types[0]) node can_allocate_3 = neq(_can_allocate_T_3, UInt<1>(0h0)) node _T_395 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_396 = and(issue_slots[1].request, _T_395) node _T_397 = and(_T_396, can_allocate_3) node _T_398 = eq(_T_364, UInt<1>(0h0)) node _T_399 = and(_T_397, _T_398) when _T_399 : connect issue_slots[1].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[1].uop node _T_400 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_401 = and(issue_slots[1].request, _T_400) node _T_402 = and(_T_401, can_allocate_3) node _T_403 = or(_T_402, _T_364) node _T_404 = and(issue_slots[1].request, can_allocate_3) node _T_405 = eq(_T_364, UInt<1>(0h0)) node _T_406 = and(_T_404, _T_405) node _T_407 = or(_T_406, UInt<1>(0h0)) node _can_allocate_T_4 = and(issue_slots[1].uop.fu_code, io.fu_types[1]) node can_allocate_4 = neq(_can_allocate_T_4, UInt<1>(0h0)) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = and(issue_slots[1].request, _T_408) node _T_410 = and(_T_409, can_allocate_4) node _T_411 = eq(_T_377, UInt<1>(0h0)) node _T_412 = and(_T_410, _T_411) when _T_412 : connect issue_slots[1].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[1].uop node _T_413 = eq(_T_407, UInt<1>(0h0)) node _T_414 = and(issue_slots[1].request, _T_413) node _T_415 = and(_T_414, can_allocate_4) node _T_416 = or(_T_415, _T_377) node _T_417 = and(issue_slots[1].request, can_allocate_4) node _T_418 = eq(_T_377, UInt<1>(0h0)) node _T_419 = and(_T_417, _T_418) node _T_420 = or(_T_419, _T_407) node _can_allocate_T_5 = and(issue_slots[1].uop.fu_code, io.fu_types[2]) node can_allocate_5 = neq(_can_allocate_T_5, UInt<1>(0h0)) node _T_421 = eq(_T_420, UInt<1>(0h0)) node _T_422 = and(issue_slots[1].request, _T_421) node _T_423 = and(_T_422, can_allocate_5) node _T_424 = eq(_T_390, UInt<1>(0h0)) node _T_425 = and(_T_423, _T_424) when _T_425 : connect issue_slots[1].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[1].uop node _T_426 = eq(_T_420, UInt<1>(0h0)) node _T_427 = and(issue_slots[1].request, _T_426) node _T_428 = and(_T_427, can_allocate_5) node _T_429 = or(_T_428, _T_390) node _T_430 = and(issue_slots[1].request, can_allocate_5) node _T_431 = eq(_T_390, UInt<1>(0h0)) node _T_432 = and(_T_430, _T_431) node _T_433 = or(_T_432, _T_420) connect issue_slots[2].grant, UInt<1>(0h0) node _can_allocate_T_6 = and(issue_slots[2].uop.fu_code, io.fu_types[0]) node can_allocate_6 = neq(_can_allocate_T_6, UInt<1>(0h0)) node _T_434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = and(issue_slots[2].request, _T_434) node _T_436 = and(_T_435, can_allocate_6) node _T_437 = eq(_T_403, UInt<1>(0h0)) node _T_438 = and(_T_436, _T_437) when _T_438 : connect issue_slots[2].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[2].uop node _T_439 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_440 = and(issue_slots[2].request, _T_439) node _T_441 = and(_T_440, can_allocate_6) node _T_442 = or(_T_441, _T_403) node _T_443 = and(issue_slots[2].request, can_allocate_6) node _T_444 = eq(_T_403, UInt<1>(0h0)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(_T_445, UInt<1>(0h0)) node _can_allocate_T_7 = and(issue_slots[2].uop.fu_code, io.fu_types[1]) node can_allocate_7 = neq(_can_allocate_T_7, UInt<1>(0h0)) node _T_447 = eq(_T_446, UInt<1>(0h0)) node _T_448 = and(issue_slots[2].request, _T_447) node _T_449 = and(_T_448, can_allocate_7) node _T_450 = eq(_T_416, UInt<1>(0h0)) node _T_451 = and(_T_449, _T_450) when _T_451 : connect issue_slots[2].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[2].uop node _T_452 = eq(_T_446, UInt<1>(0h0)) node _T_453 = and(issue_slots[2].request, _T_452) node _T_454 = and(_T_453, can_allocate_7) node _T_455 = or(_T_454, _T_416) node _T_456 = and(issue_slots[2].request, can_allocate_7) node _T_457 = eq(_T_416, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = or(_T_458, _T_446) node _can_allocate_T_8 = and(issue_slots[2].uop.fu_code, io.fu_types[2]) node can_allocate_8 = neq(_can_allocate_T_8, UInt<1>(0h0)) node _T_460 = eq(_T_459, UInt<1>(0h0)) node _T_461 = and(issue_slots[2].request, _T_460) node _T_462 = and(_T_461, can_allocate_8) node _T_463 = eq(_T_429, UInt<1>(0h0)) node _T_464 = and(_T_462, _T_463) when _T_464 : connect issue_slots[2].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[2].uop node _T_465 = eq(_T_459, UInt<1>(0h0)) node _T_466 = and(issue_slots[2].request, _T_465) node _T_467 = and(_T_466, can_allocate_8) node _T_468 = or(_T_467, _T_429) node _T_469 = and(issue_slots[2].request, can_allocate_8) node _T_470 = eq(_T_429, UInt<1>(0h0)) node _T_471 = and(_T_469, _T_470) node _T_472 = or(_T_471, _T_459) connect issue_slots[3].grant, UInt<1>(0h0) node _can_allocate_T_9 = and(issue_slots[3].uop.fu_code, io.fu_types[0]) node can_allocate_9 = neq(_can_allocate_T_9, UInt<1>(0h0)) node _T_473 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = and(issue_slots[3].request, _T_473) node _T_475 = and(_T_474, can_allocate_9) node _T_476 = eq(_T_442, UInt<1>(0h0)) node _T_477 = and(_T_475, _T_476) when _T_477 : connect issue_slots[3].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[3].uop node _T_478 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = and(issue_slots[3].request, _T_478) node _T_480 = and(_T_479, can_allocate_9) node _T_481 = or(_T_480, _T_442) node _T_482 = and(issue_slots[3].request, can_allocate_9) node _T_483 = eq(_T_442, UInt<1>(0h0)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(_T_484, UInt<1>(0h0)) node _can_allocate_T_10 = and(issue_slots[3].uop.fu_code, io.fu_types[1]) node can_allocate_10 = neq(_can_allocate_T_10, UInt<1>(0h0)) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = and(issue_slots[3].request, _T_486) node _T_488 = and(_T_487, can_allocate_10) node _T_489 = eq(_T_455, UInt<1>(0h0)) node _T_490 = and(_T_488, _T_489) when _T_490 : connect issue_slots[3].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[3].uop node _T_491 = eq(_T_485, UInt<1>(0h0)) node _T_492 = and(issue_slots[3].request, _T_491) node _T_493 = and(_T_492, can_allocate_10) node _T_494 = or(_T_493, _T_455) node _T_495 = and(issue_slots[3].request, can_allocate_10) node _T_496 = eq(_T_455, UInt<1>(0h0)) node _T_497 = and(_T_495, _T_496) node _T_498 = or(_T_497, _T_485) node _can_allocate_T_11 = and(issue_slots[3].uop.fu_code, io.fu_types[2]) node can_allocate_11 = neq(_can_allocate_T_11, UInt<1>(0h0)) node _T_499 = eq(_T_498, UInt<1>(0h0)) node _T_500 = and(issue_slots[3].request, _T_499) node _T_501 = and(_T_500, can_allocate_11) node _T_502 = eq(_T_468, UInt<1>(0h0)) node _T_503 = and(_T_501, _T_502) when _T_503 : connect issue_slots[3].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[3].uop node _T_504 = eq(_T_498, UInt<1>(0h0)) node _T_505 = and(issue_slots[3].request, _T_504) node _T_506 = and(_T_505, can_allocate_11) node _T_507 = or(_T_506, _T_468) node _T_508 = and(issue_slots[3].request, can_allocate_11) node _T_509 = eq(_T_468, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = or(_T_510, _T_498) connect issue_slots[4].grant, UInt<1>(0h0) node _can_allocate_T_12 = and(issue_slots[4].uop.fu_code, io.fu_types[0]) node can_allocate_12 = neq(_can_allocate_T_12, UInt<1>(0h0)) node _T_512 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_513 = and(issue_slots[4].request, _T_512) node _T_514 = and(_T_513, can_allocate_12) node _T_515 = eq(_T_481, UInt<1>(0h0)) node _T_516 = and(_T_514, _T_515) when _T_516 : connect issue_slots[4].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[4].uop node _T_517 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_518 = and(issue_slots[4].request, _T_517) node _T_519 = and(_T_518, can_allocate_12) node _T_520 = or(_T_519, _T_481) node _T_521 = and(issue_slots[4].request, can_allocate_12) node _T_522 = eq(_T_481, UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) node _T_524 = or(_T_523, UInt<1>(0h0)) node _can_allocate_T_13 = and(issue_slots[4].uop.fu_code, io.fu_types[1]) node can_allocate_13 = neq(_can_allocate_T_13, UInt<1>(0h0)) node _T_525 = eq(_T_524, UInt<1>(0h0)) node _T_526 = and(issue_slots[4].request, _T_525) node _T_527 = and(_T_526, can_allocate_13) node _T_528 = eq(_T_494, UInt<1>(0h0)) node _T_529 = and(_T_527, _T_528) when _T_529 : connect issue_slots[4].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[4].uop node _T_530 = eq(_T_524, UInt<1>(0h0)) node _T_531 = and(issue_slots[4].request, _T_530) node _T_532 = and(_T_531, can_allocate_13) node _T_533 = or(_T_532, _T_494) node _T_534 = and(issue_slots[4].request, can_allocate_13) node _T_535 = eq(_T_494, UInt<1>(0h0)) node _T_536 = and(_T_534, _T_535) node _T_537 = or(_T_536, _T_524) node _can_allocate_T_14 = and(issue_slots[4].uop.fu_code, io.fu_types[2]) node can_allocate_14 = neq(_can_allocate_T_14, UInt<1>(0h0)) node _T_538 = eq(_T_537, UInt<1>(0h0)) node _T_539 = and(issue_slots[4].request, _T_538) node _T_540 = and(_T_539, can_allocate_14) node _T_541 = eq(_T_507, UInt<1>(0h0)) node _T_542 = and(_T_540, _T_541) when _T_542 : connect issue_slots[4].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[4].uop node _T_543 = eq(_T_537, UInt<1>(0h0)) node _T_544 = and(issue_slots[4].request, _T_543) node _T_545 = and(_T_544, can_allocate_14) node _T_546 = or(_T_545, _T_507) node _T_547 = and(issue_slots[4].request, can_allocate_14) node _T_548 = eq(_T_507, UInt<1>(0h0)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(_T_549, _T_537) connect issue_slots[5].grant, UInt<1>(0h0) node _can_allocate_T_15 = and(issue_slots[5].uop.fu_code, io.fu_types[0]) node can_allocate_15 = neq(_can_allocate_T_15, UInt<1>(0h0)) node _T_551 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_552 = and(issue_slots[5].request, _T_551) node _T_553 = and(_T_552, can_allocate_15) node _T_554 = eq(_T_520, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : connect issue_slots[5].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[5].uop node _T_556 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_557 = and(issue_slots[5].request, _T_556) node _T_558 = and(_T_557, can_allocate_15) node _T_559 = or(_T_558, _T_520) node _T_560 = and(issue_slots[5].request, can_allocate_15) node _T_561 = eq(_T_520, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(_T_562, UInt<1>(0h0)) node _can_allocate_T_16 = and(issue_slots[5].uop.fu_code, io.fu_types[1]) node can_allocate_16 = neq(_can_allocate_T_16, UInt<1>(0h0)) node _T_564 = eq(_T_563, UInt<1>(0h0)) node _T_565 = and(issue_slots[5].request, _T_564) node _T_566 = and(_T_565, can_allocate_16) node _T_567 = eq(_T_533, UInt<1>(0h0)) node _T_568 = and(_T_566, _T_567) when _T_568 : connect issue_slots[5].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[5].uop node _T_569 = eq(_T_563, UInt<1>(0h0)) node _T_570 = and(issue_slots[5].request, _T_569) node _T_571 = and(_T_570, can_allocate_16) node _T_572 = or(_T_571, _T_533) node _T_573 = and(issue_slots[5].request, can_allocate_16) node _T_574 = eq(_T_533, UInt<1>(0h0)) node _T_575 = and(_T_573, _T_574) node _T_576 = or(_T_575, _T_563) node _can_allocate_T_17 = and(issue_slots[5].uop.fu_code, io.fu_types[2]) node can_allocate_17 = neq(_can_allocate_T_17, UInt<1>(0h0)) node _T_577 = eq(_T_576, UInt<1>(0h0)) node _T_578 = and(issue_slots[5].request, _T_577) node _T_579 = and(_T_578, can_allocate_17) node _T_580 = eq(_T_546, UInt<1>(0h0)) node _T_581 = and(_T_579, _T_580) when _T_581 : connect issue_slots[5].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[5].uop node _T_582 = eq(_T_576, UInt<1>(0h0)) node _T_583 = and(issue_slots[5].request, _T_582) node _T_584 = and(_T_583, can_allocate_17) node _T_585 = or(_T_584, _T_546) node _T_586 = and(issue_slots[5].request, can_allocate_17) node _T_587 = eq(_T_546, UInt<1>(0h0)) node _T_588 = and(_T_586, _T_587) node _T_589 = or(_T_588, _T_576) connect issue_slots[6].grant, UInt<1>(0h0) node _can_allocate_T_18 = and(issue_slots[6].uop.fu_code, io.fu_types[0]) node can_allocate_18 = neq(_can_allocate_T_18, UInt<1>(0h0)) node _T_590 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_591 = and(issue_slots[6].request, _T_590) node _T_592 = and(_T_591, can_allocate_18) node _T_593 = eq(_T_559, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) when _T_594 : connect issue_slots[6].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[6].uop node _T_595 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_596 = and(issue_slots[6].request, _T_595) node _T_597 = and(_T_596, can_allocate_18) node _T_598 = or(_T_597, _T_559) node _T_599 = and(issue_slots[6].request, can_allocate_18) node _T_600 = eq(_T_559, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) node _T_602 = or(_T_601, UInt<1>(0h0)) node _can_allocate_T_19 = and(issue_slots[6].uop.fu_code, io.fu_types[1]) node can_allocate_19 = neq(_can_allocate_T_19, UInt<1>(0h0)) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = and(issue_slots[6].request, _T_603) node _T_605 = and(_T_604, can_allocate_19) node _T_606 = eq(_T_572, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : connect issue_slots[6].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[6].uop node _T_608 = eq(_T_602, UInt<1>(0h0)) node _T_609 = and(issue_slots[6].request, _T_608) node _T_610 = and(_T_609, can_allocate_19) node _T_611 = or(_T_610, _T_572) node _T_612 = and(issue_slots[6].request, can_allocate_19) node _T_613 = eq(_T_572, UInt<1>(0h0)) node _T_614 = and(_T_612, _T_613) node _T_615 = or(_T_614, _T_602) node _can_allocate_T_20 = and(issue_slots[6].uop.fu_code, io.fu_types[2]) node can_allocate_20 = neq(_can_allocate_T_20, UInt<1>(0h0)) node _T_616 = eq(_T_615, UInt<1>(0h0)) node _T_617 = and(issue_slots[6].request, _T_616) node _T_618 = and(_T_617, can_allocate_20) node _T_619 = eq(_T_585, UInt<1>(0h0)) node _T_620 = and(_T_618, _T_619) when _T_620 : connect issue_slots[6].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[6].uop node _T_621 = eq(_T_615, UInt<1>(0h0)) node _T_622 = and(issue_slots[6].request, _T_621) node _T_623 = and(_T_622, can_allocate_20) node _T_624 = or(_T_623, _T_585) node _T_625 = and(issue_slots[6].request, can_allocate_20) node _T_626 = eq(_T_585, UInt<1>(0h0)) node _T_627 = and(_T_625, _T_626) node _T_628 = or(_T_627, _T_615) connect issue_slots[7].grant, UInt<1>(0h0) node _can_allocate_T_21 = and(issue_slots[7].uop.fu_code, io.fu_types[0]) node can_allocate_21 = neq(_can_allocate_T_21, UInt<1>(0h0)) node _T_629 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = and(issue_slots[7].request, _T_629) node _T_631 = and(_T_630, can_allocate_21) node _T_632 = eq(_T_598, UInt<1>(0h0)) node _T_633 = and(_T_631, _T_632) when _T_633 : connect issue_slots[7].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[7].uop node _T_634 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_635 = and(issue_slots[7].request, _T_634) node _T_636 = and(_T_635, can_allocate_21) node _T_637 = or(_T_636, _T_598) node _T_638 = and(issue_slots[7].request, can_allocate_21) node _T_639 = eq(_T_598, UInt<1>(0h0)) node _T_640 = and(_T_638, _T_639) node _T_641 = or(_T_640, UInt<1>(0h0)) node _can_allocate_T_22 = and(issue_slots[7].uop.fu_code, io.fu_types[1]) node can_allocate_22 = neq(_can_allocate_T_22, UInt<1>(0h0)) node _T_642 = eq(_T_641, UInt<1>(0h0)) node _T_643 = and(issue_slots[7].request, _T_642) node _T_644 = and(_T_643, can_allocate_22) node _T_645 = eq(_T_611, UInt<1>(0h0)) node _T_646 = and(_T_644, _T_645) when _T_646 : connect issue_slots[7].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[7].uop node _T_647 = eq(_T_641, UInt<1>(0h0)) node _T_648 = and(issue_slots[7].request, _T_647) node _T_649 = and(_T_648, can_allocate_22) node _T_650 = or(_T_649, _T_611) node _T_651 = and(issue_slots[7].request, can_allocate_22) node _T_652 = eq(_T_611, UInt<1>(0h0)) node _T_653 = and(_T_651, _T_652) node _T_654 = or(_T_653, _T_641) node _can_allocate_T_23 = and(issue_slots[7].uop.fu_code, io.fu_types[2]) node can_allocate_23 = neq(_can_allocate_T_23, UInt<1>(0h0)) node _T_655 = eq(_T_654, UInt<1>(0h0)) node _T_656 = and(issue_slots[7].request, _T_655) node _T_657 = and(_T_656, can_allocate_23) node _T_658 = eq(_T_624, UInt<1>(0h0)) node _T_659 = and(_T_657, _T_658) when _T_659 : connect issue_slots[7].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[7].uop node _T_660 = eq(_T_654, UInt<1>(0h0)) node _T_661 = and(issue_slots[7].request, _T_660) node _T_662 = and(_T_661, can_allocate_23) node _T_663 = or(_T_662, _T_624) node _T_664 = and(issue_slots[7].request, can_allocate_23) node _T_665 = eq(_T_624, UInt<1>(0h0)) node _T_666 = and(_T_664, _T_665) node _T_667 = or(_T_666, _T_654) connect issue_slots[8].grant, UInt<1>(0h0) node _can_allocate_T_24 = and(issue_slots[8].uop.fu_code, io.fu_types[0]) node can_allocate_24 = neq(_can_allocate_T_24, UInt<1>(0h0)) node _T_668 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = and(issue_slots[8].request, _T_668) node _T_670 = and(_T_669, can_allocate_24) node _T_671 = eq(_T_637, UInt<1>(0h0)) node _T_672 = and(_T_670, _T_671) when _T_672 : connect issue_slots[8].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[8].uop node _T_673 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_674 = and(issue_slots[8].request, _T_673) node _T_675 = and(_T_674, can_allocate_24) node _T_676 = or(_T_675, _T_637) node _T_677 = and(issue_slots[8].request, can_allocate_24) node _T_678 = eq(_T_637, UInt<1>(0h0)) node _T_679 = and(_T_677, _T_678) node _T_680 = or(_T_679, UInt<1>(0h0)) node _can_allocate_T_25 = and(issue_slots[8].uop.fu_code, io.fu_types[1]) node can_allocate_25 = neq(_can_allocate_T_25, UInt<1>(0h0)) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = and(issue_slots[8].request, _T_681) node _T_683 = and(_T_682, can_allocate_25) node _T_684 = eq(_T_650, UInt<1>(0h0)) node _T_685 = and(_T_683, _T_684) when _T_685 : connect issue_slots[8].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[8].uop node _T_686 = eq(_T_680, UInt<1>(0h0)) node _T_687 = and(issue_slots[8].request, _T_686) node _T_688 = and(_T_687, can_allocate_25) node _T_689 = or(_T_688, _T_650) node _T_690 = and(issue_slots[8].request, can_allocate_25) node _T_691 = eq(_T_650, UInt<1>(0h0)) node _T_692 = and(_T_690, _T_691) node _T_693 = or(_T_692, _T_680) node _can_allocate_T_26 = and(issue_slots[8].uop.fu_code, io.fu_types[2]) node can_allocate_26 = neq(_can_allocate_T_26, UInt<1>(0h0)) node _T_694 = eq(_T_693, UInt<1>(0h0)) node _T_695 = and(issue_slots[8].request, _T_694) node _T_696 = and(_T_695, can_allocate_26) node _T_697 = eq(_T_663, UInt<1>(0h0)) node _T_698 = and(_T_696, _T_697) when _T_698 : connect issue_slots[8].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[8].uop node _T_699 = eq(_T_693, UInt<1>(0h0)) node _T_700 = and(issue_slots[8].request, _T_699) node _T_701 = and(_T_700, can_allocate_26) node _T_702 = or(_T_701, _T_663) node _T_703 = and(issue_slots[8].request, can_allocate_26) node _T_704 = eq(_T_663, UInt<1>(0h0)) node _T_705 = and(_T_703, _T_704) node _T_706 = or(_T_705, _T_693) connect issue_slots[9].grant, UInt<1>(0h0) node _can_allocate_T_27 = and(issue_slots[9].uop.fu_code, io.fu_types[0]) node can_allocate_27 = neq(_can_allocate_T_27, UInt<1>(0h0)) node _T_707 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_708 = and(issue_slots[9].request, _T_707) node _T_709 = and(_T_708, can_allocate_27) node _T_710 = eq(_T_676, UInt<1>(0h0)) node _T_711 = and(_T_709, _T_710) when _T_711 : connect issue_slots[9].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[9].uop node _T_712 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_713 = and(issue_slots[9].request, _T_712) node _T_714 = and(_T_713, can_allocate_27) node _T_715 = or(_T_714, _T_676) node _T_716 = and(issue_slots[9].request, can_allocate_27) node _T_717 = eq(_T_676, UInt<1>(0h0)) node _T_718 = and(_T_716, _T_717) node _T_719 = or(_T_718, UInt<1>(0h0)) node _can_allocate_T_28 = and(issue_slots[9].uop.fu_code, io.fu_types[1]) node can_allocate_28 = neq(_can_allocate_T_28, UInt<1>(0h0)) node _T_720 = eq(_T_719, UInt<1>(0h0)) node _T_721 = and(issue_slots[9].request, _T_720) node _T_722 = and(_T_721, can_allocate_28) node _T_723 = eq(_T_689, UInt<1>(0h0)) node _T_724 = and(_T_722, _T_723) when _T_724 : connect issue_slots[9].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[9].uop node _T_725 = eq(_T_719, UInt<1>(0h0)) node _T_726 = and(issue_slots[9].request, _T_725) node _T_727 = and(_T_726, can_allocate_28) node _T_728 = or(_T_727, _T_689) node _T_729 = and(issue_slots[9].request, can_allocate_28) node _T_730 = eq(_T_689, UInt<1>(0h0)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_731, _T_719) node _can_allocate_T_29 = and(issue_slots[9].uop.fu_code, io.fu_types[2]) node can_allocate_29 = neq(_can_allocate_T_29, UInt<1>(0h0)) node _T_733 = eq(_T_732, UInt<1>(0h0)) node _T_734 = and(issue_slots[9].request, _T_733) node _T_735 = and(_T_734, can_allocate_29) node _T_736 = eq(_T_702, UInt<1>(0h0)) node _T_737 = and(_T_735, _T_736) when _T_737 : connect issue_slots[9].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[9].uop node _T_738 = eq(_T_732, UInt<1>(0h0)) node _T_739 = and(issue_slots[9].request, _T_738) node _T_740 = and(_T_739, can_allocate_29) node _T_741 = or(_T_740, _T_702) node _T_742 = and(issue_slots[9].request, can_allocate_29) node _T_743 = eq(_T_702, UInt<1>(0h0)) node _T_744 = and(_T_742, _T_743) node _T_745 = or(_T_744, _T_732) connect issue_slots[10].grant, UInt<1>(0h0) node _can_allocate_T_30 = and(issue_slots[10].uop.fu_code, io.fu_types[0]) node can_allocate_30 = neq(_can_allocate_T_30, UInt<1>(0h0)) node _T_746 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_747 = and(issue_slots[10].request, _T_746) node _T_748 = and(_T_747, can_allocate_30) node _T_749 = eq(_T_715, UInt<1>(0h0)) node _T_750 = and(_T_748, _T_749) when _T_750 : connect issue_slots[10].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[10].uop node _T_751 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_752 = and(issue_slots[10].request, _T_751) node _T_753 = and(_T_752, can_allocate_30) node _T_754 = or(_T_753, _T_715) node _T_755 = and(issue_slots[10].request, can_allocate_30) node _T_756 = eq(_T_715, UInt<1>(0h0)) node _T_757 = and(_T_755, _T_756) node _T_758 = or(_T_757, UInt<1>(0h0)) node _can_allocate_T_31 = and(issue_slots[10].uop.fu_code, io.fu_types[1]) node can_allocate_31 = neq(_can_allocate_T_31, UInt<1>(0h0)) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = and(issue_slots[10].request, _T_759) node _T_761 = and(_T_760, can_allocate_31) node _T_762 = eq(_T_728, UInt<1>(0h0)) node _T_763 = and(_T_761, _T_762) when _T_763 : connect issue_slots[10].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[10].uop node _T_764 = eq(_T_758, UInt<1>(0h0)) node _T_765 = and(issue_slots[10].request, _T_764) node _T_766 = and(_T_765, can_allocate_31) node _T_767 = or(_T_766, _T_728) node _T_768 = and(issue_slots[10].request, can_allocate_31) node _T_769 = eq(_T_728, UInt<1>(0h0)) node _T_770 = and(_T_768, _T_769) node _T_771 = or(_T_770, _T_758) node _can_allocate_T_32 = and(issue_slots[10].uop.fu_code, io.fu_types[2]) node can_allocate_32 = neq(_can_allocate_T_32, UInt<1>(0h0)) node _T_772 = eq(_T_771, UInt<1>(0h0)) node _T_773 = and(issue_slots[10].request, _T_772) node _T_774 = and(_T_773, can_allocate_32) node _T_775 = eq(_T_741, UInt<1>(0h0)) node _T_776 = and(_T_774, _T_775) when _T_776 : connect issue_slots[10].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[10].uop node _T_777 = eq(_T_771, UInt<1>(0h0)) node _T_778 = and(issue_slots[10].request, _T_777) node _T_779 = and(_T_778, can_allocate_32) node _T_780 = or(_T_779, _T_741) node _T_781 = and(issue_slots[10].request, can_allocate_32) node _T_782 = eq(_T_741, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) node _T_784 = or(_T_783, _T_771) connect issue_slots[11].grant, UInt<1>(0h0) node _can_allocate_T_33 = and(issue_slots[11].uop.fu_code, io.fu_types[0]) node can_allocate_33 = neq(_can_allocate_T_33, UInt<1>(0h0)) node _T_785 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = and(issue_slots[11].request, _T_785) node _T_787 = and(_T_786, can_allocate_33) node _T_788 = eq(_T_754, UInt<1>(0h0)) node _T_789 = and(_T_787, _T_788) when _T_789 : connect issue_slots[11].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[11].uop node _T_790 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_791 = and(issue_slots[11].request, _T_790) node _T_792 = and(_T_791, can_allocate_33) node _T_793 = or(_T_792, _T_754) node _T_794 = and(issue_slots[11].request, can_allocate_33) node _T_795 = eq(_T_754, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) node _T_797 = or(_T_796, UInt<1>(0h0)) node _can_allocate_T_34 = and(issue_slots[11].uop.fu_code, io.fu_types[1]) node can_allocate_34 = neq(_can_allocate_T_34, UInt<1>(0h0)) node _T_798 = eq(_T_797, UInt<1>(0h0)) node _T_799 = and(issue_slots[11].request, _T_798) node _T_800 = and(_T_799, can_allocate_34) node _T_801 = eq(_T_767, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect issue_slots[11].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[11].uop node _T_803 = eq(_T_797, UInt<1>(0h0)) node _T_804 = and(issue_slots[11].request, _T_803) node _T_805 = and(_T_804, can_allocate_34) node _T_806 = or(_T_805, _T_767) node _T_807 = and(issue_slots[11].request, can_allocate_34) node _T_808 = eq(_T_767, UInt<1>(0h0)) node _T_809 = and(_T_807, _T_808) node _T_810 = or(_T_809, _T_797) node _can_allocate_T_35 = and(issue_slots[11].uop.fu_code, io.fu_types[2]) node can_allocate_35 = neq(_can_allocate_T_35, UInt<1>(0h0)) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = and(issue_slots[11].request, _T_811) node _T_813 = and(_T_812, can_allocate_35) node _T_814 = eq(_T_780, UInt<1>(0h0)) node _T_815 = and(_T_813, _T_814) when _T_815 : connect issue_slots[11].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[11].uop node _T_816 = eq(_T_810, UInt<1>(0h0)) node _T_817 = and(issue_slots[11].request, _T_816) node _T_818 = and(_T_817, can_allocate_35) node _T_819 = or(_T_818, _T_780) node _T_820 = and(issue_slots[11].request, can_allocate_35) node _T_821 = eq(_T_780, UInt<1>(0h0)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(_T_822, _T_810) connect issue_slots[12].grant, UInt<1>(0h0) node _can_allocate_T_36 = and(issue_slots[12].uop.fu_code, io.fu_types[0]) node can_allocate_36 = neq(_can_allocate_T_36, UInt<1>(0h0)) node _T_824 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_825 = and(issue_slots[12].request, _T_824) node _T_826 = and(_T_825, can_allocate_36) node _T_827 = eq(_T_793, UInt<1>(0h0)) node _T_828 = and(_T_826, _T_827) when _T_828 : connect issue_slots[12].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[12].uop node _T_829 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = and(issue_slots[12].request, _T_829) node _T_831 = and(_T_830, can_allocate_36) node _T_832 = or(_T_831, _T_793) node _T_833 = and(issue_slots[12].request, can_allocate_36) node _T_834 = eq(_T_793, UInt<1>(0h0)) node _T_835 = and(_T_833, _T_834) node _T_836 = or(_T_835, UInt<1>(0h0)) node _can_allocate_T_37 = and(issue_slots[12].uop.fu_code, io.fu_types[1]) node can_allocate_37 = neq(_can_allocate_T_37, UInt<1>(0h0)) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = and(issue_slots[12].request, _T_837) node _T_839 = and(_T_838, can_allocate_37) node _T_840 = eq(_T_806, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : connect issue_slots[12].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[12].uop node _T_842 = eq(_T_836, UInt<1>(0h0)) node _T_843 = and(issue_slots[12].request, _T_842) node _T_844 = and(_T_843, can_allocate_37) node _T_845 = or(_T_844, _T_806) node _T_846 = and(issue_slots[12].request, can_allocate_37) node _T_847 = eq(_T_806, UInt<1>(0h0)) node _T_848 = and(_T_846, _T_847) node _T_849 = or(_T_848, _T_836) node _can_allocate_T_38 = and(issue_slots[12].uop.fu_code, io.fu_types[2]) node can_allocate_38 = neq(_can_allocate_T_38, UInt<1>(0h0)) node _T_850 = eq(_T_849, UInt<1>(0h0)) node _T_851 = and(issue_slots[12].request, _T_850) node _T_852 = and(_T_851, can_allocate_38) node _T_853 = eq(_T_819, UInt<1>(0h0)) node _T_854 = and(_T_852, _T_853) when _T_854 : connect issue_slots[12].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[12].uop node _T_855 = eq(_T_849, UInt<1>(0h0)) node _T_856 = and(issue_slots[12].request, _T_855) node _T_857 = and(_T_856, can_allocate_38) node _T_858 = or(_T_857, _T_819) node _T_859 = and(issue_slots[12].request, can_allocate_38) node _T_860 = eq(_T_819, UInt<1>(0h0)) node _T_861 = and(_T_859, _T_860) node _T_862 = or(_T_861, _T_849) connect issue_slots[13].grant, UInt<1>(0h0) node _can_allocate_T_39 = and(issue_slots[13].uop.fu_code, io.fu_types[0]) node can_allocate_39 = neq(_can_allocate_T_39, UInt<1>(0h0)) node _T_863 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = and(issue_slots[13].request, _T_863) node _T_865 = and(_T_864, can_allocate_39) node _T_866 = eq(_T_832, UInt<1>(0h0)) node _T_867 = and(_T_865, _T_866) when _T_867 : connect issue_slots[13].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[13].uop node _T_868 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_869 = and(issue_slots[13].request, _T_868) node _T_870 = and(_T_869, can_allocate_39) node _T_871 = or(_T_870, _T_832) node _T_872 = and(issue_slots[13].request, can_allocate_39) node _T_873 = eq(_T_832, UInt<1>(0h0)) node _T_874 = and(_T_872, _T_873) node _T_875 = or(_T_874, UInt<1>(0h0)) node _can_allocate_T_40 = and(issue_slots[13].uop.fu_code, io.fu_types[1]) node can_allocate_40 = neq(_can_allocate_T_40, UInt<1>(0h0)) node _T_876 = eq(_T_875, UInt<1>(0h0)) node _T_877 = and(issue_slots[13].request, _T_876) node _T_878 = and(_T_877, can_allocate_40) node _T_879 = eq(_T_845, UInt<1>(0h0)) node _T_880 = and(_T_878, _T_879) when _T_880 : connect issue_slots[13].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[13].uop node _T_881 = eq(_T_875, UInt<1>(0h0)) node _T_882 = and(issue_slots[13].request, _T_881) node _T_883 = and(_T_882, can_allocate_40) node _T_884 = or(_T_883, _T_845) node _T_885 = and(issue_slots[13].request, can_allocate_40) node _T_886 = eq(_T_845, UInt<1>(0h0)) node _T_887 = and(_T_885, _T_886) node _T_888 = or(_T_887, _T_875) node _can_allocate_T_41 = and(issue_slots[13].uop.fu_code, io.fu_types[2]) node can_allocate_41 = neq(_can_allocate_T_41, UInt<1>(0h0)) node _T_889 = eq(_T_888, UInt<1>(0h0)) node _T_890 = and(issue_slots[13].request, _T_889) node _T_891 = and(_T_890, can_allocate_41) node _T_892 = eq(_T_858, UInt<1>(0h0)) node _T_893 = and(_T_891, _T_892) when _T_893 : connect issue_slots[13].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[13].uop node _T_894 = eq(_T_888, UInt<1>(0h0)) node _T_895 = and(issue_slots[13].request, _T_894) node _T_896 = and(_T_895, can_allocate_41) node _T_897 = or(_T_896, _T_858) node _T_898 = and(issue_slots[13].request, can_allocate_41) node _T_899 = eq(_T_858, UInt<1>(0h0)) node _T_900 = and(_T_898, _T_899) node _T_901 = or(_T_900, _T_888) connect issue_slots[14].grant, UInt<1>(0h0) node _can_allocate_T_42 = and(issue_slots[14].uop.fu_code, io.fu_types[0]) node can_allocate_42 = neq(_can_allocate_T_42, UInt<1>(0h0)) node _T_902 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_903 = and(issue_slots[14].request, _T_902) node _T_904 = and(_T_903, can_allocate_42) node _T_905 = eq(_T_871, UInt<1>(0h0)) node _T_906 = and(_T_904, _T_905) when _T_906 : connect issue_slots[14].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[14].uop node _T_907 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_908 = and(issue_slots[14].request, _T_907) node _T_909 = and(_T_908, can_allocate_42) node _T_910 = or(_T_909, _T_871) node _T_911 = and(issue_slots[14].request, can_allocate_42) node _T_912 = eq(_T_871, UInt<1>(0h0)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(_T_913, UInt<1>(0h0)) node _can_allocate_T_43 = and(issue_slots[14].uop.fu_code, io.fu_types[1]) node can_allocate_43 = neq(_can_allocate_T_43, UInt<1>(0h0)) node _T_915 = eq(_T_914, UInt<1>(0h0)) node _T_916 = and(issue_slots[14].request, _T_915) node _T_917 = and(_T_916, can_allocate_43) node _T_918 = eq(_T_884, UInt<1>(0h0)) node _T_919 = and(_T_917, _T_918) when _T_919 : connect issue_slots[14].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[14].uop node _T_920 = eq(_T_914, UInt<1>(0h0)) node _T_921 = and(issue_slots[14].request, _T_920) node _T_922 = and(_T_921, can_allocate_43) node _T_923 = or(_T_922, _T_884) node _T_924 = and(issue_slots[14].request, can_allocate_43) node _T_925 = eq(_T_884, UInt<1>(0h0)) node _T_926 = and(_T_924, _T_925) node _T_927 = or(_T_926, _T_914) node _can_allocate_T_44 = and(issue_slots[14].uop.fu_code, io.fu_types[2]) node can_allocate_44 = neq(_can_allocate_T_44, UInt<1>(0h0)) node _T_928 = eq(_T_927, UInt<1>(0h0)) node _T_929 = and(issue_slots[14].request, _T_928) node _T_930 = and(_T_929, can_allocate_44) node _T_931 = eq(_T_897, UInt<1>(0h0)) node _T_932 = and(_T_930, _T_931) when _T_932 : connect issue_slots[14].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[14].uop node _T_933 = eq(_T_927, UInt<1>(0h0)) node _T_934 = and(issue_slots[14].request, _T_933) node _T_935 = and(_T_934, can_allocate_44) node _T_936 = or(_T_935, _T_897) node _T_937 = and(issue_slots[14].request, can_allocate_44) node _T_938 = eq(_T_897, UInt<1>(0h0)) node _T_939 = and(_T_937, _T_938) node _T_940 = or(_T_939, _T_927) connect issue_slots[15].grant, UInt<1>(0h0) node _can_allocate_T_45 = and(issue_slots[15].uop.fu_code, io.fu_types[0]) node can_allocate_45 = neq(_can_allocate_T_45, UInt<1>(0h0)) node _T_941 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_942 = and(issue_slots[15].request, _T_941) node _T_943 = and(_T_942, can_allocate_45) node _T_944 = eq(_T_910, UInt<1>(0h0)) node _T_945 = and(_T_943, _T_944) when _T_945 : connect issue_slots[15].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[15].uop node _T_946 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = and(issue_slots[15].request, _T_946) node _T_948 = and(_T_947, can_allocate_45) node _T_949 = or(_T_948, _T_910) node _T_950 = and(issue_slots[15].request, can_allocate_45) node _T_951 = eq(_T_910, UInt<1>(0h0)) node _T_952 = and(_T_950, _T_951) node _T_953 = or(_T_952, UInt<1>(0h0)) node _can_allocate_T_46 = and(issue_slots[15].uop.fu_code, io.fu_types[1]) node can_allocate_46 = neq(_can_allocate_T_46, UInt<1>(0h0)) node _T_954 = eq(_T_953, UInt<1>(0h0)) node _T_955 = and(issue_slots[15].request, _T_954) node _T_956 = and(_T_955, can_allocate_46) node _T_957 = eq(_T_923, UInt<1>(0h0)) node _T_958 = and(_T_956, _T_957) when _T_958 : connect issue_slots[15].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[15].uop node _T_959 = eq(_T_953, UInt<1>(0h0)) node _T_960 = and(issue_slots[15].request, _T_959) node _T_961 = and(_T_960, can_allocate_46) node _T_962 = or(_T_961, _T_923) node _T_963 = and(issue_slots[15].request, can_allocate_46) node _T_964 = eq(_T_923, UInt<1>(0h0)) node _T_965 = and(_T_963, _T_964) node _T_966 = or(_T_965, _T_953) node _can_allocate_T_47 = and(issue_slots[15].uop.fu_code, io.fu_types[2]) node can_allocate_47 = neq(_can_allocate_T_47, UInt<1>(0h0)) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = and(issue_slots[15].request, _T_967) node _T_969 = and(_T_968, can_allocate_47) node _T_970 = eq(_T_936, UInt<1>(0h0)) node _T_971 = and(_T_969, _T_970) when _T_971 : connect issue_slots[15].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[15].uop node _T_972 = eq(_T_966, UInt<1>(0h0)) node _T_973 = and(issue_slots[15].request, _T_972) node _T_974 = and(_T_973, can_allocate_47) node _T_975 = or(_T_974, _T_936) node _T_976 = and(issue_slots[15].request, can_allocate_47) node _T_977 = eq(_T_936, UInt<1>(0h0)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(_T_978, _T_966) connect issue_slots[16].grant, UInt<1>(0h0) node _can_allocate_T_48 = and(issue_slots[16].uop.fu_code, io.fu_types[0]) node can_allocate_48 = neq(_can_allocate_T_48, UInt<1>(0h0)) node _T_980 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_981 = and(issue_slots[16].request, _T_980) node _T_982 = and(_T_981, can_allocate_48) node _T_983 = eq(_T_949, UInt<1>(0h0)) node _T_984 = and(_T_982, _T_983) when _T_984 : connect issue_slots[16].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[16].uop node _T_985 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_986 = and(issue_slots[16].request, _T_985) node _T_987 = and(_T_986, can_allocate_48) node _T_988 = or(_T_987, _T_949) node _T_989 = and(issue_slots[16].request, can_allocate_48) node _T_990 = eq(_T_949, UInt<1>(0h0)) node _T_991 = and(_T_989, _T_990) node _T_992 = or(_T_991, UInt<1>(0h0)) node _can_allocate_T_49 = and(issue_slots[16].uop.fu_code, io.fu_types[1]) node can_allocate_49 = neq(_can_allocate_T_49, UInt<1>(0h0)) node _T_993 = eq(_T_992, UInt<1>(0h0)) node _T_994 = and(issue_slots[16].request, _T_993) node _T_995 = and(_T_994, can_allocate_49) node _T_996 = eq(_T_962, UInt<1>(0h0)) node _T_997 = and(_T_995, _T_996) when _T_997 : connect issue_slots[16].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[16].uop node _T_998 = eq(_T_992, UInt<1>(0h0)) node _T_999 = and(issue_slots[16].request, _T_998) node _T_1000 = and(_T_999, can_allocate_49) node _T_1001 = or(_T_1000, _T_962) node _T_1002 = and(issue_slots[16].request, can_allocate_49) node _T_1003 = eq(_T_962, UInt<1>(0h0)) node _T_1004 = and(_T_1002, _T_1003) node _T_1005 = or(_T_1004, _T_992) node _can_allocate_T_50 = and(issue_slots[16].uop.fu_code, io.fu_types[2]) node can_allocate_50 = neq(_can_allocate_T_50, UInt<1>(0h0)) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) node _T_1007 = and(issue_slots[16].request, _T_1006) node _T_1008 = and(_T_1007, can_allocate_50) node _T_1009 = eq(_T_975, UInt<1>(0h0)) node _T_1010 = and(_T_1008, _T_1009) when _T_1010 : connect issue_slots[16].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[16].uop node _T_1011 = eq(_T_1005, UInt<1>(0h0)) node _T_1012 = and(issue_slots[16].request, _T_1011) node _T_1013 = and(_T_1012, can_allocate_50) node _T_1014 = or(_T_1013, _T_975) node _T_1015 = and(issue_slots[16].request, can_allocate_50) node _T_1016 = eq(_T_975, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = or(_T_1017, _T_1005) connect issue_slots[17].grant, UInt<1>(0h0) node _can_allocate_T_51 = and(issue_slots[17].uop.fu_code, io.fu_types[0]) node can_allocate_51 = neq(_can_allocate_T_51, UInt<1>(0h0)) node _T_1019 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1020 = and(issue_slots[17].request, _T_1019) node _T_1021 = and(_T_1020, can_allocate_51) node _T_1022 = eq(_T_988, UInt<1>(0h0)) node _T_1023 = and(_T_1021, _T_1022) when _T_1023 : connect issue_slots[17].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[17].uop node _T_1024 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1025 = and(issue_slots[17].request, _T_1024) node _T_1026 = and(_T_1025, can_allocate_51) node _T_1027 = or(_T_1026, _T_988) node _T_1028 = and(issue_slots[17].request, can_allocate_51) node _T_1029 = eq(_T_988, UInt<1>(0h0)) node _T_1030 = and(_T_1028, _T_1029) node _T_1031 = or(_T_1030, UInt<1>(0h0)) node _can_allocate_T_52 = and(issue_slots[17].uop.fu_code, io.fu_types[1]) node can_allocate_52 = neq(_can_allocate_T_52, UInt<1>(0h0)) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = and(issue_slots[17].request, _T_1032) node _T_1034 = and(_T_1033, can_allocate_52) node _T_1035 = eq(_T_1001, UInt<1>(0h0)) node _T_1036 = and(_T_1034, _T_1035) when _T_1036 : connect issue_slots[17].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[17].uop node _T_1037 = eq(_T_1031, UInt<1>(0h0)) node _T_1038 = and(issue_slots[17].request, _T_1037) node _T_1039 = and(_T_1038, can_allocate_52) node _T_1040 = or(_T_1039, _T_1001) node _T_1041 = and(issue_slots[17].request, can_allocate_52) node _T_1042 = eq(_T_1001, UInt<1>(0h0)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = or(_T_1043, _T_1031) node _can_allocate_T_53 = and(issue_slots[17].uop.fu_code, io.fu_types[2]) node can_allocate_53 = neq(_can_allocate_T_53, UInt<1>(0h0)) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) node _T_1046 = and(issue_slots[17].request, _T_1045) node _T_1047 = and(_T_1046, can_allocate_53) node _T_1048 = eq(_T_1014, UInt<1>(0h0)) node _T_1049 = and(_T_1047, _T_1048) when _T_1049 : connect issue_slots[17].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[17].uop node _T_1050 = eq(_T_1044, UInt<1>(0h0)) node _T_1051 = and(issue_slots[17].request, _T_1050) node _T_1052 = and(_T_1051, can_allocate_53) node _T_1053 = or(_T_1052, _T_1014) node _T_1054 = and(issue_slots[17].request, can_allocate_53) node _T_1055 = eq(_T_1014, UInt<1>(0h0)) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = or(_T_1056, _T_1044) connect issue_slots[18].grant, UInt<1>(0h0) node _can_allocate_T_54 = and(issue_slots[18].uop.fu_code, io.fu_types[0]) node can_allocate_54 = neq(_can_allocate_T_54, UInt<1>(0h0)) node _T_1058 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1059 = and(issue_slots[18].request, _T_1058) node _T_1060 = and(_T_1059, can_allocate_54) node _T_1061 = eq(_T_1027, UInt<1>(0h0)) node _T_1062 = and(_T_1060, _T_1061) when _T_1062 : connect issue_slots[18].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[18].uop node _T_1063 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1064 = and(issue_slots[18].request, _T_1063) node _T_1065 = and(_T_1064, can_allocate_54) node _T_1066 = or(_T_1065, _T_1027) node _T_1067 = and(issue_slots[18].request, can_allocate_54) node _T_1068 = eq(_T_1027, UInt<1>(0h0)) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = or(_T_1069, UInt<1>(0h0)) node _can_allocate_T_55 = and(issue_slots[18].uop.fu_code, io.fu_types[1]) node can_allocate_55 = neq(_can_allocate_T_55, UInt<1>(0h0)) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) node _T_1072 = and(issue_slots[18].request, _T_1071) node _T_1073 = and(_T_1072, can_allocate_55) node _T_1074 = eq(_T_1040, UInt<1>(0h0)) node _T_1075 = and(_T_1073, _T_1074) when _T_1075 : connect issue_slots[18].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[18].uop node _T_1076 = eq(_T_1070, UInt<1>(0h0)) node _T_1077 = and(issue_slots[18].request, _T_1076) node _T_1078 = and(_T_1077, can_allocate_55) node _T_1079 = or(_T_1078, _T_1040) node _T_1080 = and(issue_slots[18].request, can_allocate_55) node _T_1081 = eq(_T_1040, UInt<1>(0h0)) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = or(_T_1082, _T_1070) node _can_allocate_T_56 = and(issue_slots[18].uop.fu_code, io.fu_types[2]) node can_allocate_56 = neq(_can_allocate_T_56, UInt<1>(0h0)) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) node _T_1085 = and(issue_slots[18].request, _T_1084) node _T_1086 = and(_T_1085, can_allocate_56) node _T_1087 = eq(_T_1053, UInt<1>(0h0)) node _T_1088 = and(_T_1086, _T_1087) when _T_1088 : connect issue_slots[18].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[18].uop node _T_1089 = eq(_T_1083, UInt<1>(0h0)) node _T_1090 = and(issue_slots[18].request, _T_1089) node _T_1091 = and(_T_1090, can_allocate_56) node _T_1092 = or(_T_1091, _T_1053) node _T_1093 = and(issue_slots[18].request, can_allocate_56) node _T_1094 = eq(_T_1053, UInt<1>(0h0)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = or(_T_1095, _T_1083) connect issue_slots[19].grant, UInt<1>(0h0) node _can_allocate_T_57 = and(issue_slots[19].uop.fu_code, io.fu_types[0]) node can_allocate_57 = neq(_can_allocate_T_57, UInt<1>(0h0)) node _T_1097 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1098 = and(issue_slots[19].request, _T_1097) node _T_1099 = and(_T_1098, can_allocate_57) node _T_1100 = eq(_T_1066, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : connect issue_slots[19].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[19].uop node _T_1102 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1103 = and(issue_slots[19].request, _T_1102) node _T_1104 = and(_T_1103, can_allocate_57) node _T_1105 = or(_T_1104, _T_1066) node _T_1106 = and(issue_slots[19].request, can_allocate_57) node _T_1107 = eq(_T_1066, UInt<1>(0h0)) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = or(_T_1108, UInt<1>(0h0)) node _can_allocate_T_58 = and(issue_slots[19].uop.fu_code, io.fu_types[1]) node can_allocate_58 = neq(_can_allocate_T_58, UInt<1>(0h0)) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = and(issue_slots[19].request, _T_1110) node _T_1112 = and(_T_1111, can_allocate_58) node _T_1113 = eq(_T_1079, UInt<1>(0h0)) node _T_1114 = and(_T_1112, _T_1113) when _T_1114 : connect issue_slots[19].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[19].uop node _T_1115 = eq(_T_1109, UInt<1>(0h0)) node _T_1116 = and(issue_slots[19].request, _T_1115) node _T_1117 = and(_T_1116, can_allocate_58) node _T_1118 = or(_T_1117, _T_1079) node _T_1119 = and(issue_slots[19].request, can_allocate_58) node _T_1120 = eq(_T_1079, UInt<1>(0h0)) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = or(_T_1121, _T_1109) node _can_allocate_T_59 = and(issue_slots[19].uop.fu_code, io.fu_types[2]) node can_allocate_59 = neq(_can_allocate_T_59, UInt<1>(0h0)) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) node _T_1124 = and(issue_slots[19].request, _T_1123) node _T_1125 = and(_T_1124, can_allocate_59) node _T_1126 = eq(_T_1092, UInt<1>(0h0)) node _T_1127 = and(_T_1125, _T_1126) when _T_1127 : connect issue_slots[19].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[19].uop node _T_1128 = eq(_T_1122, UInt<1>(0h0)) node _T_1129 = and(issue_slots[19].request, _T_1128) node _T_1130 = and(_T_1129, can_allocate_59) node _T_1131 = or(_T_1130, _T_1092) node _T_1132 = and(issue_slots[19].request, can_allocate_59) node _T_1133 = eq(_T_1092, UInt<1>(0h0)) node _T_1134 = and(_T_1132, _T_1133) node _T_1135 = or(_T_1134, _T_1122) connect issue_slots[20].grant, UInt<1>(0h0) node _can_allocate_T_60 = and(issue_slots[20].uop.fu_code, io.fu_types[0]) node can_allocate_60 = neq(_can_allocate_T_60, UInt<1>(0h0)) node _T_1136 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1137 = and(issue_slots[20].request, _T_1136) node _T_1138 = and(_T_1137, can_allocate_60) node _T_1139 = eq(_T_1105, UInt<1>(0h0)) node _T_1140 = and(_T_1138, _T_1139) when _T_1140 : connect issue_slots[20].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[20].uop node _T_1141 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1142 = and(issue_slots[20].request, _T_1141) node _T_1143 = and(_T_1142, can_allocate_60) node _T_1144 = or(_T_1143, _T_1105) node _T_1145 = and(issue_slots[20].request, can_allocate_60) node _T_1146 = eq(_T_1105, UInt<1>(0h0)) node _T_1147 = and(_T_1145, _T_1146) node _T_1148 = or(_T_1147, UInt<1>(0h0)) node _can_allocate_T_61 = and(issue_slots[20].uop.fu_code, io.fu_types[1]) node can_allocate_61 = neq(_can_allocate_T_61, UInt<1>(0h0)) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) node _T_1150 = and(issue_slots[20].request, _T_1149) node _T_1151 = and(_T_1150, can_allocate_61) node _T_1152 = eq(_T_1118, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : connect issue_slots[20].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[20].uop node _T_1154 = eq(_T_1148, UInt<1>(0h0)) node _T_1155 = and(issue_slots[20].request, _T_1154) node _T_1156 = and(_T_1155, can_allocate_61) node _T_1157 = or(_T_1156, _T_1118) node _T_1158 = and(issue_slots[20].request, can_allocate_61) node _T_1159 = eq(_T_1118, UInt<1>(0h0)) node _T_1160 = and(_T_1158, _T_1159) node _T_1161 = or(_T_1160, _T_1148) node _can_allocate_T_62 = and(issue_slots[20].uop.fu_code, io.fu_types[2]) node can_allocate_62 = neq(_can_allocate_T_62, UInt<1>(0h0)) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) node _T_1163 = and(issue_slots[20].request, _T_1162) node _T_1164 = and(_T_1163, can_allocate_62) node _T_1165 = eq(_T_1131, UInt<1>(0h0)) node _T_1166 = and(_T_1164, _T_1165) when _T_1166 : connect issue_slots[20].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[20].uop node _T_1167 = eq(_T_1161, UInt<1>(0h0)) node _T_1168 = and(issue_slots[20].request, _T_1167) node _T_1169 = and(_T_1168, can_allocate_62) node _T_1170 = or(_T_1169, _T_1131) node _T_1171 = and(issue_slots[20].request, can_allocate_62) node _T_1172 = eq(_T_1131, UInt<1>(0h0)) node _T_1173 = and(_T_1171, _T_1172) node _T_1174 = or(_T_1173, _T_1161) connect issue_slots[21].grant, UInt<1>(0h0) node _can_allocate_T_63 = and(issue_slots[21].uop.fu_code, io.fu_types[0]) node can_allocate_63 = neq(_can_allocate_T_63, UInt<1>(0h0)) node _T_1175 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1176 = and(issue_slots[21].request, _T_1175) node _T_1177 = and(_T_1176, can_allocate_63) node _T_1178 = eq(_T_1144, UInt<1>(0h0)) node _T_1179 = and(_T_1177, _T_1178) when _T_1179 : connect issue_slots[21].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[21].uop node _T_1180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1181 = and(issue_slots[21].request, _T_1180) node _T_1182 = and(_T_1181, can_allocate_63) node _T_1183 = or(_T_1182, _T_1144) node _T_1184 = and(issue_slots[21].request, can_allocate_63) node _T_1185 = eq(_T_1144, UInt<1>(0h0)) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = or(_T_1186, UInt<1>(0h0)) node _can_allocate_T_64 = and(issue_slots[21].uop.fu_code, io.fu_types[1]) node can_allocate_64 = neq(_can_allocate_T_64, UInt<1>(0h0)) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) node _T_1189 = and(issue_slots[21].request, _T_1188) node _T_1190 = and(_T_1189, can_allocate_64) node _T_1191 = eq(_T_1157, UInt<1>(0h0)) node _T_1192 = and(_T_1190, _T_1191) when _T_1192 : connect issue_slots[21].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[21].uop node _T_1193 = eq(_T_1187, UInt<1>(0h0)) node _T_1194 = and(issue_slots[21].request, _T_1193) node _T_1195 = and(_T_1194, can_allocate_64) node _T_1196 = or(_T_1195, _T_1157) node _T_1197 = and(issue_slots[21].request, can_allocate_64) node _T_1198 = eq(_T_1157, UInt<1>(0h0)) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = or(_T_1199, _T_1187) node _can_allocate_T_65 = and(issue_slots[21].uop.fu_code, io.fu_types[2]) node can_allocate_65 = neq(_can_allocate_T_65, UInt<1>(0h0)) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = and(issue_slots[21].request, _T_1201) node _T_1203 = and(_T_1202, can_allocate_65) node _T_1204 = eq(_T_1170, UInt<1>(0h0)) node _T_1205 = and(_T_1203, _T_1204) when _T_1205 : connect issue_slots[21].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[21].uop node _T_1206 = eq(_T_1200, UInt<1>(0h0)) node _T_1207 = and(issue_slots[21].request, _T_1206) node _T_1208 = and(_T_1207, can_allocate_65) node _T_1209 = or(_T_1208, _T_1170) node _T_1210 = and(issue_slots[21].request, can_allocate_65) node _T_1211 = eq(_T_1170, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = or(_T_1212, _T_1200) connect issue_slots[22].grant, UInt<1>(0h0) node _can_allocate_T_66 = and(issue_slots[22].uop.fu_code, io.fu_types[0]) node can_allocate_66 = neq(_can_allocate_T_66, UInt<1>(0h0)) node _T_1214 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1215 = and(issue_slots[22].request, _T_1214) node _T_1216 = and(_T_1215, can_allocate_66) node _T_1217 = eq(_T_1183, UInt<1>(0h0)) node _T_1218 = and(_T_1216, _T_1217) when _T_1218 : connect issue_slots[22].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[22].uop node _T_1219 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1220 = and(issue_slots[22].request, _T_1219) node _T_1221 = and(_T_1220, can_allocate_66) node _T_1222 = or(_T_1221, _T_1183) node _T_1223 = and(issue_slots[22].request, can_allocate_66) node _T_1224 = eq(_T_1183, UInt<1>(0h0)) node _T_1225 = and(_T_1223, _T_1224) node _T_1226 = or(_T_1225, UInt<1>(0h0)) node _can_allocate_T_67 = and(issue_slots[22].uop.fu_code, io.fu_types[1]) node can_allocate_67 = neq(_can_allocate_T_67, UInt<1>(0h0)) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) node _T_1228 = and(issue_slots[22].request, _T_1227) node _T_1229 = and(_T_1228, can_allocate_67) node _T_1230 = eq(_T_1196, UInt<1>(0h0)) node _T_1231 = and(_T_1229, _T_1230) when _T_1231 : connect issue_slots[22].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[22].uop node _T_1232 = eq(_T_1226, UInt<1>(0h0)) node _T_1233 = and(issue_slots[22].request, _T_1232) node _T_1234 = and(_T_1233, can_allocate_67) node _T_1235 = or(_T_1234, _T_1196) node _T_1236 = and(issue_slots[22].request, can_allocate_67) node _T_1237 = eq(_T_1196, UInt<1>(0h0)) node _T_1238 = and(_T_1236, _T_1237) node _T_1239 = or(_T_1238, _T_1226) node _can_allocate_T_68 = and(issue_slots[22].uop.fu_code, io.fu_types[2]) node can_allocate_68 = neq(_can_allocate_T_68, UInt<1>(0h0)) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) node _T_1241 = and(issue_slots[22].request, _T_1240) node _T_1242 = and(_T_1241, can_allocate_68) node _T_1243 = eq(_T_1209, UInt<1>(0h0)) node _T_1244 = and(_T_1242, _T_1243) when _T_1244 : connect issue_slots[22].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[22].uop node _T_1245 = eq(_T_1239, UInt<1>(0h0)) node _T_1246 = and(issue_slots[22].request, _T_1245) node _T_1247 = and(_T_1246, can_allocate_68) node _T_1248 = or(_T_1247, _T_1209) node _T_1249 = and(issue_slots[22].request, can_allocate_68) node _T_1250 = eq(_T_1209, UInt<1>(0h0)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = or(_T_1251, _T_1239) connect issue_slots[23].grant, UInt<1>(0h0) node _can_allocate_T_69 = and(issue_slots[23].uop.fu_code, io.fu_types[0]) node can_allocate_69 = neq(_can_allocate_T_69, UInt<1>(0h0)) node _T_1253 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = and(issue_slots[23].request, _T_1253) node _T_1255 = and(_T_1254, can_allocate_69) node _T_1256 = eq(_T_1222, UInt<1>(0h0)) node _T_1257 = and(_T_1255, _T_1256) when _T_1257 : connect issue_slots[23].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[23].uop node _T_1258 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1259 = and(issue_slots[23].request, _T_1258) node _T_1260 = and(_T_1259, can_allocate_69) node _T_1261 = or(_T_1260, _T_1222) node _T_1262 = and(issue_slots[23].request, can_allocate_69) node _T_1263 = eq(_T_1222, UInt<1>(0h0)) node _T_1264 = and(_T_1262, _T_1263) node _T_1265 = or(_T_1264, UInt<1>(0h0)) node _can_allocate_T_70 = and(issue_slots[23].uop.fu_code, io.fu_types[1]) node can_allocate_70 = neq(_can_allocate_T_70, UInt<1>(0h0)) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) node _T_1267 = and(issue_slots[23].request, _T_1266) node _T_1268 = and(_T_1267, can_allocate_70) node _T_1269 = eq(_T_1235, UInt<1>(0h0)) node _T_1270 = and(_T_1268, _T_1269) when _T_1270 : connect issue_slots[23].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[23].uop node _T_1271 = eq(_T_1265, UInt<1>(0h0)) node _T_1272 = and(issue_slots[23].request, _T_1271) node _T_1273 = and(_T_1272, can_allocate_70) node _T_1274 = or(_T_1273, _T_1235) node _T_1275 = and(issue_slots[23].request, can_allocate_70) node _T_1276 = eq(_T_1235, UInt<1>(0h0)) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = or(_T_1277, _T_1265) node _can_allocate_T_71 = and(issue_slots[23].uop.fu_code, io.fu_types[2]) node can_allocate_71 = neq(_can_allocate_T_71, UInt<1>(0h0)) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) node _T_1280 = and(issue_slots[23].request, _T_1279) node _T_1281 = and(_T_1280, can_allocate_71) node _T_1282 = eq(_T_1248, UInt<1>(0h0)) node _T_1283 = and(_T_1281, _T_1282) when _T_1283 : connect issue_slots[23].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[23].uop node _T_1284 = eq(_T_1278, UInt<1>(0h0)) node _T_1285 = and(issue_slots[23].request, _T_1284) node _T_1286 = and(_T_1285, can_allocate_71) node _T_1287 = or(_T_1286, _T_1248) node _T_1288 = and(issue_slots[23].request, can_allocate_71) node _T_1289 = eq(_T_1248, UInt<1>(0h0)) node _T_1290 = and(_T_1288, _T_1289) node _T_1291 = or(_T_1290, _T_1278) connect issue_slots[24].grant, UInt<1>(0h0) node _can_allocate_T_72 = and(issue_slots[24].uop.fu_code, io.fu_types[0]) node can_allocate_72 = neq(_can_allocate_T_72, UInt<1>(0h0)) node _T_1292 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1293 = and(issue_slots[24].request, _T_1292) node _T_1294 = and(_T_1293, can_allocate_72) node _T_1295 = eq(_T_1261, UInt<1>(0h0)) node _T_1296 = and(_T_1294, _T_1295) when _T_1296 : connect issue_slots[24].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[24].uop node _T_1297 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1298 = and(issue_slots[24].request, _T_1297) node _T_1299 = and(_T_1298, can_allocate_72) node _T_1300 = or(_T_1299, _T_1261) node _T_1301 = and(issue_slots[24].request, can_allocate_72) node _T_1302 = eq(_T_1261, UInt<1>(0h0)) node _T_1303 = and(_T_1301, _T_1302) node _T_1304 = or(_T_1303, UInt<1>(0h0)) node _can_allocate_T_73 = and(issue_slots[24].uop.fu_code, io.fu_types[1]) node can_allocate_73 = neq(_can_allocate_T_73, UInt<1>(0h0)) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) node _T_1306 = and(issue_slots[24].request, _T_1305) node _T_1307 = and(_T_1306, can_allocate_73) node _T_1308 = eq(_T_1274, UInt<1>(0h0)) node _T_1309 = and(_T_1307, _T_1308) when _T_1309 : connect issue_slots[24].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[24].uop node _T_1310 = eq(_T_1304, UInt<1>(0h0)) node _T_1311 = and(issue_slots[24].request, _T_1310) node _T_1312 = and(_T_1311, can_allocate_73) node _T_1313 = or(_T_1312, _T_1274) node _T_1314 = and(issue_slots[24].request, can_allocate_73) node _T_1315 = eq(_T_1274, UInt<1>(0h0)) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = or(_T_1316, _T_1304) node _can_allocate_T_74 = and(issue_slots[24].uop.fu_code, io.fu_types[2]) node can_allocate_74 = neq(_can_allocate_T_74, UInt<1>(0h0)) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = and(issue_slots[24].request, _T_1318) node _T_1320 = and(_T_1319, can_allocate_74) node _T_1321 = eq(_T_1287, UInt<1>(0h0)) node _T_1322 = and(_T_1320, _T_1321) when _T_1322 : connect issue_slots[24].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[24].uop node _T_1323 = eq(_T_1317, UInt<1>(0h0)) node _T_1324 = and(issue_slots[24].request, _T_1323) node _T_1325 = and(_T_1324, can_allocate_74) node _T_1326 = or(_T_1325, _T_1287) node _T_1327 = and(issue_slots[24].request, can_allocate_74) node _T_1328 = eq(_T_1287, UInt<1>(0h0)) node _T_1329 = and(_T_1327, _T_1328) node _T_1330 = or(_T_1329, _T_1317) connect issue_slots[25].grant, UInt<1>(0h0) node _can_allocate_T_75 = and(issue_slots[25].uop.fu_code, io.fu_types[0]) node can_allocate_75 = neq(_can_allocate_T_75, UInt<1>(0h0)) node _T_1331 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1332 = and(issue_slots[25].request, _T_1331) node _T_1333 = and(_T_1332, can_allocate_75) node _T_1334 = eq(_T_1300, UInt<1>(0h0)) node _T_1335 = and(_T_1333, _T_1334) when _T_1335 : connect issue_slots[25].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[25].uop node _T_1336 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1337 = and(issue_slots[25].request, _T_1336) node _T_1338 = and(_T_1337, can_allocate_75) node _T_1339 = or(_T_1338, _T_1300) node _T_1340 = and(issue_slots[25].request, can_allocate_75) node _T_1341 = eq(_T_1300, UInt<1>(0h0)) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = or(_T_1342, UInt<1>(0h0)) node _can_allocate_T_76 = and(issue_slots[25].uop.fu_code, io.fu_types[1]) node can_allocate_76 = neq(_can_allocate_T_76, UInt<1>(0h0)) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) node _T_1345 = and(issue_slots[25].request, _T_1344) node _T_1346 = and(_T_1345, can_allocate_76) node _T_1347 = eq(_T_1313, UInt<1>(0h0)) node _T_1348 = and(_T_1346, _T_1347) when _T_1348 : connect issue_slots[25].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[25].uop node _T_1349 = eq(_T_1343, UInt<1>(0h0)) node _T_1350 = and(issue_slots[25].request, _T_1349) node _T_1351 = and(_T_1350, can_allocate_76) node _T_1352 = or(_T_1351, _T_1313) node _T_1353 = and(issue_slots[25].request, can_allocate_76) node _T_1354 = eq(_T_1313, UInt<1>(0h0)) node _T_1355 = and(_T_1353, _T_1354) node _T_1356 = or(_T_1355, _T_1343) node _can_allocate_T_77 = and(issue_slots[25].uop.fu_code, io.fu_types[2]) node can_allocate_77 = neq(_can_allocate_T_77, UInt<1>(0h0)) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) node _T_1358 = and(issue_slots[25].request, _T_1357) node _T_1359 = and(_T_1358, can_allocate_77) node _T_1360 = eq(_T_1326, UInt<1>(0h0)) node _T_1361 = and(_T_1359, _T_1360) when _T_1361 : connect issue_slots[25].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[25].uop node _T_1362 = eq(_T_1356, UInt<1>(0h0)) node _T_1363 = and(issue_slots[25].request, _T_1362) node _T_1364 = and(_T_1363, can_allocate_77) node _T_1365 = or(_T_1364, _T_1326) node _T_1366 = and(issue_slots[25].request, can_allocate_77) node _T_1367 = eq(_T_1326, UInt<1>(0h0)) node _T_1368 = and(_T_1366, _T_1367) node _T_1369 = or(_T_1368, _T_1356) connect issue_slots[26].grant, UInt<1>(0h0) node _can_allocate_T_78 = and(issue_slots[26].uop.fu_code, io.fu_types[0]) node can_allocate_78 = neq(_can_allocate_T_78, UInt<1>(0h0)) node _T_1370 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1371 = and(issue_slots[26].request, _T_1370) node _T_1372 = and(_T_1371, can_allocate_78) node _T_1373 = eq(_T_1339, UInt<1>(0h0)) node _T_1374 = and(_T_1372, _T_1373) when _T_1374 : connect issue_slots[26].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[26].uop node _T_1375 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1376 = and(issue_slots[26].request, _T_1375) node _T_1377 = and(_T_1376, can_allocate_78) node _T_1378 = or(_T_1377, _T_1339) node _T_1379 = and(issue_slots[26].request, can_allocate_78) node _T_1380 = eq(_T_1339, UInt<1>(0h0)) node _T_1381 = and(_T_1379, _T_1380) node _T_1382 = or(_T_1381, UInt<1>(0h0)) node _can_allocate_T_79 = and(issue_slots[26].uop.fu_code, io.fu_types[1]) node can_allocate_79 = neq(_can_allocate_T_79, UInt<1>(0h0)) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) node _T_1384 = and(issue_slots[26].request, _T_1383) node _T_1385 = and(_T_1384, can_allocate_79) node _T_1386 = eq(_T_1352, UInt<1>(0h0)) node _T_1387 = and(_T_1385, _T_1386) when _T_1387 : connect issue_slots[26].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[26].uop node _T_1388 = eq(_T_1382, UInt<1>(0h0)) node _T_1389 = and(issue_slots[26].request, _T_1388) node _T_1390 = and(_T_1389, can_allocate_79) node _T_1391 = or(_T_1390, _T_1352) node _T_1392 = and(issue_slots[26].request, can_allocate_79) node _T_1393 = eq(_T_1352, UInt<1>(0h0)) node _T_1394 = and(_T_1392, _T_1393) node _T_1395 = or(_T_1394, _T_1382) node _can_allocate_T_80 = and(issue_slots[26].uop.fu_code, io.fu_types[2]) node can_allocate_80 = neq(_can_allocate_T_80, UInt<1>(0h0)) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) node _T_1397 = and(issue_slots[26].request, _T_1396) node _T_1398 = and(_T_1397, can_allocate_80) node _T_1399 = eq(_T_1365, UInt<1>(0h0)) node _T_1400 = and(_T_1398, _T_1399) when _T_1400 : connect issue_slots[26].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[26].uop node _T_1401 = eq(_T_1395, UInt<1>(0h0)) node _T_1402 = and(issue_slots[26].request, _T_1401) node _T_1403 = and(_T_1402, can_allocate_80) node _T_1404 = or(_T_1403, _T_1365) node _T_1405 = and(issue_slots[26].request, can_allocate_80) node _T_1406 = eq(_T_1365, UInt<1>(0h0)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = or(_T_1407, _T_1395) connect issue_slots[27].grant, UInt<1>(0h0) node _can_allocate_T_81 = and(issue_slots[27].uop.fu_code, io.fu_types[0]) node can_allocate_81 = neq(_can_allocate_T_81, UInt<1>(0h0)) node _T_1409 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1410 = and(issue_slots[27].request, _T_1409) node _T_1411 = and(_T_1410, can_allocate_81) node _T_1412 = eq(_T_1378, UInt<1>(0h0)) node _T_1413 = and(_T_1411, _T_1412) when _T_1413 : connect issue_slots[27].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[27].uop node _T_1414 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1415 = and(issue_slots[27].request, _T_1414) node _T_1416 = and(_T_1415, can_allocate_81) node _T_1417 = or(_T_1416, _T_1378) node _T_1418 = and(issue_slots[27].request, can_allocate_81) node _T_1419 = eq(_T_1378, UInt<1>(0h0)) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = or(_T_1420, UInt<1>(0h0)) node _can_allocate_T_82 = and(issue_slots[27].uop.fu_code, io.fu_types[1]) node can_allocate_82 = neq(_can_allocate_T_82, UInt<1>(0h0)) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) node _T_1423 = and(issue_slots[27].request, _T_1422) node _T_1424 = and(_T_1423, can_allocate_82) node _T_1425 = eq(_T_1391, UInt<1>(0h0)) node _T_1426 = and(_T_1424, _T_1425) when _T_1426 : connect issue_slots[27].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[27].uop node _T_1427 = eq(_T_1421, UInt<1>(0h0)) node _T_1428 = and(issue_slots[27].request, _T_1427) node _T_1429 = and(_T_1428, can_allocate_82) node _T_1430 = or(_T_1429, _T_1391) node _T_1431 = and(issue_slots[27].request, can_allocate_82) node _T_1432 = eq(_T_1391, UInt<1>(0h0)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(_T_1433, _T_1421) node _can_allocate_T_83 = and(issue_slots[27].uop.fu_code, io.fu_types[2]) node can_allocate_83 = neq(_can_allocate_T_83, UInt<1>(0h0)) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) node _T_1436 = and(issue_slots[27].request, _T_1435) node _T_1437 = and(_T_1436, can_allocate_83) node _T_1438 = eq(_T_1404, UInt<1>(0h0)) node _T_1439 = and(_T_1437, _T_1438) when _T_1439 : connect issue_slots[27].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[27].uop node _T_1440 = eq(_T_1434, UInt<1>(0h0)) node _T_1441 = and(issue_slots[27].request, _T_1440) node _T_1442 = and(_T_1441, can_allocate_83) node _T_1443 = or(_T_1442, _T_1404) node _T_1444 = and(issue_slots[27].request, can_allocate_83) node _T_1445 = eq(_T_1404, UInt<1>(0h0)) node _T_1446 = and(_T_1444, _T_1445) node _T_1447 = or(_T_1446, _T_1434) connect issue_slots[28].grant, UInt<1>(0h0) node _can_allocate_T_84 = and(issue_slots[28].uop.fu_code, io.fu_types[0]) node can_allocate_84 = neq(_can_allocate_T_84, UInt<1>(0h0)) node _T_1448 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1449 = and(issue_slots[28].request, _T_1448) node _T_1450 = and(_T_1449, can_allocate_84) node _T_1451 = eq(_T_1417, UInt<1>(0h0)) node _T_1452 = and(_T_1450, _T_1451) when _T_1452 : connect issue_slots[28].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[28].uop node _T_1453 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1454 = and(issue_slots[28].request, _T_1453) node _T_1455 = and(_T_1454, can_allocate_84) node _T_1456 = or(_T_1455, _T_1417) node _T_1457 = and(issue_slots[28].request, can_allocate_84) node _T_1458 = eq(_T_1417, UInt<1>(0h0)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = or(_T_1459, UInt<1>(0h0)) node _can_allocate_T_85 = and(issue_slots[28].uop.fu_code, io.fu_types[1]) node can_allocate_85 = neq(_can_allocate_T_85, UInt<1>(0h0)) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) node _T_1462 = and(issue_slots[28].request, _T_1461) node _T_1463 = and(_T_1462, can_allocate_85) node _T_1464 = eq(_T_1430, UInt<1>(0h0)) node _T_1465 = and(_T_1463, _T_1464) when _T_1465 : connect issue_slots[28].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[28].uop node _T_1466 = eq(_T_1460, UInt<1>(0h0)) node _T_1467 = and(issue_slots[28].request, _T_1466) node _T_1468 = and(_T_1467, can_allocate_85) node _T_1469 = or(_T_1468, _T_1430) node _T_1470 = and(issue_slots[28].request, can_allocate_85) node _T_1471 = eq(_T_1430, UInt<1>(0h0)) node _T_1472 = and(_T_1470, _T_1471) node _T_1473 = or(_T_1472, _T_1460) node _can_allocate_T_86 = and(issue_slots[28].uop.fu_code, io.fu_types[2]) node can_allocate_86 = neq(_can_allocate_T_86, UInt<1>(0h0)) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) node _T_1475 = and(issue_slots[28].request, _T_1474) node _T_1476 = and(_T_1475, can_allocate_86) node _T_1477 = eq(_T_1443, UInt<1>(0h0)) node _T_1478 = and(_T_1476, _T_1477) when _T_1478 : connect issue_slots[28].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[28].uop node _T_1479 = eq(_T_1473, UInt<1>(0h0)) node _T_1480 = and(issue_slots[28].request, _T_1479) node _T_1481 = and(_T_1480, can_allocate_86) node _T_1482 = or(_T_1481, _T_1443) node _T_1483 = and(issue_slots[28].request, can_allocate_86) node _T_1484 = eq(_T_1443, UInt<1>(0h0)) node _T_1485 = and(_T_1483, _T_1484) node _T_1486 = or(_T_1485, _T_1473) connect issue_slots[29].grant, UInt<1>(0h0) node _can_allocate_T_87 = and(issue_slots[29].uop.fu_code, io.fu_types[0]) node can_allocate_87 = neq(_can_allocate_T_87, UInt<1>(0h0)) node _T_1487 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1488 = and(issue_slots[29].request, _T_1487) node _T_1489 = and(_T_1488, can_allocate_87) node _T_1490 = eq(_T_1456, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect issue_slots[29].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[29].uop node _T_1492 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1493 = and(issue_slots[29].request, _T_1492) node _T_1494 = and(_T_1493, can_allocate_87) node _T_1495 = or(_T_1494, _T_1456) node _T_1496 = and(issue_slots[29].request, can_allocate_87) node _T_1497 = eq(_T_1456, UInt<1>(0h0)) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = or(_T_1498, UInt<1>(0h0)) node _can_allocate_T_88 = and(issue_slots[29].uop.fu_code, io.fu_types[1]) node can_allocate_88 = neq(_can_allocate_T_88, UInt<1>(0h0)) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) node _T_1501 = and(issue_slots[29].request, _T_1500) node _T_1502 = and(_T_1501, can_allocate_88) node _T_1503 = eq(_T_1469, UInt<1>(0h0)) node _T_1504 = and(_T_1502, _T_1503) when _T_1504 : connect issue_slots[29].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[29].uop node _T_1505 = eq(_T_1499, UInt<1>(0h0)) node _T_1506 = and(issue_slots[29].request, _T_1505) node _T_1507 = and(_T_1506, can_allocate_88) node _T_1508 = or(_T_1507, _T_1469) node _T_1509 = and(issue_slots[29].request, can_allocate_88) node _T_1510 = eq(_T_1469, UInt<1>(0h0)) node _T_1511 = and(_T_1509, _T_1510) node _T_1512 = or(_T_1511, _T_1499) node _can_allocate_T_89 = and(issue_slots[29].uop.fu_code, io.fu_types[2]) node can_allocate_89 = neq(_can_allocate_T_89, UInt<1>(0h0)) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) node _T_1514 = and(issue_slots[29].request, _T_1513) node _T_1515 = and(_T_1514, can_allocate_89) node _T_1516 = eq(_T_1482, UInt<1>(0h0)) node _T_1517 = and(_T_1515, _T_1516) when _T_1517 : connect issue_slots[29].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[29].uop node _T_1518 = eq(_T_1512, UInt<1>(0h0)) node _T_1519 = and(issue_slots[29].request, _T_1518) node _T_1520 = and(_T_1519, can_allocate_89) node _T_1521 = or(_T_1520, _T_1482) node _T_1522 = and(issue_slots[29].request, can_allocate_89) node _T_1523 = eq(_T_1482, UInt<1>(0h0)) node _T_1524 = and(_T_1522, _T_1523) node _T_1525 = or(_T_1524, _T_1512) connect issue_slots[30].grant, UInt<1>(0h0) node _can_allocate_T_90 = and(issue_slots[30].uop.fu_code, io.fu_types[0]) node can_allocate_90 = neq(_can_allocate_T_90, UInt<1>(0h0)) node _T_1526 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1527 = and(issue_slots[30].request, _T_1526) node _T_1528 = and(_T_1527, can_allocate_90) node _T_1529 = eq(_T_1495, UInt<1>(0h0)) node _T_1530 = and(_T_1528, _T_1529) when _T_1530 : connect issue_slots[30].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[30].uop node _T_1531 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1532 = and(issue_slots[30].request, _T_1531) node _T_1533 = and(_T_1532, can_allocate_90) node _T_1534 = or(_T_1533, _T_1495) node _T_1535 = and(issue_slots[30].request, can_allocate_90) node _T_1536 = eq(_T_1495, UInt<1>(0h0)) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = or(_T_1537, UInt<1>(0h0)) node _can_allocate_T_91 = and(issue_slots[30].uop.fu_code, io.fu_types[1]) node can_allocate_91 = neq(_can_allocate_T_91, UInt<1>(0h0)) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) node _T_1540 = and(issue_slots[30].request, _T_1539) node _T_1541 = and(_T_1540, can_allocate_91) node _T_1542 = eq(_T_1508, UInt<1>(0h0)) node _T_1543 = and(_T_1541, _T_1542) when _T_1543 : connect issue_slots[30].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[30].uop node _T_1544 = eq(_T_1538, UInt<1>(0h0)) node _T_1545 = and(issue_slots[30].request, _T_1544) node _T_1546 = and(_T_1545, can_allocate_91) node _T_1547 = or(_T_1546, _T_1508) node _T_1548 = and(issue_slots[30].request, can_allocate_91) node _T_1549 = eq(_T_1508, UInt<1>(0h0)) node _T_1550 = and(_T_1548, _T_1549) node _T_1551 = or(_T_1550, _T_1538) node _can_allocate_T_92 = and(issue_slots[30].uop.fu_code, io.fu_types[2]) node can_allocate_92 = neq(_can_allocate_T_92, UInt<1>(0h0)) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) node _T_1553 = and(issue_slots[30].request, _T_1552) node _T_1554 = and(_T_1553, can_allocate_92) node _T_1555 = eq(_T_1521, UInt<1>(0h0)) node _T_1556 = and(_T_1554, _T_1555) when _T_1556 : connect issue_slots[30].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[30].uop node _T_1557 = eq(_T_1551, UInt<1>(0h0)) node _T_1558 = and(issue_slots[30].request, _T_1557) node _T_1559 = and(_T_1558, can_allocate_92) node _T_1560 = or(_T_1559, _T_1521) node _T_1561 = and(issue_slots[30].request, can_allocate_92) node _T_1562 = eq(_T_1521, UInt<1>(0h0)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(_T_1563, _T_1551) connect issue_slots[31].grant, UInt<1>(0h0) node _can_allocate_T_93 = and(issue_slots[31].uop.fu_code, io.fu_types[0]) node can_allocate_93 = neq(_can_allocate_T_93, UInt<1>(0h0)) node _T_1565 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1566 = and(issue_slots[31].request, _T_1565) node _T_1567 = and(_T_1566, can_allocate_93) node _T_1568 = eq(_T_1534, UInt<1>(0h0)) node _T_1569 = and(_T_1567, _T_1568) when _T_1569 : connect issue_slots[31].grant, UInt<1>(0h1) connect io.iss_valids[0], UInt<1>(0h1) connect io.iss_uops[0], issue_slots[31].uop node _T_1570 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1571 = and(issue_slots[31].request, _T_1570) node _T_1572 = and(_T_1571, can_allocate_93) node _T_1573 = or(_T_1572, _T_1534) node _T_1574 = and(issue_slots[31].request, can_allocate_93) node _T_1575 = eq(_T_1534, UInt<1>(0h0)) node _T_1576 = and(_T_1574, _T_1575) node _T_1577 = or(_T_1576, UInt<1>(0h0)) node _can_allocate_T_94 = and(issue_slots[31].uop.fu_code, io.fu_types[1]) node can_allocate_94 = neq(_can_allocate_T_94, UInt<1>(0h0)) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) node _T_1579 = and(issue_slots[31].request, _T_1578) node _T_1580 = and(_T_1579, can_allocate_94) node _T_1581 = eq(_T_1547, UInt<1>(0h0)) node _T_1582 = and(_T_1580, _T_1581) when _T_1582 : connect issue_slots[31].grant, UInt<1>(0h1) connect io.iss_valids[1], UInt<1>(0h1) connect io.iss_uops[1], issue_slots[31].uop node _T_1583 = eq(_T_1577, UInt<1>(0h0)) node _T_1584 = and(issue_slots[31].request, _T_1583) node _T_1585 = and(_T_1584, can_allocate_94) node _T_1586 = or(_T_1585, _T_1547) node _T_1587 = and(issue_slots[31].request, can_allocate_94) node _T_1588 = eq(_T_1547, UInt<1>(0h0)) node _T_1589 = and(_T_1587, _T_1588) node _T_1590 = or(_T_1589, _T_1577) node _can_allocate_T_95 = and(issue_slots[31].uop.fu_code, io.fu_types[2]) node can_allocate_95 = neq(_can_allocate_T_95, UInt<1>(0h0)) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) node _T_1592 = and(issue_slots[31].request, _T_1591) node _T_1593 = and(_T_1592, can_allocate_95) node _T_1594 = eq(_T_1560, UInt<1>(0h0)) node _T_1595 = and(_T_1593, _T_1594) when _T_1595 : connect issue_slots[31].grant, UInt<1>(0h1) connect io.iss_valids[2], UInt<1>(0h1) connect io.iss_uops[2], issue_slots[31].uop node _T_1596 = eq(_T_1590, UInt<1>(0h0)) node _T_1597 = and(issue_slots[31].request, _T_1596) node _T_1598 = and(_T_1597, can_allocate_95) node _T_1599 = or(_T_1598, _T_1560) node _T_1600 = and(issue_slots[31].request, can_allocate_95) node _T_1601 = eq(_T_1560, UInt<1>(0h0)) node _T_1602 = and(_T_1600, _T_1601) node _T_1603 = or(_T_1602, _T_1590)
module IssueUnitCollapsing_5( // @[issue-unit-age-ordered.scala:29:7] input clock, // @[issue-unit-age-ordered.scala:29:7] input reset, // @[issue-unit-age-ordered.scala:29:7] output io_dis_uops_0_ready, // @[issue-unit.scala:112:14] input io_dis_uops_0_valid, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_uopc, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_dis_uops_0_bits_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_0_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_load, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_iw_state, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_br, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jalr, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_jal, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:112:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:112:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_dis_uops_0_bits_csr_addr, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:112:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_fp_single, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:112:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:112:14] output io_dis_uops_1_ready, // @[issue-unit.scala:112:14] input io_dis_uops_1_valid, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_uopc, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_1_bits_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_dis_uops_1_bits_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_1_bits_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_1_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_1_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_1_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_1_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ctrl_is_load, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_iw_state, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_br, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_jalr, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_jal, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:112:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:112:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_dis_uops_1_bits_csr_addr, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:112:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_fp_single, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:112:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:112:14] output io_dis_uops_2_ready, // @[issue-unit.scala:112:14] input io_dis_uops_2_valid, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_uopc, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:112:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_2_bits_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_dis_uops_2_bits_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_2_bits_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_2_bits_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_2_bits_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_2_bits_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_dis_uops_2_bits_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ctrl_is_load, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_iw_state, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_br, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_jalr, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_jal, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:112:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:112:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:112:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_dis_uops_2_bits_csr_addr, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:112:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:112:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_fp_single, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:112:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:112:14] output io_iss_valids_0, // @[issue-unit.scala:112:14] output io_iss_valids_1, // @[issue-unit.scala:112:14] output io_iss_valids_2, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_uopc, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_inst, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_0_debug_inst, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_rvc, // @[issue-unit.scala:112:14] output [39:0] io_iss_uops_0_debug_pc, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_iq_type, // @[issue-unit.scala:112:14] output [9:0] io_iss_uops_0_fu_code, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_ctrl_br_type, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_ctrl_op1_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_op2_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_imm_sel, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ctrl_op_fcn, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_fcn_dw, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_load, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_sta, // @[issue-unit.scala:112:14] output io_iss_uops_0_ctrl_is_std, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_iw_state, // @[issue-unit.scala:112:14] output io_iss_uops_0_iw_p1_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_0_iw_p2_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_br, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jalr, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_jal, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sfb, // @[issue-unit.scala:112:14] output [15:0] io_iss_uops_0_br_mask, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_0_br_tag, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ftq_idx, // @[issue-unit.scala:112:14] output io_iss_uops_0_edge_inst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_pc_lob, // @[issue-unit.scala:112:14] output io_iss_uops_0_taken, // @[issue-unit.scala:112:14] output [19:0] io_iss_uops_0_imm_packed, // @[issue-unit.scala:112:14] output [11:0] io_iss_uops_0_csr_addr, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_rob_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ldq_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_stq_idx, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_rxq_idx, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_pdst, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_prs1, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_prs2, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_prs3, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_ppred, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs1_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs2_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_prs3_busy, // @[issue-unit.scala:112:14] output io_iss_uops_0_ppred_busy, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_0_stale_pdst, // @[issue-unit.scala:112:14] output io_iss_uops_0_exception, // @[issue-unit.scala:112:14] output [63:0] io_iss_uops_0_exc_cause, // @[issue-unit.scala:112:14] output io_iss_uops_0_bypassable, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_0_mem_cmd, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_mem_size, // @[issue-unit.scala:112:14] output io_iss_uops_0_mem_signed, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fence, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_fencei, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_amo, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_ldq, // @[issue-unit.scala:112:14] output io_iss_uops_0_uses_stq, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_sys_pc2epc, // @[issue-unit.scala:112:14] output io_iss_uops_0_is_unique, // @[issue-unit.scala:112:14] output io_iss_uops_0_flush_on_commit, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_is_rs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_ldst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_0_lrs3, // @[issue-unit.scala:112:14] output io_iss_uops_0_ldst_val, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_dst_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs1_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_lrs2_rtype, // @[issue-unit.scala:112:14] output io_iss_uops_0_frs3_en, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_val, // @[issue-unit.scala:112:14] output io_iss_uops_0_fp_single, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_pf_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ae_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_xcpt_ma_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_debug_if, // @[issue-unit.scala:112:14] output io_iss_uops_0_bp_xcpt_if, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_fsrc, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_0_debug_tsrc, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_uopc, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_1_inst, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_1_debug_inst, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_rvc, // @[issue-unit.scala:112:14] output [39:0] io_iss_uops_1_debug_pc, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_1_iq_type, // @[issue-unit.scala:112:14] output [9:0] io_iss_uops_1_fu_code, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_1_ctrl_br_type, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_ctrl_op1_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_1_ctrl_op2_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_1_ctrl_imm_sel, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_ctrl_op_fcn, // @[issue-unit.scala:112:14] output io_iss_uops_1_ctrl_fcn_dw, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_1_ctrl_csr_cmd, // @[issue-unit.scala:112:14] output io_iss_uops_1_ctrl_is_load, // @[issue-unit.scala:112:14] output io_iss_uops_1_ctrl_is_sta, // @[issue-unit.scala:112:14] output io_iss_uops_1_ctrl_is_std, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_iw_state, // @[issue-unit.scala:112:14] output io_iss_uops_1_iw_p1_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_1_iw_p2_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_br, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_jalr, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_jal, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_sfb, // @[issue-unit.scala:112:14] output [15:0] io_iss_uops_1_br_mask, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_1_br_tag, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_ftq_idx, // @[issue-unit.scala:112:14] output io_iss_uops_1_edge_inst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_1_pc_lob, // @[issue-unit.scala:112:14] output io_iss_uops_1_taken, // @[issue-unit.scala:112:14] output [19:0] io_iss_uops_1_imm_packed, // @[issue-unit.scala:112:14] output [11:0] io_iss_uops_1_csr_addr, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_rob_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_ldq_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_stq_idx, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_rxq_idx, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_pdst, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_prs1, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_prs2, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_prs3, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_ppred, // @[issue-unit.scala:112:14] output io_iss_uops_1_prs1_busy, // @[issue-unit.scala:112:14] output io_iss_uops_1_prs2_busy, // @[issue-unit.scala:112:14] output io_iss_uops_1_prs3_busy, // @[issue-unit.scala:112:14] output io_iss_uops_1_ppred_busy, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_1_stale_pdst, // @[issue-unit.scala:112:14] output io_iss_uops_1_exception, // @[issue-unit.scala:112:14] output [63:0] io_iss_uops_1_exc_cause, // @[issue-unit.scala:112:14] output io_iss_uops_1_bypassable, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_1_mem_cmd, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_mem_size, // @[issue-unit.scala:112:14] output io_iss_uops_1_mem_signed, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_fence, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_fencei, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_amo, // @[issue-unit.scala:112:14] output io_iss_uops_1_uses_ldq, // @[issue-unit.scala:112:14] output io_iss_uops_1_uses_stq, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_sys_pc2epc, // @[issue-unit.scala:112:14] output io_iss_uops_1_is_unique, // @[issue-unit.scala:112:14] output io_iss_uops_1_flush_on_commit, // @[issue-unit.scala:112:14] output io_iss_uops_1_ldst_is_rs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_1_ldst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_1_lrs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_1_lrs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_1_lrs3, // @[issue-unit.scala:112:14] output io_iss_uops_1_ldst_val, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_dst_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_lrs1_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_lrs2_rtype, // @[issue-unit.scala:112:14] output io_iss_uops_1_frs3_en, // @[issue-unit.scala:112:14] output io_iss_uops_1_fp_val, // @[issue-unit.scala:112:14] output io_iss_uops_1_fp_single, // @[issue-unit.scala:112:14] output io_iss_uops_1_xcpt_pf_if, // @[issue-unit.scala:112:14] output io_iss_uops_1_xcpt_ae_if, // @[issue-unit.scala:112:14] output io_iss_uops_1_xcpt_ma_if, // @[issue-unit.scala:112:14] output io_iss_uops_1_bp_debug_if, // @[issue-unit.scala:112:14] output io_iss_uops_1_bp_xcpt_if, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_debug_fsrc, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_1_debug_tsrc, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_uopc, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_2_inst, // @[issue-unit.scala:112:14] output [31:0] io_iss_uops_2_debug_inst, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_rvc, // @[issue-unit.scala:112:14] output [39:0] io_iss_uops_2_debug_pc, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_2_iq_type, // @[issue-unit.scala:112:14] output [9:0] io_iss_uops_2_fu_code, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_2_ctrl_br_type, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_ctrl_op1_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_2_ctrl_op2_sel, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_2_ctrl_imm_sel, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_ctrl_op_fcn, // @[issue-unit.scala:112:14] output io_iss_uops_2_ctrl_fcn_dw, // @[issue-unit.scala:112:14] output [2:0] io_iss_uops_2_ctrl_csr_cmd, // @[issue-unit.scala:112:14] output io_iss_uops_2_ctrl_is_load, // @[issue-unit.scala:112:14] output io_iss_uops_2_ctrl_is_sta, // @[issue-unit.scala:112:14] output io_iss_uops_2_ctrl_is_std, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_iw_state, // @[issue-unit.scala:112:14] output io_iss_uops_2_iw_p1_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_2_iw_p2_poisoned, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_br, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_jalr, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_jal, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_sfb, // @[issue-unit.scala:112:14] output [15:0] io_iss_uops_2_br_mask, // @[issue-unit.scala:112:14] output [3:0] io_iss_uops_2_br_tag, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_ftq_idx, // @[issue-unit.scala:112:14] output io_iss_uops_2_edge_inst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_2_pc_lob, // @[issue-unit.scala:112:14] output io_iss_uops_2_taken, // @[issue-unit.scala:112:14] output [19:0] io_iss_uops_2_imm_packed, // @[issue-unit.scala:112:14] output [11:0] io_iss_uops_2_csr_addr, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_rob_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_ldq_idx, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_stq_idx, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_rxq_idx, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_pdst, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_prs1, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_prs2, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_prs3, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_ppred, // @[issue-unit.scala:112:14] output io_iss_uops_2_prs1_busy, // @[issue-unit.scala:112:14] output io_iss_uops_2_prs2_busy, // @[issue-unit.scala:112:14] output io_iss_uops_2_prs3_busy, // @[issue-unit.scala:112:14] output io_iss_uops_2_ppred_busy, // @[issue-unit.scala:112:14] output [6:0] io_iss_uops_2_stale_pdst, // @[issue-unit.scala:112:14] output io_iss_uops_2_exception, // @[issue-unit.scala:112:14] output [63:0] io_iss_uops_2_exc_cause, // @[issue-unit.scala:112:14] output io_iss_uops_2_bypassable, // @[issue-unit.scala:112:14] output [4:0] io_iss_uops_2_mem_cmd, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_mem_size, // @[issue-unit.scala:112:14] output io_iss_uops_2_mem_signed, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_fence, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_fencei, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_amo, // @[issue-unit.scala:112:14] output io_iss_uops_2_uses_ldq, // @[issue-unit.scala:112:14] output io_iss_uops_2_uses_stq, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_sys_pc2epc, // @[issue-unit.scala:112:14] output io_iss_uops_2_is_unique, // @[issue-unit.scala:112:14] output io_iss_uops_2_flush_on_commit, // @[issue-unit.scala:112:14] output io_iss_uops_2_ldst_is_rs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_2_ldst, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_2_lrs1, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_2_lrs2, // @[issue-unit.scala:112:14] output [5:0] io_iss_uops_2_lrs3, // @[issue-unit.scala:112:14] output io_iss_uops_2_ldst_val, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_dst_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_lrs1_rtype, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_lrs2_rtype, // @[issue-unit.scala:112:14] output io_iss_uops_2_frs3_en, // @[issue-unit.scala:112:14] output io_iss_uops_2_fp_val, // @[issue-unit.scala:112:14] output io_iss_uops_2_fp_single, // @[issue-unit.scala:112:14] output io_iss_uops_2_xcpt_pf_if, // @[issue-unit.scala:112:14] output io_iss_uops_2_xcpt_ae_if, // @[issue-unit.scala:112:14] output io_iss_uops_2_xcpt_ma_if, // @[issue-unit.scala:112:14] output io_iss_uops_2_bp_debug_if, // @[issue-unit.scala:112:14] output io_iss_uops_2_bp_xcpt_if, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_debug_fsrc, // @[issue-unit.scala:112:14] output [1:0] io_iss_uops_2_debug_tsrc, // @[issue-unit.scala:112:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_2_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_3_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_4_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_5_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-unit.scala:112:14] input io_wakeup_ports_6_valid, // @[issue-unit.scala:112:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-unit.scala:112:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-unit.scala:112:14] input io_spec_ld_wakeup_0_valid, // @[issue-unit.scala:112:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-unit.scala:112:14] input [9:0] io_fu_types_0, // @[issue-unit.scala:112:14] input [9:0] io_fu_types_1, // @[issue-unit.scala:112:14] input [9:0] io_fu_types_2, // @[issue-unit.scala:112:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:112:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:112:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-unit.scala:112:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_br, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jalr, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_jal, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:112:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:112:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:112:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:112:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:112:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:112:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bypassable, // @[issue-unit.scala:112:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:112:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_ldst_val, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_fp_single, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:112:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:112:14] input io_brupdate_b2_valid, // @[issue-unit.scala:112:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:112:14] input io_brupdate_b2_taken, // @[issue-unit.scala:112:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:112:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:112:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:112:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:112:14] input io_flush_pipeline, // @[issue-unit.scala:112:14] input io_ld_miss, // @[issue-unit.scala:112:14] input [63:0] io_tsc_reg // @[issue-unit.scala:112:14] ); wire _slots_31_io_valid; // @[issue-unit.scala:153:73] wire _slots_30_io_valid; // @[issue-unit.scala:153:73] wire _slots_29_io_valid; // @[issue-unit.scala:153:73] wire _slots_28_io_valid; // @[issue-unit.scala:153:73] wire _slots_27_io_valid; // @[issue-unit.scala:153:73] wire _slots_26_io_valid; // @[issue-unit.scala:153:73] wire _slots_25_io_valid; // @[issue-unit.scala:153:73] wire _slots_24_io_valid; // @[issue-unit.scala:153:73] wire _slots_23_io_valid; // @[issue-unit.scala:153:73] wire _slots_22_io_valid; // @[issue-unit.scala:153:73] wire _slots_21_io_valid; // @[issue-unit.scala:153:73] wire _slots_20_io_valid; // @[issue-unit.scala:153:73] wire _slots_19_io_valid; // @[issue-unit.scala:153:73] wire _slots_18_io_valid; // @[issue-unit.scala:153:73] wire _slots_17_io_valid; // @[issue-unit.scala:153:73] wire _slots_16_io_valid; // @[issue-unit.scala:153:73] wire _slots_15_io_valid; // @[issue-unit.scala:153:73] wire _slots_14_io_valid; // @[issue-unit.scala:153:73] wire _slots_13_io_valid; // @[issue-unit.scala:153:73] wire _slots_12_io_valid; // @[issue-unit.scala:153:73] wire _slots_11_io_valid; // @[issue-unit.scala:153:73] wire _slots_10_io_valid; // @[issue-unit.scala:153:73] wire _slots_9_io_valid; // @[issue-unit.scala:153:73] wire _slots_8_io_valid; // @[issue-unit.scala:153:73] wire _slots_7_io_valid; // @[issue-unit.scala:153:73] wire _slots_6_io_valid; // @[issue-unit.scala:153:73] wire _slots_5_io_valid; // @[issue-unit.scala:153:73] wire _slots_4_io_valid; // @[issue-unit.scala:153:73] wire _slots_3_io_valid; // @[issue-unit.scala:153:73] wire _slots_2_io_valid; // @[issue-unit.scala:153:73] wire _slots_1_io_valid; // @[issue-unit.scala:153:73] wire _slots_0_io_valid; // @[issue-unit.scala:153:73] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_uopc_0 = io_dis_uops_0_bits_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_iq_type_0 = io_dis_uops_0_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_dis_uops_0_bits_fu_code_0 = io_dis_uops_0_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_ctrl_br_type_0 = io_dis_uops_0_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_ctrl_op1_sel_0 = io_dis_uops_0_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_op2_sel_0 = io_dis_uops_0_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_imm_sel_0 = io_dis_uops_0_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_ctrl_op_fcn_0 = io_dis_uops_0_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_fcn_dw_0 = io_dis_uops_0_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_0_bits_ctrl_csr_cmd_0 = io_dis_uops_0_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_load_0 = io_dis_uops_0_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_sta_0 = io_dis_uops_0_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ctrl_is_std_0 = io_dis_uops_0_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_iw_state_0 = io_dis_uops_0_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p1_poisoned_0 = io_dis_uops_0_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_iw_p2_poisoned_0 = io_dis_uops_0_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_br_0 = io_dis_uops_0_bits_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jalr_0 = io_dis_uops_0_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_jal_0 = io_dis_uops_0_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_dis_uops_0_bits_csr_addr_0 = io_dis_uops_0_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bypassable_0 = io_dis_uops_0_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ldst_val_0 = io_dis_uops_0_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_fp_single_0 = io_dis_uops_0_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_uopc_0 = io_dis_uops_1_bits_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_1_bits_iq_type_0 = io_dis_uops_1_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_dis_uops_1_bits_fu_code_0 = io_dis_uops_1_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_1_bits_ctrl_br_type_0 = io_dis_uops_1_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_ctrl_op1_sel_0 = io_dis_uops_1_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_1_bits_ctrl_op2_sel_0 = io_dis_uops_1_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_1_bits_ctrl_imm_sel_0 = io_dis_uops_1_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_ctrl_op_fcn_0 = io_dis_uops_1_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ctrl_fcn_dw_0 = io_dis_uops_1_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_1_bits_ctrl_csr_cmd_0 = io_dis_uops_1_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ctrl_is_load_0 = io_dis_uops_1_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ctrl_is_sta_0 = io_dis_uops_1_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ctrl_is_std_0 = io_dis_uops_1_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_iw_state_0 = io_dis_uops_1_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_iw_p1_poisoned_0 = io_dis_uops_1_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_iw_p2_poisoned_0 = io_dis_uops_1_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_br_0 = io_dis_uops_1_bits_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_jalr_0 = io_dis_uops_1_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_jal_0 = io_dis_uops_1_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_dis_uops_1_bits_csr_addr_0 = io_dis_uops_1_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_bypassable_0 = io_dis_uops_1_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ldst_val_0 = io_dis_uops_1_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_fp_single_0 = io_dis_uops_1_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_uopc_0 = io_dis_uops_2_bits_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_2_bits_iq_type_0 = io_dis_uops_2_bits_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_dis_uops_2_bits_fu_code_0 = io_dis_uops_2_bits_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_2_bits_ctrl_br_type_0 = io_dis_uops_2_bits_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_ctrl_op1_sel_0 = io_dis_uops_2_bits_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_2_bits_ctrl_op2_sel_0 = io_dis_uops_2_bits_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_2_bits_ctrl_imm_sel_0 = io_dis_uops_2_bits_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_ctrl_op_fcn_0 = io_dis_uops_2_bits_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ctrl_fcn_dw_0 = io_dis_uops_2_bits_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_dis_uops_2_bits_ctrl_csr_cmd_0 = io_dis_uops_2_bits_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ctrl_is_load_0 = io_dis_uops_2_bits_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ctrl_is_sta_0 = io_dis_uops_2_bits_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ctrl_is_std_0 = io_dis_uops_2_bits_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_iw_state_0 = io_dis_uops_2_bits_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_iw_p1_poisoned_0 = io_dis_uops_2_bits_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_iw_p2_poisoned_0 = io_dis_uops_2_bits_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_br_0 = io_dis_uops_2_bits_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_jalr_0 = io_dis_uops_2_bits_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_jal_0 = io_dis_uops_2_bits_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_dis_uops_2_bits_csr_addr_0 = io_dis_uops_2_bits_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_bypassable_0 = io_dis_uops_2_bits_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ldst_val_0 = io_dis_uops_2_bits_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_fp_single_0 = io_dis_uops_2_bits_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_fu_types_0_0 = io_fu_types_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_fu_types_1_0 = io_fu_types_1; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_fu_types_2_0 = io_fu_types_2; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:29:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:29:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:29:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:29:7] wire io_ld_miss_0 = io_ld_miss; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_0_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:29:7] wire issue_slots_0_clear = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_16_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_17_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_18_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_19_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_20_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_21_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_22_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_23_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_24_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_25_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_26_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_27_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_28_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_29_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_30_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_pred_wakeup_port_valid = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_prs3_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_prs3_busy = 1'h0; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ppred_busy = 1'h0; // @[issue-unit.scala:154:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:76:49] wire io_iss_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_1_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_br = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_taken = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_exception = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_1_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_1_cs_is_load = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_1_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_1_cs_is_std = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_2_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_br = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_taken = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_exception = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire io_iss_uops_2_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_2_cs_is_load = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_2_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire io_iss_uops_2_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_dis_uops_0_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_1_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_dis_uops_2_bits_ppred = 5'h0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_pred_wakeup_port_bits = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_ppred = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_ppred = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_ppred = 5'h0; // @[issue-unit.scala:154:28] wire [4:0] io_iss_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] io_iss_uops_1_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_1_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] io_iss_uops_2_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] io_iss_uops_2_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_1_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_1_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_1_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_1_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_1_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_1_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_1_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_2_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_2_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_2_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_2_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] io_iss_uops_2_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_2_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] io_iss_uops_2_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_1_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_2_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] _next_T = 4'h0; // @[issue-unit-age-ordered.scala:48:26] wire [3:0] io_iss_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] io_iss_uops_1_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_1_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_1_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] io_iss_uops_2_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_2_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] io_iss_uops_2_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] io_iss_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] io_iss_uops_1_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] io_iss_uops_2_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_1_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_1_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_1_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_1_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_1_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_2_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_2_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_2_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_2_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] io_iss_uops_2_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] io_iss_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] io_iss_uops_1_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] io_iss_uops_2_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_0_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_1_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] io_iss_uops_2_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] io_iss_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] io_iss_uops_1_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] io_iss_uops_2_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] io_iss_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] io_iss_uops_1_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] io_iss_uops_2_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] io_iss_uops_0_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] io_iss_uops_1_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] io_iss_uops_2_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] io_iss_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] io_iss_uops_1_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] io_iss_uops_2_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] io_iss_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] io_iss_uops_1_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] io_iss_uops_2_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_1_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_1_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_2_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] io_iss_uops_2_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_0_bits_pdst = io_wakeup_ports_0_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_0_bits_poisoned = io_wakeup_ports_0_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_1_bits_pdst = io_wakeup_ports_1_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_1_bits_poisoned = io_wakeup_ports_1_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_2_valid = io_wakeup_ports_2_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_2_bits_pdst = io_wakeup_ports_2_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_2_bits_poisoned = io_wakeup_ports_2_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_3_valid = io_wakeup_ports_3_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_3_bits_pdst = io_wakeup_ports_3_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_3_bits_poisoned = io_wakeup_ports_3_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_4_valid = io_wakeup_ports_4_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_4_bits_pdst = io_wakeup_ports_4_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_4_bits_poisoned = io_wakeup_ports_4_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_5_valid = io_wakeup_ports_5_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_5_bits_pdst = io_wakeup_ports_5_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_5_bits_poisoned = io_wakeup_ports_5_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_6_valid = io_wakeup_ports_6_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_wakeup_ports_6_bits_pdst = io_wakeup_ports_6_bits_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_wakeup_ports_6_bits_poisoned = io_wakeup_ports_6_bits_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_spec_ld_wakeup_0_valid = io_spec_ld_wakeup_0_valid_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_spec_ld_wakeup_0_bits = io_spec_ld_wakeup_0_bits_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_uopc = io_brupdate_b2_uop_uopc_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_20_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_21_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_22_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_23_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_24_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_25_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_26_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_27_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_28_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_29_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_30_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_31_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_brupdate_b2_uop_iq_type = io_brupdate_b2_uop_iq_type_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_8_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_9_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_10_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_11_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_12_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_13_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_14_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_15_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_16_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_17_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_18_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_19_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_20_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_21_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_22_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_23_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_24_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_25_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_26_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_27_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_28_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_29_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_30_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_31_brupdate_b2_uop_fu_code = io_brupdate_b2_uop_fu_code_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_brupdate_b2_uop_ctrl_br_type = io_brupdate_b2_uop_ctrl_br_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_ctrl_op1_sel = io_brupdate_b2_uop_ctrl_op1_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_brupdate_b2_uop_ctrl_op2_sel = io_brupdate_b2_uop_ctrl_op2_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_brupdate_b2_uop_ctrl_imm_sel = io_brupdate_b2_uop_ctrl_imm_sel_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_ctrl_op_fcn = io_brupdate_b2_uop_ctrl_op_fcn_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ctrl_fcn_dw = io_brupdate_b2_uop_ctrl_fcn_dw_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_brupdate_b2_uop_ctrl_csr_cmd = io_brupdate_b2_uop_ctrl_csr_cmd_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ctrl_is_load = io_brupdate_b2_uop_ctrl_is_load_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ctrl_is_sta = io_brupdate_b2_uop_ctrl_is_sta_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ctrl_is_std = io_brupdate_b2_uop_ctrl_is_std_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_iw_state = io_brupdate_b2_uop_iw_state_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_iw_p1_poisoned = io_brupdate_b2_uop_iw_p1_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_iw_p2_poisoned = io_brupdate_b2_uop_iw_p2_poisoned_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_br = io_brupdate_b2_uop_is_br_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_jalr = io_brupdate_b2_uop_is_jalr_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_jal = io_brupdate_b2_uop_is_jal_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_20_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_21_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_22_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_23_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_24_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_25_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_26_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_27_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_28_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_29_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_30_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_31_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_8_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_9_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_10_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_11_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_12_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_13_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_14_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_15_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_16_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_17_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_18_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_19_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_20_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_21_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_22_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_23_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_24_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_25_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_26_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_27_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_28_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_29_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_30_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_31_brupdate_b2_uop_csr_addr = io_brupdate_b2_uop_csr_addr_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_20_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_21_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_22_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_23_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_24_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_25_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_26_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_27_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_28_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_29_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_30_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_31_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_bypassable = io_brupdate_b2_uop_bypassable_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_ldst_val = io_brupdate_b2_uop_ldst_val_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_fp_single = io_brupdate_b2_uop_fp_single_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_valid = io_brupdate_b2_valid_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit.scala:154:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_20_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_21_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_22_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_23_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_24_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_25_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_26_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_27_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_28_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_29_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_30_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire issue_slots_31_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_20_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_21_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_22_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_23_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_24_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_25_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_26_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_27_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_28_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_29_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_30_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_31_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_20_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_21_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_22_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_23_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_24_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_25_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_26_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_27_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_28_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_29_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_30_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire [20:0] issue_slots_31_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit.scala:154:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_16_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_17_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_18_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_19_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_20_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_21_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_22_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_23_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_24_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_25_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_26_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_27_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_28_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_29_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_30_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_31_kill = io_flush_pipeline_0; // @[issue-unit.scala:154:28] wire issue_slots_0_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_1_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_2_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_3_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_4_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_5_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_6_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_7_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_8_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_9_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_10_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_11_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_12_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_13_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_14_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_15_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_16_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_17_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_18_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_19_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_20_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_21_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_22_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_23_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_24_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_25_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_26_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_27_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_28_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_29_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_30_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire issue_slots_31_ldspec_miss = io_ld_miss_0; // @[issue-unit.scala:154:28] wire _io_event_empty_T_31; // @[issue-unit.scala:165:21] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:29:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_valids_0_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_valids_1_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_valids_2_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_uopc_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_0_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_iss_uops_0_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_0_iq_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_iss_uops_0_fu_code_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_iw_state_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_br_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_jal_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_iss_uops_0_br_mask_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_0_br_tag_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_taken_0; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_iss_uops_0_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_iss_uops_0_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_prs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_prs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_prs3_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_ppred_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_0_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_exception_0; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_iss_uops_0_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bypassable_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_0_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_mem_size_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fence_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_amo_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_is_unique_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_ldst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_0_lrs3_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_val_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_fp_single_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_0_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_0_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_1_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_1_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_1_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_1_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_uopc_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_1_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_1_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_iss_uops_1_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_1_iq_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_iss_uops_1_fu_code_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_iw_state_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_br_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_jal_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_iss_uops_1_br_mask_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_1_br_tag_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_1_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_taken_0; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_iss_uops_1_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_iss_uops_1_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_prs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_prs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_prs3_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_ppred_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_1_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_exception_0; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_iss_uops_1_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_bypassable_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_1_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_mem_size_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_fence_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_amo_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_is_unique_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_1_ldst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_1_lrs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_1_lrs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_1_lrs3_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_fp_val_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_fp_single_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_1_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_1_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_2_ctrl_br_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_ctrl_op1_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_2_ctrl_op2_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_2_ctrl_imm_sel_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_ctrl_op_fcn_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ctrl_fcn_dw_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_2_ctrl_csr_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ctrl_is_load_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ctrl_is_sta_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ctrl_is_std_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_uopc_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_2_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [31:0] io_iss_uops_2_debug_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_rvc_0; // @[issue-unit-age-ordered.scala:29:7] wire [39:0] io_iss_uops_2_debug_pc_0; // @[issue-unit-age-ordered.scala:29:7] wire [2:0] io_iss_uops_2_iq_type_0; // @[issue-unit-age-ordered.scala:29:7] wire [9:0] io_iss_uops_2_fu_code_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_iw_state_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_iw_p1_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_iw_p2_poisoned_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_br_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_jalr_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_jal_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_sfb_0; // @[issue-unit-age-ordered.scala:29:7] wire [15:0] io_iss_uops_2_br_mask_0; // @[issue-unit-age-ordered.scala:29:7] wire [3:0] io_iss_uops_2_br_tag_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_ftq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_edge_inst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_2_pc_lob_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_taken_0; // @[issue-unit-age-ordered.scala:29:7] wire [19:0] io_iss_uops_2_imm_packed_0; // @[issue-unit-age-ordered.scala:29:7] wire [11:0] io_iss_uops_2_csr_addr_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_rob_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_ldq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_stq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_rxq_idx_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_prs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_prs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_prs3_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_ppred_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_prs1_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_prs2_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_prs3_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ppred_busy_0; // @[issue-unit-age-ordered.scala:29:7] wire [6:0] io_iss_uops_2_stale_pdst_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_exception_0; // @[issue-unit-age-ordered.scala:29:7] wire [63:0] io_iss_uops_2_exc_cause_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_bypassable_0; // @[issue-unit-age-ordered.scala:29:7] wire [4:0] io_iss_uops_2_mem_cmd_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_mem_size_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_mem_signed_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_fence_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_fencei_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_amo_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_uses_ldq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_uses_stq_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_is_unique_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_flush_on_commit_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_2_ldst_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_2_lrs1_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_2_lrs2_0; // @[issue-unit-age-ordered.scala:29:7] wire [5:0] io_iss_uops_2_lrs3_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_ldst_val_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_dst_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_frs3_en_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_fp_val_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_fp_single_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_bp_debug_if_0; // @[issue-unit-age-ordered.scala:29:7] wire io_iss_uops_2_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_debug_fsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire [1:0] io_iss_uops_2_debug_tsrc_0; // @[issue-unit-age-ordered.scala:29:7] wire io_event_empty; // @[issue-unit-age-ordered.scala:29:7] wire _T_5 = io_dis_uops_0_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39] wire _T_4 = _T_5 & io_dis_uops_0_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_0_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39] wire [1:0] _WIRE_iw_state = _T_4 ? 2'h2 : 2'h1; // @[issue-unit.scala:123:26, :127:96, :128:54, :129:30] wire _GEN = _T_4 | ~(_T_5 & (|io_dis_uops_0_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}] wire [1:0] _WIRE_lrs2_rtype = _GEN ? io_dis_uops_0_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102] wire _WIRE_prs2_busy = _GEN & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102] wire _T_13 = io_dis_uops_1_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39] wire _T_12 = _T_13 & io_dis_uops_1_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_1_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39] wire _GEN_0 = _T_12 | ~(_T_13 & (|io_dis_uops_1_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}] wire [1:0] _WIRE_1_lrs2_rtype = _GEN_0 ? io_dis_uops_1_bits_lrs2_rtype_0 : 2'h2; // @[issue-unit.scala:120:17, :128:54, :131:102] wire _WIRE_1_prs2_busy = _GEN_0 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit.scala:120:17, :128:54, :131:102] wire _T_21 = io_dis_uops_2_bits_uopc_0 == 7'h2; // @[issue-unit.scala:127:39] wire _T_20 = _T_21 & io_dis_uops_2_bits_lrs2_rtype_0 == 2'h0 | io_dis_uops_2_bits_uopc_0 == 7'h43; // @[issue-unit.scala:127:{39,50,84,96}, :128:39] wire _GEN_1 = _T_20 | ~(_T_21 & (|io_dis_uops_2_bits_lrs2_rtype_0)); // @[issue-unit.scala:120:17, :127:{39,96}, :128:54, :131:{56,90,102}] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_24_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_25_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_26_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_27_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_28_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_29_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_30_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire _issue_slots_31_clear_T; // @[issue-unit-age-ordered.scala:76:49] wire [3:0] issue_slots_0_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_0_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_0_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_0_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_0_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_0_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_0_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_0_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_0_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_0_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_0_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_0_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_0_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_0_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_0_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_0_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_0_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_0_request; // @[issue-unit.scala:154:28] wire issue_slots_0_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_0_grant; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_1_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_1_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_1_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_1_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_1_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_1_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_1_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_1_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_1_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_1_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_1_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_1_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_1_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_1_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_1_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_1_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_1_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_1_request; // @[issue-unit.scala:154:28] wire issue_slots_1_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_1_grant; // @[issue-unit.scala:154:28] wire issue_slots_1_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_2_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_2_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_2_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_2_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_2_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_2_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_2_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_2_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_2_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_2_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_2_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_2_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_2_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_2_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_2_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_2_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_2_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_2_request; // @[issue-unit.scala:154:28] wire issue_slots_2_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_2_grant; // @[issue-unit.scala:154:28] wire issue_slots_2_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_3_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_3_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_3_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_3_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_3_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_3_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_3_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_3_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_3_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_3_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_3_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_3_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_3_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_3_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_3_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_3_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_3_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_3_request; // @[issue-unit.scala:154:28] wire issue_slots_3_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_3_grant; // @[issue-unit.scala:154:28] wire issue_slots_3_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_4_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_4_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_4_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_4_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_4_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_4_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_4_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_4_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_4_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_4_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_4_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_4_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_4_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_4_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_4_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_4_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_4_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_4_request; // @[issue-unit.scala:154:28] wire issue_slots_4_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_4_grant; // @[issue-unit.scala:154:28] wire issue_slots_4_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_5_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_5_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_5_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_5_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_5_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_5_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_5_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_5_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_5_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_5_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_5_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_5_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_5_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_5_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_5_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_5_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_5_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_5_request; // @[issue-unit.scala:154:28] wire issue_slots_5_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_5_grant; // @[issue-unit.scala:154:28] wire issue_slots_5_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_6_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_6_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_6_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_6_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_6_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_6_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_6_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_6_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_6_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_6_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_6_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_6_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_6_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_6_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_6_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_6_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_6_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_6_request; // @[issue-unit.scala:154:28] wire issue_slots_6_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_6_grant; // @[issue-unit.scala:154:28] wire issue_slots_6_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_7_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_7_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_7_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_7_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_7_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_7_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_7_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_7_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_7_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_7_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_7_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_7_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_7_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_7_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_7_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_7_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_7_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_7_request; // @[issue-unit.scala:154:28] wire issue_slots_7_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_7_grant; // @[issue-unit.scala:154:28] wire issue_slots_7_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_8_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_8_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_8_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_8_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_8_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_8_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_8_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_8_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_8_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_8_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_8_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_8_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_8_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_8_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_8_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_8_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_8_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_8_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_8_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_8_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_8_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_8_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_8_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_8_valid; // @[issue-unit.scala:154:28] wire issue_slots_8_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_8_request; // @[issue-unit.scala:154:28] wire issue_slots_8_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_8_grant; // @[issue-unit.scala:154:28] wire issue_slots_8_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_9_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_9_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_9_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_9_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_9_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_9_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_9_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_9_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_9_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_9_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_9_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_9_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_9_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_9_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_9_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_9_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_9_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_9_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_9_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_9_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_9_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_9_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_9_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_9_valid; // @[issue-unit.scala:154:28] wire issue_slots_9_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_9_request; // @[issue-unit.scala:154:28] wire issue_slots_9_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_9_grant; // @[issue-unit.scala:154:28] wire issue_slots_9_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_10_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_10_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_10_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_10_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_10_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_10_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_10_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_10_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_10_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_10_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_10_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_10_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_10_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_10_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_10_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_10_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_10_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_10_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_10_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_10_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_10_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_10_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_10_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_10_valid; // @[issue-unit.scala:154:28] wire issue_slots_10_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_10_request; // @[issue-unit.scala:154:28] wire issue_slots_10_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_10_grant; // @[issue-unit.scala:154:28] wire issue_slots_10_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_11_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_11_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_11_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_11_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_11_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_11_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_11_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_11_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_11_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_11_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_11_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_11_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_11_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_11_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_11_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_11_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_11_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_11_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_11_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_11_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_11_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_11_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_11_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_11_valid; // @[issue-unit.scala:154:28] wire issue_slots_11_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_11_request; // @[issue-unit.scala:154:28] wire issue_slots_11_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_11_grant; // @[issue-unit.scala:154:28] wire issue_slots_11_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_12_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_12_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_12_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_12_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_12_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_12_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_12_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_12_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_12_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_12_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_12_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_12_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_12_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_12_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_12_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_12_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_12_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_12_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_12_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_12_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_12_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_12_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_12_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_12_valid; // @[issue-unit.scala:154:28] wire issue_slots_12_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_12_request; // @[issue-unit.scala:154:28] wire issue_slots_12_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_12_grant; // @[issue-unit.scala:154:28] wire issue_slots_12_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_13_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_13_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_13_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_13_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_13_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_13_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_13_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_13_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_13_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_13_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_13_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_13_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_13_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_13_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_13_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_13_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_13_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_13_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_13_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_13_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_13_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_13_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_13_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_13_valid; // @[issue-unit.scala:154:28] wire issue_slots_13_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_13_request; // @[issue-unit.scala:154:28] wire issue_slots_13_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_13_grant; // @[issue-unit.scala:154:28] wire issue_slots_13_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_14_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_14_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_14_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_14_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_14_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_14_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_14_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_14_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_14_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_14_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_14_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_14_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_14_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_14_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_14_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_14_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_14_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_14_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_14_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_14_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_14_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_14_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_14_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_14_valid; // @[issue-unit.scala:154:28] wire issue_slots_14_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_14_request; // @[issue-unit.scala:154:28] wire issue_slots_14_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_14_grant; // @[issue-unit.scala:154:28] wire issue_slots_14_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_15_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_15_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_15_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_15_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_15_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_15_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_15_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_15_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_15_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_15_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_15_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_15_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_15_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_15_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_15_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_15_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_15_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_15_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_15_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_15_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_15_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_15_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_15_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_15_valid; // @[issue-unit.scala:154:28] wire issue_slots_15_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_15_request; // @[issue-unit.scala:154:28] wire issue_slots_15_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_15_grant; // @[issue-unit.scala:154:28] wire issue_slots_15_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_16_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_16_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_16_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_16_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_16_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_16_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_16_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_16_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_16_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_16_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_16_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_16_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_16_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_16_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_16_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_16_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_16_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_16_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_16_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_16_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_16_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_16_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_16_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_16_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_16_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_16_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_16_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_16_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_16_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_16_valid; // @[issue-unit.scala:154:28] wire issue_slots_16_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_16_request; // @[issue-unit.scala:154:28] wire issue_slots_16_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_16_grant; // @[issue-unit.scala:154:28] wire issue_slots_16_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_17_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_17_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_17_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_17_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_17_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_17_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_17_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_17_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_17_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_17_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_17_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_17_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_17_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_17_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_17_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_17_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_17_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_17_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_17_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_17_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_17_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_17_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_17_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_17_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_17_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_17_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_17_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_17_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_17_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_17_valid; // @[issue-unit.scala:154:28] wire issue_slots_17_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_17_request; // @[issue-unit.scala:154:28] wire issue_slots_17_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_17_grant; // @[issue-unit.scala:154:28] wire issue_slots_17_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_18_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_18_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_18_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_18_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_18_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_18_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_18_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_18_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_18_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_18_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_18_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_18_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_18_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_18_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_18_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_18_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_18_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_18_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_18_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_18_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_18_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_18_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_18_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_18_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_18_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_18_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_18_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_18_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_18_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_18_valid; // @[issue-unit.scala:154:28] wire issue_slots_18_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_18_request; // @[issue-unit.scala:154:28] wire issue_slots_18_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_18_grant; // @[issue-unit.scala:154:28] wire issue_slots_18_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_19_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_19_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_19_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_19_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_19_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_19_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_19_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_19_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_19_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_19_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_19_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_19_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_19_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_19_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_19_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_19_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_19_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_19_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_19_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_19_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_19_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_19_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_19_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_19_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_19_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_19_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_19_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_19_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_19_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_19_valid; // @[issue-unit.scala:154:28] wire issue_slots_19_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_19_request; // @[issue-unit.scala:154:28] wire issue_slots_19_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_19_grant; // @[issue-unit.scala:154:28] wire issue_slots_19_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_20_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_20_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_20_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_20_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_20_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_20_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_20_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_20_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_20_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_20_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_20_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_20_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_20_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_20_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_20_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_20_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_20_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_20_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_20_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_20_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_20_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_20_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_20_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_20_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_20_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_20_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_20_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_20_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_20_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_20_valid; // @[issue-unit.scala:154:28] wire issue_slots_20_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_20_request; // @[issue-unit.scala:154:28] wire issue_slots_20_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_20_grant; // @[issue-unit.scala:154:28] wire issue_slots_20_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_21_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_21_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_21_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_21_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_21_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_21_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_21_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_21_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_21_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_21_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_21_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_21_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_21_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_21_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_21_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_21_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_21_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_21_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_21_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_21_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_21_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_21_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_21_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_21_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_21_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_21_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_21_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_21_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_21_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_21_valid; // @[issue-unit.scala:154:28] wire issue_slots_21_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_21_request; // @[issue-unit.scala:154:28] wire issue_slots_21_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_21_grant; // @[issue-unit.scala:154:28] wire issue_slots_21_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_22_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_22_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_22_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_22_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_22_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_22_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_22_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_22_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_22_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_22_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_22_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_22_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_22_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_22_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_22_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_22_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_22_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_22_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_22_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_22_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_22_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_22_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_22_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_22_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_22_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_22_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_22_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_22_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_22_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_22_valid; // @[issue-unit.scala:154:28] wire issue_slots_22_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_22_request; // @[issue-unit.scala:154:28] wire issue_slots_22_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_22_grant; // @[issue-unit.scala:154:28] wire issue_slots_22_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_23_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_23_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_23_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_23_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_23_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_23_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_23_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_23_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_23_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_23_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_23_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_23_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_23_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_23_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_23_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_23_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_23_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_23_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_23_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_23_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_23_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_23_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_23_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_23_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_23_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_23_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_23_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_23_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_23_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_23_valid; // @[issue-unit.scala:154:28] wire issue_slots_23_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_23_request; // @[issue-unit.scala:154:28] wire issue_slots_23_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_23_grant; // @[issue-unit.scala:154:28] wire issue_slots_23_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_24_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_24_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_24_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_24_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_24_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_24_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_24_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_24_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_24_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_24_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_24_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_24_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_24_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_24_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_24_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_24_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_24_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_24_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_24_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_24_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_24_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_24_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_24_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_24_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_24_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_24_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_24_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_24_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_24_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_24_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_24_valid; // @[issue-unit.scala:154:28] wire issue_slots_24_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_24_request; // @[issue-unit.scala:154:28] wire issue_slots_24_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_24_grant; // @[issue-unit.scala:154:28] wire issue_slots_24_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_25_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_25_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_25_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_25_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_25_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_25_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_25_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_25_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_25_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_25_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_25_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_25_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_25_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_25_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_25_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_25_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_25_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_25_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_25_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_25_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_25_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_25_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_25_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_25_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_25_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_25_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_25_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_25_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_25_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_25_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_25_valid; // @[issue-unit.scala:154:28] wire issue_slots_25_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_25_request; // @[issue-unit.scala:154:28] wire issue_slots_25_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_25_grant; // @[issue-unit.scala:154:28] wire issue_slots_25_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_26_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_26_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_26_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_26_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_26_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_26_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_26_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_26_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_26_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_26_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_26_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_26_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_26_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_26_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_26_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_26_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_26_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_26_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_26_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_26_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_26_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_26_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_26_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_26_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_26_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_26_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_26_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_26_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_26_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_26_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_26_valid; // @[issue-unit.scala:154:28] wire issue_slots_26_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_26_request; // @[issue-unit.scala:154:28] wire issue_slots_26_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_26_grant; // @[issue-unit.scala:154:28] wire issue_slots_26_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_27_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_27_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_27_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_27_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_27_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_27_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_27_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_27_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_27_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_27_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_27_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_27_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_27_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_27_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_27_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_27_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_27_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_27_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_27_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_27_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_27_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_27_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_27_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_27_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_27_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_27_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_27_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_27_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_27_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_27_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_27_valid; // @[issue-unit.scala:154:28] wire issue_slots_27_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_27_request; // @[issue-unit.scala:154:28] wire issue_slots_27_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_27_grant; // @[issue-unit.scala:154:28] wire issue_slots_27_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_28_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_28_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_28_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_28_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_28_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_28_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_28_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_28_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_28_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_28_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_28_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_28_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_28_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_28_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_28_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_28_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_28_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_28_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_28_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_28_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_28_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_28_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_28_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_28_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_28_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_28_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_28_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_28_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_28_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_28_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_28_valid; // @[issue-unit.scala:154:28] wire issue_slots_28_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_28_request; // @[issue-unit.scala:154:28] wire issue_slots_28_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_28_grant; // @[issue-unit.scala:154:28] wire issue_slots_28_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_29_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_29_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_29_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_29_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_ppred; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_29_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_29_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_29_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_29_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_29_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_29_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_29_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_29_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_29_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_29_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_29_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_29_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_29_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_29_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_29_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_29_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_29_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_29_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_29_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_29_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_29_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_29_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_29_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_29_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_29_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_29_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_29_valid; // @[issue-unit.scala:154:28] wire issue_slots_29_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_29_request; // @[issue-unit.scala:154:28] wire issue_slots_29_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_29_grant; // @[issue-unit.scala:154:28] wire issue_slots_29_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_30_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_30_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_30_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_30_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_30_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_30_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_30_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_30_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_30_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_30_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_30_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_30_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_30_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_30_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_30_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_30_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_30_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_30_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_30_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_30_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_prs3; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_ppred; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_30_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_30_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_30_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_30_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_30_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_30_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_30_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_30_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_30_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_30_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_30_valid; // @[issue-unit.scala:154:28] wire issue_slots_30_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_30_request; // @[issue-unit.scala:154:28] wire issue_slots_30_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_30_grant; // @[issue-unit.scala:154:28] wire issue_slots_30_clear; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_in_uop_bits_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_in_uop_bits_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_in_uop_bits_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_in_uop_bits_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_in_uop_bits_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_in_uop_bits_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_31_in_uop_bits_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_in_uop_bits_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_31_in_uop_bits_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_br; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_in_uop_bits_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_in_uop_bits_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_in_uop_bits_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_31_in_uop_bits_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_31_in_uop_bits_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_prs3; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_prs2_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_in_uop_bits_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_31_in_uop_bits_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_in_uop_bits_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_in_uop_bits_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_in_uop_bits_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_in_uop_bits_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_in_uop_bits_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_bits_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_in_uop_bits_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_31_in_uop_valid; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_out_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_out_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_out_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_out_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_out_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_out_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_31_out_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_out_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_31_out_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_out_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_out_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_out_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_31_out_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_31_out_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_prs2_busy; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_prs3_busy; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ppred_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_out_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_31_out_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_out_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_out_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_out_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_out_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_out_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_31_out_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_out_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_uop_ctrl_br_type; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_ctrl_op1_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_uop_ctrl_op2_sel; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_uop_ctrl_imm_sel; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_ctrl_op_fcn; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ctrl_fcn_dw; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_uop_ctrl_csr_cmd; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ctrl_is_load; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ctrl_is_sta; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ctrl_is_std; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_uopc; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_uop_inst; // @[issue-unit.scala:154:28] wire [31:0] issue_slots_31_uop_debug_inst; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_rvc; // @[issue-unit.scala:154:28] wire [39:0] issue_slots_31_uop_debug_pc; // @[issue-unit.scala:154:28] wire [2:0] issue_slots_31_uop_iq_type; // @[issue-unit.scala:154:28] wire [9:0] issue_slots_31_uop_fu_code; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_iw_state; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_iw_p1_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_iw_p2_poisoned; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_br; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_jalr; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_jal; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_sfb; // @[issue-unit.scala:154:28] wire [15:0] issue_slots_31_uop_br_mask; // @[issue-unit.scala:154:28] wire [3:0] issue_slots_31_uop_br_tag; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_ftq_idx; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_edge_inst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_uop_pc_lob; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_taken; // @[issue-unit.scala:154:28] wire [19:0] issue_slots_31_uop_imm_packed; // @[issue-unit.scala:154:28] wire [11:0] issue_slots_31_uop_csr_addr; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_rob_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_ldq_idx; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_stq_idx; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_rxq_idx; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_pdst; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_prs1; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_prs2; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_prs3; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_prs1_busy; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_prs2_busy; // @[issue-unit.scala:154:28] wire [6:0] issue_slots_31_uop_stale_pdst; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_exception; // @[issue-unit.scala:154:28] wire [63:0] issue_slots_31_uop_exc_cause; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_bypassable; // @[issue-unit.scala:154:28] wire [4:0] issue_slots_31_uop_mem_cmd; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_mem_size; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_mem_signed; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_fence; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_fencei; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_amo; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_uses_ldq; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_uses_stq; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_sys_pc2epc; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_is_unique; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_flush_on_commit; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ldst_is_rs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_uop_ldst; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_uop_lrs1; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_uop_lrs2; // @[issue-unit.scala:154:28] wire [5:0] issue_slots_31_uop_lrs3; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_ldst_val; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_dst_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_lrs1_rtype; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_lrs2_rtype; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_frs3_en; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_fp_val; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_fp_single; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_xcpt_pf_if; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_xcpt_ae_if; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_xcpt_ma_if; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_bp_debug_if; // @[issue-unit.scala:154:28] wire issue_slots_31_uop_bp_xcpt_if; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_debug_fsrc; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_uop_debug_tsrc; // @[issue-unit.scala:154:28] wire issue_slots_31_debug_p1; // @[issue-unit.scala:154:28] wire issue_slots_31_debug_p2; // @[issue-unit.scala:154:28] wire issue_slots_31_debug_p3; // @[issue-unit.scala:154:28] wire issue_slots_31_debug_ppred; // @[issue-unit.scala:154:28] wire [1:0] issue_slots_31_debug_state; // @[issue-unit.scala:154:28] wire issue_slots_31_valid; // @[issue-unit.scala:154:28] wire issue_slots_31_will_be_valid; // @[issue-unit.scala:154:28] wire issue_slots_31_request; // @[issue-unit.scala:154:28] wire issue_slots_31_request_hp; // @[issue-unit.scala:154:28] wire issue_slots_31_grant; // @[issue-unit.scala:154:28] wire issue_slots_31_clear; // @[issue-unit.scala:154:28] wire _io_event_empty_T = issue_slots_0_valid | issue_slots_1_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_1 = _io_event_empty_T | issue_slots_2_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_2 = _io_event_empty_T_1 | issue_slots_3_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_3 = _io_event_empty_T_2 | issue_slots_4_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_4 = _io_event_empty_T_3 | issue_slots_5_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_5 = _io_event_empty_T_4 | issue_slots_6_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_6 = _io_event_empty_T_5 | issue_slots_7_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_7 = _io_event_empty_T_6 | issue_slots_8_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_8 = _io_event_empty_T_7 | issue_slots_9_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_9 = _io_event_empty_T_8 | issue_slots_10_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_10 = _io_event_empty_T_9 | issue_slots_11_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_11 = _io_event_empty_T_10 | issue_slots_12_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_12 = _io_event_empty_T_11 | issue_slots_13_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_13 = _io_event_empty_T_12 | issue_slots_14_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_14 = _io_event_empty_T_13 | issue_slots_15_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_15 = _io_event_empty_T_14 | issue_slots_16_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_16 = _io_event_empty_T_15 | issue_slots_17_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_17 = _io_event_empty_T_16 | issue_slots_18_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_18 = _io_event_empty_T_17 | issue_slots_19_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_19 = _io_event_empty_T_18 | issue_slots_20_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_20 = _io_event_empty_T_19 | issue_slots_21_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_21 = _io_event_empty_T_20 | issue_slots_22_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_22 = _io_event_empty_T_21 | issue_slots_23_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_23 = _io_event_empty_T_22 | issue_slots_24_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_24 = _io_event_empty_T_23 | issue_slots_25_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_25 = _io_event_empty_T_24 | issue_slots_26_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_26 = _io_event_empty_T_25 | issue_slots_27_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_27 = _io_event_empty_T_26 | issue_slots_28_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_28 = _io_event_empty_T_27 | issue_slots_29_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_29 = _io_event_empty_T_28 | issue_slots_30_valid; // @[issue-unit.scala:154:28, :165:61] wire _io_event_empty_T_30 = _io_event_empty_T_29 | issue_slots_31_valid; // @[issue-unit.scala:154:28, :165:61] assign _io_event_empty_T_31 = ~_io_event_empty_T_30; // @[issue-unit.scala:165:{21,61}] assign io_event_empty = _io_event_empty_T_31; // @[issue-unit.scala:165:21] wire [1:0] _count_T = {1'h0, _slots_0_io_valid} + {1'h0, _slots_1_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_1 = _count_T; // @[issue-unit.scala:167:23] wire [1:0] _count_T_2 = {1'h0, _slots_2_io_valid} + {1'h0, _slots_3_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_3 = _count_T_2; // @[issue-unit.scala:167:23] wire [2:0] _count_T_4 = {1'h0, _count_T_1} + {1'h0, _count_T_3}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_5 = _count_T_4; // @[issue-unit.scala:167:23] wire [1:0] _count_T_6 = {1'h0, _slots_4_io_valid} + {1'h0, _slots_5_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_7 = _count_T_6; // @[issue-unit.scala:167:23] wire [1:0] _count_T_8 = {1'h0, _slots_6_io_valid} + {1'h0, _slots_7_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_9 = _count_T_8; // @[issue-unit.scala:167:23] wire [2:0] _count_T_10 = {1'h0, _count_T_7} + {1'h0, _count_T_9}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_11 = _count_T_10; // @[issue-unit.scala:167:23] wire [3:0] _count_T_12 = {1'h0, _count_T_5} + {1'h0, _count_T_11}; // @[issue-unit.scala:167:23] wire [3:0] _count_T_13 = _count_T_12; // @[issue-unit.scala:167:23] wire [1:0] _count_T_14 = {1'h0, _slots_8_io_valid} + {1'h0, _slots_9_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_15 = _count_T_14; // @[issue-unit.scala:167:23] wire [1:0] _count_T_16 = {1'h0, _slots_10_io_valid} + {1'h0, _slots_11_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_17 = _count_T_16; // @[issue-unit.scala:167:23] wire [2:0] _count_T_18 = {1'h0, _count_T_15} + {1'h0, _count_T_17}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_19 = _count_T_18; // @[issue-unit.scala:167:23] wire [1:0] _count_T_20 = {1'h0, _slots_12_io_valid} + {1'h0, _slots_13_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_21 = _count_T_20; // @[issue-unit.scala:167:23] wire [1:0] _count_T_22 = {1'h0, _slots_14_io_valid} + {1'h0, _slots_15_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_23 = _count_T_22; // @[issue-unit.scala:167:23] wire [2:0] _count_T_24 = {1'h0, _count_T_21} + {1'h0, _count_T_23}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_25 = _count_T_24; // @[issue-unit.scala:167:23] wire [3:0] _count_T_26 = {1'h0, _count_T_19} + {1'h0, _count_T_25}; // @[issue-unit.scala:167:23] wire [3:0] _count_T_27 = _count_T_26; // @[issue-unit.scala:167:23] wire [4:0] _count_T_28 = {1'h0, _count_T_13} + {1'h0, _count_T_27}; // @[issue-unit.scala:167:23] wire [4:0] _count_T_29 = _count_T_28; // @[issue-unit.scala:167:23] wire [1:0] _count_T_30 = {1'h0, _slots_16_io_valid} + {1'h0, _slots_17_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_31 = _count_T_30; // @[issue-unit.scala:167:23] wire [1:0] _count_T_32 = {1'h0, _slots_18_io_valid} + {1'h0, _slots_19_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_33 = _count_T_32; // @[issue-unit.scala:167:23] wire [2:0] _count_T_34 = {1'h0, _count_T_31} + {1'h0, _count_T_33}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_35 = _count_T_34; // @[issue-unit.scala:167:23] wire [1:0] _count_T_36 = {1'h0, _slots_20_io_valid} + {1'h0, _slots_21_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_37 = _count_T_36; // @[issue-unit.scala:167:23] wire [1:0] _count_T_38 = {1'h0, _slots_22_io_valid} + {1'h0, _slots_23_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_39 = _count_T_38; // @[issue-unit.scala:167:23] wire [2:0] _count_T_40 = {1'h0, _count_T_37} + {1'h0, _count_T_39}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_41 = _count_T_40; // @[issue-unit.scala:167:23] wire [3:0] _count_T_42 = {1'h0, _count_T_35} + {1'h0, _count_T_41}; // @[issue-unit.scala:167:23] wire [3:0] _count_T_43 = _count_T_42; // @[issue-unit.scala:167:23] wire [1:0] _count_T_44 = {1'h0, _slots_24_io_valid} + {1'h0, _slots_25_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_45 = _count_T_44; // @[issue-unit.scala:167:23] wire [1:0] _count_T_46 = {1'h0, _slots_26_io_valid} + {1'h0, _slots_27_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_47 = _count_T_46; // @[issue-unit.scala:167:23] wire [2:0] _count_T_48 = {1'h0, _count_T_45} + {1'h0, _count_T_47}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_49 = _count_T_48; // @[issue-unit.scala:167:23] wire [1:0] _count_T_50 = {1'h0, _slots_28_io_valid} + {1'h0, _slots_29_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_51 = _count_T_50; // @[issue-unit.scala:167:23] wire [1:0] _count_T_52 = {1'h0, _slots_30_io_valid} + {1'h0, _slots_31_io_valid}; // @[issue-unit.scala:153:73, :167:23] wire [1:0] _count_T_53 = _count_T_52; // @[issue-unit.scala:167:23] wire [2:0] _count_T_54 = {1'h0, _count_T_51} + {1'h0, _count_T_53}; // @[issue-unit.scala:167:23] wire [2:0] _count_T_55 = _count_T_54; // @[issue-unit.scala:167:23] wire [3:0] _count_T_56 = {1'h0, _count_T_49} + {1'h0, _count_T_55}; // @[issue-unit.scala:167:23] wire [3:0] _count_T_57 = _count_T_56; // @[issue-unit.scala:167:23] wire [4:0] _count_T_58 = {1'h0, _count_T_43} + {1'h0, _count_T_57}; // @[issue-unit.scala:167:23] wire [4:0] _count_T_59 = _count_T_58; // @[issue-unit.scala:167:23] wire [5:0] _count_T_60 = {1'h0, _count_T_29} + {1'h0, _count_T_59}; // @[issue-unit.scala:167:23] wire [5:0] count = _count_T_60; // @[issue-unit.scala:167:23]
Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_6 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_8 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue128_L2InternalTracking_4 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue64_UInt5_4 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<6>, clock, reset, UInt<6>(0h0) node _T_4 = neq(tags_init_reg, UInt<6>(0h20)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_dic_reader] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [huf_dic_reader] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_12 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_138 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_139 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_140 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_141 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset inst Queue4_L2RespInternal_4 of Queue4_L2RespInternal_142 connect Queue4_L2RespInternal_4.clock, clock connect Queue4_L2RespInternal_4.reset, reset inst Queue4_L2RespInternal_5 of Queue4_L2RespInternal_143 connect Queue4_L2RespInternal_5.clock, clock connect Queue4_L2RespInternal_5.reset, reset inst Queue4_L2RespInternal_6 of Queue4_L2RespInternal_144 connect Queue4_L2RespInternal_6.clock, clock connect Queue4_L2RespInternal_6.reset, reset inst Queue4_L2RespInternal_7 of Queue4_L2RespInternal_145 connect Queue4_L2RespInternal_7.clock, clock connect Queue4_L2RespInternal_7.reset, reset inst Queue4_L2RespInternal_8 of Queue4_L2RespInternal_146 connect Queue4_L2RespInternal_8.clock, clock connect Queue4_L2RespInternal_8.reset, reset inst Queue4_L2RespInternal_9 of Queue4_L2RespInternal_147 connect Queue4_L2RespInternal_9.clock, clock connect Queue4_L2RespInternal_9.reset, reset inst Queue4_L2RespInternal_10 of Queue4_L2RespInternal_148 connect Queue4_L2RespInternal_10.clock, clock connect Queue4_L2RespInternal_10.reset, reset inst Queue4_L2RespInternal_11 of Queue4_L2RespInternal_149 connect Queue4_L2RespInternal_11.clock, clock connect Queue4_L2RespInternal_11.reset, reset inst Queue4_L2RespInternal_12 of Queue4_L2RespInternal_150 connect Queue4_L2RespInternal_12.clock, clock connect Queue4_L2RespInternal_12.reset, reset inst Queue4_L2RespInternal_13 of Queue4_L2RespInternal_151 connect Queue4_L2RespInternal_13.clock, clock connect Queue4_L2RespInternal_13.reset, reset inst Queue4_L2RespInternal_14 of Queue4_L2RespInternal_152 connect Queue4_L2RespInternal_14.clock, clock connect Queue4_L2RespInternal_14.reset, reset inst Queue4_L2RespInternal_15 of Queue4_L2RespInternal_153 connect Queue4_L2RespInternal_15.clock, clock connect Queue4_L2RespInternal_15.reset, reset inst Queue4_L2RespInternal_16 of Queue4_L2RespInternal_154 connect Queue4_L2RespInternal_16.clock, clock connect Queue4_L2RespInternal_16.reset, reset inst Queue4_L2RespInternal_17 of Queue4_L2RespInternal_155 connect Queue4_L2RespInternal_17.clock, clock connect Queue4_L2RespInternal_17.reset, reset inst Queue4_L2RespInternal_18 of Queue4_L2RespInternal_156 connect Queue4_L2RespInternal_18.clock, clock connect Queue4_L2RespInternal_18.reset, reset inst Queue4_L2RespInternal_19 of Queue4_L2RespInternal_157 connect Queue4_L2RespInternal_19.clock, clock connect Queue4_L2RespInternal_19.reset, reset inst Queue4_L2RespInternal_20 of Queue4_L2RespInternal_158 connect Queue4_L2RespInternal_20.clock, clock connect Queue4_L2RespInternal_20.reset, reset inst Queue4_L2RespInternal_21 of Queue4_L2RespInternal_159 connect Queue4_L2RespInternal_21.clock, clock connect Queue4_L2RespInternal_21.reset, reset inst Queue4_L2RespInternal_22 of Queue4_L2RespInternal_160 connect Queue4_L2RespInternal_22.clock, clock connect Queue4_L2RespInternal_22.reset, reset inst Queue4_L2RespInternal_23 of Queue4_L2RespInternal_161 connect Queue4_L2RespInternal_23.clock, clock connect Queue4_L2RespInternal_23.reset, reset inst Queue4_L2RespInternal_24 of Queue4_L2RespInternal_162 connect Queue4_L2RespInternal_24.clock, clock connect Queue4_L2RespInternal_24.reset, reset inst Queue4_L2RespInternal_25 of Queue4_L2RespInternal_163 connect Queue4_L2RespInternal_25.clock, clock connect Queue4_L2RespInternal_25.reset, reset inst Queue4_L2RespInternal_26 of Queue4_L2RespInternal_164 connect Queue4_L2RespInternal_26.clock, clock connect Queue4_L2RespInternal_26.reset, reset inst Queue4_L2RespInternal_27 of Queue4_L2RespInternal_165 connect Queue4_L2RespInternal_27.clock, clock connect Queue4_L2RespInternal_27.reset, reset inst Queue4_L2RespInternal_28 of Queue4_L2RespInternal_166 connect Queue4_L2RespInternal_28.clock, clock connect Queue4_L2RespInternal_28.reset, reset inst Queue4_L2RespInternal_29 of Queue4_L2RespInternal_167 connect Queue4_L2RespInternal_29.clock, clock connect Queue4_L2RespInternal_29.reset, reset inst Queue4_L2RespInternal_30 of Queue4_L2RespInternal_168 connect Queue4_L2RespInternal_30.clock, clock connect Queue4_L2RespInternal_30.reset, reset inst Queue4_L2RespInternal_31 of Queue4_L2RespInternal_169 connect Queue4_L2RespInternal_31.clock, clock connect Queue4_L2RespInternal_31.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = eq(UInt<3>(0h4), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _current_request_tag_has_response_space_T_8) node _current_request_tag_has_response_space_T_10 = eq(UInt<3>(0h5), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _current_request_tag_has_response_space_T_10) node _current_request_tag_has_response_space_T_12 = eq(UInt<3>(0h6), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _current_request_tag_has_response_space_T_12) node _current_request_tag_has_response_space_T_14 = eq(UInt<3>(0h7), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _current_request_tag_has_response_space_T_14) node _current_request_tag_has_response_space_T_16 = eq(UInt<4>(0h8), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _current_request_tag_has_response_space_T_16) node _current_request_tag_has_response_space_T_18 = eq(UInt<4>(0h9), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _current_request_tag_has_response_space_T_18) node _current_request_tag_has_response_space_T_20 = eq(UInt<4>(0ha), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _current_request_tag_has_response_space_T_20) node _current_request_tag_has_response_space_T_22 = eq(UInt<4>(0hb), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _current_request_tag_has_response_space_T_22) node _current_request_tag_has_response_space_T_24 = eq(UInt<4>(0hc), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _current_request_tag_has_response_space_T_24) node _current_request_tag_has_response_space_T_26 = eq(UInt<4>(0hd), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _current_request_tag_has_response_space_T_26) node _current_request_tag_has_response_space_T_28 = eq(UInt<4>(0he), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _current_request_tag_has_response_space_T_28) node _current_request_tag_has_response_space_T_30 = eq(UInt<4>(0hf), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _current_request_tag_has_response_space_T_30) node _current_request_tag_has_response_space_T_32 = eq(UInt<5>(0h10), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _current_request_tag_has_response_space_T_32) node _current_request_tag_has_response_space_T_34 = eq(UInt<5>(0h11), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _current_request_tag_has_response_space_T_34) node _current_request_tag_has_response_space_T_36 = eq(UInt<5>(0h12), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _current_request_tag_has_response_space_T_36) node _current_request_tag_has_response_space_T_38 = eq(UInt<5>(0h13), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _current_request_tag_has_response_space_T_38) node _current_request_tag_has_response_space_T_40 = eq(UInt<5>(0h14), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _current_request_tag_has_response_space_T_40) node _current_request_tag_has_response_space_T_42 = eq(UInt<5>(0h15), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _current_request_tag_has_response_space_T_42) node _current_request_tag_has_response_space_T_44 = eq(UInt<5>(0h16), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _current_request_tag_has_response_space_T_44) node _current_request_tag_has_response_space_T_46 = eq(UInt<5>(0h17), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _current_request_tag_has_response_space_T_46) node _current_request_tag_has_response_space_T_48 = eq(UInt<5>(0h18), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _current_request_tag_has_response_space_T_48) node _current_request_tag_has_response_space_T_50 = eq(UInt<5>(0h19), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _current_request_tag_has_response_space_T_50) node _current_request_tag_has_response_space_T_52 = eq(UInt<5>(0h1a), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _current_request_tag_has_response_space_T_52) node _current_request_tag_has_response_space_T_54 = eq(UInt<5>(0h1b), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _current_request_tag_has_response_space_T_54) node _current_request_tag_has_response_space_T_56 = eq(UInt<5>(0h1c), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _current_request_tag_has_response_space_T_56) node _current_request_tag_has_response_space_T_58 = eq(UInt<5>(0h1d), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _current_request_tag_has_response_space_T_58) node _current_request_tag_has_response_space_T_60 = eq(UInt<5>(0h1e), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _current_request_tag_has_response_space_T_60) node _current_request_tag_has_response_space_T_62 = eq(UInt<5>(0h1f), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _current_request_tag_has_response_space_T_62) node _current_request_tag_has_response_space_T_64 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_65 = or(_current_request_tag_has_response_space_T_64, _current_request_tag_has_response_space_T_5) node _current_request_tag_has_response_space_T_66 = or(_current_request_tag_has_response_space_T_65, _current_request_tag_has_response_space_T_7) node _current_request_tag_has_response_space_T_67 = or(_current_request_tag_has_response_space_T_66, _current_request_tag_has_response_space_T_9) node _current_request_tag_has_response_space_T_68 = or(_current_request_tag_has_response_space_T_67, _current_request_tag_has_response_space_T_11) node _current_request_tag_has_response_space_T_69 = or(_current_request_tag_has_response_space_T_68, _current_request_tag_has_response_space_T_13) node _current_request_tag_has_response_space_T_70 = or(_current_request_tag_has_response_space_T_69, _current_request_tag_has_response_space_T_15) node _current_request_tag_has_response_space_T_71 = or(_current_request_tag_has_response_space_T_70, _current_request_tag_has_response_space_T_17) node _current_request_tag_has_response_space_T_72 = or(_current_request_tag_has_response_space_T_71, _current_request_tag_has_response_space_T_19) node _current_request_tag_has_response_space_T_73 = or(_current_request_tag_has_response_space_T_72, _current_request_tag_has_response_space_T_21) node _current_request_tag_has_response_space_T_74 = or(_current_request_tag_has_response_space_T_73, _current_request_tag_has_response_space_T_23) node _current_request_tag_has_response_space_T_75 = or(_current_request_tag_has_response_space_T_74, _current_request_tag_has_response_space_T_25) node _current_request_tag_has_response_space_T_76 = or(_current_request_tag_has_response_space_T_75, _current_request_tag_has_response_space_T_27) node _current_request_tag_has_response_space_T_77 = or(_current_request_tag_has_response_space_T_76, _current_request_tag_has_response_space_T_29) node _current_request_tag_has_response_space_T_78 = or(_current_request_tag_has_response_space_T_77, _current_request_tag_has_response_space_T_31) node _current_request_tag_has_response_space_T_79 = or(_current_request_tag_has_response_space_T_78, _current_request_tag_has_response_space_T_33) node _current_request_tag_has_response_space_T_80 = or(_current_request_tag_has_response_space_T_79, _current_request_tag_has_response_space_T_35) node _current_request_tag_has_response_space_T_81 = or(_current_request_tag_has_response_space_T_80, _current_request_tag_has_response_space_T_37) node _current_request_tag_has_response_space_T_82 = or(_current_request_tag_has_response_space_T_81, _current_request_tag_has_response_space_T_39) node _current_request_tag_has_response_space_T_83 = or(_current_request_tag_has_response_space_T_82, _current_request_tag_has_response_space_T_41) node _current_request_tag_has_response_space_T_84 = or(_current_request_tag_has_response_space_T_83, _current_request_tag_has_response_space_T_43) node _current_request_tag_has_response_space_T_85 = or(_current_request_tag_has_response_space_T_84, _current_request_tag_has_response_space_T_45) node _current_request_tag_has_response_space_T_86 = or(_current_request_tag_has_response_space_T_85, _current_request_tag_has_response_space_T_47) node _current_request_tag_has_response_space_T_87 = or(_current_request_tag_has_response_space_T_86, _current_request_tag_has_response_space_T_49) node _current_request_tag_has_response_space_T_88 = or(_current_request_tag_has_response_space_T_87, _current_request_tag_has_response_space_T_51) node _current_request_tag_has_response_space_T_89 = or(_current_request_tag_has_response_space_T_88, _current_request_tag_has_response_space_T_53) node _current_request_tag_has_response_space_T_90 = or(_current_request_tag_has_response_space_T_89, _current_request_tag_has_response_space_T_55) node _current_request_tag_has_response_space_T_91 = or(_current_request_tag_has_response_space_T_90, _current_request_tag_has_response_space_T_57) node _current_request_tag_has_response_space_T_92 = or(_current_request_tag_has_response_space_T_91, _current_request_tag_has_response_space_T_59) node _current_request_tag_has_response_space_T_93 = or(_current_request_tag_has_response_space_T_92, _current_request_tag_has_response_space_T_61) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_93, _current_request_tag_has_response_space_T_63) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 inst response_latency_injection_q of LatencyInjectionQueue_13 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = eq(UInt<3>(0h4), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _selectQready_T_8) node _selectQready_T_10 = eq(UInt<3>(0h5), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _selectQready_T_10) node _selectQready_T_12 = eq(UInt<3>(0h6), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _selectQready_T_12) node _selectQready_T_14 = eq(UInt<3>(0h7), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _selectQready_T_14) node _selectQready_T_16 = eq(UInt<4>(0h8), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _selectQready_T_16) node _selectQready_T_18 = eq(UInt<4>(0h9), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _selectQready_T_18) node _selectQready_T_20 = eq(UInt<4>(0ha), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _selectQready_T_20) node _selectQready_T_22 = eq(UInt<4>(0hb), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _selectQready_T_22) node _selectQready_T_24 = eq(UInt<4>(0hc), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _selectQready_T_24) node _selectQready_T_26 = eq(UInt<4>(0hd), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _selectQready_T_26) node _selectQready_T_28 = eq(UInt<4>(0he), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _selectQready_T_28) node _selectQready_T_30 = eq(UInt<4>(0hf), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _selectQready_T_30) node _selectQready_T_32 = eq(UInt<5>(0h10), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _selectQready_T_32) node _selectQready_T_34 = eq(UInt<5>(0h11), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _selectQready_T_34) node _selectQready_T_36 = eq(UInt<5>(0h12), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _selectQready_T_36) node _selectQready_T_38 = eq(UInt<5>(0h13), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _selectQready_T_38) node _selectQready_T_40 = eq(UInt<5>(0h14), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _selectQready_T_40) node _selectQready_T_42 = eq(UInt<5>(0h15), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _selectQready_T_42) node _selectQready_T_44 = eq(UInt<5>(0h16), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _selectQready_T_44) node _selectQready_T_46 = eq(UInt<5>(0h17), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _selectQready_T_46) node _selectQready_T_48 = eq(UInt<5>(0h18), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _selectQready_T_48) node _selectQready_T_50 = eq(UInt<5>(0h19), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _selectQready_T_50) node _selectQready_T_52 = eq(UInt<5>(0h1a), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _selectQready_T_52) node _selectQready_T_54 = eq(UInt<5>(0h1b), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _selectQready_T_54) node _selectQready_T_56 = eq(UInt<5>(0h1c), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _selectQready_T_56) node _selectQready_T_58 = eq(UInt<5>(0h1d), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _selectQready_T_58) node _selectQready_T_60 = eq(UInt<5>(0h1e), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _selectQready_T_60) node _selectQready_T_62 = eq(UInt<5>(0h1f), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _selectQready_T_62) node _selectQready_T_64 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_65 = or(_selectQready_T_64, _selectQready_T_5) node _selectQready_T_66 = or(_selectQready_T_65, _selectQready_T_7) node _selectQready_T_67 = or(_selectQready_T_66, _selectQready_T_9) node _selectQready_T_68 = or(_selectQready_T_67, _selectQready_T_11) node _selectQready_T_69 = or(_selectQready_T_68, _selectQready_T_13) node _selectQready_T_70 = or(_selectQready_T_69, _selectQready_T_15) node _selectQready_T_71 = or(_selectQready_T_70, _selectQready_T_17) node _selectQready_T_72 = or(_selectQready_T_71, _selectQready_T_19) node _selectQready_T_73 = or(_selectQready_T_72, _selectQready_T_21) node _selectQready_T_74 = or(_selectQready_T_73, _selectQready_T_23) node _selectQready_T_75 = or(_selectQready_T_74, _selectQready_T_25) node _selectQready_T_76 = or(_selectQready_T_75, _selectQready_T_27) node _selectQready_T_77 = or(_selectQready_T_76, _selectQready_T_29) node _selectQready_T_78 = or(_selectQready_T_77, _selectQready_T_31) node _selectQready_T_79 = or(_selectQready_T_78, _selectQready_T_33) node _selectQready_T_80 = or(_selectQready_T_79, _selectQready_T_35) node _selectQready_T_81 = or(_selectQready_T_80, _selectQready_T_37) node _selectQready_T_82 = or(_selectQready_T_81, _selectQready_T_39) node _selectQready_T_83 = or(_selectQready_T_82, _selectQready_T_41) node _selectQready_T_84 = or(_selectQready_T_83, _selectQready_T_43) node _selectQready_T_85 = or(_selectQready_T_84, _selectQready_T_45) node _selectQready_T_86 = or(_selectQready_T_85, _selectQready_T_47) node _selectQready_T_87 = or(_selectQready_T_86, _selectQready_T_49) node _selectQready_T_88 = or(_selectQready_T_87, _selectQready_T_51) node _selectQready_T_89 = or(_selectQready_T_88, _selectQready_T_53) node _selectQready_T_90 = or(_selectQready_T_89, _selectQready_T_55) node _selectQready_T_91 = or(_selectQready_T_90, _selectQready_T_57) node _selectQready_T_92 = or(_selectQready_T_91, _selectQready_T_59) node _selectQready_T_93 = or(_selectQready_T_92, _selectQready_T_61) node selectQready = or(_selectQready_T_93, _selectQready_T_63) node _T_56 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_56 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_57 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_58 = and(_T_57, tags_for_issue_Q.io.enq.valid) when _T_58 : regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_20 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_63 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_64 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) connect Queue4_L2RespInternal.io.enq.valid, _T_65 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_66 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_67 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_68 = and(_T_66, _T_67) connect Queue4_L2RespInternal_1.io.enq.valid, _T_68 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_69 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_70 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_71 = and(_T_69, _T_70) connect Queue4_L2RespInternal_2.io.enq.valid, _T_71 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_72 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_73 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_74 = and(_T_72, _T_73) connect Queue4_L2RespInternal_3.io.enq.valid, _T_74 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_75 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_76 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h4)) node _T_77 = and(_T_75, _T_76) connect Queue4_L2RespInternal_4.io.enq.valid, _T_77 connect Queue4_L2RespInternal_4.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_78 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_79 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h5)) node _T_80 = and(_T_78, _T_79) connect Queue4_L2RespInternal_5.io.enq.valid, _T_80 connect Queue4_L2RespInternal_5.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_81 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_82 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h6)) node _T_83 = and(_T_81, _T_82) connect Queue4_L2RespInternal_6.io.enq.valid, _T_83 connect Queue4_L2RespInternal_6.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_84 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_85 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h7)) node _T_86 = and(_T_84, _T_85) connect Queue4_L2RespInternal_7.io.enq.valid, _T_86 connect Queue4_L2RespInternal_7.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_87 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_88 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h8)) node _T_89 = and(_T_87, _T_88) connect Queue4_L2RespInternal_8.io.enq.valid, _T_89 connect Queue4_L2RespInternal_8.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_90 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_91 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h9)) node _T_92 = and(_T_90, _T_91) connect Queue4_L2RespInternal_9.io.enq.valid, _T_92 connect Queue4_L2RespInternal_9.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_93 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_94 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0ha)) node _T_95 = and(_T_93, _T_94) connect Queue4_L2RespInternal_10.io.enq.valid, _T_95 connect Queue4_L2RespInternal_10.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_96 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_97 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hb)) node _T_98 = and(_T_96, _T_97) connect Queue4_L2RespInternal_11.io.enq.valid, _T_98 connect Queue4_L2RespInternal_11.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_99 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_100 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) connect Queue4_L2RespInternal_12.io.enq.valid, _T_101 connect Queue4_L2RespInternal_12.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_102 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_103 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hd)) node _T_104 = and(_T_102, _T_103) connect Queue4_L2RespInternal_13.io.enq.valid, _T_104 connect Queue4_L2RespInternal_13.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_105 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_106 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0he)) node _T_107 = and(_T_105, _T_106) connect Queue4_L2RespInternal_14.io.enq.valid, _T_107 connect Queue4_L2RespInternal_14.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_108 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_109 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hf)) node _T_110 = and(_T_108, _T_109) connect Queue4_L2RespInternal_15.io.enq.valid, _T_110 connect Queue4_L2RespInternal_15.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_111 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_112 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h10)) node _T_113 = and(_T_111, _T_112) connect Queue4_L2RespInternal_16.io.enq.valid, _T_113 connect Queue4_L2RespInternal_16.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_114 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_115 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h11)) node _T_116 = and(_T_114, _T_115) connect Queue4_L2RespInternal_17.io.enq.valid, _T_116 connect Queue4_L2RespInternal_17.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_117 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_118 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h12)) node _T_119 = and(_T_117, _T_118) connect Queue4_L2RespInternal_18.io.enq.valid, _T_119 connect Queue4_L2RespInternal_18.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_120 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_121 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h13)) node _T_122 = and(_T_120, _T_121) connect Queue4_L2RespInternal_19.io.enq.valid, _T_122 connect Queue4_L2RespInternal_19.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_123 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_124 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h14)) node _T_125 = and(_T_123, _T_124) connect Queue4_L2RespInternal_20.io.enq.valid, _T_125 connect Queue4_L2RespInternal_20.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_126 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_127 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h15)) node _T_128 = and(_T_126, _T_127) connect Queue4_L2RespInternal_21.io.enq.valid, _T_128 connect Queue4_L2RespInternal_21.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_129 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_130 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h16)) node _T_131 = and(_T_129, _T_130) connect Queue4_L2RespInternal_22.io.enq.valid, _T_131 connect Queue4_L2RespInternal_22.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_132 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_133 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h17)) node _T_134 = and(_T_132, _T_133) connect Queue4_L2RespInternal_23.io.enq.valid, _T_134 connect Queue4_L2RespInternal_23.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_135 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_136 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h18)) node _T_137 = and(_T_135, _T_136) connect Queue4_L2RespInternal_24.io.enq.valid, _T_137 connect Queue4_L2RespInternal_24.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_138 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_139 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h19)) node _T_140 = and(_T_138, _T_139) connect Queue4_L2RespInternal_25.io.enq.valid, _T_140 connect Queue4_L2RespInternal_25.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_141 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_142 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1a)) node _T_143 = and(_T_141, _T_142) connect Queue4_L2RespInternal_26.io.enq.valid, _T_143 connect Queue4_L2RespInternal_26.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_144 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_145 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1b)) node _T_146 = and(_T_144, _T_145) connect Queue4_L2RespInternal_27.io.enq.valid, _T_146 connect Queue4_L2RespInternal_27.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_147 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_148 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1c)) node _T_149 = and(_T_147, _T_148) connect Queue4_L2RespInternal_28.io.enq.valid, _T_149 connect Queue4_L2RespInternal_28.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_150 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_151 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1d)) node _T_152 = and(_T_150, _T_151) connect Queue4_L2RespInternal_29.io.enq.valid, _T_152 connect Queue4_L2RespInternal_29.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_153 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_154 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1e)) node _T_155 = and(_T_153, _T_154) connect Queue4_L2RespInternal_30.io.enq.valid, _T_155 connect Queue4_L2RespInternal_30.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_156 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_157 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) connect Queue4_L2RespInternal_31.io.enq.valid, _T_158 connect Queue4_L2RespInternal_31.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_9 = and(Queue4_L2RespInternal_4.io.deq.valid, _queueValid_T_8) node _queueValid_T_10 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_11 = and(Queue4_L2RespInternal_5.io.deq.valid, _queueValid_T_10) node _queueValid_T_12 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_13 = and(Queue4_L2RespInternal_6.io.deq.valid, _queueValid_T_12) node _queueValid_T_14 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_15 = and(Queue4_L2RespInternal_7.io.deq.valid, _queueValid_T_14) node _queueValid_T_16 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_17 = and(Queue4_L2RespInternal_8.io.deq.valid, _queueValid_T_16) node _queueValid_T_18 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_19 = and(Queue4_L2RespInternal_9.io.deq.valid, _queueValid_T_18) node _queueValid_T_20 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_21 = and(Queue4_L2RespInternal_10.io.deq.valid, _queueValid_T_20) node _queueValid_T_22 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_23 = and(Queue4_L2RespInternal_11.io.deq.valid, _queueValid_T_22) node _queueValid_T_24 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_25 = and(Queue4_L2RespInternal_12.io.deq.valid, _queueValid_T_24) node _queueValid_T_26 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_27 = and(Queue4_L2RespInternal_13.io.deq.valid, _queueValid_T_26) node _queueValid_T_28 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_29 = and(Queue4_L2RespInternal_14.io.deq.valid, _queueValid_T_28) node _queueValid_T_30 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_31 = and(Queue4_L2RespInternal_15.io.deq.valid, _queueValid_T_30) node _queueValid_T_32 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_33 = and(Queue4_L2RespInternal_16.io.deq.valid, _queueValid_T_32) node _queueValid_T_34 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_35 = and(Queue4_L2RespInternal_17.io.deq.valid, _queueValid_T_34) node _queueValid_T_36 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_37 = and(Queue4_L2RespInternal_18.io.deq.valid, _queueValid_T_36) node _queueValid_T_38 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_39 = and(Queue4_L2RespInternal_19.io.deq.valid, _queueValid_T_38) node _queueValid_T_40 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_41 = and(Queue4_L2RespInternal_20.io.deq.valid, _queueValid_T_40) node _queueValid_T_42 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_43 = and(Queue4_L2RespInternal_21.io.deq.valid, _queueValid_T_42) node _queueValid_T_44 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_45 = and(Queue4_L2RespInternal_22.io.deq.valid, _queueValid_T_44) node _queueValid_T_46 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_47 = and(Queue4_L2RespInternal_23.io.deq.valid, _queueValid_T_46) node _queueValid_T_48 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_49 = and(Queue4_L2RespInternal_24.io.deq.valid, _queueValid_T_48) node _queueValid_T_50 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_51 = and(Queue4_L2RespInternal_25.io.deq.valid, _queueValid_T_50) node _queueValid_T_52 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_53 = and(Queue4_L2RespInternal_26.io.deq.valid, _queueValid_T_52) node _queueValid_T_54 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_55 = and(Queue4_L2RespInternal_27.io.deq.valid, _queueValid_T_54) node _queueValid_T_56 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_57 = and(Queue4_L2RespInternal_28.io.deq.valid, _queueValid_T_56) node _queueValid_T_58 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_59 = and(Queue4_L2RespInternal_29.io.deq.valid, _queueValid_T_58) node _queueValid_T_60 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_61 = and(Queue4_L2RespInternal_30.io.deq.valid, _queueValid_T_60) node _queueValid_T_62 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_63 = and(Queue4_L2RespInternal_31.io.deq.valid, _queueValid_T_62) node _queueValid_T_64 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_65 = or(_queueValid_T_64, _queueValid_T_5) node _queueValid_T_66 = or(_queueValid_T_65, _queueValid_T_7) node _queueValid_T_67 = or(_queueValid_T_66, _queueValid_T_9) node _queueValid_T_68 = or(_queueValid_T_67, _queueValid_T_11) node _queueValid_T_69 = or(_queueValid_T_68, _queueValid_T_13) node _queueValid_T_70 = or(_queueValid_T_69, _queueValid_T_15) node _queueValid_T_71 = or(_queueValid_T_70, _queueValid_T_17) node _queueValid_T_72 = or(_queueValid_T_71, _queueValid_T_19) node _queueValid_T_73 = or(_queueValid_T_72, _queueValid_T_21) node _queueValid_T_74 = or(_queueValid_T_73, _queueValid_T_23) node _queueValid_T_75 = or(_queueValid_T_74, _queueValid_T_25) node _queueValid_T_76 = or(_queueValid_T_75, _queueValid_T_27) node _queueValid_T_77 = or(_queueValid_T_76, _queueValid_T_29) node _queueValid_T_78 = or(_queueValid_T_77, _queueValid_T_31) node _queueValid_T_79 = or(_queueValid_T_78, _queueValid_T_33) node _queueValid_T_80 = or(_queueValid_T_79, _queueValid_T_35) node _queueValid_T_81 = or(_queueValid_T_80, _queueValid_T_37) node _queueValid_T_82 = or(_queueValid_T_81, _queueValid_T_39) node _queueValid_T_83 = or(_queueValid_T_82, _queueValid_T_41) node _queueValid_T_84 = or(_queueValid_T_83, _queueValid_T_43) node _queueValid_T_85 = or(_queueValid_T_84, _queueValid_T_45) node _queueValid_T_86 = or(_queueValid_T_85, _queueValid_T_47) node _queueValid_T_87 = or(_queueValid_T_86, _queueValid_T_49) node _queueValid_T_88 = or(_queueValid_T_87, _queueValid_T_51) node _queueValid_T_89 = or(_queueValid_T_88, _queueValid_T_53) node _queueValid_T_90 = or(_queueValid_T_89, _queueValid_T_55) node _queueValid_T_91 = or(_queueValid_T_90, _queueValid_T_57) node _queueValid_T_92 = or(_queueValid_T_91, _queueValid_T_59) node _queueValid_T_93 = or(_queueValid_T_92, _queueValid_T_61) node queueValid = or(_queueValid_T_93, _queueValid_T_63) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node resultdata_is_current_q_4 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_4 : UInt<256> when resultdata_is_current_q_4 : node _resultdata_data_T_8 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_9 = dshr(Queue4_L2RespInternal_4.io.deq.bits.data, _resultdata_data_T_8) connect resultdata_data_4, _resultdata_data_T_9 else : connect resultdata_data_4, UInt<1>(0h0) node resultdata_is_current_q_5 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_5 : UInt<256> when resultdata_is_current_q_5 : node _resultdata_data_T_10 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_11 = dshr(Queue4_L2RespInternal_5.io.deq.bits.data, _resultdata_data_T_10) connect resultdata_data_5, _resultdata_data_T_11 else : connect resultdata_data_5, UInt<1>(0h0) node resultdata_is_current_q_6 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_6 : UInt<256> when resultdata_is_current_q_6 : node _resultdata_data_T_12 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_13 = dshr(Queue4_L2RespInternal_6.io.deq.bits.data, _resultdata_data_T_12) connect resultdata_data_6, _resultdata_data_T_13 else : connect resultdata_data_6, UInt<1>(0h0) node resultdata_is_current_q_7 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_7 : UInt<256> when resultdata_is_current_q_7 : node _resultdata_data_T_14 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_15 = dshr(Queue4_L2RespInternal_7.io.deq.bits.data, _resultdata_data_T_14) connect resultdata_data_7, _resultdata_data_T_15 else : connect resultdata_data_7, UInt<1>(0h0) node resultdata_is_current_q_8 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_8 : UInt<256> when resultdata_is_current_q_8 : node _resultdata_data_T_16 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_17 = dshr(Queue4_L2RespInternal_8.io.deq.bits.data, _resultdata_data_T_16) connect resultdata_data_8, _resultdata_data_T_17 else : connect resultdata_data_8, UInt<1>(0h0) node resultdata_is_current_q_9 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_9 : UInt<256> when resultdata_is_current_q_9 : node _resultdata_data_T_18 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_19 = dshr(Queue4_L2RespInternal_9.io.deq.bits.data, _resultdata_data_T_18) connect resultdata_data_9, _resultdata_data_T_19 else : connect resultdata_data_9, UInt<1>(0h0) node resultdata_is_current_q_10 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_10 : UInt<256> when resultdata_is_current_q_10 : node _resultdata_data_T_20 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_21 = dshr(Queue4_L2RespInternal_10.io.deq.bits.data, _resultdata_data_T_20) connect resultdata_data_10, _resultdata_data_T_21 else : connect resultdata_data_10, UInt<1>(0h0) node resultdata_is_current_q_11 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_11 : UInt<256> when resultdata_is_current_q_11 : node _resultdata_data_T_22 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_23 = dshr(Queue4_L2RespInternal_11.io.deq.bits.data, _resultdata_data_T_22) connect resultdata_data_11, _resultdata_data_T_23 else : connect resultdata_data_11, UInt<1>(0h0) node resultdata_is_current_q_12 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_12 : UInt<256> when resultdata_is_current_q_12 : node _resultdata_data_T_24 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_25 = dshr(Queue4_L2RespInternal_12.io.deq.bits.data, _resultdata_data_T_24) connect resultdata_data_12, _resultdata_data_T_25 else : connect resultdata_data_12, UInt<1>(0h0) node resultdata_is_current_q_13 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_13 : UInt<256> when resultdata_is_current_q_13 : node _resultdata_data_T_26 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_27 = dshr(Queue4_L2RespInternal_13.io.deq.bits.data, _resultdata_data_T_26) connect resultdata_data_13, _resultdata_data_T_27 else : connect resultdata_data_13, UInt<1>(0h0) node resultdata_is_current_q_14 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_14 : UInt<256> when resultdata_is_current_q_14 : node _resultdata_data_T_28 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_29 = dshr(Queue4_L2RespInternal_14.io.deq.bits.data, _resultdata_data_T_28) connect resultdata_data_14, _resultdata_data_T_29 else : connect resultdata_data_14, UInt<1>(0h0) node resultdata_is_current_q_15 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_15 : UInt<256> when resultdata_is_current_q_15 : node _resultdata_data_T_30 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_31 = dshr(Queue4_L2RespInternal_15.io.deq.bits.data, _resultdata_data_T_30) connect resultdata_data_15, _resultdata_data_T_31 else : connect resultdata_data_15, UInt<1>(0h0) node resultdata_is_current_q_16 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_16 : UInt<256> when resultdata_is_current_q_16 : node _resultdata_data_T_32 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_33 = dshr(Queue4_L2RespInternal_16.io.deq.bits.data, _resultdata_data_T_32) connect resultdata_data_16, _resultdata_data_T_33 else : connect resultdata_data_16, UInt<1>(0h0) node resultdata_is_current_q_17 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_17 : UInt<256> when resultdata_is_current_q_17 : node _resultdata_data_T_34 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_35 = dshr(Queue4_L2RespInternal_17.io.deq.bits.data, _resultdata_data_T_34) connect resultdata_data_17, _resultdata_data_T_35 else : connect resultdata_data_17, UInt<1>(0h0) node resultdata_is_current_q_18 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_18 : UInt<256> when resultdata_is_current_q_18 : node _resultdata_data_T_36 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_37 = dshr(Queue4_L2RespInternal_18.io.deq.bits.data, _resultdata_data_T_36) connect resultdata_data_18, _resultdata_data_T_37 else : connect resultdata_data_18, UInt<1>(0h0) node resultdata_is_current_q_19 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_19 : UInt<256> when resultdata_is_current_q_19 : node _resultdata_data_T_38 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_39 = dshr(Queue4_L2RespInternal_19.io.deq.bits.data, _resultdata_data_T_38) connect resultdata_data_19, _resultdata_data_T_39 else : connect resultdata_data_19, UInt<1>(0h0) node resultdata_is_current_q_20 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_20 : UInt<256> when resultdata_is_current_q_20 : node _resultdata_data_T_40 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_41 = dshr(Queue4_L2RespInternal_20.io.deq.bits.data, _resultdata_data_T_40) connect resultdata_data_20, _resultdata_data_T_41 else : connect resultdata_data_20, UInt<1>(0h0) node resultdata_is_current_q_21 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_21 : UInt<256> when resultdata_is_current_q_21 : node _resultdata_data_T_42 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_43 = dshr(Queue4_L2RespInternal_21.io.deq.bits.data, _resultdata_data_T_42) connect resultdata_data_21, _resultdata_data_T_43 else : connect resultdata_data_21, UInt<1>(0h0) node resultdata_is_current_q_22 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_22 : UInt<256> when resultdata_is_current_q_22 : node _resultdata_data_T_44 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_45 = dshr(Queue4_L2RespInternal_22.io.deq.bits.data, _resultdata_data_T_44) connect resultdata_data_22, _resultdata_data_T_45 else : connect resultdata_data_22, UInt<1>(0h0) node resultdata_is_current_q_23 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_23 : UInt<256> when resultdata_is_current_q_23 : node _resultdata_data_T_46 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_47 = dshr(Queue4_L2RespInternal_23.io.deq.bits.data, _resultdata_data_T_46) connect resultdata_data_23, _resultdata_data_T_47 else : connect resultdata_data_23, UInt<1>(0h0) node resultdata_is_current_q_24 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_24 : UInt<256> when resultdata_is_current_q_24 : node _resultdata_data_T_48 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_49 = dshr(Queue4_L2RespInternal_24.io.deq.bits.data, _resultdata_data_T_48) connect resultdata_data_24, _resultdata_data_T_49 else : connect resultdata_data_24, UInt<1>(0h0) node resultdata_is_current_q_25 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_25 : UInt<256> when resultdata_is_current_q_25 : node _resultdata_data_T_50 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_51 = dshr(Queue4_L2RespInternal_25.io.deq.bits.data, _resultdata_data_T_50) connect resultdata_data_25, _resultdata_data_T_51 else : connect resultdata_data_25, UInt<1>(0h0) node resultdata_is_current_q_26 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_26 : UInt<256> when resultdata_is_current_q_26 : node _resultdata_data_T_52 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_53 = dshr(Queue4_L2RespInternal_26.io.deq.bits.data, _resultdata_data_T_52) connect resultdata_data_26, _resultdata_data_T_53 else : connect resultdata_data_26, UInt<1>(0h0) node resultdata_is_current_q_27 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_27 : UInt<256> when resultdata_is_current_q_27 : node _resultdata_data_T_54 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_55 = dshr(Queue4_L2RespInternal_27.io.deq.bits.data, _resultdata_data_T_54) connect resultdata_data_27, _resultdata_data_T_55 else : connect resultdata_data_27, UInt<1>(0h0) node resultdata_is_current_q_28 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_28 : UInt<256> when resultdata_is_current_q_28 : node _resultdata_data_T_56 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_57 = dshr(Queue4_L2RespInternal_28.io.deq.bits.data, _resultdata_data_T_56) connect resultdata_data_28, _resultdata_data_T_57 else : connect resultdata_data_28, UInt<1>(0h0) node resultdata_is_current_q_29 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_29 : UInt<256> when resultdata_is_current_q_29 : node _resultdata_data_T_58 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_59 = dshr(Queue4_L2RespInternal_29.io.deq.bits.data, _resultdata_data_T_58) connect resultdata_data_29, _resultdata_data_T_59 else : connect resultdata_data_29, UInt<1>(0h0) node resultdata_is_current_q_30 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_30 : UInt<256> when resultdata_is_current_q_30 : node _resultdata_data_T_60 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_61 = dshr(Queue4_L2RespInternal_30.io.deq.bits.data, _resultdata_data_T_60) connect resultdata_data_30, _resultdata_data_T_61 else : connect resultdata_data_30, UInt<1>(0h0) node resultdata_is_current_q_31 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_31 : UInt<256> when resultdata_is_current_q_31 : node _resultdata_data_T_62 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_63 = dshr(Queue4_L2RespInternal_31.io.deq.bits.data, _resultdata_data_T_62) connect resultdata_data_31, _resultdata_data_T_63 else : connect resultdata_data_31, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node _resultdata_T_2 = or(_resultdata_T_1, resultdata_data_3) node _resultdata_T_3 = or(_resultdata_T_2, resultdata_data_4) node _resultdata_T_4 = or(_resultdata_T_3, resultdata_data_5) node _resultdata_T_5 = or(_resultdata_T_4, resultdata_data_6) node _resultdata_T_6 = or(_resultdata_T_5, resultdata_data_7) node _resultdata_T_7 = or(_resultdata_T_6, resultdata_data_8) node _resultdata_T_8 = or(_resultdata_T_7, resultdata_data_9) node _resultdata_T_9 = or(_resultdata_T_8, resultdata_data_10) node _resultdata_T_10 = or(_resultdata_T_9, resultdata_data_11) node _resultdata_T_11 = or(_resultdata_T_10, resultdata_data_12) node _resultdata_T_12 = or(_resultdata_T_11, resultdata_data_13) node _resultdata_T_13 = or(_resultdata_T_12, resultdata_data_14) node _resultdata_T_14 = or(_resultdata_T_13, resultdata_data_15) node _resultdata_T_15 = or(_resultdata_T_14, resultdata_data_16) node _resultdata_T_16 = or(_resultdata_T_15, resultdata_data_17) node _resultdata_T_17 = or(_resultdata_T_16, resultdata_data_18) node _resultdata_T_18 = or(_resultdata_T_17, resultdata_data_19) node _resultdata_T_19 = or(_resultdata_T_18, resultdata_data_20) node _resultdata_T_20 = or(_resultdata_T_19, resultdata_data_21) node _resultdata_T_21 = or(_resultdata_T_20, resultdata_data_22) node _resultdata_T_22 = or(_resultdata_T_21, resultdata_data_23) node _resultdata_T_23 = or(_resultdata_T_22, resultdata_data_24) node _resultdata_T_24 = or(_resultdata_T_23, resultdata_data_25) node _resultdata_T_25 = or(_resultdata_T_24, resultdata_data_26) node _resultdata_T_26 = or(_resultdata_T_25, resultdata_data_27) node _resultdata_T_27 = or(_resultdata_T_26, resultdata_data_28) node _resultdata_T_28 = or(_resultdata_T_27, resultdata_data_29) node _resultdata_T_29 = or(_resultdata_T_28, resultdata_data_30) node resultdata = or(_resultdata_T_29, resultdata_data_31) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_159 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_160 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) connect Queue4_L2RespInternal.io.deq.ready, _T_161 node _T_162 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_163 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_164 = and(_T_162, _T_163) connect Queue4_L2RespInternal_1.io.deq.ready, _T_164 node _T_165 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_166 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_167 = and(_T_165, _T_166) connect Queue4_L2RespInternal_2.io.deq.ready, _T_167 node _T_168 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_169 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_170 = and(_T_168, _T_169) connect Queue4_L2RespInternal_3.io.deq.ready, _T_170 node _T_171 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_172 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h4)) node _T_173 = and(_T_171, _T_172) connect Queue4_L2RespInternal_4.io.deq.ready, _T_173 node _T_174 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_175 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h5)) node _T_176 = and(_T_174, _T_175) connect Queue4_L2RespInternal_5.io.deq.ready, _T_176 node _T_177 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_178 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h6)) node _T_179 = and(_T_177, _T_178) connect Queue4_L2RespInternal_6.io.deq.ready, _T_179 node _T_180 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_181 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h7)) node _T_182 = and(_T_180, _T_181) connect Queue4_L2RespInternal_7.io.deq.ready, _T_182 node _T_183 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_184 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h8)) node _T_185 = and(_T_183, _T_184) connect Queue4_L2RespInternal_8.io.deq.ready, _T_185 node _T_186 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_187 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h9)) node _T_188 = and(_T_186, _T_187) connect Queue4_L2RespInternal_9.io.deq.ready, _T_188 node _T_189 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_190 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0ha)) node _T_191 = and(_T_189, _T_190) connect Queue4_L2RespInternal_10.io.deq.ready, _T_191 node _T_192 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_193 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hb)) node _T_194 = and(_T_192, _T_193) connect Queue4_L2RespInternal_11.io.deq.ready, _T_194 node _T_195 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_196 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hc)) node _T_197 = and(_T_195, _T_196) connect Queue4_L2RespInternal_12.io.deq.ready, _T_197 node _T_198 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_199 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hd)) node _T_200 = and(_T_198, _T_199) connect Queue4_L2RespInternal_13.io.deq.ready, _T_200 node _T_201 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_202 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0he)) node _T_203 = and(_T_201, _T_202) connect Queue4_L2RespInternal_14.io.deq.ready, _T_203 node _T_204 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_205 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hf)) node _T_206 = and(_T_204, _T_205) connect Queue4_L2RespInternal_15.io.deq.ready, _T_206 node _T_207 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_208 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h10)) node _T_209 = and(_T_207, _T_208) connect Queue4_L2RespInternal_16.io.deq.ready, _T_209 node _T_210 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_211 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h11)) node _T_212 = and(_T_210, _T_211) connect Queue4_L2RespInternal_17.io.deq.ready, _T_212 node _T_213 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_214 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h12)) node _T_215 = and(_T_213, _T_214) connect Queue4_L2RespInternal_18.io.deq.ready, _T_215 node _T_216 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_217 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h13)) node _T_218 = and(_T_216, _T_217) connect Queue4_L2RespInternal_19.io.deq.ready, _T_218 node _T_219 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_220 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h14)) node _T_221 = and(_T_219, _T_220) connect Queue4_L2RespInternal_20.io.deq.ready, _T_221 node _T_222 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_223 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h15)) node _T_224 = and(_T_222, _T_223) connect Queue4_L2RespInternal_21.io.deq.ready, _T_224 node _T_225 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_226 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h16)) node _T_227 = and(_T_225, _T_226) connect Queue4_L2RespInternal_22.io.deq.ready, _T_227 node _T_228 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_229 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h17)) node _T_230 = and(_T_228, _T_229) connect Queue4_L2RespInternal_23.io.deq.ready, _T_230 node _T_231 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_232 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h18)) node _T_233 = and(_T_231, _T_232) connect Queue4_L2RespInternal_24.io.deq.ready, _T_233 node _T_234 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_235 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h19)) node _T_236 = and(_T_234, _T_235) connect Queue4_L2RespInternal_25.io.deq.ready, _T_236 node _T_237 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_238 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1a)) node _T_239 = and(_T_237, _T_238) connect Queue4_L2RespInternal_26.io.deq.ready, _T_239 node _T_240 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_241 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1b)) node _T_242 = and(_T_240, _T_241) connect Queue4_L2RespInternal_27.io.deq.ready, _T_242 node _T_243 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_244 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1c)) node _T_245 = and(_T_243, _T_244) connect Queue4_L2RespInternal_28.io.deq.ready, _T_245 node _T_246 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_247 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1d)) node _T_248 = and(_T_246, _T_247) connect Queue4_L2RespInternal_29.io.deq.ready, _T_248 node _T_249 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_250 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1e)) node _T_251 = and(_T_249, _T_250) connect Queue4_L2RespInternal_30.io.deq.ready, _T_251 node _T_252 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_253 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1f)) node _T_254 = and(_T_252, _T_253) connect Queue4_L2RespInternal_31.io.deq.ready, _T_254 node _T_255 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_255 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_22 else : regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_24 node _T_264 = and(response_output.ready, response_output.valid) when _T_264 : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "[huf_dic_reader] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_26 node _T_269 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_269 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_270 = and(response_output.ready, response_output.valid) when _T_270 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_128 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_129 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module L2MemHelperLatencyInjection_6( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [70:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_bits_cmd, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [70:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd_0 = io_userif_req_bits_cmd; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [70:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire request_input_bits_cmd = io_userif_req_bits_cmd_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = request_input_bits_addr & addr_mask_check; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 | _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 | _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 | _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 | _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 | _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 | _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 | _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 | _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 | _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 | _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 | _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 | _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 | _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 | _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 | _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 | _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 | _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 | _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 | _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 | _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 | _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 | _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 | _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 | _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 | _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 | _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 | _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 | _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 | _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 | _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 | _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 | _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 | _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 | _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 | _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 | _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 | _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 | _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 | _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 | _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 | _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 | _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 | _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 | _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 | _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 | _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 | _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 | _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 | _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 | _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 | _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 | _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 | _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 | _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 | _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 | _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 | _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 | _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 | _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 | _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 | _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 | _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 | _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 | _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 | _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 | _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 | _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 | _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 | _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 | _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 | _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 | _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 | _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 | _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 | _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 | _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 | _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 | _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 | _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 | _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 | _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 | _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 | _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 | _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 | _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 | _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 | _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 | _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 | _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 | _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 | _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 | _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [70:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {66'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 | _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 | _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 | _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 | _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 | _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 | _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 | _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 | _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 | _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 | _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 | _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 | _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 | _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 | _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 | _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 | _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 | _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 | _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 | _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 | _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 | _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 | _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 | _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 | _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 | _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 | _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 | _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 | _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_57 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_57 | _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_57 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_156 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_160 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_160; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_163 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_163; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_166 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_166; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_169 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_169; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_172 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_172; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_175 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_175; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_178 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_178; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_181 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_181; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_184 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_184; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_187 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_187; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_190 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_190; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_193 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_193; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_196 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_196; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_199 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_199; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_202 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_202; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_205 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_205; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_208 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_208; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_211 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_211; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_214 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_214; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_217 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_217; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_220 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_220; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_223 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_223; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_226 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_226; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_229 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_229; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_232 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_232; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_235 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_235; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_238 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_238; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_241 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_241; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_244 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_244; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_247 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_247; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_250 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_250; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 | _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 | _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 | _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 | _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 | _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 | _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 | _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 | _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 | _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 | _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 | _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 | _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 | _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 | _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 | _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 | _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 | _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 | _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 | _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 | _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 | _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 | _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 | _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 | _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 | _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 | _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 | _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 | _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 | resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 | resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 | resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 | resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 | resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 | resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 | resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 | resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 | resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 | resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 | resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 | resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 | resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 | resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 | resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 | resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 | resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 | resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 | resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 | resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 | resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 | resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 | resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 | resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 | resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 | resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 | resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 | resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_252 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_270 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_acd_router_9ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_9 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect routers.auto.ingress_nodes_in, auto.routers_ingress_nodes_in connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLSplitACDxBENoC_acd_router_9ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [5:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_9 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (auto_routers_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (auto_routers_ingress_nodes_in_flit_valid), .auto_ingress_nodes_in_flit_bits_head (auto_routers_ingress_nodes_in_flit_bits_head), .auto_ingress_nodes_in_flit_bits_tail (auto_routers_ingress_nodes_in_flit_bits_tail), .auto_ingress_nodes_in_flit_bits_payload (auto_routers_ingress_nodes_in_flit_bits_payload), .auto_ingress_nodes_in_flit_bits_egress_id (auto_routers_ingress_nodes_in_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_157 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_157( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_273 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_51 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_51( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w43 : input clock : Clock input reset : Reset output io : { flip d : UInt<43>, q : UInt<43>, flip en : UInt<1>} reg cdc_reg : UInt<43>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg
module ClockCrossingReg_w43( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input [42:0] io_d, // @[SynchronizerReg.scala:195:14] output [42:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); reg [42:0] cdc_reg; // @[SynchronizerReg.scala:201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en) // @[SynchronizerReg.scala:195:14] cdc_reg <= io_d; // @[SynchronizerReg.scala:201:76] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_123 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_124 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_61( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_107 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_215 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_216 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_107( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable_1 : input clock : Clock input reset : Reset output io : { read_ports : { flip addr : UInt<6>, data : UInt<64>}[4], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<6>, data : UInt<64>}}[2]} cmem regfile : UInt<64> [52] wire read_data : UInt<64>[4] reg read_addrs_0 : UInt, clock connect read_addrs_0, io.read_ports[0].addr reg read_addrs_1 : UInt, clock connect read_addrs_1, io.read_ports[1].addr reg read_addrs_2 : UInt, clock connect read_addrs_2, io.read_ports[2].addr reg read_addrs_3 : UInt, clock connect read_addrs_3, io.read_ports[3].addr node _read_data_0_T = or(read_addrs_0, UInt<6>(0h0)) node _read_data_0_T_1 = bits(_read_data_0_T, 5, 0) infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock connect read_data[0], read_data_0_MPORT node _read_data_1_T = or(read_addrs_1, UInt<6>(0h0)) node _read_data_1_T_1 = bits(_read_data_1_T, 5, 0) infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock connect read_data[1], read_data_1_MPORT node _read_data_2_T = or(read_addrs_2, UInt<6>(0h0)) node _read_data_2_T_1 = bits(_read_data_2_T, 5, 0) infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock connect read_data[2], read_data_2_MPORT node _read_data_3_T = or(read_addrs_3, UInt<6>(0h0)) node _read_data_3_T_1 = bits(_read_data_3_T, 5, 0) infer mport read_data_3_MPORT = regfile[_read_data_3_T_1], clock connect read_data[3], read_data_3_MPORT node _bypass_ens_T = eq(io.write_ports[0].bits.addr, read_addrs_0) node bypass_ens_0 = and(io.write_ports[0].valid, _bypass_ens_T) node _bypass_ens_T_1 = eq(io.write_ports[1].bits.addr, read_addrs_0) node bypass_ens_1 = and(io.write_ports[1].valid, _bypass_ens_T_1) wire _bypass_data_WIRE : UInt<1>[2] connect _bypass_data_WIRE[0], bypass_ens_0 connect _bypass_data_WIRE[1], bypass_ens_1 wire _bypass_data_WIRE_1 : UInt<64>[2] connect _bypass_data_WIRE_1[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_1[1], io.write_ports[1].bits.data node _bypass_data_T = mux(_bypass_data_WIRE[0], _bypass_data_WIRE_1[0], UInt<1>(0h0)) node _bypass_data_T_1 = mux(_bypass_data_WIRE[1], _bypass_data_WIRE_1[1], UInt<1>(0h0)) node _bypass_data_T_2 = or(_bypass_data_T, _bypass_data_T_1) wire bypass_data : UInt<64> connect bypass_data, _bypass_data_T_2 node _io_read_ports_0_data_T = or(bypass_ens_0, bypass_ens_1) node _io_read_ports_0_data_T_1 = mux(_io_read_ports_0_data_T, bypass_data, read_data[0]) connect io.read_ports[0].data, _io_read_ports_0_data_T_1 node _bypass_ens_T_2 = eq(io.write_ports[0].bits.addr, read_addrs_1) node bypass_ens_0_1 = and(io.write_ports[0].valid, _bypass_ens_T_2) node _bypass_ens_T_3 = eq(io.write_ports[1].bits.addr, read_addrs_1) node bypass_ens_1_1 = and(io.write_ports[1].valid, _bypass_ens_T_3) wire _bypass_data_WIRE_2 : UInt<1>[2] connect _bypass_data_WIRE_2[0], bypass_ens_0_1 connect _bypass_data_WIRE_2[1], bypass_ens_1_1 wire _bypass_data_WIRE_3 : UInt<64>[2] connect _bypass_data_WIRE_3[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_3[1], io.write_ports[1].bits.data node _bypass_data_T_3 = mux(_bypass_data_WIRE_2[0], _bypass_data_WIRE_3[0], UInt<1>(0h0)) node _bypass_data_T_4 = mux(_bypass_data_WIRE_2[1], _bypass_data_WIRE_3[1], UInt<1>(0h0)) node _bypass_data_T_5 = or(_bypass_data_T_3, _bypass_data_T_4) wire bypass_data_1 : UInt<64> connect bypass_data_1, _bypass_data_T_5 node _io_read_ports_1_data_T = or(bypass_ens_0_1, bypass_ens_1_1) node _io_read_ports_1_data_T_1 = mux(_io_read_ports_1_data_T, bypass_data_1, read_data[1]) connect io.read_ports[1].data, _io_read_ports_1_data_T_1 node _bypass_ens_T_4 = eq(io.write_ports[0].bits.addr, read_addrs_2) node bypass_ens_0_2 = and(io.write_ports[0].valid, _bypass_ens_T_4) node _bypass_ens_T_5 = eq(io.write_ports[1].bits.addr, read_addrs_2) node bypass_ens_1_2 = and(io.write_ports[1].valid, _bypass_ens_T_5) wire _bypass_data_WIRE_4 : UInt<1>[2] connect _bypass_data_WIRE_4[0], bypass_ens_0_2 connect _bypass_data_WIRE_4[1], bypass_ens_1_2 wire _bypass_data_WIRE_5 : UInt<64>[2] connect _bypass_data_WIRE_5[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_5[1], io.write_ports[1].bits.data node _bypass_data_T_6 = mux(_bypass_data_WIRE_4[0], _bypass_data_WIRE_5[0], UInt<1>(0h0)) node _bypass_data_T_7 = mux(_bypass_data_WIRE_4[1], _bypass_data_WIRE_5[1], UInt<1>(0h0)) node _bypass_data_T_8 = or(_bypass_data_T_6, _bypass_data_T_7) wire bypass_data_2 : UInt<64> connect bypass_data_2, _bypass_data_T_8 node _io_read_ports_2_data_T = or(bypass_ens_0_2, bypass_ens_1_2) node _io_read_ports_2_data_T_1 = mux(_io_read_ports_2_data_T, bypass_data_2, read_data[2]) connect io.read_ports[2].data, _io_read_ports_2_data_T_1 node _bypass_ens_T_6 = eq(io.write_ports[0].bits.addr, read_addrs_3) node bypass_ens_0_3 = and(io.write_ports[0].valid, _bypass_ens_T_6) node _bypass_ens_T_7 = eq(io.write_ports[1].bits.addr, read_addrs_3) node bypass_ens_1_3 = and(io.write_ports[1].valid, _bypass_ens_T_7) wire _bypass_data_WIRE_6 : UInt<1>[2] connect _bypass_data_WIRE_6[0], bypass_ens_0_3 connect _bypass_data_WIRE_6[1], bypass_ens_1_3 wire _bypass_data_WIRE_7 : UInt<64>[2] connect _bypass_data_WIRE_7[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_7[1], io.write_ports[1].bits.data node _bypass_data_T_9 = mux(_bypass_data_WIRE_6[0], _bypass_data_WIRE_7[0], UInt<1>(0h0)) node _bypass_data_T_10 = mux(_bypass_data_WIRE_6[1], _bypass_data_WIRE_7[1], UInt<1>(0h0)) node _bypass_data_T_11 = or(_bypass_data_T_9, _bypass_data_T_10) wire bypass_data_3 : UInt<64> connect bypass_data_3, _bypass_data_T_11 node _io_read_ports_3_data_T = or(bypass_ens_0_3, bypass_ens_1_3) node _io_read_ports_3_data_T_1 = mux(_io_read_ports_3_data_T, bypass_data_3, read_data[3]) connect io.read_ports[3].data, _io_read_ports_3_data_T_1 when io.write_ports[0].valid : infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock connect MPORT, io.write_ports[0].bits.data when io.write_ports[1].valid : infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock connect MPORT_1, io.write_ports[1].bits.data node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0)) node _T_6 = or(_T_4, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert
module RegisterFileSynthesizable_1( // @[regfile.scala:106:7] input clock, // @[regfile.scala:106:7] input reset, // @[regfile.scala:106:7] input [5:0] io_read_ports_0_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_0_data, // @[regfile.scala:82:14] input [5:0] io_read_ports_1_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_1_data, // @[regfile.scala:82:14] input [5:0] io_read_ports_2_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_2_data, // @[regfile.scala:82:14] input [5:0] io_read_ports_3_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_3_data, // @[regfile.scala:82:14] input io_write_ports_0_valid, // @[regfile.scala:82:14] input [5:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14] input io_write_ports_1_valid, // @[regfile.scala:82:14] input [5:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_1_bits_data // @[regfile.scala:82:14] ); wire [5:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7] wire [5:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7] wire [5:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7] wire [5:0] io_read_ports_3_addr_0 = io_read_ports_3_addr; // @[regfile.scala:106:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7] wire [5:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7] wire [5:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7] wire [63:0] _io_read_ports_0_data_T_1; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_1_data_T_1; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_2_data_T_1; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_3_data_T_1; // @[regfile.scala:150:35] wire [63:0] _bypass_data_WIRE_1_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_1_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] io_read_ports_0_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_1_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_2_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_3_data_0; // @[regfile.scala:106:7] wire [63:0] read_data_0; // @[regfile.scala:122:23] wire [63:0] read_data_1; // @[regfile.scala:122:23] wire [63:0] read_data_2; // @[regfile.scala:122:23] wire [63:0] read_data_3; // @[regfile.scala:122:23] reg [5:0] read_addrs_0; // @[regfile.scala:125:50] wire [5:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28] reg [5:0] read_addrs_1; // @[regfile.scala:125:50] wire [5:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28] reg [5:0] read_addrs_2; // @[regfile.scala:125:50] wire [5:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28] reg [5:0] read_addrs_3; // @[regfile.scala:125:50] wire [5:0] _read_data_3_T = read_addrs_3; // @[regfile.scala:125:50, :128:28] wire [5:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28] wire [5:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28] wire [5:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28] wire [5:0] _read_data_3_T_1 = _read_data_3_T; // @[regfile.scala:128:28] wire _bypass_ens_T = io_write_ports_0_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0 = io_write_ports_0_valid_0 & _bypass_ens_T; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_0 = bypass_ens_0; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_1 = io_write_ports_1_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1 = io_write_ports_1_valid_0 & _bypass_ens_T_1; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_1 = bypass_ens_1; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T = _bypass_data_WIRE_0 ? _bypass_data_WIRE_1_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_1 = _bypass_data_WIRE_1 ? _bypass_data_WIRE_1_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_2 = _bypass_data_T | _bypass_data_T_1; // @[Mux.scala:30:73] wire [63:0] bypass_data = _bypass_data_T_2; // @[Mux.scala:30:73] wire _io_read_ports_0_data_T = bypass_ens_0 | bypass_ens_1; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_0_data_T_1 = _io_read_ports_0_data_T ? bypass_data : read_data_0; // @[Mux.scala:30:73] assign io_read_ports_0_data_0 = _io_read_ports_0_data_T_1; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_2 = io_write_ports_0_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_1 = io_write_ports_0_valid_0 & _bypass_ens_T_2; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_0 = bypass_ens_0_1; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_3 = io_write_ports_1_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_1 = io_write_ports_1_valid_0 & _bypass_ens_T_3; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_1 = bypass_ens_1_1; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_3 = _bypass_data_WIRE_2_0 ? _bypass_data_WIRE_3_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_4 = _bypass_data_WIRE_2_1 ? _bypass_data_WIRE_3_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_5 = _bypass_data_T_3 | _bypass_data_T_4; // @[Mux.scala:30:73] wire [63:0] bypass_data_1 = _bypass_data_T_5; // @[Mux.scala:30:73] wire _io_read_ports_1_data_T = bypass_ens_0_1 | bypass_ens_1_1; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_1_data_T_1 = _io_read_ports_1_data_T ? bypass_data_1 : read_data_1; // @[Mux.scala:30:73] assign io_read_ports_1_data_0 = _io_read_ports_1_data_T_1; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_4 = io_write_ports_0_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_2 = io_write_ports_0_valid_0 & _bypass_ens_T_4; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_0 = bypass_ens_0_2; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_5 = io_write_ports_1_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_2 = io_write_ports_1_valid_0 & _bypass_ens_T_5; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_1 = bypass_ens_1_2; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_6 = _bypass_data_WIRE_4_0 ? _bypass_data_WIRE_5_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_7 = _bypass_data_WIRE_4_1 ? _bypass_data_WIRE_5_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_8 = _bypass_data_T_6 | _bypass_data_T_7; // @[Mux.scala:30:73] wire [63:0] bypass_data_2 = _bypass_data_T_8; // @[Mux.scala:30:73] wire _io_read_ports_2_data_T = bypass_ens_0_2 | bypass_ens_1_2; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_2_data_T_1 = _io_read_ports_2_data_T ? bypass_data_2 : read_data_2; // @[Mux.scala:30:73] assign io_read_ports_2_data_0 = _io_read_ports_2_data_T_1; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_6 = io_write_ports_0_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_3 = io_write_ports_0_valid_0 & _bypass_ens_T_6; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_0 = bypass_ens_0_3; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_7 = io_write_ports_1_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_3 = io_write_ports_1_valid_0 & _bypass_ens_T_7; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_1 = bypass_ens_1_3; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_9 = _bypass_data_WIRE_6_0 ? _bypass_data_WIRE_7_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_10 = _bypass_data_WIRE_6_1 ? _bypass_data_WIRE_7_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_11 = _bypass_data_T_9 | _bypass_data_T_10; // @[Mux.scala:30:73] wire [63:0] bypass_data_3 = _bypass_data_T_11; // @[Mux.scala:30:73] wire _io_read_ports_3_data_T = bypass_ens_0_3 | bypass_ens_1_3; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_3_data_T_1 = _io_read_ports_3_data_T ? bypass_data_3 : read_data_3; // @[Mux.scala:30:73] assign io_read_ports_3_data_0 = _io_read_ports_3_data_T_1; // @[regfile.scala:106:7, :150:35]
Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF : input clock : Clock input reset : Reset output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<7>}[3], rrd_read_resps : UInt<65>[3], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<65>}}[2]} node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) node _T_4 = or(_T_2, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert connect io.arb_read_reqs[0].ready, UInt<1>(0h1) connect io.arb_read_reqs[1].ready, UInt<1>(0h1) connect io.arb_read_reqs[2].ready, UInt<1>(0h1) cmem regfile : UInt<65> [96] reg io_rrd_read_resps_0_REG : UInt, clock connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<7>(0h0)) node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 6, 0) infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT reg io_rrd_read_resps_1_REG : UInt, clock connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<7>(0h0)) node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 6, 0) infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT reg io_rrd_read_resps_2_REG : UInt, clock connect io_rrd_read_resps_2_REG, io.arb_read_reqs[2].bits node _io_rrd_read_resps_2_T = or(io_rrd_read_resps_2_REG, UInt<7>(0h0)) node _io_rrd_read_resps_2_T_1 = bits(_io_rrd_read_resps_2_T, 6, 0) infer mport io_rrd_read_resps_2_MPORT = regfile[_io_rrd_read_resps_2_T_1], clock connect io.rrd_read_resps[2], io_rrd_read_resps_2_MPORT when io.write_ports[0].valid : infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock connect MPORT, io.write_ports[0].bits.data when io.write_ports[1].valid : infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock connect MPORT_1, io.write_ports[1].bits.data
module FullyPortedRF( // @[regfile.scala:186:7] input clock, // @[regfile.scala:186:7] input reset, // @[regfile.scala:186:7] input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14] input [6:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14] input [6:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14] input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14] input [6:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14] output [64:0] io_rrd_read_resps_0, // @[regfile.scala:31:14] output [64:0] io_rrd_read_resps_1, // @[regfile.scala:31:14] output [64:0] io_rrd_read_resps_2, // @[regfile.scala:31:14] input io_write_ports_0_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14] input [64:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14] input io_write_ports_1_valid, // @[regfile.scala:31:14] input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14] input [64:0] io_write_ports_1_bits_data // @[regfile.scala:31:14] ); wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7] wire [6:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7] wire [6:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:186:7] wire [6:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:186:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7] wire [64:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:186:7] wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:186:7] wire [64:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:186:7] wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7] wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:186:7] wire [64:0] io_rrd_read_resps_0_0; // @[regfile.scala:186:7] wire [64:0] io_rrd_read_resps_1_0; // @[regfile.scala:186:7] wire [64:0] io_rrd_read_resps_2_0; // @[regfile.scala:186:7]
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_62 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[2] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_11 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] node _tile_async_resets_1_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[1], _tile_async_resets_1_T inst r_tile_resets_1 of AsyncResetRegVec_w1_i0_12 connect r_tile_resets_1.clock, clock connect r_tile_resets_1.reset, tile_async_resets[1] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[2] wire out_wivalid : UInt<1>[2] wire out_roready : UInt<1>[2] wire out_woready : UInt<1>[2] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 32, 32) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 32, 32) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 32, 32) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 32, 32) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 32, 32) connect r_tile_resets_1.io.en, out_f_woready_1 connect r_tile_resets_1.io.d, _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<32>(0h0)) node out_prepend = cat(r_tile_resets_1.io.q, _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<33>(0h0)) node _out_T_15 = bits(_out_T_14, 32, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<33>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_15 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_128 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_129 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33] wire tile_async_resets_1 = 1'h1; // @[TileResetSetter.scala:29:33] wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38] wire _tile_async_resets_1_T = 1'h1; // @[TileResetSetter.scala:31:38] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25] wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T = 32'h0; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire [32:0] _out_T_14 = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire [32:0] _out_T_15 = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire [32:0] _out_out_bits_data_WIRE_1_0 = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire [32:0] _out_out_bits_data_T_3 = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire [32:0] _out_out_bits_data_T_4 = 33'h0; // @[MuxLiteral.scala:49:{10,48}] wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25] wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_1 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_1 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire _out_romask_T_1 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_1 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_62 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i0_11 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] AsyncResetRegVec_w1_i0_12 r_tile_resets_1 ( // @[TileResetSetter.scala:33:15] .clock (clock), .io_d (_out_T_9), // @[RegisterRouter.scala:87:24] .io_en (out_f_woready_1) // @[RegisterRouter.scala:87:24] ); // @[TileResetSetter.scala:33:15] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<15>(0h4000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<15>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<15>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<15>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_16 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<15>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<15>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<15>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<15>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<15>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<15>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<15>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<15>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<15>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<15>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<15>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<15>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<15>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<15>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<15>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<15>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<15>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<15>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<15>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<15>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<15>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<15>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_17 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/example/GCD.scala:311:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<15>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<15>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [14:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [14:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_38 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<12>(0h800))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<16>(0h8000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_27, _T_32) node _T_74 = or(_T_73, _T_37) node _T_75 = or(_T_74, _T_42) node _T_76 = or(_T_75, _T_47) node _T_77 = or(_T_76, _T_52) node _T_78 = or(_T_77, _T_57) node _T_79 = or(_T_78, _T_62) node _T_80 = or(_T_79, _T_67) node _T_81 = or(_T_80, _T_72) node _T_82 = and(_T_22, _T_81) node _T_83 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<17>(0h10000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<29>(0h10000000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_84, _T_95) node _T_97 = or(UInt<1>(0h0), _T_82) node _T_98 = or(_T_97, _T_96) node _T_99 = and(_T_21, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_99, UInt<1>(0h1), "") : assert_2 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<12>(0h800))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<16>(0h8000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<27>(0h4000000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<13>(0h1000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_111, _T_116) node _T_168 = or(_T_167, _T_121) node _T_169 = or(_T_168, _T_126) node _T_170 = or(_T_169, _T_131) node _T_171 = or(_T_170, _T_136) node _T_172 = or(_T_171, _T_141) node _T_173 = or(_T_172, _T_146) node _T_174 = or(_T_173, _T_151) node _T_175 = or(_T_174, _T_156) node _T_176 = or(_T_175, _T_161) node _T_177 = or(_T_176, _T_166) node _T_178 = and(_T_106, _T_177) node _T_179 = or(UInt<1>(0h0), _T_178) node _T_180 = and(UInt<1>(0h0), _T_179) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_180, UInt<1>(0h1), "") : assert_3 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_187 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_187, UInt<1>(0h1), "") : assert_5 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(is_aligned, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_194 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_194, UInt<1>(0h1), "") : assert_7 node _T_198 = not(io.in.a.bits.mask) node _T_199 = eq(_T_198, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_199, UInt<1>(0h1), "") : assert_8 node _T_203 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_203, UInt<1>(0h1), "") : assert_9 node _T_207 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_207 : node _T_208 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_209 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_212 = and(_T_210, _T_211) node _T_213 = or(UInt<1>(0h0), _T_212) node _T_214 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<14>(0h2000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<13>(0h1000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<17>(0h10000))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<18>(0h2f000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<12>(0h800))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<16>(0h8000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<17>(0h10000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<13>(0h1000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<27>(0h4000000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = or(_T_219, _T_224) node _T_266 = or(_T_265, _T_229) node _T_267 = or(_T_266, _T_234) node _T_268 = or(_T_267, _T_239) node _T_269 = or(_T_268, _T_244) node _T_270 = or(_T_269, _T_249) node _T_271 = or(_T_270, _T_254) node _T_272 = or(_T_271, _T_259) node _T_273 = or(_T_272, _T_264) node _T_274 = and(_T_214, _T_273) node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<17>(0h10000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<29>(0h10000000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = and(_T_276, _T_287) node _T_289 = or(UInt<1>(0h0), _T_274) node _T_290 = or(_T_289, _T_288) node _T_291 = and(_T_213, _T_290) node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(_T_291, UInt<1>(0h0)) when _T_294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_291, UInt<1>(0h1), "") : assert_10 node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_300 = cvt(_T_299) node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000))) node _T_302 = asSInt(_T_301) node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0))) node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_305 = cvt(_T_304) node _T_306 = and(_T_305, asSInt(UInt<13>(0h1000))) node _T_307 = asSInt(_T_306) node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h10000))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<18>(0h2f000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<12>(0h800))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<16>(0h8000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<27>(0h4000000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<29>(0h10000000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_303, _T_308) node _T_360 = or(_T_359, _T_313) node _T_361 = or(_T_360, _T_318) node _T_362 = or(_T_361, _T_323) node _T_363 = or(_T_362, _T_328) node _T_364 = or(_T_363, _T_333) node _T_365 = or(_T_364, _T_338) node _T_366 = or(_T_365, _T_343) node _T_367 = or(_T_366, _T_348) node _T_368 = or(_T_367, _T_353) node _T_369 = or(_T_368, _T_358) node _T_370 = and(_T_298, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = and(UInt<1>(0h0), _T_371) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_372, UInt<1>(0h1), "") : assert_11 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_379 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_379, UInt<1>(0h1), "") : assert_13 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(is_aligned, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_386 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_386, UInt<1>(0h1), "") : assert_15 node _T_390 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_390, UInt<1>(0h1), "") : assert_16 node _T_394 = not(io.in.a.bits.mask) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_395, UInt<1>(0h1), "") : assert_17 node _T_399 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_399, UInt<1>(0h1), "") : assert_18 node _T_403 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_403 : node _T_404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_406 = and(_T_404, _T_405) node _T_407 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_408 = and(_T_406, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<12>(0h800))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<16>(0h8000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<13>(0h1000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<27>(0h4000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<29>(0h10000000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = or(_T_431, _T_436) node _T_483 = or(_T_482, _T_441) node _T_484 = or(_T_483, _T_446) node _T_485 = or(_T_484, _T_451) node _T_486 = or(_T_485, _T_456) node _T_487 = or(_T_486, _T_461) node _T_488 = or(_T_487, _T_466) node _T_489 = or(_T_488, _T_471) node _T_490 = or(_T_489, _T_476) node _T_491 = or(_T_490, _T_481) node _T_492 = and(_T_426, _T_491) node _T_493 = or(UInt<1>(0h0), _T_422) node _T_494 = or(_T_493, _T_492) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_494, UInt<1>(0h1), "") : assert_20 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(is_aligned, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_504 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_504, UInt<1>(0h1), "") : assert_23 node _T_508 = eq(io.in.a.bits.mask, mask) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_508, UInt<1>(0h1), "") : assert_24 node _T_512 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_512, UInt<1>(0h1), "") : assert_25 node _T_516 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_516 : node _T_517 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_518 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_519 = and(_T_517, _T_518) node _T_520 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_521 = and(_T_519, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_524 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_525 = and(_T_523, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<13>(0h1000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = and(_T_526, _T_531) node _T_533 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_534 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_535 = and(_T_533, _T_534) node _T_536 = or(UInt<1>(0h0), _T_535) node _T_537 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<14>(0h2000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<18>(0h2f000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<12>(0h800))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_553 = cvt(_T_552) node _T_554 = and(_T_553, asSInt(UInt<16>(0h8000))) node _T_555 = asSInt(_T_554) node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0))) node _T_557 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<13>(0h1000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<17>(0h10000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<27>(0h4000000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<13>(0h1000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<29>(0h10000000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = or(_T_541, _T_546) node _T_588 = or(_T_587, _T_551) node _T_589 = or(_T_588, _T_556) node _T_590 = or(_T_589, _T_561) node _T_591 = or(_T_590, _T_566) node _T_592 = or(_T_591, _T_571) node _T_593 = or(_T_592, _T_576) node _T_594 = or(_T_593, _T_581) node _T_595 = or(_T_594, _T_586) node _T_596 = and(_T_536, _T_595) node _T_597 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_598 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<17>(0h10000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = and(_T_597, _T_602) node _T_604 = or(UInt<1>(0h0), _T_532) node _T_605 = or(_T_604, _T_596) node _T_606 = or(_T_605, _T_603) node _T_607 = and(_T_522, _T_606) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_607, UInt<1>(0h1), "") : assert_26 node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(is_aligned, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_617 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_618 = asUInt(reset) node _T_619 = eq(_T_618, UInt<1>(0h0)) when _T_619 : node _T_620 = eq(_T_617, UInt<1>(0h0)) when _T_620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_617, UInt<1>(0h1), "") : assert_29 node _T_621 = eq(io.in.a.bits.mask, mask) node _T_622 = asUInt(reset) node _T_623 = eq(_T_622, UInt<1>(0h0)) when _T_623 : node _T_624 = eq(_T_621, UInt<1>(0h0)) when _T_624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_621, UInt<1>(0h1), "") : assert_30 node _T_625 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_625 : node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_628 = and(_T_626, _T_627) node _T_629 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_630 = and(_T_628, _T_629) node _T_631 = or(UInt<1>(0h0), _T_630) node _T_632 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_633 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_634 = and(_T_632, _T_633) node _T_635 = or(UInt<1>(0h0), _T_634) node _T_636 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_637 = cvt(_T_636) node _T_638 = and(_T_637, asSInt(UInt<13>(0h1000))) node _T_639 = asSInt(_T_638) node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0))) node _T_641 = and(_T_635, _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<14>(0h2000))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<18>(0h2f000))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_657 = cvt(_T_656) node _T_658 = and(_T_657, asSInt(UInt<12>(0h800))) node _T_659 = asSInt(_T_658) node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0))) node _T_661 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_662 = cvt(_T_661) node _T_663 = and(_T_662, asSInt(UInt<16>(0h8000))) node _T_664 = asSInt(_T_663) node _T_665 = eq(_T_664, asSInt(UInt<1>(0h0))) node _T_666 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_667 = cvt(_T_666) node _T_668 = and(_T_667, asSInt(UInt<17>(0h10000))) node _T_669 = asSInt(_T_668) node _T_670 = eq(_T_669, asSInt(UInt<1>(0h0))) node _T_671 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_672 = cvt(_T_671) node _T_673 = and(_T_672, asSInt(UInt<13>(0h1000))) node _T_674 = asSInt(_T_673) node _T_675 = eq(_T_674, asSInt(UInt<1>(0h0))) node _T_676 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_677 = cvt(_T_676) node _T_678 = and(_T_677, asSInt(UInt<17>(0h10000))) node _T_679 = asSInt(_T_678) node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0))) node _T_681 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_682 = cvt(_T_681) node _T_683 = and(_T_682, asSInt(UInt<27>(0h4000000))) node _T_684 = asSInt(_T_683) node _T_685 = eq(_T_684, asSInt(UInt<1>(0h0))) node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_692 = cvt(_T_691) node _T_693 = and(_T_692, asSInt(UInt<29>(0h10000000))) node _T_694 = asSInt(_T_693) node _T_695 = eq(_T_694, asSInt(UInt<1>(0h0))) node _T_696 = or(_T_650, _T_655) node _T_697 = or(_T_696, _T_660) node _T_698 = or(_T_697, _T_665) node _T_699 = or(_T_698, _T_670) node _T_700 = or(_T_699, _T_675) node _T_701 = or(_T_700, _T_680) node _T_702 = or(_T_701, _T_685) node _T_703 = or(_T_702, _T_690) node _T_704 = or(_T_703, _T_695) node _T_705 = and(_T_645, _T_704) node _T_706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = and(_T_706, _T_711) node _T_713 = or(UInt<1>(0h0), _T_641) node _T_714 = or(_T_713, _T_705) node _T_715 = or(_T_714, _T_712) node _T_716 = and(_T_631, _T_715) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_716, UInt<1>(0h1), "") : assert_31 node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(is_aligned, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_726 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_726, UInt<1>(0h1), "") : assert_34 node _T_730 = not(mask) node _T_731 = and(io.in.a.bits.mask, _T_730) node _T_732 = eq(_T_731, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_732, UInt<1>(0h1), "") : assert_35 node _T_736 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_736 : node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_741 = and(_T_739, _T_740) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_744 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _T_746 = or(UInt<1>(0h0), _T_745) node _T_747 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_748 = cvt(_T_747) node _T_749 = and(_T_748, asSInt(UInt<14>(0h2000))) node _T_750 = asSInt(_T_749) node _T_751 = eq(_T_750, asSInt(UInt<1>(0h0))) node _T_752 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_753 = cvt(_T_752) node _T_754 = and(_T_753, asSInt(UInt<13>(0h1000))) node _T_755 = asSInt(_T_754) node _T_756 = eq(_T_755, asSInt(UInt<1>(0h0))) node _T_757 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_758 = cvt(_T_757) node _T_759 = and(_T_758, asSInt(UInt<18>(0h2f000))) node _T_760 = asSInt(_T_759) node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0))) node _T_762 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_763 = cvt(_T_762) node _T_764 = and(_T_763, asSInt(UInt<12>(0h800))) node _T_765 = asSInt(_T_764) node _T_766 = eq(_T_765, asSInt(UInt<1>(0h0))) node _T_767 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_768 = cvt(_T_767) node _T_769 = and(_T_768, asSInt(UInt<16>(0h8000))) node _T_770 = asSInt(_T_769) node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0))) node _T_772 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_773 = cvt(_T_772) node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000))) node _T_775 = asSInt(_T_774) node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0))) node _T_777 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_778 = cvt(_T_777) node _T_779 = and(_T_778, asSInt(UInt<13>(0h1000))) node _T_780 = asSInt(_T_779) node _T_781 = eq(_T_780, asSInt(UInt<1>(0h0))) node _T_782 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_783 = cvt(_T_782) node _T_784 = and(_T_783, asSInt(UInt<17>(0h10000))) node _T_785 = asSInt(_T_784) node _T_786 = eq(_T_785, asSInt(UInt<1>(0h0))) node _T_787 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_788 = cvt(_T_787) node _T_789 = and(_T_788, asSInt(UInt<27>(0h4000000))) node _T_790 = asSInt(_T_789) node _T_791 = eq(_T_790, asSInt(UInt<1>(0h0))) node _T_792 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_793 = cvt(_T_792) node _T_794 = and(_T_793, asSInt(UInt<13>(0h1000))) node _T_795 = asSInt(_T_794) node _T_796 = eq(_T_795, asSInt(UInt<1>(0h0))) node _T_797 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<29>(0h10000000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = or(_T_751, _T_756) node _T_803 = or(_T_802, _T_761) node _T_804 = or(_T_803, _T_766) node _T_805 = or(_T_804, _T_771) node _T_806 = or(_T_805, _T_776) node _T_807 = or(_T_806, _T_781) node _T_808 = or(_T_807, _T_786) node _T_809 = or(_T_808, _T_791) node _T_810 = or(_T_809, _T_796) node _T_811 = or(_T_810, _T_801) node _T_812 = and(_T_746, _T_811) node _T_813 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_815 = cvt(_T_814) node _T_816 = and(_T_815, asSInt(UInt<17>(0h10000))) node _T_817 = asSInt(_T_816) node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0))) node _T_819 = and(_T_813, _T_818) node _T_820 = or(UInt<1>(0h0), _T_812) node _T_821 = or(_T_820, _T_819) node _T_822 = and(_T_742, _T_821) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_822, UInt<1>(0h1), "") : assert_36 node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(is_aligned, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_832, UInt<1>(0h1), "") : assert_39 node _T_836 = eq(io.in.a.bits.mask, mask) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_836, UInt<1>(0h1), "") : assert_40 node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_840 : node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_849 = and(_T_847, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<14>(0h2000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<13>(0h1000))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<18>(0h2f000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<12>(0h800))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<16>(0h8000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<17>(0h10000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<13>(0h1000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h10000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<29>(0h10000000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = or(_T_855, _T_860) node _T_907 = or(_T_906, _T_865) node _T_908 = or(_T_907, _T_870) node _T_909 = or(_T_908, _T_875) node _T_910 = or(_T_909, _T_880) node _T_911 = or(_T_910, _T_885) node _T_912 = or(_T_911, _T_890) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_900) node _T_915 = or(_T_914, _T_905) node _T_916 = and(_T_850, _T_915) node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = and(_T_917, _T_922) node _T_924 = or(UInt<1>(0h0), _T_916) node _T_925 = or(_T_924, _T_923) node _T_926 = and(_T_846, _T_925) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_926, UInt<1>(0h1), "") : assert_41 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_936 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_936, UInt<1>(0h1), "") : assert_44 node _T_940 = eq(io.in.a.bits.mask, mask) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_940, UInt<1>(0h1), "") : assert_45 node _T_944 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) node _T_950 = or(UInt<1>(0h0), _T_949) node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_953 = and(_T_951, _T_952) node _T_954 = or(UInt<1>(0h0), _T_953) node _T_955 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_956 = cvt(_T_955) node _T_957 = and(_T_956, asSInt(UInt<13>(0h1000))) node _T_958 = asSInt(_T_957) node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0))) node _T_960 = and(_T_954, _T_959) node _T_961 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_962 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<14>(0h2000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<17>(0h10000))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<18>(0h2f000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<22>(0h200000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<12>(0h800))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<22>(0h300000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<16>(0h8000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<17>(0h10000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<27>(0h4000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = or(_T_966, _T_971) node _T_1008 = or(_T_1007, _T_976) node _T_1009 = or(_T_1008, _T_981) node _T_1010 = or(_T_1009, _T_986) node _T_1011 = or(_T_1010, _T_991) node _T_1012 = or(_T_1011, _T_996) node _T_1013 = or(_T_1012, _T_1001) node _T_1014 = or(_T_1013, _T_1006) node _T_1015 = and(_T_961, _T_1014) node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1017 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<17>(0h10000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<29>(0h10000000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_1024, _T_1029) node _T_1031 = and(_T_1019, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_960) node _T_1033 = or(_T_1032, _T_1015) node _T_1034 = or(_T_1033, _T_1031) node _T_1035 = and(_T_950, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_46 node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(is_aligned, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1045 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_49 node _T_1049 = eq(io.in.a.bits.mask, mask) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_50 node _T_1053 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1057 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1061 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1061 : node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1065 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_54 node _T_1069 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_55 node _T_1073 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_56 node _T_1077 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_57 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_60 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_61 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_62 node _T_1100 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_63 node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1105 = or(UInt<1>(0h1), _T_1104) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_64 node _T_1109 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1109 : node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(sink_ok, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1116 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_67 node _T_1120 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_68 node _T_1124 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_69 node _T_1128 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1129 = or(_T_1128, io.in.d.bits.corrupt) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_70 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_71 node _T_1138 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1138 : node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_73 node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_74 node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1151 = or(UInt<1>(0h1), _T_1150) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_75 node _T_1155 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1155 : node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1159 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_77 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(_T_1163, io.in.d.bits.corrupt) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_78 node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1169 = or(UInt<1>(0h1), _T_1168) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_79 node _T_1173 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1173 : node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1177 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_81 node _T_1181 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_82 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1190 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1194 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1198 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1202 = eq(a_first, UInt<1>(0h0)) node _T_1203 = and(io.in.a.valid, _T_1202) when _T_1203 : node _T_1204 = eq(io.in.a.bits.opcode, opcode) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_87 node _T_1208 = eq(io.in.a.bits.param, param) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_88 node _T_1212 = eq(io.in.a.bits.size, size) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_89 node _T_1216 = eq(io.in.a.bits.source, source) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.a.bits.address, address) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = and(io.in.a.ready, io.in.a.valid) node _T_1225 = and(_T_1224, a_first) when _T_1225 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1226 = eq(d_first, UInt<1>(0h0)) node _T_1227 = and(io.in.d.valid, _T_1226) when _T_1227 : node _T_1228 = eq(io.in.d.bits.opcode, opcode_1) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_92 node _T_1232 = eq(io.in.d.bits.param, param_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_93 node _T_1236 = eq(io.in.d.bits.size, size_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_94 node _T_1240 = eq(io.in.d.bits.source, source_1) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_95 node _T_1244 = eq(io.in.d.bits.sink, sink) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_96 node _T_1248 = eq(io.in.d.bits.denied, denied) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_97 node _T_1252 = and(io.in.d.ready, io.in.d.valid) node _T_1253 = and(_T_1252, d_first) when _T_1253 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1254 = and(io.in.a.valid, a_first_1) node _T_1255 = and(_T_1254, UInt<1>(0h1)) when _T_1255 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1256 = and(io.in.a.ready, io.in.a.valid) node _T_1257 = and(_T_1256, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1259 = dshr(inflight, io.in.a.bits.source) node _T_1260 = bits(_T_1259, 0, 0) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1265 = and(io.in.d.valid, d_first_1) node _T_1266 = and(_T_1265, UInt<1>(0h1)) node _T_1267 = eq(d_release_ack, UInt<1>(0h0)) node _T_1268 = and(_T_1266, _T_1267) when _T_1268 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1269 = and(io.in.d.ready, io.in.d.valid) node _T_1270 = and(_T_1269, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1274 = and(io.in.d.valid, d_first_1) node _T_1275 = and(_T_1274, UInt<1>(0h1)) node _T_1276 = eq(d_release_ack, UInt<1>(0h0)) node _T_1277 = and(_T_1275, _T_1276) when _T_1277 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1278 = dshr(inflight, io.in.d.bits.source) node _T_1279 = bits(_T_1278, 0, 0) node _T_1280 = or(_T_1279, same_cycle_resp) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1284 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1285 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1286 = or(_T_1284, _T_1285) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_100 node _T_1290 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_101 else : node _T_1294 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1295 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1296 = or(_T_1294, _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_102 node _T_1300 = eq(io.in.d.bits.size, a_size_lookup) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_103 node _T_1304 = and(io.in.d.valid, d_first_1) node _T_1305 = and(_T_1304, a_first_1) node _T_1306 = and(_T_1305, io.in.a.valid) node _T_1307 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(d_release_ack, UInt<1>(0h0)) node _T_1310 = and(_T_1308, _T_1309) when _T_1310 : node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1312 = or(_T_1311, io.in.a.ready) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_104 node _T_1316 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1317 = orr(a_set_wo_ready) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = or(_T_1316, _T_1318) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_76 node _T_1323 = orr(inflight) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) node _T_1325 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1326 = or(_T_1324, _T_1325) node _T_1327 = lt(watchdog, plusarg_reader.out) node _T_1328 = or(_T_1326, _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1332 = and(io.in.a.ready, io.in.a.valid) node _T_1333 = and(io.in.d.ready, io.in.d.valid) node _T_1334 = or(_T_1332, _T_1333) when _T_1334 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1335 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1336 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1337 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1338 = and(_T_1336, _T_1337) node _T_1339 = and(_T_1335, _T_1338) when _T_1339 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1340 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1341 = and(_T_1340, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1342 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1343 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = and(_T_1341, _T_1344) when _T_1345 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1346 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1347 = bits(_T_1346, 0, 0) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1352 = and(io.in.d.valid, d_first_2) node _T_1353 = and(_T_1352, UInt<1>(0h1)) node _T_1354 = and(_T_1353, d_release_ack_1) when _T_1354 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1355 = and(io.in.d.ready, io.in.d.valid) node _T_1356 = and(_T_1355, d_first_2) node _T_1357 = and(_T_1356, UInt<1>(0h1)) node _T_1358 = and(_T_1357, d_release_ack_1) when _T_1358 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1359 = and(io.in.d.valid, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1362 = dshr(inflight_1, io.in.d.bits.source) node _T_1363 = bits(_T_1362, 0, 0) node _T_1364 = or(_T_1363, same_cycle_resp_1) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1368 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_109 else : node _T_1372 = eq(io.in.d.bits.size, c_size_lookup) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_110 node _T_1376 = and(io.in.d.valid, d_first_2) node _T_1377 = and(_T_1376, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1378 = and(_T_1377, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1379 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1380 = and(_T_1378, _T_1379) node _T_1381 = and(_T_1380, d_release_ack_1) node _T_1382 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1383 = and(_T_1381, _T_1382) when _T_1383 : node _T_1384 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1385 = or(_T_1384, _WIRE_23.ready) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_111 node _T_1389 = orr(c_set_wo_ready) when _T_1389 : node _T_1390 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_77 node _T_1394 = orr(inflight_1) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) node _T_1396 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1397 = or(_T_1395, _T_1396) node _T_1398 = lt(watchdog_1, plusarg_reader_1.out) node _T_1399 = or(_T_1397, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1403 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1404 = and(io.in.d.ready, io.in.d.valid) node _T_1405 = or(_T_1403, _T_1404) when _T_1405 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_78 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_79 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_38( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1332 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1332; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1332; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1405 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1405; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1405; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1405; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1255 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1255; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1255; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1332 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1304 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1304 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1405 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1376 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1376 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1405 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_189 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_189( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_345 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_22 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_221 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_222 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_22( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_221 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_222 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_23 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61
module PMAChecker_23( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a17d64s8k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)
module Repeater_TLBundleA_a17d64s8k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [16:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [16:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); reg full; // @[Repeater.scala:20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [7:0] saved_source; // @[Repeater.scala:21:18] reg [16:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] wire io_deq_valid_0 = io_enq_valid | full; // @[Repeater.scala:20:21, :24:32] wire io_enq_ready_0 = io_deq_ready & ~full; // @[Repeater.scala:20:21, :25:{32,35}] wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full); // @[Decoupled.scala:51:35] if (_GEN) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala:21:18] saved_param <= io_enq_bits_param; // @[Repeater.scala:21:18] saved_size <= io_enq_bits_size; // @[Repeater.scala:21:18] saved_source <= io_enq_bits_source; // @[Repeater.scala:21:18] saved_address <= io_enq_bits_address; // @[Repeater.scala:21:18] saved_mask <= io_enq_bits_mask; // @[Repeater.scala:21:18] saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala:21:18] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MSHR_4 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<4>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<4>, clock reg probes_toN : UInt<4>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<7>(0h44)) node _req_clientBit_T_1 = eq(request.source, UInt<7>(0h40)) node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0) node _req_clientBit_T_2 = shr(request.source, 3) node _req_clientBit_T_3 = eq(_req_clientBit_T_2, UInt<3>(0h6)) node _req_clientBit_T_4 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_T_6 = leq(req_clientBit_uncommonBits, UInt<3>(0h4)) node _req_clientBit_T_7 = and(_req_clientBit_T_5, _req_clientBit_T_6) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<3>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 2, 0) node _req_clientBit_T_8 = shr(request.source, 3) node _req_clientBit_T_9 = eq(_req_clientBit_T_8, UInt<3>(0h4)) node _req_clientBit_T_10 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node _req_clientBit_T_12 = leq(req_clientBit_uncommonBits_1, UInt<3>(0h4)) node _req_clientBit_T_13 = and(_req_clientBit_T_11, _req_clientBit_T_12) node req_clientBit_lo = cat(_req_clientBit_T_1, _req_clientBit_T) node req_clientBit_hi = cat(_req_clientBit_T_13, _req_clientBit_T_7) node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<7>(0h44)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<7>(0h40)) node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0) node _probe_bit_T_2 = shr(io.sinkc.bits.source, 3) node _probe_bit_T_3 = eq(_probe_bit_T_2, UInt<3>(0h6)) node _probe_bit_T_4 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_T_6 = leq(probe_bit_uncommonBits, UInt<3>(0h4)) node _probe_bit_T_7 = and(_probe_bit_T_5, _probe_bit_T_6) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<3>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 2, 0) node _probe_bit_T_8 = shr(io.sinkc.bits.source, 3) node _probe_bit_T_9 = eq(_probe_bit_T_8, UInt<3>(0h4)) node _probe_bit_T_10 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node _probe_bit_T_12 = leq(probe_bit_uncommonBits_1, UInt<3>(0h4)) node _probe_bit_T_13 = and(_probe_bit_T_11, _probe_bit_T_12) node probe_bit_lo = cat(_probe_bit_T_1, _probe_bit_T) node probe_bit_hi = cat(_probe_bit_T_13, _probe_bit_T_7) node probe_bit = cat(probe_bit_hi, probe_bit_lo) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<7>(0h44)) node _new_clientBit_T_1 = eq(new_request.source, UInt<7>(0h40)) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0) node _new_clientBit_T_2 = shr(new_request.source, 3) node _new_clientBit_T_3 = eq(_new_clientBit_T_2, UInt<3>(0h6)) node _new_clientBit_T_4 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_T_6 = leq(new_clientBit_uncommonBits, UInt<3>(0h4)) node _new_clientBit_T_7 = and(_new_clientBit_T_5, _new_clientBit_T_6) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<3>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 2, 0) node _new_clientBit_T_8 = shr(new_request.source, 3) node _new_clientBit_T_9 = eq(_new_clientBit_T_8, UInt<3>(0h4)) node _new_clientBit_T_10 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node _new_clientBit_T_12 = leq(new_clientBit_uncommonBits_1, UInt<3>(0h4)) node _new_clientBit_T_13 = and(_new_clientBit_T_11, _new_clientBit_T_12) node new_clientBit_lo = cat(_new_clientBit_T_1, _new_clientBit_T) node new_clientBit_hi = cat(_new_clientBit_T_13, _new_clientBit_T_7) node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [3:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [3:0] invalid_clients = 4'h0; // @[MSHR.scala:268:21] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [3:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [3:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [6:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [6:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [3:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [3:0] probes_done; // @[MSHR.scala:150:24] reg [3:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [3:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 7'h44; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T_2 = request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_8 = request_source[6:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_3 = _req_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_5 = _req_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_6 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_7 = _req_clientBit_T_5 & _req_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_9 = _req_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_11 = _req_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_12 = req_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_13 = _req_clientBit_T_11 & _req_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi = {_req_clientBit_T_13, _req_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [3:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [3:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [3:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [3:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [3:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [3:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 4'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [3:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 4'h0; // @[Parameters.scala:201:10] wire [3:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [3:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [3:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 4'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [3:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [3:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [3:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 4'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 7'h44; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T_2 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_8 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_3 = _probe_bit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_5 = _probe_bit_T_3; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_6 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_7 = _probe_bit_T_5 & _probe_bit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_9 = _probe_bit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_11 = _probe_bit_T_9; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_12 = probe_bit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_13 = _probe_bit_T_11 & _probe_bit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi = {_probe_bit_T_13, _probe_bit_T_7}; // @[Parameters.scala:56:48] wire [3:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [3:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [3:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [3:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [3:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [3:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _probes_toN_T = probe_toN ? probe_bit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [6:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 7'h44; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T_2 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_8 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_3 = _new_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_5 = _new_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_6 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_7 = _new_clientBit_T_5 & _new_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_9 = _new_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_11 = _new_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_12 = new_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_13 = _new_clientBit_T_11 & _new_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi = {_new_clientBit_T_13, _new_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [3:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 4'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module MulDiv_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, full_data : UInt<128>, tag : UInt<5>}}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) reg req : { fn : UInt<5>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock reg count : UInt<7>, clock reg neg_out : UInt<1>, clock reg isHi : UInt<1>, clock reg resHi : UInt<1>, clock reg divisor : UInt<65>, clock reg remainder : UInt<130>, clock wire decoded_plaInput : UInt<3> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_3_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_4_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 2, 2) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_1_2 = andr(decoded_andMatrixOutputs_andMatrixInput_0_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput, 2, 2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, io.req.bits.fn node _T = bits(decoded, 3, 3) node _T_1 = bits(decoded, 2, 2) node _T_2 = bits(decoded, 1, 1) node _T_3 = bits(decoded, 0, 0) node cmdMul = bits(_T, 0, 0) node cmdHi = bits(_T_1, 0, 0) node lhsSigned = bits(_T_2, 0, 0) node rhsSigned = bits(_T_3, 0, 0) node _T_4 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_5 = and(UInt<1>(0h1), _T_4) node _sign_T = bits(io.req.bits.in1, 31, 31) node _sign_T_1 = bits(io.req.bits.in1, 63, 63) node _sign_T_2 = mux(_T_5, _sign_T, _sign_T_1) node lhs_sign = and(lhsSigned, _sign_T_2) node _hi_T = mux(lhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_1 = bits(io.req.bits.in1, 63, 32) node hi = mux(_T_5, _hi_T, _hi_T_1) node _T_6 = bits(io.req.bits.in1, 31, 0) node lhs_in = cat(hi, _T_6) node _T_7 = eq(io.req.bits.dw, UInt<1>(0h0)) node _T_8 = and(UInt<1>(0h1), _T_7) node _sign_T_3 = bits(io.req.bits.in2, 31, 31) node _sign_T_4 = bits(io.req.bits.in2, 63, 63) node _sign_T_5 = mux(_T_8, _sign_T_3, _sign_T_4) node rhs_sign = and(rhsSigned, _sign_T_5) node _hi_T_2 = mux(rhs_sign, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hi_T_3 = bits(io.req.bits.in2, 63, 32) node hi_1 = mux(_T_8, _hi_T_2, _hi_T_3) node _T_9 = bits(io.req.bits.in2, 31, 0) node rhs_in = cat(hi_1, _T_9) node _subtractor_T = bits(remainder, 128, 64) node _subtractor_T_1 = sub(_subtractor_T, divisor) node subtractor = tail(_subtractor_T_1, 1) node _result_T = bits(remainder, 128, 65) node _result_T_1 = bits(remainder, 63, 0) node result = mux(resHi, _result_T, _result_T_1) node _negated_remainder_T = sub(UInt<1>(0h0), result) node negated_remainder = tail(_negated_remainder_T, 1) node _T_10 = eq(state, UInt<3>(0h1)) when _T_10 : node _T_11 = bits(remainder, 63, 63) when _T_11 : connect remainder, negated_remainder node _T_12 = bits(divisor, 63, 63) when _T_12 : connect divisor, subtractor connect state, UInt<3>(0h3) node _T_13 = eq(state, UInt<3>(0h5)) when _T_13 : connect remainder, negated_remainder connect state, UInt<3>(0h7) connect resHi, UInt<1>(0h0) node _T_14 = eq(state, UInt<3>(0h2)) when _T_14 : node _mulReg_T = bits(remainder, 129, 65) node _mulReg_T_1 = bits(remainder, 63, 0) node mulReg = cat(_mulReg_T, _mulReg_T_1) node mplierSign = bits(remainder, 64, 64) node mplier = bits(mulReg, 63, 0) node _accum_T = bits(mulReg, 128, 64) node accum = asSInt(_accum_T) node mpcand = asSInt(divisor) node _prod_T = bits(mplier, 7, 0) node _prod_T_1 = cat(mplierSign, _prod_T) node _prod_T_2 = asSInt(_prod_T_1) node _prod_T_3 = mul(_prod_T_2, mpcand) node _prod_T_4 = add(_prod_T_3, accum) node _prod_T_5 = tail(_prod_T_4, 1) node prod = asSInt(_prod_T_5) node _nextMulReg_T = bits(mplier, 63, 8) node nextMulReg_hi = asUInt(prod) node nextMulReg = cat(nextMulReg_hi, _nextMulReg_T) node _nextMplierSign_T = eq(count, UInt<3>(0h6)) node nextMplierSign = and(_nextMplierSign_T, neg_out) node _eOutMask_T = mul(count, UInt<4>(0h8)) node _eOutMask_T_1 = bits(_eOutMask_T, 5, 0) node _eOutMask_T_2 = dshr(asSInt(UInt<65>(0h10000000000000000)), _eOutMask_T_1) node eOutMask = bits(_eOutMask_T_2, 63, 0) node _eOut_T = neq(count, UInt<3>(0h7)) node _eOut_T_1 = and(UInt<1>(0h1), _eOut_T) node _eOut_T_2 = neq(count, UInt<1>(0h0)) node _eOut_T_3 = and(_eOut_T_1, _eOut_T_2) node _eOut_T_4 = eq(isHi, UInt<1>(0h0)) node _eOut_T_5 = and(_eOut_T_3, _eOut_T_4) node _eOut_T_6 = not(eOutMask) node _eOut_T_7 = and(mplier, _eOut_T_6) node _eOut_T_8 = eq(_eOut_T_7, UInt<1>(0h0)) node eOut = and(_eOut_T_5, _eOut_T_8) node _eOutRes_T = mul(count, UInt<4>(0h8)) node _eOutRes_T_1 = sub(UInt<7>(0h40), _eOutRes_T) node _eOutRes_T_2 = tail(_eOutRes_T_1, 1) node _eOutRes_T_3 = bits(_eOutRes_T_2, 5, 0) node eOutRes = dshr(mulReg, _eOutRes_T_3) node _nextMulReg1_T = bits(nextMulReg, 128, 64) node _nextMulReg1_T_1 = mux(eOut, eOutRes, nextMulReg) node _nextMulReg1_T_2 = bits(_nextMulReg1_T_1, 63, 0) node nextMulReg1 = cat(_nextMulReg1_T, _nextMulReg1_T_2) node _remainder_T = shr(nextMulReg1, 64) node _remainder_T_1 = bits(nextMulReg1, 63, 0) node remainder_hi = cat(_remainder_T, nextMplierSign) node _remainder_T_2 = cat(remainder_hi, _remainder_T_1) connect remainder, _remainder_T_2 node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 node _T_15 = eq(count, UInt<3>(0h7)) node _T_16 = or(eOut, _T_15) when _T_16 : connect state, UInt<3>(0h6) connect resHi, isHi node _T_17 = eq(state, UInt<3>(0h3)) when _T_17 : node unrolls_less = bits(subtractor, 64, 64) node _unrolls_T = bits(remainder, 127, 64) node _unrolls_T_1 = bits(subtractor, 63, 0) node _unrolls_T_2 = mux(unrolls_less, _unrolls_T, _unrolls_T_1) node _unrolls_T_3 = bits(remainder, 63, 0) node _unrolls_T_4 = eq(unrolls_less, UInt<1>(0h0)) node unrolls_hi = cat(_unrolls_T_2, _unrolls_T_3) node unrolls_0 = cat(unrolls_hi, _unrolls_T_4) connect remainder, unrolls_0 node _T_18 = eq(count, UInt<7>(0h40)) when _T_18 : node _state_T = mux(neg_out, UInt<3>(0h5), UInt<3>(0h7)) connect state, _state_T connect resHi, isHi node _count_T_2 = add(count, UInt<1>(0h1)) node _count_T_3 = tail(_count_T_2, 1) connect count, _count_T_3 node _divby0_T = eq(count, UInt<1>(0h0)) node _divby0_T_1 = bits(subtractor, 64, 64) node _divby0_T_2 = eq(_divby0_T_1, UInt<1>(0h0)) node divby0 = and(_divby0_T, _divby0_T_2) node alignMask = not(UInt<6>(0h0)) node _divisorMSB_T = bits(divisor, 63, 0) node divisorMSB_hi = bits(_divisorMSB_T, 63, 32) node divisorMSB_lo = bits(_divisorMSB_T, 31, 0) node divisorMSB_useHi = orr(divisorMSB_hi) node divisorMSB_hi_1 = bits(divisorMSB_hi, 31, 16) node divisorMSB_lo_1 = bits(divisorMSB_hi, 15, 0) node divisorMSB_useHi_1 = orr(divisorMSB_hi_1) node divisorMSB_hi_2 = bits(divisorMSB_hi_1, 15, 8) node divisorMSB_lo_2 = bits(divisorMSB_hi_1, 7, 0) node divisorMSB_useHi_2 = orr(divisorMSB_hi_2) node divisorMSB_hi_3 = bits(divisorMSB_hi_2, 7, 4) node divisorMSB_lo_3 = bits(divisorMSB_hi_2, 3, 0) node divisorMSB_useHi_3 = orr(divisorMSB_hi_3) node _divisorMSB_T_1 = bits(divisorMSB_hi_3, 3, 3) node _divisorMSB_T_2 = bits(divisorMSB_hi_3, 2, 2) node _divisorMSB_T_3 = bits(divisorMSB_hi_3, 1, 1) node _divisorMSB_T_4 = mux(_divisorMSB_T_2, UInt<2>(0h2), _divisorMSB_T_3) node _divisorMSB_T_5 = mux(_divisorMSB_T_1, UInt<2>(0h3), _divisorMSB_T_4) node _divisorMSB_T_6 = bits(divisorMSB_lo_3, 3, 3) node _divisorMSB_T_7 = bits(divisorMSB_lo_3, 2, 2) node _divisorMSB_T_8 = bits(divisorMSB_lo_3, 1, 1) node _divisorMSB_T_9 = mux(_divisorMSB_T_7, UInt<2>(0h2), _divisorMSB_T_8) node _divisorMSB_T_10 = mux(_divisorMSB_T_6, UInt<2>(0h3), _divisorMSB_T_9) node _divisorMSB_T_11 = mux(divisorMSB_useHi_3, _divisorMSB_T_5, _divisorMSB_T_10) node _divisorMSB_T_12 = cat(divisorMSB_useHi_3, _divisorMSB_T_11) node divisorMSB_hi_4 = bits(divisorMSB_lo_2, 7, 4) node divisorMSB_lo_4 = bits(divisorMSB_lo_2, 3, 0) node divisorMSB_useHi_4 = orr(divisorMSB_hi_4) node _divisorMSB_T_13 = bits(divisorMSB_hi_4, 3, 3) node _divisorMSB_T_14 = bits(divisorMSB_hi_4, 2, 2) node _divisorMSB_T_15 = bits(divisorMSB_hi_4, 1, 1) node _divisorMSB_T_16 = mux(_divisorMSB_T_14, UInt<2>(0h2), _divisorMSB_T_15) node _divisorMSB_T_17 = mux(_divisorMSB_T_13, UInt<2>(0h3), _divisorMSB_T_16) node _divisorMSB_T_18 = bits(divisorMSB_lo_4, 3, 3) node _divisorMSB_T_19 = bits(divisorMSB_lo_4, 2, 2) node _divisorMSB_T_20 = bits(divisorMSB_lo_4, 1, 1) node _divisorMSB_T_21 = mux(_divisorMSB_T_19, UInt<2>(0h2), _divisorMSB_T_20) node _divisorMSB_T_22 = mux(_divisorMSB_T_18, UInt<2>(0h3), _divisorMSB_T_21) node _divisorMSB_T_23 = mux(divisorMSB_useHi_4, _divisorMSB_T_17, _divisorMSB_T_22) node _divisorMSB_T_24 = cat(divisorMSB_useHi_4, _divisorMSB_T_23) node _divisorMSB_T_25 = mux(divisorMSB_useHi_2, _divisorMSB_T_12, _divisorMSB_T_24) node _divisorMSB_T_26 = cat(divisorMSB_useHi_2, _divisorMSB_T_25) node divisorMSB_hi_5 = bits(divisorMSB_lo_1, 15, 8) node divisorMSB_lo_5 = bits(divisorMSB_lo_1, 7, 0) node divisorMSB_useHi_5 = orr(divisorMSB_hi_5) node divisorMSB_hi_6 = bits(divisorMSB_hi_5, 7, 4) node divisorMSB_lo_6 = bits(divisorMSB_hi_5, 3, 0) node divisorMSB_useHi_6 = orr(divisorMSB_hi_6) node _divisorMSB_T_27 = bits(divisorMSB_hi_6, 3, 3) node _divisorMSB_T_28 = bits(divisorMSB_hi_6, 2, 2) node _divisorMSB_T_29 = bits(divisorMSB_hi_6, 1, 1) node _divisorMSB_T_30 = mux(_divisorMSB_T_28, UInt<2>(0h2), _divisorMSB_T_29) node _divisorMSB_T_31 = mux(_divisorMSB_T_27, UInt<2>(0h3), _divisorMSB_T_30) node _divisorMSB_T_32 = bits(divisorMSB_lo_6, 3, 3) node _divisorMSB_T_33 = bits(divisorMSB_lo_6, 2, 2) node _divisorMSB_T_34 = bits(divisorMSB_lo_6, 1, 1) node _divisorMSB_T_35 = mux(_divisorMSB_T_33, UInt<2>(0h2), _divisorMSB_T_34) node _divisorMSB_T_36 = mux(_divisorMSB_T_32, UInt<2>(0h3), _divisorMSB_T_35) node _divisorMSB_T_37 = mux(divisorMSB_useHi_6, _divisorMSB_T_31, _divisorMSB_T_36) node _divisorMSB_T_38 = cat(divisorMSB_useHi_6, _divisorMSB_T_37) node divisorMSB_hi_7 = bits(divisorMSB_lo_5, 7, 4) node divisorMSB_lo_7 = bits(divisorMSB_lo_5, 3, 0) node divisorMSB_useHi_7 = orr(divisorMSB_hi_7) node _divisorMSB_T_39 = bits(divisorMSB_hi_7, 3, 3) node _divisorMSB_T_40 = bits(divisorMSB_hi_7, 2, 2) node _divisorMSB_T_41 = bits(divisorMSB_hi_7, 1, 1) node _divisorMSB_T_42 = mux(_divisorMSB_T_40, UInt<2>(0h2), _divisorMSB_T_41) node _divisorMSB_T_43 = mux(_divisorMSB_T_39, UInt<2>(0h3), _divisorMSB_T_42) node _divisorMSB_T_44 = bits(divisorMSB_lo_7, 3, 3) node _divisorMSB_T_45 = bits(divisorMSB_lo_7, 2, 2) node _divisorMSB_T_46 = bits(divisorMSB_lo_7, 1, 1) node _divisorMSB_T_47 = mux(_divisorMSB_T_45, UInt<2>(0h2), _divisorMSB_T_46) node _divisorMSB_T_48 = mux(_divisorMSB_T_44, UInt<2>(0h3), _divisorMSB_T_47) node _divisorMSB_T_49 = mux(divisorMSB_useHi_7, _divisorMSB_T_43, _divisorMSB_T_48) node _divisorMSB_T_50 = cat(divisorMSB_useHi_7, _divisorMSB_T_49) node _divisorMSB_T_51 = mux(divisorMSB_useHi_5, _divisorMSB_T_38, _divisorMSB_T_50) node _divisorMSB_T_52 = cat(divisorMSB_useHi_5, _divisorMSB_T_51) node _divisorMSB_T_53 = mux(divisorMSB_useHi_1, _divisorMSB_T_26, _divisorMSB_T_52) node _divisorMSB_T_54 = cat(divisorMSB_useHi_1, _divisorMSB_T_53) node divisorMSB_hi_8 = bits(divisorMSB_lo, 31, 16) node divisorMSB_lo_8 = bits(divisorMSB_lo, 15, 0) node divisorMSB_useHi_8 = orr(divisorMSB_hi_8) node divisorMSB_hi_9 = bits(divisorMSB_hi_8, 15, 8) node divisorMSB_lo_9 = bits(divisorMSB_hi_8, 7, 0) node divisorMSB_useHi_9 = orr(divisorMSB_hi_9) node divisorMSB_hi_10 = bits(divisorMSB_hi_9, 7, 4) node divisorMSB_lo_10 = bits(divisorMSB_hi_9, 3, 0) node divisorMSB_useHi_10 = orr(divisorMSB_hi_10) node _divisorMSB_T_55 = bits(divisorMSB_hi_10, 3, 3) node _divisorMSB_T_56 = bits(divisorMSB_hi_10, 2, 2) node _divisorMSB_T_57 = bits(divisorMSB_hi_10, 1, 1) node _divisorMSB_T_58 = mux(_divisorMSB_T_56, UInt<2>(0h2), _divisorMSB_T_57) node _divisorMSB_T_59 = mux(_divisorMSB_T_55, UInt<2>(0h3), _divisorMSB_T_58) node _divisorMSB_T_60 = bits(divisorMSB_lo_10, 3, 3) node _divisorMSB_T_61 = bits(divisorMSB_lo_10, 2, 2) node _divisorMSB_T_62 = bits(divisorMSB_lo_10, 1, 1) node _divisorMSB_T_63 = mux(_divisorMSB_T_61, UInt<2>(0h2), _divisorMSB_T_62) node _divisorMSB_T_64 = mux(_divisorMSB_T_60, UInt<2>(0h3), _divisorMSB_T_63) node _divisorMSB_T_65 = mux(divisorMSB_useHi_10, _divisorMSB_T_59, _divisorMSB_T_64) node _divisorMSB_T_66 = cat(divisorMSB_useHi_10, _divisorMSB_T_65) node divisorMSB_hi_11 = bits(divisorMSB_lo_9, 7, 4) node divisorMSB_lo_11 = bits(divisorMSB_lo_9, 3, 0) node divisorMSB_useHi_11 = orr(divisorMSB_hi_11) node _divisorMSB_T_67 = bits(divisorMSB_hi_11, 3, 3) node _divisorMSB_T_68 = bits(divisorMSB_hi_11, 2, 2) node _divisorMSB_T_69 = bits(divisorMSB_hi_11, 1, 1) node _divisorMSB_T_70 = mux(_divisorMSB_T_68, UInt<2>(0h2), _divisorMSB_T_69) node _divisorMSB_T_71 = mux(_divisorMSB_T_67, UInt<2>(0h3), _divisorMSB_T_70) node _divisorMSB_T_72 = bits(divisorMSB_lo_11, 3, 3) node _divisorMSB_T_73 = bits(divisorMSB_lo_11, 2, 2) node _divisorMSB_T_74 = bits(divisorMSB_lo_11, 1, 1) node _divisorMSB_T_75 = mux(_divisorMSB_T_73, UInt<2>(0h2), _divisorMSB_T_74) node _divisorMSB_T_76 = mux(_divisorMSB_T_72, UInt<2>(0h3), _divisorMSB_T_75) node _divisorMSB_T_77 = mux(divisorMSB_useHi_11, _divisorMSB_T_71, _divisorMSB_T_76) node _divisorMSB_T_78 = cat(divisorMSB_useHi_11, _divisorMSB_T_77) node _divisorMSB_T_79 = mux(divisorMSB_useHi_9, _divisorMSB_T_66, _divisorMSB_T_78) node _divisorMSB_T_80 = cat(divisorMSB_useHi_9, _divisorMSB_T_79) node divisorMSB_hi_12 = bits(divisorMSB_lo_8, 15, 8) node divisorMSB_lo_12 = bits(divisorMSB_lo_8, 7, 0) node divisorMSB_useHi_12 = orr(divisorMSB_hi_12) node divisorMSB_hi_13 = bits(divisorMSB_hi_12, 7, 4) node divisorMSB_lo_13 = bits(divisorMSB_hi_12, 3, 0) node divisorMSB_useHi_13 = orr(divisorMSB_hi_13) node _divisorMSB_T_81 = bits(divisorMSB_hi_13, 3, 3) node _divisorMSB_T_82 = bits(divisorMSB_hi_13, 2, 2) node _divisorMSB_T_83 = bits(divisorMSB_hi_13, 1, 1) node _divisorMSB_T_84 = mux(_divisorMSB_T_82, UInt<2>(0h2), _divisorMSB_T_83) node _divisorMSB_T_85 = mux(_divisorMSB_T_81, UInt<2>(0h3), _divisorMSB_T_84) node _divisorMSB_T_86 = bits(divisorMSB_lo_13, 3, 3) node _divisorMSB_T_87 = bits(divisorMSB_lo_13, 2, 2) node _divisorMSB_T_88 = bits(divisorMSB_lo_13, 1, 1) node _divisorMSB_T_89 = mux(_divisorMSB_T_87, UInt<2>(0h2), _divisorMSB_T_88) node _divisorMSB_T_90 = mux(_divisorMSB_T_86, UInt<2>(0h3), _divisorMSB_T_89) node _divisorMSB_T_91 = mux(divisorMSB_useHi_13, _divisorMSB_T_85, _divisorMSB_T_90) node _divisorMSB_T_92 = cat(divisorMSB_useHi_13, _divisorMSB_T_91) node divisorMSB_hi_14 = bits(divisorMSB_lo_12, 7, 4) node divisorMSB_lo_14 = bits(divisorMSB_lo_12, 3, 0) node divisorMSB_useHi_14 = orr(divisorMSB_hi_14) node _divisorMSB_T_93 = bits(divisorMSB_hi_14, 3, 3) node _divisorMSB_T_94 = bits(divisorMSB_hi_14, 2, 2) node _divisorMSB_T_95 = bits(divisorMSB_hi_14, 1, 1) node _divisorMSB_T_96 = mux(_divisorMSB_T_94, UInt<2>(0h2), _divisorMSB_T_95) node _divisorMSB_T_97 = mux(_divisorMSB_T_93, UInt<2>(0h3), _divisorMSB_T_96) node _divisorMSB_T_98 = bits(divisorMSB_lo_14, 3, 3) node _divisorMSB_T_99 = bits(divisorMSB_lo_14, 2, 2) node _divisorMSB_T_100 = bits(divisorMSB_lo_14, 1, 1) node _divisorMSB_T_101 = mux(_divisorMSB_T_99, UInt<2>(0h2), _divisorMSB_T_100) node _divisorMSB_T_102 = mux(_divisorMSB_T_98, UInt<2>(0h3), _divisorMSB_T_101) node _divisorMSB_T_103 = mux(divisorMSB_useHi_14, _divisorMSB_T_97, _divisorMSB_T_102) node _divisorMSB_T_104 = cat(divisorMSB_useHi_14, _divisorMSB_T_103) node _divisorMSB_T_105 = mux(divisorMSB_useHi_12, _divisorMSB_T_92, _divisorMSB_T_104) node _divisorMSB_T_106 = cat(divisorMSB_useHi_12, _divisorMSB_T_105) node _divisorMSB_T_107 = mux(divisorMSB_useHi_8, _divisorMSB_T_80, _divisorMSB_T_106) node _divisorMSB_T_108 = cat(divisorMSB_useHi_8, _divisorMSB_T_107) node _divisorMSB_T_109 = mux(divisorMSB_useHi, _divisorMSB_T_54, _divisorMSB_T_108) node _divisorMSB_T_110 = cat(divisorMSB_useHi, _divisorMSB_T_109) node divisorMSB = and(_divisorMSB_T_110, alignMask) node _dividendMSB_T = bits(remainder, 63, 0) node dividendMSB_hi = bits(_dividendMSB_T, 63, 32) node dividendMSB_lo = bits(_dividendMSB_T, 31, 0) node dividendMSB_useHi = orr(dividendMSB_hi) node dividendMSB_hi_1 = bits(dividendMSB_hi, 31, 16) node dividendMSB_lo_1 = bits(dividendMSB_hi, 15, 0) node dividendMSB_useHi_1 = orr(dividendMSB_hi_1) node dividendMSB_hi_2 = bits(dividendMSB_hi_1, 15, 8) node dividendMSB_lo_2 = bits(dividendMSB_hi_1, 7, 0) node dividendMSB_useHi_2 = orr(dividendMSB_hi_2) node dividendMSB_hi_3 = bits(dividendMSB_hi_2, 7, 4) node dividendMSB_lo_3 = bits(dividendMSB_hi_2, 3, 0) node dividendMSB_useHi_3 = orr(dividendMSB_hi_3) node _dividendMSB_T_1 = bits(dividendMSB_hi_3, 3, 3) node _dividendMSB_T_2 = bits(dividendMSB_hi_3, 2, 2) node _dividendMSB_T_3 = bits(dividendMSB_hi_3, 1, 1) node _dividendMSB_T_4 = mux(_dividendMSB_T_2, UInt<2>(0h2), _dividendMSB_T_3) node _dividendMSB_T_5 = mux(_dividendMSB_T_1, UInt<2>(0h3), _dividendMSB_T_4) node _dividendMSB_T_6 = bits(dividendMSB_lo_3, 3, 3) node _dividendMSB_T_7 = bits(dividendMSB_lo_3, 2, 2) node _dividendMSB_T_8 = bits(dividendMSB_lo_3, 1, 1) node _dividendMSB_T_9 = mux(_dividendMSB_T_7, UInt<2>(0h2), _dividendMSB_T_8) node _dividendMSB_T_10 = mux(_dividendMSB_T_6, UInt<2>(0h3), _dividendMSB_T_9) node _dividendMSB_T_11 = mux(dividendMSB_useHi_3, _dividendMSB_T_5, _dividendMSB_T_10) node _dividendMSB_T_12 = cat(dividendMSB_useHi_3, _dividendMSB_T_11) node dividendMSB_hi_4 = bits(dividendMSB_lo_2, 7, 4) node dividendMSB_lo_4 = bits(dividendMSB_lo_2, 3, 0) node dividendMSB_useHi_4 = orr(dividendMSB_hi_4) node _dividendMSB_T_13 = bits(dividendMSB_hi_4, 3, 3) node _dividendMSB_T_14 = bits(dividendMSB_hi_4, 2, 2) node _dividendMSB_T_15 = bits(dividendMSB_hi_4, 1, 1) node _dividendMSB_T_16 = mux(_dividendMSB_T_14, UInt<2>(0h2), _dividendMSB_T_15) node _dividendMSB_T_17 = mux(_dividendMSB_T_13, UInt<2>(0h3), _dividendMSB_T_16) node _dividendMSB_T_18 = bits(dividendMSB_lo_4, 3, 3) node _dividendMSB_T_19 = bits(dividendMSB_lo_4, 2, 2) node _dividendMSB_T_20 = bits(dividendMSB_lo_4, 1, 1) node _dividendMSB_T_21 = mux(_dividendMSB_T_19, UInt<2>(0h2), _dividendMSB_T_20) node _dividendMSB_T_22 = mux(_dividendMSB_T_18, UInt<2>(0h3), _dividendMSB_T_21) node _dividendMSB_T_23 = mux(dividendMSB_useHi_4, _dividendMSB_T_17, _dividendMSB_T_22) node _dividendMSB_T_24 = cat(dividendMSB_useHi_4, _dividendMSB_T_23) node _dividendMSB_T_25 = mux(dividendMSB_useHi_2, _dividendMSB_T_12, _dividendMSB_T_24) node _dividendMSB_T_26 = cat(dividendMSB_useHi_2, _dividendMSB_T_25) node dividendMSB_hi_5 = bits(dividendMSB_lo_1, 15, 8) node dividendMSB_lo_5 = bits(dividendMSB_lo_1, 7, 0) node dividendMSB_useHi_5 = orr(dividendMSB_hi_5) node dividendMSB_hi_6 = bits(dividendMSB_hi_5, 7, 4) node dividendMSB_lo_6 = bits(dividendMSB_hi_5, 3, 0) node dividendMSB_useHi_6 = orr(dividendMSB_hi_6) node _dividendMSB_T_27 = bits(dividendMSB_hi_6, 3, 3) node _dividendMSB_T_28 = bits(dividendMSB_hi_6, 2, 2) node _dividendMSB_T_29 = bits(dividendMSB_hi_6, 1, 1) node _dividendMSB_T_30 = mux(_dividendMSB_T_28, UInt<2>(0h2), _dividendMSB_T_29) node _dividendMSB_T_31 = mux(_dividendMSB_T_27, UInt<2>(0h3), _dividendMSB_T_30) node _dividendMSB_T_32 = bits(dividendMSB_lo_6, 3, 3) node _dividendMSB_T_33 = bits(dividendMSB_lo_6, 2, 2) node _dividendMSB_T_34 = bits(dividendMSB_lo_6, 1, 1) node _dividendMSB_T_35 = mux(_dividendMSB_T_33, UInt<2>(0h2), _dividendMSB_T_34) node _dividendMSB_T_36 = mux(_dividendMSB_T_32, UInt<2>(0h3), _dividendMSB_T_35) node _dividendMSB_T_37 = mux(dividendMSB_useHi_6, _dividendMSB_T_31, _dividendMSB_T_36) node _dividendMSB_T_38 = cat(dividendMSB_useHi_6, _dividendMSB_T_37) node dividendMSB_hi_7 = bits(dividendMSB_lo_5, 7, 4) node dividendMSB_lo_7 = bits(dividendMSB_lo_5, 3, 0) node dividendMSB_useHi_7 = orr(dividendMSB_hi_7) node _dividendMSB_T_39 = bits(dividendMSB_hi_7, 3, 3) node _dividendMSB_T_40 = bits(dividendMSB_hi_7, 2, 2) node _dividendMSB_T_41 = bits(dividendMSB_hi_7, 1, 1) node _dividendMSB_T_42 = mux(_dividendMSB_T_40, UInt<2>(0h2), _dividendMSB_T_41) node _dividendMSB_T_43 = mux(_dividendMSB_T_39, UInt<2>(0h3), _dividendMSB_T_42) node _dividendMSB_T_44 = bits(dividendMSB_lo_7, 3, 3) node _dividendMSB_T_45 = bits(dividendMSB_lo_7, 2, 2) node _dividendMSB_T_46 = bits(dividendMSB_lo_7, 1, 1) node _dividendMSB_T_47 = mux(_dividendMSB_T_45, UInt<2>(0h2), _dividendMSB_T_46) node _dividendMSB_T_48 = mux(_dividendMSB_T_44, UInt<2>(0h3), _dividendMSB_T_47) node _dividendMSB_T_49 = mux(dividendMSB_useHi_7, _dividendMSB_T_43, _dividendMSB_T_48) node _dividendMSB_T_50 = cat(dividendMSB_useHi_7, _dividendMSB_T_49) node _dividendMSB_T_51 = mux(dividendMSB_useHi_5, _dividendMSB_T_38, _dividendMSB_T_50) node _dividendMSB_T_52 = cat(dividendMSB_useHi_5, _dividendMSB_T_51) node _dividendMSB_T_53 = mux(dividendMSB_useHi_1, _dividendMSB_T_26, _dividendMSB_T_52) node _dividendMSB_T_54 = cat(dividendMSB_useHi_1, _dividendMSB_T_53) node dividendMSB_hi_8 = bits(dividendMSB_lo, 31, 16) node dividendMSB_lo_8 = bits(dividendMSB_lo, 15, 0) node dividendMSB_useHi_8 = orr(dividendMSB_hi_8) node dividendMSB_hi_9 = bits(dividendMSB_hi_8, 15, 8) node dividendMSB_lo_9 = bits(dividendMSB_hi_8, 7, 0) node dividendMSB_useHi_9 = orr(dividendMSB_hi_9) node dividendMSB_hi_10 = bits(dividendMSB_hi_9, 7, 4) node dividendMSB_lo_10 = bits(dividendMSB_hi_9, 3, 0) node dividendMSB_useHi_10 = orr(dividendMSB_hi_10) node _dividendMSB_T_55 = bits(dividendMSB_hi_10, 3, 3) node _dividendMSB_T_56 = bits(dividendMSB_hi_10, 2, 2) node _dividendMSB_T_57 = bits(dividendMSB_hi_10, 1, 1) node _dividendMSB_T_58 = mux(_dividendMSB_T_56, UInt<2>(0h2), _dividendMSB_T_57) node _dividendMSB_T_59 = mux(_dividendMSB_T_55, UInt<2>(0h3), _dividendMSB_T_58) node _dividendMSB_T_60 = bits(dividendMSB_lo_10, 3, 3) node _dividendMSB_T_61 = bits(dividendMSB_lo_10, 2, 2) node _dividendMSB_T_62 = bits(dividendMSB_lo_10, 1, 1) node _dividendMSB_T_63 = mux(_dividendMSB_T_61, UInt<2>(0h2), _dividendMSB_T_62) node _dividendMSB_T_64 = mux(_dividendMSB_T_60, UInt<2>(0h3), _dividendMSB_T_63) node _dividendMSB_T_65 = mux(dividendMSB_useHi_10, _dividendMSB_T_59, _dividendMSB_T_64) node _dividendMSB_T_66 = cat(dividendMSB_useHi_10, _dividendMSB_T_65) node dividendMSB_hi_11 = bits(dividendMSB_lo_9, 7, 4) node dividendMSB_lo_11 = bits(dividendMSB_lo_9, 3, 0) node dividendMSB_useHi_11 = orr(dividendMSB_hi_11) node _dividendMSB_T_67 = bits(dividendMSB_hi_11, 3, 3) node _dividendMSB_T_68 = bits(dividendMSB_hi_11, 2, 2) node _dividendMSB_T_69 = bits(dividendMSB_hi_11, 1, 1) node _dividendMSB_T_70 = mux(_dividendMSB_T_68, UInt<2>(0h2), _dividendMSB_T_69) node _dividendMSB_T_71 = mux(_dividendMSB_T_67, UInt<2>(0h3), _dividendMSB_T_70) node _dividendMSB_T_72 = bits(dividendMSB_lo_11, 3, 3) node _dividendMSB_T_73 = bits(dividendMSB_lo_11, 2, 2) node _dividendMSB_T_74 = bits(dividendMSB_lo_11, 1, 1) node _dividendMSB_T_75 = mux(_dividendMSB_T_73, UInt<2>(0h2), _dividendMSB_T_74) node _dividendMSB_T_76 = mux(_dividendMSB_T_72, UInt<2>(0h3), _dividendMSB_T_75) node _dividendMSB_T_77 = mux(dividendMSB_useHi_11, _dividendMSB_T_71, _dividendMSB_T_76) node _dividendMSB_T_78 = cat(dividendMSB_useHi_11, _dividendMSB_T_77) node _dividendMSB_T_79 = mux(dividendMSB_useHi_9, _dividendMSB_T_66, _dividendMSB_T_78) node _dividendMSB_T_80 = cat(dividendMSB_useHi_9, _dividendMSB_T_79) node dividendMSB_hi_12 = bits(dividendMSB_lo_8, 15, 8) node dividendMSB_lo_12 = bits(dividendMSB_lo_8, 7, 0) node dividendMSB_useHi_12 = orr(dividendMSB_hi_12) node dividendMSB_hi_13 = bits(dividendMSB_hi_12, 7, 4) node dividendMSB_lo_13 = bits(dividendMSB_hi_12, 3, 0) node dividendMSB_useHi_13 = orr(dividendMSB_hi_13) node _dividendMSB_T_81 = bits(dividendMSB_hi_13, 3, 3) node _dividendMSB_T_82 = bits(dividendMSB_hi_13, 2, 2) node _dividendMSB_T_83 = bits(dividendMSB_hi_13, 1, 1) node _dividendMSB_T_84 = mux(_dividendMSB_T_82, UInt<2>(0h2), _dividendMSB_T_83) node _dividendMSB_T_85 = mux(_dividendMSB_T_81, UInt<2>(0h3), _dividendMSB_T_84) node _dividendMSB_T_86 = bits(dividendMSB_lo_13, 3, 3) node _dividendMSB_T_87 = bits(dividendMSB_lo_13, 2, 2) node _dividendMSB_T_88 = bits(dividendMSB_lo_13, 1, 1) node _dividendMSB_T_89 = mux(_dividendMSB_T_87, UInt<2>(0h2), _dividendMSB_T_88) node _dividendMSB_T_90 = mux(_dividendMSB_T_86, UInt<2>(0h3), _dividendMSB_T_89) node _dividendMSB_T_91 = mux(dividendMSB_useHi_13, _dividendMSB_T_85, _dividendMSB_T_90) node _dividendMSB_T_92 = cat(dividendMSB_useHi_13, _dividendMSB_T_91) node dividendMSB_hi_14 = bits(dividendMSB_lo_12, 7, 4) node dividendMSB_lo_14 = bits(dividendMSB_lo_12, 3, 0) node dividendMSB_useHi_14 = orr(dividendMSB_hi_14) node _dividendMSB_T_93 = bits(dividendMSB_hi_14, 3, 3) node _dividendMSB_T_94 = bits(dividendMSB_hi_14, 2, 2) node _dividendMSB_T_95 = bits(dividendMSB_hi_14, 1, 1) node _dividendMSB_T_96 = mux(_dividendMSB_T_94, UInt<2>(0h2), _dividendMSB_T_95) node _dividendMSB_T_97 = mux(_dividendMSB_T_93, UInt<2>(0h3), _dividendMSB_T_96) node _dividendMSB_T_98 = bits(dividendMSB_lo_14, 3, 3) node _dividendMSB_T_99 = bits(dividendMSB_lo_14, 2, 2) node _dividendMSB_T_100 = bits(dividendMSB_lo_14, 1, 1) node _dividendMSB_T_101 = mux(_dividendMSB_T_99, UInt<2>(0h2), _dividendMSB_T_100) node _dividendMSB_T_102 = mux(_dividendMSB_T_98, UInt<2>(0h3), _dividendMSB_T_101) node _dividendMSB_T_103 = mux(dividendMSB_useHi_14, _dividendMSB_T_97, _dividendMSB_T_102) node _dividendMSB_T_104 = cat(dividendMSB_useHi_14, _dividendMSB_T_103) node _dividendMSB_T_105 = mux(dividendMSB_useHi_12, _dividendMSB_T_92, _dividendMSB_T_104) node _dividendMSB_T_106 = cat(dividendMSB_useHi_12, _dividendMSB_T_105) node _dividendMSB_T_107 = mux(dividendMSB_useHi_8, _dividendMSB_T_80, _dividendMSB_T_106) node _dividendMSB_T_108 = cat(dividendMSB_useHi_8, _dividendMSB_T_107) node _dividendMSB_T_109 = mux(dividendMSB_useHi, _dividendMSB_T_54, _dividendMSB_T_108) node _dividendMSB_T_110 = cat(dividendMSB_useHi, _dividendMSB_T_109) node _dividendMSB_T_111 = not(alignMask) node dividendMSB = or(_dividendMSB_T_110, _dividendMSB_T_111) node _eOutPos_T = sub(dividendMSB, divisorMSB) node _eOutPos_T_1 = tail(_eOutPos_T, 1) node eOutPos = not(_eOutPos_T_1) node _eOut_T_9 = eq(count, UInt<1>(0h0)) node _eOut_T_10 = eq(divby0, UInt<1>(0h0)) node _eOut_T_11 = and(_eOut_T_9, _eOut_T_10) node _eOut_T_12 = geq(eOutPos, UInt<1>(0h1)) node eOut_1 = and(_eOut_T_11, _eOut_T_12) when eOut_1 : node _remainder_T_3 = bits(remainder, 63, 0) node _remainder_T_4 = dshl(_remainder_T_3, eOutPos) connect remainder, _remainder_T_4 node _count_T_4 = shr(eOutPos, 0) connect count, _count_T_4 node _T_19 = eq(isHi, UInt<1>(0h0)) node _T_20 = and(divby0, _T_19) when _T_20 : connect neg_out, UInt<1>(0h0) node _T_21 = and(io.resp.ready, io.resp.valid) node _T_22 = or(_T_21, io.kill) when _T_22 : connect state, UInt<3>(0h0) node _T_23 = and(io.req.ready, io.req.valid) when _T_23 : node _state_T_1 = or(lhs_sign, rhs_sign) node _state_T_2 = mux(_state_T_1, UInt<3>(0h1), UInt<3>(0h3)) node _state_T_3 = mux(cmdMul, UInt<3>(0h2), _state_T_2) connect state, _state_T_3 connect isHi, cmdHi connect resHi, UInt<1>(0h0) node _count_T_5 = eq(io.req.bits.dw, UInt<1>(0h0)) node _count_T_6 = and(UInt<1>(0h1), _count_T_5) node _count_T_7 = and(cmdMul, _count_T_6) node _count_T_8 = mux(_count_T_7, UInt<3>(0h4), UInt<1>(0h0)) connect count, _count_T_8 node _neg_out_T = neq(lhs_sign, rhs_sign) node _neg_out_T_1 = mux(cmdHi, lhs_sign, _neg_out_T) connect neg_out, _neg_out_T_1 node _divisor_T = cat(rhs_sign, rhs_in) connect divisor, _divisor_T connect remainder, lhs_in connect req, io.req.bits node _outMul_T = xor(UInt<3>(0h6), UInt<3>(0h7)) node _outMul_T_1 = and(state, _outMul_T) node _outMul_T_2 = not(UInt<3>(0h7)) node _outMul_T_3 = and(UInt<3>(0h6), _outMul_T_2) node outMul = eq(_outMul_T_1, _outMul_T_3) node _loOut_T = eq(req.dw, UInt<1>(0h0)) node _loOut_T_1 = and(UInt<1>(0h1), _loOut_T) node _loOut_T_2 = and(UInt<1>(0h1), _loOut_T_1) node _loOut_T_3 = and(_loOut_T_2, outMul) node _loOut_T_4 = bits(result, 63, 32) node _loOut_T_5 = bits(result, 31, 0) node loOut = mux(_loOut_T_3, _loOut_T_4, _loOut_T_5) node _hiOut_T = eq(req.dw, UInt<1>(0h0)) node _hiOut_T_1 = and(UInt<1>(0h1), _hiOut_T) node _hiOut_T_2 = bits(loOut, 31, 31) node _hiOut_T_3 = mux(_hiOut_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _hiOut_T_4 = bits(result, 63, 32) node hiOut = mux(_hiOut_T_1, _hiOut_T_3, _hiOut_T_4) connect io.resp.bits.tag, req.tag node _io_resp_bits_data_T = cat(hiOut, loOut) connect io.resp.bits.data, _io_resp_bits_data_T node _io_resp_bits_full_data_T = bits(remainder, 128, 65) node _io_resp_bits_full_data_T_1 = bits(remainder, 63, 0) node _io_resp_bits_full_data_T_2 = cat(_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1) connect io.resp.bits.full_data, _io_resp_bits_full_data_T_2 node _io_resp_valid_T = eq(state, UInt<3>(0h6)) node _io_resp_valid_T_1 = eq(state, UInt<3>(0h7)) node _io_resp_valid_T_2 = or(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _io_req_ready_T = eq(state, UInt<3>(0h0)) connect io.req.ready, _io_req_ready_T
module MulDiv_1( // @[Multiplier.scala:40:7] input clock, // @[Multiplier.scala:40:7] input reset, // @[Multiplier.scala:40:7] output io_req_ready, // @[Multiplier.scala:45:14] input io_req_valid, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14] input io_req_bits_dw, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14] input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14] input [4:0] io_req_bits_tag, // @[Multiplier.scala:45:14] input io_kill, // @[Multiplier.scala:45:14] input io_resp_ready, // @[Multiplier.scala:45:14] output io_resp_valid, // @[Multiplier.scala:45:14] output [63:0] io_resp_bits_data, // @[Multiplier.scala:45:14] output [4:0] io_resp_bits_tag // @[Multiplier.scala:45:14] ); wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7] wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7] wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7] wire [4:0] io_req_bits_tag_0 = io_req_bits_tag; // @[Multiplier.scala:40:7] wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7] wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7] wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23] wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53] wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37] wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70] wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68] wire _io_req_ready_T; // @[Multiplier.scala:183:25] wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42] wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27] wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32] wire io_req_ready_0; // @[Multiplier.scala:40:7] wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7] wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7] wire [4:0] io_resp_bits_tag_0; // @[Multiplier.scala:40:7] wire io_resp_valid_0; // @[Multiplier.scala:40:7] reg [2:0] state; // @[Multiplier.scala:51:22] reg [4:0] req_fn; // @[Multiplier.scala:53:16] reg req_dw; // @[Multiplier.scala:53:16] reg [63:0] req_in1; // @[Multiplier.scala:53:16] reg [63:0] req_in2; // @[Multiplier.scala:53:16] reg [4:0] req_tag; // @[Multiplier.scala:53:16] assign io_resp_bits_tag_0 = req_tag; // @[Multiplier.scala:40:7, :53:16] reg [6:0] count; // @[Multiplier.scala:54:18] reg neg_out; // @[Multiplier.scala:57:20] reg isHi; // @[Multiplier.scala:58:17] reg resHi; // @[Multiplier.scala:59:18] reg [64:0] divisor; // @[Multiplier.scala:60:20] wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26] reg [129:0] remainder; // @[Multiplier.scala:61:22] wire [2:0] decoded_plaInput; // @[pla.scala:77:22] wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [3:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22] wire cmdMul = decoded[3]; // @[pla.scala:81:23] wire cmdHi = decoded[2]; // @[pla.scala:81:23] wire lhsSigned = decoded[1]; // @[pla.scala:81:23] wire rhsSigned = decoded[0]; // @[pla.scala:81:23] wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60] wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38] wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48] wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}] wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}] wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29] wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43] wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}] wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}] wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29] wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}] wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37] wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36] wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42] wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57] wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55] wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58] wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39] wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31] wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63] wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}] wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27] wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27] wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31] wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}] wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31] wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24] wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23] wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}] wire [7:0] _prod_T = mplier[7:0]; // @[Multiplier.scala:109:24, :112:38] wire [8:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}] wire [8:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}] wire [73:0] _prod_T_3 = {{65{_prod_T_2[8]}}, _prod_T_2} * {{9{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}] wire [74:0] _prod_T_4 = {_prod_T_3[73], _prod_T_3} + {{10{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}] wire [73:0] _prod_T_5 = _prod_T_4[73:0]; // @[Multiplier.scala:112:76] wire [73:0] prod = _prod_T_5; // @[Multiplier.scala:112:76] wire [73:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25] wire [55:0] _nextMulReg_T = mplier[63:8]; // @[Multiplier.scala:109:24, :113:38] wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}] wire _nextMplierSign_T = count == 7'h6; // @[Multiplier.scala:54:18, :114:32] wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}] wire [10:0] _GEN = {1'h0, count, 3'h0}; // @[Multiplier.scala:54:18, :116:54] wire [10:0] _eOutMask_T; // @[Multiplier.scala:116:54] assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54] wire [10:0] _eOutRes_T; // @[Multiplier.scala:119:46] assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46] wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}] wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}] wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}] wire _eOut_T = count != 7'h7; // @[Multiplier.scala:54:18, :117:45] wire _eOut_T_1 = _eOut_T; // @[Multiplier.scala:117:{36,45}] wire _eOut_T_2 = |count; // @[Multiplier.scala:54:18, :117:83] wire _eOut_T_3 = _eOut_T_1 & _eOut_T_2; // @[Multiplier.scala:117:{36,74,83}] wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7] wire _eOut_T_5 = _eOut_T_3 & _eOut_T_4; // @[Multiplier.scala:117:{74,91}, :118:7] wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26] wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}] wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}] wire eOut = _eOut_T_5 & _eOut_T_8; // @[Multiplier.scala:117:91, :118:{13,37}] wire [11:0] _eOutRes_T_1 = 12'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}] wire [10:0] _eOutRes_T_2 = _eOutRes_T_1[10:0]; // @[Multiplier.scala:119:38] wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}] wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}] wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37] wire [129:0] _nextMulReg1_T_1 = eOut ? {1'h0, eOutRes} : nextMulReg; // @[Multiplier.scala:113:25, :118:13, :119:27, :120:55] wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}] wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}] wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34] wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67] wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}] wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}] wire [7:0] _GEN_0 = {1'h0, count} + 8'h1; // @[Multiplier.scala:54:18, :123:20] wire [7:0] _count_T; // @[Multiplier.scala:123:20] assign _count_T = _GEN_0; // @[Multiplier.scala:123:20] wire [7:0] _count_T_2; // @[Multiplier.scala:144:20] assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20] wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20] wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28] wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46] wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24] wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45] wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}] wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67] wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}] wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}] wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19] wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20] wire _divby0_T = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24] wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}] wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}] wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36] wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi = |divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_1 = |divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_2 = |divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_3 = |divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_4 = |divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_5 = |divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_6 = |divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_7 = |divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_8 = |divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_9 = |divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_10 = |divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_11 = |divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_12 = |divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire divisorMSB_useHi_13 = |divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire divisorMSB_useHi_14 = |divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10] wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17] wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi = |dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22] wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17] wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_1 = |dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_2 = |dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_3 = |dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_4 = |dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_5 = |dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_6 = |dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_7 = |dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17] wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_8 = |dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22] wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17] wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_9 = |dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_10 = |dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_11 = |dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17] wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_12 = |dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22] wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17] wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17] wire dividendMSB_useHi_13 = |dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17] wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17] wire dividendMSB_useHi_14 = |dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22] wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17] wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17] wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}] wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17] wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17] wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}] wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}] wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21] wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}] wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10] wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35] wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35] wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}] wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26] wire _eOut_T_9 = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24] wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35] wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}] wire _eOut_T_12 = |eOutPos; // @[Multiplier.scala:152:21, :153:54] wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}] wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}] wire _state_T_1 = lhs_sign | rhs_sign; // @[Multiplier.scala:81:23, :165:46] wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}] wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}] wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}] wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46] wire [2:0] _count_T_8 = {_count_T_7, 2'h0}; // @[Multiplier.scala:168:{38,46}] wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46] wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}] wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19] wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23] wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}] wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}] wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30] wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}] wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65] wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66] wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82] wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}] wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60] wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}] wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50] wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}] wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}] assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27] assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27] assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}] assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32] wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27] wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51] assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42] assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25] assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25] wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39] wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39] wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39] wire _GEN_1 = _T_14 & (eOut | count == 7'h7); // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :118:13, :124:{16,25,55}, :125:13] wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39] wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17] wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Multiplier.scala:40:7] if (reset) // @[Multiplier.scala:40:7] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_23) // @[Decoupled.scala:51:35] state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17] else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0) // @[Decoupled.scala:51:35] state <= 3'h0; // @[Multiplier.scala:51:22] else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13] state <= _state_T; // @[Multiplier.scala:51:22, :139:19] else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13] state <= 3'h6; // @[Multiplier.scala:51:22] else if (_T_13) // @[Multiplier.scala:101:39] state <= 3'h7; // @[Multiplier.scala:51:22] else if (_T_10) // @[Multiplier.scala:92:39] state <= 3'h3; // @[Multiplier.scala:51:22] if (_T_23) begin // @[Decoupled.scala:51:35] req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16] req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16] req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16] req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16] req_tag <= io_req_bits_tag_0; // @[Multiplier.scala:40:7, :53:16] count <= {4'h0, _count_T_8}; // @[Multiplier.scala:54:18, :114:32, :168:{11,38}] isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107] divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19] remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15] end else begin // @[Decoupled.scala:51:35] if (_T_17) begin // @[Multiplier.scala:129:39] count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}] remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}] end else if (_T_14) begin // @[Multiplier.scala:106:39] count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20] remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21] end else if (_T_13 | _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15] remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17] if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15] divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37] end neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35] resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35] always @(posedge) assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7] assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7] assign io_resp_bits_tag = io_resp_bits_tag_0; // @[Multiplier.scala:40:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_79 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_79 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_659 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_660 = and(_T_658, _T_659) node _T_661 = or(UInt<1>(0h0), _T_660) node _T_662 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_663 = cvt(_T_662) node _T_664 = and(_T_663, asSInt(UInt<13>(0h1000))) node _T_665 = asSInt(_T_664) node _T_666 = eq(_T_665, asSInt(UInt<1>(0h0))) node _T_667 = and(_T_661, _T_666) node _T_668 = or(UInt<1>(0h0), _T_667) node _T_669 = and(_T_657, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_669, UInt<1>(0h1), "") : assert_36 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(source_ok, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(is_aligned, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_679 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_679, UInt<1>(0h1), "") : assert_39 node _T_683 = eq(io.in.a.bits.mask, mask) node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(_T_683, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_683, UInt<1>(0h1), "") : assert_40 node _T_687 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_687 : node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_689 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_690 = and(_T_688, _T_689) node _T_691 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_692 = shr(io.in.a.bits.source, 2) node _T_693 = eq(_T_692, UInt<1>(0h0)) node _T_694 = leq(UInt<1>(0h0), uncommonBits_36) node _T_695 = and(_T_693, _T_694) node _T_696 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_697 = and(_T_695, _T_696) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<1>(0h1)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_37) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<2>(0h2)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_38) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_710 = shr(io.in.a.bits.source, 2) node _T_711 = eq(_T_710, UInt<2>(0h3)) node _T_712 = leq(UInt<1>(0h0), uncommonBits_39) node _T_713 = and(_T_711, _T_712) node _T_714 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_715 = and(_T_713, _T_714) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_718 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_719 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_720 = or(_T_691, _T_697) node _T_721 = or(_T_720, _T_703) node _T_722 = or(_T_721, _T_709) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = or(_T_724, _T_717) node _T_726 = or(_T_725, _T_718) node _T_727 = or(_T_726, _T_719) node _T_728 = and(_T_690, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_731 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _T_733 = or(UInt<1>(0h0), _T_732) node _T_734 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_735 = cvt(_T_734) node _T_736 = and(_T_735, asSInt(UInt<13>(0h1000))) node _T_737 = asSInt(_T_736) node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) node _T_739 = and(_T_733, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = and(_T_729, _T_740) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_741, UInt<1>(0h1), "") : assert_41 node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(source_ok, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(is_aligned, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_751 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_751, UInt<1>(0h1), "") : assert_44 node _T_755 = eq(io.in.a.bits.mask, mask) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_755, UInt<1>(0h1), "") : assert_45 node _T_759 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_759 : node _T_760 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_761 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_762 = and(_T_760, _T_761) node _T_763 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h0)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_40) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h1)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_41) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h2)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_42) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h3)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_43) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_791 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_792 = or(_T_763, _T_769) node _T_793 = or(_T_792, _T_775) node _T_794 = or(_T_793, _T_781) node _T_795 = or(_T_794, _T_787) node _T_796 = or(_T_795, _T_788) node _T_797 = or(_T_796, _T_789) node _T_798 = or(_T_797, _T_790) node _T_799 = or(_T_798, _T_791) node _T_800 = and(_T_762, _T_799) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_803 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_804 = and(_T_802, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_807 = cvt(_T_806) node _T_808 = and(_T_807, asSInt(UInt<13>(0h1000))) node _T_809 = asSInt(_T_808) node _T_810 = eq(_T_809, asSInt(UInt<1>(0h0))) node _T_811 = and(_T_805, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = and(_T_801, _T_812) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_813, UInt<1>(0h1), "") : assert_46 node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(source_ok, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(is_aligned, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_823 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_824 = asUInt(reset) node _T_825 = eq(_T_824, UInt<1>(0h0)) when _T_825 : node _T_826 = eq(_T_823, UInt<1>(0h0)) when _T_826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_823, UInt<1>(0h1), "") : assert_49 node _T_827 = eq(io.in.a.bits.mask, mask) node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(_T_827, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_827, UInt<1>(0h1), "") : assert_50 node _T_831 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_831, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_835 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_836 = asUInt(reset) node _T_837 = eq(_T_836, UInt<1>(0h0)) when _T_837 : node _T_838 = eq(_T_835, UInt<1>(0h0)) when _T_838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_835, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_839 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_839 : node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok_1, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_843 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(_T_843, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_843, UInt<1>(0h1), "") : assert_54 node _T_847 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_847, UInt<1>(0h1), "") : assert_55 node _T_851 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_851, UInt<1>(0h1), "") : assert_56 node _T_855 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_855, UInt<1>(0h1), "") : assert_57 node _T_859 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_859 : node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(source_ok_1, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(sink_ok, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_866 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(_T_866, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_866, UInt<1>(0h1), "") : assert_60 node _T_870 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_870, UInt<1>(0h1), "") : assert_61 node _T_874 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_874, UInt<1>(0h1), "") : assert_62 node _T_878 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_878, UInt<1>(0h1), "") : assert_63 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_883, UInt<1>(0h1), "") : assert_64 node _T_887 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(source_ok_1, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(sink_ok, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_894 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_894, UInt<1>(0h1), "") : assert_67 node _T_898 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_898, UInt<1>(0h1), "") : assert_68 node _T_902 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_902, UInt<1>(0h1), "") : assert_69 node _T_906 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_907 = or(_T_906, io.in.d.bits.corrupt) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_907, UInt<1>(0h1), "") : assert_70 node _T_911 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_912 = or(UInt<1>(0h1), _T_911) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_912, UInt<1>(0h1), "") : assert_71 node _T_916 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_916 : node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(source_ok_1, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_920 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_920, UInt<1>(0h1), "") : assert_73 node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_924, UInt<1>(0h1), "") : assert_74 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(UInt<1>(0h1), _T_928) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_929, UInt<1>(0h1), "") : assert_75 node _T_933 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_933 : node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(source_ok_1, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_937 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_937, UInt<1>(0h1), "") : assert_77 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = or(_T_941, io.in.d.bits.corrupt) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_942, UInt<1>(0h1), "") : assert_78 node _T_946 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_947 = or(UInt<1>(0h1), _T_946) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_947, UInt<1>(0h1), "") : assert_79 node _T_951 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(source_ok_1, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_955 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_955, UInt<1>(0h1), "") : assert_81 node _T_959 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_959, UInt<1>(0h1), "") : assert_82 node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_964 = or(UInt<1>(0h1), _T_963) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_964, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_968 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_968, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_972 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_972, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_976 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_976, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_980 = eq(a_first, UInt<1>(0h0)) node _T_981 = and(io.in.a.valid, _T_980) when _T_981 : node _T_982 = eq(io.in.a.bits.opcode, opcode) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_982, UInt<1>(0h1), "") : assert_87 node _T_986 = eq(io.in.a.bits.param, param) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_986, UInt<1>(0h1), "") : assert_88 node _T_990 = eq(io.in.a.bits.size, size) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_990, UInt<1>(0h1), "") : assert_89 node _T_994 = eq(io.in.a.bits.source, source) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_994, UInt<1>(0h1), "") : assert_90 node _T_998 = eq(io.in.a.bits.address, address) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_998, UInt<1>(0h1), "") : assert_91 node _T_1002 = and(io.in.a.ready, io.in.a.valid) node _T_1003 = and(_T_1002, a_first) when _T_1003 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1004 = eq(d_first, UInt<1>(0h0)) node _T_1005 = and(io.in.d.valid, _T_1004) when _T_1005 : node _T_1006 = eq(io.in.d.bits.opcode, opcode_1) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_92 node _T_1010 = eq(io.in.d.bits.param, param_1) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_93 node _T_1014 = eq(io.in.d.bits.size, size_1) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_94 node _T_1018 = eq(io.in.d.bits.source, source_1) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_95 node _T_1022 = eq(io.in.d.bits.sink, sink) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_96 node _T_1026 = eq(io.in.d.bits.denied, denied) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_97 node _T_1030 = and(io.in.d.ready, io.in.d.valid) node _T_1031 = and(_T_1030, d_first) when _T_1031 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1032 = and(io.in.a.valid, a_first_1) node _T_1033 = and(_T_1032, UInt<1>(0h1)) when _T_1033 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1034 = and(io.in.a.ready, io.in.a.valid) node _T_1035 = and(_T_1034, a_first_1) node _T_1036 = and(_T_1035, UInt<1>(0h1)) when _T_1036 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1037 = dshr(inflight, io.in.a.bits.source) node _T_1038 = bits(_T_1037, 0, 0) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1047 = and(io.in.d.ready, io.in.d.valid) node _T_1048 = and(_T_1047, d_first_1) node _T_1049 = and(_T_1048, UInt<1>(0h1)) node _T_1050 = eq(d_release_ack, UInt<1>(0h0)) node _T_1051 = and(_T_1049, _T_1050) when _T_1051 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1052 = and(io.in.d.valid, d_first_1) node _T_1053 = and(_T_1052, UInt<1>(0h1)) node _T_1054 = eq(d_release_ack, UInt<1>(0h0)) node _T_1055 = and(_T_1053, _T_1054) when _T_1055 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1056 = dshr(inflight, io.in.d.bits.source) node _T_1057 = bits(_T_1056, 0, 0) node _T_1058 = or(_T_1057, same_cycle_resp) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1062 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1063 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1064 = or(_T_1062, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_100 node _T_1068 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_101 else : node _T_1072 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1073 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1074 = or(_T_1072, _T_1073) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_102 node _T_1078 = eq(io.in.d.bits.size, a_size_lookup) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_103 node _T_1082 = and(io.in.d.valid, d_first_1) node _T_1083 = and(_T_1082, a_first_1) node _T_1084 = and(_T_1083, io.in.a.valid) node _T_1085 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = eq(d_release_ack, UInt<1>(0h0)) node _T_1088 = and(_T_1086, _T_1087) when _T_1088 : node _T_1089 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1090 = or(_T_1089, io.in.a.ready) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_104 node _T_1094 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1095 = orr(a_set_wo_ready) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) node _T_1097 = or(_T_1094, _T_1096) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_44 node _T_1101 = orr(inflight) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) node _T_1103 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1104 = or(_T_1102, _T_1103) node _T_1105 = lt(watchdog, plusarg_reader.out) node _T_1106 = or(_T_1104, _T_1105) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1110 = and(io.in.a.ready, io.in.a.valid) node _T_1111 = and(io.in.d.ready, io.in.d.valid) node _T_1112 = or(_T_1110, _T_1111) when _T_1112 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1113 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1114 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1115 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = and(_T_1113, _T_1116) when _T_1117 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1118 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1119 = and(_T_1118, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1120 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1121 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1122 = and(_T_1120, _T_1121) node _T_1123 = and(_T_1119, _T_1122) when _T_1123 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1124 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1130 = and(io.in.d.valid, d_first_2) node _T_1131 = and(_T_1130, UInt<1>(0h1)) node _T_1132 = and(_T_1131, d_release_ack_1) when _T_1132 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1133 = and(io.in.d.ready, io.in.d.valid) node _T_1134 = and(_T_1133, d_first_2) node _T_1135 = and(_T_1134, UInt<1>(0h1)) node _T_1136 = and(_T_1135, d_release_ack_1) when _T_1136 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1137 = and(io.in.d.valid, d_first_2) node _T_1138 = and(_T_1137, UInt<1>(0h1)) node _T_1139 = and(_T_1138, d_release_ack_1) when _T_1139 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1140 = dshr(inflight_1, io.in.d.bits.source) node _T_1141 = bits(_T_1140, 0, 0) node _T_1142 = or(_T_1141, same_cycle_resp_1) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1146 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_109 else : node _T_1150 = eq(io.in.d.bits.size, c_size_lookup) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_110 node _T_1154 = and(io.in.d.valid, d_first_2) node _T_1155 = and(_T_1154, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1156 = and(_T_1155, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1157 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1158 = and(_T_1156, _T_1157) node _T_1159 = and(_T_1158, d_release_ack_1) node _T_1160 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1161 = and(_T_1159, _T_1160) when _T_1161 : node _T_1162 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1163 = or(_T_1162, _WIRE_27.ready) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_111 node _T_1167 = orr(c_set_wo_ready) when _T_1167 : node _T_1168 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_45 node _T_1172 = orr(inflight_1) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1175 = or(_T_1173, _T_1174) node _T_1176 = lt(watchdog_1, plusarg_reader_1.out) node _T_1177 = or(_T_1175, _T_1176) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1181 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1182 = and(io.in.d.ready, io.in.d.valid) node _T_1183 = or(_T_1181, _T_1182) when _T_1183 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_75 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h13)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h101c0))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<29>(0h100001c0))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = or(_T_37, _T_42) node _T_44 = and(_T_32, _T_43) node _T_45 = or(UInt<1>(0h0), _T_44) node _T_46 = and(_T_31, _T_45) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_46, UInt<1>(0h1), "") : assert_2 node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_52 = and(_T_50, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h101c0))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<29>(0h100001c0))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = or(_T_58, _T_63) node _T_65 = and(_T_53, _T_64) node _T_66 = or(UInt<1>(0h0), _T_65) node _T_67 = and(UInt<1>(0h0), _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(is_aligned, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_81, UInt<1>(0h1), "") : assert_7 node _T_85 = not(io.in.a.bits.mask) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_86, UInt<1>(0h1), "") : assert_8 node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_94 : node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_97 = and(_T_95, _T_96) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_98 = shr(io.in.a.bits.source, 5) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) node _T_101 = and(_T_99, _T_100) node _T_102 = leq(uncommonBits_2, UInt<5>(0h13)) node _T_103 = and(_T_101, _T_102) node _T_104 = and(_T_97, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h101c0))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<29>(0h100001c0))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(_T_105, _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_120, UInt<1>(0h1), "") : assert_10 node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_126 = and(_T_124, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_129 = cvt(_T_128) node _T_130 = and(_T_129, asSInt(UInt<17>(0h101c0))) node _T_131 = asSInt(_T_130) node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_134 = cvt(_T_133) node _T_135 = and(_T_134, asSInt(UInt<29>(0h100001c0))) node _T_136 = asSInt(_T_135) node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = or(_T_132, _T_137) node _T_139 = and(_T_127, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = and(UInt<1>(0h0), _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_141, UInt<1>(0h1), "") : assert_11 node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_148, UInt<1>(0h1), "") : assert_13 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_155, UInt<1>(0h1), "") : assert_15 node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_159, UInt<1>(0h1), "") : assert_16 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_164, UInt<1>(0h1), "") : assert_17 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_168, UInt<1>(0h1), "") : assert_18 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_176 = shr(io.in.a.bits.source, 5) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_3, UInt<5>(0h13)) node _T_181 = and(_T_179, _T_180) node _T_182 = and(_T_175, _T_181) node _T_183 = or(UInt<1>(0h0), _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_183, UInt<1>(0h1), "") : assert_19 node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<17>(0h101c0))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<29>(0h100001c0))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = or(_T_195, _T_200) node _T_202 = and(_T_190, _T_201) node _T_203 = or(UInt<1>(0h0), _T_202) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_203, UInt<1>(0h1), "") : assert_20 node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(is_aligned, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_213, UInt<1>(0h1), "") : assert_23 node _T_217 = eq(io.in.a.bits.mask, mask) node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(_T_217, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_217, UInt<1>(0h1), "") : assert_24 node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_221, UInt<1>(0h1), "") : assert_25 node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_225 : node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_229 = shr(io.in.a.bits.source, 5) node _T_230 = eq(_T_229, UInt<1>(0h0)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_4, UInt<5>(0h13)) node _T_234 = and(_T_232, _T_233) node _T_235 = and(_T_228, _T_234) node _T_236 = or(UInt<1>(0h0), _T_235) node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_239 = and(_T_237, _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h101c0))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h100001c0))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_236, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_254, UInt<1>(0h1), "") : assert_26 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_264, UInt<1>(0h1), "") : assert_29 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_268, UInt<1>(0h1), "") : assert_30 node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_272 : node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_276 = shr(io.in.a.bits.source, 5) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_5, UInt<5>(0h13)) node _T_281 = and(_T_279, _T_280) node _T_282 = and(_T_275, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h101c0))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<29>(0h100001c0))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = or(_T_292, _T_297) node _T_299 = and(_T_287, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = and(_T_283, _T_300) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_301, UInt<1>(0h1), "") : assert_31 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(is_aligned, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_311, UInt<1>(0h1), "") : assert_34 node _T_315 = not(mask) node _T_316 = and(io.in.a.bits.mask, _T_315) node _T_317 = eq(_T_316, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_317, UInt<1>(0h1), "") : assert_35 node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_325 = shr(io.in.a.bits.source, 5) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_6, UInt<5>(0h13)) node _T_330 = and(_T_328, _T_329) node _T_331 = and(_T_324, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h101c0))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<29>(0h100001c0))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = or(_T_338, _T_343) node _T_345 = and(_T_333, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_332, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_347, UInt<1>(0h1), "") : assert_36 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(is_aligned, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_357, UInt<1>(0h1), "") : assert_39 node _T_361 = eq(io.in.a.bits.mask, mask) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_361, UInt<1>(0h1), "") : assert_40 node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_365 : node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_369 = shr(io.in.a.bits.source, 5) node _T_370 = eq(_T_369, UInt<1>(0h0)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_7, UInt<5>(0h13)) node _T_374 = and(_T_372, _T_373) node _T_375 = and(_T_368, _T_374) node _T_376 = or(UInt<1>(0h0), _T_375) node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h101c0))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<29>(0h100001c0))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = or(_T_382, _T_387) node _T_389 = and(_T_377, _T_388) node _T_390 = or(UInt<1>(0h0), _T_389) node _T_391 = and(_T_376, _T_390) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_391, UInt<1>(0h1), "") : assert_41 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(is_aligned, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_401, UInt<1>(0h1), "") : assert_44 node _T_405 = eq(io.in.a.bits.mask, mask) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_405, UInt<1>(0h1), "") : assert_45 node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_409 : node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_413 = shr(io.in.a.bits.source, 5) node _T_414 = eq(_T_413, UInt<1>(0h0)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_8, UInt<5>(0h13)) node _T_418 = and(_T_416, _T_417) node _T_419 = and(_T_412, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_423 = cvt(_T_422) node _T_424 = and(_T_423, asSInt(UInt<17>(0h101c0))) node _T_425 = asSInt(_T_424) node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<29>(0h100001c0))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = or(_T_426, _T_431) node _T_433 = and(_T_421, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = and(_T_420, _T_434) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_435, UInt<1>(0h1), "") : assert_46 node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(is_aligned, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_445, UInt<1>(0h1), "") : assert_49 node _T_449 = eq(io.in.a.bits.mask, mask) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_449, UInt<1>(0h1), "") : assert_50 node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_453, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_457, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_461 : node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_465, UInt<1>(0h1), "") : assert_54 node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_469, UInt<1>(0h1), "") : assert_55 node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_473, UInt<1>(0h1), "") : assert_56 node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_477, UInt<1>(0h1), "") : assert_57 node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(sink_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_488, UInt<1>(0h1), "") : assert_60 node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_492, UInt<1>(0h1), "") : assert_61 node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_496, UInt<1>(0h1), "") : assert_62 node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_500, UInt<1>(0h1), "") : assert_63 node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_505 = or(UInt<1>(0h1), _T_504) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_505, UInt<1>(0h1), "") : assert_64 node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_509 : node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(sink_ok, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_516, UInt<1>(0h1), "") : assert_67 node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_520, UInt<1>(0h1), "") : assert_68 node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_524, UInt<1>(0h1), "") : assert_69 node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_529 = or(_T_528, io.in.d.bits.corrupt) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_529, UInt<1>(0h1), "") : assert_70 node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_534 = or(UInt<1>(0h1), _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_534, UInt<1>(0h1), "") : assert_71 node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_538 : node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_542, UInt<1>(0h1), "") : assert_73 node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_546, UInt<1>(0h1), "") : assert_74 node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_551 = or(UInt<1>(0h1), _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_551, UInt<1>(0h1), "") : assert_75 node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_555 : node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_559, UInt<1>(0h1), "") : assert_77 node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_564 = or(_T_563, io.in.d.bits.corrupt) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_564, UInt<1>(0h1), "") : assert_78 node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_569 = or(UInt<1>(0h1), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_569, UInt<1>(0h1), "") : assert_79 node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_573 : node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_577, UInt<1>(0h1), "") : assert_81 node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_581, UInt<1>(0h1), "") : assert_82 node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_586 = or(UInt<1>(0h1), _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_586, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_590, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_594, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_598, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_602 = eq(a_first, UInt<1>(0h0)) node _T_603 = and(io.in.a.valid, _T_602) when _T_603 : node _T_604 = eq(io.in.a.bits.opcode, opcode) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_604, UInt<1>(0h1), "") : assert_87 node _T_608 = eq(io.in.a.bits.param, param) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_608, UInt<1>(0h1), "") : assert_88 node _T_612 = eq(io.in.a.bits.size, size) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_612, UInt<1>(0h1), "") : assert_89 node _T_616 = eq(io.in.a.bits.source, source) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_616, UInt<1>(0h1), "") : assert_90 node _T_620 = eq(io.in.a.bits.address, address) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_620, UInt<1>(0h1), "") : assert_91 node _T_624 = and(io.in.a.ready, io.in.a.valid) node _T_625 = and(_T_624, a_first) when _T_625 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_626 = eq(d_first, UInt<1>(0h0)) node _T_627 = and(io.in.d.valid, _T_626) when _T_627 : node _T_628 = eq(io.in.d.bits.opcode, opcode_1) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_628, UInt<1>(0h1), "") : assert_92 node _T_632 = eq(io.in.d.bits.param, param_1) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_632, UInt<1>(0h1), "") : assert_93 node _T_636 = eq(io.in.d.bits.size, size_1) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_636, UInt<1>(0h1), "") : assert_94 node _T_640 = eq(io.in.d.bits.source, source_1) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_640, UInt<1>(0h1), "") : assert_95 node _T_644 = eq(io.in.d.bits.sink, sink) node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(_T_644, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_644, UInt<1>(0h1), "") : assert_96 node _T_648 = eq(io.in.d.bits.denied, denied) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_648, UInt<1>(0h1), "") : assert_97 node _T_652 = and(io.in.d.ready, io.in.d.valid) node _T_653 = and(_T_652, d_first) when _T_653 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<20> connect a_set, UInt<20>(0h0) wire a_set_wo_ready : UInt<20> connect a_set_wo_ready, UInt<20>(0h0) wire a_opcodes_set : UInt<80> connect a_opcodes_set, UInt<80>(0h0) wire a_sizes_set : UInt<80> connect a_sizes_set, UInt<80>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_654 = and(io.in.a.valid, a_first_1) node _T_655 = and(_T_654, UInt<1>(0h1)) when _T_655 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_656 = and(io.in.a.ready, io.in.a.valid) node _T_657 = and(_T_656, a_first_1) node _T_658 = and(_T_657, UInt<1>(0h1)) when _T_658 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_659 = dshr(inflight, io.in.a.bits.source) node _T_660 = bits(_T_659, 0, 0) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_661, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<20> connect d_clr, UInt<20>(0h0) wire d_clr_wo_ready : UInt<20> connect d_clr_wo_ready, UInt<20>(0h0) wire d_opcodes_clr : UInt<80> connect d_opcodes_clr, UInt<80>(0h0) wire d_sizes_clr : UInt<80> connect d_sizes_clr, UInt<80>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_665 = and(io.in.d.valid, d_first_1) node _T_666 = and(_T_665, UInt<1>(0h1)) node _T_667 = eq(d_release_ack, UInt<1>(0h0)) node _T_668 = and(_T_666, _T_667) when _T_668 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_669 = and(io.in.d.ready, io.in.d.valid) node _T_670 = and(_T_669, d_first_1) node _T_671 = and(_T_670, UInt<1>(0h1)) node _T_672 = eq(d_release_ack, UInt<1>(0h0)) node _T_673 = and(_T_671, _T_672) when _T_673 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_674 = and(io.in.d.valid, d_first_1) node _T_675 = and(_T_674, UInt<1>(0h1)) node _T_676 = eq(d_release_ack, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) when _T_677 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_678 = dshr(inflight, io.in.d.bits.source) node _T_679 = bits(_T_678, 0, 0) node _T_680 = or(_T_679, same_cycle_resp) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_680, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_686 = or(_T_684, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_686, UInt<1>(0h1), "") : assert_100 node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_690, UInt<1>(0h1), "") : assert_101 else : node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_696 = or(_T_694, _T_695) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_696, UInt<1>(0h1), "") : assert_102 node _T_700 = eq(io.in.d.bits.size, a_size_lookup) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_700, UInt<1>(0h1), "") : assert_103 node _T_704 = and(io.in.d.valid, d_first_1) node _T_705 = and(_T_704, a_first_1) node _T_706 = and(_T_705, io.in.a.valid) node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(d_release_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_712 = or(_T_711, io.in.a.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_712, UInt<1>(0h1), "") : assert_104 node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_717 = orr(a_set_wo_ready) node _T_718 = eq(_T_717, UInt<1>(0h0)) node _T_719 = or(_T_716, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_719, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_150 node _T_723 = orr(inflight) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_726 = or(_T_724, _T_725) node _T_727 = lt(watchdog, plusarg_reader.out) node _T_728 = or(_T_726, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_728, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_732 = and(io.in.a.ready, io.in.a.valid) node _T_733 = and(io.in.d.ready, io.in.d.valid) node _T_734 = or(_T_732, _T_733) when _T_734 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<20> connect c_set, UInt<20>(0h0) wire c_set_wo_ready : UInt<20> connect c_set_wo_ready, UInt<20>(0h0) wire c_opcodes_set : UInt<80> connect c_opcodes_set, UInt<80>(0h0) wire c_sizes_set : UInt<80> connect c_sizes_set, UInt<80>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_735 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_738 = and(_T_736, _T_737) node _T_739 = and(_T_735, _T_738) when _T_739 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_741 = and(_T_740, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_744 = and(_T_742, _T_743) node _T_745 = and(_T_741, _T_744) when _T_745 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) node _T_747 = bits(_T_746, 0, 0) node _T_748 = eq(_T_747, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_748, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<20> connect d_clr_1, UInt<20>(0h0) wire d_clr_wo_ready_1 : UInt<20> connect d_clr_wo_ready_1, UInt<20>(0h0) wire d_opcodes_clr_1 : UInt<80> connect d_opcodes_clr_1, UInt<80>(0h0) wire d_sizes_clr_1 : UInt<80> connect d_sizes_clr_1, UInt<80>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_752 = and(io.in.d.valid, d_first_2) node _T_753 = and(_T_752, UInt<1>(0h1)) node _T_754 = and(_T_753, d_release_ack_1) when _T_754 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_755 = and(io.in.d.ready, io.in.d.valid) node _T_756 = and(_T_755, d_first_2) node _T_757 = and(_T_756, UInt<1>(0h1)) node _T_758 = and(_T_757, d_release_ack_1) when _T_758 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_759 = and(io.in.d.valid, d_first_2) node _T_760 = and(_T_759, UInt<1>(0h1)) node _T_761 = and(_T_760, d_release_ack_1) when _T_761 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_762 = dshr(inflight_1, io.in.d.bits.source) node _T_763 = bits(_T_762, 0, 0) node _T_764 = or(_T_763, same_cycle_resp_1) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_764, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_768, UInt<1>(0h1), "") : assert_109 else : node _T_772 = eq(io.in.d.bits.size, c_size_lookup) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_772, UInt<1>(0h1), "") : assert_110 node _T_776 = and(io.in.d.valid, d_first_2) node _T_777 = and(_T_776, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_778 = and(_T_777, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_780 = and(_T_778, _T_779) node _T_781 = and(_T_780, d_release_ack_1) node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) when _T_783 : node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_785 = or(_T_784, _WIRE_23.ready) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_785, UInt<1>(0h1), "") : assert_111 node _T_789 = orr(c_set_wo_ready) when _T_789 : node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_790, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_151 node _T_794 = orr(inflight_1) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_797 = or(_T_795, _T_796) node _T_798 = lt(watchdog_1, plusarg_reader_1.out) node _T_799 = or(_T_797, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_799, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_804 = and(io.in.d.ready, io.in.d.valid) node _T_805 = or(_T_803, _T_804) when _T_805 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_152 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_153 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_75( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34] wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34] wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34] wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_732; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [19:0] inflight; // @[Monitor.scala:614:27] reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [79:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [19:0] a_set; // @[Monitor.scala:626:34] wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [79:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [19:0] d_clr; // @[Monitor.scala:664:34] wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [19:0] inflight_1; // @[Monitor.scala:726:35] wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [19:0] d_clr_1; // @[Monitor.scala:774:34] wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module SinkD : input clock : Clock input reset : Reset output io : { resp : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, source : UInt<4>, flip way : UInt<4>, flip set : UInt<11>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, grant_req : { set : UInt<11>, way : UInt<4>}, flip grant_safe : UInt<1>} inst d_q of Queue2_TLBundleD_a32d64s4k3z3c connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, io.d.valid connect d_q.io.enq.bits.corrupt, io.d.bits.corrupt connect d_q.io.enq.bits.data, io.d.bits.data connect d_q.io.enq.bits.denied, io.d.bits.denied connect d_q.io.enq.bits.sink, io.d.bits.sink connect d_q.io.enq.bits.source, io.d.bits.source connect d_q.io.enq.bits.size, io.d.bits.size connect d_q.io.enq.bits.param, io.d.bits.param connect d_q.io.enq.bits.opcode, io.d.bits.opcode connect io.d.ready, d_q.io.enq.ready node _T = and(d_q.io.deq.ready, d_q.io.deq.valid) node _r_beats1_decode_T = dshl(UInt<6>(0h3f), d_q.io.deq.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(d_q.io.deq.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node last = or(_r_last_T, _r_last_T_1) node r_3 = and(last, _T) node _r_count_T = not(r_counter1) node beat = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(first, r_beats1, r_counter1) connect r_counter, _r_counter_T node hasData = bits(d_q.io.deq.bits.opcode, 0, 0) reg io_source_r : UInt<4>, clock when d_q.io.deq.valid : connect io_source_r, d_q.io.deq.bits.source node _io_source_T = mux(d_q.io.deq.valid, d_q.io.deq.bits.source, io_source_r) connect io.source, _io_source_T connect io.grant_req.way, io.way connect io.grant_req.set, io.set node _io_resp_valid_T = or(first, last) node _io_resp_valid_T_1 = and(d_q.io.deq.ready, d_q.io.deq.valid) node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _q_io_deq_ready_T = eq(first, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, io.grant_safe) node _q_io_deq_ready_T_2 = and(io.bs_adr.ready, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 node _io_bs_adr_valid_T = eq(first, UInt<1>(0h0)) node _io_bs_adr_valid_T_1 = and(d_q.io.deq.valid, io.grant_safe) node _io_bs_adr_valid_T_2 = or(_io_bs_adr_valid_T, _io_bs_adr_valid_T_1) connect io.bs_adr.valid, _io_bs_adr_valid_T_2 node _T_1 = and(d_q.io.deq.valid, first) node _T_2 = eq(io.grant_safe, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(io.bs_adr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_adr.valid, _T_4) connect io.resp.bits.last, last connect io.resp.bits.opcode, d_q.io.deq.bits.opcode connect io.resp.bits.param, d_q.io.deq.bits.param connect io.resp.bits.source, d_q.io.deq.bits.source connect io.resp.bits.sink, d_q.io.deq.bits.sink connect io.resp.bits.denied, d_q.io.deq.bits.denied node _io_bs_adr_bits_noop_T = eq(d_q.io.deq.valid, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_1 = eq(hasData, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_2 = or(_io_bs_adr_bits_noop_T, _io_bs_adr_bits_noop_T_1) connect io.bs_adr.bits.noop, _io_bs_adr_bits_noop_T_2 connect io.bs_adr.bits.way, io.way connect io.bs_adr.bits.set, io.set node _io_bs_adr_bits_beat_T = add(beat, io.bs_adr.ready) node _io_bs_adr_bits_beat_T_1 = tail(_io_bs_adr_bits_beat_T, 1) reg io_bs_adr_bits_beat_r : UInt<3>, clock when d_q.io.deq.valid : connect io_bs_adr_bits_beat_r, _io_bs_adr_bits_beat_T_1 node _io_bs_adr_bits_beat_T_2 = mux(d_q.io.deq.valid, beat, io_bs_adr_bits_beat_r) connect io.bs_adr.bits.beat, _io_bs_adr_bits_beat_T_2 node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0)) connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T connect io.bs_dat.data, d_q.io.deq.bits.data node _T_6 = and(d_q.io.deq.valid, d_q.io.deq.bits.corrupt) node _T_7 = eq(d_q.io.deq.bits.denied, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SinkD.scala:82 assert (!(d.valid && d.bits.corrupt && !d.bits.denied), \"Data poisoning unsupported\")\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert
module SinkD( // @[SinkD.scala:34:7] input clock, // @[SinkD.scala:34:7] input reset, // @[SinkD.scala:34:7] output io_resp_valid, // @[SinkD.scala:36:14] output io_resp_bits_last, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_opcode, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_param, // @[SinkD.scala:36:14] output [3:0] io_resp_bits_source, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_sink, // @[SinkD.scala:36:14] output io_resp_bits_denied, // @[SinkD.scala:36:14] output io_d_ready, // @[SinkD.scala:36:14] input io_d_valid, // @[SinkD.scala:36:14] input [2:0] io_d_bits_opcode, // @[SinkD.scala:36:14] input [1:0] io_d_bits_param, // @[SinkD.scala:36:14] input [2:0] io_d_bits_size, // @[SinkD.scala:36:14] input [3:0] io_d_bits_source, // @[SinkD.scala:36:14] input [2:0] io_d_bits_sink, // @[SinkD.scala:36:14] input io_d_bits_denied, // @[SinkD.scala:36:14] input [63:0] io_d_bits_data, // @[SinkD.scala:36:14] input io_d_bits_corrupt, // @[SinkD.scala:36:14] output [3:0] io_source, // @[SinkD.scala:36:14] input [3:0] io_way, // @[SinkD.scala:36:14] input [10:0] io_set, // @[SinkD.scala:36:14] input io_bs_adr_ready, // @[SinkD.scala:36:14] output io_bs_adr_valid, // @[SinkD.scala:36:14] output io_bs_adr_bits_noop, // @[SinkD.scala:36:14] output [3:0] io_bs_adr_bits_way, // @[SinkD.scala:36:14] output [10:0] io_bs_adr_bits_set, // @[SinkD.scala:36:14] output [2:0] io_bs_adr_bits_beat, // @[SinkD.scala:36:14] output [63:0] io_bs_dat_data, // @[SinkD.scala:36:14] output [10:0] io_grant_req_set, // @[SinkD.scala:36:14] output [3:0] io_grant_req_way, // @[SinkD.scala:36:14] input io_grant_safe // @[SinkD.scala:36:14] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_d_valid_0 = io_d_valid; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_opcode_0 = io_d_bits_opcode; // @[SinkD.scala:34:7] wire [1:0] io_d_bits_param_0 = io_d_bits_param; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_size_0 = io_d_bits_size; // @[SinkD.scala:34:7] wire [3:0] io_d_bits_source_0 = io_d_bits_source; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_sink_0 = io_d_bits_sink; // @[SinkD.scala:34:7] wire io_d_bits_denied_0 = io_d_bits_denied; // @[SinkD.scala:34:7] wire [63:0] io_d_bits_data_0 = io_d_bits_data; // @[SinkD.scala:34:7] wire io_d_bits_corrupt_0 = io_d_bits_corrupt; // @[SinkD.scala:34:7] wire [3:0] io_way_0 = io_way; // @[SinkD.scala:34:7] wire [10:0] io_set_0 = io_set; // @[SinkD.scala:34:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkD.scala:34:7] wire io_grant_safe_0 = io_grant_safe; // @[SinkD.scala:34:7] wire io_bs_adr_bits_mask = 1'h1; // @[SinkD.scala:34:7] wire _io_bs_adr_bits_mask_T = 1'h1; // @[SinkD.scala:79:26] wire _io_resp_valid_T_2; // @[SinkD.scala:62:36] wire last; // @[Edges.scala:232:33] wire [3:0] _io_source_T; // @[SinkD.scala:57:19] wire [3:0] io_bs_adr_bits_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [3:0] io_grant_req_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [10:0] io_bs_adr_bits_set_0 = io_set_0; // @[SinkD.scala:34:7] wire [10:0] io_grant_req_set_0 = io_set_0; // @[SinkD.scala:34:7] wire _io_bs_adr_valid_T_2; // @[SinkD.scala:64:29] wire _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:75:35] wire [2:0] _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:78:29] wire io_resp_bits_last_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_opcode_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_param_0; // @[SinkD.scala:34:7] wire [3:0] io_resp_bits_source_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_sink_0; // @[SinkD.scala:34:7] wire io_resp_bits_denied_0; // @[SinkD.scala:34:7] wire io_resp_valid_0; // @[SinkD.scala:34:7] wire io_d_ready_0; // @[SinkD.scala:34:7] wire io_bs_adr_bits_noop_0; // @[SinkD.scala:34:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SinkD.scala:34:7] wire io_bs_adr_valid_0; // @[SinkD.scala:34:7] wire [63:0] io_bs_dat_data_0; // @[SinkD.scala:34:7] wire [3:0] io_source_0; // @[SinkD.scala:34:7] wire _q_io_deq_ready_T_2; // @[SinkD.scala:63:30] wire _io_resp_valid_T_1 = _q_io_deq_ready_T_2 & _d_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire hasData = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [3:0] io_source_r; // @[SinkD.scala:57:53] assign _io_source_T = _d_q_io_deq_valid ? _d_q_io_deq_bits_source : io_source_r; // @[Decoupled.scala:362:21] assign io_source_0 = _io_source_T; // @[SinkD.scala:34:7, :57:19] wire _io_resp_valid_T = first | last; // @[Edges.scala:231:25, :232:33] assign _io_resp_valid_T_2 = _io_resp_valid_T & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[SinkD.scala:34:7, :62:36] wire _q_io_deq_ready_T = ~first; // @[Edges.scala:231:25] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T | io_grant_safe_0; // @[SinkD.scala:34:7, :63:{34,41}] assign _q_io_deq_ready_T_2 = io_bs_adr_ready_0 & _q_io_deq_ready_T_1; // @[SinkD.scala:34:7, :63:{30,41}] wire _io_bs_adr_valid_T = ~first; // @[Edges.scala:231:25] wire _io_bs_adr_valid_T_1 = _d_q_io_deq_valid & io_grant_safe_0; // @[Decoupled.scala:362:21] assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T | _io_bs_adr_valid_T_1; // @[SinkD.scala:64:{22,29,41}] assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SinkD.scala:34:7, :64:29] assign io_resp_bits_param_0 = {1'h0, _d_q_io_deq_bits_param}; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T = ~_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T_1 = ~hasData; // @[Edges.scala:106:36] assign _io_bs_adr_bits_noop_T_2 = _io_bs_adr_bits_noop_T | _io_bs_adr_bits_noop_T_1; // @[SinkD.scala:75:{26,35,38}] assign io_bs_adr_bits_noop_0 = _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:34:7, :75:35] wire [3:0] _io_bs_adr_bits_beat_T = {1'h0, beat} + {3'h0, io_bs_adr_ready_0}; // @[Edges.scala:234:25] wire [2:0] _io_bs_adr_bits_beat_T_1 = _io_bs_adr_bits_beat_T[2:0]; // @[SinkD.scala:78:60] reg [2:0] io_bs_adr_bits_beat_r; // @[SinkD.scala:78:54] assign _io_bs_adr_bits_beat_T_2 = _d_q_io_deq_valid ? beat : io_bs_adr_bits_beat_r; // @[Decoupled.scala:362:21] assign io_bs_adr_bits_beat_0 = _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:34:7, :78:29]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_7 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], _T_191, UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], _T_331, UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_14 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_15 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_7( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_197 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_361 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_197( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_361 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_331 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_331( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_67 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[8], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], chosen_oh : UInt<8>[1]} regreset lock_0 : UInt<8>, clock, reset, UInt<8>(0h0) node unassigned_lo_lo = cat(io.in[1].valid, io.in[0].valid) node unassigned_lo_hi = cat(io.in[3].valid, io.in[2].valid) node unassigned_lo = cat(unassigned_lo_hi, unassigned_lo_lo) node unassigned_hi_lo = cat(io.in[5].valid, io.in[4].valid) node unassigned_hi_hi = cat(io.in[7].valid, io.in[6].valid) node unassigned_hi = cat(unassigned_hi_hi, unassigned_hi_lo) node _unassigned_T = cat(unassigned_hi, unassigned_lo) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire choices : UInt<8>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = bits(_sel_T_2, 6, 6) node _sel_T_10 = bits(_sel_T_2, 7, 7) node _sel_T_11 = bits(_sel_T_2, 8, 8) node _sel_T_12 = bits(_sel_T_2, 9, 9) node _sel_T_13 = bits(_sel_T_2, 10, 10) node _sel_T_14 = bits(_sel_T_2, 11, 11) node _sel_T_15 = bits(_sel_T_2, 12, 12) node _sel_T_16 = bits(_sel_T_2, 13, 13) node _sel_T_17 = bits(_sel_T_2, 14, 14) node _sel_T_18 = bits(_sel_T_2, 15, 15) node _sel_T_19 = mux(_sel_T_18, UInt<16>(0h8000), UInt<16>(0h0)) node _sel_T_20 = mux(_sel_T_17, UInt<16>(0h4000), _sel_T_19) node _sel_T_21 = mux(_sel_T_16, UInt<16>(0h2000), _sel_T_20) node _sel_T_22 = mux(_sel_T_15, UInt<16>(0h1000), _sel_T_21) node _sel_T_23 = mux(_sel_T_14, UInt<16>(0h800), _sel_T_22) node _sel_T_24 = mux(_sel_T_13, UInt<16>(0h400), _sel_T_23) node _sel_T_25 = mux(_sel_T_12, UInt<16>(0h200), _sel_T_24) node _sel_T_26 = mux(_sel_T_11, UInt<16>(0h100), _sel_T_25) node _sel_T_27 = mux(_sel_T_10, UInt<16>(0h80), _sel_T_26) node _sel_T_28 = mux(_sel_T_9, UInt<16>(0h40), _sel_T_27) node _sel_T_29 = mux(_sel_T_8, UInt<16>(0h20), _sel_T_28) node _sel_T_30 = mux(_sel_T_7, UInt<16>(0h10), _sel_T_29) node _sel_T_31 = mux(_sel_T_6, UInt<16>(0h8), _sel_T_30) node _sel_T_32 = mux(_sel_T_5, UInt<16>(0h4), _sel_T_31) node _sel_T_33 = mux(_sel_T_4, UInt<16>(0h2), _sel_T_32) node sel = mux(_sel_T_3, UInt<16>(0h1), _sel_T_33) node _choices_0_T = shr(sel, 8) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = bits(_T_1, 3, 3) node _T_6 = bits(_T_1, 4, 4) node _T_7 = bits(_T_1, 5, 5) node _T_8 = bits(_T_1, 6, 6) node _T_9 = bits(_T_1, 7, 7) node _T_10 = mux(_T_9, UInt<8>(0h80), UInt<8>(0h0)) node _T_11 = mux(_T_8, UInt<8>(0h40), _T_10) node _T_12 = mux(_T_7, UInt<8>(0h20), _T_11) node _T_13 = mux(_T_6, UInt<8>(0h10), _T_12) node _T_14 = mux(_T_5, UInt<8>(0h8), _T_13) node _T_15 = mux(_T_4, UInt<8>(0h4), _T_14) node _T_16 = mux(_T_3, UInt<8>(0h2), _T_15) node _T_17 = mux(_T_2, UInt<8>(0h1), _T_16) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) connect io.in[3].ready, UInt<1>(0h0) connect io.in[4].ready, UInt<1>(0h0) connect io.in[5].ready, UInt<1>(0h0) connect io.in[6].ready, UInt<1>(0h0) connect io.in[7].ready, UInt<1>(0h0) node in_tails_lo_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail) node in_tails_lo_hi = cat(io.in[3].bits.tail, io.in[2].bits.tail) node in_tails_lo = cat(in_tails_lo_hi, in_tails_lo_lo) node in_tails_hi_lo = cat(io.in[5].bits.tail, io.in[4].bits.tail) node in_tails_hi_hi = cat(io.in[7].bits.tail, io.in[6].bits.tail) node in_tails_hi = cat(in_tails_hi_hi, in_tails_hi_lo) node in_tails = cat(in_tails_hi, in_tails_lo) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6) node _in_valids_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_9 = and(io.in[4].valid, _in_valids_T_8) node _in_valids_T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_11 = and(io.in[5].valid, _in_valids_T_10) node _in_valids_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_13 = and(io.in[6].valid, _in_valids_T_12) node _in_valids_T_14 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_15 = and(io.in[7].valid, _in_valids_T_14) node in_valids_lo_lo = cat(_in_valids_T_3, _in_valids_T_1) node in_valids_lo_hi = cat(_in_valids_T_7, _in_valids_T_5) node in_valids_lo = cat(in_valids_lo_hi, in_valids_lo_lo) node in_valids_hi_lo = cat(_in_valids_T_11, _in_valids_T_9) node in_valids_hi_hi = cat(_in_valids_T_15, _in_valids_T_13) node in_valids_hi = cat(in_valids_hi_hi, in_valids_hi_lo) node in_valids = cat(in_valids_hi, in_valids_lo) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<8>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) node _io_out_0_bits_T_3 = bits(chosen, 3, 3) node _io_out_0_bits_T_4 = bits(chosen, 4, 4) node _io_out_0_bits_T_5 = bits(chosen, 5, 5) node _io_out_0_bits_T_6 = bits(chosen, 6, 6) node _io_out_0_bits_T_7 = bits(chosen, 7, 7) wire _io_out_0_bits_WIRE : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>} node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_4, io.in[4].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_5, io.in[5].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_6, io.in[6].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_7, io.in[7].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_10) node _io_out_0_bits_T_18 = or(_io_out_0_bits_T_17, _io_out_0_bits_T_11) node _io_out_0_bits_T_19 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_12) node _io_out_0_bits_T_20 = or(_io_out_0_bits_T_19, _io_out_0_bits_T_13) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_14) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_out_0_bits_WIRE_3 : UInt<1>[8] node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_26 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_27 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_25) node _io_out_0_bits_T_33 = or(_io_out_0_bits_T_32, _io_out_0_bits_T_26) node _io_out_0_bits_T_34 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_27) node _io_out_0_bits_T_35 = or(_io_out_0_bits_T_34, _io_out_0_bits_T_28) node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_35, _io_out_0_bits_T_29) node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_30) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_37 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_41 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_42 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_40) node _io_out_0_bits_T_48 = or(_io_out_0_bits_T_47, _io_out_0_bits_T_41) node _io_out_0_bits_T_49 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_42) node _io_out_0_bits_T_50 = or(_io_out_0_bits_T_49, _io_out_0_bits_T_43) node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_50, _io_out_0_bits_T_44) node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_45) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_52 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_57 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_58 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_59 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_61 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54) node _io_out_0_bits_T_62 = or(_io_out_0_bits_T_61, _io_out_0_bits_T_55) node _io_out_0_bits_T_63 = or(_io_out_0_bits_T_62, _io_out_0_bits_T_56) node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_63, _io_out_0_bits_T_57) node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_58) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_59) node _io_out_0_bits_T_67 = or(_io_out_0_bits_T_66, _io_out_0_bits_T_60) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_67 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_71 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_72 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_73 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_74 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_75 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_76 = or(_io_out_0_bits_T_68, _io_out_0_bits_T_69) node _io_out_0_bits_T_77 = or(_io_out_0_bits_T_76, _io_out_0_bits_T_70) node _io_out_0_bits_T_78 = or(_io_out_0_bits_T_77, _io_out_0_bits_T_71) node _io_out_0_bits_T_79 = or(_io_out_0_bits_T_78, _io_out_0_bits_T_72) node _io_out_0_bits_T_80 = or(_io_out_0_bits_T_79, _io_out_0_bits_T_73) node _io_out_0_bits_T_81 = or(_io_out_0_bits_T_80, _io_out_0_bits_T_74) node _io_out_0_bits_T_82 = or(_io_out_0_bits_T_81, _io_out_0_bits_T_75) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_82 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_83 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_84 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_85 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_86 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_87 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_91 = or(_io_out_0_bits_T_83, _io_out_0_bits_T_84) node _io_out_0_bits_T_92 = or(_io_out_0_bits_T_91, _io_out_0_bits_T_85) node _io_out_0_bits_T_93 = or(_io_out_0_bits_T_92, _io_out_0_bits_T_86) node _io_out_0_bits_T_94 = or(_io_out_0_bits_T_93, _io_out_0_bits_T_87) node _io_out_0_bits_T_95 = or(_io_out_0_bits_T_94, _io_out_0_bits_T_88) node _io_out_0_bits_T_96 = or(_io_out_0_bits_T_95, _io_out_0_bits_T_89) node _io_out_0_bits_T_97 = or(_io_out_0_bits_T_96, _io_out_0_bits_T_90) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_97 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_98 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_99 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_100 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_101 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_102 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_103 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_104 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_105 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_106 = or(_io_out_0_bits_T_98, _io_out_0_bits_T_99) node _io_out_0_bits_T_107 = or(_io_out_0_bits_T_106, _io_out_0_bits_T_100) node _io_out_0_bits_T_108 = or(_io_out_0_bits_T_107, _io_out_0_bits_T_101) node _io_out_0_bits_T_109 = or(_io_out_0_bits_T_108, _io_out_0_bits_T_102) node _io_out_0_bits_T_110 = or(_io_out_0_bits_T_109, _io_out_0_bits_T_103) node _io_out_0_bits_T_111 = or(_io_out_0_bits_T_110, _io_out_0_bits_T_104) node _io_out_0_bits_T_112 = or(_io_out_0_bits_T_111, _io_out_0_bits_T_105) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_112 connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_113 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_114 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_115 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_116 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_117 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_118 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_119 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_120 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_121 = or(_io_out_0_bits_T_113, _io_out_0_bits_T_114) node _io_out_0_bits_T_122 = or(_io_out_0_bits_T_121, _io_out_0_bits_T_115) node _io_out_0_bits_T_123 = or(_io_out_0_bits_T_122, _io_out_0_bits_T_116) node _io_out_0_bits_T_124 = or(_io_out_0_bits_T_123, _io_out_0_bits_T_117) node _io_out_0_bits_T_125 = or(_io_out_0_bits_T_124, _io_out_0_bits_T_118) node _io_out_0_bits_T_126 = or(_io_out_0_bits_T_125, _io_out_0_bits_T_119) node _io_out_0_bits_T_127 = or(_io_out_0_bits_T_126, _io_out_0_bits_T_120) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_127 connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_128 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_129 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_130 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_131 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_132 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_133 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_134 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_135 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_136 = or(_io_out_0_bits_T_128, _io_out_0_bits_T_129) node _io_out_0_bits_T_137 = or(_io_out_0_bits_T_136, _io_out_0_bits_T_130) node _io_out_0_bits_T_138 = or(_io_out_0_bits_T_137, _io_out_0_bits_T_131) node _io_out_0_bits_T_139 = or(_io_out_0_bits_T_138, _io_out_0_bits_T_132) node _io_out_0_bits_T_140 = or(_io_out_0_bits_T_139, _io_out_0_bits_T_133) node _io_out_0_bits_T_141 = or(_io_out_0_bits_T_140, _io_out_0_bits_T_134) node _io_out_0_bits_T_142 = or(_io_out_0_bits_T_141, _io_out_0_bits_T_135) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_142 connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_12 : UInt<1>[8] node _io_out_0_bits_T_143 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_144 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_145 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_146 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_147 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_148 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_149 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_150 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_151 = or(_io_out_0_bits_T_143, _io_out_0_bits_T_144) node _io_out_0_bits_T_152 = or(_io_out_0_bits_T_151, _io_out_0_bits_T_145) node _io_out_0_bits_T_153 = or(_io_out_0_bits_T_152, _io_out_0_bits_T_146) node _io_out_0_bits_T_154 = or(_io_out_0_bits_T_153, _io_out_0_bits_T_147) node _io_out_0_bits_T_155 = or(_io_out_0_bits_T_154, _io_out_0_bits_T_148) node _io_out_0_bits_T_156 = or(_io_out_0_bits_T_155, _io_out_0_bits_T_149) node _io_out_0_bits_T_157 = or(_io_out_0_bits_T_156, _io_out_0_bits_T_150) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_157 connect _io_out_0_bits_WIRE_12[0], _io_out_0_bits_WIRE_13 node _io_out_0_bits_T_158 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_159 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_160 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_161 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_162 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_163 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_164 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_165 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[1], UInt<1>(0h0)) node _io_out_0_bits_T_166 = or(_io_out_0_bits_T_158, _io_out_0_bits_T_159) node _io_out_0_bits_T_167 = or(_io_out_0_bits_T_166, _io_out_0_bits_T_160) node _io_out_0_bits_T_168 = or(_io_out_0_bits_T_167, _io_out_0_bits_T_161) node _io_out_0_bits_T_169 = or(_io_out_0_bits_T_168, _io_out_0_bits_T_162) node _io_out_0_bits_T_170 = or(_io_out_0_bits_T_169, _io_out_0_bits_T_163) node _io_out_0_bits_T_171 = or(_io_out_0_bits_T_170, _io_out_0_bits_T_164) node _io_out_0_bits_T_172 = or(_io_out_0_bits_T_171, _io_out_0_bits_T_165) wire _io_out_0_bits_WIRE_14 : UInt<1> connect _io_out_0_bits_WIRE_14, _io_out_0_bits_T_172 connect _io_out_0_bits_WIRE_12[1], _io_out_0_bits_WIRE_14 node _io_out_0_bits_T_173 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_174 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_175 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_176 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_177 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_178 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_179 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_180 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[2], UInt<1>(0h0)) node _io_out_0_bits_T_181 = or(_io_out_0_bits_T_173, _io_out_0_bits_T_174) node _io_out_0_bits_T_182 = or(_io_out_0_bits_T_181, _io_out_0_bits_T_175) node _io_out_0_bits_T_183 = or(_io_out_0_bits_T_182, _io_out_0_bits_T_176) node _io_out_0_bits_T_184 = or(_io_out_0_bits_T_183, _io_out_0_bits_T_177) node _io_out_0_bits_T_185 = or(_io_out_0_bits_T_184, _io_out_0_bits_T_178) node _io_out_0_bits_T_186 = or(_io_out_0_bits_T_185, _io_out_0_bits_T_179) node _io_out_0_bits_T_187 = or(_io_out_0_bits_T_186, _io_out_0_bits_T_180) wire _io_out_0_bits_WIRE_15 : UInt<1> connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_187 connect _io_out_0_bits_WIRE_12[2], _io_out_0_bits_WIRE_15 node _io_out_0_bits_T_188 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_189 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_190 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_191 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_192 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_193 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_194 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_195 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[3], UInt<1>(0h0)) node _io_out_0_bits_T_196 = or(_io_out_0_bits_T_188, _io_out_0_bits_T_189) node _io_out_0_bits_T_197 = or(_io_out_0_bits_T_196, _io_out_0_bits_T_190) node _io_out_0_bits_T_198 = or(_io_out_0_bits_T_197, _io_out_0_bits_T_191) node _io_out_0_bits_T_199 = or(_io_out_0_bits_T_198, _io_out_0_bits_T_192) node _io_out_0_bits_T_200 = or(_io_out_0_bits_T_199, _io_out_0_bits_T_193) node _io_out_0_bits_T_201 = or(_io_out_0_bits_T_200, _io_out_0_bits_T_194) node _io_out_0_bits_T_202 = or(_io_out_0_bits_T_201, _io_out_0_bits_T_195) wire _io_out_0_bits_WIRE_16 : UInt<1> connect _io_out_0_bits_WIRE_16, _io_out_0_bits_T_202 connect _io_out_0_bits_WIRE_12[3], _io_out_0_bits_WIRE_16 node _io_out_0_bits_T_203 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_204 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_205 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_206 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_207 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_208 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_209 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_210 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[4], UInt<1>(0h0)) node _io_out_0_bits_T_211 = or(_io_out_0_bits_T_203, _io_out_0_bits_T_204) node _io_out_0_bits_T_212 = or(_io_out_0_bits_T_211, _io_out_0_bits_T_205) node _io_out_0_bits_T_213 = or(_io_out_0_bits_T_212, _io_out_0_bits_T_206) node _io_out_0_bits_T_214 = or(_io_out_0_bits_T_213, _io_out_0_bits_T_207) node _io_out_0_bits_T_215 = or(_io_out_0_bits_T_214, _io_out_0_bits_T_208) node _io_out_0_bits_T_216 = or(_io_out_0_bits_T_215, _io_out_0_bits_T_209) node _io_out_0_bits_T_217 = or(_io_out_0_bits_T_216, _io_out_0_bits_T_210) wire _io_out_0_bits_WIRE_17 : UInt<1> connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_217 connect _io_out_0_bits_WIRE_12[4], _io_out_0_bits_WIRE_17 node _io_out_0_bits_T_218 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_219 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_220 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_221 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_222 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_223 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_224 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_225 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[5], UInt<1>(0h0)) node _io_out_0_bits_T_226 = or(_io_out_0_bits_T_218, _io_out_0_bits_T_219) node _io_out_0_bits_T_227 = or(_io_out_0_bits_T_226, _io_out_0_bits_T_220) node _io_out_0_bits_T_228 = or(_io_out_0_bits_T_227, _io_out_0_bits_T_221) node _io_out_0_bits_T_229 = or(_io_out_0_bits_T_228, _io_out_0_bits_T_222) node _io_out_0_bits_T_230 = or(_io_out_0_bits_T_229, _io_out_0_bits_T_223) node _io_out_0_bits_T_231 = or(_io_out_0_bits_T_230, _io_out_0_bits_T_224) node _io_out_0_bits_T_232 = or(_io_out_0_bits_T_231, _io_out_0_bits_T_225) wire _io_out_0_bits_WIRE_18 : UInt<1> connect _io_out_0_bits_WIRE_18, _io_out_0_bits_T_232 connect _io_out_0_bits_WIRE_12[5], _io_out_0_bits_WIRE_18 node _io_out_0_bits_T_233 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_234 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_235 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_236 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_237 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_238 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_239 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_240 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[6], UInt<1>(0h0)) node _io_out_0_bits_T_241 = or(_io_out_0_bits_T_233, _io_out_0_bits_T_234) node _io_out_0_bits_T_242 = or(_io_out_0_bits_T_241, _io_out_0_bits_T_235) node _io_out_0_bits_T_243 = or(_io_out_0_bits_T_242, _io_out_0_bits_T_236) node _io_out_0_bits_T_244 = or(_io_out_0_bits_T_243, _io_out_0_bits_T_237) node _io_out_0_bits_T_245 = or(_io_out_0_bits_T_244, _io_out_0_bits_T_238) node _io_out_0_bits_T_246 = or(_io_out_0_bits_T_245, _io_out_0_bits_T_239) node _io_out_0_bits_T_247 = or(_io_out_0_bits_T_246, _io_out_0_bits_T_240) wire _io_out_0_bits_WIRE_19 : UInt<1> connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_247 connect _io_out_0_bits_WIRE_12[6], _io_out_0_bits_WIRE_19 node _io_out_0_bits_T_248 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_249 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_250 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_251 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_252 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_253 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_254 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_255 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[7], UInt<1>(0h0)) node _io_out_0_bits_T_256 = or(_io_out_0_bits_T_248, _io_out_0_bits_T_249) node _io_out_0_bits_T_257 = or(_io_out_0_bits_T_256, _io_out_0_bits_T_250) node _io_out_0_bits_T_258 = or(_io_out_0_bits_T_257, _io_out_0_bits_T_251) node _io_out_0_bits_T_259 = or(_io_out_0_bits_T_258, _io_out_0_bits_T_252) node _io_out_0_bits_T_260 = or(_io_out_0_bits_T_259, _io_out_0_bits_T_253) node _io_out_0_bits_T_261 = or(_io_out_0_bits_T_260, _io_out_0_bits_T_254) node _io_out_0_bits_T_262 = or(_io_out_0_bits_T_261, _io_out_0_bits_T_255) wire _io_out_0_bits_WIRE_20 : UInt<1> connect _io_out_0_bits_WIRE_20, _io_out_0_bits_T_262 connect _io_out_0_bits_WIRE_12[7], _io_out_0_bits_WIRE_20 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_12 wire _io_out_0_bits_WIRE_21 : UInt<1>[8] node _io_out_0_bits_T_263 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_264 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_265 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_266 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_267 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_268 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_269 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_270 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_271 = or(_io_out_0_bits_T_263, _io_out_0_bits_T_264) node _io_out_0_bits_T_272 = or(_io_out_0_bits_T_271, _io_out_0_bits_T_265) node _io_out_0_bits_T_273 = or(_io_out_0_bits_T_272, _io_out_0_bits_T_266) node _io_out_0_bits_T_274 = or(_io_out_0_bits_T_273, _io_out_0_bits_T_267) node _io_out_0_bits_T_275 = or(_io_out_0_bits_T_274, _io_out_0_bits_T_268) node _io_out_0_bits_T_276 = or(_io_out_0_bits_T_275, _io_out_0_bits_T_269) node _io_out_0_bits_T_277 = or(_io_out_0_bits_T_276, _io_out_0_bits_T_270) wire _io_out_0_bits_WIRE_22 : UInt<1> connect _io_out_0_bits_WIRE_22, _io_out_0_bits_T_277 connect _io_out_0_bits_WIRE_21[0], _io_out_0_bits_WIRE_22 node _io_out_0_bits_T_278 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_279 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_280 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_281 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_282 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_283 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_284 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_285 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[1], UInt<1>(0h0)) node _io_out_0_bits_T_286 = or(_io_out_0_bits_T_278, _io_out_0_bits_T_279) node _io_out_0_bits_T_287 = or(_io_out_0_bits_T_286, _io_out_0_bits_T_280) node _io_out_0_bits_T_288 = or(_io_out_0_bits_T_287, _io_out_0_bits_T_281) node _io_out_0_bits_T_289 = or(_io_out_0_bits_T_288, _io_out_0_bits_T_282) node _io_out_0_bits_T_290 = or(_io_out_0_bits_T_289, _io_out_0_bits_T_283) node _io_out_0_bits_T_291 = or(_io_out_0_bits_T_290, _io_out_0_bits_T_284) node _io_out_0_bits_T_292 = or(_io_out_0_bits_T_291, _io_out_0_bits_T_285) wire _io_out_0_bits_WIRE_23 : UInt<1> connect _io_out_0_bits_WIRE_23, _io_out_0_bits_T_292 connect _io_out_0_bits_WIRE_21[1], _io_out_0_bits_WIRE_23 node _io_out_0_bits_T_293 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_294 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_295 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_296 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_297 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_298 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_299 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_300 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[2], UInt<1>(0h0)) node _io_out_0_bits_T_301 = or(_io_out_0_bits_T_293, _io_out_0_bits_T_294) node _io_out_0_bits_T_302 = or(_io_out_0_bits_T_301, _io_out_0_bits_T_295) node _io_out_0_bits_T_303 = or(_io_out_0_bits_T_302, _io_out_0_bits_T_296) node _io_out_0_bits_T_304 = or(_io_out_0_bits_T_303, _io_out_0_bits_T_297) node _io_out_0_bits_T_305 = or(_io_out_0_bits_T_304, _io_out_0_bits_T_298) node _io_out_0_bits_T_306 = or(_io_out_0_bits_T_305, _io_out_0_bits_T_299) node _io_out_0_bits_T_307 = or(_io_out_0_bits_T_306, _io_out_0_bits_T_300) wire _io_out_0_bits_WIRE_24 : UInt<1> connect _io_out_0_bits_WIRE_24, _io_out_0_bits_T_307 connect _io_out_0_bits_WIRE_21[2], _io_out_0_bits_WIRE_24 node _io_out_0_bits_T_308 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_309 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_310 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_311 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_312 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_313 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_314 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_315 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[3], UInt<1>(0h0)) node _io_out_0_bits_T_316 = or(_io_out_0_bits_T_308, _io_out_0_bits_T_309) node _io_out_0_bits_T_317 = or(_io_out_0_bits_T_316, _io_out_0_bits_T_310) node _io_out_0_bits_T_318 = or(_io_out_0_bits_T_317, _io_out_0_bits_T_311) node _io_out_0_bits_T_319 = or(_io_out_0_bits_T_318, _io_out_0_bits_T_312) node _io_out_0_bits_T_320 = or(_io_out_0_bits_T_319, _io_out_0_bits_T_313) node _io_out_0_bits_T_321 = or(_io_out_0_bits_T_320, _io_out_0_bits_T_314) node _io_out_0_bits_T_322 = or(_io_out_0_bits_T_321, _io_out_0_bits_T_315) wire _io_out_0_bits_WIRE_25 : UInt<1> connect _io_out_0_bits_WIRE_25, _io_out_0_bits_T_322 connect _io_out_0_bits_WIRE_21[3], _io_out_0_bits_WIRE_25 node _io_out_0_bits_T_323 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_324 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_325 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_326 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_327 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_328 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_329 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_330 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[4], UInt<1>(0h0)) node _io_out_0_bits_T_331 = or(_io_out_0_bits_T_323, _io_out_0_bits_T_324) node _io_out_0_bits_T_332 = or(_io_out_0_bits_T_331, _io_out_0_bits_T_325) node _io_out_0_bits_T_333 = or(_io_out_0_bits_T_332, _io_out_0_bits_T_326) node _io_out_0_bits_T_334 = or(_io_out_0_bits_T_333, _io_out_0_bits_T_327) node _io_out_0_bits_T_335 = or(_io_out_0_bits_T_334, _io_out_0_bits_T_328) node _io_out_0_bits_T_336 = or(_io_out_0_bits_T_335, _io_out_0_bits_T_329) node _io_out_0_bits_T_337 = or(_io_out_0_bits_T_336, _io_out_0_bits_T_330) wire _io_out_0_bits_WIRE_26 : UInt<1> connect _io_out_0_bits_WIRE_26, _io_out_0_bits_T_337 connect _io_out_0_bits_WIRE_21[4], _io_out_0_bits_WIRE_26 node _io_out_0_bits_T_338 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_339 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_340 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_341 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_342 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_343 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_344 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_345 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[5], UInt<1>(0h0)) node _io_out_0_bits_T_346 = or(_io_out_0_bits_T_338, _io_out_0_bits_T_339) node _io_out_0_bits_T_347 = or(_io_out_0_bits_T_346, _io_out_0_bits_T_340) node _io_out_0_bits_T_348 = or(_io_out_0_bits_T_347, _io_out_0_bits_T_341) node _io_out_0_bits_T_349 = or(_io_out_0_bits_T_348, _io_out_0_bits_T_342) node _io_out_0_bits_T_350 = or(_io_out_0_bits_T_349, _io_out_0_bits_T_343) node _io_out_0_bits_T_351 = or(_io_out_0_bits_T_350, _io_out_0_bits_T_344) node _io_out_0_bits_T_352 = or(_io_out_0_bits_T_351, _io_out_0_bits_T_345) wire _io_out_0_bits_WIRE_27 : UInt<1> connect _io_out_0_bits_WIRE_27, _io_out_0_bits_T_352 connect _io_out_0_bits_WIRE_21[5], _io_out_0_bits_WIRE_27 node _io_out_0_bits_T_353 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_354 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_355 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_356 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_357 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_358 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_359 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_360 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[6], UInt<1>(0h0)) node _io_out_0_bits_T_361 = or(_io_out_0_bits_T_353, _io_out_0_bits_T_354) node _io_out_0_bits_T_362 = or(_io_out_0_bits_T_361, _io_out_0_bits_T_355) node _io_out_0_bits_T_363 = or(_io_out_0_bits_T_362, _io_out_0_bits_T_356) node _io_out_0_bits_T_364 = or(_io_out_0_bits_T_363, _io_out_0_bits_T_357) node _io_out_0_bits_T_365 = or(_io_out_0_bits_T_364, _io_out_0_bits_T_358) node _io_out_0_bits_T_366 = or(_io_out_0_bits_T_365, _io_out_0_bits_T_359) node _io_out_0_bits_T_367 = or(_io_out_0_bits_T_366, _io_out_0_bits_T_360) wire _io_out_0_bits_WIRE_28 : UInt<1> connect _io_out_0_bits_WIRE_28, _io_out_0_bits_T_367 connect _io_out_0_bits_WIRE_21[6], _io_out_0_bits_WIRE_28 node _io_out_0_bits_T_368 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_369 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_370 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_371 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_372 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_373 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_374 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_375 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[7], UInt<1>(0h0)) node _io_out_0_bits_T_376 = or(_io_out_0_bits_T_368, _io_out_0_bits_T_369) node _io_out_0_bits_T_377 = or(_io_out_0_bits_T_376, _io_out_0_bits_T_370) node _io_out_0_bits_T_378 = or(_io_out_0_bits_T_377, _io_out_0_bits_T_371) node _io_out_0_bits_T_379 = or(_io_out_0_bits_T_378, _io_out_0_bits_T_372) node _io_out_0_bits_T_380 = or(_io_out_0_bits_T_379, _io_out_0_bits_T_373) node _io_out_0_bits_T_381 = or(_io_out_0_bits_T_380, _io_out_0_bits_T_374) node _io_out_0_bits_T_382 = or(_io_out_0_bits_T_381, _io_out_0_bits_T_375) wire _io_out_0_bits_WIRE_29 : UInt<1> connect _io_out_0_bits_WIRE_29, _io_out_0_bits_T_382 connect _io_out_0_bits_WIRE_21[7], _io_out_0_bits_WIRE_29 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_21 wire _io_out_0_bits_WIRE_30 : UInt<1>[8] node _io_out_0_bits_T_383 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_384 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_385 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_386 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_387 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_388 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_389 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_390 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_391 = or(_io_out_0_bits_T_383, _io_out_0_bits_T_384) node _io_out_0_bits_T_392 = or(_io_out_0_bits_T_391, _io_out_0_bits_T_385) node _io_out_0_bits_T_393 = or(_io_out_0_bits_T_392, _io_out_0_bits_T_386) node _io_out_0_bits_T_394 = or(_io_out_0_bits_T_393, _io_out_0_bits_T_387) node _io_out_0_bits_T_395 = or(_io_out_0_bits_T_394, _io_out_0_bits_T_388) node _io_out_0_bits_T_396 = or(_io_out_0_bits_T_395, _io_out_0_bits_T_389) node _io_out_0_bits_T_397 = or(_io_out_0_bits_T_396, _io_out_0_bits_T_390) wire _io_out_0_bits_WIRE_31 : UInt<1> connect _io_out_0_bits_WIRE_31, _io_out_0_bits_T_397 connect _io_out_0_bits_WIRE_30[0], _io_out_0_bits_WIRE_31 node _io_out_0_bits_T_398 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_399 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_400 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_401 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_402 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_403 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_404 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_405 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[1], UInt<1>(0h0)) node _io_out_0_bits_T_406 = or(_io_out_0_bits_T_398, _io_out_0_bits_T_399) node _io_out_0_bits_T_407 = or(_io_out_0_bits_T_406, _io_out_0_bits_T_400) node _io_out_0_bits_T_408 = or(_io_out_0_bits_T_407, _io_out_0_bits_T_401) node _io_out_0_bits_T_409 = or(_io_out_0_bits_T_408, _io_out_0_bits_T_402) node _io_out_0_bits_T_410 = or(_io_out_0_bits_T_409, _io_out_0_bits_T_403) node _io_out_0_bits_T_411 = or(_io_out_0_bits_T_410, _io_out_0_bits_T_404) node _io_out_0_bits_T_412 = or(_io_out_0_bits_T_411, _io_out_0_bits_T_405) wire _io_out_0_bits_WIRE_32 : UInt<1> connect _io_out_0_bits_WIRE_32, _io_out_0_bits_T_412 connect _io_out_0_bits_WIRE_30[1], _io_out_0_bits_WIRE_32 node _io_out_0_bits_T_413 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_414 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_415 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_416 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_417 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_418 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_419 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_420 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[2], UInt<1>(0h0)) node _io_out_0_bits_T_421 = or(_io_out_0_bits_T_413, _io_out_0_bits_T_414) node _io_out_0_bits_T_422 = or(_io_out_0_bits_T_421, _io_out_0_bits_T_415) node _io_out_0_bits_T_423 = or(_io_out_0_bits_T_422, _io_out_0_bits_T_416) node _io_out_0_bits_T_424 = or(_io_out_0_bits_T_423, _io_out_0_bits_T_417) node _io_out_0_bits_T_425 = or(_io_out_0_bits_T_424, _io_out_0_bits_T_418) node _io_out_0_bits_T_426 = or(_io_out_0_bits_T_425, _io_out_0_bits_T_419) node _io_out_0_bits_T_427 = or(_io_out_0_bits_T_426, _io_out_0_bits_T_420) wire _io_out_0_bits_WIRE_33 : UInt<1> connect _io_out_0_bits_WIRE_33, _io_out_0_bits_T_427 connect _io_out_0_bits_WIRE_30[2], _io_out_0_bits_WIRE_33 node _io_out_0_bits_T_428 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_429 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_430 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_431 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_432 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_433 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_434 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_435 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[3], UInt<1>(0h0)) node _io_out_0_bits_T_436 = or(_io_out_0_bits_T_428, _io_out_0_bits_T_429) node _io_out_0_bits_T_437 = or(_io_out_0_bits_T_436, _io_out_0_bits_T_430) node _io_out_0_bits_T_438 = or(_io_out_0_bits_T_437, _io_out_0_bits_T_431) node _io_out_0_bits_T_439 = or(_io_out_0_bits_T_438, _io_out_0_bits_T_432) node _io_out_0_bits_T_440 = or(_io_out_0_bits_T_439, _io_out_0_bits_T_433) node _io_out_0_bits_T_441 = or(_io_out_0_bits_T_440, _io_out_0_bits_T_434) node _io_out_0_bits_T_442 = or(_io_out_0_bits_T_441, _io_out_0_bits_T_435) wire _io_out_0_bits_WIRE_34 : UInt<1> connect _io_out_0_bits_WIRE_34, _io_out_0_bits_T_442 connect _io_out_0_bits_WIRE_30[3], _io_out_0_bits_WIRE_34 node _io_out_0_bits_T_443 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_444 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_445 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_446 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_447 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_448 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_449 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_450 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[4], UInt<1>(0h0)) node _io_out_0_bits_T_451 = or(_io_out_0_bits_T_443, _io_out_0_bits_T_444) node _io_out_0_bits_T_452 = or(_io_out_0_bits_T_451, _io_out_0_bits_T_445) node _io_out_0_bits_T_453 = or(_io_out_0_bits_T_452, _io_out_0_bits_T_446) node _io_out_0_bits_T_454 = or(_io_out_0_bits_T_453, _io_out_0_bits_T_447) node _io_out_0_bits_T_455 = or(_io_out_0_bits_T_454, _io_out_0_bits_T_448) node _io_out_0_bits_T_456 = or(_io_out_0_bits_T_455, _io_out_0_bits_T_449) node _io_out_0_bits_T_457 = or(_io_out_0_bits_T_456, _io_out_0_bits_T_450) wire _io_out_0_bits_WIRE_35 : UInt<1> connect _io_out_0_bits_WIRE_35, _io_out_0_bits_T_457 connect _io_out_0_bits_WIRE_30[4], _io_out_0_bits_WIRE_35 node _io_out_0_bits_T_458 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_459 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_460 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_461 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_462 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_463 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_464 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_465 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[5], UInt<1>(0h0)) node _io_out_0_bits_T_466 = or(_io_out_0_bits_T_458, _io_out_0_bits_T_459) node _io_out_0_bits_T_467 = or(_io_out_0_bits_T_466, _io_out_0_bits_T_460) node _io_out_0_bits_T_468 = or(_io_out_0_bits_T_467, _io_out_0_bits_T_461) node _io_out_0_bits_T_469 = or(_io_out_0_bits_T_468, _io_out_0_bits_T_462) node _io_out_0_bits_T_470 = or(_io_out_0_bits_T_469, _io_out_0_bits_T_463) node _io_out_0_bits_T_471 = or(_io_out_0_bits_T_470, _io_out_0_bits_T_464) node _io_out_0_bits_T_472 = or(_io_out_0_bits_T_471, _io_out_0_bits_T_465) wire _io_out_0_bits_WIRE_36 : UInt<1> connect _io_out_0_bits_WIRE_36, _io_out_0_bits_T_472 connect _io_out_0_bits_WIRE_30[5], _io_out_0_bits_WIRE_36 node _io_out_0_bits_T_473 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_474 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_475 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_476 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_477 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_478 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_479 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_480 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[6], UInt<1>(0h0)) node _io_out_0_bits_T_481 = or(_io_out_0_bits_T_473, _io_out_0_bits_T_474) node _io_out_0_bits_T_482 = or(_io_out_0_bits_T_481, _io_out_0_bits_T_475) node _io_out_0_bits_T_483 = or(_io_out_0_bits_T_482, _io_out_0_bits_T_476) node _io_out_0_bits_T_484 = or(_io_out_0_bits_T_483, _io_out_0_bits_T_477) node _io_out_0_bits_T_485 = or(_io_out_0_bits_T_484, _io_out_0_bits_T_478) node _io_out_0_bits_T_486 = or(_io_out_0_bits_T_485, _io_out_0_bits_T_479) node _io_out_0_bits_T_487 = or(_io_out_0_bits_T_486, _io_out_0_bits_T_480) wire _io_out_0_bits_WIRE_37 : UInt<1> connect _io_out_0_bits_WIRE_37, _io_out_0_bits_T_487 connect _io_out_0_bits_WIRE_30[6], _io_out_0_bits_WIRE_37 node _io_out_0_bits_T_488 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_489 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_490 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_491 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_492 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_493 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_494 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_495 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[7], UInt<1>(0h0)) node _io_out_0_bits_T_496 = or(_io_out_0_bits_T_488, _io_out_0_bits_T_489) node _io_out_0_bits_T_497 = or(_io_out_0_bits_T_496, _io_out_0_bits_T_490) node _io_out_0_bits_T_498 = or(_io_out_0_bits_T_497, _io_out_0_bits_T_491) node _io_out_0_bits_T_499 = or(_io_out_0_bits_T_498, _io_out_0_bits_T_492) node _io_out_0_bits_T_500 = or(_io_out_0_bits_T_499, _io_out_0_bits_T_493) node _io_out_0_bits_T_501 = or(_io_out_0_bits_T_500, _io_out_0_bits_T_494) node _io_out_0_bits_T_502 = or(_io_out_0_bits_T_501, _io_out_0_bits_T_495) wire _io_out_0_bits_WIRE_38 : UInt<1> connect _io_out_0_bits_WIRE_38, _io_out_0_bits_T_502 connect _io_out_0_bits_WIRE_30[7], _io_out_0_bits_WIRE_38 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_30 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_18 = bits(chosen, 0, 0) node _T_19 = and(_T_18, io.out[0].ready) when _T_19 : connect io.in[0].ready, UInt<1>(0h1) node _T_20 = bits(chosen, 1, 1) node _T_21 = and(_T_20, io.out[0].ready) when _T_21 : connect io.in[1].ready, UInt<1>(0h1) node _T_22 = bits(chosen, 2, 2) node _T_23 = and(_T_22, io.out[0].ready) when _T_23 : connect io.in[2].ready, UInt<1>(0h1) node _T_24 = bits(chosen, 3, 3) node _T_25 = and(_T_24, io.out[0].ready) when _T_25 : connect io.in[3].ready, UInt<1>(0h1) node _T_26 = bits(chosen, 4, 4) node _T_27 = and(_T_26, io.out[0].ready) when _T_27 : connect io.in[4].ready, UInt<1>(0h1) node _T_28 = bits(chosen, 5, 5) node _T_29 = and(_T_28, io.out[0].ready) when _T_29 : connect io.in[5].ready, UInt<1>(0h1) node _T_30 = bits(chosen, 6, 6) node _T_31 = and(_T_30, io.out[0].ready) when _T_31 : connect io.in[6].ready, UInt<1>(0h1) node _T_32 = bits(chosen, 7, 7) node _T_33 = and(_T_32, io.out[0].ready) when _T_33 : connect io.in[7].ready, UInt<1>(0h1) node _T_34 = or(UInt<8>(0h0), chosen) node _T_35 = and(io.out[0].ready, io.out[0].valid) when _T_35 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_36 = and(io.out[0].ready, io.out[0].valid) when _T_36 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = shr(io.chosen_oh[0], 3) node _mask_T_4 = shr(io.chosen_oh[0], 4) node _mask_T_5 = shr(io.chosen_oh[0], 5) node _mask_T_6 = shr(io.chosen_oh[0], 6) node _mask_T_7 = shr(io.chosen_oh[0], 7) node _mask_T_8 = or(_mask_T, _mask_T_1) node _mask_T_9 = or(_mask_T_8, _mask_T_2) node _mask_T_10 = or(_mask_T_9, _mask_T_3) node _mask_T_11 = or(_mask_T_10, _mask_T_4) node _mask_T_12 = or(_mask_T_11, _mask_T_5) node _mask_T_13 = or(_mask_T_12, _mask_T_6) node _mask_T_14 = or(_mask_T_13, _mask_T_7) connect mask, _mask_T_14 else : node _mask_T_15 = not(mask) node _mask_T_16 = eq(_mask_T_15, UInt<1>(0h0)) node _mask_T_17 = shl(mask, 1) node _mask_T_18 = or(_mask_T_17, UInt<1>(0h1)) node _mask_T_19 = mux(_mask_T_16, UInt<1>(0h0), _mask_T_18) connect mask, _mask_T_19
module SwitchArbiter_67( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_6_ready, // @[SwitchAllocator.scala:18:14] input io_in_6_valid, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_6_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_7_ready, // @[SwitchAllocator.scala:18:14] input io_in_7_valid, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_7_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [7:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [7:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [7:0] unassigned = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [7:0] mask; // @[SwitchAllocator.scala:27:21] wire [7:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [15:0] sel = _sel_T_1[0] ? 16'h1 : _sel_T_1[1] ? 16'h2 : _sel_T_1[2] ? 16'h4 : _sel_T_1[3] ? 16'h8 : _sel_T_1[4] ? 16'h10 : _sel_T_1[5] ? 16'h20 : _sel_T_1[6] ? 16'h40 : _sel_T_1[7] ? 16'h80 : unassigned[0] ? 16'h100 : unassigned[1] ? 16'h200 : unassigned[2] ? 16'h400 : unassigned[3] ? 16'h800 : unassigned[4] ? 16'h1000 : unassigned[5] ? 16'h2000 : unassigned[6] ? 16'h4000 : {unassigned[7], 15'h0}; // @[OneHot.scala:85:71] wire [7:0] in_valids = {io_in_7_valid, io_in_6_valid, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [7:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[7:0] | sel[15:8]; // @[Mux.scala:50:70] wire [7:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire _GEN = io_out_0_ready & (|_io_out_0_valid_T); // @[Decoupled.scala:51:35] wire [6:0] _GEN_0 = chosen[6:0] | chosen[7:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_1 = _GEN_0[5:0] | chosen[7:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_2 = _GEN_1[4:0] | chosen[7:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_3 = _GEN_2[3:0] | chosen[7:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_4 = _GEN_3[2:0] | chosen[7:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_5 = _GEN_4[1:0] | chosen[7:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 8'h0; // @[SwitchAllocator.scala:24:38] mask <= 8'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN) // @[Decoupled.scala:51:35] lock_0 <= chosen & ~{io_in_7_bits_tail, io_in_6_bits_tail, io_in_5_bits_tail, io_in_4_bits_tail, io_in_3_bits_tail, io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN ? {chosen[7], _GEN_0[6], _GEN_1[5], _GEN_2[4], _GEN_3[3], _GEN_4[2], _GEN_5[1], _GEN_5[0] | chosen[7]} : (&mask) ? 8'h0 : {mask[6:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_24 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut
module MulFullRawFN_24( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 connect _source_ok_WIRE[2], _source_ok_T_2 node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_23 = cvt(_T_22) node _T_24 = and(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = asSInt(_T_24) node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = or(_T_21, _T_26) node _T_28 = and(_T_11, _T_19) node _T_29 = and(_T_28, _T_27) node _T_30 = asUInt(reset) node _T_31 = eq(_T_30, UInt<1>(0h0)) when _T_31 : node _T_32 = eq(_T_29, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_29, UInt<1>(0h1), "") : assert_1 node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_33 : node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_40 = or(_T_37, _T_38) node _T_41 = or(_T_40, _T_39) node _T_42 = and(_T_36, _T_41) node _T_43 = or(UInt<1>(0h0), _T_42) node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = or(_T_49, _T_54) node _T_86 = or(_T_85, _T_59) node _T_87 = or(_T_86, _T_64) node _T_88 = or(_T_87, _T_69) node _T_89 = or(_T_88, _T_74) node _T_90 = or(_T_89, _T_79) node _T_91 = or(_T_90, _T_84) node _T_92 = and(_T_44, _T_91) node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = and(_T_94, _T_105) node _T_107 = or(UInt<1>(0h0), _T_92) node _T_108 = or(_T_107, _T_106) node _T_109 = and(_T_43, _T_108) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_109, UInt<1>(0h1), "") : assert_2 node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_113 connect _WIRE[1], _T_114 connect _WIRE[2], _T_115 node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0)) node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_120 = or(_T_117, _T_118) node _T_121 = or(_T_120, _T_119) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_121 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(_WIRE_1, _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_221 = or(_T_218, _T_219) node _T_222 = or(_T_221, _T_220) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_230, _T_235) node _T_267 = or(_T_266, _T_240) node _T_268 = or(_T_267, _T_245) node _T_269 = or(_T_268, _T_250) node _T_270 = or(_T_269, _T_255) node _T_271 = or(_T_270, _T_260) node _T_272 = or(_T_271, _T_265) node _T_273 = and(_T_225, _T_272) node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_280, _T_285) node _T_287 = and(_T_275, _T_286) node _T_288 = or(UInt<1>(0h0), _T_273) node _T_289 = or(_T_288, _T_287) node _T_290 = and(_T_224, _T_289) node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(_T_290, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_290, UInt<1>(0h1), "") : assert_10 node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_294 connect _WIRE_2[1], _T_295 connect _WIRE_2[2], _T_296 node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0)) node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_301 = or(_T_298, _T_299) node _T_302 = or(_T_301, _T_300) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_302 node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_305 = and(_T_303, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_313 = cvt(_T_312) node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000))) node _T_315 = asSInt(_T_314) node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = or(_T_311, _T_316) node _T_358 = or(_T_357, _T_321) node _T_359 = or(_T_358, _T_326) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_336) node _T_362 = or(_T_361, _T_341) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_351) node _T_365 = or(_T_364, _T_356) node _T_366 = and(_T_306, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_WIRE_3, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_368, UInt<1>(0h1), "") : assert_11 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_375, UInt<1>(0h1), "") : assert_13 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(is_aligned, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_382, UInt<1>(0h1), "") : assert_15 node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_386, UInt<1>(0h1), "") : assert_16 node _T_390 = not(io.in.a.bits.mask) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_391, UInt<1>(0h1), "") : assert_17 node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_395, UInt<1>(0h1), "") : assert_18 node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_399 : node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = and(_T_402, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = or(_T_431, _T_436) node _T_473 = or(_T_472, _T_441) node _T_474 = or(_T_473, _T_446) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_456) node _T_477 = or(_T_476, _T_461) node _T_478 = or(_T_477, _T_466) node _T_479 = or(_T_478, _T_471) node _T_480 = and(_T_426, _T_479) node _T_481 = or(UInt<1>(0h0), _T_422) node _T_482 = or(_T_481, _T_480) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_482, UInt<1>(0h1), "") : assert_20 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_492, UInt<1>(0h1), "") : assert_23 node _T_496 = eq(io.in.a.bits.mask, mask) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_496, UInt<1>(0h1), "") : assert_24 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_500, UInt<1>(0h1), "") : assert_25 node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_511 = or(_T_508, _T_509) node _T_512 = or(_T_511, _T_510) node _T_513 = and(_T_507, _T_512) node _T_514 = or(UInt<1>(0h0), _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = and(_T_518, _T_523) node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_527 = and(_T_525, _T_526) node _T_528 = or(UInt<1>(0h0), _T_527) node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = or(_T_533, _T_538) node _T_570 = or(_T_569, _T_543) node _T_571 = or(_T_570, _T_548) node _T_572 = or(_T_571, _T_553) node _T_573 = or(_T_572, _T_558) node _T_574 = or(_T_573, _T_563) node _T_575 = or(_T_574, _T_568) node _T_576 = and(_T_528, _T_575) node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = and(_T_577, _T_582) node _T_584 = or(UInt<1>(0h0), _T_524) node _T_585 = or(_T_584, _T_576) node _T_586 = or(_T_585, _T_583) node _T_587 = and(_T_514, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_587, UInt<1>(0h1), "") : assert_26 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(is_aligned, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_597, UInt<1>(0h1), "") : assert_29 node _T_601 = eq(io.in.a.bits.mask, mask) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_601, UInt<1>(0h1), "") : assert_30 node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_605 : node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_612 = or(_T_609, _T_610) node _T_613 = or(_T_612, _T_611) node _T_614 = and(_T_608, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = or(_T_634, _T_639) node _T_671 = or(_T_670, _T_644) node _T_672 = or(_T_671, _T_649) node _T_673 = or(_T_672, _T_654) node _T_674 = or(_T_673, _T_659) node _T_675 = or(_T_674, _T_664) node _T_676 = or(_T_675, _T_669) node _T_677 = and(_T_629, _T_676) node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_680 = cvt(_T_679) node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000))) node _T_682 = asSInt(_T_681) node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0))) node _T_684 = and(_T_678, _T_683) node _T_685 = or(UInt<1>(0h0), _T_625) node _T_686 = or(_T_685, _T_677) node _T_687 = or(_T_686, _T_684) node _T_688 = and(_T_615, _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_688, UInt<1>(0h1), "") : assert_31 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_698, UInt<1>(0h1), "") : assert_34 node _T_702 = not(mask) node _T_703 = and(io.in.a.bits.mask, _T_702) node _T_704 = eq(_T_703, UInt<1>(0h0)) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_704, UInt<1>(0h1), "") : assert_35 node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_708 : node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_715 = or(_T_712, _T_713) node _T_716 = or(_T_715, _T_714) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_749 = cvt(_T_748) node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000))) node _T_751 = asSInt(_T_750) node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0))) node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = or(_T_727, _T_732) node _T_769 = or(_T_768, _T_737) node _T_770 = or(_T_769, _T_742) node _T_771 = or(_T_770, _T_747) node _T_772 = or(_T_771, _T_752) node _T_773 = or(_T_772, _T_757) node _T_774 = or(_T_773, _T_762) node _T_775 = or(_T_774, _T_767) node _T_776 = and(_T_722, _T_775) node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = and(_T_777, _T_782) node _T_784 = or(UInt<1>(0h0), _T_776) node _T_785 = or(_T_784, _T_783) node _T_786 = and(_T_718, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_786, UInt<1>(0h1), "") : assert_36 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_796, UInt<1>(0h1), "") : assert_39 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_800, UInt<1>(0h1), "") : assert_40 node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_811 = or(_T_808, _T_809) node _T_812 = or(_T_811, _T_810) node _T_813 = and(_T_807, _T_812) node _T_814 = or(UInt<1>(0h0), _T_813) node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_817 = and(_T_815, _T_816) node _T_818 = or(UInt<1>(0h0), _T_817) node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_845 = cvt(_T_844) node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000))) node _T_847 = asSInt(_T_846) node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0))) node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = or(_T_823, _T_828) node _T_865 = or(_T_864, _T_833) node _T_866 = or(_T_865, _T_838) node _T_867 = or(_T_866, _T_843) node _T_868 = or(_T_867, _T_848) node _T_869 = or(_T_868, _T_853) node _T_870 = or(_T_869, _T_858) node _T_871 = or(_T_870, _T_863) node _T_872 = and(_T_818, _T_871) node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = and(_T_873, _T_878) node _T_880 = or(UInt<1>(0h0), _T_872) node _T_881 = or(_T_880, _T_879) node _T_882 = and(_T_814, _T_881) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_882, UInt<1>(0h1), "") : assert_41 node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(source_ok, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(is_aligned, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_892, UInt<1>(0h1), "") : assert_44 node _T_896 = eq(io.in.a.bits.mask, mask) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_896, UInt<1>(0h1), "") : assert_45 node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2)) node _T_907 = or(_T_904, _T_905) node _T_908 = or(_T_907, _T_906) node _T_909 = and(_T_903, _T_908) node _T_910 = or(UInt<1>(0h0), _T_909) node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_913 = and(_T_911, _T_912) node _T_914 = or(UInt<1>(0h0), _T_913) node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = and(_T_914, _T_919) node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_948 = cvt(_T_947) node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000))) node _T_950 = asSInt(_T_949) node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0))) node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_953 = cvt(_T_952) node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000))) node _T_955 = asSInt(_T_954) node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0))) node _T_957 = or(_T_926, _T_931) node _T_958 = or(_T_957, _T_936) node _T_959 = or(_T_958, _T_941) node _T_960 = or(_T_959, _T_946) node _T_961 = or(_T_960, _T_951) node _T_962 = or(_T_961, _T_956) node _T_963 = and(_T_921, _T_962) node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_966 = and(_T_964, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_969 = cvt(_T_968) node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000))) node _T_971 = asSInt(_T_970) node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0))) node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_974 = cvt(_T_973) node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000))) node _T_976 = asSInt(_T_975) node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0))) node _T_978 = or(_T_972, _T_977) node _T_979 = and(_T_967, _T_978) node _T_980 = or(UInt<1>(0h0), _T_920) node _T_981 = or(_T_980, _T_963) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_910, _T_982) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_983, UInt<1>(0h1), "") : assert_46 node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(source_ok, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(is_aligned, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_993, UInt<1>(0h1), "") : assert_49 node _T_997 = eq(io.in.a.bits.mask, mask) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_997, UInt<1>(0h1), "") : assert_50 node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52 node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1)) node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_4 connect _source_ok_WIRE_1[1], _source_ok_T_5 connect _source_ok_WIRE_1[2], _source_ok_T_6 node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1009 : node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(source_ok_1, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54 node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55 node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56 node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57 node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1029 : node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(source_ok_1, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(sink_ok, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60 node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61 node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62 node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h1), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64 node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(sink_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67 node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68 node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(_T_1076, io.in.d.bits.corrupt) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = or(UInt<1>(0h1), _T_1081) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71 node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73 node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(UInt<1>(0h1), _T_1098) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75 node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1103 : node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(source_ok_1, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77 node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.d.bits.corrupt) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78 node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1117 = or(UInt<1>(0h1), _T_1116) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79 node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1121 : node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(source_ok_1, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81 node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84 node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = or(_T_1143, _T_1148) node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = or(_T_1151, _T_1156) node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2)) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1161 = cvt(_T_1160) node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0))) node _T_1163 = asSInt(_T_1162) node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0))) node _T_1165 = or(_T_1159, _T_1164) node _T_1166 = and(_T_1149, _T_1157) node _T_1167 = and(_T_1166, _T_1165) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 connect _legal_source_WIRE[2], _legal_source_T_2 node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0)) node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_7 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1172 connect _WIRE_4[1], _T_1173 connect _WIRE_4[2], _T_1174 node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0)) node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1179 = or(_T_1176, _T_1177) node _T_1180 = or(_T_1179, _T_1178) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1180 node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1183 = and(_T_1181, _T_1182) node _T_1184 = or(UInt<1>(0h0), _T_1183) node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1201 = cvt(_T_1200) node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000))) node _T_1203 = asSInt(_T_1202) node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0))) node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1211 = cvt(_T_1210) node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000))) node _T_1213 = asSInt(_T_1212) node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1216 = cvt(_T_1215) node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000))) node _T_1218 = asSInt(_T_1217) node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0))) node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1226 = cvt(_T_1225) node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000))) node _T_1228 = asSInt(_T_1227) node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0))) node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1189, _T_1194) node _T_1236 = or(_T_1235, _T_1199) node _T_1237 = or(_T_1236, _T_1204) node _T_1238 = or(_T_1237, _T_1209) node _T_1239 = or(_T_1238, _T_1214) node _T_1240 = or(_T_1239, _T_1219) node _T_1241 = or(_T_1240, _T_1224) node _T_1242 = or(_T_1241, _T_1229) node _T_1243 = or(_T_1242, _T_1234) node _T_1244 = and(_T_1184, _T_1243) node _T_1245 = or(UInt<1>(0h0), _T_1244) node _T_1246 = and(_WIRE_5, _T_1245) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86 node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(address_ok, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(legal_source, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90 node _T_1263 = eq(io.in.b.bits.mask, mask_1) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91 node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92 node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1271 : node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1274 = and(_T_1272, _T_1273) node _T_1275 = or(UInt<1>(0h0), _T_1274) node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1277 = cvt(_T_1276) node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000))) node _T_1279 = asSInt(_T_1278) node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1282 = cvt(_T_1281) node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000))) node _T_1284 = asSInt(_T_1283) node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0))) node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1292 = cvt(_T_1291) node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000))) node _T_1294 = asSInt(_T_1293) node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0))) node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1297 = cvt(_T_1296) node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000))) node _T_1299 = asSInt(_T_1298) node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0))) node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1302 = cvt(_T_1301) node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000))) node _T_1304 = asSInt(_T_1303) node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0))) node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1307 = cvt(_T_1306) node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000))) node _T_1309 = asSInt(_T_1308) node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0))) node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1312 = cvt(_T_1311) node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000))) node _T_1314 = asSInt(_T_1313) node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0))) node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1317 = cvt(_T_1316) node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000))) node _T_1319 = asSInt(_T_1318) node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0))) node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1322 = cvt(_T_1321) node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000))) node _T_1324 = asSInt(_T_1323) node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0))) node _T_1326 = or(_T_1280, _T_1285) node _T_1327 = or(_T_1326, _T_1290) node _T_1328 = or(_T_1327, _T_1295) node _T_1329 = or(_T_1328, _T_1300) node _T_1330 = or(_T_1329, _T_1305) node _T_1331 = or(_T_1330, _T_1310) node _T_1332 = or(_T_1331, _T_1315) node _T_1333 = or(_T_1332, _T_1320) node _T_1334 = or(_T_1333, _T_1325) node _T_1335 = and(_T_1275, _T_1334) node _T_1336 = or(UInt<1>(0h0), _T_1335) node _T_1337 = and(UInt<1>(0h0), _T_1336) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93 node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(address_ok, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(legal_source, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97 node _T_1354 = eq(io.in.b.bits.mask, mask_1) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98 node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99 node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1362 : node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1365 = and(_T_1363, _T_1364) node _T_1366 = or(UInt<1>(0h0), _T_1365) node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1368 = cvt(_T_1367) node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000))) node _T_1370 = asSInt(_T_1369) node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0))) node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1373 = cvt(_T_1372) node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000))) node _T_1375 = asSInt(_T_1374) node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0))) node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1388 = cvt(_T_1387) node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000))) node _T_1390 = asSInt(_T_1389) node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0))) node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1393 = cvt(_T_1392) node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000))) node _T_1395 = asSInt(_T_1394) node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0))) node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1398 = cvt(_T_1397) node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000))) node _T_1400 = asSInt(_T_1399) node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0))) node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1403 = cvt(_T_1402) node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000))) node _T_1405 = asSInt(_T_1404) node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0))) node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1408 = cvt(_T_1407) node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000))) node _T_1410 = asSInt(_T_1409) node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0))) node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1413 = cvt(_T_1412) node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000))) node _T_1415 = asSInt(_T_1414) node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0))) node _T_1417 = or(_T_1371, _T_1376) node _T_1418 = or(_T_1417, _T_1381) node _T_1419 = or(_T_1418, _T_1386) node _T_1420 = or(_T_1419, _T_1391) node _T_1421 = or(_T_1420, _T_1396) node _T_1422 = or(_T_1421, _T_1401) node _T_1423 = or(_T_1422, _T_1406) node _T_1424 = or(_T_1423, _T_1411) node _T_1425 = or(_T_1424, _T_1416) node _T_1426 = and(_T_1366, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = and(UInt<1>(0h0), _T_1427) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100 node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(address_ok, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1435 = asUInt(reset) node _T_1436 = eq(_T_1435, UInt<1>(0h0)) when _T_1436 : node _T_1437 = eq(legal_source, UInt<1>(0h0)) when _T_1437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104 node _T_1445 = eq(io.in.b.bits.mask, mask_1) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105 node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1449 : node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1452 = and(_T_1450, _T_1451) node _T_1453 = or(UInt<1>(0h0), _T_1452) node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1455 = cvt(_T_1454) node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000))) node _T_1457 = asSInt(_T_1456) node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0))) node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1460 = cvt(_T_1459) node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000))) node _T_1462 = asSInt(_T_1461) node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1465 = cvt(_T_1464) node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000))) node _T_1467 = asSInt(_T_1466) node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0))) node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1470 = cvt(_T_1469) node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000))) node _T_1472 = asSInt(_T_1471) node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0))) node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1480 = cvt(_T_1479) node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000))) node _T_1482 = asSInt(_T_1481) node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0))) node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1485 = cvt(_T_1484) node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000))) node _T_1487 = asSInt(_T_1486) node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0))) node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1490 = cvt(_T_1489) node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000))) node _T_1492 = asSInt(_T_1491) node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0))) node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1500 = cvt(_T_1499) node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000))) node _T_1502 = asSInt(_T_1501) node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0))) node _T_1504 = or(_T_1458, _T_1463) node _T_1505 = or(_T_1504, _T_1468) node _T_1506 = or(_T_1505, _T_1473) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1483) node _T_1509 = or(_T_1508, _T_1488) node _T_1510 = or(_T_1509, _T_1493) node _T_1511 = or(_T_1510, _T_1498) node _T_1512 = or(_T_1511, _T_1503) node _T_1513 = and(_T_1453, _T_1512) node _T_1514 = or(UInt<1>(0h0), _T_1513) node _T_1515 = and(UInt<1>(0h0), _T_1514) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106 node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(address_ok, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(legal_source, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110 node _T_1532 = not(mask_1) node _T_1533 = and(io.in.b.bits.mask, _T_1532) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111 node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1538 : node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1541 = and(_T_1539, _T_1540) node _T_1542 = or(UInt<1>(0h0), _T_1541) node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1544 = cvt(_T_1543) node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000))) node _T_1546 = asSInt(_T_1545) node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0))) node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1549 = cvt(_T_1548) node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000))) node _T_1551 = asSInt(_T_1550) node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0))) node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1554 = cvt(_T_1553) node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000))) node _T_1556 = asSInt(_T_1555) node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0))) node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1559 = cvt(_T_1558) node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000))) node _T_1561 = asSInt(_T_1560) node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1564 = cvt(_T_1563) node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000))) node _T_1566 = asSInt(_T_1565) node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0))) node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1574 = cvt(_T_1573) node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000))) node _T_1576 = asSInt(_T_1575) node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0))) node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1584 = cvt(_T_1583) node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000))) node _T_1586 = asSInt(_T_1585) node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0))) node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1589 = cvt(_T_1588) node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000))) node _T_1591 = asSInt(_T_1590) node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0))) node _T_1593 = or(_T_1547, _T_1552) node _T_1594 = or(_T_1593, _T_1557) node _T_1595 = or(_T_1594, _T_1562) node _T_1596 = or(_T_1595, _T_1567) node _T_1597 = or(_T_1596, _T_1572) node _T_1598 = or(_T_1597, _T_1577) node _T_1599 = or(_T_1598, _T_1582) node _T_1600 = or(_T_1599, _T_1587) node _T_1601 = or(_T_1600, _T_1592) node _T_1602 = and(_T_1542, _T_1601) node _T_1603 = or(UInt<1>(0h0), _T_1602) node _T_1604 = and(UInt<1>(0h0), _T_1603) node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(_T_1604, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112 node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(address_ok, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(legal_source, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1614 = asUInt(reset) node _T_1615 = eq(_T_1614, UInt<1>(0h0)) when _T_1615 : node _T_1616 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116 node _T_1621 = eq(io.in.b.bits.mask, mask_1) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117 node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1625 : node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1628 = and(_T_1626, _T_1627) node _T_1629 = or(UInt<1>(0h0), _T_1628) node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1631 = cvt(_T_1630) node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000))) node _T_1633 = asSInt(_T_1632) node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0))) node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1636 = cvt(_T_1635) node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000))) node _T_1638 = asSInt(_T_1637) node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0))) node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1641 = cvt(_T_1640) node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000))) node _T_1643 = asSInt(_T_1642) node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0))) node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1646 = cvt(_T_1645) node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000))) node _T_1648 = asSInt(_T_1647) node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0))) node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1651 = cvt(_T_1650) node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000))) node _T_1653 = asSInt(_T_1652) node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0))) node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1656 = cvt(_T_1655) node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000))) node _T_1658 = asSInt(_T_1657) node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0))) node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1666 = cvt(_T_1665) node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000))) node _T_1668 = asSInt(_T_1667) node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1671 = cvt(_T_1670) node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000))) node _T_1673 = asSInt(_T_1672) node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0))) node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1676 = cvt(_T_1675) node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000))) node _T_1678 = asSInt(_T_1677) node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0))) node _T_1680 = or(_T_1634, _T_1639) node _T_1681 = or(_T_1680, _T_1644) node _T_1682 = or(_T_1681, _T_1649) node _T_1683 = or(_T_1682, _T_1654) node _T_1684 = or(_T_1683, _T_1659) node _T_1685 = or(_T_1684, _T_1664) node _T_1686 = or(_T_1685, _T_1669) node _T_1687 = or(_T_1686, _T_1674) node _T_1688 = or(_T_1687, _T_1679) node _T_1689 = and(_T_1629, _T_1688) node _T_1690 = or(UInt<1>(0h0), _T_1689) node _T_1691 = and(UInt<1>(0h0), _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118 node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(address_ok, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1698 = asUInt(reset) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) when _T_1699 : node _T_1700 = eq(legal_source, UInt<1>(0h0)) when _T_1700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1701 = asUInt(reset) node _T_1702 = eq(_T_1701, UInt<1>(0h0)) when _T_1702 : node _T_1703 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122 node _T_1708 = eq(io.in.b.bits.mask, mask_1) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123 node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1712 : node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1715 = and(_T_1713, _T_1714) node _T_1716 = or(UInt<1>(0h0), _T_1715) node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1718 = cvt(_T_1717) node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000))) node _T_1720 = asSInt(_T_1719) node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0))) node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1728 = cvt(_T_1727) node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000))) node _T_1730 = asSInt(_T_1729) node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0))) node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1733 = cvt(_T_1732) node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000))) node _T_1735 = asSInt(_T_1734) node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0))) node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1738 = cvt(_T_1737) node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000))) node _T_1740 = asSInt(_T_1739) node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0))) node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1743 = cvt(_T_1742) node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000))) node _T_1745 = asSInt(_T_1744) node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1748 = cvt(_T_1747) node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000))) node _T_1750 = asSInt(_T_1749) node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0))) node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1758 = cvt(_T_1757) node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000))) node _T_1760 = asSInt(_T_1759) node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0))) node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1721, _T_1726) node _T_1768 = or(_T_1767, _T_1731) node _T_1769 = or(_T_1768, _T_1736) node _T_1770 = or(_T_1769, _T_1741) node _T_1771 = or(_T_1770, _T_1746) node _T_1772 = or(_T_1771, _T_1751) node _T_1773 = or(_T_1772, _T_1756) node _T_1774 = or(_T_1773, _T_1761) node _T_1775 = or(_T_1774, _T_1766) node _T_1776 = and(_T_1716, _T_1775) node _T_1777 = or(UInt<1>(0h0), _T_1776) node _T_1778 = and(UInt<1>(0h0), _T_1777) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124 node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(address_ok, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1785 = asUInt(reset) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) when _T_1786 : node _T_1787 = eq(legal_source, UInt<1>(0h0)) when _T_1787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1791 = eq(io.in.b.bits.mask, mask_1) node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(_T_1791, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128 node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130 node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_8 connect _source_ok_WIRE_2[1], _source_ok_T_9 connect _source_ok_WIRE_2[2], _source_ok_T_10 node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1806 = cvt(_T_1805) node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0))) node _T_1808 = asSInt(_T_1807) node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0))) node _T_1810 = or(_T_1804, _T_1809) node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1814 = cvt(_T_1813) node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0))) node _T_1816 = asSInt(_T_1815) node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0))) node _T_1818 = or(_T_1812, _T_1817) node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1820 = eq(_T_1819, UInt<1>(0h0)) node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1822 = cvt(_T_1821) node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0))) node _T_1824 = asSInt(_T_1823) node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0))) node _T_1826 = or(_T_1820, _T_1825) node _T_1827 = and(_T_1810, _T_1818) node _T_1828 = and(_T_1827, _T_1826) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131 node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1832 : node _T_1833 = asUInt(reset) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) when _T_1834 : node _T_1835 = eq(address_ok_1, UInt<1>(0h0)) when _T_1835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1836 = asUInt(reset) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) when _T_1837 : node _T_1838 = eq(source_ok_2, UInt<1>(0h0)) when _T_1838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1840 = asUInt(reset) node _T_1841 = eq(_T_1840, UInt<1>(0h0)) when _T_1841 : node _T_1842 = eq(_T_1839, UInt<1>(0h0)) when _T_1842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134 node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136 node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(_T_1850, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137 node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1854 : node _T_1855 = asUInt(reset) node _T_1856 = eq(_T_1855, UInt<1>(0h0)) when _T_1856 : node _T_1857 = eq(address_ok_1, UInt<1>(0h0)) when _T_1857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(source_ok_2, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140 node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1872 : node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1875 = and(_T_1873, _T_1874) node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_1879 = or(_T_1876, _T_1877) node _T_1880 = or(_T_1879, _T_1878) node _T_1881 = and(_T_1875, _T_1880) node _T_1882 = or(UInt<1>(0h0), _T_1881) node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1895 = cvt(_T_1894) node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000))) node _T_1897 = asSInt(_T_1896) node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0))) node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1900 = cvt(_T_1899) node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000))) node _T_1902 = asSInt(_T_1901) node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1905 = cvt(_T_1904) node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000))) node _T_1907 = asSInt(_T_1906) node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0))) node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1910 = cvt(_T_1909) node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000))) node _T_1912 = asSInt(_T_1911) node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0))) node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1915 = cvt(_T_1914) node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000))) node _T_1917 = asSInt(_T_1916) node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0))) node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1920 = cvt(_T_1919) node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000))) node _T_1922 = asSInt(_T_1921) node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0))) node _T_1924 = or(_T_1888, _T_1893) node _T_1925 = or(_T_1924, _T_1898) node _T_1926 = or(_T_1925, _T_1903) node _T_1927 = or(_T_1926, _T_1908) node _T_1928 = or(_T_1927, _T_1913) node _T_1929 = or(_T_1928, _T_1918) node _T_1930 = or(_T_1929, _T_1923) node _T_1931 = and(_T_1883, _T_1930) node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1933 = or(UInt<1>(0h0), _T_1932) node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1935 = cvt(_T_1934) node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000))) node _T_1937 = asSInt(_T_1936) node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0))) node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1940 = cvt(_T_1939) node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000))) node _T_1942 = asSInt(_T_1941) node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0))) node _T_1944 = or(_T_1938, _T_1943) node _T_1945 = and(_T_1933, _T_1944) node _T_1946 = or(UInt<1>(0h0), _T_1931) node _T_1947 = or(_T_1946, _T_1945) node _T_1948 = and(_T_1882, _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143 node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_1952 connect _WIRE_6[1], _T_1953 connect _WIRE_6[2], _T_1954 node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = or(_T_1956, _T_1957) node _T_1960 = or(_T_1959, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1960 node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1963 = and(_T_1961, _T_1962) node _T_1964 = or(UInt<1>(0h0), _T_1963) node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1966 = cvt(_T_1965) node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000))) node _T_1968 = asSInt(_T_1967) node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0))) node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1986 = cvt(_T_1985) node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000))) node _T_1988 = asSInt(_T_1987) node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0))) node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1991 = cvt(_T_1990) node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000))) node _T_1993 = asSInt(_T_1992) node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0))) node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1996 = cvt(_T_1995) node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000))) node _T_1998 = asSInt(_T_1997) node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0))) node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2001 = cvt(_T_2000) node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000))) node _T_2003 = asSInt(_T_2002) node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0))) node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2006 = cvt(_T_2005) node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000))) node _T_2008 = asSInt(_T_2007) node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0))) node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_1969, _T_1974) node _T_2016 = or(_T_2015, _T_1979) node _T_2017 = or(_T_2016, _T_1984) node _T_2018 = or(_T_2017, _T_1989) node _T_2019 = or(_T_2018, _T_1994) node _T_2020 = or(_T_2019, _T_1999) node _T_2021 = or(_T_2020, _T_2004) node _T_2022 = or(_T_2021, _T_2009) node _T_2023 = or(_T_2022, _T_2014) node _T_2024 = and(_T_1964, _T_2023) node _T_2025 = or(UInt<1>(0h0), _T_2024) node _T_2026 = and(_WIRE_7, _T_2025) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144 node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(source_ok_2, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146 node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148 node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149 node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2048 : node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2051 = and(_T_2049, _T_2050) node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2)) node _T_2055 = or(_T_2052, _T_2053) node _T_2056 = or(_T_2055, _T_2054) node _T_2057 = and(_T_2051, _T_2056) node _T_2058 = or(UInt<1>(0h0), _T_2057) node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = or(_T_2064, _T_2069) node _T_2101 = or(_T_2100, _T_2074) node _T_2102 = or(_T_2101, _T_2079) node _T_2103 = or(_T_2102, _T_2084) node _T_2104 = or(_T_2103, _T_2089) node _T_2105 = or(_T_2104, _T_2094) node _T_2106 = or(_T_2105, _T_2099) node _T_2107 = and(_T_2059, _T_2106) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = or(UInt<1>(0h0), _T_2108) node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2116 = cvt(_T_2115) node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000))) node _T_2118 = asSInt(_T_2117) node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0))) node _T_2120 = or(_T_2114, _T_2119) node _T_2121 = and(_T_2109, _T_2120) node _T_2122 = or(UInt<1>(0h0), _T_2107) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = and(_T_2058, _T_2123) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150 node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2128 connect _WIRE_8[1], _T_2129 connect _WIRE_8[2], _T_2130 node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0)) node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2135 = or(_T_2132, _T_2133) node _T_2136 = or(_T_2135, _T_2134) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2136 node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = or(UInt<1>(0h0), _T_2139) node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2147 = cvt(_T_2146) node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000))) node _T_2149 = asSInt(_T_2148) node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0))) node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2152 = cvt(_T_2151) node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000))) node _T_2154 = asSInt(_T_2153) node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0))) node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2157 = cvt(_T_2156) node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000))) node _T_2159 = asSInt(_T_2158) node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2162 = cvt(_T_2161) node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000))) node _T_2164 = asSInt(_T_2163) node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0))) node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2172 = cvt(_T_2171) node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000))) node _T_2174 = asSInt(_T_2173) node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0))) node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2177 = cvt(_T_2176) node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000))) node _T_2179 = asSInt(_T_2178) node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0))) node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2182 = cvt(_T_2181) node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000))) node _T_2184 = asSInt(_T_2183) node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0))) node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2187 = cvt(_T_2186) node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000))) node _T_2189 = asSInt(_T_2188) node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0))) node _T_2191 = or(_T_2145, _T_2150) node _T_2192 = or(_T_2191, _T_2155) node _T_2193 = or(_T_2192, _T_2160) node _T_2194 = or(_T_2193, _T_2165) node _T_2195 = or(_T_2194, _T_2170) node _T_2196 = or(_T_2195, _T_2175) node _T_2197 = or(_T_2196, _T_2180) node _T_2198 = or(_T_2197, _T_2185) node _T_2199 = or(_T_2198, _T_2190) node _T_2200 = and(_T_2140, _T_2199) node _T_2201 = or(UInt<1>(0h0), _T_2200) node _T_2202 = and(_WIRE_9, _T_2201) node _T_2203 = asUInt(reset) node _T_2204 = eq(_T_2203, UInt<1>(0h0)) when _T_2204 : node _T_2205 = eq(_T_2202, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(source_ok_2, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153 node _T_2213 = asUInt(reset) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2217 = asUInt(reset) node _T_2218 = eq(_T_2217, UInt<1>(0h0)) when _T_2218 : node _T_2219 = eq(_T_2216, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155 node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2220 : node _T_2221 = asUInt(reset) node _T_2222 = eq(_T_2221, UInt<1>(0h0)) when _T_2222 : node _T_2223 = eq(address_ok_1, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(source_ok_2, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159 node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160 node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2238 : node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(address_ok_1, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(source_ok_2, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164 node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2252 : node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(address_ok_1, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(source_ok_2, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168 node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2273 = eq(a_first, UInt<1>(0h0)) node _T_2274 = and(io.in.a.valid, _T_2273) when _T_2274 : node _T_2275 = eq(io.in.a.bits.opcode, opcode) node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : node _T_2278 = eq(_T_2275, UInt<1>(0h0)) when _T_2278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171 node _T_2279 = eq(io.in.a.bits.param, param) node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : node _T_2282 = eq(_T_2279, UInt<1>(0h0)) when _T_2282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172 node _T_2283 = eq(io.in.a.bits.size, size) node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(_T_2283, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173 node _T_2287 = eq(io.in.a.bits.source, source) node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : node _T_2290 = eq(_T_2287, UInt<1>(0h0)) when _T_2290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174 node _T_2291 = eq(io.in.a.bits.address, address) node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : node _T_2294 = eq(_T_2291, UInt<1>(0h0)) when _T_2294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175 node _T_2295 = and(io.in.a.ready, io.in.a.valid) node _T_2296 = and(_T_2295, a_first) when _T_2296 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2297 = eq(d_first, UInt<1>(0h0)) node _T_2298 = and(io.in.d.valid, _T_2297) when _T_2298 : node _T_2299 = eq(io.in.d.bits.opcode, opcode_1) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176 node _T_2303 = eq(io.in.d.bits.param, param_1) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177 node _T_2307 = eq(io.in.d.bits.size, size_1) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178 node _T_2311 = eq(io.in.d.bits.source, source_1) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179 node _T_2315 = eq(io.in.d.bits.sink, sink) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180 node _T_2319 = eq(io.in.d.bits.denied, denied) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181 node _T_2323 = and(io.in.d.ready, io.in.d.valid) node _T_2324 = and(_T_2323, d_first) when _T_2324 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2325 = eq(b_first, UInt<1>(0h0)) node _T_2326 = and(io.in.b.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.b.bits.opcode, opcode_2) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182 node _T_2331 = eq(io.in.b.bits.param, param_2) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183 node _T_2335 = eq(io.in.b.bits.size, size_2) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184 node _T_2339 = eq(io.in.b.bits.source, source_2) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185 node _T_2343 = eq(io.in.b.bits.address, address_1) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186 node _T_2347 = and(io.in.b.ready, io.in.b.valid) node _T_2348 = and(_T_2347, b_first) when _T_2348 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2349 = eq(c_first, UInt<1>(0h0)) node _T_2350 = and(io.in.c.valid, _T_2349) when _T_2350 : node _T_2351 = eq(io.in.c.bits.opcode, opcode_3) node _T_2352 = asUInt(reset) node _T_2353 = eq(_T_2352, UInt<1>(0h0)) when _T_2353 : node _T_2354 = eq(_T_2351, UInt<1>(0h0)) when _T_2354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187 node _T_2355 = eq(io.in.c.bits.param, param_3) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188 node _T_2359 = eq(io.in.c.bits.size, size_3) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189 node _T_2363 = eq(io.in.c.bits.source, source_3) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190 node _T_2367 = eq(io.in.c.bits.address, address_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191 node _T_2371 = and(io.in.c.ready, io.in.c.valid) node _T_2372 = and(_T_2371, c_first) when _T_2372 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<3> connect a_set, UInt<3>(0h0) wire a_set_wo_ready : UInt<3> connect a_set_wo_ready, UInt<3>(0h0) wire a_opcodes_set : UInt<12> connect a_opcodes_set, UInt<12>(0h0) wire a_sizes_set : UInt<24> connect a_sizes_set, UInt<24>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2373 = and(io.in.a.valid, a_first_1) node _T_2374 = and(_T_2373, UInt<1>(0h1)) when _T_2374 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2375 = and(io.in.a.ready, io.in.a.valid) node _T_2376 = and(_T_2375, a_first_1) node _T_2377 = and(_T_2376, UInt<1>(0h1)) when _T_2377 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2378 = dshr(inflight, io.in.a.bits.source) node _T_2379 = bits(_T_2378, 0, 0) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<3> connect d_clr, UInt<3>(0h0) wire d_clr_wo_ready : UInt<3> connect d_clr_wo_ready, UInt<3>(0h0) wire d_opcodes_clr : UInt<12> connect d_opcodes_clr, UInt<12>(0h0) wire d_sizes_clr : UInt<24> connect d_sizes_clr, UInt<24>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = and(io.in.d.valid, d_first_1) node _T_2385 = and(_T_2384, UInt<1>(0h1)) node _T_2386 = eq(d_release_ack, UInt<1>(0h0)) node _T_2387 = and(_T_2385, _T_2386) when _T_2387 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2388 = and(io.in.d.ready, io.in.d.valid) node _T_2389 = and(_T_2388, d_first_1) node _T_2390 = and(_T_2389, UInt<1>(0h1)) node _T_2391 = eq(d_release_ack, UInt<1>(0h0)) node _T_2392 = and(_T_2390, _T_2391) when _T_2392 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2393 = and(io.in.d.valid, d_first_1) node _T_2394 = and(_T_2393, UInt<1>(0h1)) node _T_2395 = eq(d_release_ack, UInt<1>(0h0)) node _T_2396 = and(_T_2394, _T_2395) when _T_2396 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2397 = dshr(inflight, io.in.d.bits.source) node _T_2398 = bits(_T_2397, 0, 0) node _T_2399 = or(_T_2398, same_cycle_resp) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2405 = or(_T_2403, _T_2404) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194 node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195 else : node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2415 = or(_T_2413, _T_2414) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196 node _T_2419 = eq(io.in.d.bits.size, a_size_lookup) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197 node _T_2423 = and(io.in.d.valid, d_first_1) node _T_2424 = and(_T_2423, a_first_1) node _T_2425 = and(_T_2424, io.in.a.valid) node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2427 = and(_T_2425, _T_2426) node _T_2428 = eq(d_release_ack, UInt<1>(0h0)) node _T_2429 = and(_T_2427, _T_2428) when _T_2429 : node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2431 = or(_T_2430, io.in.a.ready) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198 node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2436 = orr(a_set_wo_ready) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) node _T_2438 = or(_T_2435, _T_2437) node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(_T_2438, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_90 node _T_2442 = orr(inflight) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2445 = or(_T_2443, _T_2444) node _T_2446 = lt(watchdog, plusarg_reader.out) node _T_2447 = or(_T_2445, _T_2446) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2451 = and(io.in.a.ready, io.in.a.valid) node _T_2452 = and(io.in.d.ready, io.in.d.valid) node _T_2453 = or(_T_2451, _T_2452) when _T_2453 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0) regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0) regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<3> connect c_set, UInt<3>(0h0) wire c_set_wo_ready : UInt<3> connect c_set_wo_ready, UInt<3>(0h0) wire c_opcodes_set : UInt<12> connect c_opcodes_set, UInt<12>(0h0) wire c_sizes_set : UInt<24> connect c_sizes_set, UInt<24>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2454 = and(io.in.c.valid, c_first_1) node _T_2455 = bits(io.in.c.bits.opcode, 2, 2) node _T_2456 = bits(io.in.c.bits.opcode, 1, 1) node _T_2457 = and(_T_2455, _T_2456) node _T_2458 = and(_T_2454, _T_2457) when _T_2458 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2459 = and(io.in.c.ready, io.in.c.valid) node _T_2460 = and(_T_2459, c_first_1) node _T_2461 = bits(io.in.c.bits.opcode, 2, 2) node _T_2462 = bits(io.in.c.bits.opcode, 1, 1) node _T_2463 = and(_T_2461, _T_2462) node _T_2464 = and(_T_2460, _T_2463) when _T_2464 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2465 = dshr(inflight_1, io.in.c.bits.source) node _T_2466 = bits(_T_2465, 0, 0) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<3> connect d_clr_1, UInt<3>(0h0) wire d_clr_wo_ready_1 : UInt<3> connect d_clr_wo_ready_1, UInt<3>(0h0) wire d_opcodes_clr_1 : UInt<12> connect d_opcodes_clr_1, UInt<12>(0h0) wire d_sizes_clr_1 : UInt<24> connect d_sizes_clr_1, UInt<24>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2471 = and(io.in.d.valid, d_first_2) node _T_2472 = and(_T_2471, UInt<1>(0h1)) node _T_2473 = and(_T_2472, d_release_ack_1) when _T_2473 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_2) node _T_2476 = and(_T_2475, UInt<1>(0h1)) node _T_2477 = and(_T_2476, d_release_ack_1) when _T_2477 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2478 = and(io.in.d.valid, d_first_2) node _T_2479 = and(_T_2478, UInt<1>(0h1)) node _T_2480 = and(_T_2479, d_release_ack_1) when _T_2480 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2481 = dshr(inflight_1, io.in.d.bits.source) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = or(_T_2482, same_cycle_resp_1) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2488 = asUInt(reset) node _T_2489 = eq(_T_2488, UInt<1>(0h0)) when _T_2489 : node _T_2490 = eq(_T_2487, UInt<1>(0h0)) when _T_2490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203 else : node _T_2491 = eq(io.in.d.bits.size, c_size_lookup) node _T_2492 = asUInt(reset) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) when _T_2493 : node _T_2494 = eq(_T_2491, UInt<1>(0h0)) when _T_2494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204 node _T_2495 = and(io.in.d.valid, d_first_2) node _T_2496 = and(_T_2495, c_first_1) node _T_2497 = and(_T_2496, io.in.c.valid) node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2499 = and(_T_2497, _T_2498) node _T_2500 = and(_T_2499, d_release_ack_1) node _T_2501 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2502 = and(_T_2500, _T_2501) when _T_2502 : node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2504 = or(_T_2503, io.in.c.ready) node _T_2505 = asUInt(reset) node _T_2506 = eq(_T_2505, UInt<1>(0h0)) when _T_2506 : node _T_2507 = eq(_T_2504, UInt<1>(0h0)) when _T_2507 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205 node _T_2508 = orr(c_set_wo_ready) when _T_2508 : node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_91 node _T_2513 = orr(inflight_1) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2516 = or(_T_2514, _T_2515) node _T_2517 = lt(watchdog_1, plusarg_reader_1.out) node _T_2518 = or(_T_2516, _T_2517) node _T_2519 = asUInt(reset) node _T_2520 = eq(_T_2519, UInt<1>(0h0)) when _T_2520 : node _T_2521 = eq(_T_2518, UInt<1>(0h0)) when _T_2521 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2522 = and(io.in.c.ready, io.in.c.valid) node _T_2523 = and(io.in.d.ready, io.in.d.valid) node _T_2524 = or(_T_2522, _T_2523) when _T_2524 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2525 = and(io.in.d.ready, io.in.d.valid) node _T_2526 = and(_T_2525, d_first_3) node _T_2527 = bits(io.in.d.bits.opcode, 2, 2) node _T_2528 = bits(io.in.d.bits.opcode, 1, 1) node _T_2529 = eq(_T_2528, UInt<1>(0h0)) node _T_2530 = and(_T_2527, _T_2529) node _T_2531 = and(_T_2526, _T_2530) when _T_2531 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2532 = dshr(inflight_2, io.in.d.bits.sink) node _T_2533 = bits(_T_2532, 0, 0) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = asUInt(reset) node _T_2536 = eq(_T_2535, UInt<1>(0h0)) when _T_2536 : node _T_2537 = eq(_T_2534, UInt<1>(0h0)) when _T_2537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2538 = and(io.in.e.ready, io.in.e.valid) node _T_2539 = and(_T_2538, UInt<1>(0h1)) node _T_2540 = and(_T_2539, UInt<1>(0h1)) when _T_2540 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2541 = or(d_set, inflight_2) node _T_2542 = dshr(_T_2541, io.in.e.bits.sink) node _T_2543 = bits(_T_2542, 0, 0) node _T_2544 = asUInt(reset) node _T_2545 = eq(_T_2544, UInt<1>(0h0)) when _T_2545 : node _T_2546 = eq(_T_2543, UInt<1>(0h0)) when _T_2546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31] wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31] wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31] wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31] wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [2:0] inflight; // @[Monitor.scala:614:27] reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [23:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] a_set; // @[Monitor.scala:626:34] wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [23:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [2:0] d_clr; // @[Monitor.scala:664:34] wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [2:0] inflight_1; // @[Monitor.scala:726:35] reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [2:0] c_set; // @[Monitor.scala:738:34] wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [23:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [2:0] d_clr_1; // @[Monitor.scala:774:34] wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module PE_380 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_124 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_380( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_124 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN : output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 51, 51) node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0)) node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1) connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2 connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RecFNToRecFN( // @[RecFNToRecFN.scala:44:5] input [64:0] io_in, // @[RecFNToRecFN.scala:48:16] input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out, // @[RecFNToRecFN.scala:48:16] output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23] RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19] .io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46] .io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23] .io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23] .io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RecFNToRecFN.scala:72:19] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_2 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1
module BranchKillableQueue_2( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [39:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [7:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [39:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [3:0] out_uop_br_tag; // @[util.scala:506:17] wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [6:0] out_uop_rob_idx; // @[util.scala:506:17] wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [4:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [4:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [39:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [19:0] out_old_meta_tag; // @[util.scala:506:17] wire [7:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg valids_3; // @[util.scala:465:24] reg valids_4; // @[util.scala:465:24] reg valids_5; // @[util.scala:465:24] reg valids_6; // @[util.scala:465:24] reg valids_7; // @[util.scala:465:24] reg valids_8; // @[util.scala:465:24] reg valids_9; // @[util.scala:465:24] reg valids_10; // @[util.scala:465:24] reg valids_11; // @[util.scala:465:24] reg valids_12; // @[util.scala:465:24] reg valids_13; // @[util.scala:465:24] reg valids_14; // @[util.scala:465:24] reg valids_15; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [15:0] uops_0_br_mask; // @[util.scala:466:20] reg [3:0] uops_0_br_tag; // @[util.scala:466:20] reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [6:0] uops_0_rob_idx; // @[util.scala:466:20] reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [4:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [15:0] uops_1_br_mask; // @[util.scala:466:20] reg [3:0] uops_1_br_tag; // @[util.scala:466:20] reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [6:0] uops_1_rob_idx; // @[util.scala:466:20] reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [4:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [15:0] uops_2_br_mask; // @[util.scala:466:20] reg [3:0] uops_2_br_tag; // @[util.scala:466:20] reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [6:0] uops_2_rob_idx; // @[util.scala:466:20] reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [4:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [39:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [15:0] uops_3_br_mask; // @[util.scala:466:20] reg [3:0] uops_3_br_tag; // @[util.scala:466:20] reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [6:0] uops_3_rob_idx; // @[util.scala:466:20] reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [4:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [39:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [15:0] uops_4_br_mask; // @[util.scala:466:20] reg [3:0] uops_4_br_tag; // @[util.scala:466:20] reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [6:0] uops_4_rob_idx; // @[util.scala:466:20] reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [4:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [39:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [15:0] uops_5_br_mask; // @[util.scala:466:20] reg [3:0] uops_5_br_tag; // @[util.scala:466:20] reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [6:0] uops_5_rob_idx; // @[util.scala:466:20] reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [4:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [39:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [15:0] uops_6_br_mask; // @[util.scala:466:20] reg [3:0] uops_6_br_tag; // @[util.scala:466:20] reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [6:0] uops_6_rob_idx; // @[util.scala:466:20] reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [4:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [39:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [15:0] uops_7_br_mask; // @[util.scala:466:20] reg [3:0] uops_7_br_tag; // @[util.scala:466:20] reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [6:0] uops_7_rob_idx; // @[util.scala:466:20] reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [4:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [39:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [15:0] uops_8_br_mask; // @[util.scala:466:20] reg [3:0] uops_8_br_tag; // @[util.scala:466:20] reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [6:0] uops_8_rob_idx; // @[util.scala:466:20] reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [4:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [39:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [15:0] uops_9_br_mask; // @[util.scala:466:20] reg [3:0] uops_9_br_tag; // @[util.scala:466:20] reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [6:0] uops_9_rob_idx; // @[util.scala:466:20] reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [4:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [39:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [15:0] uops_10_br_mask; // @[util.scala:466:20] reg [3:0] uops_10_br_tag; // @[util.scala:466:20] reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [6:0] uops_10_rob_idx; // @[util.scala:466:20] reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [4:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [39:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [15:0] uops_11_br_mask; // @[util.scala:466:20] reg [3:0] uops_11_br_tag; // @[util.scala:466:20] reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [6:0] uops_11_rob_idx; // @[util.scala:466:20] reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [4:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [39:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [15:0] uops_12_br_mask; // @[util.scala:466:20] reg [3:0] uops_12_br_tag; // @[util.scala:466:20] reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [6:0] uops_12_rob_idx; // @[util.scala:466:20] reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [4:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [39:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [15:0] uops_13_br_mask; // @[util.scala:466:20] reg [3:0] uops_13_br_tag; // @[util.scala:466:20] reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [6:0] uops_13_rob_idx; // @[util.scala:466:20] reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [4:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [39:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [15:0] uops_14_br_mask; // @[util.scala:466:20] reg [3:0] uops_14_br_tag; // @[util.scala:466:20] reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [6:0] uops_14_rob_idx; // @[util.scala:466:20] reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [4:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [39:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [15:0] uops_15_br_mask; // @[util.scala:466:20] reg [3:0] uops_15_br_tag; // @[util.scala:466:20] reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [6:0] uops_15_rob_idx; // @[util.scala:466:20] reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [4:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}] wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32] wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}] wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:118:{51,59}] wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32] wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}] wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:118:{51,59}] wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32] wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}] wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:118:{51,59}] wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32] wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}] wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:118:{51,59}] wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32] wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}] wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:118:{51,59}] wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32] wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}] wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:118:{51,59}] wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32] wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}] wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:118:{51,59}] wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32] wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}] wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:118:{51,59}] wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32] wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}] wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:118:{51,59}] wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32] wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}] wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:118:{51,59}] wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32] wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}] wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:118:{51,59}] wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32] wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}] wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_15_T_1 = |_valids_15_T; // @[util.scala:118:{51,59}] wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32] wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}] wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0] out_uop_br_mask; // @[util.scala:506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x141 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_96 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_96( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_66 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_77 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_66( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_77 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_45 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_90 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_45 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0hc) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0hc)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_16 = eq(UInt<4>(0h9), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_91 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_45 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node _c_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node _c_T_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node out_channel_oh_0 = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _out_bundle_bits_out_virt_channel_T_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 1) node _out_bundle_bits_out_virt_channel_T_2 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_1, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_3 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_4 = or(_out_bundle_bits_out_virt_channel_T_2, _out_bundle_bits_out_virt_channel_T_3) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<1> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_4 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1
module IngressUnit_45( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hC; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hC; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLBusBypassBar : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} output io : { flip bypass : UInt<1>, pending : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_47 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in regreset in_reset : UInt<1>, clock, reset, UInt<1>(0h1) connect in_reset, UInt<1>(0h0) reg bypass_reg : UInt<1>, clock node bypass = mux(in_reset, io.bypass, bypass_reg) regreset flight : UInt<2>, clock, reset, UInt<2>(0h0) node _T = and(nodeIn.a.ready, nodeIn.a.valid) node _r_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 1, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 2) node _r_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node r_beats1_opdata = eq(_r_beats1_opdata_T, UInt<1>(0h0)) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node a_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node a_last = or(_r_last_T, _r_last_T_1) node r_3 = and(a_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(a_first, r_beats1, r_counter1) connect r_counter, _r_counter_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1 = and(_WIRE_1.ready, _WIRE_1.valid) node _r_beats1_decode_T_3 = dshl(UInt<2>(0h3), _WIRE_1.bits.size) node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 1, 0) node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4) node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 2) node _r_beats1_opdata_T_1 = bits(_WIRE_1.bits.opcode, 2, 2) node r_beats1_opdata_1 = eq(_r_beats1_opdata_T_1, UInt<1>(0h0)) node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0)) regreset r_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1)) node r_counter1_1 = tail(_r_counter1_T_1, 1) node b_first = eq(r_counter_1, UInt<1>(0h0)) node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1)) node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0)) node b_last = or(_r_last_T_2, _r_last_T_3) node r_3_1 = and(b_last, _T_1) node _r_count_T_1 = not(r_counter1_1) node r_4_1 = and(r_beats1_1, _r_count_T_1) when _T_1 : node _r_counter_T_1 = mux(b_first, r_beats1_1, r_counter1_1) connect r_counter_1, _r_counter_T_1 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_2 = and(_WIRE_3.ready, _WIRE_3.valid) node _r_beats1_decode_T_6 = dshl(UInt<2>(0h3), _WIRE_3.bits.size) node _r_beats1_decode_T_7 = bits(_r_beats1_decode_T_6, 1, 0) node _r_beats1_decode_T_8 = not(_r_beats1_decode_T_7) node r_beats1_decode_2 = shr(_r_beats1_decode_T_8, 2) node r_beats1_opdata_2 = bits(_WIRE_3.bits.opcode, 0, 0) node r_beats1_2 = mux(UInt<1>(0h0), r_beats1_decode_2, UInt<1>(0h0)) regreset r_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_2 = sub(r_counter_2, UInt<1>(0h1)) node r_counter1_2 = tail(_r_counter1_T_2, 1) node c_first = eq(r_counter_2, UInt<1>(0h0)) node _r_last_T_4 = eq(r_counter_2, UInt<1>(0h1)) node _r_last_T_5 = eq(r_beats1_2, UInt<1>(0h0)) node c_last = or(_r_last_T_4, _r_last_T_5) node r_3_2 = and(c_last, _T_2) node _r_count_T_2 = not(r_counter1_2) node r_4_2 = and(r_beats1_2, _r_count_T_2) when _T_2 : node _r_counter_T_2 = mux(c_first, r_beats1_2, r_counter1_2) connect r_counter_2, _r_counter_T_2 node _T_3 = and(nodeIn.d.ready, nodeIn.d.valid) node _r_beats1_decode_T_9 = dshl(UInt<2>(0h3), nodeIn.d.bits.size) node _r_beats1_decode_T_10 = bits(_r_beats1_decode_T_9, 1, 0) node _r_beats1_decode_T_11 = not(_r_beats1_decode_T_10) node r_beats1_decode_3 = shr(_r_beats1_decode_T_11, 2) node r_beats1_opdata_3 = bits(nodeIn.d.bits.opcode, 0, 0) node r_beats1_3 = mux(r_beats1_opdata_3, r_beats1_decode_3, UInt<1>(0h0)) regreset r_counter_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_3 = sub(r_counter_3, UInt<1>(0h1)) node r_counter1_3 = tail(_r_counter1_T_3, 1) node d_first = eq(r_counter_3, UInt<1>(0h0)) node _r_last_T_6 = eq(r_counter_3, UInt<1>(0h1)) node _r_last_T_7 = eq(r_beats1_3, UInt<1>(0h0)) node d_last = or(_r_last_T_6, _r_last_T_7) node r_3_3 = and(d_last, _T_3) node _r_count_T_3 = not(r_counter1_3) node r_4_3 = and(r_beats1_3, _r_count_T_3) when _T_3 : node _r_counter_T_3 = mux(d_first, r_beats1_3, r_counter1_3) connect r_counter_3, _r_counter_T_3 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_4 = and(_WIRE_5.ready, _WIRE_5.valid) regreset r_counter_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _r_counter1_T_4 = sub(r_counter_4, UInt<1>(0h1)) node r_counter1_4 = tail(_r_counter1_T_4, 1) node e_first = eq(r_counter_4, UInt<1>(0h0)) node _r_last_T_8 = eq(r_counter_4, UInt<1>(0h1)) node _r_last_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0)) node e_last = or(_r_last_T_8, _r_last_T_9) node r_3_4 = and(e_last, _T_4) node _r_count_T_4 = not(r_counter1_4) node r_4_4 = and(UInt<1>(0h0), _r_count_T_4) when _T_4 : node _r_counter_T_4 = mux(e_first, UInt<1>(0h0), r_counter1_4) connect r_counter_4, _r_counter_T_4 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.mask, UInt<4>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.mask, UInt<4>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<2>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_5 = bits(_WIRE_11.bits.opcode, 2, 2) node _T_6 = bits(_WIRE_11.bits.opcode, 1, 1) node c_request = and(_T_5, _T_6) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_7 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_8 = eq(_T_7, UInt<1>(0h0)) node _T_9 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_10 = eq(_T_9, UInt<1>(0h0)) node c_response = or(_T_8, _T_10) node _T_11 = bits(nodeIn.d.bits.opcode, 2, 2) node _T_12 = bits(nodeIn.d.bits.opcode, 1, 1) node _T_13 = eq(_T_12, UInt<1>(0h0)) node d_request = and(_T_11, _T_13) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_14.bits.sink, UInt<1>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _a_inc_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_inc_T_1 = and(_a_inc_T, a_first) node a_inc = and(_a_inc_T_1, UInt<1>(0h1)) wire _b_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_inc_WIRE.bits.data, UInt<32>(0h0) connect _b_inc_WIRE.bits.mask, UInt<4>(0h0) connect _b_inc_WIRE.bits.address, UInt<9>(0h0) connect _b_inc_WIRE.bits.source, UInt<1>(0h0) connect _b_inc_WIRE.bits.size, UInt<2>(0h0) connect _b_inc_WIRE.bits.param, UInt<2>(0h0) connect _b_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _b_inc_WIRE.valid, UInt<1>(0h0) connect _b_inc_WIRE.ready, UInt<1>(0h0) wire _b_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_inc_WIRE_1.bits, _b_inc_WIRE.bits connect _b_inc_WIRE_1.valid, _b_inc_WIRE.valid connect _b_inc_WIRE_1.ready, _b_inc_WIRE.ready node _b_inc_T = and(_b_inc_WIRE_1.ready, _b_inc_WIRE_1.valid) node _b_inc_T_1 = and(_b_inc_T, b_first) node b_inc = and(_b_inc_T_1, UInt<1>(0h1)) wire _c_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_inc_WIRE.bits.data, UInt<32>(0h0) connect _c_inc_WIRE.bits.address, UInt<9>(0h0) connect _c_inc_WIRE.bits.source, UInt<1>(0h0) connect _c_inc_WIRE.bits.size, UInt<2>(0h0) connect _c_inc_WIRE.bits.param, UInt<3>(0h0) connect _c_inc_WIRE.bits.opcode, UInt<3>(0h0) connect _c_inc_WIRE.valid, UInt<1>(0h0) connect _c_inc_WIRE.ready, UInt<1>(0h0) wire _c_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_inc_WIRE_1.bits, _c_inc_WIRE.bits connect _c_inc_WIRE_1.valid, _c_inc_WIRE.valid connect _c_inc_WIRE_1.ready, _c_inc_WIRE.ready node _c_inc_T = and(_c_inc_WIRE_1.ready, _c_inc_WIRE_1.valid) node _c_inc_T_1 = and(_c_inc_T, c_first) node c_inc = and(_c_inc_T_1, c_request) node _d_inc_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_inc_T_1 = and(_d_inc_T, d_first) node d_inc = and(_d_inc_T_1, d_request) wire _e_inc_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE.bits.sink, UInt<1>(0h0) connect _e_inc_WIRE.valid, UInt<1>(0h0) connect _e_inc_WIRE.ready, UInt<1>(0h0) wire _e_inc_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_inc_WIRE_1.bits, _e_inc_WIRE.bits connect _e_inc_WIRE_1.valid, _e_inc_WIRE.valid connect _e_inc_WIRE_1.ready, _e_inc_WIRE.ready node _e_inc_T = and(_e_inc_WIRE_1.ready, _e_inc_WIRE_1.valid) node _e_inc_T_1 = and(_e_inc_T, e_first) node e_inc = and(_e_inc_T_1, UInt<1>(0h0)) node inc = cat(a_inc, d_inc) node _a_dec_T = and(nodeIn.a.ready, nodeIn.a.valid) node _a_dec_T_1 = and(_a_dec_T, a_last) node a_dec = and(_a_dec_T_1, UInt<1>(0h0)) wire _b_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _b_dec_WIRE.bits.data, UInt<32>(0h0) connect _b_dec_WIRE.bits.mask, UInt<4>(0h0) connect _b_dec_WIRE.bits.address, UInt<9>(0h0) connect _b_dec_WIRE.bits.source, UInt<1>(0h0) connect _b_dec_WIRE.bits.size, UInt<2>(0h0) connect _b_dec_WIRE.bits.param, UInt<2>(0h0) connect _b_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _b_dec_WIRE.valid, UInt<1>(0h0) connect _b_dec_WIRE.ready, UInt<1>(0h0) wire _b_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _b_dec_WIRE_1.bits, _b_dec_WIRE.bits connect _b_dec_WIRE_1.valid, _b_dec_WIRE.valid connect _b_dec_WIRE_1.ready, _b_dec_WIRE.ready node _b_dec_T = and(_b_dec_WIRE_1.ready, _b_dec_WIRE_1.valid) node _b_dec_T_1 = and(_b_dec_T, b_last) node b_dec = and(_b_dec_T_1, UInt<1>(0h0)) wire _c_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_dec_WIRE.bits.data, UInt<32>(0h0) connect _c_dec_WIRE.bits.address, UInt<9>(0h0) connect _c_dec_WIRE.bits.source, UInt<1>(0h0) connect _c_dec_WIRE.bits.size, UInt<2>(0h0) connect _c_dec_WIRE.bits.param, UInt<3>(0h0) connect _c_dec_WIRE.bits.opcode, UInt<3>(0h0) connect _c_dec_WIRE.valid, UInt<1>(0h0) connect _c_dec_WIRE.ready, UInt<1>(0h0) wire _c_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_dec_WIRE_1.bits, _c_dec_WIRE.bits connect _c_dec_WIRE_1.valid, _c_dec_WIRE.valid connect _c_dec_WIRE_1.ready, _c_dec_WIRE.ready node _c_dec_T = and(_c_dec_WIRE_1.ready, _c_dec_WIRE_1.valid) node _c_dec_T_1 = and(_c_dec_T, c_last) node c_dec = and(_c_dec_T_1, c_response) node _d_dec_T = and(nodeIn.d.ready, nodeIn.d.valid) node _d_dec_T_1 = and(_d_dec_T, d_last) node d_dec = and(_d_dec_T_1, UInt<1>(0h1)) wire _e_dec_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE.bits.sink, UInt<1>(0h0) connect _e_dec_WIRE.valid, UInt<1>(0h0) connect _e_dec_WIRE.ready, UInt<1>(0h0) wire _e_dec_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _e_dec_WIRE_1.bits, _e_dec_WIRE.bits connect _e_dec_WIRE_1.valid, _e_dec_WIRE.valid connect _e_dec_WIRE_1.ready, _e_dec_WIRE.ready node _e_dec_T = and(_e_dec_WIRE_1.ready, _e_dec_WIRE_1.valid) node _e_dec_T_1 = and(_e_dec_T, e_last) node e_dec = and(_e_dec_T_1, UInt<1>(0h1)) node dec = cat(a_dec, d_dec) node _next_flight_T = bits(inc, 0, 0) node _next_flight_T_1 = bits(inc, 1, 1) node _next_flight_T_2 = add(_next_flight_T, _next_flight_T_1) node _next_flight_T_3 = bits(_next_flight_T_2, 1, 0) node _next_flight_T_4 = add(flight, _next_flight_T_3) node _next_flight_T_5 = tail(_next_flight_T_4, 1) node _next_flight_T_6 = bits(dec, 0, 0) node _next_flight_T_7 = bits(dec, 1, 1) node _next_flight_T_8 = add(_next_flight_T_6, _next_flight_T_7) node _next_flight_T_9 = bits(_next_flight_T_8, 1, 0) node _next_flight_T_10 = sub(_next_flight_T_5, _next_flight_T_9) node next_flight = tail(_next_flight_T_10, 1) connect flight, next_flight node _io_pending_T = gt(flight, UInt<1>(0h0)) connect io.pending, _io_pending_T node _T_14 = eq(next_flight, UInt<1>(0h0)) node _T_15 = or(in_reset, _T_14) when _T_15 : connect bypass_reg, io.bypass node _stall_T = neq(bypass, io.bypass) node _stall_T_1 = and(nodeIn.a.ready, nodeIn.a.valid) node _stall_beats1_decode_T = dshl(UInt<2>(0h3), nodeIn.a.bits.size) node _stall_beats1_decode_T_1 = bits(_stall_beats1_decode_T, 1, 0) node _stall_beats1_decode_T_2 = not(_stall_beats1_decode_T_1) node stall_beats1_decode = shr(_stall_beats1_decode_T_2, 2) node _stall_beats1_opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node stall_beats1_opdata = eq(_stall_beats1_opdata_T, UInt<1>(0h0)) node stall_beats1 = mux(stall_beats1_opdata, stall_beats1_decode, UInt<1>(0h0)) regreset stall_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _stall_counter1_T = sub(stall_counter, UInt<1>(0h1)) node stall_counter1 = tail(_stall_counter1_T, 1) node stall_first = eq(stall_counter, UInt<1>(0h0)) node _stall_last_T = eq(stall_counter, UInt<1>(0h1)) node _stall_last_T_1 = eq(stall_beats1, UInt<1>(0h0)) node stall_last = or(_stall_last_T, _stall_last_T_1) node stall_done = and(stall_last, _stall_T_1) node _stall_count_T = not(stall_counter1) node stall_count = and(stall_beats1, _stall_count_T) when _stall_T_1 : node _stall_counter_T = mux(stall_first, stall_beats1, stall_counter1) connect stall_counter, _stall_counter_T node stall = and(_stall_T, stall_first) node _nodeOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(_nodeOut_a_valid_T, nodeIn.a.valid) node _nodeOut_a_valid_T_2 = and(_nodeOut_a_valid_T_1, bypass) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 node _nodeOut_a_valid_T_3 = eq(stall, UInt<1>(0h0)) node _nodeOut_a_valid_T_4 = and(_nodeOut_a_valid_T_3, nodeIn.a.valid) node _nodeOut_a_valid_T_5 = eq(bypass, UInt<1>(0h0)) node _nodeOut_a_valid_T_6 = and(_nodeOut_a_valid_T_4, _nodeOut_a_valid_T_5) connect x1_nodeOut.a.valid, _nodeOut_a_valid_T_6 node _nodeIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _nodeIn_a_ready_T_1 = mux(bypass, nodeOut.a.ready, x1_nodeOut.a.ready) node _nodeIn_a_ready_T_2 = and(_nodeIn_a_ready_T, _nodeIn_a_ready_T_1) connect nodeIn.a.ready, _nodeIn_a_ready_T_2 connect nodeOut.a.bits, nodeIn.a.bits connect x1_nodeOut.a.bits, nodeIn.a.bits node _nodeOut_d_ready_T = and(nodeIn.d.ready, bypass) connect nodeOut.d.ready, _nodeOut_d_ready_T node _nodeOut_d_ready_T_1 = eq(bypass, UInt<1>(0h0)) node _nodeOut_d_ready_T_2 = and(nodeIn.d.ready, _nodeOut_d_ready_T_1) connect x1_nodeOut.d.ready, _nodeOut_d_ready_T_2 node _nodeIn_d_valid_T = mux(bypass, nodeOut.d.valid, x1_nodeOut.d.valid) connect nodeIn.d.valid, _nodeIn_d_valid_T wire nodeIn_d_bits_out : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out, nodeIn.d.bits connect nodeIn_d_bits_out, nodeOut.d.bits wire nodeIn_d_bits_out_1 : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>} connect nodeIn_d_bits_out_1, nodeIn.d.bits connect nodeIn_d_bits_out_1, x1_nodeOut.d.bits node _nodeIn_d_bits_T = mux(bypass, nodeIn_d_bits_out, nodeIn_d_bits_out_1) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_T.corrupt connect nodeIn.d.bits.data, _nodeIn_d_bits_T.data connect nodeIn.d.bits.denied, _nodeIn_d_bits_T.denied connect nodeIn.d.bits.sink, _nodeIn_d_bits_T.sink connect nodeIn.d.bits.source, _nodeIn_d_bits_T.source connect nodeIn.d.bits.size, _nodeIn_d_bits_T.size connect nodeIn.d.bits.param, _nodeIn_d_bits_T.param connect nodeIn.d.bits.opcode, _nodeIn_d_bits_T.opcode wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.mask, UInt<4>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.mask, UInt<4>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.ready, UInt<1>(0h1) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<32>(0h0) connect _WIRE_26.bits.address, UInt<128>(0h0) connect _WIRE_26.bits.source, UInt<1>(0h0) connect _WIRE_26.bits.size, UInt<2>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.valid, UInt<1>(0h0) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_28.bits.sink, UInt<1>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<32>(0h0) connect _WIRE_30.bits.mask, UInt<4>(0h0) connect _WIRE_30.bits.address, UInt<9>(0h0) connect _WIRE_30.bits.source, UInt<1>(0h0) connect _WIRE_30.bits.size, UInt<2>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<32>(0h0) connect _WIRE_32.bits.address, UInt<9>(0h0) connect _WIRE_32.bits.source, UInt<1>(0h0) connect _WIRE_32.bits.size, UInt<2>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) extmodule plusarg_reader_96 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_97 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = |flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset | next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_47 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_105 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 7, 0) node _source_ok_T = shr(io.in.a.bits.source, 8) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<8>(0h9f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits = bits(_uncommonBits_T, 7, 0) node _T_4 = shr(io.in.a.bits.source, 8) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<8>(0h9f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 7, 0) node _T_24 = shr(io.in.a.bits.source, 8) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<8>(0h9f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 7, 0) node _T_86 = shr(io.in.a.bits.source, 8) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<8>(0h9f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 7, 0) node _T_152 = shr(io.in.a.bits.source, 8) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<8>(0h9f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 7, 0) node _T_199 = shr(io.in.a.bits.source, 8) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<8>(0h9f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 7, 0) node _T_240 = shr(io.in.a.bits.source, 8) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<8>(0h9f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 7, 0) node _T_283 = shr(io.in.a.bits.source, 8) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<8>(0h9f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 7, 0) node _T_321 = shr(io.in.a.bits.source, 8) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<8>(0h9f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 7, 0) node _T_359 = shr(io.in.a.bits.source, 8) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<8>(0h9f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 7, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 8) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<8>(0h9f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes : UInt<640>, clock, reset, UInt<640>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<160> connect a_set, UInt<160>(0h0) wire a_set_wo_ready : UInt<160> connect a_set_wo_ready, UInt<160>(0h0) wire a_opcodes_set : UInt<640> connect a_opcodes_set, UInt<640>(0h0) wire a_sizes_set : UInt<640> connect a_sizes_set, UInt<640>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<160> connect d_clr, UInt<160>(0h0) wire d_clr_wo_ready : UInt<160> connect d_clr_wo_ready, UInt<160>(0h0) wire d_opcodes_clr : UInt<640> connect d_opcodes_clr, UInt<640>(0h0) wire d_sizes_clr : UInt<640> connect d_sizes_clr, UInt<640>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_211 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<160>, clock, reset, UInt<160>(0h0) regreset inflight_opcodes_1 : UInt<640>, clock, reset, UInt<640>(0h0) regreset inflight_sizes_1 : UInt<640>, clock, reset, UInt<640>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<160> connect c_set, UInt<160>(0h0) wire c_set_wo_ready : UInt<160> connect c_set_wo_ready, UInt<160>(0h0) wire c_opcodes_set : UInt<640> connect c_opcodes_set, UInt<640>(0h0) wire c_sizes_set : UInt<640> connect c_sizes_set, UInt<640>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<160> connect d_clr_1, UInt<160>(0h0) wire d_clr_wo_ready_1 : UInt<160> connect d_clr_wo_ready_1, UInt<160>(0h0) wire d_opcodes_clr_1 : UInt<640> connect d_opcodes_clr_1, UInt<640>(0h0) wire d_sizes_clr_1 : UInt<640> connect d_sizes_clr_1, UInt<640>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_212 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_105( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2049:0] _c_sizes_set_T_1 = 2050'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [639:0] c_opcodes_set = 640'h0; // @[Monitor.scala:740:34] wire [639:0] c_sizes_set = 640'h0; // @[Monitor.scala:741:34] wire [159:0] c_set = 160'h0; // @[Monitor.scala:738:34] wire [159:0] c_set_wo_ready = 160'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hA0; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [159:0] inflight; // @[Monitor.scala:614:27] reg [639:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [639:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [159:0] a_set; // @[Monitor.scala:626:34] wire [159:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [639:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [639:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [639:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [639:0] _a_opcode_lookup_T_6 = {636'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [639:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [639:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [639:0] _a_size_lookup_T_6 = {636'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [639:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[639:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2049:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[639:0] : 640'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [159:0] d_clr; // @[Monitor.scala:664:34] wire [159:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [639:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [639:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[639:0] : 640'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [159:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [159:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [159:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [639:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [639:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [639:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [639:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [639:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [639:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [159:0] inflight_1; // @[Monitor.scala:726:35] wire [159:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [639:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [639:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [639:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [639:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [639:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [639:0] _c_opcode_lookup_T_6 = {636'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [639:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[639:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [639:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [639:0] _c_size_lookup_T_6 = {636'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [639:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[639:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [159:0] d_clr_1; // @[Monitor.scala:774:34] wire [159:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [639:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [639:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[159:0] : 160'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[639:0] : 640'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [159:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [159:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [639:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [639:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [639:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [639:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_22 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_EntryData_22( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_82 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_82( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_531 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_531( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLReadQueue : input clock : Clock input reset : Reset output auto : { flip mem_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip stream_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<0>, keep : UInt<0>, last : UInt<1>, id : UInt<0>, dest : UInt<0>, user : UInt<0>}}} wire streamNodeIn : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<0>, keep : UInt<0>, last : UInt<1>, id : UInt<0>, dest : UInt<0>, user : UInt<0>}} invalidate streamNodeIn.bits.user invalidate streamNodeIn.bits.dest invalidate streamNodeIn.bits.id invalidate streamNodeIn.bits.last invalidate streamNodeIn.bits.keep invalidate streamNodeIn.bits.strb invalidate streamNodeIn.bits.data invalidate streamNodeIn.valid invalidate streamNodeIn.ready wire memIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate memIn.d.bits.corrupt invalidate memIn.d.bits.data invalidate memIn.d.bits.denied invalidate memIn.d.bits.sink invalidate memIn.d.bits.source invalidate memIn.d.bits.size invalidate memIn.d.bits.param invalidate memIn.d.bits.opcode invalidate memIn.d.valid invalidate memIn.d.ready invalidate memIn.a.bits.corrupt invalidate memIn.a.bits.data invalidate memIn.a.bits.mask invalidate memIn.a.bits.address invalidate memIn.a.bits.source invalidate memIn.a.bits.size invalidate memIn.a.bits.param invalidate memIn.a.bits.opcode invalidate memIn.a.valid invalidate memIn.a.ready inst monitor of TLMonitor_56 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, memIn.d.bits.corrupt connect monitor.io.in.d.bits.data, memIn.d.bits.data connect monitor.io.in.d.bits.denied, memIn.d.bits.denied connect monitor.io.in.d.bits.sink, memIn.d.bits.sink connect monitor.io.in.d.bits.source, memIn.d.bits.source connect monitor.io.in.d.bits.size, memIn.d.bits.size connect monitor.io.in.d.bits.param, memIn.d.bits.param connect monitor.io.in.d.bits.opcode, memIn.d.bits.opcode connect monitor.io.in.d.valid, memIn.d.valid connect monitor.io.in.d.ready, memIn.d.ready connect monitor.io.in.a.bits.corrupt, memIn.a.bits.corrupt connect monitor.io.in.a.bits.data, memIn.a.bits.data connect monitor.io.in.a.bits.mask, memIn.a.bits.mask connect monitor.io.in.a.bits.address, memIn.a.bits.address connect monitor.io.in.a.bits.source, memIn.a.bits.source connect monitor.io.in.a.bits.size, memIn.a.bits.size connect monitor.io.in.a.bits.param, memIn.a.bits.param connect monitor.io.in.a.bits.opcode, memIn.a.bits.opcode connect monitor.io.in.a.valid, memIn.a.valid connect monitor.io.in.a.ready, memIn.a.ready connect streamNodeIn, auto.stream_in connect memIn, auto.mem_in wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt} inst queue of Queue8_UInt64_1 connect queue.clock, clock connect queue.reset, reset connect queue.io.enq.valid, streamNodeIn.valid connect queue.io.enq.bits, streamNodeIn.bits.data connect streamNodeIn.ready, queue.io.enq.ready connect out.valid, queue.io.deq.valid connect out.bits, queue.io.deq.bits connect queue.io.deq.ready, out.ready wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<5>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(memIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(memIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, memIn.a.bits.data connect in.bits.mask, memIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, memIn.a.bits.source connect in.bits.extra.tlrr_extra.size, memIn.a.bits.size wire out_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<5>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<5>(0h1)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<5>(0h0)) node _out_T_1 = eq(out_bindex, UInt<5>(0h0)) node _out_T_2 = eq(out_findex, UInt<5>(0h0)) node _out_T_3 = eq(out_bindex, UInt<5>(0h0)) wire out_rivalid : UInt<1>[2] wire out_wivalid : UInt<1>[2] wire out_roready : UInt<1>[2] wire out_woready : UInt<1>[2] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 63, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 63, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 63, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 63, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) connect out.ready, out_f_roready node _out_T_4 = bits(out_front.bits.data, 63, 0) node _out_T_5 = eq(out_rimask, UInt<1>(0h0)) node _out_T_6 = eq(out_wimask, UInt<1>(0h0)) node _out_T_7 = eq(out_romask, UInt<1>(0h0)) node _out_T_8 = or(out.valid, _out_T_7) node _out_T_9 = eq(out_womask, UInt<1>(0h0)) node _out_T_10 = or(out.bits, UInt<64>(0h0)) node _out_T_11 = bits(_out_T_10, 63, 0) node _out_rimask_T_1 = bits(out_frontMask, 63, 0) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 63, 0) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 63, 0) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 63, 0) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_12 = bits(out_front.bits.data, 63, 0) node _out_T_13 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_14 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_15 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_16 = eq(out_womask_1, UInt<1>(0h0)) node _out_T_17 = or(queue.io.count, UInt<64>(0h0)) node _out_T_18 = bits(_out_T_17, 63, 0) node out_iindex = bits(out_front.bits.index, 0, 0) node _out_iindex_T = bits(out_front.bits.index, 1, 1) node _out_iindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_3 = bits(out_front.bits.index, 4, 4) node out_oindex = bits(out_front.bits.index, 0, 0) node _out_oindex_T = bits(out_front.bits.index, 1, 1) node _out_oindex_T_1 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_2 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_3 = bits(out_front.bits.index, 4, 4) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) node _out_rifireMux_T_10 = geq(out_iindex, UInt<2>(0h2)) wire _out_rifireMux_WIRE : UInt<1>[2] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 node out_rifireMux = mux(_out_rifireMux_T_10, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) node _out_wifireMux_T_11 = geq(out_iindex, UInt<2>(0h2)) wire _out_wifireMux_WIRE : UInt<1>[2] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 node out_wifireMux = mux(_out_wifireMux_T_11, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out_1.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) node out_rofireMux_all = and(_out_rofireMux_T_3, _out_T_8) connect out_rofireMux_out, _out_T_8 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) node _out_rofireMux_T_10 = geq(out_oindex, UInt<2>(0h2)) wire _out_rofireMux_WIRE : UInt<1>[2] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 node out_rofireMux = mux(_out_rofireMux_T_10, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out_1.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) node _out_wofireMux_T_11 = geq(out_oindex, UInt<2>(0h2)) wire _out_wofireMux_WIRE : UInt<1>[2] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 node out_wofireMux = mux(_out_wofireMux_T_11, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out_1.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out_1.valid, _out_out_valid_T connect out_1.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE : UInt<1>[2] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<2>(0h2)) wire _out_out_bits_data_WIRE_1 : UInt<64>[2] connect _out_out_bits_data_WIRE_1[0], _out_T_11 connect _out_out_bits_data_WIRE_1[1], _out_T_18 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out_1.bits.data, _out_out_bits_data_T_4 connect out_1.bits.extra, out_front.bits.extra connect in.valid, memIn.a.valid connect memIn.a.ready, in.ready connect memIn.d.valid, out_1.valid connect out_1.ready, memIn.d.ready wire memIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect memIn_d_bits_d.opcode, UInt<1>(0h0) connect memIn_d_bits_d.param, UInt<1>(0h0) connect memIn_d_bits_d.size, out_1.bits.extra.tlrr_extra.size connect memIn_d_bits_d.source, out_1.bits.extra.tlrr_extra.source connect memIn_d_bits_d.sink, UInt<1>(0h0) connect memIn_d_bits_d.denied, UInt<1>(0h0) invalidate memIn_d_bits_d.data connect memIn_d_bits_d.corrupt, UInt<1>(0h0) connect memIn.d.bits.corrupt, memIn_d_bits_d.corrupt connect memIn.d.bits.data, memIn_d_bits_d.data connect memIn.d.bits.denied, memIn_d_bits_d.denied connect memIn.d.bits.sink, memIn_d_bits_d.sink connect memIn.d.bits.source, memIn_d_bits_d.source connect memIn.d.bits.size, memIn_d_bits_d.size connect memIn.d.bits.param, memIn_d_bits_d.param connect memIn.d.bits.opcode, memIn_d_bits_d.opcode connect memIn.d.bits.data, out_1.bits.data node _memIn_d_bits_opcode_T = mux(out_1.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect memIn.d.bits.opcode, _memIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_117 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_118 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLReadQueue( // @[DspBlocks.scala:102:25] input clock, // @[DspBlocks.scala:102:25] input reset, // @[DspBlocks.scala:102:25] output auto_mem_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_mem_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_mem_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_mem_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_mem_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_mem_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_mem_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_mem_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_mem_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_mem_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_mem_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_mem_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_mem_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_mem_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_mem_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_stream_in_ready, // @[LazyModuleImp.scala:107:25] input auto_stream_in_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_stream_in_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_backSel_0; // @[RegisterRouter.scala:87:24] wire _queue_io_deq_valid; // @[DspBlocks.scala:112:23] wire [63:0] _queue_io_deq_bits; // @[DspBlocks.scala:112:23] wire [3:0] _queue_io_count; // @[DspBlocks.scala:112:23] wire in_bits_read = auto_mem_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_3 = auto_mem_in_a_bits_address[7:4] == 4'h0; // @[RegisterRouter.scala:75:19, :87:24] wire [63:0] out_backMask = {{8{auto_mem_in_a_bits_mask[7]}}, {8{auto_mem_in_a_bits_mask[6]}}, {8{auto_mem_in_a_bits_mask[5]}}, {8{auto_mem_in_a_bits_mask[4]}}, {8{auto_mem_in_a_bits_mask[3]}}, {8{auto_mem_in_a_bits_mask[2]}}, {8{auto_mem_in_a_bits_mask[1]}}, {8{auto_mem_in_a_bits_mask[0]}}}; // @[RegisterRouter.scala:87:24] assign out_backSel_0 = ~(auto_mem_in_a_bits_address[3]); // @[RegisterRouter.scala:87:24] wire out_oready = ~in_bits_read | auto_mem_in_a_bits_address[3] | (|{_queue_io_deq_valid | ~(|out_backMask), auto_mem_in_a_bits_address[7:4]}); // @[MuxLiteral.scala:49:10] wire out_front_ready = auto_mem_in_d_ready & out_oready; // @[MuxLiteral.scala:49:10] wire out_1_valid = auto_mem_in_a_valid & out_oready; // @[MuxLiteral.scala:49:10] wire [2:0] memIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_56 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (out_front_ready), // @[RegisterRouter.scala:87:24] .io_in_a_valid (auto_mem_in_a_valid), .io_in_a_bits_opcode (auto_mem_in_a_bits_opcode), .io_in_a_bits_param (auto_mem_in_a_bits_param), .io_in_a_bits_size (auto_mem_in_a_bits_size), .io_in_a_bits_source (auto_mem_in_a_bits_source), .io_in_a_bits_address (auto_mem_in_a_bits_address), .io_in_a_bits_mask (auto_mem_in_a_bits_mask), .io_in_a_bits_corrupt (auto_mem_in_a_bits_corrupt), .io_in_d_ready (auto_mem_in_d_ready), .io_in_d_valid (out_1_valid), // @[RegisterRouter.scala:87:24] .io_in_d_bits_opcode (memIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_mem_in_a_bits_size), .io_in_d_bits_source (auto_mem_in_a_bits_source) ); // @[Nodes.scala:27:25] Queue8_UInt64 queue ( // @[DspBlocks.scala:112:23] .clock (clock), .reset (reset), .io_enq_ready (auto_stream_in_ready), .io_enq_valid (auto_stream_in_valid), .io_enq_bits (auto_stream_in_bits_data), .io_deq_ready (auto_mem_in_a_valid & auto_mem_in_d_ready & in_bits_read & out_backSel_0 & _out_T_3 & (|out_backMask)), // @[RegisterRouter.scala:74:36, :87:24] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits (_queue_io_deq_bits), .io_count (_queue_io_count) ); // @[DspBlocks.scala:112:23] assign auto_mem_in_a_ready = out_front_ready; // @[RegisterRouter.scala:87:24] assign auto_mem_in_d_valid = out_1_valid; // @[RegisterRouter.scala:87:24] assign auto_mem_in_d_bits_opcode = memIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_mem_in_d_bits_size = auto_mem_in_a_bits_size; // @[DspBlocks.scala:102:25] assign auto_mem_in_d_bits_source = auto_mem_in_a_bits_source; // @[DspBlocks.scala:102:25] assign auto_mem_in_d_bits_data = _out_T_3 ? (auto_mem_in_a_bits_address[3] ? {60'h0, _queue_io_count} : _queue_io_deq_bits) : 64'h0; // @[MuxLiteral.scala:49:10] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<13>(0h1000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<27>(0h4000000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<13>(0h1000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<13>(0h1000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<27>(0h4000000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<13>(0h1000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<13>(0h1000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<27>(0h4000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<13>(0h1000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<13>(0h1000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<27>(0h4000000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<13>(0h1000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<27>(0h4000000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<13>(0h1000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<27>(0h4000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<13>(0h1000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<13>(0h1000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<27>(0h4000000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<14>(0h2000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_871 = cvt(_T_870) node _T_872 = and(_T_871, asSInt(UInt<18>(0h2f000))) node _T_873 = asSInt(_T_872) node _T_874 = eq(_T_873, asSInt(UInt<1>(0h0))) node _T_875 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_876 = cvt(_T_875) node _T_877 = and(_T_876, asSInt(UInt<17>(0h10000))) node _T_878 = asSInt(_T_877) node _T_879 = eq(_T_878, asSInt(UInt<1>(0h0))) node _T_880 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<13>(0h1000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_886 = cvt(_T_885) node _T_887 = and(_T_886, asSInt(UInt<27>(0h4000000))) node _T_888 = asSInt(_T_887) node _T_889 = eq(_T_888, asSInt(UInt<1>(0h0))) node _T_890 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_891 = cvt(_T_890) node _T_892 = and(_T_891, asSInt(UInt<13>(0h1000))) node _T_893 = asSInt(_T_892) node _T_894 = eq(_T_893, asSInt(UInt<1>(0h0))) node _T_895 = or(_T_864, _T_869) node _T_896 = or(_T_895, _T_874) node _T_897 = or(_T_896, _T_879) node _T_898 = or(_T_897, _T_884) node _T_899 = or(_T_898, _T_889) node _T_900 = or(_T_899, _T_894) node _T_901 = and(_T_859, _T_900) node _T_902 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_903 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_904 = cvt(_T_903) node _T_905 = and(_T_904, asSInt(UInt<17>(0h10000))) node _T_906 = asSInt(_T_905) node _T_907 = eq(_T_906, asSInt(UInt<1>(0h0))) node _T_908 = and(_T_902, _T_907) node _T_909 = or(UInt<1>(0h0), _T_901) node _T_910 = or(_T_909, _T_908) node _T_911 = and(_T_855, _T_910) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_911, UInt<1>(0h1), "") : assert_36 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(is_aligned, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_921 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_921, UInt<1>(0h1), "") : assert_39 node _T_925 = eq(io.in.a.bits.mask, mask) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_925, UInt<1>(0h1), "") : assert_40 node _T_929 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_929 : node _T_930 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_931 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_932 = and(_T_930, _T_931) node _T_933 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<1>(0h0)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_28) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<1>(0h1)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_29) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<2>(0h2)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_30) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<2>(0h3)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_31) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_933, _T_939) node _T_962 = or(_T_961, _T_945) node _T_963 = or(_T_962, _T_951) node _T_964 = or(_T_963, _T_957) node _T_965 = or(_T_964, _T_958) node _T_966 = or(_T_965, _T_959) node _T_967 = or(_T_966, _T_960) node _T_968 = and(_T_932, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_972 = and(_T_970, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<14>(0h2000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<13>(0h1000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<18>(0h2f000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<17>(0h10000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<27>(0h4000000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = or(_T_978, _T_983) node _T_1010 = or(_T_1009, _T_988) node _T_1011 = or(_T_1010, _T_993) node _T_1012 = or(_T_1011, _T_998) node _T_1013 = or(_T_1012, _T_1003) node _T_1014 = or(_T_1013, _T_1008) node _T_1015 = and(_T_973, _T_1014) node _T_1016 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1017 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<17>(0h10000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = and(_T_1016, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_1015) node _T_1024 = or(_T_1023, _T_1022) node _T_1025 = and(_T_969, _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_41 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(is_aligned, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1035 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_44 node _T_1039 = eq(io.in.a.bits.mask, mask) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_45 node _T_1043 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1043 : node _T_1044 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1045 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h1)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h2)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h3)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1075 = or(_T_1047, _T_1053) node _T_1076 = or(_T_1075, _T_1059) node _T_1077 = or(_T_1076, _T_1065) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) node _T_1081 = or(_T_1080, _T_1074) node _T_1082 = and(_T_1046, _T_1081) node _T_1083 = or(UInt<1>(0h0), _T_1082) node _T_1084 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1085 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = and(_T_1087, _T_1092) node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<14>(0h2000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<17>(0h10000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1106 = cvt(_T_1105) node _T_1107 = and(_T_1106, asSInt(UInt<18>(0h2f000))) node _T_1108 = asSInt(_T_1107) node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0))) node _T_1110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1111 = cvt(_T_1110) node _T_1112 = and(_T_1111, asSInt(UInt<17>(0h10000))) node _T_1113 = asSInt(_T_1112) node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1116 = cvt(_T_1115) node _T_1117 = and(_T_1116, asSInt(UInt<13>(0h1000))) node _T_1118 = asSInt(_T_1117) node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0))) node _T_1120 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1121 = cvt(_T_1120) node _T_1122 = and(_T_1121, asSInt(UInt<27>(0h4000000))) node _T_1123 = asSInt(_T_1122) node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<13>(0h1000))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1099, _T_1104) node _T_1131 = or(_T_1130, _T_1109) node _T_1132 = or(_T_1131, _T_1114) node _T_1133 = or(_T_1132, _T_1119) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = or(_T_1134, _T_1129) node _T_1136 = and(_T_1094, _T_1135) node _T_1137 = or(UInt<1>(0h0), _T_1093) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = and(_T_1083, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_46 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(source_ok, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(is_aligned, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1149 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_49 node _T_1153 = eq(io.in.a.bits.mask, mask) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_50 node _T_1157 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1161 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1165 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1165 : node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok_1, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1169 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_54 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_55 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_56 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_57 node _T_1185 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1185 : node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(source_ok_1, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(sink_ok, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1192 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_60 node _T_1196 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_61 node _T_1200 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_62 node _T_1204 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_63 node _T_1208 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1209 = or(UInt<1>(0h1), _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_64 node _T_1213 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1213 : node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(source_ok_1, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(sink_ok, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1220 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_67 node _T_1224 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_68 node _T_1228 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_69 node _T_1232 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1233 = or(_T_1232, io.in.d.bits.corrupt) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_70 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_71 node _T_1242 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1242 : node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(source_ok_1, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1246 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_73 node _T_1250 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_74 node _T_1254 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1255 = or(UInt<1>(0h1), _T_1254) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_75 node _T_1259 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1259 : node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(source_ok_1, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1263 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_77 node _T_1267 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1268 = or(_T_1267, io.in.d.bits.corrupt) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_78 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h1), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_79 node _T_1277 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_81 node _T_1285 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_82 node _T_1289 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1290 = or(UInt<1>(0h1), _T_1289) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1294 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1298 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1302 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1306 = eq(a_first, UInt<1>(0h0)) node _T_1307 = and(io.in.a.valid, _T_1306) when _T_1307 : node _T_1308 = eq(io.in.a.bits.opcode, opcode) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_87 node _T_1312 = eq(io.in.a.bits.param, param) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_88 node _T_1316 = eq(io.in.a.bits.size, size) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_89 node _T_1320 = eq(io.in.a.bits.source, source) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_90 node _T_1324 = eq(io.in.a.bits.address, address) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_91 node _T_1328 = and(io.in.a.ready, io.in.a.valid) node _T_1329 = and(_T_1328, a_first) when _T_1329 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1330 = eq(d_first, UInt<1>(0h0)) node _T_1331 = and(io.in.d.valid, _T_1330) when _T_1331 : node _T_1332 = eq(io.in.d.bits.opcode, opcode_1) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.d.bits.param, param_1) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_93 node _T_1340 = eq(io.in.d.bits.size, size_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_94 node _T_1344 = eq(io.in.d.bits.source, source_1) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_95 node _T_1348 = eq(io.in.d.bits.sink, sink) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_96 node _T_1352 = eq(io.in.d.bits.denied, denied) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_97 node _T_1356 = and(io.in.d.ready, io.in.d.valid) node _T_1357 = and(_T_1356, d_first) when _T_1357 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1358 = and(io.in.a.valid, a_first_1) node _T_1359 = and(_T_1358, UInt<1>(0h1)) when _T_1359 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1360 = and(io.in.a.ready, io.in.a.valid) node _T_1361 = and(_T_1360, a_first_1) node _T_1362 = and(_T_1361, UInt<1>(0h1)) when _T_1362 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1363 = dshr(inflight, io.in.a.bits.source) node _T_1364 = bits(_T_1363, 0, 0) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1369 = and(io.in.d.valid, d_first_1) node _T_1370 = and(_T_1369, UInt<1>(0h1)) node _T_1371 = eq(d_release_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1373 = and(io.in.d.ready, io.in.d.valid) node _T_1374 = and(_T_1373, d_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) node _T_1376 = eq(d_release_ack, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1378 = and(io.in.d.valid, d_first_1) node _T_1379 = and(_T_1378, UInt<1>(0h1)) node _T_1380 = eq(d_release_ack, UInt<1>(0h0)) node _T_1381 = and(_T_1379, _T_1380) when _T_1381 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1382 = dshr(inflight, io.in.d.bits.source) node _T_1383 = bits(_T_1382, 0, 0) node _T_1384 = or(_T_1383, same_cycle_resp) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1388 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1389 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_100 node _T_1394 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_101 else : node _T_1398 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1399 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_102 node _T_1404 = eq(io.in.d.bits.size, a_size_lookup) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_103 node _T_1408 = and(io.in.d.valid, d_first_1) node _T_1409 = and(_T_1408, a_first_1) node _T_1410 = and(_T_1409, io.in.a.valid) node _T_1411 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1412 = and(_T_1410, _T_1411) node _T_1413 = eq(d_release_ack, UInt<1>(0h0)) node _T_1414 = and(_T_1412, _T_1413) when _T_1414 : node _T_1415 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1416 = or(_T_1415, io.in.a.ready) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_104 node _T_1420 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1421 = orr(a_set_wo_ready) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) node _T_1423 = or(_T_1420, _T_1422) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_40 node _T_1427 = orr(inflight) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) node _T_1429 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1430 = or(_T_1428, _T_1429) node _T_1431 = lt(watchdog, plusarg_reader.out) node _T_1432 = or(_T_1430, _T_1431) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1436 = and(io.in.a.ready, io.in.a.valid) node _T_1437 = and(io.in.d.ready, io.in.d.valid) node _T_1438 = or(_T_1436, _T_1437) when _T_1438 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1439 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1440 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1441 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1442 = and(_T_1440, _T_1441) node _T_1443 = and(_T_1439, _T_1442) when _T_1443 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1444 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1445 = and(_T_1444, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1446 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1447 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1448 = and(_T_1446, _T_1447) node _T_1449 = and(_T_1445, _T_1448) when _T_1449 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1450 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1451 = bits(_T_1450, 0, 0) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1456 = and(io.in.d.valid, d_first_2) node _T_1457 = and(_T_1456, UInt<1>(0h1)) node _T_1458 = and(_T_1457, d_release_ack_1) when _T_1458 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1459 = and(io.in.d.ready, io.in.d.valid) node _T_1460 = and(_T_1459, d_first_2) node _T_1461 = and(_T_1460, UInt<1>(0h1)) node _T_1462 = and(_T_1461, d_release_ack_1) when _T_1462 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1463 = and(io.in.d.valid, d_first_2) node _T_1464 = and(_T_1463, UInt<1>(0h1)) node _T_1465 = and(_T_1464, d_release_ack_1) when _T_1465 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1466 = dshr(inflight_1, io.in.d.bits.source) node _T_1467 = bits(_T_1466, 0, 0) node _T_1468 = or(_T_1467, same_cycle_resp_1) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1472 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_109 else : node _T_1476 = eq(io.in.d.bits.size, c_size_lookup) node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(_T_1476, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1476, UInt<1>(0h1), "") : assert_110 node _T_1480 = and(io.in.d.valid, d_first_2) node _T_1481 = and(_T_1480, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1482 = and(_T_1481, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1483 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1484 = and(_T_1482, _T_1483) node _T_1485 = and(_T_1484, d_release_ack_1) node _T_1486 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1487 = and(_T_1485, _T_1486) when _T_1487 : node _T_1488 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1489 = or(_T_1488, _WIRE_23.ready) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_111 node _T_1493 = orr(c_set_wo_ready) when _T_1493 : node _T_1494 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_41 node _T_1498 = orr(inflight_1) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) node _T_1500 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1501 = or(_T_1499, _T_1500) node _T_1502 = lt(watchdog_1, plusarg_reader_1.out) node _T_1503 = or(_T_1501, _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1507 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1508 = and(io.in.d.ready, io.in.d.valid) node _T_1509 = or(_T_1507, _T_1508) when _T_1509 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1436 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1436; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1436; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1509 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1509; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1509; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1509; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1362 = _T_1436 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1362 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1362 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1362 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1362 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1362 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1408 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1408 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1377 = _T_1509 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1377 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1377 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1377 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1480 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1480 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1462 = _T_1509 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1462 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1462 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1462 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_86 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_86 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_86( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_86 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_11, _T_24) node _T_97 = and(_T_96, _T_37) node _T_98 = and(_T_97, _T_50) node _T_99 = and(_T_98, _T_63) node _T_100 = and(_T_99, _T_71) node _T_101 = and(_T_100, _T_79) node _T_102 = and(_T_101, _T_87) node _T_103 = and(_T_102, _T_95) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_103, UInt<1>(0h1), "") : assert_1 node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_107 : node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_118 = shr(io.in.a.bits.source, 2) node _T_119 = eq(_T_118, UInt<1>(0h1)) node _T_120 = leq(UInt<1>(0h0), uncommonBits_5) node _T_121 = and(_T_119, _T_120) node _T_122 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_123 = and(_T_121, _T_122) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_124 = shr(io.in.a.bits.source, 2) node _T_125 = eq(_T_124, UInt<2>(0h2)) node _T_126 = leq(UInt<1>(0h0), uncommonBits_6) node _T_127 = and(_T_125, _T_126) node _T_128 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_129 = and(_T_127, _T_128) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_130 = shr(io.in.a.bits.source, 2) node _T_131 = eq(_T_130, UInt<2>(0h3)) node _T_132 = leq(UInt<1>(0h0), uncommonBits_7) node _T_133 = and(_T_131, _T_132) node _T_134 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_140 = or(_T_111, _T_117) node _T_141 = or(_T_140, _T_123) node _T_142 = or(_T_141, _T_129) node _T_143 = or(_T_142, _T_135) node _T_144 = or(_T_143, _T_136) node _T_145 = or(_T_144, _T_137) node _T_146 = or(_T_145, _T_138) node _T_147 = or(_T_146, _T_139) node _T_148 = and(_T_110, _T_147) node _T_149 = or(UInt<1>(0h0), _T_148) node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_151 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = and(_T_150, _T_155) node _T_157 = or(UInt<1>(0h0), _T_156) node _T_158 = and(_T_149, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_158, UInt<1>(0h1), "") : assert_2 node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_8) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h1)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_9) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_10) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h3)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_11) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_162 connect _WIRE[1], _T_168 connect _WIRE[2], _T_174 connect _WIRE[3], _T_180 connect _WIRE[4], _T_186 connect _WIRE[5], _T_187 connect _WIRE[6], _T_188 connect _WIRE[7], _T_189 connect _WIRE[8], _T_190 node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = mux(_WIRE[5], _T_191, UInt<1>(0h0)) node _T_198 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = or(_T_192, _T_193) node _T_202 = or(_T_201, _T_194) node _T_203 = or(_T_202, _T_195) node _T_204 = or(_T_203, _T_196) node _T_205 = or(_T_204, _T_197) node _T_206 = or(_T_205, _T_198) node _T_207 = or(_T_206, _T_199) node _T_208 = or(_T_207, _T_200) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_208 node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_211 = and(_T_209, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = and(_T_212, _T_217) node _T_219 = or(UInt<1>(0h0), _T_218) node _T_220 = and(_WIRE_1, _T_219) node _T_221 = asUInt(reset) node _T_222 = eq(_T_221, UInt<1>(0h0)) when _T_222 : node _T_223 = eq(_T_220, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_220, UInt<1>(0h1), "") : assert_3 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(source_ok, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_227, UInt<1>(0h1), "") : assert_5 node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(is_aligned, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_234, UInt<1>(0h1), "") : assert_7 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_239, UInt<1>(0h1), "") : assert_8 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_243, UInt<1>(0h1), "") : assert_9 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_247 : node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_252 = shr(io.in.a.bits.source, 2) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = leq(UInt<1>(0h0), uncommonBits_12) node _T_255 = and(_T_253, _T_254) node _T_256 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_257 = and(_T_255, _T_256) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_258 = shr(io.in.a.bits.source, 2) node _T_259 = eq(_T_258, UInt<1>(0h1)) node _T_260 = leq(UInt<1>(0h0), uncommonBits_13) node _T_261 = and(_T_259, _T_260) node _T_262 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_263 = and(_T_261, _T_262) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_264 = shr(io.in.a.bits.source, 2) node _T_265 = eq(_T_264, UInt<2>(0h2)) node _T_266 = leq(UInt<1>(0h0), uncommonBits_14) node _T_267 = and(_T_265, _T_266) node _T_268 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_269 = and(_T_267, _T_268) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_270 = shr(io.in.a.bits.source, 2) node _T_271 = eq(_T_270, UInt<2>(0h3)) node _T_272 = leq(UInt<1>(0h0), uncommonBits_15) node _T_273 = and(_T_271, _T_272) node _T_274 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_275 = and(_T_273, _T_274) node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_280 = or(_T_251, _T_257) node _T_281 = or(_T_280, _T_263) node _T_282 = or(_T_281, _T_269) node _T_283 = or(_T_282, _T_275) node _T_284 = or(_T_283, _T_276) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_278) node _T_287 = or(_T_286, _T_279) node _T_288 = and(_T_250, _T_287) node _T_289 = or(UInt<1>(0h0), _T_288) node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = and(_T_290, _T_295) node _T_297 = or(UInt<1>(0h0), _T_296) node _T_298 = and(_T_289, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_303 = shr(io.in.a.bits.source, 2) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_16) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_308 = and(_T_306, _T_307) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_309 = shr(io.in.a.bits.source, 2) node _T_310 = eq(_T_309, UInt<1>(0h1)) node _T_311 = leq(UInt<1>(0h0), uncommonBits_17) node _T_312 = and(_T_310, _T_311) node _T_313 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_315 = shr(io.in.a.bits.source, 2) node _T_316 = eq(_T_315, UInt<2>(0h2)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_18) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_321 = shr(io.in.a.bits.source, 2) node _T_322 = eq(_T_321, UInt<2>(0h3)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_19) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_302 connect _WIRE_2[1], _T_308 connect _WIRE_2[2], _T_314 connect _WIRE_2[3], _T_320 connect _WIRE_2[4], _T_326 connect _WIRE_2[5], _T_327 connect _WIRE_2[6], _T_328 connect _WIRE_2[7], _T_329 connect _WIRE_2[8], _T_330 node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE_2[5], _T_331, UInt<1>(0h0)) node _T_338 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = or(_T_332, _T_333) node _T_342 = or(_T_341, _T_334) node _T_343 = or(_T_342, _T_335) node _T_344 = or(_T_343, _T_336) node _T_345 = or(_T_344, _T_337) node _T_346 = or(_T_345, _T_338) node _T_347 = or(_T_346, _T_339) node _T_348 = or(_T_347, _T_340) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_348 node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_351 = and(_T_349, _T_350) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = and(_T_352, _T_357) node _T_359 = or(UInt<1>(0h0), _T_358) node _T_360 = and(_WIRE_3, _T_359) node _T_361 = asUInt(reset) node _T_362 = eq(_T_361, UInt<1>(0h0)) when _T_362 : node _T_363 = eq(_T_360, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_360, UInt<1>(0h1), "") : assert_11 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(source_ok, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_367, UInt<1>(0h1), "") : assert_13 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(is_aligned, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_374, UInt<1>(0h1), "") : assert_15 node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_378, UInt<1>(0h1), "") : assert_16 node _T_382 = not(io.in.a.bits.mask) node _T_383 = eq(_T_382, UInt<1>(0h0)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_383, UInt<1>(0h1), "") : assert_17 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_387, UInt<1>(0h1), "") : assert_18 node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_391 : node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_20) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_21) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h2)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_22) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_414 = shr(io.in.a.bits.source, 2) node _T_415 = eq(_T_414, UInt<2>(0h3)) node _T_416 = leq(UInt<1>(0h0), uncommonBits_23) node _T_417 = and(_T_415, _T_416) node _T_418 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_424 = or(_T_395, _T_401) node _T_425 = or(_T_424, _T_407) node _T_426 = or(_T_425, _T_413) node _T_427 = or(_T_426, _T_419) node _T_428 = or(_T_427, _T_420) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_422) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_394, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_433, UInt<1>(0h1), "") : assert_19 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = asUInt(reset) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(_T_447, UInt<1>(0h0)) when _T_450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_447, UInt<1>(0h1), "") : assert_20 node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(source_ok, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(is_aligned, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_457, UInt<1>(0h1), "") : assert_23 node _T_461 = eq(io.in.a.bits.mask, mask) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_461, UInt<1>(0h1), "") : assert_24 node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_465, UInt<1>(0h1), "") : assert_25 node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_469 : node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_472 = and(_T_470, _T_471) node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_474 = shr(io.in.a.bits.source, 2) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = leq(UInt<1>(0h0), uncommonBits_24) node _T_477 = and(_T_475, _T_476) node _T_478 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h1)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_25) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_486 = shr(io.in.a.bits.source, 2) node _T_487 = eq(_T_486, UInt<2>(0h2)) node _T_488 = leq(UInt<1>(0h0), uncommonBits_26) node _T_489 = and(_T_487, _T_488) node _T_490 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_491 = and(_T_489, _T_490) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_492 = shr(io.in.a.bits.source, 2) node _T_493 = eq(_T_492, UInt<2>(0h3)) node _T_494 = leq(UInt<1>(0h0), uncommonBits_27) node _T_495 = and(_T_493, _T_494) node _T_496 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_497 = and(_T_495, _T_496) node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_502 = or(_T_473, _T_479) node _T_503 = or(_T_502, _T_485) node _T_504 = or(_T_503, _T_491) node _T_505 = or(_T_504, _T_497) node _T_506 = or(_T_505, _T_498) node _T_507 = or(_T_506, _T_499) node _T_508 = or(_T_507, _T_500) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_472, _T_509) node _T_511 = or(UInt<1>(0h0), _T_510) node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_514 = and(_T_512, _T_513) node _T_515 = or(UInt<1>(0h0), _T_514) node _T_516 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = and(_T_515, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = and(_T_511, _T_522) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_523, UInt<1>(0h1), "") : assert_26 node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(source_ok, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(is_aligned, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_533, UInt<1>(0h1), "") : assert_29 node _T_537 = eq(io.in.a.bits.mask, mask) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_537, UInt<1>(0h1), "") : assert_30 node _T_541 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_541 : node _T_542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_543 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<1>(0h0)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_28) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<1>(0h1)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_29) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_558 = shr(io.in.a.bits.source, 2) node _T_559 = eq(_T_558, UInt<2>(0h2)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_30) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_563 = and(_T_561, _T_562) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_564 = shr(io.in.a.bits.source, 2) node _T_565 = eq(_T_564, UInt<2>(0h3)) node _T_566 = leq(UInt<1>(0h0), uncommonBits_31) node _T_567 = and(_T_565, _T_566) node _T_568 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_569 = and(_T_567, _T_568) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_573 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_574 = or(_T_545, _T_551) node _T_575 = or(_T_574, _T_557) node _T_576 = or(_T_575, _T_563) node _T_577 = or(_T_576, _T_569) node _T_578 = or(_T_577, _T_570) node _T_579 = or(_T_578, _T_571) node _T_580 = or(_T_579, _T_572) node _T_581 = or(_T_580, _T_573) node _T_582 = and(_T_544, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_585 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_586 = and(_T_584, _T_585) node _T_587 = or(UInt<1>(0h0), _T_586) node _T_588 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_583, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_595, UInt<1>(0h1), "") : assert_31 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_605 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_605, UInt<1>(0h1), "") : assert_34 node _T_609 = not(mask) node _T_610 = and(io.in.a.bits.mask, _T_609) node _T_611 = eq(_T_610, UInt<1>(0h0)) node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_T_611, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_611, UInt<1>(0h1), "") : assert_35 node _T_615 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_615 : node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_620 = shr(io.in.a.bits.source, 2) node _T_621 = eq(_T_620, UInt<1>(0h0)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_32) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_625 = and(_T_623, _T_624) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_626 = shr(io.in.a.bits.source, 2) node _T_627 = eq(_T_626, UInt<1>(0h1)) node _T_628 = leq(UInt<1>(0h0), uncommonBits_33) node _T_629 = and(_T_627, _T_628) node _T_630 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_631 = and(_T_629, _T_630) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_632 = shr(io.in.a.bits.source, 2) node _T_633 = eq(_T_632, UInt<2>(0h2)) node _T_634 = leq(UInt<1>(0h0), uncommonBits_34) node _T_635 = and(_T_633, _T_634) node _T_636 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_637 = and(_T_635, _T_636) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_638 = shr(io.in.a.bits.source, 2) node _T_639 = eq(_T_638, UInt<2>(0h3)) node _T_640 = leq(UInt<1>(0h0), uncommonBits_35) node _T_641 = and(_T_639, _T_640) node _T_642 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_648 = or(_T_619, _T_625) node _T_649 = or(_T_648, _T_631) node _T_650 = or(_T_649, _T_637) node _T_651 = or(_T_650, _T_643) node _T_652 = or(_T_651, _T_644) node _T_653 = or(_T_652, _T_645) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = and(_T_618, _T_655) node _T_657 = or(UInt<1>(0h0), _T_656) node _T_658 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_659 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_657, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_689 = shr(io.in.a.bits.source, 2) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_36) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_695 = shr(io.in.a.bits.source, 2) node _T_696 = eq(_T_695, UInt<1>(0h1)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_37) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<2>(0h2)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_38) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<2>(0h3)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_39) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_716 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_717 = or(_T_688, _T_694) node _T_718 = or(_T_717, _T_700) node _T_719 = or(_T_718, _T_706) node _T_720 = or(_T_719, _T_712) node _T_721 = or(_T_720, _T_713) node _T_722 = or(_T_721, _T_714) node _T_723 = or(_T_722, _T_715) node _T_724 = or(_T_723, _T_716) node _T_725 = and(_T_687, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = and(_T_727, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_735, UInt<1>(0h1), "") : assert_41 node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(source_ok, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(is_aligned, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_745 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_745, UInt<1>(0h1), "") : assert_44 node _T_749 = eq(io.in.a.bits.mask, mask) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_749, UInt<1>(0h1), "") : assert_45 node _T_753 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_753 : node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_756 = and(_T_754, _T_755) node _T_757 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_758 = shr(io.in.a.bits.source, 2) node _T_759 = eq(_T_758, UInt<1>(0h0)) node _T_760 = leq(UInt<1>(0h0), uncommonBits_40) node _T_761 = and(_T_759, _T_760) node _T_762 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_763 = and(_T_761, _T_762) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_764 = shr(io.in.a.bits.source, 2) node _T_765 = eq(_T_764, UInt<1>(0h1)) node _T_766 = leq(UInt<1>(0h0), uncommonBits_41) node _T_767 = and(_T_765, _T_766) node _T_768 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_769 = and(_T_767, _T_768) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<2>(0h2)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_42) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<2>(0h3)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_43) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_786 = or(_T_757, _T_763) node _T_787 = or(_T_786, _T_769) node _T_788 = or(_T_787, _T_775) node _T_789 = or(_T_788, _T_781) node _T_790 = or(_T_789, _T_782) node _T_791 = or(_T_790, _T_783) node _T_792 = or(_T_791, _T_784) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_756, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_804, UInt<1>(0h1), "") : assert_46 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_814 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_814, UInt<1>(0h1), "") : assert_49 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_818, UInt<1>(0h1), "") : assert_50 node _T_822 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_822, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_826 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_826, UInt<1>(0h1), "") : assert_52 node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_37 = shr(io.in.d.bits.source, 2) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_43 = shr(io.in.d.bits.source, 2) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 2) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 2) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_36 connect _source_ok_WIRE_1[1], _source_ok_T_42 connect _source_ok_WIRE_1[2], _source_ok_T_48 connect _source_ok_WIRE_1[3], _source_ok_T_54 connect _source_ok_WIRE_1[4], _source_ok_T_60 connect _source_ok_WIRE_1[5], _source_ok_T_61 connect _source_ok_WIRE_1[6], _source_ok_T_62 connect _source_ok_WIRE_1[7], _source_ok_T_63 connect _source_ok_WIRE_1[8], _source_ok_T_64 node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok_1, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_834 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_834, UInt<1>(0h1), "") : assert_54 node _T_838 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_838, UInt<1>(0h1), "") : assert_55 node _T_842 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_842, UInt<1>(0h1), "") : assert_56 node _T_846 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_846, UInt<1>(0h1), "") : assert_57 node _T_850 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_850 : node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(source_ok_1, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(sink_ok, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_857 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_857, UInt<1>(0h1), "") : assert_60 node _T_861 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_861, UInt<1>(0h1), "") : assert_61 node _T_865 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_865, UInt<1>(0h1), "") : assert_62 node _T_869 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_869, UInt<1>(0h1), "") : assert_63 node _T_873 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_874 = or(UInt<1>(0h0), _T_873) node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(_T_874, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_874, UInt<1>(0h1), "") : assert_64 node _T_878 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_878 : node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(source_ok_1, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(sink_ok, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_885 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_885, UInt<1>(0h1), "") : assert_67 node _T_889 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(_T_889, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_889, UInt<1>(0h1), "") : assert_68 node _T_893 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_893, UInt<1>(0h1), "") : assert_69 node _T_897 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_898 = or(_T_897, io.in.d.bits.corrupt) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_898, UInt<1>(0h1), "") : assert_70 node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_903 = or(UInt<1>(0h0), _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_903, UInt<1>(0h1), "") : assert_71 node _T_907 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_907 : node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(source_ok_1, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_911 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_911, UInt<1>(0h1), "") : assert_73 node _T_915 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_915, UInt<1>(0h1), "") : assert_74 node _T_919 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_920, UInt<1>(0h1), "") : assert_75 node _T_924 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_924 : node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(source_ok_1, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_928 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_928, UInt<1>(0h1), "") : assert_77 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(_T_932, io.in.d.bits.corrupt) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_933, UInt<1>(0h1), "") : assert_78 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_938, UInt<1>(0h1), "") : assert_79 node _T_942 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_946 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_946, UInt<1>(0h1), "") : assert_81 node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_950, UInt<1>(0h1), "") : assert_82 node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_955 = or(UInt<1>(0h0), _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_955, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_959 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_959, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_963 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_963, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_967 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_967, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_971 = eq(a_first, UInt<1>(0h0)) node _T_972 = and(io.in.a.valid, _T_971) when _T_972 : node _T_973 = eq(io.in.a.bits.opcode, opcode) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_973, UInt<1>(0h1), "") : assert_87 node _T_977 = eq(io.in.a.bits.param, param) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_977, UInt<1>(0h1), "") : assert_88 node _T_981 = eq(io.in.a.bits.size, size) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_981, UInt<1>(0h1), "") : assert_89 node _T_985 = eq(io.in.a.bits.source, source) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_985, UInt<1>(0h1), "") : assert_90 node _T_989 = eq(io.in.a.bits.address, address) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_989, UInt<1>(0h1), "") : assert_91 node _T_993 = and(io.in.a.ready, io.in.a.valid) node _T_994 = and(_T_993, a_first) when _T_994 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_995 = eq(d_first, UInt<1>(0h0)) node _T_996 = and(io.in.d.valid, _T_995) when _T_996 : node _T_997 = eq(io.in.d.bits.opcode, opcode_1) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_997, UInt<1>(0h1), "") : assert_92 node _T_1001 = eq(io.in.d.bits.param, param_1) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_93 node _T_1005 = eq(io.in.d.bits.size, size_1) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_94 node _T_1009 = eq(io.in.d.bits.source, source_1) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_95 node _T_1013 = eq(io.in.d.bits.sink, sink) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_96 node _T_1017 = eq(io.in.d.bits.denied, denied) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_97 node _T_1021 = and(io.in.d.ready, io.in.d.valid) node _T_1022 = and(_T_1021, d_first) when _T_1022 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1023 = and(io.in.a.valid, a_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) when _T_1024 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1025 = and(io.in.a.ready, io.in.a.valid) node _T_1026 = and(_T_1025, a_first_1) node _T_1027 = and(_T_1026, UInt<1>(0h1)) when _T_1027 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1028 = dshr(inflight, io.in.a.bits.source) node _T_1029 = bits(_T_1028, 0, 0) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1034 = and(io.in.d.valid, d_first_1) node _T_1035 = and(_T_1034, UInt<1>(0h1)) node _T_1036 = eq(d_release_ack, UInt<1>(0h0)) node _T_1037 = and(_T_1035, _T_1036) when _T_1037 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1038 = and(io.in.d.ready, io.in.d.valid) node _T_1039 = and(_T_1038, d_first_1) node _T_1040 = and(_T_1039, UInt<1>(0h1)) node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) node _T_1042 = and(_T_1040, _T_1041) when _T_1042 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1043 = and(io.in.d.valid, d_first_1) node _T_1044 = and(_T_1043, UInt<1>(0h1)) node _T_1045 = eq(d_release_ack, UInt<1>(0h0)) node _T_1046 = and(_T_1044, _T_1045) when _T_1046 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1047 = dshr(inflight, io.in.d.bits.source) node _T_1048 = bits(_T_1047, 0, 0) node _T_1049 = or(_T_1048, same_cycle_resp) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1053 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1054 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1055 = or(_T_1053, _T_1054) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_100 node _T_1059 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_101 else : node _T_1063 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1064 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1065 = or(_T_1063, _T_1064) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_102 node _T_1069 = eq(io.in.d.bits.size, a_size_lookup) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_103 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, a_first_1) node _T_1075 = and(_T_1074, io.in.a.valid) node _T_1076 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(d_release_ack, UInt<1>(0h0)) node _T_1079 = and(_T_1077, _T_1078) when _T_1079 : node _T_1080 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.a.ready) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_119 node _T_1085 = orr(inflight) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) node _T_1087 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1088 = or(_T_1086, _T_1087) node _T_1089 = lt(watchdog, plusarg_reader.out) node _T_1090 = or(_T_1088, _T_1089) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1094 = and(io.in.a.ready, io.in.a.valid) node _T_1095 = and(io.in.d.ready, io.in.d.valid) node _T_1096 = or(_T_1094, _T_1095) when _T_1096 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1097 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1098 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1099 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = and(_T_1097, _T_1100) when _T_1101 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1102 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1103 = and(_T_1102, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1104 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1105 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = and(_T_1103, _T_1106) when _T_1107 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1108 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1109 = bits(_T_1108, 0, 0) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1114 = and(io.in.d.valid, d_first_2) node _T_1115 = and(_T_1114, UInt<1>(0h1)) node _T_1116 = and(_T_1115, d_release_ack_1) when _T_1116 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1117 = and(io.in.d.ready, io.in.d.valid) node _T_1118 = and(_T_1117, d_first_2) node _T_1119 = and(_T_1118, UInt<1>(0h1)) node _T_1120 = and(_T_1119, d_release_ack_1) when _T_1120 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1121 = and(io.in.d.valid, d_first_2) node _T_1122 = and(_T_1121, UInt<1>(0h1)) node _T_1123 = and(_T_1122, d_release_ack_1) when _T_1123 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1124 = dshr(inflight_1, io.in.d.bits.source) node _T_1125 = bits(_T_1124, 0, 0) node _T_1126 = or(_T_1125, same_cycle_resp_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1130 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_108 else : node _T_1134 = eq(io.in.d.bits.size, c_size_lookup) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_109 node _T_1138 = and(io.in.d.valid, d_first_2) node _T_1139 = and(_T_1138, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1140 = and(_T_1139, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1141 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, d_release_ack_1) node _T_1144 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1145 = and(_T_1143, _T_1144) when _T_1145 : node _T_1146 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1147 = or(_T_1146, _WIRE_27.ready) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_120 node _T_1151 = orr(inflight_1) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) node _T_1153 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1154 = or(_T_1152, _T_1153) node _T_1155 = lt(watchdog_1, plusarg_reader_1.out) node _T_1156 = or(_T_1154, _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1160 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1161 = and(io.in.d.ready, io.in.d.valid) node _T_1162 = or(_T_1160, _T_1161) when _T_1162 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_58( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1094 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1094; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1094; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1162 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1162; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1162; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1027 = _T_1094 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1027 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1027 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1027 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1027 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1027 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1073 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1073 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1042 = _T_1162 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1042 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1042 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1042 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1138 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1138 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1120 = _T_1162 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1120 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1120 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1120 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RegisterFileSynthesizable_1 : input clock : Clock input reset : Reset output io : { read_ports : { flip addr : UInt<7>, data : UInt<64>}[8], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<64>}}[4]} cmem regfile : UInt<64> [100] wire read_data : UInt<64>[8] reg read_addrs_0 : UInt, clock connect read_addrs_0, io.read_ports[0].addr reg read_addrs_1 : UInt, clock connect read_addrs_1, io.read_ports[1].addr reg read_addrs_2 : UInt, clock connect read_addrs_2, io.read_ports[2].addr reg read_addrs_3 : UInt, clock connect read_addrs_3, io.read_ports[3].addr reg read_addrs_4 : UInt, clock connect read_addrs_4, io.read_ports[4].addr reg read_addrs_5 : UInt, clock connect read_addrs_5, io.read_ports[5].addr reg read_addrs_6 : UInt, clock connect read_addrs_6, io.read_ports[6].addr reg read_addrs_7 : UInt, clock connect read_addrs_7, io.read_ports[7].addr node _read_data_0_T = or(read_addrs_0, UInt<7>(0h0)) node _read_data_0_T_1 = bits(_read_data_0_T, 6, 0) infer mport read_data_0_MPORT = regfile[_read_data_0_T_1], clock connect read_data[0], read_data_0_MPORT node _read_data_1_T = or(read_addrs_1, UInt<7>(0h0)) node _read_data_1_T_1 = bits(_read_data_1_T, 6, 0) infer mport read_data_1_MPORT = regfile[_read_data_1_T_1], clock connect read_data[1], read_data_1_MPORT node _read_data_2_T = or(read_addrs_2, UInt<7>(0h0)) node _read_data_2_T_1 = bits(_read_data_2_T, 6, 0) infer mport read_data_2_MPORT = regfile[_read_data_2_T_1], clock connect read_data[2], read_data_2_MPORT node _read_data_3_T = or(read_addrs_3, UInt<7>(0h0)) node _read_data_3_T_1 = bits(_read_data_3_T, 6, 0) infer mport read_data_3_MPORT = regfile[_read_data_3_T_1], clock connect read_data[3], read_data_3_MPORT node _read_data_4_T = or(read_addrs_4, UInt<7>(0h0)) node _read_data_4_T_1 = bits(_read_data_4_T, 6, 0) infer mport read_data_4_MPORT = regfile[_read_data_4_T_1], clock connect read_data[4], read_data_4_MPORT node _read_data_5_T = or(read_addrs_5, UInt<7>(0h0)) node _read_data_5_T_1 = bits(_read_data_5_T, 6, 0) infer mport read_data_5_MPORT = regfile[_read_data_5_T_1], clock connect read_data[5], read_data_5_MPORT node _read_data_6_T = or(read_addrs_6, UInt<7>(0h0)) node _read_data_6_T_1 = bits(_read_data_6_T, 6, 0) infer mport read_data_6_MPORT = regfile[_read_data_6_T_1], clock connect read_data[6], read_data_6_MPORT node _read_data_7_T = or(read_addrs_7, UInt<7>(0h0)) node _read_data_7_T_1 = bits(_read_data_7_T, 6, 0) infer mport read_data_7_MPORT = regfile[_read_data_7_T_1], clock connect read_data[7], read_data_7_MPORT node _bypass_ens_T = eq(io.write_ports[0].bits.addr, read_addrs_0) node bypass_ens_0 = and(io.write_ports[0].valid, _bypass_ens_T) node _bypass_ens_T_1 = eq(io.write_ports[1].bits.addr, read_addrs_0) node bypass_ens_1 = and(io.write_ports[1].valid, _bypass_ens_T_1) node _bypass_ens_T_2 = eq(io.write_ports[2].bits.addr, read_addrs_0) node bypass_ens_2 = and(io.write_ports[2].valid, _bypass_ens_T_2) node _bypass_ens_T_3 = eq(io.write_ports[3].bits.addr, read_addrs_0) node bypass_ens_3 = and(io.write_ports[3].valid, _bypass_ens_T_3) wire _bypass_data_WIRE : UInt<1>[4] connect _bypass_data_WIRE[0], bypass_ens_0 connect _bypass_data_WIRE[1], bypass_ens_1 connect _bypass_data_WIRE[2], bypass_ens_2 connect _bypass_data_WIRE[3], bypass_ens_3 wire _bypass_data_WIRE_1 : UInt<64>[4] connect _bypass_data_WIRE_1[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_1[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_1[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_1[3], io.write_ports[3].bits.data node _bypass_data_T = mux(_bypass_data_WIRE[0], _bypass_data_WIRE_1[0], UInt<1>(0h0)) node _bypass_data_T_1 = mux(_bypass_data_WIRE[1], _bypass_data_WIRE_1[1], UInt<1>(0h0)) node _bypass_data_T_2 = mux(_bypass_data_WIRE[2], _bypass_data_WIRE_1[2], UInt<1>(0h0)) node _bypass_data_T_3 = mux(_bypass_data_WIRE[3], _bypass_data_WIRE_1[3], UInt<1>(0h0)) node _bypass_data_T_4 = or(_bypass_data_T, _bypass_data_T_1) node _bypass_data_T_5 = or(_bypass_data_T_4, _bypass_data_T_2) node _bypass_data_T_6 = or(_bypass_data_T_5, _bypass_data_T_3) wire bypass_data : UInt<64> connect bypass_data, _bypass_data_T_6 node _io_read_ports_0_data_T = or(bypass_ens_0, bypass_ens_1) node _io_read_ports_0_data_T_1 = or(_io_read_ports_0_data_T, bypass_ens_2) node _io_read_ports_0_data_T_2 = or(_io_read_ports_0_data_T_1, bypass_ens_3) node _io_read_ports_0_data_T_3 = mux(_io_read_ports_0_data_T_2, bypass_data, read_data[0]) connect io.read_ports[0].data, _io_read_ports_0_data_T_3 node _bypass_ens_T_4 = eq(io.write_ports[0].bits.addr, read_addrs_1) node bypass_ens_0_1 = and(io.write_ports[0].valid, _bypass_ens_T_4) node _bypass_ens_T_5 = eq(io.write_ports[1].bits.addr, read_addrs_1) node bypass_ens_1_1 = and(io.write_ports[1].valid, _bypass_ens_T_5) node _bypass_ens_T_6 = eq(io.write_ports[2].bits.addr, read_addrs_1) node bypass_ens_2_1 = and(io.write_ports[2].valid, _bypass_ens_T_6) node _bypass_ens_T_7 = eq(io.write_ports[3].bits.addr, read_addrs_1) node bypass_ens_3_1 = and(io.write_ports[3].valid, _bypass_ens_T_7) wire _bypass_data_WIRE_2 : UInt<1>[4] connect _bypass_data_WIRE_2[0], bypass_ens_0_1 connect _bypass_data_WIRE_2[1], bypass_ens_1_1 connect _bypass_data_WIRE_2[2], bypass_ens_2_1 connect _bypass_data_WIRE_2[3], bypass_ens_3_1 wire _bypass_data_WIRE_3 : UInt<64>[4] connect _bypass_data_WIRE_3[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_3[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_3[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_3[3], io.write_ports[3].bits.data node _bypass_data_T_7 = mux(_bypass_data_WIRE_2[0], _bypass_data_WIRE_3[0], UInt<1>(0h0)) node _bypass_data_T_8 = mux(_bypass_data_WIRE_2[1], _bypass_data_WIRE_3[1], UInt<1>(0h0)) node _bypass_data_T_9 = mux(_bypass_data_WIRE_2[2], _bypass_data_WIRE_3[2], UInt<1>(0h0)) node _bypass_data_T_10 = mux(_bypass_data_WIRE_2[3], _bypass_data_WIRE_3[3], UInt<1>(0h0)) node _bypass_data_T_11 = or(_bypass_data_T_7, _bypass_data_T_8) node _bypass_data_T_12 = or(_bypass_data_T_11, _bypass_data_T_9) node _bypass_data_T_13 = or(_bypass_data_T_12, _bypass_data_T_10) wire bypass_data_1 : UInt<64> connect bypass_data_1, _bypass_data_T_13 node _io_read_ports_1_data_T = or(bypass_ens_0_1, bypass_ens_1_1) node _io_read_ports_1_data_T_1 = or(_io_read_ports_1_data_T, bypass_ens_2_1) node _io_read_ports_1_data_T_2 = or(_io_read_ports_1_data_T_1, bypass_ens_3_1) node _io_read_ports_1_data_T_3 = mux(_io_read_ports_1_data_T_2, bypass_data_1, read_data[1]) connect io.read_ports[1].data, _io_read_ports_1_data_T_3 node _bypass_ens_T_8 = eq(io.write_ports[0].bits.addr, read_addrs_2) node bypass_ens_0_2 = and(io.write_ports[0].valid, _bypass_ens_T_8) node _bypass_ens_T_9 = eq(io.write_ports[1].bits.addr, read_addrs_2) node bypass_ens_1_2 = and(io.write_ports[1].valid, _bypass_ens_T_9) node _bypass_ens_T_10 = eq(io.write_ports[2].bits.addr, read_addrs_2) node bypass_ens_2_2 = and(io.write_ports[2].valid, _bypass_ens_T_10) node _bypass_ens_T_11 = eq(io.write_ports[3].bits.addr, read_addrs_2) node bypass_ens_3_2 = and(io.write_ports[3].valid, _bypass_ens_T_11) wire _bypass_data_WIRE_4 : UInt<1>[4] connect _bypass_data_WIRE_4[0], bypass_ens_0_2 connect _bypass_data_WIRE_4[1], bypass_ens_1_2 connect _bypass_data_WIRE_4[2], bypass_ens_2_2 connect _bypass_data_WIRE_4[3], bypass_ens_3_2 wire _bypass_data_WIRE_5 : UInt<64>[4] connect _bypass_data_WIRE_5[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_5[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_5[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_5[3], io.write_ports[3].bits.data node _bypass_data_T_14 = mux(_bypass_data_WIRE_4[0], _bypass_data_WIRE_5[0], UInt<1>(0h0)) node _bypass_data_T_15 = mux(_bypass_data_WIRE_4[1], _bypass_data_WIRE_5[1], UInt<1>(0h0)) node _bypass_data_T_16 = mux(_bypass_data_WIRE_4[2], _bypass_data_WIRE_5[2], UInt<1>(0h0)) node _bypass_data_T_17 = mux(_bypass_data_WIRE_4[3], _bypass_data_WIRE_5[3], UInt<1>(0h0)) node _bypass_data_T_18 = or(_bypass_data_T_14, _bypass_data_T_15) node _bypass_data_T_19 = or(_bypass_data_T_18, _bypass_data_T_16) node _bypass_data_T_20 = or(_bypass_data_T_19, _bypass_data_T_17) wire bypass_data_2 : UInt<64> connect bypass_data_2, _bypass_data_T_20 node _io_read_ports_2_data_T = or(bypass_ens_0_2, bypass_ens_1_2) node _io_read_ports_2_data_T_1 = or(_io_read_ports_2_data_T, bypass_ens_2_2) node _io_read_ports_2_data_T_2 = or(_io_read_ports_2_data_T_1, bypass_ens_3_2) node _io_read_ports_2_data_T_3 = mux(_io_read_ports_2_data_T_2, bypass_data_2, read_data[2]) connect io.read_ports[2].data, _io_read_ports_2_data_T_3 node _bypass_ens_T_12 = eq(io.write_ports[0].bits.addr, read_addrs_3) node bypass_ens_0_3 = and(io.write_ports[0].valid, _bypass_ens_T_12) node _bypass_ens_T_13 = eq(io.write_ports[1].bits.addr, read_addrs_3) node bypass_ens_1_3 = and(io.write_ports[1].valid, _bypass_ens_T_13) node _bypass_ens_T_14 = eq(io.write_ports[2].bits.addr, read_addrs_3) node bypass_ens_2_3 = and(io.write_ports[2].valid, _bypass_ens_T_14) node _bypass_ens_T_15 = eq(io.write_ports[3].bits.addr, read_addrs_3) node bypass_ens_3_3 = and(io.write_ports[3].valid, _bypass_ens_T_15) wire _bypass_data_WIRE_6 : UInt<1>[4] connect _bypass_data_WIRE_6[0], bypass_ens_0_3 connect _bypass_data_WIRE_6[1], bypass_ens_1_3 connect _bypass_data_WIRE_6[2], bypass_ens_2_3 connect _bypass_data_WIRE_6[3], bypass_ens_3_3 wire _bypass_data_WIRE_7 : UInt<64>[4] connect _bypass_data_WIRE_7[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_7[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_7[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_7[3], io.write_ports[3].bits.data node _bypass_data_T_21 = mux(_bypass_data_WIRE_6[0], _bypass_data_WIRE_7[0], UInt<1>(0h0)) node _bypass_data_T_22 = mux(_bypass_data_WIRE_6[1], _bypass_data_WIRE_7[1], UInt<1>(0h0)) node _bypass_data_T_23 = mux(_bypass_data_WIRE_6[2], _bypass_data_WIRE_7[2], UInt<1>(0h0)) node _bypass_data_T_24 = mux(_bypass_data_WIRE_6[3], _bypass_data_WIRE_7[3], UInt<1>(0h0)) node _bypass_data_T_25 = or(_bypass_data_T_21, _bypass_data_T_22) node _bypass_data_T_26 = or(_bypass_data_T_25, _bypass_data_T_23) node _bypass_data_T_27 = or(_bypass_data_T_26, _bypass_data_T_24) wire bypass_data_3 : UInt<64> connect bypass_data_3, _bypass_data_T_27 node _io_read_ports_3_data_T = or(bypass_ens_0_3, bypass_ens_1_3) node _io_read_ports_3_data_T_1 = or(_io_read_ports_3_data_T, bypass_ens_2_3) node _io_read_ports_3_data_T_2 = or(_io_read_ports_3_data_T_1, bypass_ens_3_3) node _io_read_ports_3_data_T_3 = mux(_io_read_ports_3_data_T_2, bypass_data_3, read_data[3]) connect io.read_ports[3].data, _io_read_ports_3_data_T_3 node _bypass_ens_T_16 = eq(io.write_ports[0].bits.addr, read_addrs_4) node bypass_ens_0_4 = and(io.write_ports[0].valid, _bypass_ens_T_16) node _bypass_ens_T_17 = eq(io.write_ports[1].bits.addr, read_addrs_4) node bypass_ens_1_4 = and(io.write_ports[1].valid, _bypass_ens_T_17) node _bypass_ens_T_18 = eq(io.write_ports[2].bits.addr, read_addrs_4) node bypass_ens_2_4 = and(io.write_ports[2].valid, _bypass_ens_T_18) node _bypass_ens_T_19 = eq(io.write_ports[3].bits.addr, read_addrs_4) node bypass_ens_3_4 = and(io.write_ports[3].valid, _bypass_ens_T_19) wire _bypass_data_WIRE_8 : UInt<1>[4] connect _bypass_data_WIRE_8[0], bypass_ens_0_4 connect _bypass_data_WIRE_8[1], bypass_ens_1_4 connect _bypass_data_WIRE_8[2], bypass_ens_2_4 connect _bypass_data_WIRE_8[3], bypass_ens_3_4 wire _bypass_data_WIRE_9 : UInt<64>[4] connect _bypass_data_WIRE_9[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_9[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_9[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_9[3], io.write_ports[3].bits.data node _bypass_data_T_28 = mux(_bypass_data_WIRE_8[0], _bypass_data_WIRE_9[0], UInt<1>(0h0)) node _bypass_data_T_29 = mux(_bypass_data_WIRE_8[1], _bypass_data_WIRE_9[1], UInt<1>(0h0)) node _bypass_data_T_30 = mux(_bypass_data_WIRE_8[2], _bypass_data_WIRE_9[2], UInt<1>(0h0)) node _bypass_data_T_31 = mux(_bypass_data_WIRE_8[3], _bypass_data_WIRE_9[3], UInt<1>(0h0)) node _bypass_data_T_32 = or(_bypass_data_T_28, _bypass_data_T_29) node _bypass_data_T_33 = or(_bypass_data_T_32, _bypass_data_T_30) node _bypass_data_T_34 = or(_bypass_data_T_33, _bypass_data_T_31) wire bypass_data_4 : UInt<64> connect bypass_data_4, _bypass_data_T_34 node _io_read_ports_4_data_T = or(bypass_ens_0_4, bypass_ens_1_4) node _io_read_ports_4_data_T_1 = or(_io_read_ports_4_data_T, bypass_ens_2_4) node _io_read_ports_4_data_T_2 = or(_io_read_ports_4_data_T_1, bypass_ens_3_4) node _io_read_ports_4_data_T_3 = mux(_io_read_ports_4_data_T_2, bypass_data_4, read_data[4]) connect io.read_ports[4].data, _io_read_ports_4_data_T_3 node _bypass_ens_T_20 = eq(io.write_ports[0].bits.addr, read_addrs_5) node bypass_ens_0_5 = and(io.write_ports[0].valid, _bypass_ens_T_20) node _bypass_ens_T_21 = eq(io.write_ports[1].bits.addr, read_addrs_5) node bypass_ens_1_5 = and(io.write_ports[1].valid, _bypass_ens_T_21) node _bypass_ens_T_22 = eq(io.write_ports[2].bits.addr, read_addrs_5) node bypass_ens_2_5 = and(io.write_ports[2].valid, _bypass_ens_T_22) node _bypass_ens_T_23 = eq(io.write_ports[3].bits.addr, read_addrs_5) node bypass_ens_3_5 = and(io.write_ports[3].valid, _bypass_ens_T_23) wire _bypass_data_WIRE_10 : UInt<1>[4] connect _bypass_data_WIRE_10[0], bypass_ens_0_5 connect _bypass_data_WIRE_10[1], bypass_ens_1_5 connect _bypass_data_WIRE_10[2], bypass_ens_2_5 connect _bypass_data_WIRE_10[3], bypass_ens_3_5 wire _bypass_data_WIRE_11 : UInt<64>[4] connect _bypass_data_WIRE_11[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_11[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_11[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_11[3], io.write_ports[3].bits.data node _bypass_data_T_35 = mux(_bypass_data_WIRE_10[0], _bypass_data_WIRE_11[0], UInt<1>(0h0)) node _bypass_data_T_36 = mux(_bypass_data_WIRE_10[1], _bypass_data_WIRE_11[1], UInt<1>(0h0)) node _bypass_data_T_37 = mux(_bypass_data_WIRE_10[2], _bypass_data_WIRE_11[2], UInt<1>(0h0)) node _bypass_data_T_38 = mux(_bypass_data_WIRE_10[3], _bypass_data_WIRE_11[3], UInt<1>(0h0)) node _bypass_data_T_39 = or(_bypass_data_T_35, _bypass_data_T_36) node _bypass_data_T_40 = or(_bypass_data_T_39, _bypass_data_T_37) node _bypass_data_T_41 = or(_bypass_data_T_40, _bypass_data_T_38) wire bypass_data_5 : UInt<64> connect bypass_data_5, _bypass_data_T_41 node _io_read_ports_5_data_T = or(bypass_ens_0_5, bypass_ens_1_5) node _io_read_ports_5_data_T_1 = or(_io_read_ports_5_data_T, bypass_ens_2_5) node _io_read_ports_5_data_T_2 = or(_io_read_ports_5_data_T_1, bypass_ens_3_5) node _io_read_ports_5_data_T_3 = mux(_io_read_ports_5_data_T_2, bypass_data_5, read_data[5]) connect io.read_ports[5].data, _io_read_ports_5_data_T_3 node _bypass_ens_T_24 = eq(io.write_ports[0].bits.addr, read_addrs_6) node bypass_ens_0_6 = and(io.write_ports[0].valid, _bypass_ens_T_24) node _bypass_ens_T_25 = eq(io.write_ports[1].bits.addr, read_addrs_6) node bypass_ens_1_6 = and(io.write_ports[1].valid, _bypass_ens_T_25) node _bypass_ens_T_26 = eq(io.write_ports[2].bits.addr, read_addrs_6) node bypass_ens_2_6 = and(io.write_ports[2].valid, _bypass_ens_T_26) node _bypass_ens_T_27 = eq(io.write_ports[3].bits.addr, read_addrs_6) node bypass_ens_3_6 = and(io.write_ports[3].valid, _bypass_ens_T_27) wire _bypass_data_WIRE_12 : UInt<1>[4] connect _bypass_data_WIRE_12[0], bypass_ens_0_6 connect _bypass_data_WIRE_12[1], bypass_ens_1_6 connect _bypass_data_WIRE_12[2], bypass_ens_2_6 connect _bypass_data_WIRE_12[3], bypass_ens_3_6 wire _bypass_data_WIRE_13 : UInt<64>[4] connect _bypass_data_WIRE_13[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_13[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_13[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_13[3], io.write_ports[3].bits.data node _bypass_data_T_42 = mux(_bypass_data_WIRE_12[0], _bypass_data_WIRE_13[0], UInt<1>(0h0)) node _bypass_data_T_43 = mux(_bypass_data_WIRE_12[1], _bypass_data_WIRE_13[1], UInt<1>(0h0)) node _bypass_data_T_44 = mux(_bypass_data_WIRE_12[2], _bypass_data_WIRE_13[2], UInt<1>(0h0)) node _bypass_data_T_45 = mux(_bypass_data_WIRE_12[3], _bypass_data_WIRE_13[3], UInt<1>(0h0)) node _bypass_data_T_46 = or(_bypass_data_T_42, _bypass_data_T_43) node _bypass_data_T_47 = or(_bypass_data_T_46, _bypass_data_T_44) node _bypass_data_T_48 = or(_bypass_data_T_47, _bypass_data_T_45) wire bypass_data_6 : UInt<64> connect bypass_data_6, _bypass_data_T_48 node _io_read_ports_6_data_T = or(bypass_ens_0_6, bypass_ens_1_6) node _io_read_ports_6_data_T_1 = or(_io_read_ports_6_data_T, bypass_ens_2_6) node _io_read_ports_6_data_T_2 = or(_io_read_ports_6_data_T_1, bypass_ens_3_6) node _io_read_ports_6_data_T_3 = mux(_io_read_ports_6_data_T_2, bypass_data_6, read_data[6]) connect io.read_ports[6].data, _io_read_ports_6_data_T_3 node _bypass_ens_T_28 = eq(io.write_ports[0].bits.addr, read_addrs_7) node bypass_ens_0_7 = and(io.write_ports[0].valid, _bypass_ens_T_28) node _bypass_ens_T_29 = eq(io.write_ports[1].bits.addr, read_addrs_7) node bypass_ens_1_7 = and(io.write_ports[1].valid, _bypass_ens_T_29) node _bypass_ens_T_30 = eq(io.write_ports[2].bits.addr, read_addrs_7) node bypass_ens_2_7 = and(io.write_ports[2].valid, _bypass_ens_T_30) node _bypass_ens_T_31 = eq(io.write_ports[3].bits.addr, read_addrs_7) node bypass_ens_3_7 = and(io.write_ports[3].valid, _bypass_ens_T_31) wire _bypass_data_WIRE_14 : UInt<1>[4] connect _bypass_data_WIRE_14[0], bypass_ens_0_7 connect _bypass_data_WIRE_14[1], bypass_ens_1_7 connect _bypass_data_WIRE_14[2], bypass_ens_2_7 connect _bypass_data_WIRE_14[3], bypass_ens_3_7 wire _bypass_data_WIRE_15 : UInt<64>[4] connect _bypass_data_WIRE_15[0], io.write_ports[0].bits.data connect _bypass_data_WIRE_15[1], io.write_ports[1].bits.data connect _bypass_data_WIRE_15[2], io.write_ports[2].bits.data connect _bypass_data_WIRE_15[3], io.write_ports[3].bits.data node _bypass_data_T_49 = mux(_bypass_data_WIRE_14[0], _bypass_data_WIRE_15[0], UInt<1>(0h0)) node _bypass_data_T_50 = mux(_bypass_data_WIRE_14[1], _bypass_data_WIRE_15[1], UInt<1>(0h0)) node _bypass_data_T_51 = mux(_bypass_data_WIRE_14[2], _bypass_data_WIRE_15[2], UInt<1>(0h0)) node _bypass_data_T_52 = mux(_bypass_data_WIRE_14[3], _bypass_data_WIRE_15[3], UInt<1>(0h0)) node _bypass_data_T_53 = or(_bypass_data_T_49, _bypass_data_T_50) node _bypass_data_T_54 = or(_bypass_data_T_53, _bypass_data_T_51) node _bypass_data_T_55 = or(_bypass_data_T_54, _bypass_data_T_52) wire bypass_data_7 : UInt<64> connect bypass_data_7, _bypass_data_T_55 node _io_read_ports_7_data_T = or(bypass_ens_0_7, bypass_ens_1_7) node _io_read_ports_7_data_T_1 = or(_io_read_ports_7_data_T, bypass_ens_2_7) node _io_read_ports_7_data_T_2 = or(_io_read_ports_7_data_T_1, bypass_ens_3_7) node _io_read_ports_7_data_T_3 = mux(_io_read_ports_7_data_T_2, bypass_data_7, read_data[7]) connect io.read_ports[7].data, _io_read_ports_7_data_T_3 when io.write_ports[0].valid : infer mport MPORT = regfile[io.write_ports[0].bits.addr], clock connect MPORT, io.write_ports[0].bits.data when io.write_ports[1].valid : infer mport MPORT_1 = regfile[io.write_ports[1].bits.addr], clock connect MPORT_1, io.write_ports[1].bits.data when io.write_ports[2].valid : infer mport MPORT_2 = regfile[io.write_ports[2].bits.addr], clock connect MPORT_2, io.write_ports[2].bits.data when io.write_ports[3].valid : infer mport MPORT_3 = regfile[io.write_ports[3].bits.addr], clock connect MPORT_3, io.write_ports[3].bits.data node _T = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0)) node _T_6 = or(_T_4, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_11 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = neq(io.write_ports[0].bits.addr, io.write_ports[2].bits.addr) node _T_14 = or(_T_12, _T_13) node _T_15 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0)) node _T_16 = or(_T_14, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.write_ports[0].valid, UInt<1>(0h0)) node _T_21 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_22 = or(_T_20, _T_21) node _T_23 = neq(io.write_ports[0].bits.addr, io.write_ports[3].bits.addr) node _T_24 = or(_T_22, _T_23) node _T_25 = eq(io.write_ports[0].bits.addr, UInt<1>(0h0)) node _T_26 = or(_T_24, _T_25) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf_2 assert(clock, _T_26, UInt<1>(0h1), "") : assert_2 node _T_30 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_31 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_32 = or(_T_30, _T_31) node _T_33 = neq(io.write_ports[1].bits.addr, io.write_ports[2].bits.addr) node _T_34 = or(_T_32, _T_33) node _T_35 = eq(io.write_ports[1].bits.addr, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf_3 assert(clock, _T_36, UInt<1>(0h1), "") : assert_3 node _T_40 = eq(io.write_ports[1].valid, UInt<1>(0h0)) node _T_41 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = neq(io.write_ports[1].bits.addr, io.write_ports[3].bits.addr) node _T_44 = or(_T_42, _T_43) node _T_45 = eq(io.write_ports[1].bits.addr, UInt<1>(0h0)) node _T_46 = or(_T_44, _T_45) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf_4 assert(clock, _T_46, UInt<1>(0h1), "") : assert_4 node _T_50 = eq(io.write_ports[2].valid, UInt<1>(0h0)) node _T_51 = eq(io.write_ports[3].valid, UInt<1>(0h0)) node _T_52 = or(_T_50, _T_51) node _T_53 = neq(io.write_ports[2].bits.addr, io.write_ports[3].bits.addr) node _T_54 = or(_T_52, _T_53) node _T_55 = eq(io.write_ports[2].bits.addr, UInt<1>(0h0)) node _T_56 = or(_T_54, _T_55) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:171 assert(!io.write_ports(i).valid ||\n") : printf_5 assert(clock, _T_56, UInt<1>(0h1), "") : assert_5
module RegisterFileSynthesizable_1( // @[regfile.scala:106:7] input clock, // @[regfile.scala:106:7] input reset, // @[regfile.scala:106:7] input [6:0] io_read_ports_0_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_0_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_1_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_1_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_2_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_2_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_3_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_3_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_4_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_4_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_5_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_5_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_6_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_6_data, // @[regfile.scala:82:14] input [6:0] io_read_ports_7_addr, // @[regfile.scala:82:14] output [63:0] io_read_ports_7_data, // @[regfile.scala:82:14] input io_write_ports_0_valid, // @[regfile.scala:82:14] input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:82:14] input io_write_ports_1_valid, // @[regfile.scala:82:14] input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_1_bits_data, // @[regfile.scala:82:14] input io_write_ports_2_valid, // @[regfile.scala:82:14] input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_2_bits_data, // @[regfile.scala:82:14] input io_write_ports_3_valid, // @[regfile.scala:82:14] input [6:0] io_write_ports_3_bits_addr, // @[regfile.scala:82:14] input [63:0] io_write_ports_3_bits_data // @[regfile.scala:82:14] ); wire [6:0] io_read_ports_0_addr_0 = io_read_ports_0_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_1_addr_0 = io_read_ports_1_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_2_addr_0 = io_read_ports_2_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_3_addr_0 = io_read_ports_3_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_4_addr_0 = io_read_ports_4_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_5_addr_0 = io_read_ports_5_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_6_addr_0 = io_read_ports_6_addr; // @[regfile.scala:106:7] wire [6:0] io_read_ports_7_addr_0 = io_read_ports_7_addr; // @[regfile.scala:106:7] wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:106:7] wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:106:7] wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:106:7] wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:106:7] wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:106:7] wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:106:7] wire io_write_ports_3_valid_0 = io_write_ports_3_valid; // @[regfile.scala:106:7] wire [6:0] io_write_ports_3_bits_addr_0 = io_write_ports_3_bits_addr; // @[regfile.scala:106:7] wire [63:0] io_write_ports_3_bits_data_0 = io_write_ports_3_bits_data; // @[regfile.scala:106:7] wire [63:0] _io_read_ports_0_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_1_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_2_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_3_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_4_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_5_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_6_data_T_3; // @[regfile.scala:150:35] wire [63:0] _io_read_ports_7_data_T_3; // @[regfile.scala:150:35] wire [63:0] _bypass_data_WIRE_1_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_9_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_11_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_13_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_15_0 = io_write_ports_0_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_1_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_9_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_11_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_13_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_15_1 = io_write_ports_1_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_1_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_9_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_11_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_13_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_15_2 = io_write_ports_2_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_1_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_3_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_5_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_7_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_9_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_11_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_13_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] _bypass_data_WIRE_15_3 = io_write_ports_3_bits_data_0; // @[regfile.scala:106:7, :148:65] wire [63:0] io_read_ports_0_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_1_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_2_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_3_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_4_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_5_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_6_data_0; // @[regfile.scala:106:7] wire [63:0] io_read_ports_7_data_0; // @[regfile.scala:106:7] wire [63:0] read_data_0; // @[regfile.scala:122:23] wire [63:0] read_data_1; // @[regfile.scala:122:23] wire [63:0] read_data_2; // @[regfile.scala:122:23] wire [63:0] read_data_3; // @[regfile.scala:122:23] wire [63:0] read_data_4; // @[regfile.scala:122:23] wire [63:0] read_data_5; // @[regfile.scala:122:23] wire [63:0] read_data_6; // @[regfile.scala:122:23] wire [63:0] read_data_7; // @[regfile.scala:122:23] reg [6:0] read_addrs_0; // @[regfile.scala:125:50] wire [6:0] _read_data_0_T = read_addrs_0; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_1; // @[regfile.scala:125:50] wire [6:0] _read_data_1_T = read_addrs_1; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_2; // @[regfile.scala:125:50] wire [6:0] _read_data_2_T = read_addrs_2; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_3; // @[regfile.scala:125:50] wire [6:0] _read_data_3_T = read_addrs_3; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_4; // @[regfile.scala:125:50] wire [6:0] _read_data_4_T = read_addrs_4; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_5; // @[regfile.scala:125:50] wire [6:0] _read_data_5_T = read_addrs_5; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_6; // @[regfile.scala:125:50] wire [6:0] _read_data_6_T = read_addrs_6; // @[regfile.scala:125:50, :128:28] reg [6:0] read_addrs_7; // @[regfile.scala:125:50] wire [6:0] _read_data_7_T = read_addrs_7; // @[regfile.scala:125:50, :128:28] wire [6:0] _read_data_0_T_1 = _read_data_0_T; // @[regfile.scala:128:28] wire [6:0] _read_data_1_T_1 = _read_data_1_T; // @[regfile.scala:128:28] wire [6:0] _read_data_2_T_1 = _read_data_2_T; // @[regfile.scala:128:28] wire [6:0] _read_data_3_T_1 = _read_data_3_T; // @[regfile.scala:128:28] wire [6:0] _read_data_4_T_1 = _read_data_4_T; // @[regfile.scala:128:28] wire [6:0] _read_data_5_T_1 = _read_data_5_T; // @[regfile.scala:128:28] wire [6:0] _read_data_6_T_1 = _read_data_6_T; // @[regfile.scala:128:28] wire [6:0] _read_data_7_T_1 = _read_data_7_T; // @[regfile.scala:128:28] wire _bypass_ens_T = io_write_ports_0_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0 = io_write_ports_0_valid_0 & _bypass_ens_T; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_0 = bypass_ens_0; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_1 = io_write_ports_1_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1 = io_write_ports_1_valid_0 & _bypass_ens_T_1; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_1 = bypass_ens_1; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_2 = io_write_ports_2_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2 = io_write_ports_2_valid_0 & _bypass_ens_T_2; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2 = bypass_ens_2; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_3 = io_write_ports_3_bits_addr_0 == read_addrs_0; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3 = io_write_ports_3_valid_0 & _bypass_ens_T_3; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_3 = bypass_ens_3; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T = _bypass_data_WIRE_0 ? _bypass_data_WIRE_1_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_1 = _bypass_data_WIRE_1 ? _bypass_data_WIRE_1_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_2 = _bypass_data_WIRE_2 ? _bypass_data_WIRE_1_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_3 = _bypass_data_WIRE_3 ? _bypass_data_WIRE_1_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_4 = _bypass_data_T | _bypass_data_T_1; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_5 = _bypass_data_T_4 | _bypass_data_T_2; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_6 = _bypass_data_T_5 | _bypass_data_T_3; // @[Mux.scala:30:73] wire [63:0] bypass_data = _bypass_data_T_6; // @[Mux.scala:30:73] wire _io_read_ports_0_data_T = bypass_ens_0 | bypass_ens_1; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_0_data_T_1 = _io_read_ports_0_data_T | bypass_ens_2; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_0_data_T_2 = _io_read_ports_0_data_T_1 | bypass_ens_3; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_0_data_T_3 = _io_read_ports_0_data_T_2 ? bypass_data : read_data_0; // @[Mux.scala:30:73] assign io_read_ports_0_data_0 = _io_read_ports_0_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_4 = io_write_ports_0_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_1 = io_write_ports_0_valid_0 & _bypass_ens_T_4; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_0 = bypass_ens_0_1; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_5 = io_write_ports_1_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_1 = io_write_ports_1_valid_0 & _bypass_ens_T_5; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_1 = bypass_ens_1_1; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_6 = io_write_ports_2_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_1 = io_write_ports_2_valid_0 & _bypass_ens_T_6; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_2 = bypass_ens_2_1; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_7 = io_write_ports_3_bits_addr_0 == read_addrs_1; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_1 = io_write_ports_3_valid_0 & _bypass_ens_T_7; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_2_3 = bypass_ens_3_1; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_7 = _bypass_data_WIRE_2_0 ? _bypass_data_WIRE_3_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_8 = _bypass_data_WIRE_2_1 ? _bypass_data_WIRE_3_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_9 = _bypass_data_WIRE_2_2 ? _bypass_data_WIRE_3_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_10 = _bypass_data_WIRE_2_3 ? _bypass_data_WIRE_3_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_11 = _bypass_data_T_7 | _bypass_data_T_8; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_12 = _bypass_data_T_11 | _bypass_data_T_9; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_13 = _bypass_data_T_12 | _bypass_data_T_10; // @[Mux.scala:30:73] wire [63:0] bypass_data_1 = _bypass_data_T_13; // @[Mux.scala:30:73] wire _io_read_ports_1_data_T = bypass_ens_0_1 | bypass_ens_1_1; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_1_data_T_1 = _io_read_ports_1_data_T | bypass_ens_2_1; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_1_data_T_2 = _io_read_ports_1_data_T_1 | bypass_ens_3_1; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_1_data_T_3 = _io_read_ports_1_data_T_2 ? bypass_data_1 : read_data_1; // @[Mux.scala:30:73] assign io_read_ports_1_data_0 = _io_read_ports_1_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_8 = io_write_ports_0_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_2 = io_write_ports_0_valid_0 & _bypass_ens_T_8; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_0 = bypass_ens_0_2; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_9 = io_write_ports_1_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_2 = io_write_ports_1_valid_0 & _bypass_ens_T_9; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_1 = bypass_ens_1_2; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_10 = io_write_ports_2_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_2 = io_write_ports_2_valid_0 & _bypass_ens_T_10; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_2 = bypass_ens_2_2; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_11 = io_write_ports_3_bits_addr_0 == read_addrs_2; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_2 = io_write_ports_3_valid_0 & _bypass_ens_T_11; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_4_3 = bypass_ens_3_2; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_14 = _bypass_data_WIRE_4_0 ? _bypass_data_WIRE_5_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_15 = _bypass_data_WIRE_4_1 ? _bypass_data_WIRE_5_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_16 = _bypass_data_WIRE_4_2 ? _bypass_data_WIRE_5_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_17 = _bypass_data_WIRE_4_3 ? _bypass_data_WIRE_5_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_18 = _bypass_data_T_14 | _bypass_data_T_15; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_19 = _bypass_data_T_18 | _bypass_data_T_16; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_20 = _bypass_data_T_19 | _bypass_data_T_17; // @[Mux.scala:30:73] wire [63:0] bypass_data_2 = _bypass_data_T_20; // @[Mux.scala:30:73] wire _io_read_ports_2_data_T = bypass_ens_0_2 | bypass_ens_1_2; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_2_data_T_1 = _io_read_ports_2_data_T | bypass_ens_2_2; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_2_data_T_2 = _io_read_ports_2_data_T_1 | bypass_ens_3_2; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_2_data_T_3 = _io_read_ports_2_data_T_2 ? bypass_data_2 : read_data_2; // @[Mux.scala:30:73] assign io_read_ports_2_data_0 = _io_read_ports_2_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_12 = io_write_ports_0_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_3 = io_write_ports_0_valid_0 & _bypass_ens_T_12; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_0 = bypass_ens_0_3; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_13 = io_write_ports_1_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_3 = io_write_ports_1_valid_0 & _bypass_ens_T_13; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_1 = bypass_ens_1_3; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_14 = io_write_ports_2_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_3 = io_write_ports_2_valid_0 & _bypass_ens_T_14; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_2 = bypass_ens_2_3; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_15 = io_write_ports_3_bits_addr_0 == read_addrs_3; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_3 = io_write_ports_3_valid_0 & _bypass_ens_T_15; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_6_3 = bypass_ens_3_3; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_21 = _bypass_data_WIRE_6_0 ? _bypass_data_WIRE_7_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_22 = _bypass_data_WIRE_6_1 ? _bypass_data_WIRE_7_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_23 = _bypass_data_WIRE_6_2 ? _bypass_data_WIRE_7_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_24 = _bypass_data_WIRE_6_3 ? _bypass_data_WIRE_7_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_25 = _bypass_data_T_21 | _bypass_data_T_22; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_26 = _bypass_data_T_25 | _bypass_data_T_23; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_27 = _bypass_data_T_26 | _bypass_data_T_24; // @[Mux.scala:30:73] wire [63:0] bypass_data_3 = _bypass_data_T_27; // @[Mux.scala:30:73] wire _io_read_ports_3_data_T = bypass_ens_0_3 | bypass_ens_1_3; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_3_data_T_1 = _io_read_ports_3_data_T | bypass_ens_2_3; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_3_data_T_2 = _io_read_ports_3_data_T_1 | bypass_ens_3_3; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_3_data_T_3 = _io_read_ports_3_data_T_2 ? bypass_data_3 : read_data_3; // @[Mux.scala:30:73] assign io_read_ports_3_data_0 = _io_read_ports_3_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_16 = io_write_ports_0_bits_addr_0 == read_addrs_4; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_4 = io_write_ports_0_valid_0 & _bypass_ens_T_16; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_8_0 = bypass_ens_0_4; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_17 = io_write_ports_1_bits_addr_0 == read_addrs_4; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_4 = io_write_ports_1_valid_0 & _bypass_ens_T_17; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_8_1 = bypass_ens_1_4; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_18 = io_write_ports_2_bits_addr_0 == read_addrs_4; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_4 = io_write_ports_2_valid_0 & _bypass_ens_T_18; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_8_2 = bypass_ens_2_4; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_19 = io_write_ports_3_bits_addr_0 == read_addrs_4; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_4 = io_write_ports_3_valid_0 & _bypass_ens_T_19; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_8_3 = bypass_ens_3_4; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_28 = _bypass_data_WIRE_8_0 ? _bypass_data_WIRE_9_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_29 = _bypass_data_WIRE_8_1 ? _bypass_data_WIRE_9_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_30 = _bypass_data_WIRE_8_2 ? _bypass_data_WIRE_9_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_31 = _bypass_data_WIRE_8_3 ? _bypass_data_WIRE_9_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_32 = _bypass_data_T_28 | _bypass_data_T_29; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_33 = _bypass_data_T_32 | _bypass_data_T_30; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_34 = _bypass_data_T_33 | _bypass_data_T_31; // @[Mux.scala:30:73] wire [63:0] bypass_data_4 = _bypass_data_T_34; // @[Mux.scala:30:73] wire _io_read_ports_4_data_T = bypass_ens_0_4 | bypass_ens_1_4; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_4_data_T_1 = _io_read_ports_4_data_T | bypass_ens_2_4; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_4_data_T_2 = _io_read_ports_4_data_T_1 | bypass_ens_3_4; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_4_data_T_3 = _io_read_ports_4_data_T_2 ? bypass_data_4 : read_data_4; // @[Mux.scala:30:73] assign io_read_ports_4_data_0 = _io_read_ports_4_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_20 = io_write_ports_0_bits_addr_0 == read_addrs_5; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_5 = io_write_ports_0_valid_0 & _bypass_ens_T_20; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_10_0 = bypass_ens_0_5; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_21 = io_write_ports_1_bits_addr_0 == read_addrs_5; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_5 = io_write_ports_1_valid_0 & _bypass_ens_T_21; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_10_1 = bypass_ens_1_5; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_22 = io_write_ports_2_bits_addr_0 == read_addrs_5; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_5 = io_write_ports_2_valid_0 & _bypass_ens_T_22; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_10_2 = bypass_ens_2_5; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_23 = io_write_ports_3_bits_addr_0 == read_addrs_5; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_5 = io_write_ports_3_valid_0 & _bypass_ens_T_23; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_10_3 = bypass_ens_3_5; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_35 = _bypass_data_WIRE_10_0 ? _bypass_data_WIRE_11_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_36 = _bypass_data_WIRE_10_1 ? _bypass_data_WIRE_11_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_37 = _bypass_data_WIRE_10_2 ? _bypass_data_WIRE_11_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_38 = _bypass_data_WIRE_10_3 ? _bypass_data_WIRE_11_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_39 = _bypass_data_T_35 | _bypass_data_T_36; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_40 = _bypass_data_T_39 | _bypass_data_T_37; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_41 = _bypass_data_T_40 | _bypass_data_T_38; // @[Mux.scala:30:73] wire [63:0] bypass_data_5 = _bypass_data_T_41; // @[Mux.scala:30:73] wire _io_read_ports_5_data_T = bypass_ens_0_5 | bypass_ens_1_5; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_5_data_T_1 = _io_read_ports_5_data_T | bypass_ens_2_5; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_5_data_T_2 = _io_read_ports_5_data_T_1 | bypass_ens_3_5; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_5_data_T_3 = _io_read_ports_5_data_T_2 ? bypass_data_5 : read_data_5; // @[Mux.scala:30:73] assign io_read_ports_5_data_0 = _io_read_ports_5_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_24 = io_write_ports_0_bits_addr_0 == read_addrs_6; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_6 = io_write_ports_0_valid_0 & _bypass_ens_T_24; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_12_0 = bypass_ens_0_6; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_25 = io_write_ports_1_bits_addr_0 == read_addrs_6; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_6 = io_write_ports_1_valid_0 & _bypass_ens_T_25; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_12_1 = bypass_ens_1_6; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_26 = io_write_ports_2_bits_addr_0 == read_addrs_6; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_6 = io_write_ports_2_valid_0 & _bypass_ens_T_26; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_12_2 = bypass_ens_2_6; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_27 = io_write_ports_3_bits_addr_0 == read_addrs_6; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_6 = io_write_ports_3_valid_0 & _bypass_ens_T_27; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_12_3 = bypass_ens_3_6; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_42 = _bypass_data_WIRE_12_0 ? _bypass_data_WIRE_13_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_43 = _bypass_data_WIRE_12_1 ? _bypass_data_WIRE_13_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_44 = _bypass_data_WIRE_12_2 ? _bypass_data_WIRE_13_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_45 = _bypass_data_WIRE_12_3 ? _bypass_data_WIRE_13_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_46 = _bypass_data_T_42 | _bypass_data_T_43; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_47 = _bypass_data_T_46 | _bypass_data_T_44; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_48 = _bypass_data_T_47 | _bypass_data_T_45; // @[Mux.scala:30:73] wire [63:0] bypass_data_6 = _bypass_data_T_48; // @[Mux.scala:30:73] wire _io_read_ports_6_data_T = bypass_ens_0_6 | bypass_ens_1_6; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_6_data_T_1 = _io_read_ports_6_data_T | bypass_ens_2_6; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_6_data_T_2 = _io_read_ports_6_data_T_1 | bypass_ens_3_6; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_6_data_T_3 = _io_read_ports_6_data_T_2 ? bypass_data_6 : read_data_6; // @[Mux.scala:30:73] assign io_read_ports_6_data_0 = _io_read_ports_6_data_T_3; // @[regfile.scala:106:7, :150:35] wire _bypass_ens_T_28 = io_write_ports_0_bits_addr_0 == read_addrs_7; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_0_7 = io_write_ports_0_valid_0 & _bypass_ens_T_28; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_14_0 = bypass_ens_0_7; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_29 = io_write_ports_1_bits_addr_0 == read_addrs_7; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_1_7 = io_write_ports_1_valid_0 & _bypass_ens_T_29; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_14_1 = bypass_ens_1_7; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_30 = io_write_ports_2_bits_addr_0 == read_addrs_7; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_2_7 = io_write_ports_2_valid_0 & _bypass_ens_T_30; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_14_2 = bypass_ens_2_7; // @[regfile.scala:145:59, :148:38] wire _bypass_ens_T_31 = io_write_ports_3_bits_addr_0 == read_addrs_7; // @[regfile.scala:106:7, :125:50, :146:21] wire bypass_ens_3_7 = io_write_ports_3_valid_0 & _bypass_ens_T_31; // @[regfile.scala:106:7, :145:59, :146:21] wire _bypass_data_WIRE_14_3 = bypass_ens_3_7; // @[regfile.scala:145:59, :148:38] wire [63:0] _bypass_data_T_49 = _bypass_data_WIRE_14_0 ? _bypass_data_WIRE_15_0 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_50 = _bypass_data_WIRE_14_1 ? _bypass_data_WIRE_15_1 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_51 = _bypass_data_WIRE_14_2 ? _bypass_data_WIRE_15_2 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_52 = _bypass_data_WIRE_14_3 ? _bypass_data_WIRE_15_3 : 64'h0; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_53 = _bypass_data_T_49 | _bypass_data_T_50; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_54 = _bypass_data_T_53 | _bypass_data_T_51; // @[Mux.scala:30:73] wire [63:0] _bypass_data_T_55 = _bypass_data_T_54 | _bypass_data_T_52; // @[Mux.scala:30:73] wire [63:0] bypass_data_7 = _bypass_data_T_55; // @[Mux.scala:30:73] wire _io_read_ports_7_data_T = bypass_ens_0_7 | bypass_ens_1_7; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_7_data_T_1 = _io_read_ports_7_data_T | bypass_ens_2_7; // @[regfile.scala:145:59, :150:55] wire _io_read_ports_7_data_T_2 = _io_read_ports_7_data_T_1 | bypass_ens_3_7; // @[regfile.scala:145:59, :150:55] assign _io_read_ports_7_data_T_3 = _io_read_ports_7_data_T_2 ? bypass_data_7 : read_data_7; // @[Mux.scala:30:73] assign io_read_ports_7_data_0 = _io_read_ports_7_data_T_3; // @[regfile.scala:106:7, :150:35]
Generate the Verilog code corresponding to this FIRRTL code module FrontEnd : input clock : Clock input reset : Reset output io : { cpu : { flip req : { valid : UInt<1>, bits : { pc : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<32>, inst : UInt<32>}}, debug : { if_pc : UInt<32>, if_inst : UInt<32>}, imiss : UInt<1>, flip exe_kill : UInt<1>}, imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip reset_vector : UInt} invalidate io.reset_vector invalidate io.imem.resp.bits.data invalidate io.imem.resp.valid invalidate io.imem.req.bits.typ invalidate io.imem.req.bits.fcn invalidate io.imem.req.bits.data invalidate io.imem.req.bits.addr invalidate io.imem.req.valid invalidate io.imem.req.ready invalidate io.cpu.exe_kill invalidate io.cpu.imiss invalidate io.cpu.debug.if_inst invalidate io.cpu.debug.if_pc invalidate io.cpu.resp.bits.inst invalidate io.cpu.resp.bits.pc invalidate io.cpu.resp.valid invalidate io.cpu.resp.ready invalidate io.cpu.req.bits.pc invalidate io.cpu.req.valid node _if_reg_pc_T = sub(io.reset_vector, UInt<3>(0h4)) node _if_reg_pc_T_1 = tail(_if_reg_pc_T, 1) regreset if_reg_pc : UInt, clock, reset, _if_reg_pc_T_1 regreset exe_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg exe_reg_pc : UInt<32>, clock reg exe_reg_inst : UInt<32>, clock wire if_pc_next : UInt<32> wire if_val_next : UInt<1> node _if_pc_plus4_T = add(if_reg_pc, UInt<32>(0h4)) node if_pc_plus4 = tail(_if_pc_plus4_T, 1) regreset if_redirected : UInt<1>, clock, reset, UInt<1>(0h0) reg if_redirected_pc : UInt<32>, clock wire if_buffer_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>}} connect if_buffer_in.valid, io.imem.resp.valid connect if_buffer_in.bits, io.imem.resp.bits node _if_val_next_T = eq(io.imem.resp.valid, UInt<1>(0h0)) node _if_val_next_T_1 = and(if_buffer_in.ready, _if_val_next_T) node _if_val_next_T_2 = or(io.cpu.resp.ready, _if_val_next_T_1) connect if_val_next, _if_val_next_T_2 node _T = eq(if_buffer_in.valid, UInt<1>(0h0)) node _T_1 = or(if_buffer_in.ready, _T) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed: Inst buffer overflow\n at frontend.scala:112 assert(if_buffer_in.ready || !if_buffer_in.valid, \"Inst buffer overflow\")\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert inst if_buffer_out_q of Queue1_MemResp connect if_buffer_out_q.clock, clock connect if_buffer_out_q.reset, reset connect if_buffer_out_q.io.enq.valid, if_buffer_in.valid connect if_buffer_out_q.io.enq.bits.data, if_buffer_in.bits.data connect if_buffer_in.ready, if_buffer_out_q.io.enq.ready connect if_pc_next, if_pc_plus4 when io.cpu.req.valid : connect if_redirected, UInt<1>(0h1) connect if_redirected_pc, io.cpu.req.bits.pc when if_redirected : connect if_pc_next, if_redirected_pc regreset if_reg_pc_responded : UInt<1>, clock, reset, UInt<1>(0h0) node if_pc_responsed = or(if_reg_pc_responded, io.imem.resp.valid) node _T_5 = and(io.cpu.resp.ready, io.imem.req.ready) node _T_6 = and(_T_5, if_pc_responsed) when _T_6 : connect if_reg_pc_responded, UInt<1>(0h0) connect if_reg_pc, if_pc_next node _T_7 = eq(io.cpu.req.valid, UInt<1>(0h0)) when _T_7 : connect if_redirected, UInt<1>(0h0) else : when io.imem.resp.valid : connect if_reg_pc_responded, UInt<1>(0h1) connect io.imem.req.bits.addr, if_pc_next node _io_imem_req_valid_T = eq(io.cpu.req.valid, UInt<1>(0h0)) node _io_imem_req_valid_T_1 = and(if_val_next, _io_imem_req_valid_T) connect io.imem.req.valid, _io_imem_req_valid_T_1 connect io.imem.req.bits.fcn, UInt<1>(0h0) connect io.imem.req.bits.typ, UInt<3>(0h7) connect if_buffer_out_q.io.deq.ready, io.cpu.resp.ready when io.cpu.exe_kill : connect exe_reg_valid, UInt<1>(0h0) else : when io.cpu.resp.ready : node _exe_reg_valid_T = eq(io.cpu.req.valid, UInt<1>(0h0)) node _exe_reg_valid_T_1 = and(if_buffer_out_q.io.deq.valid, _exe_reg_valid_T) node _exe_reg_valid_T_2 = eq(if_redirected, UInt<1>(0h0)) node _exe_reg_valid_T_3 = and(_exe_reg_valid_T_1, _exe_reg_valid_T_2) connect exe_reg_valid, _exe_reg_valid_T_3 connect exe_reg_pc, if_reg_pc connect exe_reg_inst, if_buffer_out_q.io.deq.bits.data connect io.cpu.resp.valid, exe_reg_valid connect io.cpu.resp.bits.inst, exe_reg_inst connect io.cpu.resp.bits.pc, exe_reg_pc connect io.cpu.debug.if_pc, if_reg_pc connect io.cpu.debug.if_inst, io.imem.resp.bits.data
module FrontEnd( // @[frontend.scala:82:7] input clock, // @[frontend.scala:82:7] input reset, // @[frontend.scala:82:7] input io_cpu_req_valid, // @[frontend.scala:84:15] input [31:0] io_cpu_req_bits_pc, // @[frontend.scala:84:15] input io_cpu_resp_ready, // @[frontend.scala:84:15] output io_cpu_resp_valid, // @[frontend.scala:84:15] output [31:0] io_cpu_resp_bits_pc, // @[frontend.scala:84:15] output [31:0] io_cpu_resp_bits_inst, // @[frontend.scala:84:15] output [31:0] io_cpu_debug_if_pc, // @[frontend.scala:84:15] output [31:0] io_cpu_debug_if_inst, // @[frontend.scala:84:15] input io_cpu_exe_kill, // @[frontend.scala:84:15] input io_imem_req_ready, // @[frontend.scala:84:15] output io_imem_req_valid, // @[frontend.scala:84:15] output [31:0] io_imem_req_bits_addr, // @[frontend.scala:84:15] input io_imem_resp_valid, // @[frontend.scala:84:15] input [31:0] io_imem_resp_bits_data // @[frontend.scala:84:15] ); wire _if_buffer_out_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [31:0] _if_buffer_out_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[frontend.scala:82:7] wire [31:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[frontend.scala:82:7] wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[frontend.scala:82:7] wire io_cpu_exe_kill_0 = io_cpu_exe_kill; // @[frontend.scala:82:7] wire io_imem_req_ready_0 = io_imem_req_ready; // @[frontend.scala:82:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[frontend.scala:82:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[frontend.scala:82:7] wire io_cpu_imiss = 1'h0; // @[frontend.scala:82:7] wire io_imem_req_bits_fcn = 1'h0; // @[frontend.scala:82:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[frontend.scala:82:7] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[frontend.scala:82:7] wire [31:0] io_reset_vector = 32'h10000; // @[frontend.scala:82:7] wire [31:0] _if_reg_pc_T_1 = 32'hFFFC; // @[frontend.scala:89:48] wire [32:0] _if_reg_pc_T = 33'hFFFC; // @[frontend.scala:89:48] wire _io_imem_req_valid_T_1; // @[frontend.scala:146:41] wire [31:0] if_pc_next; // @[frontend.scala:97:25] wire if_buffer_in_valid = io_imem_resp_valid_0; // @[frontend.scala:82:7, :108:27] wire [31:0] io_cpu_debug_if_inst_0 = io_imem_resp_bits_data_0; // @[frontend.scala:82:7] wire [31:0] if_buffer_in_bits_data = io_imem_resp_bits_data_0; // @[frontend.scala:82:7, :108:27] wire [31:0] io_cpu_resp_bits_pc_0; // @[frontend.scala:82:7] wire [31:0] io_cpu_resp_bits_inst_0; // @[frontend.scala:82:7] wire io_cpu_resp_valid_0; // @[frontend.scala:82:7] wire [31:0] io_cpu_debug_if_pc_0; // @[frontend.scala:82:7] wire [31:0] io_imem_req_bits_addr_0; // @[frontend.scala:82:7] wire io_imem_req_valid_0; // @[frontend.scala:82:7] reg [31:0] if_reg_pc; // @[frontend.scala:89:31] assign io_cpu_debug_if_pc_0 = if_reg_pc; // @[frontend.scala:82:7, :89:31] reg exe_reg_valid; // @[frontend.scala:91:31] assign io_cpu_resp_valid_0 = exe_reg_valid; // @[frontend.scala:82:7, :91:31] reg [31:0] exe_reg_pc; // @[frontend.scala:92:27] assign io_cpu_resp_bits_pc_0 = exe_reg_pc; // @[frontend.scala:82:7, :92:27] reg [31:0] exe_reg_inst; // @[frontend.scala:93:27] assign io_cpu_resp_bits_inst_0 = exe_reg_inst; // @[frontend.scala:82:7, :93:27] assign io_imem_req_bits_addr_0 = if_pc_next; // @[frontend.scala:82:7, :97:25] wire _if_val_next_T_2; // @[frontend.scala:111:37] wire if_val_next; // @[frontend.scala:98:26] wire [32:0] _if_pc_plus4_T = {1'h0, if_reg_pc} + 33'h4; // @[frontend.scala:89:31, :101:33] wire [31:0] if_pc_plus4 = _if_pc_plus4_T[31:0]; // @[frontend.scala:101:33] reg if_redirected; // @[frontend.scala:104:31] reg [31:0] if_redirected_pc; // @[frontend.scala:105:30] wire if_buffer_in_ready; // @[frontend.scala:108:27] wire _if_val_next_T = ~io_imem_resp_valid_0; // @[frontend.scala:82:7, :111:63] wire _if_val_next_T_1 = if_buffer_in_ready & _if_val_next_T; // @[frontend.scala:108:27, :111:{60,63}] assign _if_val_next_T_2 = io_cpu_resp_ready_0 | _if_val_next_T_1; // @[frontend.scala:82:7, :111:{37,60}] assign if_val_next = _if_val_next_T_2; // @[frontend.scala:98:26, :111:37]
Generate the Verilog code corresponding to this FIRRTL code module SynchronizerShiftReg_w1_d3_2 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = bits(io.d, 0, 0) inst output_chain of NonSyncResetSynchronizerPrimitiveShiftReg_d3_2 connect output_chain.clock, clock connect output_chain.reset, reset connect output_chain.io.d, _output_T wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module SynchronizerShiftReg_w1_d3_2( // @[SynchronizerReg.scala:169:7] input clock, // @[SynchronizerReg.scala:169:7] input reset, // @[SynchronizerReg.scala:169:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:169:7] wire _output_T = io_d_0; // @[SynchronizerReg.scala:169:7, :173:39] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:169:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:169:7] NonSyncResetSynchronizerPrimitiveShiftReg_d3_2 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (_output_T), // @[SynchronizerReg.scala:173:39] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_58 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_120 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_121 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_58 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DebugTransportModuleJTAG : output io : { flip jtag_clock : Clock, flip jtag_reset : Reset, dmi : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<32>, resp : UInt<2>}}}, flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip jtag_mfr_id : UInt<11>, flip jtag_part_number : UInt<16>, flip jtag_version : UInt<4>} input rf_reset : Reset node _T = asAsyncReset(io.jtag_reset) wire dtmInfo : { reserved1 : UInt<15>, dmireset : UInt<1>, reserved0 : UInt<1>, dmiIdleCycles : UInt<3>, dmiStatus : UInt<2>, debugAddrBits : UInt<6>, debugVersion : UInt<4>} regreset busyReg : UInt<1>, io.jtag_clock, _T, UInt<1>(0h0) regreset stickyBusyReg : UInt<1>, io.jtag_clock, _T, UInt<1>(0h0) regreset stickyNonzeroRespReg : UInt<1>, io.jtag_clock, _T, UInt<1>(0h0) regreset downgradeOpReg : UInt<1>, io.jtag_clock, _T, UInt<1>(0h0) wire busy : UInt<1> wire nonzeroResp : UInt<1> wire busyResp : { addr : UInt<7>, data : UInt<32>, resp : UInt<2>} wire dmiResp : { addr : UInt<7>, data : UInt<32>, resp : UInt<2>} wire nopResp : { addr : UInt<7>, data : UInt<32>, resp : UInt<2>} reg dmiReqReg : { addr : UInt<7>, data : UInt<32>, op : UInt<2>}, io.jtag_clock regreset dmiReqValidReg : UInt<1>, io.jtag_clock, _T, UInt<1>(0h0) wire dmiStatus : UInt<2> node _dmiStatus_T = or(stickyNonzeroRespReg, stickyBusyReg) node _dmiStatus_T_1 = cat(stickyNonzeroRespReg, _dmiStatus_T) connect dmiStatus, _dmiStatus_T_1 connect dtmInfo.debugVersion, UInt<1>(0h1) connect dtmInfo.debugAddrBits, UInt<3>(0h7) connect dtmInfo.dmiStatus, dmiStatus connect dtmInfo.dmiIdleCycles, UInt<3>(0h5) connect dtmInfo.reserved0, UInt<1>(0h0) connect dtmInfo.dmireset, UInt<1>(0h0) connect dtmInfo.reserved1, UInt<1>(0h0) inst dtmInfoChain of CaptureUpdateChain_DTMInfo_To_DTMInfo connect dtmInfoChain.clock, io.jtag_clock connect dtmInfoChain.reset, _T connect dtmInfoChain.io.capture.bits.debugVersion, dtmInfo.debugVersion connect dtmInfoChain.io.capture.bits.debugAddrBits, dtmInfo.debugAddrBits connect dtmInfoChain.io.capture.bits.dmiStatus, dtmInfo.dmiStatus connect dtmInfoChain.io.capture.bits.dmiIdleCycles, dtmInfo.dmiIdleCycles connect dtmInfoChain.io.capture.bits.reserved0, dtmInfo.reserved0 connect dtmInfoChain.io.capture.bits.dmireset, dtmInfo.dmireset connect dtmInfoChain.io.capture.bits.reserved1, dtmInfo.reserved1 inst dmiAccessChain of CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate connect dmiAccessChain.clock, io.jtag_clock connect dmiAccessChain.reset, _T when io.dmi.req.valid : connect busyReg, UInt<1>(0h1) node _T_1 = and(io.dmi.resp.ready, io.dmi.resp.valid) when _T_1 : connect busyReg, UInt<1>(0h0) node _busy_T = eq(io.dmi.resp.valid, UInt<1>(0h0)) node _busy_T_1 = and(busyReg, _busy_T) node _busy_T_2 = or(_busy_T_1, stickyBusyReg) connect busy, _busy_T_2 when dmiAccessChain.io.update.valid : connect downgradeOpReg, UInt<1>(0h0) when dmiAccessChain.io.capture.capture : node _downgradeOpReg_T = eq(busy, UInt<1>(0h0)) node _downgradeOpReg_T_1 = and(_downgradeOpReg_T, nonzeroResp) connect downgradeOpReg, _downgradeOpReg_T_1 connect stickyBusyReg, busy connect stickyNonzeroRespReg, nonzeroResp when dtmInfoChain.io.update.valid : when dtmInfoChain.io.update.bits.dmireset : connect stickyNonzeroRespReg, UInt<1>(0h0) connect stickyBusyReg, UInt<1>(0h0) node _nonzeroResp_T = neq(io.dmi.resp.bits.resp, UInt<1>(0h0)) node _nonzeroResp_T_1 = and(io.dmi.resp.valid, _nonzeroResp_T) node _nonzeroResp_T_2 = or(stickyNonzeroRespReg, _nonzeroResp_T_1) connect nonzeroResp, _nonzeroResp_T_2 node _T_2 = eq(nonzeroResp, UInt<1>(0h0)) node _T_3 = eq(stickyNonzeroRespReg, UInt<1>(0h0)) connect busyResp.addr, UInt<1>(0h0) node _busyResp_resp_T = not(UInt<2>(0h0)) connect busyResp.resp, _busyResp_resp_T connect busyResp.data, UInt<1>(0h0) connect dmiResp.addr, dmiReqReg.addr connect dmiResp.resp, io.dmi.resp.bits.resp connect dmiResp.data, io.dmi.resp.bits.data connect nopResp.addr, UInt<1>(0h0) connect nopResp.resp, UInt<1>(0h0) connect nopResp.data, UInt<1>(0h0) node _dmiAccessChain_io_capture_bits_T = mux(io.dmi.resp.valid, dmiResp, nopResp) node _dmiAccessChain_io_capture_bits_T_1 = mux(busy, busyResp, _dmiAccessChain_io_capture_bits_T) connect dmiAccessChain.io.capture.bits.resp, _dmiAccessChain_io_capture_bits_T_1.resp connect dmiAccessChain.io.capture.bits.data, _dmiAccessChain_io_capture_bits_T_1.data connect dmiAccessChain.io.capture.bits.addr, _dmiAccessChain_io_capture_bits_T_1.addr wire dmiReqValidCheck : UInt<1> connect dmiReqValidCheck, UInt<1>(0h0) node _T_4 = and(io.dmi.req.ready, io.dmi.req.valid) node _T_5 = and(dmiReqValidCheck, _T_4) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(_T) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(io.jtag_clock, UInt<1>(0h1), "Assertion failed: Conflicting updates for dmiReqValidReg, should not happen.\n at DebugTransport.scala:203 assert(!(dmiReqValidCheck && io.dmi.req.fire), \"Conflicting updates for dmiReqValidReg, should not happen.\");\n") : printf assert(io.jtag_clock, _T_6, UInt<1>(0h1), "") : assert when dmiAccessChain.io.update.valid : when stickyBusyReg : skip else : node _T_10 = eq(dmiAccessChain.io.update.bits.op, UInt<1>(0h0)) node _T_11 = or(downgradeOpReg, _T_10) when _T_11 : connect dmiReqReg.addr, UInt<1>(0h0) connect dmiReqReg.data, UInt<1>(0h0) connect dmiReqReg.op, UInt<1>(0h0) else : connect dmiReqReg, dmiAccessChain.io.update.bits connect dmiReqValidReg, UInt<1>(0h1) connect dmiReqValidCheck, UInt<1>(0h1) node _T_12 = and(io.dmi.req.ready, io.dmi.req.valid) when _T_12 : connect dmiReqValidReg, UInt<1>(0h0) node _io_dmi_resp_ready_T = eq(dmiReqReg.op, UInt<2>(0h2)) node _io_dmi_resp_ready_T_1 = eq(busy, UInt<1>(0h0)) node _io_dmi_resp_ready_T_2 = and(dmiAccessChain.io.capture.capture, _io_dmi_resp_ready_T_1) node _io_dmi_resp_ready_T_3 = mux(_io_dmi_resp_ready_T, io.dmi.resp.valid, _io_dmi_resp_ready_T_2) connect io.dmi.resp.ready, _io_dmi_resp_ready_T_3 node _T_13 = eq(dmiReqReg.op, UInt<2>(0h2)) node _T_14 = and(_T_13, dmiAccessChain.io.capture.capture) node _T_15 = and(_T_14, busy) node _T_16 = eq(dmiReqReg.op, UInt<2>(0h2)) node _T_17 = and(_T_16, dmiAccessChain.io.capture.capture) node _T_18 = eq(busy, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(dmiReqReg.op, UInt<1>(0h1)) node _T_21 = and(_T_20, dmiAccessChain.io.capture.capture) node _T_22 = and(_T_21, busy) node _T_23 = eq(dmiReqReg.op, UInt<1>(0h1)) node _T_24 = and(_T_23, dmiAccessChain.io.capture.capture) node _T_25 = eq(busy, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) connect io.dmi.req.valid, dmiReqValidReg connect io.dmi.req.bits, dmiReqReg wire _idcode_WIRE : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>} connect _idcode_WIRE.always1, UInt<1>(0h0) connect _idcode_WIRE.mfrId, UInt<11>(0h0) connect _idcode_WIRE.partNumber, UInt<16>(0h0) connect _idcode_WIRE.version, UInt<4>(0h0) wire idcode : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>} connect idcode, _idcode_WIRE connect idcode.always1, UInt<1>(0h1) connect idcode.version, io.jtag_version connect idcode.partNumber, io.jtag_part_number connect idcode.mfrId, io.jtag_mfr_id wire tapIO : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, control : { flip jtag_reset : AsyncReset}, output : { state : UInt<4>, instruction : UInt<5>, tapIsInTestLogicReset : UInt<1>}, flip idcode : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>}} inst tapIO_idcodeChain of CaptureChain_JTAGIdcodeBundle connect tapIO_idcodeChain.clock, io.jtag_clock connect tapIO_idcodeChain.reset, _T node tapIO_i_lo = cat(tapIO.idcode.mfrId, tapIO.idcode.always1) node tapIO_i_hi = cat(tapIO.idcode.version, tapIO.idcode.partNumber) node tapIO_i = cat(tapIO_i_hi, tapIO_i_lo) node _tapIO_T = rem(tapIO_i, UInt<2>(0h2)) node _tapIO_T_1 = eq(_tapIO_T, UInt<1>(0h1)) node _tapIO_T_2 = asUInt(_T) node _tapIO_T_3 = eq(_tapIO_T_2, UInt<1>(0h0)) when _tapIO_T_3 : node _tapIO_T_4 = eq(_tapIO_T_1, UInt<1>(0h0)) when _tapIO_T_4 : printf(io.jtag_clock, UInt<1>(0h1), "Assertion failed: LSB must be set in IDCODE, see 12.1.1d\n at JtagTap.scala:184 assert(i %%%% 2.U === 1.U, \"LSB must be set in IDCODE, see 12.1.1d\")\n") : tapIO_printf assert(io.jtag_clock, _tapIO_T_1, UInt<1>(0h1), "") : tapIO_assert node _tapIO_T_5 = shr(tapIO_i, 1) node _tapIO_T_6 = shl(UInt<1>(0h1), 11) node _tapIO_T_7 = sub(_tapIO_T_6, UInt<1>(0h1)) node _tapIO_T_8 = tail(_tapIO_T_7, 1) node _tapIO_T_9 = and(_tapIO_T_5, _tapIO_T_8) node _tapIO_T_10 = neq(_tapIO_T_9, UInt<7>(0h7f)) node _tapIO_T_11 = asUInt(_T) node _tapIO_T_12 = eq(_tapIO_T_11, UInt<1>(0h0)) when _tapIO_T_12 : node _tapIO_T_13 = eq(_tapIO_T_10, UInt<1>(0h0)) when _tapIO_T_13 : printf(io.jtag_clock, UInt<1>(0h1), "Assertion failed: IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b\n at JtagTap.scala:185 assert(((i >> 1) & ((1.U << 11) - 1.U)) =/= JtagIdcode.dummyMfrId.U,\n") : tapIO_printf_1 assert(io.jtag_clock, _tapIO_T_10, UInt<1>(0h1), "") : tapIO_assert_1 connect tapIO_idcodeChain.io.capture.bits.always1, tapIO.idcode.always1 connect tapIO_idcodeChain.io.capture.bits.mfrId, tapIO.idcode.mfrId connect tapIO_idcodeChain.io.capture.bits.partNumber, tapIO.idcode.partNumber connect tapIO_idcodeChain.io.capture.bits.version, tapIO.idcode.version inst tapIO_controllerInternal of JtagTapController connect tapIO_controllerInternal.clock, io.jtag_clock connect tapIO_controllerInternal.reset, _T wire tapIO_unusedChainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>} connect tapIO_unusedChainOut.shift, UInt<1>(0h0) connect tapIO_unusedChainOut.data, UInt<1>(0h0) connect tapIO_unusedChainOut.capture, UInt<1>(0h0) connect tapIO_unusedChainOut.update, UInt<1>(0h0) inst tapIO_bypassChain of JtagBypassChain connect tapIO_bypassChain.clock, io.jtag_clock connect tapIO_bypassChain.reset, _T connect tapIO_bypassChain.io.chainIn.update, tapIO_controllerInternal.io.dataChainOut.update connect tapIO_bypassChain.io.chainIn.capture, tapIO_controllerInternal.io.dataChainOut.capture connect tapIO_bypassChain.io.chainIn.data, tapIO_controllerInternal.io.dataChainOut.data connect tapIO_bypassChain.io.chainIn.shift, tapIO_controllerInternal.io.dataChainOut.shift node tapIO_chainToSelect_0_2 = eq(tapIO_controllerInternal.io.output.instruction, UInt<5>(0h1)) node tapIO_chainToSelect_1_2 = eq(tapIO_controllerInternal.io.output.instruction, UInt<5>(0h10)) node tapIO_chainToSelect_2_2 = eq(tapIO_controllerInternal.io.output.instruction, UInt<5>(0h11)) connect tapIO_controllerInternal.io.dataChainIn.update, tapIO_bypassChain.io.chainOut.update connect tapIO_controllerInternal.io.dataChainIn.capture, tapIO_bypassChain.io.chainOut.capture connect tapIO_controllerInternal.io.dataChainIn.data, tapIO_bypassChain.io.chainOut.data connect tapIO_controllerInternal.io.dataChainIn.shift, tapIO_bypassChain.io.chainOut.shift when UInt<1>(0h0) : skip else : when tapIO_chainToSelect_0_2 : connect tapIO_controllerInternal.io.dataChainIn.update, tapIO_idcodeChain.io.chainOut.update connect tapIO_controllerInternal.io.dataChainIn.capture, tapIO_idcodeChain.io.chainOut.capture connect tapIO_controllerInternal.io.dataChainIn.data, tapIO_idcodeChain.io.chainOut.data connect tapIO_controllerInternal.io.dataChainIn.shift, tapIO_idcodeChain.io.chainOut.shift else : when tapIO_chainToSelect_1_2 : connect tapIO_controllerInternal.io.dataChainIn.update, dtmInfoChain.io.chainOut.update connect tapIO_controllerInternal.io.dataChainIn.capture, dtmInfoChain.io.chainOut.capture connect tapIO_controllerInternal.io.dataChainIn.data, dtmInfoChain.io.chainOut.data connect tapIO_controllerInternal.io.dataChainIn.shift, dtmInfoChain.io.chainOut.shift else : when tapIO_chainToSelect_2_2 : connect tapIO_controllerInternal.io.dataChainIn.update, dmiAccessChain.io.chainOut.update connect tapIO_controllerInternal.io.dataChainIn.capture, dmiAccessChain.io.chainOut.capture connect tapIO_controllerInternal.io.dataChainIn.data, dmiAccessChain.io.chainOut.data connect tapIO_controllerInternal.io.dataChainIn.shift, dmiAccessChain.io.chainOut.shift else : connect tapIO_controllerInternal.io.dataChainIn.update, tapIO_bypassChain.io.chainOut.update connect tapIO_controllerInternal.io.dataChainIn.capture, tapIO_bypassChain.io.chainOut.capture connect tapIO_controllerInternal.io.dataChainIn.data, tapIO_bypassChain.io.chainOut.data connect tapIO_controllerInternal.io.dataChainIn.shift, tapIO_bypassChain.io.chainOut.shift when tapIO_chainToSelect_0_2 : connect tapIO_idcodeChain.io.chainIn.update, tapIO_controllerInternal.io.dataChainOut.update connect tapIO_idcodeChain.io.chainIn.capture, tapIO_controllerInternal.io.dataChainOut.capture connect tapIO_idcodeChain.io.chainIn.data, tapIO_controllerInternal.io.dataChainOut.data connect tapIO_idcodeChain.io.chainIn.shift, tapIO_controllerInternal.io.dataChainOut.shift else : connect tapIO_idcodeChain.io.chainIn.update, tapIO_unusedChainOut.update connect tapIO_idcodeChain.io.chainIn.capture, tapIO_unusedChainOut.capture connect tapIO_idcodeChain.io.chainIn.data, tapIO_unusedChainOut.data connect tapIO_idcodeChain.io.chainIn.shift, tapIO_unusedChainOut.shift when tapIO_chainToSelect_1_2 : connect dtmInfoChain.io.chainIn.update, tapIO_controllerInternal.io.dataChainOut.update connect dtmInfoChain.io.chainIn.capture, tapIO_controllerInternal.io.dataChainOut.capture connect dtmInfoChain.io.chainIn.data, tapIO_controllerInternal.io.dataChainOut.data connect dtmInfoChain.io.chainIn.shift, tapIO_controllerInternal.io.dataChainOut.shift else : connect dtmInfoChain.io.chainIn.update, tapIO_unusedChainOut.update connect dtmInfoChain.io.chainIn.capture, tapIO_unusedChainOut.capture connect dtmInfoChain.io.chainIn.data, tapIO_unusedChainOut.data connect dtmInfoChain.io.chainIn.shift, tapIO_unusedChainOut.shift when tapIO_chainToSelect_2_2 : connect dmiAccessChain.io.chainIn.update, tapIO_controllerInternal.io.dataChainOut.update connect dmiAccessChain.io.chainIn.capture, tapIO_controllerInternal.io.dataChainOut.capture connect dmiAccessChain.io.chainIn.data, tapIO_controllerInternal.io.dataChainOut.data connect dmiAccessChain.io.chainIn.shift, tapIO_controllerInternal.io.dataChainOut.shift else : connect dmiAccessChain.io.chainIn.update, tapIO_unusedChainOut.update connect dmiAccessChain.io.chainIn.capture, tapIO_unusedChainOut.capture connect dmiAccessChain.io.chainIn.data, tapIO_unusedChainOut.data connect dmiAccessChain.io.chainIn.shift, tapIO_unusedChainOut.shift connect tapIO_controllerInternal.io.jtag, tapIO.jtag connect tapIO_controllerInternal.io.control.jtag_reset, tapIO.control.jtag_reset connect tapIO.output, tapIO_controllerInternal.io.output connect tapIO.idcode.always1, idcode.always1 connect tapIO.idcode.mfrId, idcode.mfrId connect tapIO.idcode.partNumber, idcode.partNumber connect tapIO.idcode.version, idcode.version connect tapIO.jtag, io.jtag node _tapIO_control_jtag_reset_T = asAsyncReset(io.jtag_reset) connect tapIO.control.jtag_reset, _tapIO_control_jtag_reset_T when tapIO.output.tapIsInTestLogicReset : connect busyReg, UInt<1>(0h0) connect stickyBusyReg, UInt<1>(0h0) connect stickyNonzeroRespReg, UInt<1>(0h0) connect downgradeOpReg, UInt<1>(0h0) connect dmiReqValidReg, UInt<1>(0h0)
module DebugTransportModuleJTAG( // @[DebugTransport.scala:73:7] input io_jtag_clock, // @[DebugTransport.scala:76:14] input io_jtag_reset, // @[DebugTransport.scala:76:14] input io_dmi_req_ready, // @[DebugTransport.scala:76:14] output io_dmi_req_valid, // @[DebugTransport.scala:76:14] output [6:0] io_dmi_req_bits_addr, // @[DebugTransport.scala:76:14] output [31:0] io_dmi_req_bits_data, // @[DebugTransport.scala:76:14] output [1:0] io_dmi_req_bits_op, // @[DebugTransport.scala:76:14] output io_dmi_resp_ready, // @[DebugTransport.scala:76:14] input io_dmi_resp_valid, // @[DebugTransport.scala:76:14] input [31:0] io_dmi_resp_bits_data, // @[DebugTransport.scala:76:14] input [1:0] io_dmi_resp_bits_resp, // @[DebugTransport.scala:76:14] input io_jtag_TMS, // @[DebugTransport.scala:76:14] input io_jtag_TDI, // @[DebugTransport.scala:76:14] output io_jtag_TDO_data // @[DebugTransport.scala:76:14] ); wire _GEN; // @[DebugTransport.scala:202:34, :206:26, :208:97] wire _GEN_0; // @[DebugTransport.scala:202:34, :208:97, :216:24] wire _tapIO_bypassChain_io_chainOut_data; // @[JtagTap.scala:207:29] wire [4:0] _tapIO_controllerInternal_io_output_instruction; // @[JtagTap.scala:199:36] wire _tapIO_controllerInternal_io_output_tapIsInTestLogicReset; // @[JtagTap.scala:199:36] wire _tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala:199:36] wire _tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala:199:36] wire _tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala:199:36] wire _tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala:199:36] wire _tapIO_idcodeChain_io_chainOut_data; // @[JtagTap.scala:181:33] wire _dmiAccessChain_io_chainOut_data; // @[DebugTransport.scala:134:31] wire _dmiAccessChain_io_capture_capture; // @[DebugTransport.scala:134:31] wire _dmiAccessChain_io_update_valid; // @[DebugTransport.scala:134:31] wire [6:0] _dmiAccessChain_io_update_bits_addr; // @[DebugTransport.scala:134:31] wire [31:0] _dmiAccessChain_io_update_bits_data; // @[DebugTransport.scala:134:31] wire [1:0] _dmiAccessChain_io_update_bits_op; // @[DebugTransport.scala:134:31] wire _dtmInfoChain_io_chainOut_data; // @[DebugTransport.scala:128:29] wire _dtmInfoChain_io_update_valid; // @[DebugTransport.scala:128:29] wire _dtmInfoChain_io_update_bits_dmireset; // @[DebugTransport.scala:128:29] reg busyReg; // @[DebugTransport.scala:96:24] reg stickyBusyReg; // @[DebugTransport.scala:97:30] reg stickyNonzeroRespReg; // @[DebugTransport.scala:98:37] reg downgradeOpReg; // @[DebugTransport.scala:100:31] reg [6:0] dmiReqReg_addr; // @[DebugTransport.scala:110:23] reg [31:0] dmiReqReg_data; // @[DebugTransport.scala:110:23] reg [1:0] dmiReqReg_op; // @[DebugTransport.scala:110:23] reg dmiReqValidReg; // @[DebugTransport.scala:111:31] wire _busy_T_1 = busyReg & ~io_dmi_resp_valid; // @[DebugTransport.scala:96:24, :155:{20,22}] wire busy = _busy_T_1 | stickyBusyReg; // @[DebugTransport.scala:97:30, :155:{20,42}] wire _nonzeroResp_T_1 = io_dmi_resp_valid & (|io_dmi_resp_bits_resp); // @[DebugTransport.scala:178:{60,85}] wire _GEN_1 = busy | ~io_dmi_resp_valid; // @[DebugTransport.scala:155:42, :197:40] wire _GEN_2 = io_dmi_req_ready & dmiReqValidReg; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64ToRaw_mulAddZ31_1 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} regreset cycleNum_A : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_B : UInt<4>, clock, reset, UInt<4>(0h0) regreset cycleNum_C : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_E : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid_PA : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PA : UInt<1>, clock reg majorExc_PA : UInt<1>, clock reg isNaN_PA : UInt<1>, clock reg isInf_PA : UInt<1>, clock reg isZero_PA : UInt<1>, clock reg sign_PA : UInt<1>, clock reg sExp_PA : SInt<13>, clock reg fractB_PA : UInt<52>, clock reg fractA_PA : UInt<52>, clock reg roundingMode_PA : UInt<3>, clock regreset valid_PB : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PB : UInt<1>, clock reg majorExc_PB : UInt<1>, clock reg isNaN_PB : UInt<1>, clock reg isInf_PB : UInt<1>, clock reg isZero_PB : UInt<1>, clock reg sign_PB : UInt<1>, clock reg sExp_PB : SInt<13>, clock reg bit0FractA_PB : UInt<1>, clock reg fractB_PB : UInt<52>, clock reg roundingMode_PB : UInt<3>, clock regreset valid_PC : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PC : UInt<1>, clock reg majorExc_PC : UInt<1>, clock reg isNaN_PC : UInt<1>, clock reg isInf_PC : UInt<1>, clock reg isZero_PC : UInt<1>, clock reg sign_PC : UInt<1>, clock reg sExp_PC : SInt<13>, clock reg bit0FractA_PC : UInt<1>, clock reg fractB_PC : UInt<52>, clock reg roundingMode_PC : UInt<3>, clock reg fractR0_A : UInt<9>, clock reg hiSqrR0_A_sqrt : UInt<10>, clock reg partNegSigma0_A : UInt<21>, clock reg nextMulAdd9A_A : UInt<9>, clock reg nextMulAdd9B_A : UInt<9>, clock reg ER1_B_sqrt : UInt<17>, clock reg ESqrR1_B_sqrt : UInt<32>, clock reg sigX1_B : UInt<58>, clock reg sqrSigma1_C : UInt<33>, clock reg sigXN_C : UInt<58>, clock reg u_C_sqrt : UInt<31>, clock reg E_E_div : UInt<1>, clock reg sigT_E : UInt<54>, clock reg isNegRemT_E : UInt<1>, clock reg isZeroRemT_E : UInt<1>, clock wire ready_PA : UInt<1> wire ready_PB : UInt<1> wire ready_PC : UInt<1> wire leaving_PA : UInt<1> wire leaving_PB : UInt<1> wire leaving_PC : UInt<1> wire zSigma1_B4 : UInt wire sigXNU_B3_CX : UInt wire zComplSigT_C1_sqrt : UInt wire zComplSigT_C1 : UInt node _cyc_S_div_T = and(io.inReady_div, io.inValid) node _cyc_S_div_T_1 = eq(io.sqrtOp, UInt<1>(0h0)) node cyc_S_div = and(_cyc_S_div_T, _cyc_S_div_T_1) node _cyc_S_sqrt_T = and(io.inReady_sqrt, io.inValid) node cyc_S_sqrt = and(_cyc_S_sqrt_T, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) node rawA_S_exp = bits(io.a, 63, 52) node _rawA_S_isZero_T = bits(rawA_S_exp, 11, 9) node rawA_S_isZero = eq(_rawA_S_isZero_T, UInt<1>(0h0)) node _rawA_S_isSpecial_T = bits(rawA_S_exp, 11, 10) node rawA_S_isSpecial = eq(_rawA_S_isSpecial_T, UInt<2>(0h3)) wire rawA_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_S_out_isNaN_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isNaN_T_1 = and(rawA_S_isSpecial, _rawA_S_out_isNaN_T) connect rawA_S.isNaN, _rawA_S_out_isNaN_T_1 node _rawA_S_out_isInf_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isInf_T_1 = eq(_rawA_S_out_isInf_T, UInt<1>(0h0)) node _rawA_S_out_isInf_T_2 = and(rawA_S_isSpecial, _rawA_S_out_isInf_T_1) connect rawA_S.isInf, _rawA_S_out_isInf_T_2 connect rawA_S.isZero, rawA_S_isZero node _rawA_S_out_sign_T = bits(io.a, 64, 64) connect rawA_S.sign, _rawA_S_out_sign_T node _rawA_S_out_sExp_T = cvt(rawA_S_exp) connect rawA_S.sExp, _rawA_S_out_sExp_T node _rawA_S_out_sig_T = eq(rawA_S_isZero, UInt<1>(0h0)) node _rawA_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_S_out_sig_T) node _rawA_S_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_S_out_sig_T_3 = cat(_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2) connect rawA_S.sig, _rawA_S_out_sig_T_3 node rawB_S_exp = bits(io.b, 63, 52) node _rawB_S_isZero_T = bits(rawB_S_exp, 11, 9) node rawB_S_isZero = eq(_rawB_S_isZero_T, UInt<1>(0h0)) node _rawB_S_isSpecial_T = bits(rawB_S_exp, 11, 10) node rawB_S_isSpecial = eq(_rawB_S_isSpecial_T, UInt<2>(0h3)) wire rawB_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_S_out_isNaN_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isNaN_T_1 = and(rawB_S_isSpecial, _rawB_S_out_isNaN_T) connect rawB_S.isNaN, _rawB_S_out_isNaN_T_1 node _rawB_S_out_isInf_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isInf_T_1 = eq(_rawB_S_out_isInf_T, UInt<1>(0h0)) node _rawB_S_out_isInf_T_2 = and(rawB_S_isSpecial, _rawB_S_out_isInf_T_1) connect rawB_S.isInf, _rawB_S_out_isInf_T_2 connect rawB_S.isZero, rawB_S_isZero node _rawB_S_out_sign_T = bits(io.b, 64, 64) connect rawB_S.sign, _rawB_S_out_sign_T node _rawB_S_out_sExp_T = cvt(rawB_S_exp) connect rawB_S.sExp, _rawB_S_out_sExp_T node _rawB_S_out_sig_T = eq(rawB_S_isZero, UInt<1>(0h0)) node _rawB_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_S_out_sig_T) node _rawB_S_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_S_out_sig_T_3 = cat(_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2) connect rawB_S.sig, _rawB_S_out_sig_T_3 node _notSigNaNIn_invalidExc_S_div_T = and(rawA_S.isZero, rawB_S.isZero) node _notSigNaNIn_invalidExc_S_div_T_1 = and(rawA_S.isInf, rawB_S.isInf) node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) node _notSigNaNIn_invalidExc_S_sqrt_T = eq(rawB_S.isNaN, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(rawB_S.isZero, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, rawB_S.sign) node _majorExc_S_T = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) node _majorExc_S_T_2 = and(rawB_S.isNaN, _majorExc_S_T_1) node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) node _majorExc_S_T_4 = bits(rawA_S.sig, 51, 51) node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) node _majorExc_S_T_6 = and(rawA_S.isNaN, _majorExc_S_T_5) node _majorExc_S_T_7 = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) node _majorExc_S_T_9 = and(rawB_S.isNaN, _majorExc_S_T_8) node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) node _majorExc_S_T_12 = eq(rawA_S.isNaN, UInt<1>(0h0)) node _majorExc_S_T_13 = eq(rawA_S.isInf, UInt<1>(0h0)) node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) node _majorExc_S_T_15 = and(_majorExc_S_T_14, rawB_S.isZero) node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) node _isNaN_S_T = or(rawB_S.isNaN, notSigNaNIn_invalidExc_S_sqrt) node _isNaN_S_T_1 = or(rawA_S.isNaN, rawB_S.isNaN) node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) node _isInf_S_T = or(rawA_S.isInf, rawB_S.isZero) node isInf_S = mux(io.sqrtOp, rawB_S.isInf, _isInf_S_T) node _isZero_S_T = or(rawA_S.isZero, rawB_S.isInf) node isZero_S = mux(io.sqrtOp, rawB_S.isZero, _isZero_S_T) node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sign_S_T_1 = and(_sign_S_T, rawA_S.sign) node sign_S = xor(_sign_S_T_1, rawB_S.sign) node _specialCaseA_S_T = or(rawA_S.isNaN, rawA_S.isInf) node specialCaseA_S = or(_specialCaseA_S_T, rawA_S.isZero) node _specialCaseB_S_T = or(rawB_S.isNaN, rawB_S.isInf) node specialCaseB_S = or(_specialCaseB_S_T, rawB_S.isZero) node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) node _normalCase_S_sqrt_T = eq(specialCaseB_S, UInt<1>(0h0)) node _normalCase_S_sqrt_T_1 = eq(rawB_S.sign, UInt<1>(0h0)) node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node _sExpQuot_S_div_T = bits(rawB_S.sExp, 11, 11) node _sExpQuot_S_div_T_1 = bits(rawB_S.sExp, 10, 0) node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) node sExpQuot_S_div = add(rawA_S.sExp, _sExpQuot_S_div_T_4) node _sSatExpQuot_S_div_T = leq(asSInt(UInt<13>(0he00)), sExpQuot_S_div) node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 12, 9) node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 8, 0) node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) node _T = neq(cycleNum_A, UInt<1>(0h0)) node _T_1 = or(entering_PA_normalCase, _T) when _T_1 : node _cycleNum_A_T = mux(entering_PA_normalCase_div, UInt<2>(0h3), UInt<1>(0h0)) node _cycleNum_A_T_1 = mux(entering_PA_normalCase_sqrt, UInt<3>(0h6), UInt<1>(0h0)) node _cycleNum_A_T_2 = or(_cycleNum_A_T, _cycleNum_A_T_1) node _cycleNum_A_T_3 = eq(entering_PA_normalCase, UInt<1>(0h0)) node _cycleNum_A_T_4 = sub(cycleNum_A, UInt<1>(0h1)) node _cycleNum_A_T_5 = tail(_cycleNum_A_T_4, 1) node _cycleNum_A_T_6 = mux(_cycleNum_A_T_3, _cycleNum_A_T_5, UInt<1>(0h0)) node _cycleNum_A_T_7 = or(_cycleNum_A_T_2, _cycleNum_A_T_6) connect cycleNum_A, _cycleNum_A_T_7 node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>(0h6)) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>(0h5)) node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>(0h4)) node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) node cyc_A3 = eq(cycleNum_A, UInt<2>(0h3)) node cyc_A2 = eq(cycleNum_A, UInt<2>(0h2)) node cyc_A1 = eq(cycleNum_A, UInt<1>(0h1)) node _cyc_A3_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A3_div = and(cyc_A3, _cyc_A3_div_T) node _cyc_A2_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A2_div = and(cyc_A2, _cyc_A2_div_T) node _cyc_A1_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A1_div = and(cyc_A1, _cyc_A1_div_T) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) node _T_2 = neq(cycleNum_B, UInt<1>(0h0)) node _T_3 = or(cyc_A1, _T_2) when _T_3 : node _cycleNum_B_T = mux(sqrtOp_PA, UInt<4>(0ha), UInt<3>(0h6)) node _cycleNum_B_T_1 = sub(cycleNum_B, UInt<1>(0h1)) node _cycleNum_B_T_2 = tail(_cycleNum_B_T_1, 1) node _cycleNum_B_T_3 = mux(cyc_A1, _cycleNum_B_T, _cycleNum_B_T_2) connect cycleNum_B, _cycleNum_B_T_3 node cyc_B10_sqrt = eq(cycleNum_B, UInt<4>(0ha)) node cyc_B9_sqrt = eq(cycleNum_B, UInt<4>(0h9)) node cyc_B8_sqrt = eq(cycleNum_B, UInt<4>(0h8)) node cyc_B7_sqrt = eq(cycleNum_B, UInt<3>(0h7)) node cyc_B6 = eq(cycleNum_B, UInt<3>(0h6)) node cyc_B5 = eq(cycleNum_B, UInt<3>(0h5)) node cyc_B4 = eq(cycleNum_B, UInt<3>(0h4)) node cyc_B3 = eq(cycleNum_B, UInt<2>(0h3)) node cyc_B2 = eq(cycleNum_B, UInt<2>(0h2)) node cyc_B1 = eq(cycleNum_B, UInt<1>(0h1)) node _cyc_B6_div_T = and(cyc_B6, valid_PA) node _cyc_B6_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B6_div = and(_cyc_B6_div_T, _cyc_B6_div_T_1) node _cyc_B5_div_T = and(cyc_B5, valid_PA) node _cyc_B5_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B5_div = and(_cyc_B5_div_T, _cyc_B5_div_T_1) node _cyc_B4_div_T = and(cyc_B4, valid_PA) node _cyc_B4_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B4_div = and(_cyc_B4_div_T, _cyc_B4_div_T_1) node _cyc_B3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B3_div = and(cyc_B3, _cyc_B3_div_T) node _cyc_B2_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B2_div = and(cyc_B2, _cyc_B2_div_T) node _cyc_B1_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B1_div = and(cyc_B1, _cyc_B1_div_T) node _cyc_B6_sqrt_T = and(cyc_B6, valid_PB) node cyc_B6_sqrt = and(_cyc_B6_sqrt_T, sqrtOp_PB) node _cyc_B5_sqrt_T = and(cyc_B5, valid_PB) node cyc_B5_sqrt = and(_cyc_B5_sqrt_T, sqrtOp_PB) node _cyc_B4_sqrt_T = and(cyc_B4, valid_PB) node cyc_B4_sqrt = and(_cyc_B4_sqrt_T, sqrtOp_PB) node cyc_B3_sqrt = and(cyc_B3, sqrtOp_PB) node cyc_B2_sqrt = and(cyc_B2, sqrtOp_PB) node cyc_B1_sqrt = and(cyc_B1, sqrtOp_PB) node _T_4 = neq(cycleNum_C, UInt<1>(0h0)) node _T_5 = or(cyc_B1, _T_4) when _T_5 : node _cycleNum_C_T = mux(sqrtOp_PB, UInt<3>(0h6), UInt<3>(0h5)) node _cycleNum_C_T_1 = sub(cycleNum_C, UInt<1>(0h1)) node _cycleNum_C_T_2 = tail(_cycleNum_C_T_1, 1) node _cycleNum_C_T_3 = mux(cyc_B1, _cycleNum_C_T, _cycleNum_C_T_2) connect cycleNum_C, _cycleNum_C_T_3 node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>(0h6)) node cyc_C5 = eq(cycleNum_C, UInt<3>(0h5)) node cyc_C4 = eq(cycleNum_C, UInt<3>(0h4)) node cyc_C3 = eq(cycleNum_C, UInt<2>(0h3)) node cyc_C2 = eq(cycleNum_C, UInt<2>(0h2)) node cyc_C1 = eq(cycleNum_C, UInt<1>(0h1)) node _cyc_C5_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C5_div = and(cyc_C5, _cyc_C5_div_T) node _cyc_C4_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C4_div = and(cyc_C4, _cyc_C4_div_T) node _cyc_C3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C3_div = and(cyc_C3, _cyc_C3_div_T) node _cyc_C2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C2_div = and(cyc_C2, _cyc_C2_div_T) node _cyc_C1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C1_div = and(cyc_C1, _cyc_C1_div_T) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) node _T_6 = neq(cycleNum_E, UInt<1>(0h0)) node _T_7 = or(cyc_C1, _T_6) when _T_7 : node _cycleNum_E_T = sub(cycleNum_E, UInt<1>(0h1)) node _cycleNum_E_T_1 = tail(_cycleNum_E_T, 1) node _cycleNum_E_T_2 = mux(cyc_C1, UInt<3>(0h4), _cycleNum_E_T_1) connect cycleNum_E, _cycleNum_E_T_2 node cyc_E4 = eq(cycleNum_E, UInt<3>(0h4)) node cyc_E3 = eq(cycleNum_E, UInt<2>(0h3)) node cyc_E2 = eq(cycleNum_E, UInt<2>(0h2)) node cyc_E1 = eq(cycleNum_E, UInt<1>(0h1)) node _cyc_E4_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E4_div = and(cyc_E4, _cyc_E4_div_T) node _cyc_E3_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E3_div = and(cyc_E3, _cyc_E3_div_T) node _cyc_E2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E2_div = and(cyc_E2, _cyc_E2_div_T) node _cyc_E1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E1_div = and(cyc_E1, _cyc_E1_div_T) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node _entering_PA_T = eq(ready_PB, UInt<1>(0h0)) node _entering_PA_T_1 = or(valid_PA, _entering_PA_T) node _entering_PA_T_2 = and(cyc_S, _entering_PA_T_1) node entering_PA = or(entering_PA_normalCase, _entering_PA_T_2) node _T_8 = or(entering_PA, leaving_PA) when _T_8 : connect valid_PA, entering_PA when entering_PA : connect sqrtOp_PA, io.sqrtOp connect majorExc_PA, majorExc_S connect isNaN_PA, isNaN_S connect isInf_PA, isInf_S connect isZero_PA, isZero_S connect sign_PA, sign_S when entering_PA_normalCase : node _sExp_PA_T = mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div) connect sExp_PA, _sExp_PA_T node _fractB_PA_T = bits(rawB_S.sig, 51, 0) connect fractB_PA, _fractB_PA_T connect roundingMode_PA, io.roundingMode when entering_PA_normalCase_div : node _fractA_PA_T = bits(rawA_S.sig, 51, 0) connect fractA_PA, _fractA_PA_T node _normalCase_PA_T = eq(isNaN_PA, UInt<1>(0h0)) node _normalCase_PA_T_1 = eq(isInf_PA, UInt<1>(0h0)) node _normalCase_PA_T_2 = and(_normalCase_PA_T, _normalCase_PA_T_1) node _normalCase_PA_T_3 = eq(isZero_PA, UInt<1>(0h0)) node normalCase_PA = and(_normalCase_PA_T_2, _normalCase_PA_T_3) node sigA_PA = cat(UInt<1>(0h1), fractA_PA) node sigB_PA = cat(UInt<1>(0h1), fractB_PA) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) node _leaving_PA_T = and(valid_PA, valid_leaving_PA) connect leaving_PA, _leaving_PA_T node _ready_PA_T = eq(valid_PA, UInt<1>(0h0)) node _ready_PA_T_1 = or(_ready_PA_T, valid_leaving_PA) connect ready_PA, _ready_PA_T_1 node _entering_PB_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PB_S_T_1 = and(cyc_S, _entering_PB_S_T) node _entering_PB_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PB_S_T_3 = and(_entering_PB_S_T_1, _entering_PB_S_T_2) node _entering_PB_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PB_S_T_5 = eq(ready_PC, UInt<1>(0h0)) node _entering_PB_S_T_6 = and(_entering_PB_S_T_4, _entering_PB_S_T_5) node _entering_PB_S_T_7 = or(leaving_PB, _entering_PB_S_T_6) node entering_PB_S = and(_entering_PB_S_T_3, _entering_PB_S_T_7) node _entering_PB_normalCase_T = and(valid_PA, normalCase_PA) node entering_PB_normalCase = and(_entering_PB_normalCase_T, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) node _T_9 = or(entering_PB, leaving_PB) when _T_9 : connect valid_PB, entering_PB when entering_PB : node _sqrtOp_PB_T = mux(valid_PA, sqrtOp_PA, io.sqrtOp) connect sqrtOp_PB, _sqrtOp_PB_T node _majorExc_PB_T = mux(valid_PA, majorExc_PA, majorExc_S) connect majorExc_PB, _majorExc_PB_T node _isNaN_PB_T = mux(valid_PA, isNaN_PA, isNaN_S) connect isNaN_PB, _isNaN_PB_T node _isInf_PB_T = mux(valid_PA, isInf_PA, isInf_S) connect isInf_PB, _isInf_PB_T node _isZero_PB_T = mux(valid_PA, isZero_PA, isZero_S) connect isZero_PB, _isZero_PB_T node _sign_PB_T = mux(valid_PA, sign_PA, sign_S) connect sign_PB, _sign_PB_T when entering_PB_normalCase : connect sExp_PB, sExp_PA node _bit0FractA_PB_T = bits(fractA_PA, 0, 0) connect bit0FractA_PB, _bit0FractA_PB_T connect fractB_PB, fractB_PA node _roundingMode_PB_T = mux(valid_PA, roundingMode_PA, io.roundingMode) connect roundingMode_PB, _roundingMode_PB_T node _normalCase_PB_T = eq(isNaN_PB, UInt<1>(0h0)) node _normalCase_PB_T_1 = eq(isInf_PB, UInt<1>(0h0)) node _normalCase_PB_T_2 = and(_normalCase_PB_T, _normalCase_PB_T_1) node _normalCase_PB_T_3 = eq(isZero_PB, UInt<1>(0h0)) node normalCase_PB = and(_normalCase_PB_T_2, _normalCase_PB_T_3) node valid_leaving_PB = mux(normalCase_PB, cyc_C3, ready_PC) node _leaving_PB_T = and(valid_PB, valid_leaving_PB) connect leaving_PB, _leaving_PB_T node _ready_PB_T = eq(valid_PB, UInt<1>(0h0)) node _ready_PB_T_1 = or(_ready_PB_T, valid_leaving_PB) connect ready_PB, _ready_PB_T_1 node _entering_PC_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PC_S_T_1 = and(cyc_S, _entering_PC_S_T) node _entering_PC_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PC_S_T_3 = and(_entering_PC_S_T_1, _entering_PC_S_T_2) node _entering_PC_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PC_S_T_5 = and(_entering_PC_S_T_3, _entering_PC_S_T_4) node entering_PC_S = and(_entering_PC_S_T_5, ready_PC) node _entering_PC_normalCase_T = and(valid_PB, normalCase_PB) node entering_PC_normalCase = and(_entering_PC_normalCase_T, cyc_C3) node entering_PC = or(entering_PC_S, leaving_PB) node _T_10 = or(entering_PC, leaving_PC) when _T_10 : connect valid_PC, entering_PC when entering_PC : node _sqrtOp_PC_T = mux(valid_PB, sqrtOp_PB, io.sqrtOp) connect sqrtOp_PC, _sqrtOp_PC_T node _majorExc_PC_T = mux(valid_PB, majorExc_PB, majorExc_S) connect majorExc_PC, _majorExc_PC_T node _isNaN_PC_T = mux(valid_PB, isNaN_PB, isNaN_S) connect isNaN_PC, _isNaN_PC_T node _isInf_PC_T = mux(valid_PB, isInf_PB, isInf_S) connect isInf_PC, _isInf_PC_T node _isZero_PC_T = mux(valid_PB, isZero_PB, isZero_S) connect isZero_PC, _isZero_PC_T node _sign_PC_T = mux(valid_PB, sign_PB, sign_S) connect sign_PC, _sign_PC_T when entering_PC_normalCase : connect sExp_PC, sExp_PB connect bit0FractA_PC, bit0FractA_PB connect fractB_PC, fractB_PB node _roundingMode_PC_T = mux(valid_PB, roundingMode_PB, io.roundingMode) connect roundingMode_PC, _roundingMode_PC_T node _normalCase_PC_T = eq(isNaN_PC, UInt<1>(0h0)) node _normalCase_PC_T_1 = eq(isInf_PC, UInt<1>(0h0)) node _normalCase_PC_T_2 = and(_normalCase_PC_T, _normalCase_PC_T_1) node _normalCase_PC_T_3 = eq(isZero_PC, UInt<1>(0h0)) node normalCase_PC = and(_normalCase_PC_T_2, _normalCase_PC_T_3) node sigB_PC = cat(UInt<1>(0h1), fractB_PC) node _valid_leaving_PC_T = eq(normalCase_PC, UInt<1>(0h0)) node valid_leaving_PC = or(_valid_leaving_PC_T, cyc_E1) node _leaving_PC_T = and(valid_PC, valid_leaving_PC) connect leaving_PC, _leaving_PC_T node _ready_PC_T = eq(valid_PC, UInt<1>(0h0)) node _ready_PC_T_1 = or(_ready_PC_T, valid_leaving_PC) connect ready_PC, _ready_PC_T_1 node _io_inReady_div_T = eq(cyc_B7_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_1 = and(ready_PA, _io_inReady_div_T) node _io_inReady_div_T_2 = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_3 = and(_io_inReady_div_T_1, _io_inReady_div_T_2) node _io_inReady_div_T_4 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_5 = and(_io_inReady_div_T_3, _io_inReady_div_T_4) node _io_inReady_div_T_6 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_7 = and(_io_inReady_div_T_5, _io_inReady_div_T_6) node _io_inReady_div_T_8 = eq(cyc_B3, UInt<1>(0h0)) node _io_inReady_div_T_9 = and(_io_inReady_div_T_7, _io_inReady_div_T_8) node _io_inReady_div_T_10 = eq(cyc_B2, UInt<1>(0h0)) node _io_inReady_div_T_11 = and(_io_inReady_div_T_9, _io_inReady_div_T_10) node _io_inReady_div_T_12 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_13 = and(_io_inReady_div_T_11, _io_inReady_div_T_12) node _io_inReady_div_T_14 = eq(cyc_C5, UInt<1>(0h0)) node _io_inReady_div_T_15 = and(_io_inReady_div_T_13, _io_inReady_div_T_14) node _io_inReady_div_T_16 = eq(cyc_C4, UInt<1>(0h0)) node _io_inReady_div_T_17 = and(_io_inReady_div_T_15, _io_inReady_div_T_16) connect io.inReady_div, _io_inReady_div_T_17 node _io_inReady_sqrt_T = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_1 = and(ready_PA, _io_inReady_sqrt_T) node _io_inReady_sqrt_T_2 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_3 = and(_io_inReady_sqrt_T_1, _io_inReady_sqrt_T_2) node _io_inReady_sqrt_T_4 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_5 = and(_io_inReady_sqrt_T_3, _io_inReady_sqrt_T_4) node _io_inReady_sqrt_T_6 = eq(cyc_B2_div, UInt<1>(0h0)) node _io_inReady_sqrt_T_7 = and(_io_inReady_sqrt_T_5, _io_inReady_sqrt_T_6) node _io_inReady_sqrt_T_8 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_9 = and(_io_inReady_sqrt_T_7, _io_inReady_sqrt_T_8) connect io.inReady_sqrt, _io_inReady_sqrt_T_9 node _zFractB_A4_div_T = bits(rawB_S.sig, 51, 0) node zFractB_A4_div = mux(entering_PA_normalCase_div, _zFractB_A4_div_T, UInt<1>(0h0)) node _zLinPiece_0_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_0_A4_div_T_1 = eq(_zLinPiece_0_A4_div_T, UInt<1>(0h0)) node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, _zLinPiece_0_A4_div_T_1) node _zLinPiece_1_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_1_A4_div_T_1 = eq(_zLinPiece_1_A4_div_T, UInt<1>(0h1)) node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, _zLinPiece_1_A4_div_T_1) node _zLinPiece_2_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_2_A4_div_T_1 = eq(_zLinPiece_2_A4_div_T, UInt<2>(0h2)) node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, _zLinPiece_2_A4_div_T_1) node _zLinPiece_3_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_3_A4_div_T_1 = eq(_zLinPiece_3_A4_div_T, UInt<2>(0h3)) node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, _zLinPiece_3_A4_div_T_1) node _zLinPiece_4_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_4_A4_div_T_1 = eq(_zLinPiece_4_A4_div_T, UInt<3>(0h4)) node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, _zLinPiece_4_A4_div_T_1) node _zLinPiece_5_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_5_A4_div_T_1 = eq(_zLinPiece_5_A4_div_T, UInt<3>(0h5)) node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, _zLinPiece_5_A4_div_T_1) node _zLinPiece_6_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_6_A4_div_T_1 = eq(_zLinPiece_6_A4_div_T, UInt<3>(0h6)) node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, _zLinPiece_6_A4_div_T_1) node _zLinPiece_7_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_7_A4_div_T_1 = eq(_zLinPiece_7_A4_div_T, UInt<3>(0h7)) node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, _zLinPiece_7_A4_div_T_1) node _zK1_A4_div_T = mux(zLinPiece_0_A4_div, UInt<9>(0h1c7), UInt<1>(0h0)) node _zK1_A4_div_T_1 = mux(zLinPiece_1_A4_div, UInt<9>(0h16c), UInt<1>(0h0)) node _zK1_A4_div_T_2 = or(_zK1_A4_div_T, _zK1_A4_div_T_1) node _zK1_A4_div_T_3 = mux(zLinPiece_2_A4_div, UInt<9>(0h12a), UInt<1>(0h0)) node _zK1_A4_div_T_4 = or(_zK1_A4_div_T_2, _zK1_A4_div_T_3) node _zK1_A4_div_T_5 = mux(zLinPiece_3_A4_div, UInt<8>(0hf8), UInt<1>(0h0)) node _zK1_A4_div_T_6 = or(_zK1_A4_div_T_4, _zK1_A4_div_T_5) node _zK1_A4_div_T_7 = mux(zLinPiece_4_A4_div, UInt<8>(0hd2), UInt<1>(0h0)) node _zK1_A4_div_T_8 = or(_zK1_A4_div_T_6, _zK1_A4_div_T_7) node _zK1_A4_div_T_9 = mux(zLinPiece_5_A4_div, UInt<8>(0hb4), UInt<1>(0h0)) node _zK1_A4_div_T_10 = or(_zK1_A4_div_T_8, _zK1_A4_div_T_9) node _zK1_A4_div_T_11 = mux(zLinPiece_6_A4_div, UInt<8>(0h9c), UInt<1>(0h0)) node _zK1_A4_div_T_12 = or(_zK1_A4_div_T_10, _zK1_A4_div_T_11) node _zK1_A4_div_T_13 = mux(zLinPiece_7_A4_div, UInt<8>(0h89), UInt<1>(0h0)) node zK1_A4_div = or(_zK1_A4_div_T_12, _zK1_A4_div_T_13) node _zComplFractK0_A4_div_T = not(UInt<12>(0hfe3)) node _zComplFractK0_A4_div_T_1 = mux(zLinPiece_0_A4_div, _zComplFractK0_A4_div_T, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_2 = not(UInt<12>(0hc5d)) node _zComplFractK0_A4_div_T_3 = mux(zLinPiece_1_A4_div, _zComplFractK0_A4_div_T_2, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_4 = or(_zComplFractK0_A4_div_T_1, _zComplFractK0_A4_div_T_3) node _zComplFractK0_A4_div_T_5 = not(UInt<12>(0h98a)) node _zComplFractK0_A4_div_T_6 = mux(zLinPiece_2_A4_div, _zComplFractK0_A4_div_T_5, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_7 = or(_zComplFractK0_A4_div_T_4, _zComplFractK0_A4_div_T_6) node _zComplFractK0_A4_div_T_8 = not(UInt<12>(0h739)) node _zComplFractK0_A4_div_T_9 = mux(zLinPiece_3_A4_div, _zComplFractK0_A4_div_T_8, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_10 = or(_zComplFractK0_A4_div_T_7, _zComplFractK0_A4_div_T_9) node _zComplFractK0_A4_div_T_11 = not(UInt<12>(0h54b)) node _zComplFractK0_A4_div_T_12 = mux(zLinPiece_4_A4_div, _zComplFractK0_A4_div_T_11, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_13 = or(_zComplFractK0_A4_div_T_10, _zComplFractK0_A4_div_T_12) node _zComplFractK0_A4_div_T_14 = not(UInt<12>(0h3a9)) node _zComplFractK0_A4_div_T_15 = mux(zLinPiece_5_A4_div, _zComplFractK0_A4_div_T_14, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_16 = or(_zComplFractK0_A4_div_T_13, _zComplFractK0_A4_div_T_15) node _zComplFractK0_A4_div_T_17 = not(UInt<12>(0h242)) node _zComplFractK0_A4_div_T_18 = mux(zLinPiece_6_A4_div, _zComplFractK0_A4_div_T_17, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_19 = or(_zComplFractK0_A4_div_T_16, _zComplFractK0_A4_div_T_18) node _zComplFractK0_A4_div_T_20 = not(UInt<12>(0h10b)) node _zComplFractK0_A4_div_T_21 = mux(zLinPiece_7_A4_div, _zComplFractK0_A4_div_T_20, UInt<1>(0h0)) node zComplFractK0_A4_div = or(_zComplFractK0_A4_div_T_19, _zComplFractK0_A4_div_T_21) node _zFractB_A7_sqrt_T = bits(rawB_S.sig, 51, 0) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, _zFractB_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_0_A7_sqrt_T_1 = eq(_zQuadPiece_0_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_0_A7_sqrt_T_1) node _zQuadPiece_0_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_0_A7_sqrt_T_4 = eq(_zQuadPiece_0_A7_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A7_sqrt = and(_zQuadPiece_0_A7_sqrt_T_2, _zQuadPiece_0_A7_sqrt_T_4) node _zQuadPiece_1_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_1_A7_sqrt_T_1 = eq(_zQuadPiece_1_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_1_A7_sqrt_T_1) node _zQuadPiece_1_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node zQuadPiece_1_A7_sqrt = and(_zQuadPiece_1_A7_sqrt_T_2, _zQuadPiece_1_A7_sqrt_T_3) node _zQuadPiece_2_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_2_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_2_A7_sqrt_T) node _zQuadPiece_2_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_2_A7_sqrt_T_3 = eq(_zQuadPiece_2_A7_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A7_sqrt = and(_zQuadPiece_2_A7_sqrt_T_1, _zQuadPiece_2_A7_sqrt_T_3) node _zQuadPiece_3_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_3_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_3_A7_sqrt_T) node _zQuadPiece_3_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node zQuadPiece_3_A7_sqrt = and(_zQuadPiece_3_A7_sqrt_T_1, _zQuadPiece_3_A7_sqrt_T_2) node _zK2_A7_sqrt_T = mux(zQuadPiece_0_A7_sqrt, UInt<9>(0h1c8), UInt<1>(0h0)) node _zK2_A7_sqrt_T_1 = mux(zQuadPiece_1_A7_sqrt, UInt<8>(0hc1), UInt<1>(0h0)) node _zK2_A7_sqrt_T_2 = or(_zK2_A7_sqrt_T, _zK2_A7_sqrt_T_1) node _zK2_A7_sqrt_T_3 = mux(zQuadPiece_2_A7_sqrt, UInt<9>(0h143), UInt<1>(0h0)) node _zK2_A7_sqrt_T_4 = or(_zK2_A7_sqrt_T_2, _zK2_A7_sqrt_T_3) node _zK2_A7_sqrt_T_5 = mux(zQuadPiece_3_A7_sqrt, UInt<8>(0h89), UInt<1>(0h0)) node zK2_A7_sqrt = or(_zK2_A7_sqrt_T_4, _zK2_A7_sqrt_T_5) node _zComplK1_A7_sqrt_T = not(UInt<10>(0h3d0)) node _zComplK1_A7_sqrt_T_1 = mux(zQuadPiece_0_A7_sqrt, _zComplK1_A7_sqrt_T, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_2 = not(UInt<10>(0h220)) node _zComplK1_A7_sqrt_T_3 = mux(zQuadPiece_1_A7_sqrt, _zComplK1_A7_sqrt_T_2, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_4 = or(_zComplK1_A7_sqrt_T_1, _zComplK1_A7_sqrt_T_3) node _zComplK1_A7_sqrt_T_5 = not(UInt<10>(0h2b2)) node _zComplK1_A7_sqrt_T_6 = mux(zQuadPiece_2_A7_sqrt, _zComplK1_A7_sqrt_T_5, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_7 = or(_zComplK1_A7_sqrt_T_4, _zComplK1_A7_sqrt_T_6) node _zComplK1_A7_sqrt_T_8 = not(UInt<10>(0h181)) node _zComplK1_A7_sqrt_T_9 = mux(zQuadPiece_3_A7_sqrt, _zComplK1_A7_sqrt_T_8, UInt<1>(0h0)) node zComplK1_A7_sqrt = or(_zComplK1_A7_sqrt_T_7, _zComplK1_A7_sqrt_T_9) node _zQuadPiece_0_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_0_A6_sqrt_T_1 = eq(_zQuadPiece_0_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_0_A6_sqrt_T_1) node _zQuadPiece_0_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node _zQuadPiece_0_A6_sqrt_T_4 = eq(_zQuadPiece_0_A6_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A6_sqrt = and(_zQuadPiece_0_A6_sqrt_T_2, _zQuadPiece_0_A6_sqrt_T_4) node _zQuadPiece_1_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_1_A6_sqrt_T_1 = eq(_zQuadPiece_1_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_1_A6_sqrt_T_1) node _zQuadPiece_1_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node zQuadPiece_1_A6_sqrt = and(_zQuadPiece_1_A6_sqrt_T_2, _zQuadPiece_1_A6_sqrt_T_3) node _zQuadPiece_2_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_2_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_2_A6_sqrt_T) node _zQuadPiece_2_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node _zQuadPiece_2_A6_sqrt_T_3 = eq(_zQuadPiece_2_A6_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A6_sqrt = and(_zQuadPiece_2_A6_sqrt_T_1, _zQuadPiece_2_A6_sqrt_T_3) node _zQuadPiece_3_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_3_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_3_A6_sqrt_T) node _zQuadPiece_3_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node zQuadPiece_3_A6_sqrt = and(_zQuadPiece_3_A6_sqrt_T_1, _zQuadPiece_3_A6_sqrt_T_2) node _zComplFractK0_A6_sqrt_T = not(UInt<13>(0h1fe5)) node _zComplFractK0_A6_sqrt_T_1 = mux(zQuadPiece_0_A6_sqrt, _zComplFractK0_A6_sqrt_T, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_2 = not(UInt<13>(0h1435)) node _zComplFractK0_A6_sqrt_T_3 = mux(zQuadPiece_1_A6_sqrt, _zComplFractK0_A6_sqrt_T_2, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_4 = or(_zComplFractK0_A6_sqrt_T_1, _zComplFractK0_A6_sqrt_T_3) node _zComplFractK0_A6_sqrt_T_5 = not(UInt<13>(0hd2c)) node _zComplFractK0_A6_sqrt_T_6 = mux(zQuadPiece_2_A6_sqrt, _zComplFractK0_A6_sqrt_T_5, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_7 = or(_zComplFractK0_A6_sqrt_T_4, _zComplFractK0_A6_sqrt_T_6) node _zComplFractK0_A6_sqrt_T_8 = not(UInt<13>(0h4e8)) node _zComplFractK0_A6_sqrt_T_9 = mux(zQuadPiece_3_A6_sqrt, _zComplFractK0_A6_sqrt_T_8, UInt<1>(0h0)) node zComplFractK0_A6_sqrt = or(_zComplFractK0_A6_sqrt_T_7, _zComplFractK0_A6_sqrt_T_9) node _mulAdd9A_A_T = bits(zFractB_A4_div, 48, 40) node _mulAdd9A_A_T_1 = or(_mulAdd9A_A_T, zK2_A7_sqrt) node _mulAdd9A_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9A_A_T_3 = mux(_mulAdd9A_A_T_2, nextMulAdd9A_A, UInt<1>(0h0)) node mulAdd9A_A = or(_mulAdd9A_A_T_1, _mulAdd9A_A_T_3) node _mulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _mulAdd9B_A_T_1 = or(zK1_A4_div, _mulAdd9B_A_T) node _mulAdd9B_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9B_A_T_3 = mux(_mulAdd9B_A_T_2, nextMulAdd9B_A, UInt<1>(0h0)) node mulAdd9B_A = or(_mulAdd9B_A_T_1, _mulAdd9B_A_T_3) node _mulAdd9C_A_T = mux(entering_PA_normalCase_sqrt, UInt<10>(0h3ff), UInt<10>(0h0)) node _mulAdd9C_A_T_1 = cat(zComplK1_A7_sqrt, _mulAdd9C_A_T) node _mulAdd9C_A_T_2 = mux(cyc_A6_sqrt, UInt<6>(0h3f), UInt<6>(0h0)) node mulAdd9C_A_hi = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) node _mulAdd9C_A_T_3 = cat(mulAdd9C_A_hi, _mulAdd9C_A_T_2) node _mulAdd9C_A_T_4 = or(_mulAdd9C_A_T_1, _mulAdd9C_A_T_3) node _mulAdd9C_A_T_5 = mux(entering_PA_normalCase_div, UInt<8>(0hff), UInt<8>(0h0)) node mulAdd9C_A_hi_1 = cat(entering_PA_normalCase_div, zComplFractK0_A4_div) node _mulAdd9C_A_T_6 = cat(mulAdd9C_A_hi_1, _mulAdd9C_A_T_5) node _mulAdd9C_A_T_7 = or(_mulAdd9C_A_T_4, _mulAdd9C_A_T_6) node _mulAdd9C_A_T_8 = shl(fractR0_A, 10) node _mulAdd9C_A_T_9 = add(UInt<19>(0h40000), _mulAdd9C_A_T_8) node _mulAdd9C_A_T_10 = mux(cyc_A5_sqrt, _mulAdd9C_A_T_9, UInt<1>(0h0)) node _mulAdd9C_A_T_11 = or(_mulAdd9C_A_T_7, _mulAdd9C_A_T_10) node _mulAdd9C_A_T_12 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_13 = eq(_mulAdd9C_A_T_12, UInt<1>(0h0)) node _mulAdd9C_A_T_14 = and(cyc_A4_sqrt, _mulAdd9C_A_T_13) node _mulAdd9C_A_T_15 = mux(_mulAdd9C_A_T_14, UInt<11>(0h400), UInt<1>(0h0)) node _mulAdd9C_A_T_16 = or(_mulAdd9C_A_T_11, _mulAdd9C_A_T_15) node _mulAdd9C_A_T_17 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_18 = and(cyc_A4_sqrt, _mulAdd9C_A_T_17) node _mulAdd9C_A_T_19 = or(_mulAdd9C_A_T_18, cyc_A3_div) node _mulAdd9C_A_T_20 = bits(sigB_PA, 46, 26) node _mulAdd9C_A_T_21 = add(_mulAdd9C_A_T_20, UInt<11>(0h400)) node _mulAdd9C_A_T_22 = tail(_mulAdd9C_A_T_21, 1) node _mulAdd9C_A_T_23 = mux(_mulAdd9C_A_T_19, _mulAdd9C_A_T_22, UInt<1>(0h0)) node _mulAdd9C_A_T_24 = or(_mulAdd9C_A_T_16, _mulAdd9C_A_T_23) node _mulAdd9C_A_T_25 = or(cyc_A3_sqrt, cyc_A2) node _mulAdd9C_A_T_26 = mux(_mulAdd9C_A_T_25, partNegSigma0_A, UInt<1>(0h0)) node _mulAdd9C_A_T_27 = or(_mulAdd9C_A_T_24, _mulAdd9C_A_T_26) node _mulAdd9C_A_T_28 = shl(fractR0_A, 16) node _mulAdd9C_A_T_29 = mux(cyc_A1_sqrt, _mulAdd9C_A_T_28, UInt<1>(0h0)) node _mulAdd9C_A_T_30 = or(_mulAdd9C_A_T_27, _mulAdd9C_A_T_29) node _mulAdd9C_A_T_31 = shl(fractR0_A, 15) node _mulAdd9C_A_T_32 = mux(cyc_A1_div, _mulAdd9C_A_T_31, UInt<1>(0h0)) node mulAdd9C_A = or(_mulAdd9C_A_T_30, _mulAdd9C_A_T_32) node _loMulAdd9Out_A_T = mul(mulAdd9A_A, mulAdd9B_A) node _loMulAdd9Out_A_T_1 = bits(mulAdd9C_A, 17, 0) node loMulAdd9Out_A = add(_loMulAdd9Out_A_T, _loMulAdd9Out_A_T_1) node _mulAdd9Out_A_T = bits(loMulAdd9Out_A, 18, 18) node _mulAdd9Out_A_T_1 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_2 = add(_mulAdd9Out_A_T_1, UInt<1>(0h1)) node _mulAdd9Out_A_T_3 = tail(_mulAdd9Out_A_T_2, 1) node _mulAdd9Out_A_T_4 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_5 = mux(_mulAdd9Out_A_T, _mulAdd9Out_A_T_3, _mulAdd9Out_A_T_4) node _mulAdd9Out_A_T_6 = bits(loMulAdd9Out_A, 17, 0) node mulAdd9Out_A = cat(_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6) node _zFractR0_A6_sqrt_T = bits(mulAdd9Out_A, 19, 19) node _zFractR0_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zFractR0_A6_sqrt_T) node _zFractR0_A6_sqrt_T_2 = shr(mulAdd9Out_A, 10) node _zFractR0_A6_sqrt_T_3 = not(_zFractR0_A6_sqrt_T_2) node zFractR0_A6_sqrt = mux(_zFractR0_A6_sqrt_T_1, _zFractR0_A6_sqrt_T_3, UInt<1>(0h0)) node _sqrR0_A5_sqrt_T = bits(sExp_PA, 0, 0) node _sqrR0_A5_sqrt_T_1 = shl(mulAdd9Out_A, 1) node sqrR0_A5_sqrt = mux(_sqrR0_A5_sqrt_T, _sqrR0_A5_sqrt_T_1, mulAdd9Out_A) node _zFractR0_A4_div_T = bits(mulAdd9Out_A, 20, 20) node _zFractR0_A4_div_T_1 = and(entering_PA_normalCase_div, _zFractR0_A4_div_T) node _zFractR0_A4_div_T_2 = shr(mulAdd9Out_A, 11) node _zFractR0_A4_div_T_3 = not(_zFractR0_A4_div_T_2) node zFractR0_A4_div = mux(_zFractR0_A4_div_T_1, _zFractR0_A4_div_T_3, UInt<1>(0h0)) node _zSigma0_A2_T = bits(mulAdd9Out_A, 11, 11) node _zSigma0_A2_T_1 = and(cyc_A2, _zSigma0_A2_T) node _zSigma0_A2_T_2 = shr(mulAdd9Out_A, 2) node _zSigma0_A2_T_3 = not(_zSigma0_A2_T_2) node zSigma0_A2 = mux(_zSigma0_A2_T_1, _zSigma0_A2_T_3, UInt<1>(0h0)) node _r1_A1_T = shr(mulAdd9Out_A, 10) node _r1_A1_T_1 = shr(mulAdd9Out_A, 9) node _r1_A1_T_2 = mux(sqrtOp_PA, _r1_A1_T, _r1_A1_T_1) node r1_A1 = or(UInt<16>(0h8000), _r1_A1_T_2) node _ER1_A1_sqrt_T = bits(sExp_PA, 0, 0) node _ER1_A1_sqrt_T_1 = shl(r1_A1, 1) node ER1_A1_sqrt = mux(_ER1_A1_sqrt_T, _ER1_A1_sqrt_T_1, r1_A1) node _T_11 = or(cyc_A6_sqrt, entering_PA_normalCase_div) when _T_11 : node _fractR0_A_T = or(zFractR0_A6_sqrt, zFractR0_A4_div) connect fractR0_A, _fractR0_A_T when cyc_A5_sqrt : node _hiSqrR0_A_sqrt_T = shr(sqrR0_A5_sqrt, 10) connect hiSqrR0_A_sqrt, _hiSqrR0_A_sqrt_T node _T_12 = or(cyc_A4_sqrt, cyc_A3) when _T_12 : node _partNegSigma0_A_T = shr(mulAdd9Out_A, 9) node _partNegSigma0_A_T_1 = mux(cyc_A4_sqrt, mulAdd9Out_A, _partNegSigma0_A_T) connect partNegSigma0_A, _partNegSigma0_A_T_1 node _T_13 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_14 = or(_T_13, cyc_A5_sqrt) node _T_15 = or(_T_14, cyc_A4) node _T_16 = or(_T_15, cyc_A3) node _T_17 = or(_T_16, cyc_A2) when _T_17 : node _nextMulAdd9A_A_T = not(mulAdd9Out_A) node _nextMulAdd9A_A_T_1 = shr(_nextMulAdd9A_A_T, 11) node _nextMulAdd9A_A_T_2 = mux(entering_PA_normalCase_sqrt, _nextMulAdd9A_A_T_1, UInt<1>(0h0)) node _nextMulAdd9A_A_T_3 = or(_nextMulAdd9A_A_T_2, zFractR0_A6_sqrt) node _nextMulAdd9A_A_T_4 = bits(sigB_PA, 43, 35) node _nextMulAdd9A_A_T_5 = mux(cyc_A4_sqrt, _nextMulAdd9A_A_T_4, UInt<1>(0h0)) node _nextMulAdd9A_A_T_6 = or(_nextMulAdd9A_A_T_3, _nextMulAdd9A_A_T_5) node _nextMulAdd9A_A_T_7 = bits(zFractB_A4_div, 43, 35) node _nextMulAdd9A_A_T_8 = or(_nextMulAdd9A_A_T_6, _nextMulAdd9A_A_T_7) node _nextMulAdd9A_A_T_9 = or(cyc_A5_sqrt, cyc_A3) node _nextMulAdd9A_A_T_10 = bits(sigB_PA, 52, 44) node _nextMulAdd9A_A_T_11 = mux(_nextMulAdd9A_A_T_9, _nextMulAdd9A_A_T_10, UInt<1>(0h0)) node _nextMulAdd9A_A_T_12 = or(_nextMulAdd9A_A_T_8, _nextMulAdd9A_A_T_11) node _nextMulAdd9A_A_T_13 = or(_nextMulAdd9A_A_T_12, zSigma0_A2) connect nextMulAdd9A_A, _nextMulAdd9A_A_T_13 node _T_18 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_19 = or(_T_18, cyc_A5_sqrt) node _T_20 = or(_T_19, cyc_A4) node _T_21 = or(_T_20, cyc_A2) when _T_21 : node _nextMulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _nextMulAdd9B_A_T_1 = or(_nextMulAdd9B_A_T, zFractR0_A6_sqrt) node _nextMulAdd9B_A_T_2 = bits(sqrR0_A5_sqrt, 9, 1) node _nextMulAdd9B_A_T_3 = mux(cyc_A5_sqrt, _nextMulAdd9B_A_T_2, UInt<1>(0h0)) node _nextMulAdd9B_A_T_4 = or(_nextMulAdd9B_A_T_1, _nextMulAdd9B_A_T_3) node _nextMulAdd9B_A_T_5 = or(_nextMulAdd9B_A_T_4, zFractR0_A4_div) node _nextMulAdd9B_A_T_6 = bits(hiSqrR0_A_sqrt, 8, 0) node _nextMulAdd9B_A_T_7 = mux(cyc_A4_sqrt, _nextMulAdd9B_A_T_6, UInt<1>(0h0)) node _nextMulAdd9B_A_T_8 = or(_nextMulAdd9B_A_T_5, _nextMulAdd9B_A_T_7) node _nextMulAdd9B_A_T_9 = bits(fractR0_A, 8, 1) node _nextMulAdd9B_A_T_10 = cat(UInt<1>(0h1), _nextMulAdd9B_A_T_9) node _nextMulAdd9B_A_T_11 = mux(cyc_A2, _nextMulAdd9B_A_T_10, UInt<1>(0h0)) node _nextMulAdd9B_A_T_12 = or(_nextMulAdd9B_A_T_8, _nextMulAdd9B_A_T_11) connect nextMulAdd9B_A, _nextMulAdd9B_A_T_12 when cyc_A1_sqrt : connect ER1_B_sqrt, ER1_A1_sqrt node _io_latchMulAddA_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddA_0_T_1 = or(_io_latchMulAddA_0_T, cyc_B6_div) node _io_latchMulAddA_0_T_2 = or(_io_latchMulAddA_0_T_1, cyc_B4) node _io_latchMulAddA_0_T_3 = or(_io_latchMulAddA_0_T_2, cyc_B3) node _io_latchMulAddA_0_T_4 = or(_io_latchMulAddA_0_T_3, cyc_C6_sqrt) node _io_latchMulAddA_0_T_5 = or(_io_latchMulAddA_0_T_4, cyc_C4) node _io_latchMulAddA_0_T_6 = or(_io_latchMulAddA_0_T_5, cyc_C1) connect io.latchMulAddA_0, _io_latchMulAddA_0_T_6 node _io_mulAddA_0_T = shl(ER1_A1_sqrt, 36) node _io_mulAddA_0_T_1 = mux(cyc_A1_sqrt, _io_mulAddA_0_T, UInt<1>(0h0)) node _io_mulAddA_0_T_2 = or(cyc_B7_sqrt, cyc_A1_div) node _io_mulAddA_0_T_3 = mux(_io_mulAddA_0_T_2, sigB_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_4 = or(_io_mulAddA_0_T_1, _io_mulAddA_0_T_3) node _io_mulAddA_0_T_5 = mux(cyc_B6_div, sigA_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_6 = or(_io_mulAddA_0_T_4, _io_mulAddA_0_T_5) node _io_mulAddA_0_T_7 = bits(zSigma1_B4, 45, 12) node _io_mulAddA_0_T_8 = or(_io_mulAddA_0_T_6, _io_mulAddA_0_T_7) node _io_mulAddA_0_T_9 = or(cyc_B3, cyc_C6_sqrt) node _io_mulAddA_0_T_10 = bits(sigXNU_B3_CX, 57, 12) node _io_mulAddA_0_T_11 = mux(_io_mulAddA_0_T_9, _io_mulAddA_0_T_10, UInt<1>(0h0)) node _io_mulAddA_0_T_12 = or(_io_mulAddA_0_T_8, _io_mulAddA_0_T_11) node _io_mulAddA_0_T_13 = bits(sigXN_C, 57, 25) node _io_mulAddA_0_T_14 = shl(_io_mulAddA_0_T_13, 13) node _io_mulAddA_0_T_15 = mux(cyc_C4_div, _io_mulAddA_0_T_14, UInt<1>(0h0)) node _io_mulAddA_0_T_16 = or(_io_mulAddA_0_T_12, _io_mulAddA_0_T_15) node _io_mulAddA_0_T_17 = shl(u_C_sqrt, 15) node _io_mulAddA_0_T_18 = mux(cyc_C4_sqrt, _io_mulAddA_0_T_17, UInt<1>(0h0)) node _io_mulAddA_0_T_19 = or(_io_mulAddA_0_T_16, _io_mulAddA_0_T_18) node _io_mulAddA_0_T_20 = mux(cyc_C1_div, sigB_PC, UInt<1>(0h0)) node _io_mulAddA_0_T_21 = or(_io_mulAddA_0_T_19, _io_mulAddA_0_T_20) node _io_mulAddA_0_T_22 = or(_io_mulAddA_0_T_21, zComplSigT_C1_sqrt) connect io.mulAddA_0, _io_mulAddA_0_T_22 node _io_latchMulAddB_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddB_0_T_1 = or(_io_latchMulAddB_0_T, cyc_B6_sqrt) node _io_latchMulAddB_0_T_2 = or(_io_latchMulAddB_0_T_1, cyc_B4) node _io_latchMulAddB_0_T_3 = or(_io_latchMulAddB_0_T_2, cyc_C6_sqrt) node _io_latchMulAddB_0_T_4 = or(_io_latchMulAddB_0_T_3, cyc_C4) node _io_latchMulAddB_0_T_5 = or(_io_latchMulAddB_0_T_4, cyc_C1) connect io.latchMulAddB_0, _io_latchMulAddB_0_T_5 node _io_mulAddB_0_T = shl(r1_A1, 36) node _io_mulAddB_0_T_1 = mux(cyc_A1, _io_mulAddB_0_T, UInt<1>(0h0)) node _io_mulAddB_0_T_2 = shl(ESqrR1_B_sqrt, 19) node _io_mulAddB_0_T_3 = mux(cyc_B7_sqrt, _io_mulAddB_0_T_2, UInt<1>(0h0)) node _io_mulAddB_0_T_4 = or(_io_mulAddB_0_T_1, _io_mulAddB_0_T_3) node _io_mulAddB_0_T_5 = shl(ER1_B_sqrt, 36) node _io_mulAddB_0_T_6 = mux(cyc_B6_sqrt, _io_mulAddB_0_T_5, UInt<1>(0h0)) node _io_mulAddB_0_T_7 = or(_io_mulAddB_0_T_4, _io_mulAddB_0_T_6) node _io_mulAddB_0_T_8 = or(_io_mulAddB_0_T_7, zSigma1_B4) node _io_mulAddB_0_T_9 = bits(sqrSigma1_C, 30, 1) node _io_mulAddB_0_T_10 = mux(cyc_C6_sqrt, _io_mulAddB_0_T_9, UInt<1>(0h0)) node _io_mulAddB_0_T_11 = or(_io_mulAddB_0_T_8, _io_mulAddB_0_T_10) node _io_mulAddB_0_T_12 = mux(cyc_C4, sqrSigma1_C, UInt<1>(0h0)) node _io_mulAddB_0_T_13 = or(_io_mulAddB_0_T_11, _io_mulAddB_0_T_12) node _io_mulAddB_0_T_14 = or(_io_mulAddB_0_T_13, zComplSigT_C1) connect io.mulAddB_0, _io_mulAddB_0_T_14 node _io_usingMulAdd_T = or(cyc_A4, cyc_A3_div) node _io_usingMulAdd_T_1 = or(_io_usingMulAdd_T, cyc_A1_div) node _io_usingMulAdd_T_2 = or(_io_usingMulAdd_T_1, cyc_B10_sqrt) node _io_usingMulAdd_T_3 = or(_io_usingMulAdd_T_2, cyc_B9_sqrt) node _io_usingMulAdd_T_4 = or(_io_usingMulAdd_T_3, cyc_B7_sqrt) node _io_usingMulAdd_T_5 = or(_io_usingMulAdd_T_4, cyc_B6) node _io_usingMulAdd_T_6 = or(_io_usingMulAdd_T_5, cyc_B5_sqrt) node _io_usingMulAdd_T_7 = or(_io_usingMulAdd_T_6, cyc_B3_sqrt) node _io_usingMulAdd_T_8 = or(_io_usingMulAdd_T_7, cyc_B2_div) node _io_usingMulAdd_T_9 = or(_io_usingMulAdd_T_8, cyc_B1_sqrt) node _io_usingMulAdd_T_10 = or(_io_usingMulAdd_T_9, cyc_C4) node _io_usingMulAdd_T_11 = or(cyc_A3, cyc_A2_div) node _io_usingMulAdd_T_12 = or(_io_usingMulAdd_T_11, cyc_B9_sqrt) node _io_usingMulAdd_T_13 = or(_io_usingMulAdd_T_12, cyc_B8_sqrt) node _io_usingMulAdd_T_14 = or(_io_usingMulAdd_T_13, cyc_B6) node _io_usingMulAdd_T_15 = or(_io_usingMulAdd_T_14, cyc_B5) node _io_usingMulAdd_T_16 = or(_io_usingMulAdd_T_15, cyc_B4_sqrt) node _io_usingMulAdd_T_17 = or(_io_usingMulAdd_T_16, cyc_B2_sqrt) node _io_usingMulAdd_T_18 = or(_io_usingMulAdd_T_17, cyc_B1_div) node _io_usingMulAdd_T_19 = or(_io_usingMulAdd_T_18, cyc_C6_sqrt) node _io_usingMulAdd_T_20 = or(_io_usingMulAdd_T_19, cyc_C3) node _io_usingMulAdd_T_21 = or(cyc_A2, cyc_A1_div) node _io_usingMulAdd_T_22 = or(_io_usingMulAdd_T_21, cyc_B8_sqrt) node _io_usingMulAdd_T_23 = or(_io_usingMulAdd_T_22, cyc_B7_sqrt) node _io_usingMulAdd_T_24 = or(_io_usingMulAdd_T_23, cyc_B5) node _io_usingMulAdd_T_25 = or(_io_usingMulAdd_T_24, cyc_B4) node _io_usingMulAdd_T_26 = or(_io_usingMulAdd_T_25, cyc_B3_sqrt) node _io_usingMulAdd_T_27 = or(_io_usingMulAdd_T_26, cyc_B1_sqrt) node _io_usingMulAdd_T_28 = or(_io_usingMulAdd_T_27, cyc_C5) node _io_usingMulAdd_T_29 = or(_io_usingMulAdd_T_28, cyc_C2) node _io_usingMulAdd_T_30 = or(io.latchMulAddA_0, cyc_B6) node _io_usingMulAdd_T_31 = or(_io_usingMulAdd_T_30, cyc_B2_sqrt) node io_usingMulAdd_lo = cat(_io_usingMulAdd_T_29, _io_usingMulAdd_T_31) node io_usingMulAdd_hi = cat(_io_usingMulAdd_T_10, _io_usingMulAdd_T_20) node _io_usingMulAdd_T_32 = cat(io_usingMulAdd_hi, io_usingMulAdd_lo) connect io.usingMulAdd, _io_usingMulAdd_T_32 node _io_mulAddC_2_T = shl(sigX1_B, 47) node _io_mulAddC_2_T_1 = mux(cyc_B1, _io_mulAddC_2_T, UInt<1>(0h0)) node _io_mulAddC_2_T_2 = shl(sigX1_B, 46) node _io_mulAddC_2_T_3 = mux(cyc_C6_sqrt, _io_mulAddC_2_T_2, UInt<1>(0h0)) node _io_mulAddC_2_T_4 = or(_io_mulAddC_2_T_1, _io_mulAddC_2_T_3) node _io_mulAddC_2_T_5 = or(cyc_C4_sqrt, cyc_C2) node _io_mulAddC_2_T_6 = shl(sigXN_C, 47) node _io_mulAddC_2_T_7 = mux(_io_mulAddC_2_T_5, _io_mulAddC_2_T_6, UInt<1>(0h0)) node _io_mulAddC_2_T_8 = or(_io_mulAddC_2_T_4, _io_mulAddC_2_T_7) node _io_mulAddC_2_T_9 = eq(E_E_div, UInt<1>(0h0)) node _io_mulAddC_2_T_10 = and(cyc_E3_div, _io_mulAddC_2_T_9) node _io_mulAddC_2_T_11 = shl(bit0FractA_PC, 53) node _io_mulAddC_2_T_12 = mux(_io_mulAddC_2_T_10, _io_mulAddC_2_T_11, UInt<1>(0h0)) node _io_mulAddC_2_T_13 = or(_io_mulAddC_2_T_8, _io_mulAddC_2_T_12) node _io_mulAddC_2_T_14 = bits(sExp_PC, 0, 0) node _io_mulAddC_2_T_15 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_16 = shl(_io_mulAddC_2_T_15, 1) node _io_mulAddC_2_T_17 = bits(sigB_PC, 1, 1) node _io_mulAddC_2_T_18 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_19 = xor(_io_mulAddC_2_T_17, _io_mulAddC_2_T_18) node _io_mulAddC_2_T_20 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_21 = cat(_io_mulAddC_2_T_19, _io_mulAddC_2_T_20) node _io_mulAddC_2_T_22 = mux(_io_mulAddC_2_T_14, _io_mulAddC_2_T_16, _io_mulAddC_2_T_21) node _io_mulAddC_2_T_23 = bits(sigT_E, 0, 0) node _io_mulAddC_2_T_24 = not(_io_mulAddC_2_T_23) node _io_mulAddC_2_T_25 = shl(_io_mulAddC_2_T_24, 1) node _io_mulAddC_2_T_26 = xor(_io_mulAddC_2_T_22, _io_mulAddC_2_T_25) node _io_mulAddC_2_T_27 = shl(_io_mulAddC_2_T_26, 54) node _io_mulAddC_2_T_28 = mux(cyc_E3_sqrt, _io_mulAddC_2_T_27, UInt<1>(0h0)) node _io_mulAddC_2_T_29 = or(_io_mulAddC_2_T_13, _io_mulAddC_2_T_28) connect io.mulAddC_2, _io_mulAddC_2_T_29 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) node _zSigma1_B4_T = bits(io.mulAddResult_3, 90, 45) node _zSigma1_B4_T_1 = not(_zSigma1_B4_T) node _zSigma1_B4_T_2 = mux(cyc_B4, _zSigma1_B4_T_1, UInt<1>(0h0)) connect zSigma1_B4, _zSigma1_B4_T_2 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) node _sigXNU_B3_CX_T = bits(io.mulAddResult_3, 104, 47) connect sigXNU_B3_CX, _sigXNU_B3_CX_T node _E_C1_div_T = bits(io.mulAddResult_3, 104, 104) node E_C1_div = eq(_E_C1_div_T, UInt<1>(0h0)) node _zComplSigT_C1_T = eq(E_C1_div, UInt<1>(0h0)) node _zComplSigT_C1_T_1 = and(cyc_C1_div, _zComplSigT_C1_T) node _zComplSigT_C1_T_2 = or(_zComplSigT_C1_T_1, cyc_C1_sqrt) node _zComplSigT_C1_T_3 = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_T_4 = not(_zComplSigT_C1_T_3) node _zComplSigT_C1_T_5 = mux(_zComplSigT_C1_T_2, _zComplSigT_C1_T_4, UInt<1>(0h0)) node _zComplSigT_C1_T_6 = and(cyc_C1_div, E_C1_div) node _zComplSigT_C1_T_7 = bits(io.mulAddResult_3, 102, 50) node _zComplSigT_C1_T_8 = not(_zComplSigT_C1_T_7) node _zComplSigT_C1_T_9 = mux(_zComplSigT_C1_T_6, _zComplSigT_C1_T_8, UInt<1>(0h0)) node _zComplSigT_C1_T_10 = or(_zComplSigT_C1_T_5, _zComplSigT_C1_T_9) connect zComplSigT_C1, _zComplSigT_C1_T_10 node _zComplSigT_C1_sqrt_T = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_sqrt_T_1 = not(_zComplSigT_C1_sqrt_T) node _zComplSigT_C1_sqrt_T_2 = mux(cyc_C1_sqrt, _zComplSigT_C1_sqrt_T_1, UInt<1>(0h0)) connect zComplSigT_C1_sqrt, _zComplSigT_C1_sqrt_T_2 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : connect ESqrR1_B_sqrt, ESqrR1_B8_sqrt when cyc_B3 : connect sigX1_B, sigXNU_B3_CX when cyc_B1 : connect sqrSigma1_C, sqrSigma1_B1 node _T_22 = or(cyc_C6_sqrt, cyc_C5_div) node _T_23 = or(_T_22, cyc_C3_sqrt) when _T_23 : connect sigXN_C, sigXNU_B3_CX when cyc_C5_sqrt : node _u_C_sqrt_T = bits(sigXNU_B3_CX, 56, 26) connect u_C_sqrt, _u_C_sqrt_T when cyc_C1 : connect E_E_div, E_C1_div connect sigT_E, sigT_C1 when cyc_E2 : node _isNegRemT_E_T = bits(remT_E2, 55, 55) node _isNegRemT_E_T_1 = bits(remT_E2, 53, 53) node _isNegRemT_E_T_2 = mux(sqrtOp_PC, _isNegRemT_E_T, _isNegRemT_E_T_1) connect isNegRemT_E, _isNegRemT_E_T_2 node _isZeroRemT_E_T = bits(remT_E2, 53, 0) node _isZeroRemT_E_T_1 = eq(_isZeroRemT_E_T, UInt<1>(0h0)) node _isZeroRemT_E_T_2 = eq(sqrtOp_PC, UInt<1>(0h0)) node _isZeroRemT_E_T_3 = bits(remT_E2, 55, 54) node _isZeroRemT_E_T_4 = eq(_isZeroRemT_E_T_3, UInt<1>(0h0)) node _isZeroRemT_E_T_5 = or(_isZeroRemT_E_T_2, _isZeroRemT_E_T_4) node _isZeroRemT_E_T_6 = and(_isZeroRemT_E_T_1, _isZeroRemT_E_T_5) connect isZeroRemT_E, _isZeroRemT_E_T_6 node _trueLtX_E1_T = eq(isNegRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_2 = and(_trueLtX_E1_T, _trueLtX_E1_T_1) node trueLtX_E1 = mux(sqrtOp_PC, _trueLtX_E1_T_2, isNegRemT_E) node _sExpP1_PC_T = add(sExp_PC, asSInt(UInt<2>(0h1))) node _sExpP1_PC_T_1 = tail(_sExpP1_PC_T, 1) node sExpP1_PC = asSInt(_sExpP1_PC_T_1) node sigTP1_E = add(sigT_E, UInt<1>(0h1)) node _io_rawOutValid_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOutValid_div_T_1 = and(leaving_PC, _io_rawOutValid_div_T) connect io.rawOutValid_div, _io_rawOutValid_div_T_1 node _io_rawOutValid_sqrt_T = and(leaving_PC, sqrtOp_PC) connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T connect io.roundingModeOut, roundingMode_PC node _io_invalidExc_T = and(majorExc_PC, isNaN_PC) connect io.invalidExc, _io_invalidExc_T node _io_infiniteExc_T = eq(isNaN_PC, UInt<1>(0h0)) node _io_infiniteExc_T_1 = and(majorExc_PC, _io_infiniteExc_T) connect io.infiniteExc, _io_infiniteExc_T_1 connect io.rawOut.isNaN, isNaN_PC connect io.rawOut.isInf, isInf_PC connect io.rawOut.isZero, isZero_PC connect io.rawOut.sign, sign_PC node _io_rawOut_sExp_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_1 = and(_io_rawOut_sExp_T, E_E_div) node _io_rawOut_sExp_T_2 = mux(_io_rawOut_sExp_T_1, sExp_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_3 = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_4 = eq(E_E_div, UInt<1>(0h0)) node _io_rawOut_sExp_T_5 = and(_io_rawOut_sExp_T_3, _io_rawOut_sExp_T_4) node _io_rawOut_sExp_T_6 = mux(_io_rawOut_sExp_T_5, sExpP1_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_7 = or(_io_rawOut_sExp_T_2, _io_rawOut_sExp_T_6) node _io_rawOut_sExp_T_8 = asSInt(_io_rawOut_sExp_T_7) node _io_rawOut_sExp_T_9 = shr(sExp_PC, 1) node _io_rawOut_sExp_T_10 = add(_io_rawOut_sExp_T_9, asSInt(UInt<12>(0h400))) node _io_rawOut_sExp_T_11 = mux(sqrtOp_PC, _io_rawOut_sExp_T_10, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_12 = or(_io_rawOut_sExp_T_8, _io_rawOut_sExp_T_11) node _io_rawOut_sExp_T_13 = asSInt(_io_rawOut_sExp_T_12) connect io.rawOut.sExp, _io_rawOut_sExp_T_13 node _io_rawOut_sig_T = mux(trueLtX_E1, sigT_E, sigTP1_E) node _io_rawOut_sig_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _io_rawOut_sig_T_2 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_1) connect io.rawOut.sig, _io_rawOut_sig_T_2
module DivSqrtRecF64ToRaw_mulAddZ31_1( // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_invalidExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_infiniteExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isNaN, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isInf, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isZero, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_sign, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [12:0] io_rawOut_sExp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [55:0] io_rawOut_sig // @[DivSqrtRecF64_mulAddZ31.scala:53:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [11:0] _zComplFractK0_A4_div_T = 12'h1C; // @[DivSqrtRecF64_mulAddZ31.scala:460:33] wire [11:0] _zComplFractK0_A4_div_T_2 = 12'h3A2; // @[DivSqrtRecF64_mulAddZ31.scala:461:33] wire [11:0] _zComplFractK0_A4_div_T_5 = 12'h675; // @[DivSqrtRecF64_mulAddZ31.scala:462:33] wire [11:0] _zComplFractK0_A4_div_T_8 = 12'h8C6; // @[DivSqrtRecF64_mulAddZ31.scala:463:33] wire [11:0] _zComplFractK0_A4_div_T_11 = 12'hAB4; // @[DivSqrtRecF64_mulAddZ31.scala:464:33] wire [11:0] _zComplFractK0_A4_div_T_14 = 12'hC56; // @[DivSqrtRecF64_mulAddZ31.scala:465:33] wire [11:0] _zComplFractK0_A4_div_T_17 = 12'hDBD; // @[DivSqrtRecF64_mulAddZ31.scala:466:33] wire [11:0] _zComplFractK0_A4_div_T_20 = 12'hEF4; // @[DivSqrtRecF64_mulAddZ31.scala:467:33] wire [9:0] _zComplK1_A7_sqrt_T = 10'h2F; // @[DivSqrtRecF64_mulAddZ31.scala:484:35] wire [9:0] _zComplK1_A7_sqrt_T_2 = 10'h1DF; // @[DivSqrtRecF64_mulAddZ31.scala:485:35] wire [9:0] _zComplK1_A7_sqrt_T_5 = 10'h14D; // @[DivSqrtRecF64_mulAddZ31.scala:486:35] wire [9:0] _zComplK1_A7_sqrt_T_8 = 10'h27E; // @[DivSqrtRecF64_mulAddZ31.scala:487:35] wire [12:0] _zComplFractK0_A6_sqrt_T = 13'h1A; // @[DivSqrtRecF64_mulAddZ31.scala:494:35] wire [12:0] _zComplFractK0_A6_sqrt_T_2 = 13'hBCA; // @[DivSqrtRecF64_mulAddZ31.scala:495:35] wire [12:0] _zComplFractK0_A6_sqrt_T_5 = 13'h12D3; // @[DivSqrtRecF64_mulAddZ31.scala:496:35] wire _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:432:22] wire [12:0] _zComplFractK0_A6_sqrt_T_8 = 13'h1B17; // @[DivSqrtRecF64_mulAddZ31.scala:497:35] wire _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:435:26] wire [3:0] _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] wire _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:578:35] wire [53:0] _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:588:63] wire _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:592:35] wire [53:0] _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:599:51] wire [104:0] _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:622:62] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:699:39] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:700:39] wire _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:702:40] wire _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:703:40] wire [12:0] _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] wire [55:0] _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:712:56] wire io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] reg [2:0] cycleNum_A; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] reg [3:0] cycleNum_B; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] reg [2:0] cycleNum_C; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] reg [2:0] cycleNum_E; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] reg valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] reg sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30] reg majorExc_PA; // @[DivSqrtRecF64_mulAddZ31.scala:93:30] reg isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30] reg isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30] reg isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30] reg sign_PA; // @[DivSqrtRecF64_mulAddZ31.scala:98:30] reg [12:0] sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30] reg [51:0] fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30] reg [51:0] fractA_PA; // @[DivSqrtRecF64_mulAddZ31.scala:101:30] reg [2:0] roundingMode_PA; // @[DivSqrtRecF64_mulAddZ31.scala:102:30] reg valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] reg sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30] reg majorExc_PB; // @[DivSqrtRecF64_mulAddZ31.scala:106:30] reg isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30] reg isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30] reg isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30] reg sign_PB; // @[DivSqrtRecF64_mulAddZ31.scala:111:30] reg [12:0] sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30] reg bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30] reg [51:0] fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30] reg [2:0] roundingMode_PB; // @[DivSqrtRecF64_mulAddZ31.scala:115:30] reg valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] reg sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30] reg majorExc_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30] reg isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30] assign io_rawOut_isNaN_0 = isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :121:30] reg isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30] assign io_rawOut_isInf_0 = isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :122:30] reg isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30] assign io_rawOut_isZero_0 = isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :123:30] reg sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:124:30] assign io_rawOut_sign_0 = sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :124:30] reg [12:0] sExp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:125:30] reg bit0FractA_PC; // @[DivSqrtRecF64_mulAddZ31.scala:126:30] reg [51:0] fractB_PC; // @[DivSqrtRecF64_mulAddZ31.scala:127:30] reg [2:0] roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:128:30] assign io_roundingModeOut_0 = roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :128:30] reg [8:0] fractR0_A; // @[DivSqrtRecF64_mulAddZ31.scala:130:30] reg [9:0] hiSqrR0_A_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:132:30] reg [20:0] partNegSigma0_A; // @[DivSqrtRecF64_mulAddZ31.scala:133:30] reg [8:0] nextMulAdd9A_A; // @[DivSqrtRecF64_mulAddZ31.scala:134:30] reg [8:0] nextMulAdd9B_A; // @[DivSqrtRecF64_mulAddZ31.scala:135:30] reg [16:0] ER1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30] reg [31:0] ESqrR1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30] reg [57:0] sigX1_B; // @[DivSqrtRecF64_mulAddZ31.scala:139:30] reg [32:0] sqrSigma1_C; // @[DivSqrtRecF64_mulAddZ31.scala:140:30] reg [57:0] sigXN_C; // @[DivSqrtRecF64_mulAddZ31.scala:141:30] reg [30:0] u_C_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:142:30] reg E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30] reg [53:0] sigT_E; // @[DivSqrtRecF64_mulAddZ31.scala:144:30] reg isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30] reg isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30] wire _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:355:28] wire ready_PA; // @[DivSqrtRecF64_mulAddZ31.scala:150:26] wire _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:390:28] wire ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26] wire _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:423:28] wire ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26] wire _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:354:28] wire leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26] wire _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:389:28] wire leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26] wire _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:422:28] wire leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:155:26] wire [45:0] _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:633:22] wire [45:0] zSigma1_B4; // @[DivSqrtRecF64_mulAddZ31.scala:157:34] wire [57:0] _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:635:38] wire [57:0] sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:158:34] wire [53:0] _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:644:12] wire [53:0] zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34] wire [53:0] _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:641:11] wire [53:0] zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34] wire _cyc_S_div_T = io_inReady_div_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:38] wire _cyc_S_div_T_1 = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55] wire cyc_S_div = _cyc_S_div_T & _cyc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:164:{38,52,55}] wire _cyc_S_sqrt_T = io_inReady_sqrt_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:38] wire cyc_S_sqrt = _cyc_S_sqrt_T & io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:{38,52}] wire cyc_S = cyc_S_div | cyc_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :165:52, :166:27] wire [11:0] rawA_S_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_S_isZero_T = rawA_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_S_isZero = _rawA_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_S_isZero_0 = rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_S_isSpecial_T = rawA_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_S_isSpecial = &_rawA_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_S_out_isNaN_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_S_out_isInf_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_S_out_isNaN_T_1 = rawA_S_isSpecial & _rawA_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_S_isNaN = _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_S_out_isInf_T_1 = ~_rawA_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_S_out_isInf_T_2 = rawA_S_isSpecial & _rawA_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_S_isInf = _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_S_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_S_sign = _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_S_out_sExp_T = {1'h0, rawA_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_S_sExp = _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_S_out_sig_T = ~rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_S_out_sig_T_1 = {1'h0, _rawA_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_S_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_S_out_sig_T_3 = {_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_S_sig = _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_S_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_S_isZero_T = rawB_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_S_isZero = _rawB_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_S_isZero_0 = rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_S_isSpecial_T = rawB_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_S_isSpecial = &_rawB_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_S_out_isNaN_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_S_out_isInf_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_S_out_isNaN_T_1 = rawB_S_isSpecial & _rawB_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_S_isNaN = _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_S_out_isInf_T_1 = ~_rawB_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_S_out_isInf_T_2 = rawB_S_isSpecial & _rawB_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_S_isInf = _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_S_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_S_sign = _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_S_out_sExp_T = {1'h0, rawB_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_S_sExp = _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_S_out_sig_T = ~rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_S_out_sig_T_1 = {1'h0, _rawB_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_S_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_S_out_sig_T_3 = {_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_S_sig = _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _notSigNaNIn_invalidExc_S_div_T = rawA_S_isZero_0 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_div_T_1 = rawA_S_isInf & rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:172:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:174:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_7 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = rawB_S_isNaN & _majorExc_S_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_4 = rawA_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = rawA_S_isNaN & _majorExc_S_T_5; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = rawB_S_isNaN & _majorExc_S_T_8; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :178:{38,66}] wire _majorExc_S_T_12 = ~rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_13 = ~rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:180:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:178:66, :179:46, :180:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :176:12, :177:38, :179:46] wire _isNaN_S_T = rawB_S_isNaN | notSigNaNIn_invalidExc_S_sqrt; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_1 = rawA_S_isNaN | rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :185:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :183:12, :184:26, :185:42] wire _isInf_S_T = rawA_S_isInf | rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire isInf_S = io_sqrtOp_0 ? rawB_S_isInf : _isInf_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _isZero_S_T = rawA_S_isZero_0 | rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire isZero_S = io_sqrtOp_0 ? rawB_S_isZero_0 : _isZero_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55, :189:19] wire _sign_S_T_1 = _sign_S_T & rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire sign_S = _sign_S_T_1 ^ rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseA_S_T = rawA_S_isNaN | rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseA_S = _specialCaseA_S_T | rawA_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseB_S_T = rawB_S_isNaN | rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseB_S = _specialCaseB_S_T | rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecF64_mulAddZ31.scala:191:55, :193:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:193:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48, :194:29] wire _normalCase_S_sqrt_T_1 = ~rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:194:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :193:45, :194:46, :195:27] wire _sExpQuot_S_div_T = rawB_S_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_1 = rawB_S_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:198:{44,56}] wire [11:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:198:{36,41,44}] wire [11:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:198:{41,65}] wire [13:0] sExpQuot_S_div = {rawA_S_sExp[12], rawA_S_sExp} + {{2{_sExpQuot_S_div_T_4[11]}}, _sExpQuot_S_div_T_4}; // @[rawFloatFromRecFN.scala:55:23] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 14'shDFF; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :201:24] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[12:9]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :203:27] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:201:{13,24}, :203:27, :257:30] wire [8:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :205:27] wire [12:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:201:13, :204:15, :205:27] wire [12:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:204:15, :206:11] wire entering_PA_normalCase_div = cyc_S_div & normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :193:45, :210:50] wire entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:165:52, :194:46, :211:50] wire entering_PA_normalCase = entering_PA_normalCase_div | entering_PA_normalCase_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :211:50, :213:36] wire [1:0] _cycleNum_A_T = {2{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :219:16] wire [2:0] _cycleNum_A_T_1 = entering_PA_normalCase_sqrt ? 3'h6 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :220:16] wire [2:0] _cycleNum_A_T_2 = {1'h0, _cycleNum_A_T} | _cycleNum_A_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:219:{16,69}, :220:16] wire _cycleNum_A_T_3 = ~entering_PA_normalCase; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :221:17] wire [3:0] _cycleNum_A_T_4 = {1'h0, cycleNum_A} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :221:57] wire [2:0] _cycleNum_A_T_5 = _cycleNum_A_T_4[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:221:57] wire [2:0] _cycleNum_A_T_6 = _cycleNum_A_T_3 ? _cycleNum_A_T_5 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:221:{16,17,57}] wire [2:0] _cycleNum_A_T_7 = _cycleNum_A_T_2 | _cycleNum_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:219:69, :220:69, :221:16] wire cyc_A6_sqrt = cycleNum_A == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :225:35] wire cyc_A5_sqrt = cycleNum_A == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :226:35] wire cyc_A4_sqrt = cycleNum_A == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :227:35] wire cyc_A4 = cyc_A4_sqrt | entering_PA_normalCase_div; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :227:35, :231:30] wire cyc_A3 = cycleNum_A == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :232:30] wire cyc_A2 = cycleNum_A == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :233:30] wire cyc_A1 = cycleNum_A == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :234:30] wire _cyc_A3_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32] wire cyc_A3_div = cyc_A3 & _cyc_A3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :236:{29,32}] wire _cyc_A2_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :237:32] wire cyc_A2_div = cyc_A2 & _cyc_A2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :237:{29,32}] wire _cyc_A1_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :238:32] wire cyc_A1_div = cyc_A1 & _cyc_A1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :238:{29,32}] wire cyc_A3_sqrt = cyc_A3 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :232:30, :240:30] wire cyc_A2_sqrt = cyc_A2 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :233:30, :241:30] wire cyc_A1_sqrt = cyc_A1 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :234:30, :242:30] wire [3:0] _cycleNum_B_T = sqrtOp_PA ? 4'hA : 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :247:20, :257:30] wire [4:0] _cycleNum_B_T_1 = {1'h0, cycleNum_B} - 5'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :248:28] wire [3:0] _cycleNum_B_T_2 = _cycleNum_B_T_1[3:0]; // @[DivSqrtRecF64_mulAddZ31.scala:248:28] wire [3:0] _cycleNum_B_T_3 = cyc_A1 ? _cycleNum_B_T : _cycleNum_B_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :246:16, :247:20, :248:28] wire cyc_B10_sqrt = cycleNum_B == 4'hA; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :252:36] wire cyc_B9_sqrt = cycleNum_B == 4'h9; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :253:36] wire cyc_B8_sqrt = cycleNum_B == 4'h8; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :254:36] wire cyc_B7_sqrt = cycleNum_B == 4'h7; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :255:36] wire cyc_B6 = cycleNum_B == 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :257:30] wire cyc_B5 = cycleNum_B == 4'h5; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :258:30] wire cyc_B4 = cycleNum_B == 4'h4; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :259:30] wire cyc_B3 = cycleNum_B == 4'h3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :260:30] wire cyc_B2 = cycleNum_B == 4'h2; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :261:30] wire cyc_B1 = cycleNum_B == 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :262:30] wire _cyc_B6_div_T = cyc_B6 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :257:30, :264:29] wire _cyc_B6_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :264:44] wire cyc_B6_div = _cyc_B6_div_T & _cyc_B6_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:264:{29,41,44}] wire _cyc_B5_div_T = cyc_B5 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :258:30, :265:29] wire _cyc_B5_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :265:44] wire cyc_B5_div = _cyc_B5_div_T & _cyc_B5_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:265:{29,41,44}] wire _cyc_B4_div_T = cyc_B4 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :259:30, :266:29] wire _cyc_B4_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :266:44] wire cyc_B4_div = _cyc_B4_div_T & _cyc_B4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:266:{29,41,44}] wire _cyc_B3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32] wire cyc_B3_div = cyc_B3 & _cyc_B3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :267:{29,32}] wire _cyc_B2_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :268:32] wire cyc_B2_div = cyc_B2 & _cyc_B2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :268:{29,32}] wire _cyc_B1_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :269:32] wire cyc_B1_div = cyc_B1 & _cyc_B1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :269:{29,32}] wire _cyc_B6_sqrt_T = cyc_B6 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :257:30, :271:30] wire cyc_B6_sqrt = _cyc_B6_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :271:{30,42}] wire _cyc_B5_sqrt_T = cyc_B5 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :258:30, :272:30] wire cyc_B5_sqrt = _cyc_B5_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :272:{30,42}] wire _cyc_B4_sqrt_T = cyc_B4 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :259:30, :273:30] wire cyc_B4_sqrt = _cyc_B4_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :273:{30,42}] wire cyc_B3_sqrt = cyc_B3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :260:30, :274:30] wire cyc_B2_sqrt = cyc_B2 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :261:30, :275:30] wire cyc_B1_sqrt = cyc_B1 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :262:30, :276:30] wire [2:0] _cycleNum_C_T = sqrtOp_PB ? 3'h6 : 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :280:28] wire [3:0] _cycleNum_C_T_1 = {1'h0, cycleNum_C} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:62] wire [2:0] _cycleNum_C_T_2 = _cycleNum_C_T_1[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:280:62] wire [2:0] _cycleNum_C_T_3 = cyc_B1 ? _cycleNum_C_T : _cycleNum_C_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :280:{16,28,62}] wire cyc_C6_sqrt = cycleNum_C == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :283:35] wire cyc_C5 = cycleNum_C == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :285:30] wire cyc_C4 = cycleNum_C == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :286:30] wire cyc_C3 = cycleNum_C == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :287:30] wire cyc_C2 = cycleNum_C == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :288:30] wire cyc_C1 = cycleNum_C == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :289:30] wire _cyc_C5_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :291:32] wire cyc_C5_div = cyc_C5 & _cyc_C5_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :291:{29,32}] wire _cyc_C4_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :292:32] wire cyc_C4_div = cyc_C4 & _cyc_C4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :292:{29,32}] wire _cyc_C3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :293:32] wire cyc_C3_div = cyc_C3 & _cyc_C3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :293:{29,32}] wire _cyc_C2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32] wire cyc_C2_div = cyc_C2 & _cyc_C2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :294:{29,32}] wire _cyc_C1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :295:32] wire cyc_C1_div = cyc_C1 & _cyc_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :295:{29,32}] wire cyc_C5_sqrt = cyc_C5 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :285:30, :297:30] wire cyc_C4_sqrt = cyc_C4 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :286:30, :298:30] wire cyc_C3_sqrt = cyc_C3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :287:30, :299:30] wire cyc_C2_sqrt = cyc_C2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :288:30, :300:30] wire cyc_C1_sqrt = cyc_C1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :289:30, :301:30] wire [3:0] _cycleNum_E_T = {1'h0, cycleNum_E} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:51] wire [2:0] _cycleNum_E_T_1 = _cycleNum_E_T[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:304:51] wire [2:0] _cycleNum_E_T_2 = cyc_C1 ? 3'h4 : _cycleNum_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :304:{26,51}] wire cyc_E4 = cycleNum_E == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :307:30] wire cyc_E3 = cycleNum_E == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :308:30] wire cyc_E2 = cycleNum_E == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :309:30] wire cyc_E1 = cycleNum_E == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :310:30] wire _cyc_E4_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :312:32] wire cyc_E4_div = cyc_E4 & _cyc_E4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:307:30, :312:{29,32}] wire _cyc_E3_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :313:32] wire cyc_E3_div = cyc_E3 & _cyc_E3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:308:30, :313:{29,32}] wire _cyc_E2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :314:32] wire cyc_E2_div = cyc_E2 & _cyc_E2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:309:30, :314:{29,32}] wire _cyc_E1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :315:32] wire cyc_E1_div = cyc_E1 & _cyc_E1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :315:{29,32}] wire cyc_E4_sqrt = cyc_E4 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :307:30, :317:30] wire cyc_E3_sqrt = cyc_E3 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :308:30, :318:30] wire cyc_E2_sqrt = cyc_E2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :309:30, :319:30] wire cyc_E1_sqrt = cyc_E1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :310:30, :320:30] wire _entering_PA_T = ~ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :325:58] wire _entering_PA_T_1 = valid_PA | _entering_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:{55,58}] wire _entering_PA_T_2 = cyc_S & _entering_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :325:{42,55}] wire entering_PA = entering_PA_normalCase | _entering_PA_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :325:{32,42}] wire [12:0] _sExp_PA_T = io_sqrtOp_0 ? rawB_S_sExp : sSatExpQuot_S_div; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractB_PA_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A4_div_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A7_sqrt_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractA_PA_T = rawA_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_PA_T = ~isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :347:25] wire _normalCase_PA_T_1 = ~isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :347:39] wire _normalCase_PA_T_2 = _normalCase_PA_T & _normalCase_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:347:{25,36,39}] wire _normalCase_PA_T_3 = ~isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :347:53] wire normalCase_PA = _normalCase_PA_T_2 & _normalCase_PA_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:347:{36,50,53}] wire [52:0] sigA_PA = {1'h1, fractA_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :348:28] wire [52:0] sigB_PA = {1'h1, fractB_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :349:28] wire valid_normalCase_leaving_PA = cyc_B4_div | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :266:41, :351:50] wire valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :347:50, :351:50, :353:12] assign _leaving_PA_T = valid_PA & valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :353:12, :354:28] assign leaving_PA = _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :354:28] wire _ready_PA_T = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17] assign _ready_PA_T_1 = _ready_PA_T | valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:353:12, :355:{17,28}] assign ready_PA = _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :355:28] wire _entering_PB_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18] wire _entering_PB_S_T_1 = cyc_S & _entering_PB_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :360:{15,18}] wire _entering_PB_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :360:36] wire _entering_PB_S_T_3 = _entering_PB_S_T_1 & _entering_PB_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:360:{15,33,36}] wire _entering_PB_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29] wire _entering_PB_S_T_5 = ~ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :361:43] wire _entering_PB_S_T_6 = _entering_PB_S_T_4 & _entering_PB_S_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:361:{29,40,43}] wire _entering_PB_S_T_7 = leaving_PB | _entering_PB_S_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :361:{25,40}] wire entering_PB_S = _entering_PB_S_T_3 & _entering_PB_S_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:360:{33,47}, :361:25] wire _entering_PB_normalCase_T = valid_PA & normalCase_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :347:50, :363:18] wire entering_PB_normalCase = _entering_PB_normalCase_T & valid_normalCase_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:351:50, :363:{18,35}] wire entering_PB = entering_PB_S | leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :360:47, :364:37] wire _sqrtOp_PB_T = valid_PA ? sqrtOp_PA : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :92:30, :370:27] wire _majorExc_PB_T = valid_PA ? majorExc_PA : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :93:30, :176:12, :371:27] wire _isNaN_PB_T = valid_PA ? isNaN_PA : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :95:30, :183:12, :372:27] wire _isInf_PB_T = valid_PA ? isInf_PA : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :96:30, :187:23, :373:27] wire _isZero_PB_T = valid_PA ? isZero_PA : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :97:30, :188:23, :374:27] wire _sign_PB_T = valid_PA ? sign_PA : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :98:30, :189:47, :375:27] wire _bit0FractA_PB_T = fractA_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :379:37] wire [2:0] _roundingMode_PB_T = valid_PA ? roundingMode_PA : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :102:30, :381:31] wire _normalCase_PB_T = ~isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :384:25] wire _normalCase_PB_T_1 = ~isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :384:39] wire _normalCase_PB_T_2 = _normalCase_PB_T & _normalCase_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:384:{25,36,39}] wire _normalCase_PB_T_3 = ~isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :384:53] wire normalCase_PB = _normalCase_PB_T_2 & _normalCase_PB_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:384:{36,50,53}] wire valid_leaving_PB = normalCase_PB ? cyc_C3 : ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :287:30, :384:50, :388:12] assign _leaving_PB_T = valid_PB & valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :388:12, :389:28] assign leaving_PB = _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :389:28] wire _ready_PB_T = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :390:17] assign _ready_PB_T_1 = _ready_PB_T | valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:388:12, :390:{17,28}] assign ready_PB = _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :390:28] wire _entering_PC_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18, :395:18] wire _entering_PC_S_T_1 = cyc_S & _entering_PC_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :395:{15,18}] wire _entering_PC_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :395:36] wire _entering_PC_S_T_3 = _entering_PC_S_T_1 & _entering_PC_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:395:{15,33,36}] wire _entering_PC_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :395:50] wire _entering_PC_S_T_5 = _entering_PC_S_T_3 & _entering_PC_S_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:395:{33,47,50}] wire entering_PC_S = _entering_PC_S_T_5 & ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :395:{47,61}] wire _entering_PC_normalCase_T = valid_PB & normalCase_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :384:50, :397:18] wire entering_PC_normalCase = _entering_PC_normalCase_T & cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :397:{18,35}] wire entering_PC = entering_PC_S | leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :395:61, :398:37] wire _sqrtOp_PC_T = valid_PB ? sqrtOp_PB : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :105:30, :404:27] wire _majorExc_PC_T = valid_PB ? majorExc_PB : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :106:30, :176:12, :405:27] wire _isNaN_PC_T = valid_PB ? isNaN_PB : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :108:30, :183:12, :406:27] wire _isInf_PC_T = valid_PB ? isInf_PB : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :109:30, :187:23, :407:27] wire _isZero_PC_T = valid_PB ? isZero_PB : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :110:30, :188:23, :408:27] wire _sign_PC_T = valid_PB ? sign_PB : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :111:30, :189:47, :409:27] wire [2:0] _roundingMode_PC_T = valid_PB ? roundingMode_PB : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :115:30, :415:31] wire _normalCase_PC_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25] wire _normalCase_PC_T_1 = ~isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :418:39] wire _normalCase_PC_T_2 = _normalCase_PC_T & _normalCase_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:418:{25,36,39}] wire _normalCase_PC_T_3 = ~isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :418:53] wire normalCase_PC = _normalCase_PC_T_2 & _normalCase_PC_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:418:{36,50,53}] wire [52:0] sigB_PC = {1'h1, fractB_PC}; // @[DivSqrtRecF64_mulAddZ31.scala:127:30, :419:28] wire _valid_leaving_PC_T = ~normalCase_PC; // @[DivSqrtRecF64_mulAddZ31.scala:418:50, :421:28] wire valid_leaving_PC = _valid_leaving_PC_T | cyc_E1; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :421:{28,44}] assign _leaving_PC_T = valid_PC & valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :421:44, :422:28] assign leaving_PC = _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :422:28] wire _ready_PC_T = ~valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :423:17] assign _ready_PC_T_1 = _ready_PC_T | valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:421:44, :423:{17,28}] assign ready_PC = _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :423:28] wire _io_inReady_div_T = ~cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :430:21] wire _io_inReady_div_T_1 = ready_PA & _io_inReady_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :430:{18,21}] wire _io_inReady_div_T_2 = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38] wire _io_inReady_div_T_3 = _io_inReady_div_T_1 & _io_inReady_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:430:{18,35,38}] wire _io_inReady_div_T_4 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55] wire _io_inReady_div_T_5 = _io_inReady_div_T_3 & _io_inReady_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:430:{35,52,55}] wire _io_inReady_div_T_6 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13] wire _io_inReady_div_T_7 = _io_inReady_div_T_5 & _io_inReady_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:430:{52,69}, :431:13] wire _io_inReady_div_T_8 = ~cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :431:30] wire _io_inReady_div_T_9 = _io_inReady_div_T_7 & _io_inReady_div_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:430:69, :431:{27,30}] wire _io_inReady_div_T_10 = ~cyc_B2; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :431:42] wire _io_inReady_div_T_11 = _io_inReady_div_T_9 & _io_inReady_div_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:431:{27,39,42}] wire _io_inReady_div_T_12 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54] wire _io_inReady_div_T_13 = _io_inReady_div_T_11 & _io_inReady_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:431:{39,51,54}] wire _io_inReady_div_T_14 = ~cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :432:13] wire _io_inReady_div_T_15 = _io_inReady_div_T_13 & _io_inReady_div_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:431:{51,68}, :432:13] wire _io_inReady_div_T_16 = ~cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :432:25] assign _io_inReady_div_T_17 = _io_inReady_div_T_15 & _io_inReady_div_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:431:68, :432:{22,25}] assign io_inReady_div_0 = _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :432:22] wire _io_inReady_sqrt_T = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38, :434:21] wire _io_inReady_sqrt_T_1 = ready_PA & _io_inReady_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :434:{18,21}] wire _io_inReady_sqrt_T_2 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55, :434:38] wire _io_inReady_sqrt_T_3 = _io_inReady_sqrt_T_1 & _io_inReady_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:434:{18,35,38}] wire _io_inReady_sqrt_T_4 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13, :434:55] wire _io_inReady_sqrt_T_5 = _io_inReady_sqrt_T_3 & _io_inReady_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:434:{35,52,55}] wire _io_inReady_sqrt_T_6 = ~cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :435:13] wire _io_inReady_sqrt_T_7 = _io_inReady_sqrt_T_5 & _io_inReady_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:434:{52,69}, :435:13] wire _io_inReady_sqrt_T_8 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54, :435:29] assign _io_inReady_sqrt_T_9 = _io_inReady_sqrt_T_7 & _io_inReady_sqrt_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:434:69, :435:{26,29}] assign io_inReady_sqrt_0 = _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :435:26] wire [51:0] zFractB_A4_div = entering_PA_normalCase_div ? _zFractB_A4_div_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :440:{29,52}] wire [2:0] _zLinPiece_0_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_1_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_2_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_3_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_4_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_5_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_6_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_7_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire _zLinPiece_0_A4_div_T_1 = _zLinPiece_0_A4_div_T == 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:{55,64}] wire zLinPiece_0_A4_div = entering_PA_normalCase_div & _zLinPiece_0_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :442:{41,64}] wire _zLinPiece_1_A4_div_T_1 = _zLinPiece_1_A4_div_T == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:443:{55,64}] wire zLinPiece_1_A4_div = entering_PA_normalCase_div & _zLinPiece_1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :443:{41,64}] wire _zLinPiece_2_A4_div_T_1 = _zLinPiece_2_A4_div_T == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:444:{55,64}] wire zLinPiece_2_A4_div = entering_PA_normalCase_div & _zLinPiece_2_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :444:{41,64}] wire _zLinPiece_3_A4_div_T_1 = _zLinPiece_3_A4_div_T == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:445:{55,64}] wire zLinPiece_3_A4_div = entering_PA_normalCase_div & _zLinPiece_3_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :445:{41,64}] wire _zLinPiece_4_A4_div_T_1 = _zLinPiece_4_A4_div_T == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:446:{55,64}] wire zLinPiece_4_A4_div = entering_PA_normalCase_div & _zLinPiece_4_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :446:{41,64}] wire _zLinPiece_5_A4_div_T_1 = _zLinPiece_5_A4_div_T == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:447:{55,64}] wire zLinPiece_5_A4_div = entering_PA_normalCase_div & _zLinPiece_5_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :447:{41,64}] wire _zLinPiece_6_A4_div_T_1 = _zLinPiece_6_A4_div_T == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:448:{55,64}] wire zLinPiece_6_A4_div = entering_PA_normalCase_div & _zLinPiece_6_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :448:{41,64}] wire _zLinPiece_7_A4_div_T_1 = &_zLinPiece_7_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:449:{55,64}] wire zLinPiece_7_A4_div = entering_PA_normalCase_div & _zLinPiece_7_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :449:{41,64}] wire [8:0] _zK1_A4_div_T = zLinPiece_0_A4_div ? 9'h1C7 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :451:12] wire [8:0] _zK1_A4_div_T_1 = zLinPiece_1_A4_div ? 9'h16C : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :452:12] wire [8:0] _zK1_A4_div_T_2 = _zK1_A4_div_T | _zK1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:451:{12,48}, :452:12] wire [8:0] _zK1_A4_div_T_3 = zLinPiece_2_A4_div ? 9'h12A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :453:12] wire [8:0] _zK1_A4_div_T_4 = _zK1_A4_div_T_2 | _zK1_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:451:48, :452:48, :453:12] wire [7:0] _zK1_A4_div_T_5 = zLinPiece_3_A4_div ? 8'hF8 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :454:12] wire [8:0] _zK1_A4_div_T_6 = {_zK1_A4_div_T_4[8], _zK1_A4_div_T_4[7:0] | _zK1_A4_div_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:452:48, :453:48, :454:12] wire [7:0] _zK1_A4_div_T_7 = zLinPiece_4_A4_div ? 8'hD2 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :455:12] wire [8:0] _zK1_A4_div_T_8 = {_zK1_A4_div_T_6[8], _zK1_A4_div_T_6[7:0] | _zK1_A4_div_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:453:48, :454:48, :455:12] wire [7:0] _zK1_A4_div_T_9 = zLinPiece_5_A4_div ? 8'hB4 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :456:12] wire [8:0] _zK1_A4_div_T_10 = {_zK1_A4_div_T_8[8], _zK1_A4_div_T_8[7:0] | _zK1_A4_div_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:454:48, :455:48, :456:12] wire [7:0] _zK1_A4_div_T_11 = zLinPiece_6_A4_div ? 8'h9C : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :457:12] wire [8:0] _zK1_A4_div_T_12 = {_zK1_A4_div_T_10[8], _zK1_A4_div_T_10[7:0] | _zK1_A4_div_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:455:48, :456:48, :457:12] wire [7:0] _zK1_A4_div_T_13 = zLinPiece_7_A4_div ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :458:12] wire [8:0] zK1_A4_div = {_zK1_A4_div_T_12[8], _zK1_A4_div_T_12[7:0] | _zK1_A4_div_T_13}; // @[DivSqrtRecF64_mulAddZ31.scala:456:48, :457:48, :458:12] wire [11:0] _zComplFractK0_A4_div_T_1 = zLinPiece_0_A4_div ? 12'h1C : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :460:12] wire [11:0] _zComplFractK0_A4_div_T_3 = zLinPiece_1_A4_div ? 12'h3A2 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :461:12] wire [11:0] _zComplFractK0_A4_div_T_4 = _zComplFractK0_A4_div_T_1 | _zComplFractK0_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:460:{12,55}, :461:12] wire [11:0] _zComplFractK0_A4_div_T_6 = zLinPiece_2_A4_div ? 12'h675 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :462:12] wire [11:0] _zComplFractK0_A4_div_T_7 = _zComplFractK0_A4_div_T_4 | _zComplFractK0_A4_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:460:55, :461:55, :462:12] wire [11:0] _zComplFractK0_A4_div_T_9 = zLinPiece_3_A4_div ? 12'h8C6 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :463:12] wire [11:0] _zComplFractK0_A4_div_T_10 = _zComplFractK0_A4_div_T_7 | _zComplFractK0_A4_div_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:461:55, :462:55, :463:12] wire [11:0] _zComplFractK0_A4_div_T_12 = zLinPiece_4_A4_div ? 12'hAB4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :464:12] wire [11:0] _zComplFractK0_A4_div_T_13 = _zComplFractK0_A4_div_T_10 | _zComplFractK0_A4_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:462:55, :463:55, :464:12] wire [11:0] _zComplFractK0_A4_div_T_15 = zLinPiece_5_A4_div ? 12'hC56 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :465:12] wire [11:0] _zComplFractK0_A4_div_T_16 = _zComplFractK0_A4_div_T_13 | _zComplFractK0_A4_div_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:463:55, :464:55, :465:12] wire [11:0] _zComplFractK0_A4_div_T_18 = zLinPiece_6_A4_div ? 12'hDBD : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :466:12] wire [11:0] _zComplFractK0_A4_div_T_19 = _zComplFractK0_A4_div_T_16 | _zComplFractK0_A4_div_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:464:55, :465:55, :466:12] wire [11:0] _zComplFractK0_A4_div_T_21 = zLinPiece_7_A4_div ? 12'hEF4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :467:12] wire [11:0] zComplFractK0_A4_div = _zComplFractK0_A4_div_T_19 | _zComplFractK0_A4_div_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:465:55, :466:55, :467:12] wire [51:0] zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? _zFractB_A7_sqrt_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :469:{30,54}] wire _zQuadPiece_0_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_1 = ~_zQuadPiece_0_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:472:{24,37}] wire _zQuadPiece_0_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_0_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :472:{21,24}] wire _zQuadPiece_0_A7_sqrt_T_4 = ~_zQuadPiece_0_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:472:{44,56}] wire zQuadPiece_0_A7_sqrt = _zQuadPiece_0_A7_sqrt_T_2 & _zQuadPiece_0_A7_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:472:{21,41,44}] wire _zQuadPiece_1_A7_sqrt_T_1 = ~_zQuadPiece_1_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:474:{24,37}] wire _zQuadPiece_1_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_1_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :474:{21,24}] wire zQuadPiece_1_A7_sqrt = _zQuadPiece_1_A7_sqrt_T_2 & _zQuadPiece_1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:474:{21,41,56}] wire _zQuadPiece_2_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_2_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :476:{21,37}] wire _zQuadPiece_2_A7_sqrt_T_3 = ~_zQuadPiece_2_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:476:{44,56}] wire zQuadPiece_2_A7_sqrt = _zQuadPiece_2_A7_sqrt_T_1 & _zQuadPiece_2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:476:{21,41,44}] wire _zQuadPiece_3_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_3_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :477:{44,58}] wire zQuadPiece_3_A7_sqrt = _zQuadPiece_3_A7_sqrt_T_1 & _zQuadPiece_3_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:477:{44,62,75}] wire [8:0] _zK2_A7_sqrt_T = zQuadPiece_0_A7_sqrt ? 9'h1C8 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :479:12] wire [7:0] _zK2_A7_sqrt_T_1 = zQuadPiece_1_A7_sqrt ? 8'hC1 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :480:12] wire [8:0] _zK2_A7_sqrt_T_2 = {_zK2_A7_sqrt_T[8], _zK2_A7_sqrt_T[7:0] | _zK2_A7_sqrt_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:479:{12,50}, :480:12] wire [8:0] _zK2_A7_sqrt_T_3 = zQuadPiece_2_A7_sqrt ? 9'h143 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :481:12] wire [8:0] _zK2_A7_sqrt_T_4 = _zK2_A7_sqrt_T_2 | _zK2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:479:50, :480:50, :481:12] wire [7:0] _zK2_A7_sqrt_T_5 = zQuadPiece_3_A7_sqrt ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :482:12] wire [8:0] zK2_A7_sqrt = {_zK2_A7_sqrt_T_4[8], _zK2_A7_sqrt_T_4[7:0] | _zK2_A7_sqrt_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:480:50, :481:50, :482:12] wire [9:0] _zComplK1_A7_sqrt_T_1 = zQuadPiece_0_A7_sqrt ? 10'h2F : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :484:12] wire [9:0] _zComplK1_A7_sqrt_T_3 = zQuadPiece_1_A7_sqrt ? 10'h1DF : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_4 = _zComplK1_A7_sqrt_T_1 | _zComplK1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:484:{12,57}, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_6 = zQuadPiece_2_A7_sqrt ? 10'h14D : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_7 = _zComplK1_A7_sqrt_T_4 | _zComplK1_A7_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:484:57, :485:57, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_9 = zQuadPiece_3_A7_sqrt ? 10'h27E : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :487:12] wire [9:0] zComplK1_A7_sqrt = _zComplK1_A7_sqrt_T_7 | _zComplK1_A7_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:485:57, :486:57, :487:12] wire _zQuadPiece_0_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56] wire _zQuadPiece_1_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :490:56] wire _zQuadPiece_2_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :491:56] wire _zQuadPiece_3_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :492:56] wire _sqrR0_A5_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :533:36] wire _ER1_A1_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :539:34] wire _zQuadPiece_0_A6_sqrt_T_1 = ~_zQuadPiece_0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:489:{47,56}] wire _zQuadPiece_0_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_0_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :489:{44,47}] wire _zQuadPiece_0_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72] wire _zQuadPiece_1_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :490:72] wire _zQuadPiece_2_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :491:72] wire _zQuadPiece_3_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :492:72] wire _zQuadPiece_0_A6_sqrt_T_4 = ~_zQuadPiece_0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:489:{63,72}] wire zQuadPiece_0_A6_sqrt = _zQuadPiece_0_A6_sqrt_T_2 & _zQuadPiece_0_A6_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:489:{44,60,63}] wire _zQuadPiece_1_A6_sqrt_T_1 = ~_zQuadPiece_1_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:490:{47,56}] wire _zQuadPiece_1_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_1_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :490:{44,47}] wire zQuadPiece_1_A6_sqrt = _zQuadPiece_1_A6_sqrt_T_2 & _zQuadPiece_1_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:490:{44,60,72}] wire _zQuadPiece_2_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_2_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :491:{44,56}] wire _zQuadPiece_2_A6_sqrt_T_3 = ~_zQuadPiece_2_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:491:{63,72}] wire zQuadPiece_2_A6_sqrt = _zQuadPiece_2_A6_sqrt_T_1 & _zQuadPiece_2_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:491:{44,60,63}] wire _zQuadPiece_3_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_3_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :492:{44,56}] wire zQuadPiece_3_A6_sqrt = _zQuadPiece_3_A6_sqrt_T_1 & _zQuadPiece_3_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:492:{44,60,72}] wire [12:0] _zComplFractK0_A6_sqrt_T_1 = zQuadPiece_0_A6_sqrt ? 13'h1A : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:489:60, :494:12] wire [12:0] _zComplFractK0_A6_sqrt_T_3 = zQuadPiece_1_A6_sqrt ? 13'hBCA : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:490:60, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_4 = _zComplFractK0_A6_sqrt_T_1 | _zComplFractK0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:494:{12,58}, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_6 = zQuadPiece_2_A6_sqrt ? 13'h12D3 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:491:60, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_7 = _zComplFractK0_A6_sqrt_T_4 | _zComplFractK0_A6_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:494:58, :495:58, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_9 = zQuadPiece_3_A6_sqrt ? 13'h1B17 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:492:60, :497:12] wire [12:0] zComplFractK0_A6_sqrt = _zComplFractK0_A6_sqrt_T_7 | _zComplFractK0_A6_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:495:58, :496:58, :497:12] wire [8:0] _mulAdd9A_A_T = zFractB_A4_div[48:40]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :500:23] wire [8:0] _mulAdd9A_A_T_1 = _mulAdd9A_A_T | zK2_A7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:481:50, :500:{23,32}] wire _mulAdd9A_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17] wire [8:0] _mulAdd9A_A_T_3 = _mulAdd9A_A_T_2 ? nextMulAdd9A_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :501:{16,17}] wire [8:0] mulAdd9A_A = _mulAdd9A_A_T_1 | _mulAdd9A_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:500:{32,46}, :501:16] wire [8:0] _mulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37] wire [8:0] _nextMulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37, :563:28] wire [8:0] _mulAdd9B_A_T_1 = zK1_A4_div | _mulAdd9B_A_T; // @[DivSqrtRecF64_mulAddZ31.scala:457:48, :503:{20,37}] wire _mulAdd9B_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17, :504:17] wire [8:0] _mulAdd9B_A_T_3 = _mulAdd9B_A_T_2 ? nextMulAdd9B_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :504:{16,17}] wire [8:0] mulAdd9B_A = _mulAdd9B_A_T_1 | _mulAdd9B_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:503:{20,46}, :504:16] wire [9:0] _mulAdd9C_A_T = {10{entering_PA_normalCase_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :507:50] wire [19:0] _mulAdd9C_A_T_1 = {zComplK1_A7_sqrt, _mulAdd9C_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:486:57, :507:{26,50}] wire [5:0] _mulAdd9C_A_T_2 = {6{cyc_A6_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :508:53] wire [13:0] mulAdd9C_A_hi = {cyc_A6_sqrt, zComplFractK0_A6_sqrt}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :496:58, :508:12] wire [19:0] _mulAdd9C_A_T_3 = {mulAdd9C_A_hi, _mulAdd9C_A_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:508:{12,53}] wire [19:0] _mulAdd9C_A_T_4 = _mulAdd9C_A_T_1 | _mulAdd9C_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:507:{26,68}, :508:12] wire [7:0] _mulAdd9C_A_T_5 = {8{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :509:53] wire [12:0] mulAdd9C_A_hi_1 = {entering_PA_normalCase_div, zComplFractK0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :466:55, :509:12] wire [20:0] _mulAdd9C_A_T_6 = {mulAdd9C_A_hi_1, _mulAdd9C_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:509:{12,53}] wire [20:0] _mulAdd9C_A_T_7 = {1'h0, _mulAdd9C_A_T_4} | _mulAdd9C_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:507:68, :508:71, :509:12] wire [18:0] _mulAdd9C_A_T_8 = {fractR0_A, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :510:53] wire [19:0] _mulAdd9C_A_T_9 = {1'h0, _mulAdd9C_A_T_8} + 20'h40000; // @[DivSqrtRecF64_mulAddZ31.scala:510:{40,53}] wire [19:0] _mulAdd9C_A_T_10 = cyc_A5_sqrt ? _mulAdd9C_A_T_9 : 20'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :510:{12,40}] wire [20:0] _mulAdd9C_A_T_11 = {_mulAdd9C_A_T_7[20], _mulAdd9C_A_T_7[19:0] | _mulAdd9C_A_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:508:71, :509:71, :510:12] wire _mulAdd9C_A_T_12 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44] wire _mulAdd9C_A_T_17 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44, :512:43] wire _mulAdd9C_A_T_13 = ~_mulAdd9C_A_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:511:{28,44}] wire _mulAdd9C_A_T_14 = cyc_A4_sqrt & _mulAdd9C_A_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :511:{25,28}] wire [10:0] _mulAdd9C_A_T_15 = {_mulAdd9C_A_T_14, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:511:{12,25}] wire [20:0] _mulAdd9C_A_T_16 = {_mulAdd9C_A_T_11[20:11], _mulAdd9C_A_T_11[10:0] | _mulAdd9C_A_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:509:71, :510:65, :511:12] wire _mulAdd9C_A_T_18 = cyc_A4_sqrt & _mulAdd9C_A_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :512:{26,43}] wire _mulAdd9C_A_T_19 = _mulAdd9C_A_T_18 | cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:236:29, :512:{26,48}] wire [20:0] _mulAdd9C_A_T_20 = sigB_PA[46:26]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :513:20] wire [21:0] _mulAdd9C_A_T_21 = {1'h0, _mulAdd9C_A_T_20} + 22'h400; // @[DivSqrtRecF64_mulAddZ31.scala:513:{20,29}] wire [20:0] _mulAdd9C_A_T_22 = _mulAdd9C_A_T_21[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:513:29] wire [20:0] _mulAdd9C_A_T_23 = _mulAdd9C_A_T_19 ? _mulAdd9C_A_T_22 : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:512:{12,48}, :513:29] wire [20:0] _mulAdd9C_A_T_24 = _mulAdd9C_A_T_16 | _mulAdd9C_A_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:510:65, :511:65, :512:12] wire _mulAdd9C_A_T_25 = cyc_A3_sqrt | cyc_A2; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :240:30, :516:25] wire [20:0] _mulAdd9C_A_T_26 = _mulAdd9C_A_T_25 ? partNegSigma0_A : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :516:{12,25}] wire [20:0] _mulAdd9C_A_T_27 = _mulAdd9C_A_T_24 | _mulAdd9C_A_T_26; // @[DivSqrtRecF64_mulAddZ31.scala:511:65, :515:11, :516:12] wire [24:0] _mulAdd9C_A_T_28 = {fractR0_A, 16'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :517:45] wire [24:0] _mulAdd9C_A_T_29 = cyc_A1_sqrt ? _mulAdd9C_A_T_28 : 25'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :517:{12,45}] wire [24:0] _mulAdd9C_A_T_30 = {4'h0, _mulAdd9C_A_T_27} | _mulAdd9C_A_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:515:11, :516:58, :517:12] wire [23:0] _mulAdd9C_A_T_31 = {fractR0_A, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :518:45] wire [23:0] _mulAdd9C_A_T_32 = cyc_A1_div ? _mulAdd9C_A_T_31 : 24'h0; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :518:{12,45}] wire [24:0] mulAdd9C_A = {_mulAdd9C_A_T_30[24], _mulAdd9C_A_T_30[23:0] | _mulAdd9C_A_T_32}; // @[DivSqrtRecF64_mulAddZ31.scala:516:58, :517:58, :518:12] wire [17:0] _loMulAdd9Out_A_T = {9'h0, mulAdd9A_A} * {9'h0, mulAdd9B_A}; // @[DivSqrtRecF64_mulAddZ31.scala:500:46, :503:46, :519:37] wire [17:0] _loMulAdd9Out_A_T_1 = mulAdd9C_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :519:63] wire [18:0] loMulAdd9Out_A = {1'h0, _loMulAdd9Out_A_T} + {1'h0, _loMulAdd9Out_A_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:519:{37,50,63}] wire _mulAdd9Out_A_T = loMulAdd9Out_A[18]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :521:31] wire [6:0] _mulAdd9Out_A_T_1 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27] wire [6:0] _mulAdd9Out_A_T_4 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27, :523:27] wire [7:0] _mulAdd9Out_A_T_2 = {1'h0, _mulAdd9Out_A_T_1} + 8'h1; // @[DivSqrtRecF64_mulAddZ31.scala:522:{27,36}] wire [6:0] _mulAdd9Out_A_T_3 = _mulAdd9Out_A_T_2[6:0]; // @[DivSqrtRecF64_mulAddZ31.scala:522:36] wire [6:0] _mulAdd9Out_A_T_5 = _mulAdd9Out_A_T ? _mulAdd9Out_A_T_3 : _mulAdd9Out_A_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:521:{16,31}, :522:36, :523:27] wire [17:0] _mulAdd9Out_A_T_6 = loMulAdd9Out_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :525:27] wire [24:0] mulAdd9Out_A = {_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6}; // @[DivSqrtRecF64_mulAddZ31.scala:521:{12,16}, :525:27] wire _zFractR0_A6_sqrt_T = mulAdd9Out_A[19]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:40] wire _zFractR0_A6_sqrt_T_1 = cyc_A6_sqrt & _zFractR0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :529:{25,40}] wire [14:0] _zFractR0_A6_sqrt_T_2 = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60] wire [14:0] _r1_A1_T = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60, :538:56] wire [14:0] _zFractR0_A6_sqrt_T_3 = ~_zFractR0_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:529:{46,60}] wire [14:0] zFractR0_A6_sqrt = _zFractR0_A6_sqrt_T_1 ? _zFractR0_A6_sqrt_T_3 : 15'h0; // @[DivSqrtRecF64_mulAddZ31.scala:529:{12,25,46}] wire [25:0] _sqrR0_A5_sqrt_T_1 = {mulAdd9Out_A, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:53] wire [25:0] sqrR0_A5_sqrt = _sqrR0_A5_sqrt_T ? _sqrR0_A5_sqrt_T_1 : {1'h0, mulAdd9Out_A}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:{28,36,53}] wire _zFractR0_A4_div_T = mulAdd9Out_A[20]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:39] wire _zFractR0_A4_div_T_1 = entering_PA_normalCase_div & _zFractR0_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :535:{24,39}] wire [13:0] _zFractR0_A4_div_T_2 = mulAdd9Out_A[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:59] wire [13:0] _zFractR0_A4_div_T_3 = ~_zFractR0_A4_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:535:{45,59}] wire [13:0] zFractR0_A4_div = _zFractR0_A4_div_T_1 ? _zFractR0_A4_div_T_3 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:535:{12,24,45}] wire _zSigma0_A2_T = mulAdd9Out_A[11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:35] wire _zSigma0_A2_T_1 = cyc_A2 & _zSigma0_A2_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :537:{20,35}] wire [22:0] _zSigma0_A2_T_2 = mulAdd9Out_A[24:2]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:55] wire [22:0] _zSigma0_A2_T_3 = ~_zSigma0_A2_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:537:{41,55}] wire [22:0] zSigma0_A2 = _zSigma0_A2_T_1 ? _zSigma0_A2_T_3 : 23'h0; // @[DivSqrtRecF64_mulAddZ31.scala:537:{12,20,41}] wire [15:0] _r1_A1_T_1 = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74] wire [15:0] _partNegSigma0_A_T = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74, :548:71] wire [15:0] _r1_A1_T_2 = sqrtOp_PA ? {1'h0, _r1_A1_T} : _r1_A1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :538:{32,56,74}] wire [15:0] r1_A1 = _r1_A1_T_2 | 16'h8000; // @[DivSqrtRecF64_mulAddZ31.scala:538:{27,32}] wire [16:0] _ER1_A1_sqrt_T_1 = {r1_A1, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:44] wire [16:0] ER1_A1_sqrt = _ER1_A1_sqrt_T ? _ER1_A1_sqrt_T_1 : {1'h0, r1_A1}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:{26,34,44}] wire [14:0] _fractR0_A_T = {zFractR0_A6_sqrt[14], zFractR0_A6_sqrt[13:0] | zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :535:12, :542:39] wire [15:0] _hiSqrR0_A_sqrt_T = sqrR0_A5_sqrt[25:10]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :545:40] wire [24:0] _partNegSigma0_A_T_1 = cyc_A4_sqrt ? mulAdd9Out_A : {9'h0, _partNegSigma0_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :521:12, :548:{31,71}] wire [24:0] _nextMulAdd9A_A_T = ~mulAdd9Out_A; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :554:40] wire [13:0] _nextMulAdd9A_A_T_1 = _nextMulAdd9A_A_T[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:554:{40,53}] wire [13:0] _nextMulAdd9A_A_T_2 = entering_PA_normalCase_sqrt ? _nextMulAdd9A_A_T_1 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :554:{16,53}] wire [14:0] _nextMulAdd9A_A_T_3 = {1'h0, _nextMulAdd9A_A_T_2} | zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :554:{16,64}] wire [8:0] _nextMulAdd9A_A_T_4 = sigB_PA[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :556:47] wire [8:0] _nextMulAdd9A_A_T_5 = cyc_A4_sqrt ? _nextMulAdd9A_A_T_4 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :556:{16,47}] wire [14:0] _nextMulAdd9A_A_T_6 = {_nextMulAdd9A_A_T_3[14:9], _nextMulAdd9A_A_T_3[8:0] | _nextMulAdd9A_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:554:64, :555:68, :556:16] wire [8:0] _nextMulAdd9A_A_T_7 = zFractB_A4_div[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :557:27] wire [14:0] _nextMulAdd9A_A_T_8 = {_nextMulAdd9A_A_T_6[14:9], _nextMulAdd9A_A_T_6[8:0] | _nextMulAdd9A_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:555:68, :556:64, :557:27] wire _nextMulAdd9A_A_T_9 = cyc_A5_sqrt | cyc_A3; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :232:30, :558:29] wire [8:0] _nextMulAdd9A_A_T_10 = sigB_PA[52:44]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :558:47] wire [8:0] _nextMulAdd9A_A_T_11 = _nextMulAdd9A_A_T_9 ? _nextMulAdd9A_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:558:{16,29,47}] wire [14:0] _nextMulAdd9A_A_T_12 = {_nextMulAdd9A_A_T_8[14:9], _nextMulAdd9A_A_T_8[8:0] | _nextMulAdd9A_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:556:64, :557:68, :558:16] wire [22:0] _nextMulAdd9A_A_T_13 = {8'h0, _nextMulAdd9A_A_T_12} | zSigma0_A2; // @[DivSqrtRecF64_mulAddZ31.scala:537:12, :557:68, :558:64] wire [14:0] _nextMulAdd9B_A_T_1 = {6'h0, _nextMulAdd9B_A_T} | zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :563:{28,73}] wire [8:0] _nextMulAdd9B_A_T_2 = sqrR0_A5_sqrt[9:1]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :565:43] wire [8:0] _nextMulAdd9B_A_T_3 = cyc_A5_sqrt ? _nextMulAdd9B_A_T_2 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :565:{16,43}] wire [14:0] _nextMulAdd9B_A_T_4 = {_nextMulAdd9B_A_T_1[14:9], _nextMulAdd9B_A_T_1[8:0] | _nextMulAdd9B_A_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:563:73, :564:73, :565:16] wire [14:0] _nextMulAdd9B_A_T_5 = {_nextMulAdd9B_A_T_4[14], _nextMulAdd9B_A_T_4[13:0] | zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:535:12, :564:73, :565:69] wire [8:0] _nextMulAdd9B_A_T_6 = hiSqrR0_A_sqrt[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :567:44] wire [8:0] _nextMulAdd9B_A_T_7 = cyc_A4_sqrt ? _nextMulAdd9B_A_T_6 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :567:{16,44}] wire [14:0] _nextMulAdd9B_A_T_8 = {_nextMulAdd9B_A_T_5[14:9], _nextMulAdd9B_A_T_5[8:0] | _nextMulAdd9B_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:565:69, :566:73, :567:16] wire [7:0] _nextMulAdd9B_A_T_9 = fractR0_A[8:1]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :568:53] wire [8:0] _nextMulAdd9B_A_T_10 = {1'h1, _nextMulAdd9B_A_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:568:{33,53}] wire [8:0] _nextMulAdd9B_A_T_11 = cyc_A2 ? _nextMulAdd9B_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :568:{16,33}] wire [14:0] _nextMulAdd9B_A_T_12 = {_nextMulAdd9B_A_T_8[14:9], _nextMulAdd9B_A_T_8[8:0] | _nextMulAdd9B_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:566:73, :567:69, :568:16] wire _GEN = cyc_A1 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :255:36, :577:16] wire _io_latchMulAddA_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] assign _io_latchMulAddA_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] wire _io_latchMulAddB_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:591:16] assign _io_latchMulAddB_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16, :591:16] wire _io_latchMulAddA_0_T_1 = _io_latchMulAddA_0_T | cyc_B6_div; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :577:{16,31}] wire _io_latchMulAddA_0_T_2 = _io_latchMulAddA_0_T_1 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :577:{31,45}] wire _io_latchMulAddA_0_T_3 = _io_latchMulAddA_0_T_2 | cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :577:{45,55}] wire _io_latchMulAddA_0_T_4 = _io_latchMulAddA_0_T_3 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :577:{55,65}] wire _io_latchMulAddA_0_T_5 = _io_latchMulAddA_0_T_4 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :577:65, :578:25] assign _io_latchMulAddA_0_T_6 = _io_latchMulAddA_0_T_5 | cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :578:{25,35}] assign io_latchMulAddA_0_0 = _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :578:35] wire [52:0] _io_mulAddA_0_T = {ER1_A1_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:539:26, :580:51] wire [52:0] _io_mulAddA_0_T_1 = cyc_A1_sqrt ? _io_mulAddA_0_T : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :580:{12,51}] wire _io_mulAddA_0_T_2 = cyc_B7_sqrt | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :255:36, :581:25] wire [52:0] _io_mulAddA_0_T_3 = _io_mulAddA_0_T_2 ? sigB_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :581:{12,25}] wire [52:0] _io_mulAddA_0_T_4 = _io_mulAddA_0_T_1 | _io_mulAddA_0_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:580:{12,63}, :581:12] wire [52:0] _io_mulAddA_0_T_5 = cyc_B6_div ? sigA_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :348:28, :582:12] wire [52:0] _io_mulAddA_0_T_6 = _io_mulAddA_0_T_4 | _io_mulAddA_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:580:63, :581:63, :582:12] wire [33:0] _io_mulAddA_0_T_7 = zSigma1_B4[45:12]; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :583:19] wire [52:0] _io_mulAddA_0_T_8 = {_io_mulAddA_0_T_6[52:34], _io_mulAddA_0_T_6[33:0] | _io_mulAddA_0_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:581:63, :582:63, :583:19] wire _io_mulAddA_0_T_9 = cyc_B3 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :283:35, :585:20] wire [45:0] _io_mulAddA_0_T_10 = sigXNU_B3_CX[57:12]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :585:48] wire [45:0] _io_mulAddA_0_T_11 = _io_mulAddA_0_T_9 ? _io_mulAddA_0_T_10 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:585:{12,20,48}] wire [52:0] _io_mulAddA_0_T_12 = {_io_mulAddA_0_T_8[52:46], _io_mulAddA_0_T_8[45:0] | _io_mulAddA_0_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:582:63, :583:67, :585:12] wire [32:0] _io_mulAddA_0_T_13 = sigXN_C[57:25]; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :586:43] wire [45:0] _io_mulAddA_0_T_14 = {_io_mulAddA_0_T_13, 13'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:586:{43,51}] wire [45:0] _io_mulAddA_0_T_15 = cyc_C4_div ? _io_mulAddA_0_T_14 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:292:29, :586:{12,51}] wire [52:0] _io_mulAddA_0_T_16 = {_io_mulAddA_0_T_12[52:46], _io_mulAddA_0_T_12[45:0] | _io_mulAddA_0_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:583:67, :585:63, :586:12] wire [45:0] _io_mulAddA_0_T_17 = {u_C_sqrt, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :587:44] wire [45:0] _io_mulAddA_0_T_18 = cyc_C4_sqrt ? _io_mulAddA_0_T_17 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:298:30, :587:{12,44}] wire [52:0] _io_mulAddA_0_T_19 = {_io_mulAddA_0_T_16[52:46], _io_mulAddA_0_T_16[45:0] | _io_mulAddA_0_T_18}; // @[DivSqrtRecF64_mulAddZ31.scala:585:63, :586:63, :587:12] wire [52:0] _io_mulAddA_0_T_20 = cyc_C1_div ? sigB_PC : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :419:28, :588:12] wire [52:0] _io_mulAddA_0_T_21 = _io_mulAddA_0_T_19 | _io_mulAddA_0_T_20; // @[DivSqrtRecF64_mulAddZ31.scala:586:63, :587:63, :588:12] assign _io_mulAddA_0_T_22 = {1'h0, _io_mulAddA_0_T_21} | zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :587:63, :588:63] assign io_mulAddA_0_0 = _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :588:63] wire _io_latchMulAddB_0_T_1 = _io_latchMulAddB_0_T | cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :591:{16,31}] wire _io_latchMulAddB_0_T_2 = _io_latchMulAddB_0_T_1 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :591:{31,46}] wire _io_latchMulAddB_0_T_3 = _io_latchMulAddB_0_T_2 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :591:{46,56}] wire _io_latchMulAddB_0_T_4 = _io_latchMulAddB_0_T_3 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :591:56, :592:25] assign _io_latchMulAddB_0_T_5 = _io_latchMulAddB_0_T_4 | cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :592:{25,35}] assign io_latchMulAddB_0_0 = _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :592:35] wire [51:0] _io_mulAddB_0_T = {r1_A1, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :580:51, :594:31] wire [51:0] _io_mulAddB_0_T_1 = cyc_A1 ? _io_mulAddB_0_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :594:{12,31}] wire [50:0] _io_mulAddB_0_T_2 = {ESqrR1_B_sqrt, 19'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :595:39] wire [50:0] _io_mulAddB_0_T_3 = cyc_B7_sqrt ? _io_mulAddB_0_T_2 : 51'h0; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :595:{12,39}] wire [51:0] _io_mulAddB_0_T_4 = {_io_mulAddB_0_T_1[51], _io_mulAddB_0_T_1[50:0] | _io_mulAddB_0_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:594:{12,51}, :595:12] wire [52:0] _io_mulAddB_0_T_5 = {ER1_B_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :580:51, :596:36] wire [52:0] _io_mulAddB_0_T_6 = cyc_B6_sqrt ? _io_mulAddB_0_T_5 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :596:{12,36}] wire [52:0] _io_mulAddB_0_T_7 = {1'h0, _io_mulAddB_0_T_4} | _io_mulAddB_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:594:51, :595:51, :596:12] wire [52:0] _io_mulAddB_0_T_8 = {_io_mulAddB_0_T_7[52:46], _io_mulAddB_0_T_7[45:0] | zSigma1_B4}; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :595:51, :596:51] wire [29:0] _io_mulAddB_0_T_9 = sqrSigma1_C[30:1]; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :598:37] wire [29:0] _io_mulAddB_0_T_10 = cyc_C6_sqrt ? _io_mulAddB_0_T_9 : 30'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :598:{12,37}] wire [52:0] _io_mulAddB_0_T_11 = {_io_mulAddB_0_T_8[52:30], _io_mulAddB_0_T_8[29:0] | _io_mulAddB_0_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:596:51, :597:55, :598:12] wire [32:0] _io_mulAddB_0_T_12 = cyc_C4 ? sqrSigma1_C : 33'h0; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :286:30, :599:12] wire [52:0] _io_mulAddB_0_T_13 = {_io_mulAddB_0_T_11[52:33], _io_mulAddB_0_T_11[32:0] | _io_mulAddB_0_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:597:55, :598:51, :599:12] assign _io_mulAddB_0_T_14 = {1'h0, _io_mulAddB_0_T_13} | zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :598:51, :599:51] assign io_mulAddB_0_0 = _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :599:51] wire _io_usingMulAdd_T = cyc_A4 | cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:231:30, :236:29, :603:20] wire _io_usingMulAdd_T_1 = _io_usingMulAdd_T | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :603:{20,34}] wire _io_usingMulAdd_T_2 = _io_usingMulAdd_T_1 | cyc_B10_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:252:36, :603:{34,48}] wire _io_usingMulAdd_T_3 = _io_usingMulAdd_T_2 | cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :603:48, :604:30] wire _io_usingMulAdd_T_4 = _io_usingMulAdd_T_3 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :604:{30,45}] wire _io_usingMulAdd_T_5 = _io_usingMulAdd_T_4 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :604:{45,60}] wire _io_usingMulAdd_T_6 = _io_usingMulAdd_T_5 | cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :604:{60,70}] wire _io_usingMulAdd_T_7 = _io_usingMulAdd_T_6 | cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :604:70, :605:29] wire _io_usingMulAdd_T_8 = _io_usingMulAdd_T_7 | cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :605:{29,44}] wire _io_usingMulAdd_T_9 = _io_usingMulAdd_T_8 | cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :605:{44,58}] wire _io_usingMulAdd_T_10 = _io_usingMulAdd_T_9 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :605:{58,73}] wire _io_usingMulAdd_T_11 = cyc_A3 | cyc_A2_div; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :237:29, :607:20] wire _io_usingMulAdd_T_12 = _io_usingMulAdd_T_11 | cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :607:{20,34}] wire _io_usingMulAdd_T_13 = _io_usingMulAdd_T_12 | cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :607:34, :608:29] wire _io_usingMulAdd_T_14 = _io_usingMulAdd_T_13 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :608:{29,44}] wire _io_usingMulAdd_T_15 = _io_usingMulAdd_T_14 | cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :608:{44,54}] wire _io_usingMulAdd_T_16 = _io_usingMulAdd_T_15 | cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :608:{54,64}] wire _io_usingMulAdd_T_17 = _io_usingMulAdd_T_16 | cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :608:64, :609:29] wire _io_usingMulAdd_T_18 = _io_usingMulAdd_T_17 | cyc_B1_div; // @[DivSqrtRecF64_mulAddZ31.scala:269:29, :609:{29,44}] wire _io_usingMulAdd_T_19 = _io_usingMulAdd_T_18 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :609:{44,58}] wire _io_usingMulAdd_T_20 = _io_usingMulAdd_T_19 | cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :609:{58,73}] wire _io_usingMulAdd_T_21 = cyc_A2 | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :238:29, :611:20] wire _io_usingMulAdd_T_22 = _io_usingMulAdd_T_21 | cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :611:{20,34}] wire _io_usingMulAdd_T_23 = _io_usingMulAdd_T_22 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :611:34, :612:29] wire _io_usingMulAdd_T_24 = _io_usingMulAdd_T_23 | cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :612:{29,44}] wire _io_usingMulAdd_T_25 = _io_usingMulAdd_T_24 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :612:{44,54}] wire _io_usingMulAdd_T_26 = _io_usingMulAdd_T_25 | cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :612:{54,64}] wire _io_usingMulAdd_T_27 = _io_usingMulAdd_T_26 | cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :612:64, :613:29] wire _io_usingMulAdd_T_28 = _io_usingMulAdd_T_27 | cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :613:{29,44}] wire _io_usingMulAdd_T_29 = _io_usingMulAdd_T_28 | cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :613:{44,54}] wire _io_usingMulAdd_T_30 = io_latchMulAddA_0_0 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :257:30, :615:31] wire _io_usingMulAdd_T_31 = _io_usingMulAdd_T_30 | cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :615:{31,41}] wire [1:0] io_usingMulAdd_lo = {_io_usingMulAdd_T_29, _io_usingMulAdd_T_31}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :613:54, :615:41] wire [1:0] io_usingMulAdd_hi = {_io_usingMulAdd_T_10, _io_usingMulAdd_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :605:73, :609:73] assign _io_usingMulAdd_T_32 = {io_usingMulAdd_hi, io_usingMulAdd_lo}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] assign io_usingMulAdd_0 = _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :603:12] wire [104:0] _io_mulAddC_2_T = {sigX1_B, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :619:45] wire [104:0] _io_mulAddC_2_T_1 = cyc_B1 ? _io_mulAddC_2_T : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :619:{12,45}] wire [103:0] _io_mulAddC_2_T_2 = {sigX1_B, 46'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :620:45] wire [103:0] _io_mulAddC_2_T_3 = cyc_C6_sqrt ? _io_mulAddC_2_T_2 : 104'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :620:{12,45}] wire [104:0] _io_mulAddC_2_T_4 = {_io_mulAddC_2_T_1[104], _io_mulAddC_2_T_1[103:0] | _io_mulAddC_2_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:619:{12,62}, :620:12] wire _io_mulAddC_2_T_5 = cyc_C4_sqrt | cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :298:30, :621:25] wire [104:0] _io_mulAddC_2_T_6 = {sigXN_C, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :619:45, :621:45] wire [104:0] _io_mulAddC_2_T_7 = _io_mulAddC_2_T_5 ? _io_mulAddC_2_T_6 : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:621:{12,25,45}] wire [104:0] _io_mulAddC_2_T_8 = _io_mulAddC_2_T_4 | _io_mulAddC_2_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:619:62, :620:62, :621:12] wire _io_mulAddC_2_T_9 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27] wire _io_mulAddC_2_T_10 = cyc_E3_div & _io_mulAddC_2_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:313:29, :622:{24,27}] wire [53:0] _io_mulAddC_2_T_11 = {bit0FractA_PC, 53'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:126:30, :622:51] wire [53:0] _io_mulAddC_2_T_12 = _io_mulAddC_2_T_10 ? _io_mulAddC_2_T_11 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:622:{12,24,51}] wire [104:0] _io_mulAddC_2_T_13 = {_io_mulAddC_2_T_8[104:54], _io_mulAddC_2_T_8[53:0] | _io_mulAddC_2_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:620:62, :621:62, :622:12] wire _io_mulAddC_2_T_14 = sExp_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :624:25] wire _io_mulAddC_2_T_15 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25] wire _io_mulAddC_2_T_18 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:39] wire _io_mulAddC_2_T_20 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:54] wire [1:0] _io_mulAddC_2_T_16 = {_io_mulAddC_2_T_15, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:625:{25,28}] wire _io_mulAddC_2_T_17 = sigB_PC[1]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :626:26] wire _io_mulAddC_2_T_19 = _io_mulAddC_2_T_17 ^ _io_mulAddC_2_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:626:{26,30,39}] wire [1:0] _io_mulAddC_2_T_21 = {_io_mulAddC_2_T_19, _io_mulAddC_2_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:626:{30,44,54}] wire [1:0] _io_mulAddC_2_T_22 = _io_mulAddC_2_T_14 ? _io_mulAddC_2_T_16 : _io_mulAddC_2_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:624:{17,25}, :625:28, :626:44] wire _io_mulAddC_2_T_23 = sigT_E[0]; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :627:28] wire _io_mulAddC_2_T_24 = ~_io_mulAddC_2_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,28}] wire [1:0] _io_mulAddC_2_T_25 = {_io_mulAddC_2_T_24, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,32}] wire [1:0] _io_mulAddC_2_T_26 = _io_mulAddC_2_T_22 ^ _io_mulAddC_2_T_25; // @[DivSqrtRecF64_mulAddZ31.scala:624:17, :627:{16,32}] wire [55:0] _io_mulAddC_2_T_27 = {_io_mulAddC_2_T_26, 54'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:16, :628:14] wire [55:0] _io_mulAddC_2_T_28 = cyc_E3_sqrt ? _io_mulAddC_2_T_27 : 56'h0; // @[DivSqrtRecF64_mulAddZ31.scala:318:30, :623:12, :628:14] assign _io_mulAddC_2_T_29 = {_io_mulAddC_2_T_13[104:56], _io_mulAddC_2_T_13[55:0] | _io_mulAddC_2_T_28}; // @[DivSqrtRecF64_mulAddZ31.scala:621:62, :622:62, :623:12] assign io_mulAddC_2_0 = _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :622:62] wire [31:0] ESqrR1_B8_sqrt = io_mulAddResult_3_0[103:72]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :632:43] wire [45:0] _zSigma1_B4_T = io_mulAddResult_3_0[90:45]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :633:49] wire [45:0] _zSigma1_B4_T_1 = ~_zSigma1_B4_T; // @[DivSqrtRecF64_mulAddZ31.scala:633:{31,49}] assign _zSigma1_B4_T_2 = cyc_B4 ? _zSigma1_B4_T_1 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :633:{22,31}] assign zSigma1_B4 = _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :633:22] wire [32:0] sqrSigma1_B1 = io_mulAddResult_3_0[79:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :634:41] assign _sigXNU_B3_CX_T = io_mulAddResult_3_0[104:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :635:38] assign sigXNU_B3_CX = _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :635:38] wire _E_C1_div_T = io_mulAddResult_3_0[104]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :636:39] wire E_C1_div = ~_E_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:636:{20,39}] wire _zComplSigT_C1_T = ~E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:636:20, :638:28] wire _zComplSigT_C1_T_1 = cyc_C1_div & _zComplSigT_C1_T; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :638:{25,28}] wire _zComplSigT_C1_T_2 = _zComplSigT_C1_T_1 | cyc_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :638:{25,40}] wire [53:0] _zComplSigT_C1_T_3 = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31] wire [53:0] _zComplSigT_C1_sqrt_T = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31, :644:44] wire [53:0] _zComplSigT_C1_T_4 = ~_zComplSigT_C1_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:639:{13,31}] wire [53:0] _zComplSigT_C1_T_5 = _zComplSigT_C1_T_2 ? _zComplSigT_C1_T_4 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:638:{12,40}, :639:13] wire _zComplSigT_C1_T_6 = cyc_C1_div & E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :636:20, :642:24] wire [52:0] _zComplSigT_C1_T_7 = io_mulAddResult_3_0[102:50]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :642:55] wire [52:0] _zComplSigT_C1_T_8 = ~_zComplSigT_C1_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:642:{37,55}] wire [52:0] _zComplSigT_C1_T_9 = _zComplSigT_C1_T_6 ? _zComplSigT_C1_T_8 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:642:{12,24,37}] assign _zComplSigT_C1_T_10 = {_zComplSigT_C1_T_5[53], _zComplSigT_C1_T_5[52:0] | _zComplSigT_C1_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:638:12, :641:11, :642:12] assign zComplSigT_C1 = _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :641:11] wire [53:0] _zComplSigT_C1_sqrt_T_1 = ~_zComplSigT_C1_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:644:{26,44}] assign _zComplSigT_C1_sqrt_T_2 = cyc_C1_sqrt ? _zComplSigT_C1_sqrt_T_1 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :644:{12,26}] assign zComplSigT_C1_sqrt = _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :644:12] wire [53:0] sigT_C1 = ~zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :648:19] wire [55:0] remT_E2 = io_mulAddResult_3_0[55:0]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :649:36] wire [30:0] _u_C_sqrt_T = sigXNU_B3_CX[56:26]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :665:33] wire _isNegRemT_E_T = remT_E2[55]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:47] wire _isNegRemT_E_T_1 = remT_E2[53]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:61] wire _isNegRemT_E_T_2 = sqrtOp_PC ? _isNegRemT_E_T : _isNegRemT_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :673:{27,47,61}] wire [53:0] _isZeroRemT_E_T = remT_E2[53:0]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :675:21] wire _isZeroRemT_E_T_1 = _isZeroRemT_E_T == 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:675:{21,29}] wire _isZeroRemT_E_T_2 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :676:18] wire [1:0] _isZeroRemT_E_T_3 = remT_E2[55:54]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :676:41] wire _isZeroRemT_E_T_4 = _isZeroRemT_E_T_3 == 2'h0; // @[DivSqrtRecF64_mulAddZ31.scala:676:{41,50}] wire _isZeroRemT_E_T_5 = _isZeroRemT_E_T_2 | _isZeroRemT_E_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:676:{18,30,50}] wire _isZeroRemT_E_T_6 = _isZeroRemT_E_T_1 & _isZeroRemT_E_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:675:{29,38}, :676:30] wire _trueLtX_E1_T = ~isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :686:24] wire _trueLtX_E1_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41] wire _trueLtX_E1_T_2 = _trueLtX_E1_T & _trueLtX_E1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:686:{24,38,41}] wire trueLtX_E1 = sqrtOp_PC ? _trueLtX_E1_T_2 : isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :145:30, :686:{12,38}] wire [13:0] _sExpP1_PC_T = {sExp_PC[12], sExp_PC} + 14'h1; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :694:29] wire [12:0] _sExpP1_PC_T_1 = _sExpP1_PC_T[12:0]; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [12:0] sExpP1_PC = _sExpP1_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [54:0] _GEN_0 = {1'h0, sigT_E}; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :695:27] wire [54:0] sigTP1_E = _GEN_0 + 55'h1; // @[DivSqrtRecF64_mulAddZ31.scala:695:27] wire _io_rawOutValid_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :699:42] assign _io_rawOutValid_div_T_1 = leaving_PC & _io_rawOutValid_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :699:{39,42}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :699:39] assign _io_rawOutValid_sqrt_T = leaving_PC & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :155:26, :700:39] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :700:39] assign _io_invalidExc_T = majorExc_PC & isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :121:30, :702:40] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :702:40] wire _io_infiniteExc_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25, :703:43] assign _io_infiniteExc_T_1 = majorExc_PC & _io_infiniteExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :703:{40,43}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :703:40] wire _io_rawOut_sExp_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :709:13] wire _io_rawOut_sExp_T_1 = _io_rawOut_sExp_T & E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :709:{13,25}] wire [12:0] _io_rawOut_sExp_T_2 = _io_rawOut_sExp_T_1 ? sExp_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :709:{12,25}] wire _io_rawOut_sExp_T_3 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :710:13] wire _io_rawOut_sExp_T_4 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27, :710:28] wire _io_rawOut_sExp_T_5 = _io_rawOut_sExp_T_3 & _io_rawOut_sExp_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:710:{13,25,28}] wire [12:0] _io_rawOut_sExp_T_6 = _io_rawOut_sExp_T_5 ? sExpP1_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:694:29, :710:{12,25}] wire [12:0] _io_rawOut_sExp_T_7 = _io_rawOut_sExp_T_2 | _io_rawOut_sExp_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:709:{12,72}, :710:12] wire [12:0] _io_rawOut_sExp_T_8 = _io_rawOut_sExp_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:709:72] wire [11:0] _io_rawOut_sExp_T_9 = sExp_PC[12:1]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :711:47] wire [12:0] _io_rawOut_sExp_T_10 = {_io_rawOut_sExp_T_9[11], _io_rawOut_sExp_T_9} + 13'h400; // @[DivSqrtRecF64_mulAddZ31.scala:711:{47,52}] wire [12:0] _io_rawOut_sExp_T_11 = sqrtOp_PC ? _io_rawOut_sExp_T_10 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :711:{12,52}] wire [12:0] _io_rawOut_sExp_T_12 = _io_rawOut_sExp_T_8 | _io_rawOut_sExp_T_11; // @[DivSqrtRecF64_mulAddZ31.scala:709:72, :710:72, :711:12] assign _io_rawOut_sExp_T_13 = _io_rawOut_sExp_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :710:72] wire [54:0] _io_rawOut_sig_T = trueLtX_E1 ? _GEN_0 : sigTP1_E; // @[DivSqrtRecF64_mulAddZ31.scala:686:12, :695:27, :712:25] wire _io_rawOut_sig_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41, :712:59] assign _io_rawOut_sig_T_2 = {_io_rawOut_sig_T, _io_rawOut_sig_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:712:{25,56,59}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :712:56] wire _T_18 = entering_PA_normalCase_sqrt | cyc_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :225:35, :551:21] always @(posedge clock) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (reset) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] cycleNum_A <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] cycleNum_B <= 4'h0; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] cycleNum_C <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] cycleNum_E <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] valid_PA <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] valid_PB <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] valid_PC <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] end else begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (|{entering_PA_normalCase, cycleNum_A}) // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :213:36, :217:{34,49}] cycleNum_A <= _cycleNum_A_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :220:69] if (|{cyc_A1, cycleNum_B}) // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :234:30, :244:{18,33}] cycleNum_B <= _cycleNum_B_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :246:16] if (|{cyc_B1, cycleNum_C}) // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :262:30, :278:{18,33}] cycleNum_C <= _cycleNum_C_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:16] if (|{cyc_C1, cycleNum_E}) // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :289:30, :303:{18,33}] cycleNum_E <= _cycleNum_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:26] if (entering_PA | leaving_PA) // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :325:32, :327:23] valid_PA <= entering_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:32] if (entering_PB | leaving_PB) // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :364:37, :366:23] valid_PB <= entering_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :364:37] if (entering_PC | leaving_PC) // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :398:37, :400:23] valid_PC <= entering_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :398:37] end if (entering_PA) begin // @[DivSqrtRecF64_mulAddZ31.scala:325:32] sqrtOp_PA <= io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :92:30] majorExc_PA <= majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:93:30, :176:12] isNaN_PA <= isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :183:12] isInf_PA <= isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :187:23] isZero_PA <= isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :188:23] sign_PA <= sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:98:30, :189:47] end if (entering_PA_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:213:36] sExp_PA <= _sExp_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :339:23] fractB_PA <= _fractB_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :340:32] roundingMode_PA <= io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :102:30] end if (entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50] fractA_PA <= _fractA_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :344:32] if (entering_PB) begin // @[DivSqrtRecF64_mulAddZ31.scala:364:37] sqrtOp_PB <= _sqrtOp_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :370:27] majorExc_PB <= _majorExc_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:106:30, :371:27] isNaN_PB <= _isNaN_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :372:27] isInf_PB <= _isInf_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :373:27] isZero_PB <= _isZero_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :374:27] sign_PB <= _sign_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:111:30, :375:27] end if (entering_PB_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:363:35] sExp_PB <= sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :112:30] bit0FractA_PB <= _bit0FractA_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :379:37] fractB_PB <= fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :114:30] roundingMode_PB <= _roundingMode_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:115:30, :381:31] end if (entering_PC) begin // @[DivSqrtRecF64_mulAddZ31.scala:398:37] sqrtOp_PC <= _sqrtOp_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :404:27] majorExc_PC <= _majorExc_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :405:27] isNaN_PC <= _isNaN_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :406:27] isInf_PC <= _isInf_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :407:27] isZero_PC <= _isZero_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :408:27] sign_PC <= _sign_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:124:30, :409:27] end if (entering_PC_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:397:35] sExp_PC <= sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30, :125:30] bit0FractA_PC <= bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :126:30] fractB_PC <= fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30, :127:30] roundingMode_PC <= _roundingMode_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:128:30, :415:31] end if (cyc_A6_sqrt | entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :225:35, :541:23] fractR0_A <= _fractR0_A_T[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :542:{19,39}] if (cyc_A5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:226:35] hiSqrR0_A_sqrt <= _hiSqrR0_A_sqrt_T[9:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :545:{24,40}] if (cyc_A4_sqrt | cyc_A3) // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :232:30, :547:23] partNegSigma0_A <= _partNegSigma0_A_T_1[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :548:{25,31}] if (_T_18 | cyc_A5_sqrt | cyc_A4 | cyc_A3 | cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :232:30, :233:30, :551:{21,36,51,61,71}] nextMulAdd9A_A <= _nextMulAdd9A_A_T_13[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :553:24, :558:64] if (_T_18 | cyc_A5_sqrt | cyc_A4 | cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :233:30, :551:21, :561:{38,53,63}] nextMulAdd9B_A <= _nextMulAdd9B_A_T_12[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :562:24, :567:69] if (cyc_A1_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:242:30] ER1_B_sqrt <= ER1_A1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :539:26] if (cyc_B8_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:254:36] ESqrR1_B_sqrt <= ESqrR1_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :632:43] if (cyc_B3) // @[DivSqrtRecF64_mulAddZ31.scala:260:30] sigX1_B <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :158:34] if (cyc_B1) // @[DivSqrtRecF64_mulAddZ31.scala:262:30] sqrSigma1_C <= sqrSigma1_B1; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :634:41] if (cyc_C6_sqrt | cyc_C5_div | cyc_C3_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :291:29, :299:30, :661:{23,37}] sigXN_C <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :158:34] if (cyc_C5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:297:30] u_C_sqrt <= _u_C_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :665:33] if (cyc_C1) begin // @[DivSqrtRecF64_mulAddZ31.scala:289:30] E_E_div <= E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :636:20] sigT_E <= sigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :648:19] end if (cyc_E2) begin // @[DivSqrtRecF64_mulAddZ31.scala:309:30] isNegRemT_E <= _isNegRemT_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :673:27] isZeroRemT_E <= _isZeroRemT_E_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :675:38] end always @(posedge) assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchDecode_4 : input clock : Clock input reset : Reset output io : { flip inst : UInt<32>, flip pc : UInt<40>, out : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>}} wire bpd_csignals_decoded_plaInput : UInt<32> node bpd_csignals_decoded_invInputs = not(bpd_csignals_decoded_plaInput) wire bpd_csignals_decoded : UInt<5> node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5) node bpd_csignals_decoded_andMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1) node bpd_csignals_decoded_andMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo) node _bpd_csignals_decoded_andMatrixOutputs_T = cat(bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo) node bpd_csignals_decoded_andMatrixOutputs_5_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1) node bpd_csignals_decoded_andMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1) node bpd_csignals_decoded_andMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1) node _bpd_csignals_decoded_andMatrixOutputs_T_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1) node bpd_csignals_decoded_andMatrixOutputs_9_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2) node _bpd_csignals_decoded_andMatrixOutputs_T_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2) node bpd_csignals_decoded_andMatrixOutputs_14_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3) node _bpd_csignals_decoded_andMatrixOutputs_T_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3) node bpd_csignals_decoded_andMatrixOutputs_0_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4) node _bpd_csignals_decoded_andMatrixOutputs_T_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4) node bpd_csignals_decoded_andMatrixOutputs_2_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5) node bpd_csignals_decoded_andMatrixOutputs_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5) node bpd_csignals_decoded_andMatrixOutputs_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5) node _bpd_csignals_decoded_andMatrixOutputs_T_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5) node bpd_csignals_decoded_andMatrixOutputs_12_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6) node bpd_csignals_decoded_andMatrixOutputs_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6) node bpd_csignals_decoded_andMatrixOutputs_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6) node _bpd_csignals_decoded_andMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6) node bpd_csignals_decoded_andMatrixOutputs_6_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6) node bpd_csignals_decoded_andMatrixOutputs_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7) node bpd_csignals_decoded_andMatrixOutputs_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7) node _bpd_csignals_decoded_andMatrixOutputs_T_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7) node bpd_csignals_decoded_andMatrixOutputs_15_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_7) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8) node bpd_csignals_decoded_andMatrixOutputs_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8) node bpd_csignals_decoded_andMatrixOutputs_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8) node _bpd_csignals_decoded_andMatrixOutputs_T_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8) node bpd_csignals_decoded_andMatrixOutputs_11_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_8) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9) node _bpd_csignals_decoded_andMatrixOutputs_T_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9) node bpd_csignals_decoded_andMatrixOutputs_3_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_9) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10) node _bpd_csignals_decoded_andMatrixOutputs_T_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10) node bpd_csignals_decoded_andMatrixOutputs_7_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_10) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(bpd_csignals_decoded_plaInput, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11) node bpd_csignals_decoded_andMatrixOutputs_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11) node bpd_csignals_decoded_andMatrixOutputs_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11) node _bpd_csignals_decoded_andMatrixOutputs_T_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11) node bpd_csignals_decoded_andMatrixOutputs_1_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_11) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12) node bpd_csignals_decoded_andMatrixOutputs_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12) node bpd_csignals_decoded_andMatrixOutputs_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12) node _bpd_csignals_decoded_andMatrixOutputs_T_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12) node bpd_csignals_decoded_andMatrixOutputs_13_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13) node _bpd_csignals_decoded_andMatrixOutputs_T_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13) node bpd_csignals_decoded_andMatrixOutputs_4_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14) node _bpd_csignals_decoded_andMatrixOutputs_T_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14) node bpd_csignals_decoded_andMatrixOutputs_8_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15) node _bpd_csignals_decoded_andMatrixOutputs_T_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15) node bpd_csignals_decoded_andMatrixOutputs_10_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_15) node bpd_csignals_decoded_orMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2) node _bpd_csignals_decoded_orMatrixOutputs_T = cat(bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_1 = orr(_bpd_csignals_decoded_orMatrixOutputs_T) node bpd_csignals_decoded_orMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2) node bpd_csignals_decoded_orMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo) node bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2) node bpd_csignals_decoded_orMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2) node bpd_csignals_decoded_orMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1) node _bpd_csignals_decoded_orMatrixOutputs_T_3 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_2) node _bpd_csignals_decoded_orMatrixOutputs_T_4 = orr(bpd_csignals_decoded_andMatrixOutputs_15_2) node _bpd_csignals_decoded_orMatrixOutputs_T_5 = orr(bpd_csignals_decoded_andMatrixOutputs_11_2) node _bpd_csignals_decoded_orMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2) node _bpd_csignals_decoded_orMatrixOutputs_T_7 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_6) node bpd_csignals_decoded_orMatrixOutputs_lo_2 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5) node bpd_csignals_decoded_orMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4) node bpd_csignals_decoded_orMatrixOutputs = cat(bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2) node _bpd_csignals_decoded_invMatrixOutputs_T = bits(bpd_csignals_decoded_orMatrixOutputs, 0, 0) node _bpd_csignals_decoded_invMatrixOutputs_T_1 = bits(bpd_csignals_decoded_orMatrixOutputs, 1, 1) node _bpd_csignals_decoded_invMatrixOutputs_T_2 = bits(bpd_csignals_decoded_orMatrixOutputs, 2, 2) node _bpd_csignals_decoded_invMatrixOutputs_T_3 = bits(bpd_csignals_decoded_orMatrixOutputs, 3, 3) node _bpd_csignals_decoded_invMatrixOutputs_T_4 = bits(bpd_csignals_decoded_orMatrixOutputs, 4, 4) node bpd_csignals_decoded_invMatrixOutputs_lo = cat(_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T) node bpd_csignals_decoded_invMatrixOutputs_hi_hi = cat(_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3) node bpd_csignals_decoded_invMatrixOutputs_hi = cat(bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2) node bpd_csignals_decoded_invMatrixOutputs = cat(bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo) connect bpd_csignals_decoded, bpd_csignals_decoded_invMatrixOutputs connect bpd_csignals_decoded_plaInput, io.inst node bpd_csignals_0 = bits(bpd_csignals_decoded, 4, 4) node bpd_csignals_1 = bits(bpd_csignals_decoded, 3, 3) node bpd_csignals_2 = bits(bpd_csignals_decoded, 2, 2) node bpd_csignals_3 = bits(bpd_csignals_decoded, 1, 1) node bpd_csignals_4 = bits(bpd_csignals_decoded, 0, 0) node cs_is_br = bits(bpd_csignals_0, 0, 0) node cs_is_jal = bits(bpd_csignals_1, 0, 0) node cs_is_jalr = bits(bpd_csignals_2, 0, 0) node cs_is_shadowable = bits(bpd_csignals_3, 0, 0) node cs_has_rs2 = bits(bpd_csignals_4, 0, 0) node _io_out_is_call_T = or(cs_is_jal, cs_is_jalr) node _io_out_is_call_T_1 = bits(io.inst, 11, 7) node _io_out_is_call_T_2 = eq(_io_out_is_call_T_1, UInt<1>(0h1)) node _io_out_is_call_T_3 = and(_io_out_is_call_T, _io_out_is_call_T_2) connect io.out.is_call, _io_out_is_call_T_3 node _io_out_is_ret_T = bits(io.inst, 19, 15) node _io_out_is_ret_T_1 = and(_io_out_is_ret_T, UInt<5>(0h1b)) node _io_out_is_ret_T_2 = eq(UInt<1>(0h1), _io_out_is_ret_T_1) node _io_out_is_ret_T_3 = and(cs_is_jalr, _io_out_is_ret_T_2) node _io_out_is_ret_T_4 = bits(io.inst, 11, 7) node _io_out_is_ret_T_5 = eq(_io_out_is_ret_T_4, UInt<1>(0h0)) node _io_out_is_ret_T_6 = and(_io_out_is_ret_T_3, _io_out_is_ret_T_5) connect io.out.is_ret, _io_out_is_ret_T_6 node _io_out_target_b_imm32_T = bits(io.inst, 31, 31) node _io_out_target_b_imm32_T_1 = mux(_io_out_target_b_imm32_T, UInt<20>(0hfffff), UInt<20>(0h0)) node _io_out_target_b_imm32_T_2 = bits(io.inst, 7, 7) node _io_out_target_b_imm32_T_3 = bits(io.inst, 30, 25) node _io_out_target_b_imm32_T_4 = bits(io.inst, 11, 8) node io_out_target_b_imm32_lo = cat(_io_out_target_b_imm32_T_4, UInt<1>(0h0)) node io_out_target_b_imm32_hi_hi = cat(_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2) node io_out_target_b_imm32_hi = cat(io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3) node io_out_target_b_imm32 = cat(io_out_target_b_imm32_hi, io_out_target_b_imm32_lo) node _io_out_target_T = asSInt(io.pc) node _io_out_target_T_1 = asSInt(io_out_target_b_imm32) node _io_out_target_T_2 = add(_io_out_target_T, _io_out_target_T_1) node _io_out_target_T_3 = tail(_io_out_target_T_2, 1) node _io_out_target_T_4 = asSInt(_io_out_target_T_3) node _io_out_target_T_5 = and(_io_out_target_T_4, asSInt(UInt<2>(0h2))) node _io_out_target_T_6 = asSInt(_io_out_target_T_5) node _io_out_target_T_7 = asUInt(_io_out_target_T_6) node _io_out_target_j_imm32_T = bits(io.inst, 31, 31) node _io_out_target_j_imm32_T_1 = mux(_io_out_target_j_imm32_T, UInt<12>(0hfff), UInt<12>(0h0)) node _io_out_target_j_imm32_T_2 = bits(io.inst, 19, 12) node _io_out_target_j_imm32_T_3 = bits(io.inst, 20, 20) node _io_out_target_j_imm32_T_4 = bits(io.inst, 30, 25) node _io_out_target_j_imm32_T_5 = bits(io.inst, 24, 21) node io_out_target_j_imm32_lo_hi = cat(_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5) node io_out_target_j_imm32_lo = cat(io_out_target_j_imm32_lo_hi, UInt<1>(0h0)) node io_out_target_j_imm32_hi_hi = cat(_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2) node io_out_target_j_imm32_hi = cat(io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3) node io_out_target_j_imm32 = cat(io_out_target_j_imm32_hi, io_out_target_j_imm32_lo) node _io_out_target_T_8 = asSInt(io.pc) node _io_out_target_T_9 = asSInt(io_out_target_j_imm32) node _io_out_target_T_10 = add(_io_out_target_T_8, _io_out_target_T_9) node _io_out_target_T_11 = tail(_io_out_target_T_10, 1) node _io_out_target_T_12 = asSInt(_io_out_target_T_11) node _io_out_target_T_13 = and(_io_out_target_T_12, asSInt(UInt<2>(0h2))) node _io_out_target_T_14 = asSInt(_io_out_target_T_13) node _io_out_target_T_15 = asUInt(_io_out_target_T_14) node _io_out_target_T_16 = mux(cs_is_br, _io_out_target_T_7, _io_out_target_T_15) connect io.out.target, _io_out_target_T_16 node _io_out_cfi_type_T = mux(cs_is_br, UInt<3>(0h1), UInt<3>(0h0)) node _io_out_cfi_type_T_1 = mux(cs_is_jal, UInt<3>(0h2), _io_out_cfi_type_T) node _io_out_cfi_type_T_2 = mux(cs_is_jalr, UInt<3>(0h3), _io_out_cfi_type_T_1) connect io.out.cfi_type, _io_out_cfi_type_T_2 node _br_offset_T = bits(io.inst, 7, 7) node _br_offset_T_1 = bits(io.inst, 30, 25) node _br_offset_T_2 = bits(io.inst, 11, 8) node br_offset_lo = cat(_br_offset_T_2, UInt<1>(0h0)) node br_offset_hi = cat(_br_offset_T, _br_offset_T_1) node br_offset = cat(br_offset_hi, br_offset_lo) node _io_out_sfb_offset_valid_T = bits(io.inst, 31, 31) node _io_out_sfb_offset_valid_T_1 = eq(_io_out_sfb_offset_valid_T, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_2 = and(cs_is_br, _io_out_sfb_offset_valid_T_1) node _io_out_sfb_offset_valid_T_3 = neq(br_offset, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_4 = and(_io_out_sfb_offset_valid_T_2, _io_out_sfb_offset_valid_T_3) node _io_out_sfb_offset_valid_T_5 = shr(br_offset, 6) node _io_out_sfb_offset_valid_T_6 = eq(_io_out_sfb_offset_valid_T_5, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_7 = and(_io_out_sfb_offset_valid_T_4, _io_out_sfb_offset_valid_T_6) connect io.out.sfb_offset.valid, _io_out_sfb_offset_valid_T_7 connect io.out.sfb_offset.bits, br_offset node _io_out_shadowable_T = eq(cs_has_rs2, UInt<1>(0h0)) node _io_out_shadowable_T_1 = bits(io.inst, 19, 15) node _io_out_shadowable_T_2 = bits(io.inst, 11, 7) node _io_out_shadowable_T_3 = eq(_io_out_shadowable_T_1, _io_out_shadowable_T_2) node _io_out_shadowable_T_4 = or(_io_out_shadowable_T, _io_out_shadowable_T_3) node _io_out_shadowable_T_5 = and(io.inst, UInt<32>(0hfe00707f)) node _io_out_shadowable_T_6 = eq(UInt<6>(0h33), _io_out_shadowable_T_5) node _io_out_shadowable_T_7 = bits(io.inst, 19, 15) node _io_out_shadowable_T_8 = eq(_io_out_shadowable_T_7, UInt<1>(0h0)) node _io_out_shadowable_T_9 = and(_io_out_shadowable_T_6, _io_out_shadowable_T_8) node _io_out_shadowable_T_10 = or(_io_out_shadowable_T_4, _io_out_shadowable_T_9) node _io_out_shadowable_T_11 = and(cs_is_shadowable, _io_out_shadowable_T_10) connect io.out.shadowable, _io_out_shadowable_T_11
module BranchDecode_4( // @[decode.scala:629:7] input clock, // @[decode.scala:629:7] input reset, // @[decode.scala:629:7] input [31:0] io_inst, // @[decode.scala:631:14] input [39:0] io_pc, // @[decode.scala:631:14] output io_out_is_ret, // @[decode.scala:631:14] output io_out_is_call, // @[decode.scala:631:14] output [39:0] io_out_target, // @[decode.scala:631:14] output [2:0] io_out_cfi_type, // @[decode.scala:631:14] output io_out_sfb_offset_valid, // @[decode.scala:631:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:631:14] output io_out_shadowable // @[decode.scala:631:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:629:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:701:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:629:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:629:7] wire _io_out_is_call_T_3; // @[decode.scala:700:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:703:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:706:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:716:76] wire _io_out_shadowable_T_11; // @[decode.scala:718:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:629:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:629:7] wire io_out_is_ret_0; // @[decode.scala:629:7] wire io_out_is_call_0; // @[decode.scala:629:7] wire [39:0] io_out_target_0; // @[decode.scala:629:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:629:7] wire io_out_shadowable_0; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = |_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = |_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = |_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal | cs_is_jalr; // @[decode.scala:695:34, :696:35, :700:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:629:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:700:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:700:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:629:7, :700:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:701:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:701:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:696:35, :701:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:701:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:701:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:629:7, :701:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:629:7, :716:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:189:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:629:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:629:7, :714:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:629:7, :714:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:629:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:629:7, :714:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:189:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:189:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:189:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:189:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:189:22, :190:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:190:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:190:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:190:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:190:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:195:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:629:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:629:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:195:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:195:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:195:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:195:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:195:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:195:22, :196:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:196:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:196:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:196:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:196:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:694:33, :703:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:629:7, :703:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:694:33, :710:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:695:34, :708:8, :710:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:696:35, :706:8, :708:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:629:7, :706:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:714:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:714:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:714:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:716:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:694:33, :716:{39,42}] wire _io_out_sfb_offset_valid_T_3 = |br_offset; // @[decode.scala:714:22, :716:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:716:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:714:22, :716:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:716:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:716:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:629:7, :716:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:629:7, :714:22, :717:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:698:35, :719:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:720:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T | _io_out_shadowable_T_3; // @[decode.scala:719:{5,17}, :720:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:629:7, :721:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:721:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:701:90, :721:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:721:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 | _io_out_shadowable_T_9; // @[decode.scala:719:17, :720:42, :721:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:697:41, :718:41, :720:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:629:7, :718:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:629:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:629:7] assign io_out_target = io_out_target_0; // @[decode.scala:629:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:629:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:629:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:629:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:629:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_527 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_527( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ALUUnit_1 : input clock : Clock input reset : Reset output io : { flip kill : UInt<1>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, ftq_info : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[2], pred_data : UInt<1>, imm_data : UInt<64>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}} connect io.resp.bits.fflags.valid, UInt<1>(0h0) invalidate io.resp.bits.fflags.bits connect io.resp.bits.predicated, UInt<1>(0h0) connect io.req.ready, UInt<1>(0h1) node _block_pc_T = not(io.req.bits.ftq_info[0].pc) node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f)) node block_pc = not(_block_pc_T_1) node _uop_pc_T = or(block_pc, io.req.bits.uop.pc_lob) node _uop_pc_T_1 = mux(io.req.bits.uop.edge_inst, UInt<2>(0h2), UInt<1>(0h0)) node _uop_pc_T_2 = sub(_uop_pc_T, _uop_pc_T_1) node uop_pc = tail(_uop_pc_T_2, 1) node _op1_shamt_T = eq(io.req.bits.uop.fcn_op, UInt<1>(0h0)) node _op1_shamt_T_1 = bits(io.req.bits.uop.pimm, 2, 1) node op1_shamt = mux(_op1_shamt_T, _op1_shamt_T_1, UInt<1>(0h0)) node _op1_shl_T = eq(io.req.bits.uop.fcn_dw, UInt<1>(0h0)) node _op1_shl_T_1 = bits(io.req.bits.rs1_data, 31, 0) node _op1_shl_T_2 = mux(_op1_shl_T, _op1_shl_T_1, io.req.bits.rs1_data) node op1_shl = dshl(_op1_shl_T_2, op1_shamt) node _op1_data_T = bits(uop_pc, 39, 39) node _op1_data_T_1 = mux(_op1_data_T, UInt<24>(0hffffff), UInt<24>(0h0)) node _op1_data_T_2 = cat(_op1_data_T_1, uop_pc) node _op1_data_T_3 = eq(UInt<2>(0h0), io.req.bits.uop.op1_sel) node _op1_data_T_4 = mux(_op1_data_T_3, io.req.bits.rs1_data, UInt<1>(0h0)) node _op1_data_T_5 = eq(UInt<2>(0h2), io.req.bits.uop.op1_sel) node _op1_data_T_6 = mux(_op1_data_T_5, _op1_data_T_2, _op1_data_T_4) node _op1_data_T_7 = eq(UInt<2>(0h3), io.req.bits.uop.op1_sel) node op1_data = mux(_op1_data_T_7, op1_shl, _op1_data_T_6) node _op2_oh_T = bits(io.req.bits.uop.op2_sel, 0, 0) node _op2_oh_T_1 = mux(_op2_oh_T, io.req.bits.rs2_data, io.req.bits.imm_data) node _op2_oh_T_2 = bits(_op2_oh_T_1, 5, 0) node op2_oh = dshl(UInt<1>(0h1), _op2_oh_T_2) node _op2_data_T = bits(io.req.bits.uop.prs1, 4, 0) node _op2_data_T_1 = mux(io.req.bits.uop.is_rvc, UInt<2>(0h2), UInt<3>(0h4)) node _op2_data_T_2 = eq(UInt<3>(0h1), io.req.bits.uop.op2_sel) node _op2_data_T_3 = mux(_op2_data_T_2, io.req.bits.imm_data, UInt<1>(0h0)) node _op2_data_T_4 = eq(UInt<3>(0h4), io.req.bits.uop.op2_sel) node _op2_data_T_5 = mux(_op2_data_T_4, _op2_data_T, _op2_data_T_3) node _op2_data_T_6 = eq(UInt<3>(0h0), io.req.bits.uop.op2_sel) node _op2_data_T_7 = mux(_op2_data_T_6, io.req.bits.rs2_data, _op2_data_T_5) node _op2_data_T_8 = eq(UInt<3>(0h3), io.req.bits.uop.op2_sel) node _op2_data_T_9 = mux(_op2_data_T_8, _op2_data_T_1, _op2_data_T_7) node _op2_data_T_10 = eq(UInt<3>(0h5), io.req.bits.uop.op2_sel) node _op2_data_T_11 = mux(_op2_data_T_10, op2_oh, _op2_data_T_9) node _op2_data_T_12 = eq(UInt<3>(0h6), io.req.bits.uop.op2_sel) node op2_data = mux(_op2_data_T_12, op2_oh, _op2_data_T_11) inst alu of ALU_1 connect alu.clock, clock connect alu.reset, reset connect alu.io.in1, op1_data connect alu.io.in2, op2_data connect alu.io.fn, io.req.bits.uop.fcn_op node _alu_io_dw_T = eq(io.req.bits.uop.op1_sel, UInt<2>(0h3)) node _alu_io_dw_T_1 = mux(_alu_io_dw_T, UInt<1>(0h1), io.req.bits.uop.fcn_dw) connect alu.io.dw, _alu_io_dw_T_1 node br_eq = eq(io.req.bits.rs1_data, io.req.bits.rs2_data) node br_ltu = lt(io.req.bits.rs1_data, io.req.bits.rs2_data) node _br_lt_T = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_1 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_2 = xor(_br_lt_T, _br_lt_T_1) node _br_lt_T_3 = not(_br_lt_T_2) node _br_lt_T_4 = and(_br_lt_T_3, br_ltu) node _br_lt_T_5 = bits(io.req.bits.rs1_data, 63, 63) node _br_lt_T_6 = bits(io.req.bits.rs2_data, 63, 63) node _br_lt_T_7 = not(_br_lt_T_6) node _br_lt_T_8 = and(_br_lt_T_5, _br_lt_T_7) node br_lt = or(_br_lt_T_4, _br_lt_T_8) node _pc_sel_T = eq(br_eq, UInt<1>(0h0)) node _pc_sel_T_1 = mux(_pc_sel_T, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_2 = mux(br_eq, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_3 = eq(br_lt, UInt<1>(0h0)) node _pc_sel_T_4 = mux(_pc_sel_T_3, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_5 = eq(br_ltu, UInt<1>(0h0)) node _pc_sel_T_6 = mux(_pc_sel_T_5, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_7 = mux(br_lt, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_8 = mux(br_ltu, UInt<2>(0h1), UInt<2>(0h0)) node _pc_sel_T_9 = eq(UInt<4>(0h0), io.req.bits.uop.br_type) node _pc_sel_T_10 = mux(_pc_sel_T_9, UInt<2>(0h0), UInt<2>(0h0)) node _pc_sel_T_11 = eq(UInt<4>(0h1), io.req.bits.uop.br_type) node _pc_sel_T_12 = mux(_pc_sel_T_11, _pc_sel_T_1, _pc_sel_T_10) node _pc_sel_T_13 = eq(UInt<4>(0h2), io.req.bits.uop.br_type) node _pc_sel_T_14 = mux(_pc_sel_T_13, _pc_sel_T_2, _pc_sel_T_12) node _pc_sel_T_15 = eq(UInt<4>(0h3), io.req.bits.uop.br_type) node _pc_sel_T_16 = mux(_pc_sel_T_15, _pc_sel_T_4, _pc_sel_T_14) node _pc_sel_T_17 = eq(UInt<4>(0h4), io.req.bits.uop.br_type) node _pc_sel_T_18 = mux(_pc_sel_T_17, _pc_sel_T_6, _pc_sel_T_16) node _pc_sel_T_19 = eq(UInt<4>(0h5), io.req.bits.uop.br_type) node _pc_sel_T_20 = mux(_pc_sel_T_19, _pc_sel_T_7, _pc_sel_T_18) node _pc_sel_T_21 = eq(UInt<4>(0h6), io.req.bits.uop.br_type) node _pc_sel_T_22 = mux(_pc_sel_T_21, _pc_sel_T_8, _pc_sel_T_20) node _pc_sel_T_23 = eq(UInt<4>(0h7), io.req.bits.uop.br_type) node _pc_sel_T_24 = mux(_pc_sel_T_23, UInt<2>(0h1), _pc_sel_T_22) node _pc_sel_T_25 = eq(UInt<4>(0h8), io.req.bits.uop.br_type) node pc_sel = mux(_pc_sel_T_25, UInt<2>(0h2), _pc_sel_T_24) node _is_taken_T = neq(io.req.bits.uop.br_type, UInt<3>(0h3)) node _is_taken_T_1 = and(io.req.valid, _is_taken_T) node _is_taken_T_2 = neq(pc_sel, UInt<2>(0h0)) node is_taken = and(_is_taken_T_1, _is_taken_T_2) node _target_offset_T = bits(io.req.bits.imm_data, 20, 0) node target_offset = asSInt(_target_offset_T) wire mispredict : UInt<1> connect mispredict, UInt<1>(0h0) node _is_br_T = eq(io.req.bits.uop.br_type, UInt<4>(0h1)) node _is_br_T_1 = eq(io.req.bits.uop.br_type, UInt<4>(0h2)) node _is_br_T_2 = eq(io.req.bits.uop.br_type, UInt<4>(0h3)) node _is_br_T_3 = eq(io.req.bits.uop.br_type, UInt<4>(0h4)) node _is_br_T_4 = eq(io.req.bits.uop.br_type, UInt<4>(0h5)) node _is_br_T_5 = eq(io.req.bits.uop.br_type, UInt<4>(0h6)) node _is_br_T_6 = or(_is_br_T, _is_br_T_1) node _is_br_T_7 = or(_is_br_T_6, _is_br_T_2) node _is_br_T_8 = or(_is_br_T_7, _is_br_T_3) node _is_br_T_9 = or(_is_br_T_8, _is_br_T_4) node _is_br_T_10 = or(_is_br_T_9, _is_br_T_5) node _is_br_T_11 = and(io.req.valid, _is_br_T_10) node _is_br_T_12 = eq(io.req.bits.uop.is_sfb, UInt<1>(0h0)) node is_br = and(_is_br_T_11, _is_br_T_12) node _is_jal_T = eq(io.req.bits.uop.br_type, UInt<4>(0h7)) node is_jal = and(io.req.valid, _is_jal_T) node _is_jalr_T = eq(io.req.bits.uop.br_type, UInt<4>(0h8)) node is_jalr = and(io.req.valid, _is_jalr_T) node jalr_target_base = asSInt(io.req.bits.rs1_data) wire jalr_target_xlen : UInt<64> node _jalr_target_xlen_T = add(jalr_target_base, target_offset) node _jalr_target_xlen_T_1 = tail(_jalr_target_xlen_T, 1) node _jalr_target_xlen_T_2 = asSInt(_jalr_target_xlen_T_1) node _jalr_target_xlen_T_3 = asUInt(_jalr_target_xlen_T_2) connect jalr_target_xlen, _jalr_target_xlen_T_3 node _jalr_target_a_T = asSInt(jalr_target_xlen) node jalr_target_a = shr(_jalr_target_a_T, 39) node _jalr_target_msb_T = eq(jalr_target_a, asSInt(UInt<1>(0h0))) node _jalr_target_msb_T_1 = eq(jalr_target_a, asSInt(UInt<1>(0h1))) node _jalr_target_msb_T_2 = or(_jalr_target_msb_T, _jalr_target_msb_T_1) node _jalr_target_msb_T_3 = bits(jalr_target_xlen, 39, 39) node _jalr_target_msb_T_4 = bits(jalr_target_xlen, 38, 38) node _jalr_target_msb_T_5 = eq(_jalr_target_msb_T_4, UInt<1>(0h0)) node jalr_target_msb = mux(_jalr_target_msb_T_2, _jalr_target_msb_T_3, _jalr_target_msb_T_5) node _jalr_target_T = bits(jalr_target_xlen, 38, 0) node _jalr_target_T_1 = cat(jalr_target_msb, _jalr_target_T) node _jalr_target_T_2 = asSInt(_jalr_target_T_1) node _jalr_target_T_3 = and(_jalr_target_T_2, asSInt(UInt<2>(0h2))) node _jalr_target_T_4 = asSInt(_jalr_target_T_3) node jalr_target = asUInt(_jalr_target_T_4) node _cfi_idx_T = eq(io.req.bits.ftq_info[0].entry.start_bank, UInt<1>(0h1)) node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3) node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0)) node _cfi_idx_T_3 = xor(io.req.bits.uop.pc_lob, _cfi_idx_T_2) node cfi_idx = bits(_cfi_idx_T_3, 3, 1) node _T = or(is_br, is_jalr) when _T : node _T_1 = eq(pc_sel, UInt<2>(0h0)) when _T_1 : connect mispredict, io.req.bits.uop.taken node _T_2 = eq(pc_sel, UInt<2>(0h1)) when _T_2 : node _mispredict_T = eq(io.req.bits.uop.taken, UInt<1>(0h0)) connect mispredict, _mispredict_T node _T_3 = eq(pc_sel, UInt<2>(0h2)) when _T_3 : node _mispredict_T_1 = eq(io.req.bits.ftq_info[1].valid, UInt<1>(0h0)) node _mispredict_T_2 = neq(io.req.bits.ftq_info[1].pc, jalr_target) node _mispredict_T_3 = or(_mispredict_T_1, _mispredict_T_2) node _mispredict_T_4 = eq(io.req.bits.ftq_info[0].entry.cfi_idx.valid, UInt<1>(0h0)) node _mispredict_T_5 = or(_mispredict_T_3, _mispredict_T_4) node _mispredict_T_6 = neq(io.req.bits.ftq_info[0].entry.cfi_idx.bits, cfi_idx) node _mispredict_T_7 = or(_mispredict_T_5, _mispredict_T_6) connect mispredict, _mispredict_T_7 wire brinfo : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}} node _brinfo_valid_T = or(is_br, is_jalr) connect brinfo.valid, _brinfo_valid_T connect brinfo.bits.mispredict, mispredict connect brinfo.bits.uop, io.req.bits.uop node _brinfo_bits_cfi_type_T = mux(is_br, UInt<3>(0h1), UInt<3>(0h0)) node _brinfo_bits_cfi_type_T_1 = mux(is_jalr, UInt<3>(0h3), _brinfo_bits_cfi_type_T) connect brinfo.bits.cfi_type, _brinfo_bits_cfi_type_T_1 connect brinfo.bits.taken, is_taken connect brinfo.bits.pc_sel, pc_sel invalidate brinfo.bits.jalr_target connect brinfo.bits.jalr_target, jalr_target connect brinfo.bits.target_offset, target_offset connect io.brinfo, brinfo node _alu_out_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _alu_out_T_1 = and(_alu_out_T, io.req.bits.uop.is_sfb) node _alu_out_T_2 = and(_alu_out_T_1, UInt<1>(0h1)) node _alu_out_T_3 = and(_alu_out_T_2, io.req.bits.pred_data) node _alu_out_T_4 = mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data) node _alu_out_T_5 = mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out) node alu_out = mux(_alu_out_T_3, _alu_out_T_4, _alu_out_T_5) connect io.resp.valid, io.req.valid connect io.resp.bits.uop, io.req.bits.uop node _io_resp_bits_data_T = neq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_data_T_1 = and(_io_resp_bits_data_T, io.req.bits.uop.is_sfb) node _io_resp_bits_data_T_2 = and(_io_resp_bits_data_T_1, UInt<1>(0h1)) node _io_resp_bits_data_T_3 = eq(pc_sel, UInt<2>(0h1)) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_2, _io_resp_bits_data_T_3, alu_out) connect io.resp.bits.data, _io_resp_bits_data_T_4 node _io_resp_bits_predicated_T = eq(io.req.bits.uop.br_type, UInt<4>(0h0)) node _io_resp_bits_predicated_T_1 = and(_io_resp_bits_predicated_T, io.req.bits.uop.is_sfb) node _io_resp_bits_predicated_T_2 = and(_io_resp_bits_predicated_T_1, UInt<1>(0h1)) node _io_resp_bits_predicated_T_3 = and(_io_resp_bits_predicated_T_2, io.req.bits.pred_data) connect io.resp.bits.predicated, _io_resp_bits_predicated_T_3 node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(io.resp.ready, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at functional-unit.scala:292 assert(io.resp.ready)\n") : printf assert(clock, io.resp.ready, UInt<1>(0h1), "") : assert
module ALUUnit_1( // @[functional-unit.scala:133:7] input clock, // @[functional-unit.scala:133:7] input reset, // @[functional-unit.scala:133:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_valid, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_idx_valid, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_taken, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_mispredicted, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_ftq_info_0_entry_cfi_type, // @[functional-unit.scala:105:14] input [7:0] io_req_bits_ftq_info_0_entry_br_mask, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_is_call, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_is_ret, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_cfi_npc_plus4, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_ftq_info_0_entry_ras_top, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_ftq_info_0_entry_ras_idx, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_0_entry_start_bank, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_ftq_info_0_pc, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_valid, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_idx_valid, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_taken, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_mispredicted, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_ftq_info_1_entry_cfi_type, // @[functional-unit.scala:105:14] input [7:0] io_req_bits_ftq_info_1_entry_br_mask, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_is_call, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_is_ret, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_cfi_npc_plus4, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_ftq_info_1_entry_ras_top, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_ftq_info_1_entry_ras_idx, // @[functional-unit.scala:105:14] input io_req_bits_ftq_info_1_entry_start_bank, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_ftq_info_1_pc, // @[functional-unit.scala:105:14] input io_req_bits_pred_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] output io_resp_bits_predicated, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:105:14] output io_brinfo_valid, // @[functional-unit.scala:105:14] output [31:0] io_brinfo_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_brinfo_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_brinfo_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [15:0] io_brinfo_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_brinfo_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_brinfo_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_brinfo_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_taken, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_brinfo_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_brinfo_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_brinfo_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_brinfo_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_brinfo_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_brinfo_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_brinfo_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_brinfo_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_brinfo_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output io_brinfo_bits_mispredict, // @[functional-unit.scala:105:14] output io_brinfo_bits_taken, // @[functional-unit.scala:105:14] output [2:0] io_brinfo_bits_cfi_type, // @[functional-unit.scala:105:14] output [1:0] io_brinfo_bits_pc_sel, // @[functional-unit.scala:105:14] output [39:0] io_brinfo_bits_jalr_target, // @[functional-unit.scala:105:14] output [20:0] io_brinfo_bits_target_offset // @[functional-unit.scala:105:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:173:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:133:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:133:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:133:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:133:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_valid_0 = io_req_bits_ftq_info_0_valid; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid_0 = io_req_bits_ftq_info_0_entry_cfi_idx_valid; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits_0 = io_req_bits_ftq_info_0_entry_cfi_idx_bits; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_taken_0 = io_req_bits_ftq_info_0_entry_cfi_taken; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted_0 = io_req_bits_ftq_info_0_entry_cfi_mispredicted; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type_0 = io_req_bits_ftq_info_0_entry_cfi_type; // @[functional-unit.scala:133:7] wire [7:0] io_req_bits_ftq_info_0_entry_br_mask_0 = io_req_bits_ftq_info_0_entry_br_mask; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call_0 = io_req_bits_ftq_info_0_entry_cfi_is_call; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret_0 = io_req_bits_ftq_info_0_entry_cfi_is_ret; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4_0 = io_req_bits_ftq_info_0_entry_cfi_npc_plus4; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top_0 = io_req_bits_ftq_info_0_entry_ras_top; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx_0 = io_req_bits_ftq_info_0_entry_ras_idx; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_entry_start_bank_0 = io_req_bits_ftq_info_0_entry_start_bank; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_0_pc_0 = io_req_bits_ftq_info_0_pc; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_valid_0 = io_req_bits_ftq_info_1_valid; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid_0 = io_req_bits_ftq_info_1_entry_cfi_idx_valid; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits_0 = io_req_bits_ftq_info_1_entry_cfi_idx_bits; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_taken_0 = io_req_bits_ftq_info_1_entry_cfi_taken; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted_0 = io_req_bits_ftq_info_1_entry_cfi_mispredicted; // @[functional-unit.scala:133:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type_0 = io_req_bits_ftq_info_1_entry_cfi_type; // @[functional-unit.scala:133:7] wire [7:0] io_req_bits_ftq_info_1_entry_br_mask_0 = io_req_bits_ftq_info_1_entry_br_mask; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call_0 = io_req_bits_ftq_info_1_entry_cfi_is_call; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret_0 = io_req_bits_ftq_info_1_entry_cfi_is_ret; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4_0 = io_req_bits_ftq_info_1_entry_cfi_npc_plus4; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top_0 = io_req_bits_ftq_info_1_entry_ras_top; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx_0 = io_req_bits_ftq_info_1_entry_ras_idx; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_entry_start_bank_0 = io_req_bits_ftq_info_1_entry_start_bank; // @[functional-unit.scala:133:7] wire [39:0] io_req_bits_ftq_info_1_pc_0 = io_req_bits_ftq_info_1_pc; // @[functional-unit.scala:133:7] wire io_req_bits_pred_data_0 = io_req_bits_pred_data; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:133:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:133:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:133:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:133:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:133:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:133:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:133:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:133:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:133:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:133:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:133:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:133:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:133:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:133:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:133:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:133:7] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:188:48] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[functional-unit.scala:234:90] wire io_req_ready = 1'h1; // @[functional-unit.scala:133:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:133:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:133:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:133:7] wire io_resp_valid_0 = io_req_valid_0; // @[functional-unit.scala:133:7] wire [31:0] io_resp_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [31:0] io_resp_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire [31:0] brinfo_bits_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7, :252:20] wire [39:0] io_resp_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire [39:0] brinfo_bits_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued = io_req_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [15:0] io_resp_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [15:0] brinfo_bits_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:133:7, :252:20] wire [3:0] io_resp_bits_uop_br_type_0 = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire [3:0] brinfo_bits_uop_br_type = io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sfence = io_req_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_eret_0 = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_eret = io_req_bits_uop_is_eret_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_rocc = io_req_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_mov_0 = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_mov = io_req_bits_uop_is_mov_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_imm_rename = io_req_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_imm_sel = io_req_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_pimm_0 = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_pimm = io_req_bits_uop_pimm_0; // @[functional-unit.scala:133:7, :252:20] wire [19:0] io_resp_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [19:0] brinfo_bits_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_op1_sel = io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_op2_sel = io_req_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7, :252:20] wire [6:0] io_resp_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] brinfo_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] io_resp_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [63:0] brinfo_bits_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:133:7, :252:20] wire [5:0] io_resp_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [5:0] brinfo_bits_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :252:20] wire [4:0] io_resp_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire [4:0] brinfo_bits_uop_fcn_op = io_req_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_fp_rm = io_req_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7, :252:20] wire [1:0] io_resp_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire [1:0] brinfo_bits_uop_fp_typ = io_req_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7, :252:20] wire io_resp_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire brinfo_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [2:0] io_resp_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire [2:0] brinfo_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7, :252:20] wire [63:0] jalr_target_base = io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :229:47] wire _cfi_idx_T = io_req_bits_ftq_info_0_entry_start_bank_0; // @[functional-unit.scala:133:7, :234:77] wire [63:0] _io_resp_bits_data_T_4; // @[functional-unit.scala:290:27] wire _io_resp_bits_predicated_T_3; // @[functional-unit.scala:291:60] wire brinfo_valid; // @[functional-unit.scala:252:20] wire brinfo_bits_mispredict; // @[functional-unit.scala:252:20] wire brinfo_bits_taken; // @[functional-unit.scala:252:20] wire [2:0] brinfo_bits_cfi_type; // @[functional-unit.scala:252:20] wire [1:0] brinfo_bits_pc_sel; // @[functional-unit.scala:252:20] wire [39:0] brinfo_bits_jalr_target; // @[functional-unit.scala:252:20] wire [20:0] brinfo_bits_target_offset; // @[functional-unit.scala:252:20] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:133:7] wire io_resp_bits_predicated_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_inst_0; // @[functional-unit.scala:133:7] wire [31:0] io_brinfo_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] wire [15:0] io_brinfo_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] wire [3:0] io_brinfo_bits_uop_br_type_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_taken_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_pimm_0; // @[functional-unit.scala:133:7] wire [19:0] io_brinfo_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_pdst_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs1_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs2_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_prs3_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_ppred_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] wire [6:0] io_brinfo_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_exception_0; // @[functional-unit.scala:133:7] wire [63:0] io_brinfo_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_ldst_0; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] wire [5:0] io_brinfo_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] wire [4:0] io_brinfo_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_mispredict_0; // @[functional-unit.scala:133:7] wire io_brinfo_bits_taken_0; // @[functional-unit.scala:133:7] wire [2:0] io_brinfo_bits_cfi_type_0; // @[functional-unit.scala:133:7] wire [1:0] io_brinfo_bits_pc_sel_0; // @[functional-unit.scala:133:7] wire [39:0] io_brinfo_bits_jalr_target_0; // @[functional-unit.scala:133:7] wire [20:0] io_brinfo_bits_target_offset_0; // @[functional-unit.scala:133:7] wire io_brinfo_valid_0; // @[functional-unit.scala:133:7] wire [39:0] _block_pc_T = ~io_req_bits_ftq_info_0_pc_0; // @[util.scala:245:7] wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:245:{7,11}] wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:245:{5,11}] wire [39:0] _uop_pc_T = {block_pc[39:6], block_pc[5:0] | io_req_bits_uop_pc_lob_0}; // @[util.scala:245:5] wire [1:0] _uop_pc_T_1 = {io_req_bits_uop_edge_inst_0, 1'h0}; // @[functional-unit.scala:133:7, :150:45] wire [40:0] _uop_pc_T_2 = {1'h0, _uop_pc_T} - {39'h0, _uop_pc_T_1}; // @[functional-unit.scala:150:{26,40,45}] wire [39:0] uop_pc = _uop_pc_T_2[39:0]; // @[functional-unit.scala:150:40] wire _op1_shamt_T = io_req_bits_uop_fcn_op_0 == 5'h0; // @[functional-unit.scala:133:7, :151:34] wire [1:0] _op1_shamt_T_1 = io_req_bits_uop_pimm_0[2:1]; // @[functional-unit.scala:133:7, :151:66] wire [1:0] op1_shamt = _op1_shamt_T ? _op1_shamt_T_1 : 2'h0; // @[functional-unit.scala:151:{22,34,66}] wire _op1_shl_T = ~io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :152:32] wire [31:0] _op1_shl_T_1 = io_req_bits_rs1_data_0[31:0]; // @[functional-unit.scala:133:7, :153:25] wire [63:0] _op1_shl_T_2 = _op1_shl_T ? {32'h0, _op1_shl_T_1} : io_req_bits_rs1_data_0; // @[functional-unit.scala:133:7, :152:{20,32}, :153:25] wire [66:0] op1_shl = {3'h0, _op1_shl_T_2} << op1_shamt; // @[functional-unit.scala:151:22, :152:20, :153:55] wire _op1_data_T = uop_pc[39]; // @[util.scala:269:46] wire [23:0] _op1_data_T_1 = {24{_op1_data_T}}; // @[util.scala:269:{25,46}] wire [63:0] _op1_data_T_2 = {_op1_data_T_1, uop_pc}; // @[util.scala:269:{20,25}] wire _op1_data_T_3 = io_req_bits_uop_op1_sel_0 == 2'h0; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_4 = _op1_data_T_3 ? io_req_bits_rs1_data_0 : 64'h0; // @[functional-unit.scala:133:7, :155:45] wire _op1_data_T_5 = io_req_bits_uop_op1_sel_0 == 2'h2; // @[functional-unit.scala:133:7, :155:45] wire [63:0] _op1_data_T_6 = _op1_data_T_5 ? _op1_data_T_2 : _op1_data_T_4; // @[util.scala:269:20] wire _op1_data_T_7 = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45] wire [66:0] op1_data = _op1_data_T_7 ? op1_shl : {3'h0, _op1_data_T_6}; // @[functional-unit.scala:153:55, :155:45] wire _op2_oh_T = io_req_bits_uop_op2_sel_0[0]; // @[functional-unit.scala:133:7, :162:40] wire [63:0] _op2_oh_T_1 = _op2_oh_T ? io_req_bits_rs2_data_0 : io_req_bits_imm_data_0; // @[functional-unit.scala:133:7, :162:{28,40}] wire [5:0] _op2_oh_T_2 = _op2_oh_T_1[5:0]; // @[functional-unit.scala:162:28, :163:38] wire [63:0] op2_oh = 64'h1 << _op2_oh_T_2; // @[OneHot.scala:58:35] wire [4:0] _op2_data_T = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:133:7, :166:37] wire [2:0] _op2_data_T_1 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:133:7, :168:20] wire _op2_data_T_2 = io_req_bits_uop_op2_sel_0 == 3'h1; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_3 = _op2_data_T_2 ? io_req_bits_imm_data_0 : 64'h0; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_4 = io_req_bits_uop_op2_sel_0 == 3'h4; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_5 = _op2_data_T_4 ? {59'h0, _op2_data_T} : _op2_data_T_3; // @[functional-unit.scala:164:45, :166:37] wire _op2_data_T_6 = io_req_bits_uop_op2_sel_0 == 3'h0; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_7 = _op2_data_T_6 ? io_req_bits_rs2_data_0 : _op2_data_T_5; // @[functional-unit.scala:133:7, :164:45] wire _op2_data_T_8 = io_req_bits_uop_op2_sel_0 == 3'h3; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_9 = _op2_data_T_8 ? {61'h0, _op2_data_T_1} : _op2_data_T_7; // @[functional-unit.scala:164:45, :168:20] wire _op2_data_T_10 = io_req_bits_uop_op2_sel_0 == 3'h5; // @[functional-unit.scala:133:7, :164:45] wire [63:0] _op2_data_T_11 = _op2_data_T_10 ? op2_oh : _op2_data_T_9; // @[OneHot.scala:58:35] wire _op2_data_T_12 = io_req_bits_uop_op2_sel_0 == 3'h6; // @[functional-unit.scala:133:7, :164:45] wire [63:0] op2_data = _op2_data_T_12 ? op2_oh : _op2_data_T_11; // @[OneHot.scala:58:35] wire _alu_io_dw_T = &io_req_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7, :155:45, :178:33] wire _alu_io_dw_T_1 = _alu_io_dw_T | io_req_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7, :178:{20,33}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :183:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :184:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:133:7, :185:22, :186:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:133:7, :185:36, :186:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:185:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:185:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:184:28, :185:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:186:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:186:{20,29,31}] wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:185:{46,55}, :186:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:183:21, :190:38] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:190:{37,38}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:183:21, :191:37] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:185:55, :192:38] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:192:{37,38}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:184:28, :193:38] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:193:{37,38}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:185:55, :194:37] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:184:28, :195:37] wire _pc_sel_T_9 = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _GEN = io_req_bits_uop_br_type_0 == 4'h1; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_11; // @[functional-unit.scala:188:48] assign _pc_sel_T_11 = _GEN; // @[functional-unit.scala:188:48] wire _is_br_T; // @[package.scala:16:47] assign _is_br_T = _GEN; // @[package.scala:16:47] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:188:48, :190:37] wire _GEN_0 = io_req_bits_uop_br_type_0 == 4'h2; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_13; // @[functional-unit.scala:188:48] assign _pc_sel_T_13 = _GEN_0; // @[functional-unit.scala:188:48] wire _is_br_T_1; // @[package.scala:16:47] assign _is_br_T_1 = _GEN_0; // @[package.scala:16:47] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:188:48, :191:37] wire _GEN_1 = io_req_bits_uop_br_type_0 == 4'h3; // @[functional-unit.scala:133:7, :188:48, :201:33] wire _pc_sel_T_15; // @[functional-unit.scala:188:48] assign _pc_sel_T_15 = _GEN_1; // @[functional-unit.scala:188:48] wire _is_br_T_2; // @[package.scala:16:47] assign _is_br_T_2 = _GEN_1; // @[package.scala:16:47] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:188:48, :192:37] wire _GEN_2 = io_req_bits_uop_br_type_0 == 4'h4; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_17; // @[functional-unit.scala:188:48] assign _pc_sel_T_17 = _GEN_2; // @[functional-unit.scala:188:48] wire _is_br_T_3; // @[package.scala:16:47] assign _is_br_T_3 = _GEN_2; // @[package.scala:16:47] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:188:48, :193:37] wire _GEN_3 = io_req_bits_uop_br_type_0 == 4'h5; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_19; // @[functional-unit.scala:188:48] assign _pc_sel_T_19 = _GEN_3; // @[functional-unit.scala:188:48] wire _is_br_T_4; // @[package.scala:16:47] assign _is_br_T_4 = _GEN_3; // @[package.scala:16:47] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:188:48, :194:37] wire _GEN_4 = io_req_bits_uop_br_type_0 == 4'h6; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_21; // @[functional-unit.scala:188:48] assign _pc_sel_T_21 = _GEN_4; // @[functional-unit.scala:188:48] wire _is_br_T_5; // @[package.scala:16:47] assign _is_br_T_5 = _GEN_4; // @[package.scala:16:47] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:188:48, :195:37] wire _GEN_5 = io_req_bits_uop_br_type_0 == 4'h7; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_23; // @[functional-unit.scala:188:48] assign _pc_sel_T_23 = _GEN_5; // @[functional-unit.scala:188:48] wire _is_jal_T; // @[micro-op.scala:118:34] assign _is_jal_T = _GEN_5; // @[functional-unit.scala:188:48] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:188:48] wire _GEN_6 = io_req_bits_uop_br_type_0 == 4'h8; // @[functional-unit.scala:133:7, :188:48] wire _pc_sel_T_25; // @[functional-unit.scala:188:48] assign _pc_sel_T_25 = _GEN_6; // @[functional-unit.scala:188:48] wire _is_jalr_T; // @[micro-op.scala:119:34] assign _is_jalr_T = _GEN_6; // @[functional-unit.scala:188:48] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:188:48] assign brinfo_bits_pc_sel = pc_sel; // @[functional-unit.scala:188:48, :252:20] wire _is_taken_T = io_req_bits_uop_br_type_0 != 4'h3; // @[functional-unit.scala:133:7, :201:33] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:133:7, :200:31, :201:33] wire _is_taken_T_2 = |pc_sel; // @[functional-unit.scala:188:48, :202:28] wire is_taken = _is_taken_T_1 & _is_taken_T_2; // @[functional-unit.scala:200:31, :201:43, :202:28] assign brinfo_bits_taken = is_taken; // @[functional-unit.scala:201:43, :252:20] wire [20:0] _target_offset_T = io_req_bits_imm_data_0[20:0]; // @[functional-unit.scala:133:7, :208:33] wire [20:0] target_offset = _target_offset_T; // @[functional-unit.scala:208:{33,40}] assign brinfo_bits_target_offset = target_offset; // @[functional-unit.scala:208:40, :252:20] wire mispredict; // @[functional-unit.scala:223:28] assign brinfo_bits_mispredict = mispredict; // @[functional-unit.scala:223:28, :252:20] wire _is_br_T_6 = _is_br_T | _is_br_T_1; // @[package.scala:16:47, :81:59] wire _is_br_T_7 = _is_br_T_6 | _is_br_T_2; // @[package.scala:16:47, :81:59] wire _is_br_T_8 = _is_br_T_7 | _is_br_T_3; // @[package.scala:16:47, :81:59] wire _is_br_T_9 = _is_br_T_8 | _is_br_T_4; // @[package.scala:16:47, :81:59] wire _is_br_T_10 = _is_br_T_9 | _is_br_T_5; // @[package.scala:16:47, :81:59] wire _is_br_T_11 = io_req_valid_0 & _is_br_T_10; // @[package.scala:81:59] wire _is_br_T_12 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7, :225:53] wire is_br = _is_br_T_11 & _is_br_T_12; // @[functional-unit.scala:225:{37,50,53}] wire is_jal = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:133:7, :226:37] wire is_jalr = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:133:7, :227:37] wire [63:0] _jalr_target_xlen_T_3; // @[functional-unit.scala:231:58] wire [63:0] jalr_target_xlen; // @[functional-unit.scala:230:30] wire [63:0] _jalr_target_a_T = jalr_target_xlen; // @[functional-unit.scala:215:16, :230:30] wire [64:0] _jalr_target_xlen_T = {jalr_target_base[63], jalr_target_base} + {{44{target_offset[20]}}, target_offset}; // @[functional-unit.scala:208:40, :229:47, :231:41] wire [63:0] _jalr_target_xlen_T_1 = _jalr_target_xlen_T[63:0]; // @[functional-unit.scala:231:41] wire [63:0] _jalr_target_xlen_T_2 = _jalr_target_xlen_T_1; // @[functional-unit.scala:231:41] assign _jalr_target_xlen_T_3 = _jalr_target_xlen_T_2; // @[functional-unit.scala:231:{41,58}] assign jalr_target_xlen = _jalr_target_xlen_T_3; // @[functional-unit.scala:230:30, :231:58] wire [24:0] jalr_target_a = _jalr_target_a_T[63:39]; // @[functional-unit.scala:215:{16,23}] wire _jalr_target_msb_T = jalr_target_a == 25'h0; // @[functional-unit.scala:215:23, :216:21] wire _jalr_target_msb_T_1 = &jalr_target_a; // @[functional-unit.scala:215:23, :216:34] wire _jalr_target_msb_T_2 = _jalr_target_msb_T | _jalr_target_msb_T_1; // @[functional-unit.scala:216:{21,29,34}] wire _jalr_target_msb_T_3 = jalr_target_xlen[39]; // @[functional-unit.scala:216:46, :230:30] wire _jalr_target_msb_T_4 = jalr_target_xlen[38]; // @[functional-unit.scala:216:62, :230:30] wire _jalr_target_msb_T_5 = ~_jalr_target_msb_T_4; // @[functional-unit.scala:216:{59,62}] wire jalr_target_msb = _jalr_target_msb_T_2 ? _jalr_target_msb_T_3 : _jalr_target_msb_T_5; // @[functional-unit.scala:216:{18,29,46,59}] wire [38:0] _jalr_target_T = jalr_target_xlen[38:0]; // @[functional-unit.scala:217:16, :230:30] wire [39:0] _jalr_target_T_1 = {jalr_target_msb, _jalr_target_T}; // @[functional-unit.scala:216:18, :217:{8,16}] wire [39:0] _jalr_target_T_2 = _jalr_target_T_1; // @[functional-unit.scala:217:8, :232:79] wire [39:0] _jalr_target_T_3 = _jalr_target_T_2 & 40'hFFFFFFFFFE; // @[functional-unit.scala:232:{79,86}] wire [39:0] _jalr_target_T_4 = _jalr_target_T_3; // @[functional-unit.scala:232:86] wire [39:0] jalr_target = _jalr_target_T_4; // @[functional-unit.scala:232:{86,94}] assign brinfo_bits_jalr_target = jalr_target; // @[functional-unit.scala:232:94, :252:20] wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[functional-unit.scala:234:{35,77}] wire [5:0] _cfi_idx_T_3 = {io_req_bits_uop_pc_lob_0[5:4], io_req_bits_uop_pc_lob_0[3:0] ^ _cfi_idx_T_2}; // @[functional-unit.scala:133:7, :234:{30,35}] wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[functional-unit.scala:234:{30,120}] wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:225:50, :227:37, :237:15, :255:34] wire _mispredict_T = ~io_req_bits_uop_taken_0; // @[functional-unit.scala:133:7, :242:21] wire _mispredict_T_1 = ~io_req_bits_ftq_info_1_valid_0; // @[functional-unit.scala:133:7, :245:22] wire _mispredict_T_2 = io_req_bits_ftq_info_1_pc_0 != jalr_target; // @[functional-unit.scala:133:7, :232:94, :246:50] wire _mispredict_T_3 = _mispredict_T_1 | _mispredict_T_2; // @[functional-unit.scala:245:{22,53}, :246:50] wire _mispredict_T_4 = ~io_req_bits_ftq_info_0_entry_cfi_idx_valid_0; // @[functional-unit.scala:133:7, :247:22] wire _mispredict_T_5 = _mispredict_T_3 | _mispredict_T_4; // @[functional-unit.scala:245:53, :246:67, :247:22] wire _mispredict_T_6 = io_req_bits_ftq_info_0_entry_cfi_idx_bits_0 != cfi_idx; // @[functional-unit.scala:133:7, :234:120, :248:66] wire _mispredict_T_7 = _mispredict_T_5 | _mispredict_T_6; // @[functional-unit.scala:246:67, :247:67, :248:66] assign mispredict = _brinfo_valid_T & (pc_sel == 2'h2 ? _mispredict_T_7 : pc_sel == 2'h1 ? _mispredict_T : ~(|pc_sel) & io_req_bits_uop_taken_0); // @[functional-unit.scala:133:7, :188:48, :202:28, :223:28, :237:27, :238:{18,32}, :239:18, :241:{18,32}, :242:{18,21}, :244:{18,31}, :245:18, :247:67, :255:34] assign io_brinfo_valid_0 = brinfo_valid; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_inst_0 = brinfo_bits_uop_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_inst_0 = brinfo_bits_uop_debug_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rvc_0 = brinfo_bits_uop_is_rvc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_pc_0 = brinfo_bits_uop_debug_pc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_0_0 = brinfo_bits_uop_iq_type_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_1_0 = brinfo_bits_uop_iq_type_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_2_0 = brinfo_bits_uop_iq_type_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iq_type_3_0 = brinfo_bits_uop_iq_type_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_0_0 = brinfo_bits_uop_fu_code_0; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_1_0 = brinfo_bits_uop_fu_code_1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_2_0 = brinfo_bits_uop_fu_code_2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_3_0 = brinfo_bits_uop_fu_code_3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_4_0 = brinfo_bits_uop_fu_code_4; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_5_0 = brinfo_bits_uop_fu_code_5; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_6_0 = brinfo_bits_uop_fu_code_6; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_7_0 = brinfo_bits_uop_fu_code_7; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_8_0 = brinfo_bits_uop_fu_code_8; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fu_code_9_0 = brinfo_bits_uop_fu_code_9; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_0 = brinfo_bits_uop_iw_issued; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_agen_0 = brinfo_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_issued_partial_dgen_0 = brinfo_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_speculative_child_0 = brinfo_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_speculative_child_0 = brinfo_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p1_bypass_hint_0 = brinfo_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p2_bypass_hint_0 = brinfo_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_iw_p3_bypass_hint_0 = brinfo_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dis_col_sel_0 = brinfo_bits_uop_dis_col_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_mask_0 = brinfo_bits_uop_br_mask; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_tag_0 = brinfo_bits_uop_br_tag; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_br_type_0 = brinfo_bits_uop_br_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfb_0 = brinfo_bits_uop_is_sfb; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fence_0 = brinfo_bits_uop_is_fence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_fencei_0 = brinfo_bits_uop_is_fencei; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sfence_0 = brinfo_bits_uop_is_sfence; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_amo_0 = brinfo_bits_uop_is_amo; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_eret_0 = brinfo_bits_uop_is_eret; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_sys_pc2epc_0 = brinfo_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_rocc_0 = brinfo_bits_uop_is_rocc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_mov_0 = brinfo_bits_uop_is_mov; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ftq_idx_0 = brinfo_bits_uop_ftq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_edge_inst_0 = brinfo_bits_uop_edge_inst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pc_lob_0 = brinfo_bits_uop_pc_lob; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_taken_0 = brinfo_bits_uop_taken; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_rename_0 = brinfo_bits_uop_imm_rename; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_sel_0 = brinfo_bits_uop_imm_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pimm_0 = brinfo_bits_uop_pimm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_imm_packed_0 = brinfo_bits_uop_imm_packed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op1_sel_0 = brinfo_bits_uop_op1_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_op2_sel_0 = brinfo_bits_uop_op2_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ldst_0 = brinfo_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wen_0 = brinfo_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren1_0 = brinfo_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren2_0 = brinfo_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_ren3_0 = brinfo_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap12_0 = brinfo_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_swap23_0 = brinfo_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn_0 = brinfo_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut_0 = brinfo_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fromint_0 = brinfo_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_toint_0 = brinfo_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fastpipe_0 = brinfo_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_fma_0 = brinfo_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_div_0 = brinfo_bits_uop_fp_ctrl_div; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_sqrt_0 = brinfo_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_wflags_0 = brinfo_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_ctrl_vec_0 = brinfo_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rob_idx_0 = brinfo_bits_uop_rob_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldq_idx_0 = brinfo_bits_uop_ldq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stq_idx_0 = brinfo_bits_uop_stq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_rxq_idx_0 = brinfo_bits_uop_rxq_idx; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_pdst_0 = brinfo_bits_uop_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_0 = brinfo_bits_uop_prs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_0 = brinfo_bits_uop_prs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_0 = brinfo_bits_uop_prs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_0 = brinfo_bits_uop_ppred; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs1_busy_0 = brinfo_bits_uop_prs1_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs2_busy_0 = brinfo_bits_uop_prs2_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_prs3_busy_0 = brinfo_bits_uop_prs3_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ppred_busy_0 = brinfo_bits_uop_ppred_busy; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_stale_pdst_0 = brinfo_bits_uop_stale_pdst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exception_0 = brinfo_bits_uop_exception; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_exc_cause_0 = brinfo_bits_uop_exc_cause; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_cmd_0 = brinfo_bits_uop_mem_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_size_0 = brinfo_bits_uop_mem_size; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_mem_signed_0 = brinfo_bits_uop_mem_signed; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_ldq_0 = brinfo_bits_uop_uses_ldq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_uses_stq_0 = brinfo_bits_uop_uses_stq; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_is_unique_0 = brinfo_bits_uop_is_unique; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_flush_on_commit_0 = brinfo_bits_uop_flush_on_commit; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_csr_cmd_0 = brinfo_bits_uop_csr_cmd; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_is_rs1_0 = brinfo_bits_uop_ldst_is_rs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_ldst_0 = brinfo_bits_uop_ldst; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_0 = brinfo_bits_uop_lrs1; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_0 = brinfo_bits_uop_lrs2; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs3_0 = brinfo_bits_uop_lrs3; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_dst_rtype_0 = brinfo_bits_uop_dst_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs1_rtype_0 = brinfo_bits_uop_lrs1_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_lrs2_rtype_0 = brinfo_bits_uop_lrs2_rtype; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_frs3_en_0 = brinfo_bits_uop_frs3_en; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_dw_0 = brinfo_bits_uop_fcn_dw; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fcn_op_0 = brinfo_bits_uop_fcn_op; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_val_0 = brinfo_bits_uop_fp_val; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_rm_0 = brinfo_bits_uop_fp_rm; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_fp_typ_0 = brinfo_bits_uop_fp_typ; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_pf_if_0 = brinfo_bits_uop_xcpt_pf_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ae_if_0 = brinfo_bits_uop_xcpt_ae_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_xcpt_ma_if_0 = brinfo_bits_uop_xcpt_ma_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_debug_if_0 = brinfo_bits_uop_bp_debug_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_bp_xcpt_if_0 = brinfo_bits_uop_bp_xcpt_if; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_fsrc_0 = brinfo_bits_uop_debug_fsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_uop_debug_tsrc_0 = brinfo_bits_uop_debug_tsrc; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_mispredict_0 = brinfo_bits_mispredict; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_taken_0 = brinfo_bits_taken; // @[functional-unit.scala:133:7, :252:20] wire [2:0] _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:258:36] assign io_brinfo_bits_cfi_type_0 = brinfo_bits_cfi_type; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_pc_sel_0 = brinfo_bits_pc_sel; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_jalr_target_0 = brinfo_bits_jalr_target; // @[functional-unit.scala:133:7, :252:20] assign io_brinfo_bits_target_offset_0 = brinfo_bits_target_offset; // @[functional-unit.scala:133:7, :252:20] assign brinfo_valid = _brinfo_valid_T; // @[functional-unit.scala:252:20, :255:34] wire [2:0] _brinfo_bits_cfi_type_T = {2'h0, is_br}; // @[functional-unit.scala:225:50, :259:36] assign _brinfo_bits_cfi_type_T_1 = is_jalr ? 3'h3 : _brinfo_bits_cfi_type_T; // @[functional-unit.scala:227:37, :258:36, :259:36] assign brinfo_bits_cfi_type = _brinfo_bits_cfi_type_T_1; // @[functional-unit.scala:252:20, :258:36] wire _alu_out_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _alu_out_T_1 = _alu_out_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _alu_out_T_2 = _alu_out_T_1; // @[micro-op.scala:121:{42,52}] wire _alu_out_T_3 = _alu_out_T_2 & io_req_bits_pred_data_0; // @[functional-unit.scala:133:7, :285:51] wire [63:0] _alu_out_T_4 = io_req_bits_uop_ldst_is_rs1_0 ? io_req_bits_rs1_data_0 : io_req_bits_rs2_data_0; // @[functional-unit.scala:133:7, :286:10] wire [63:0] _alu_out_T_5 = io_req_bits_uop_is_mov_0 ? io_req_bits_rs2_data_0 : _alu_io_out; // @[functional-unit.scala:133:7, :173:19, :287:10] wire [63:0] alu_out = _alu_out_T_3 ? _alu_out_T_4 : _alu_out_T_5; // @[functional-unit.scala:285:{20,51}, :286:10, :287:10] wire _io_resp_bits_data_T = |io_req_bits_uop_br_type_0; // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_data_T_2 = _io_resp_bits_data_T_1; // @[micro-op.scala:120:{42,52}] wire _io_resp_bits_data_T_3 = pc_sel == 2'h1; // @[functional-unit.scala:188:48, :290:62] assign _io_resp_bits_data_T_4 = _io_resp_bits_data_T_2 ? {63'h0, _io_resp_bits_data_T_3} : alu_out; // @[OneHot.scala:58:35] assign io_resp_bits_data_0 = _io_resp_bits_data_T_4; // @[functional-unit.scala:133:7, :290:27] wire _io_resp_bits_predicated_T = ~(|io_req_bits_uop_br_type_0); // @[functional-unit.scala:133:7, :188:48] wire _io_resp_bits_predicated_T_1 = _io_resp_bits_predicated_T & io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] wire _io_resp_bits_predicated_T_2 = _io_resp_bits_predicated_T_1; // @[micro-op.scala:121:{42,52}] assign _io_resp_bits_predicated_T_3 = _io_resp_bits_predicated_T_2 & io_req_bits_pred_data_0; // @[functional-unit.scala:133:7, :291:60] assign io_resp_bits_predicated_0 = _io_resp_bits_predicated_T_3; // @[functional-unit.scala:133:7, :291:60] ALU_1 alu ( // @[functional-unit.scala:173:19] .clock (clock), .reset (reset), .io_dw (_alu_io_dw_T_1), // @[functional-unit.scala:178:20] .io_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:133:7] .io_in2 (op2_data), // @[functional-unit.scala:164:45] .io_in1 (op1_data[63:0]), // @[functional-unit.scala:155:45, :175:14] .io_out (_alu_io_out) ); // @[functional-unit.scala:173:19] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:133:7] assign io_resp_bits_predicated = io_resp_bits_predicated_0; // @[functional-unit.scala:133:7] assign io_brinfo_valid = io_brinfo_valid_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_inst = io_brinfo_bits_uop_inst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_debug_inst = io_brinfo_bits_uop_debug_inst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_rvc = io_brinfo_bits_uop_is_rvc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_debug_pc = io_brinfo_bits_uop_debug_pc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iq_type_0 = io_brinfo_bits_uop_iq_type_0_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iq_type_1 = io_brinfo_bits_uop_iq_type_1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iq_type_2 = io_brinfo_bits_uop_iq_type_2_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iq_type_3 = io_brinfo_bits_uop_iq_type_3_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_0 = io_brinfo_bits_uop_fu_code_0_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_1 = io_brinfo_bits_uop_fu_code_1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_2 = io_brinfo_bits_uop_fu_code_2_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_3 = io_brinfo_bits_uop_fu_code_3_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_4 = io_brinfo_bits_uop_fu_code_4_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_5 = io_brinfo_bits_uop_fu_code_5_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_6 = io_brinfo_bits_uop_fu_code_6_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_7 = io_brinfo_bits_uop_fu_code_7_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_8 = io_brinfo_bits_uop_fu_code_8_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fu_code_9 = io_brinfo_bits_uop_fu_code_9_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_issued = io_brinfo_bits_uop_iw_issued_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_issued_partial_agen = io_brinfo_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_issued_partial_dgen = io_brinfo_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_p1_speculative_child = io_brinfo_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_p2_speculative_child = io_brinfo_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_p1_bypass_hint = io_brinfo_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_p2_bypass_hint = io_brinfo_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_iw_p3_bypass_hint = io_brinfo_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_dis_col_sel = io_brinfo_bits_uop_dis_col_sel_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_br_mask = io_brinfo_bits_uop_br_mask_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_br_tag = io_brinfo_bits_uop_br_tag_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_br_type = io_brinfo_bits_uop_br_type_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_sfb = io_brinfo_bits_uop_is_sfb_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_fence = io_brinfo_bits_uop_is_fence_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_fencei = io_brinfo_bits_uop_is_fencei_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_sfence = io_brinfo_bits_uop_is_sfence_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_amo = io_brinfo_bits_uop_is_amo_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_eret = io_brinfo_bits_uop_is_eret_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_sys_pc2epc = io_brinfo_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_rocc = io_brinfo_bits_uop_is_rocc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_mov = io_brinfo_bits_uop_is_mov_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ftq_idx = io_brinfo_bits_uop_ftq_idx_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_edge_inst = io_brinfo_bits_uop_edge_inst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_pc_lob = io_brinfo_bits_uop_pc_lob_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_taken = io_brinfo_bits_uop_taken_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_imm_rename = io_brinfo_bits_uop_imm_rename_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_imm_sel = io_brinfo_bits_uop_imm_sel_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_pimm = io_brinfo_bits_uop_pimm_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_imm_packed = io_brinfo_bits_uop_imm_packed_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_op1_sel = io_brinfo_bits_uop_op1_sel_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_op2_sel = io_brinfo_bits_uop_op2_sel_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_ldst = io_brinfo_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_wen = io_brinfo_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_ren1 = io_brinfo_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_ren2 = io_brinfo_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_ren3 = io_brinfo_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_swap12 = io_brinfo_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_swap23 = io_brinfo_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_typeTagIn = io_brinfo_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_typeTagOut = io_brinfo_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_fromint = io_brinfo_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_toint = io_brinfo_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_fastpipe = io_brinfo_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_fma = io_brinfo_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_div = io_brinfo_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_sqrt = io_brinfo_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_wflags = io_brinfo_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_ctrl_vec = io_brinfo_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_rob_idx = io_brinfo_bits_uop_rob_idx_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ldq_idx = io_brinfo_bits_uop_ldq_idx_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_stq_idx = io_brinfo_bits_uop_stq_idx_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_rxq_idx = io_brinfo_bits_uop_rxq_idx_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_pdst = io_brinfo_bits_uop_pdst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs1 = io_brinfo_bits_uop_prs1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs2 = io_brinfo_bits_uop_prs2_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs3 = io_brinfo_bits_uop_prs3_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ppred = io_brinfo_bits_uop_ppred_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs1_busy = io_brinfo_bits_uop_prs1_busy_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs2_busy = io_brinfo_bits_uop_prs2_busy_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_prs3_busy = io_brinfo_bits_uop_prs3_busy_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ppred_busy = io_brinfo_bits_uop_ppred_busy_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_stale_pdst = io_brinfo_bits_uop_stale_pdst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_exception = io_brinfo_bits_uop_exception_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_exc_cause = io_brinfo_bits_uop_exc_cause_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_mem_cmd = io_brinfo_bits_uop_mem_cmd_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_mem_size = io_brinfo_bits_uop_mem_size_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_mem_signed = io_brinfo_bits_uop_mem_signed_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_uses_ldq = io_brinfo_bits_uop_uses_ldq_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_uses_stq = io_brinfo_bits_uop_uses_stq_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_is_unique = io_brinfo_bits_uop_is_unique_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_flush_on_commit = io_brinfo_bits_uop_flush_on_commit_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_csr_cmd = io_brinfo_bits_uop_csr_cmd_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ldst_is_rs1 = io_brinfo_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_ldst = io_brinfo_bits_uop_ldst_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_lrs1 = io_brinfo_bits_uop_lrs1_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_lrs2 = io_brinfo_bits_uop_lrs2_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_lrs3 = io_brinfo_bits_uop_lrs3_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_dst_rtype = io_brinfo_bits_uop_dst_rtype_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_lrs1_rtype = io_brinfo_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_lrs2_rtype = io_brinfo_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_frs3_en = io_brinfo_bits_uop_frs3_en_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fcn_dw = io_brinfo_bits_uop_fcn_dw_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fcn_op = io_brinfo_bits_uop_fcn_op_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_val = io_brinfo_bits_uop_fp_val_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_rm = io_brinfo_bits_uop_fp_rm_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_fp_typ = io_brinfo_bits_uop_fp_typ_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_xcpt_pf_if = io_brinfo_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_xcpt_ae_if = io_brinfo_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_xcpt_ma_if = io_brinfo_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_bp_debug_if = io_brinfo_bits_uop_bp_debug_if_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_bp_xcpt_if = io_brinfo_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_debug_fsrc = io_brinfo_bits_uop_debug_fsrc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_uop_debug_tsrc = io_brinfo_bits_uop_debug_tsrc_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_mispredict = io_brinfo_bits_mispredict_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_taken = io_brinfo_bits_taken_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_cfi_type = io_brinfo_bits_cfi_type_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_pc_sel = io_brinfo_bits_pc_sel_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_jalr_target = io_brinfo_bits_jalr_target_0; // @[functional-unit.scala:133:7] assign io_brinfo_bits_target_offset = io_brinfo_bits_target_offset_0; // @[functional-unit.scala:133:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_25 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_25( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_19 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_19( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_158 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_158( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_16ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_14 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLNoC_router_16ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_14 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_10 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_156, _T_167) node _T_169 = or(UInt<1>(0h0), _T_154) node _T_170 = or(_T_169, _T_168) node _T_171 = and(_T_105, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_171, UInt<1>(0h1), "") : assert_2 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_183, _T_188) node _T_230 = or(_T_229, _T_193) node _T_231 = or(_T_230, _T_198) node _T_232 = or(_T_231, _T_203) node _T_233 = or(_T_232, _T_208) node _T_234 = or(_T_233, _T_213) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_223) node _T_237 = or(_T_236, _T_228) node _T_238 = and(_T_178, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_240, UInt<1>(0h1), "") : assert_3 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_247, UInt<1>(0h1), "") : assert_5 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = not(io.in.a.bits.mask) node _T_259 = eq(_T_258, UInt<1>(0h0)) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_259, UInt<1>(0h1), "") : assert_8 node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_263, UInt<1>(0h1), "") : assert_9 node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_267 : node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_8) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h1)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_9) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h2)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_10) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h3)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_11) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _T_296 = or(_T_271, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_295) node _T_300 = and(_T_270, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_307, _T_312) node _T_344 = or(_T_343, _T_317) node _T_345 = or(_T_344, _T_322) node _T_346 = or(_T_345, _T_327) node _T_347 = or(_T_346, _T_332) node _T_348 = or(_T_347, _T_337) node _T_349 = or(_T_348, _T_342) node _T_350 = and(_T_302, _T_349) node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_357, _T_362) node _T_364 = and(_T_352, _T_363) node _T_365 = or(UInt<1>(0h0), _T_350) node _T_366 = or(_T_365, _T_364) node _T_367 = and(_T_301, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_367, UInt<1>(0h1), "") : assert_10 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = or(_T_379, _T_384) node _T_426 = or(_T_425, _T_389) node _T_427 = or(_T_426, _T_394) node _T_428 = or(_T_427, _T_399) node _T_429 = or(_T_428, _T_404) node _T_430 = or(_T_429, _T_409) node _T_431 = or(_T_430, _T_414) node _T_432 = or(_T_431, _T_419) node _T_433 = or(_T_432, _T_424) node _T_434 = and(_T_374, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = and(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_436, UInt<1>(0h1), "") : assert_11 node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(source_ok, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_443 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_443, UInt<1>(0h1), "") : assert_13 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(is_aligned, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_450, UInt<1>(0h1), "") : assert_15 node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_454, UInt<1>(0h1), "") : assert_16 node _T_458 = not(io.in.a.bits.mask) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_459, UInt<1>(0h1), "") : assert_17 node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_463, UInt<1>(0h1), "") : assert_18 node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_472 = shr(io.in.a.bits.source, 2) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_12) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h1)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_13) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<2>(0h2)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_14) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h3)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_15) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_471, _T_477) node _T_497 = or(_T_496, _T_483) node _T_498 = or(_T_497, _T_489) node _T_499 = or(_T_498, _T_495) node _T_500 = and(_T_470, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_501, UInt<1>(0h1), "") : assert_19 node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = or(UInt<1>(0h0), _T_507) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = and(_T_508, _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = or(_T_523, _T_528) node _T_565 = or(_T_564, _T_533) node _T_566 = or(_T_565, _T_538) node _T_567 = or(_T_566, _T_543) node _T_568 = or(_T_567, _T_548) node _T_569 = or(_T_568, _T_553) node _T_570 = or(_T_569, _T_558) node _T_571 = or(_T_570, _T_563) node _T_572 = and(_T_518, _T_571) node _T_573 = or(UInt<1>(0h0), _T_514) node _T_574 = or(_T_573, _T_572) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_574, UInt<1>(0h1), "") : assert_20 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(source_ok, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(is_aligned, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_584, UInt<1>(0h1), "") : assert_23 node _T_588 = eq(io.in.a.bits.mask, mask) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_588, UInt<1>(0h1), "") : assert_24 node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_593 = asUInt(reset) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(_T_592, UInt<1>(0h0)) when _T_595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_592, UInt<1>(0h1), "") : assert_25 node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_596 : node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_16) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<1>(0h1)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_17) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<2>(0h2)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_18) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<2>(0h3)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_19) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _T_625 = or(_T_600, _T_606) node _T_626 = or(_T_625, _T_612) node _T_627 = or(_T_626, _T_618) node _T_628 = or(_T_627, _T_624) node _T_629 = and(_T_599, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_703, UInt<1>(0h1), "") : assert_26 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_713, UInt<1>(0h1), "") : assert_29 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_717, UInt<1>(0h1), "") : assert_30 node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_20) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_732 = shr(io.in.a.bits.source, 2) node _T_733 = eq(_T_732, UInt<1>(0h1)) node _T_734 = leq(UInt<1>(0h0), uncommonBits_21) node _T_735 = and(_T_733, _T_734) node _T_736 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_737 = and(_T_735, _T_736) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_738 = shr(io.in.a.bits.source, 2) node _T_739 = eq(_T_738, UInt<2>(0h2)) node _T_740 = leq(UInt<1>(0h0), uncommonBits_22) node _T_741 = and(_T_739, _T_740) node _T_742 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_743 = and(_T_741, _T_742) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<2>(0h3)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_23) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(_T_725, _T_731) node _T_751 = or(_T_750, _T_737) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_749) node _T_754 = and(_T_724, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = and(_T_759, _T_764) node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_768 = and(_T_766, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_774, _T_779) node _T_811 = or(_T_810, _T_784) node _T_812 = or(_T_811, _T_789) node _T_813 = or(_T_812, _T_794) node _T_814 = or(_T_813, _T_799) node _T_815 = or(_T_814, _T_804) node _T_816 = or(_T_815, _T_809) node _T_817 = and(_T_769, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_765) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_828, UInt<1>(0h1), "") : assert_31 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(source_ok, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_838, UInt<1>(0h1), "") : assert_34 node _T_842 = not(mask) node _T_843 = and(io.in.a.bits.mask, _T_842) node _T_844 = eq(_T_843, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_844, UInt<1>(0h1), "") : assert_35 node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_848 : node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_24) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_25) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h2)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_26) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<2>(0h3)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_27) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _T_877 = or(_T_852, _T_858) node _T_878 = or(_T_877, _T_864) node _T_879 = or(_T_878, _T_870) node _T_880 = or(_T_879, _T_876) node _T_881 = and(_T_851, _T_880) node _T_882 = or(UInt<1>(0h0), _T_881) node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<27>(0h4000000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_923 = cvt(_T_922) node _T_924 = and(_T_923, asSInt(UInt<13>(0h1000))) node _T_925 = asSInt(_T_924) node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0))) node _T_927 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<29>(0h10000000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = or(_T_891, _T_896) node _T_933 = or(_T_932, _T_901) node _T_934 = or(_T_933, _T_906) node _T_935 = or(_T_934, _T_911) node _T_936 = or(_T_935, _T_916) node _T_937 = or(_T_936, _T_921) node _T_938 = or(_T_937, _T_926) node _T_939 = or(_T_938, _T_931) node _T_940 = and(_T_886, _T_939) node _T_941 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_942 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<17>(0h10000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = and(_T_941, _T_946) node _T_948 = or(UInt<1>(0h0), _T_940) node _T_949 = or(_T_948, _T_947) node _T_950 = and(_T_882, _T_949) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_950, UInt<1>(0h1), "") : assert_36 node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(source_ok, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(is_aligned, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_960 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_960, UInt<1>(0h1), "") : assert_39 node _T_964 = eq(io.in.a.bits.mask, mask) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_964, UInt<1>(0h1), "") : assert_40 node _T_968 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_968 : node _T_969 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_970 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_971 = and(_T_969, _T_970) node _T_972 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_973 = shr(io.in.a.bits.source, 2) node _T_974 = eq(_T_973, UInt<1>(0h0)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_28) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_978 = and(_T_976, _T_977) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_979 = shr(io.in.a.bits.source, 2) node _T_980 = eq(_T_979, UInt<1>(0h1)) node _T_981 = leq(UInt<1>(0h0), uncommonBits_29) node _T_982 = and(_T_980, _T_981) node _T_983 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_984 = and(_T_982, _T_983) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_985 = shr(io.in.a.bits.source, 2) node _T_986 = eq(_T_985, UInt<2>(0h2)) node _T_987 = leq(UInt<1>(0h0), uncommonBits_30) node _T_988 = and(_T_986, _T_987) node _T_989 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_990 = and(_T_988, _T_989) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_991 = shr(io.in.a.bits.source, 2) node _T_992 = eq(_T_991, UInt<2>(0h3)) node _T_993 = leq(UInt<1>(0h0), uncommonBits_31) node _T_994 = and(_T_992, _T_993) node _T_995 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_996 = and(_T_994, _T_995) node _T_997 = or(_T_972, _T_978) node _T_998 = or(_T_997, _T_984) node _T_999 = or(_T_998, _T_990) node _T_1000 = or(_T_999, _T_996) node _T_1001 = and(_T_971, _T_1000) node _T_1002 = or(UInt<1>(0h0), _T_1001) node _T_1003 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1004 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<14>(0h2000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<13>(0h1000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<18>(0h2f000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<17>(0h10000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1028 = cvt(_T_1027) node _T_1029 = and(_T_1028, asSInt(UInt<13>(0h1000))) node _T_1030 = asSInt(_T_1029) node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0))) node _T_1032 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1038 = cvt(_T_1037) node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000))) node _T_1040 = asSInt(_T_1039) node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0))) node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1048 = cvt(_T_1047) node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000))) node _T_1050 = asSInt(_T_1049) node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0))) node _T_1052 = or(_T_1011, _T_1016) node _T_1053 = or(_T_1052, _T_1021) node _T_1054 = or(_T_1053, _T_1026) node _T_1055 = or(_T_1054, _T_1031) node _T_1056 = or(_T_1055, _T_1036) node _T_1057 = or(_T_1056, _T_1041) node _T_1058 = or(_T_1057, _T_1046) node _T_1059 = or(_T_1058, _T_1051) node _T_1060 = and(_T_1006, _T_1059) node _T_1061 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1062 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1063 = cvt(_T_1062) node _T_1064 = and(_T_1063, asSInt(UInt<17>(0h10000))) node _T_1065 = asSInt(_T_1064) node _T_1066 = eq(_T_1065, asSInt(UInt<1>(0h0))) node _T_1067 = and(_T_1061, _T_1066) node _T_1068 = or(UInt<1>(0h0), _T_1060) node _T_1069 = or(_T_1068, _T_1067) node _T_1070 = and(_T_1002, _T_1069) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_41 node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(source_ok, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(is_aligned, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1080 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_44 node _T_1084 = eq(io.in.a.bits.mask, mask) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_45 node _T_1088 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1088 : node _T_1089 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1090 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1091 = and(_T_1089, _T_1090) node _T_1092 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<1>(0h1)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h2)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1111 = shr(io.in.a.bits.source, 2) node _T_1112 = eq(_T_1111, UInt<2>(0h3)) node _T_1113 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1114 = and(_T_1112, _T_1113) node _T_1115 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1116 = and(_T_1114, _T_1115) node _T_1117 = or(_T_1092, _T_1098) node _T_1118 = or(_T_1117, _T_1104) node _T_1119 = or(_T_1118, _T_1110) node _T_1120 = or(_T_1119, _T_1116) node _T_1121 = and(_T_1091, _T_1120) node _T_1122 = or(UInt<1>(0h0), _T_1121) node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<13>(0h1000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = and(_T_1126, _T_1131) node _T_1133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<14>(0h2000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<17>(0h10000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<18>(0h2f000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<13>(0h1000))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<27>(0h4000000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1165 = cvt(_T_1164) node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000))) node _T_1167 = asSInt(_T_1166) node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = or(_T_1138, _T_1143) node _T_1170 = or(_T_1169, _T_1148) node _T_1171 = or(_T_1170, _T_1153) node _T_1172 = or(_T_1171, _T_1158) node _T_1173 = or(_T_1172, _T_1163) node _T_1174 = or(_T_1173, _T_1168) node _T_1175 = and(_T_1133, _T_1174) node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1177 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1178 = and(_T_1176, _T_1177) node _T_1179 = or(UInt<1>(0h0), _T_1178) node _T_1180 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1181 = cvt(_T_1180) node _T_1182 = and(_T_1181, asSInt(UInt<17>(0h10000))) node _T_1183 = asSInt(_T_1182) node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0))) node _T_1185 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1186 = cvt(_T_1185) node _T_1187 = and(_T_1186, asSInt(UInt<29>(0h10000000))) node _T_1188 = asSInt(_T_1187) node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0))) node _T_1190 = or(_T_1184, _T_1189) node _T_1191 = and(_T_1179, _T_1190) node _T_1192 = or(UInt<1>(0h0), _T_1132) node _T_1193 = or(_T_1192, _T_1175) node _T_1194 = or(_T_1193, _T_1191) node _T_1195 = and(_T_1122, _T_1194) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_46 node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(source_ok, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(is_aligned, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1205 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_49 node _T_1209 = eq(io.in.a.bits.mask, mask) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_50 node _T_1213 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1217 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1218 = asUInt(reset) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) when _T_1219 : node _T_1220 = eq(_T_1217, UInt<1>(0h0)) when _T_1220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1217, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1221 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1221 : node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(source_ok_1, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1225 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_54 node _T_1229 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_55 node _T_1233 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_56 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_57 node _T_1241 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1241 : node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(source_ok_1, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(sink_ok, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1248 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_60 node _T_1252 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_61 node _T_1256 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_62 node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_63 node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1265 = or(UInt<1>(0h1), _T_1264) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_64 node _T_1269 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1269 : node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(source_ok_1, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1273 = asUInt(reset) node _T_1274 = eq(_T_1273, UInt<1>(0h0)) when _T_1274 : node _T_1275 = eq(sink_ok, UInt<1>(0h0)) when _T_1275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1276 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_67 node _T_1280 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_68 node _T_1284 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_69 node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1289 = or(_T_1288, io.in.d.bits.corrupt) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_70 node _T_1293 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1294 = or(UInt<1>(0h1), _T_1293) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_71 node _T_1298 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1298 : node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(source_ok_1, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1302 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_73 node _T_1306 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_74 node _T_1310 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1311 = or(UInt<1>(0h1), _T_1310) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_75 node _T_1315 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1315 : node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(source_ok_1, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1319 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_77 node _T_1323 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1324 = or(_T_1323, io.in.d.bits.corrupt) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_78 node _T_1328 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1329 = or(UInt<1>(0h1), _T_1328) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_79 node _T_1333 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1333 : node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(source_ok_1, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1337 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(_T_1337, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1337, UInt<1>(0h1), "") : assert_81 node _T_1341 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1342 = asUInt(reset) node _T_1343 = eq(_T_1342, UInt<1>(0h0)) when _T_1343 : node _T_1344 = eq(_T_1341, UInt<1>(0h0)) when _T_1344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1341, UInt<1>(0h1), "") : assert_82 node _T_1345 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1346 = or(UInt<1>(0h1), _T_1345) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1350 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1354 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1358 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1362 = eq(a_first, UInt<1>(0h0)) node _T_1363 = and(io.in.a.valid, _T_1362) when _T_1363 : node _T_1364 = eq(io.in.a.bits.opcode, opcode) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_87 node _T_1368 = eq(io.in.a.bits.param, param) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_88 node _T_1372 = eq(io.in.a.bits.size, size) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_89 node _T_1376 = eq(io.in.a.bits.source, source) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_90 node _T_1380 = eq(io.in.a.bits.address, address) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_91 node _T_1384 = and(io.in.a.ready, io.in.a.valid) node _T_1385 = and(_T_1384, a_first) when _T_1385 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1386 = eq(d_first, UInt<1>(0h0)) node _T_1387 = and(io.in.d.valid, _T_1386) when _T_1387 : node _T_1388 = eq(io.in.d.bits.opcode, opcode_1) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_92 node _T_1392 = eq(io.in.d.bits.param, param_1) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_93 node _T_1396 = eq(io.in.d.bits.size, size_1) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_94 node _T_1400 = eq(io.in.d.bits.source, source_1) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_95 node _T_1404 = eq(io.in.d.bits.sink, sink) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_96 node _T_1408 = eq(io.in.d.bits.denied, denied) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_97 node _T_1412 = and(io.in.d.ready, io.in.d.valid) node _T_1413 = and(_T_1412, d_first) when _T_1413 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1414 = and(io.in.a.valid, a_first_1) node _T_1415 = and(_T_1414, UInt<1>(0h1)) when _T_1415 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1416 = and(io.in.a.ready, io.in.a.valid) node _T_1417 = and(_T_1416, a_first_1) node _T_1418 = and(_T_1417, UInt<1>(0h1)) when _T_1418 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1419 = dshr(inflight, io.in.a.bits.source) node _T_1420 = bits(_T_1419, 0, 0) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(_T_1421, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1421, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1425 = and(io.in.d.valid, d_first_1) node _T_1426 = and(_T_1425, UInt<1>(0h1)) node _T_1427 = eq(d_release_ack, UInt<1>(0h0)) node _T_1428 = and(_T_1426, _T_1427) when _T_1428 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1429 = and(io.in.d.ready, io.in.d.valid) node _T_1430 = and(_T_1429, d_first_1) node _T_1431 = and(_T_1430, UInt<1>(0h1)) node _T_1432 = eq(d_release_ack, UInt<1>(0h0)) node _T_1433 = and(_T_1431, _T_1432) when _T_1433 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1434 = and(io.in.d.valid, d_first_1) node _T_1435 = and(_T_1434, UInt<1>(0h1)) node _T_1436 = eq(d_release_ack, UInt<1>(0h0)) node _T_1437 = and(_T_1435, _T_1436) when _T_1437 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1438 = dshr(inflight, io.in.d.bits.source) node _T_1439 = bits(_T_1438, 0, 0) node _T_1440 = or(_T_1439, same_cycle_resp) node _T_1441 = asUInt(reset) node _T_1442 = eq(_T_1441, UInt<1>(0h0)) when _T_1442 : node _T_1443 = eq(_T_1440, UInt<1>(0h0)) when _T_1443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1440, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1444 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1445 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1446 = or(_T_1444, _T_1445) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_100 node _T_1450 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_101 else : node _T_1454 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1456 = or(_T_1454, _T_1455) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_102 node _T_1460 = eq(io.in.d.bits.size, a_size_lookup) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_103 node _T_1464 = and(io.in.d.valid, d_first_1) node _T_1465 = and(_T_1464, a_first_1) node _T_1466 = and(_T_1465, io.in.a.valid) node _T_1467 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = eq(d_release_ack, UInt<1>(0h0)) node _T_1470 = and(_T_1468, _T_1469) when _T_1470 : node _T_1471 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1472 = or(_T_1471, io.in.a.ready) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_104 node _T_1476 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1477 = orr(a_set_wo_ready) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) node _T_1479 = or(_T_1476, _T_1478) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_20 node _T_1483 = orr(inflight) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) node _T_1485 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1486 = or(_T_1484, _T_1485) node _T_1487 = lt(watchdog, plusarg_reader.out) node _T_1488 = or(_T_1486, _T_1487) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1492 = and(io.in.a.ready, io.in.a.valid) node _T_1493 = and(io.in.d.ready, io.in.d.valid) node _T_1494 = or(_T_1492, _T_1493) when _T_1494 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1495 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1496 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1497 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = and(_T_1495, _T_1498) when _T_1499 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1500 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1501 = and(_T_1500, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1502 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1503 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = and(_T_1501, _T_1504) when _T_1505 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1506 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1507 = bits(_T_1506, 0, 0) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1512 = and(io.in.d.valid, d_first_2) node _T_1513 = and(_T_1512, UInt<1>(0h1)) node _T_1514 = and(_T_1513, d_release_ack_1) when _T_1514 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1515 = and(io.in.d.ready, io.in.d.valid) node _T_1516 = and(_T_1515, d_first_2) node _T_1517 = and(_T_1516, UInt<1>(0h1)) node _T_1518 = and(_T_1517, d_release_ack_1) when _T_1518 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1519 = and(io.in.d.valid, d_first_2) node _T_1520 = and(_T_1519, UInt<1>(0h1)) node _T_1521 = and(_T_1520, d_release_ack_1) when _T_1521 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1522 = dshr(inflight_1, io.in.d.bits.source) node _T_1523 = bits(_T_1522, 0, 0) node _T_1524 = or(_T_1523, same_cycle_resp_1) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1528 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1529 = asUInt(reset) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(_T_1528, UInt<1>(0h0)) when _T_1531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1528, UInt<1>(0h1), "") : assert_109 else : node _T_1532 = eq(io.in.d.bits.size, c_size_lookup) node _T_1533 = asUInt(reset) node _T_1534 = eq(_T_1533, UInt<1>(0h0)) when _T_1534 : node _T_1535 = eq(_T_1532, UInt<1>(0h0)) when _T_1535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1532, UInt<1>(0h1), "") : assert_110 node _T_1536 = and(io.in.d.valid, d_first_2) node _T_1537 = and(_T_1536, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1538 = and(_T_1537, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1539 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1540 = and(_T_1538, _T_1539) node _T_1541 = and(_T_1540, d_release_ack_1) node _T_1542 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1543 = and(_T_1541, _T_1542) when _T_1543 : node _T_1544 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1545 = or(_T_1544, _WIRE_23.ready) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_111 node _T_1549 = orr(c_set_wo_ready) when _T_1549 : node _T_1550 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_21 node _T_1554 = orr(inflight_1) node _T_1555 = eq(_T_1554, UInt<1>(0h0)) node _T_1556 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1557 = or(_T_1555, _T_1556) node _T_1558 = lt(watchdog_1, plusarg_reader_1.out) node _T_1559 = or(_T_1557, _T_1558) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:61:150)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1563 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1564 = and(io.in.d.ready, io.in.d.valid) node _T_1565 = or(_T_1563, _T_1564) when _T_1565 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_10( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_65 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_65( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_50 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_50 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_391 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_391( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_3 : input clock : Clock input reset : Reset output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[3], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}} connect io.req.ready, UInt<1>(0h0) connect io.iresp.valid, UInt<1>(0h0) invalidate io.iresp.bits.fflags.bits.flags invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if invalidate io.iresp.bits.fflags.bits.uop.fp_single invalidate io.iresp.bits.fflags.bits.uop.fp_val invalidate io.iresp.bits.fflags.bits.uop.frs3_en invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype invalidate io.iresp.bits.fflags.bits.uop.dst_rtype invalidate io.iresp.bits.fflags.bits.uop.ldst_val invalidate io.iresp.bits.fflags.bits.uop.lrs3 invalidate io.iresp.bits.fflags.bits.uop.lrs2 invalidate io.iresp.bits.fflags.bits.uop.lrs1 invalidate io.iresp.bits.fflags.bits.uop.ldst invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit invalidate io.iresp.bits.fflags.bits.uop.is_unique invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.fflags.bits.uop.uses_stq invalidate io.iresp.bits.fflags.bits.uop.uses_ldq invalidate io.iresp.bits.fflags.bits.uop.is_amo invalidate io.iresp.bits.fflags.bits.uop.is_fencei invalidate io.iresp.bits.fflags.bits.uop.is_fence invalidate io.iresp.bits.fflags.bits.uop.mem_signed invalidate io.iresp.bits.fflags.bits.uop.mem_size invalidate io.iresp.bits.fflags.bits.uop.mem_cmd invalidate io.iresp.bits.fflags.bits.uop.bypassable invalidate io.iresp.bits.fflags.bits.uop.exc_cause invalidate io.iresp.bits.fflags.bits.uop.exception invalidate io.iresp.bits.fflags.bits.uop.stale_pdst invalidate io.iresp.bits.fflags.bits.uop.ppred_busy invalidate io.iresp.bits.fflags.bits.uop.prs3_busy invalidate io.iresp.bits.fflags.bits.uop.prs2_busy invalidate io.iresp.bits.fflags.bits.uop.prs1_busy invalidate io.iresp.bits.fflags.bits.uop.ppred invalidate io.iresp.bits.fflags.bits.uop.prs3 invalidate io.iresp.bits.fflags.bits.uop.prs2 invalidate io.iresp.bits.fflags.bits.uop.prs1 invalidate io.iresp.bits.fflags.bits.uop.pdst invalidate io.iresp.bits.fflags.bits.uop.rxq_idx invalidate io.iresp.bits.fflags.bits.uop.stq_idx invalidate io.iresp.bits.fflags.bits.uop.ldq_idx invalidate io.iresp.bits.fflags.bits.uop.rob_idx invalidate io.iresp.bits.fflags.bits.uop.csr_addr invalidate io.iresp.bits.fflags.bits.uop.imm_packed invalidate io.iresp.bits.fflags.bits.uop.taken invalidate io.iresp.bits.fflags.bits.uop.pc_lob invalidate io.iresp.bits.fflags.bits.uop.edge_inst invalidate io.iresp.bits.fflags.bits.uop.ftq_idx invalidate io.iresp.bits.fflags.bits.uop.br_tag invalidate io.iresp.bits.fflags.bits.uop.br_mask invalidate io.iresp.bits.fflags.bits.uop.is_sfb invalidate io.iresp.bits.fflags.bits.uop.is_jal invalidate io.iresp.bits.fflags.bits.uop.is_jalr invalidate io.iresp.bits.fflags.bits.uop.is_br invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.fflags.bits.uop.iw_state invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type invalidate io.iresp.bits.fflags.bits.uop.fu_code invalidate io.iresp.bits.fflags.bits.uop.iq_type invalidate io.iresp.bits.fflags.bits.uop.debug_pc invalidate io.iresp.bits.fflags.bits.uop.is_rvc invalidate io.iresp.bits.fflags.bits.uop.debug_inst invalidate io.iresp.bits.fflags.bits.uop.inst invalidate io.iresp.bits.fflags.bits.uop.uopc invalidate io.iresp.bits.fflags.valid invalidate io.iresp.bits.predicated invalidate io.iresp.bits.data invalidate io.iresp.bits.uop.debug_tsrc invalidate io.iresp.bits.uop.debug_fsrc invalidate io.iresp.bits.uop.bp_xcpt_if invalidate io.iresp.bits.uop.bp_debug_if invalidate io.iresp.bits.uop.xcpt_ma_if invalidate io.iresp.bits.uop.xcpt_ae_if invalidate io.iresp.bits.uop.xcpt_pf_if invalidate io.iresp.bits.uop.fp_single invalidate io.iresp.bits.uop.fp_val invalidate io.iresp.bits.uop.frs3_en invalidate io.iresp.bits.uop.lrs2_rtype invalidate io.iresp.bits.uop.lrs1_rtype invalidate io.iresp.bits.uop.dst_rtype invalidate io.iresp.bits.uop.ldst_val invalidate io.iresp.bits.uop.lrs3 invalidate io.iresp.bits.uop.lrs2 invalidate io.iresp.bits.uop.lrs1 invalidate io.iresp.bits.uop.ldst invalidate io.iresp.bits.uop.ldst_is_rs1 invalidate io.iresp.bits.uop.flush_on_commit invalidate io.iresp.bits.uop.is_unique invalidate io.iresp.bits.uop.is_sys_pc2epc invalidate io.iresp.bits.uop.uses_stq invalidate io.iresp.bits.uop.uses_ldq invalidate io.iresp.bits.uop.is_amo invalidate io.iresp.bits.uop.is_fencei invalidate io.iresp.bits.uop.is_fence invalidate io.iresp.bits.uop.mem_signed invalidate io.iresp.bits.uop.mem_size invalidate io.iresp.bits.uop.mem_cmd invalidate io.iresp.bits.uop.bypassable invalidate io.iresp.bits.uop.exc_cause invalidate io.iresp.bits.uop.exception invalidate io.iresp.bits.uop.stale_pdst invalidate io.iresp.bits.uop.ppred_busy invalidate io.iresp.bits.uop.prs3_busy invalidate io.iresp.bits.uop.prs2_busy invalidate io.iresp.bits.uop.prs1_busy invalidate io.iresp.bits.uop.ppred invalidate io.iresp.bits.uop.prs3 invalidate io.iresp.bits.uop.prs2 invalidate io.iresp.bits.uop.prs1 invalidate io.iresp.bits.uop.pdst invalidate io.iresp.bits.uop.rxq_idx invalidate io.iresp.bits.uop.stq_idx invalidate io.iresp.bits.uop.ldq_idx invalidate io.iresp.bits.uop.rob_idx invalidate io.iresp.bits.uop.csr_addr invalidate io.iresp.bits.uop.imm_packed invalidate io.iresp.bits.uop.taken invalidate io.iresp.bits.uop.pc_lob invalidate io.iresp.bits.uop.edge_inst invalidate io.iresp.bits.uop.ftq_idx invalidate io.iresp.bits.uop.br_tag invalidate io.iresp.bits.uop.br_mask invalidate io.iresp.bits.uop.is_sfb invalidate io.iresp.bits.uop.is_jal invalidate io.iresp.bits.uop.is_jalr invalidate io.iresp.bits.uop.is_br invalidate io.iresp.bits.uop.iw_p2_poisoned invalidate io.iresp.bits.uop.iw_p1_poisoned invalidate io.iresp.bits.uop.iw_state invalidate io.iresp.bits.uop.ctrl.is_std invalidate io.iresp.bits.uop.ctrl.is_sta invalidate io.iresp.bits.uop.ctrl.is_load invalidate io.iresp.bits.uop.ctrl.csr_cmd invalidate io.iresp.bits.uop.ctrl.fcn_dw invalidate io.iresp.bits.uop.ctrl.op_fcn invalidate io.iresp.bits.uop.ctrl.imm_sel invalidate io.iresp.bits.uop.ctrl.op2_sel invalidate io.iresp.bits.uop.ctrl.op1_sel invalidate io.iresp.bits.uop.ctrl.br_type invalidate io.iresp.bits.uop.fu_code invalidate io.iresp.bits.uop.iq_type invalidate io.iresp.bits.uop.debug_pc invalidate io.iresp.bits.uop.is_rvc invalidate io.iresp.bits.uop.debug_inst invalidate io.iresp.bits.uop.inst invalidate io.iresp.bits.uop.uopc connect io.iresp.bits.fflags.valid, UInt<1>(0h0) connect io.iresp.bits.predicated, UInt<1>(0h0) node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : node _T_2 = eq(io.iresp.ready, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert wire div_busy : UInt<1> connect div_busy, UInt<1>(0h0) wire ifpu_busy : UInt<1> connect ifpu_busy, UInt<1>(0h0) node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0)) node _io_fu_types_T_1 = mux(UInt<1>(0h1), UInt<10>(0h8), UInt<1>(0h0)) node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1) node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0)) node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h0)) node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0)) node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5) node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0)) node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7) node _io_fu_types_T_9 = mux(UInt<1>(0h0), UInt<10>(0h2), UInt<1>(0h0)) node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9) node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0)) node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0)) node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0)) node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13) node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0)) node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15) connect io.fu_types, _io_fu_types_T_16 inst ALUUnit of ALUUnit_2 connect ALUUnit.clock, clock connect ALUUnit.reset, reset node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1)) node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20)) node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c)) node _T_8 = and(_T_6, _T_7) node _T_9 = or(_T_5, _T_8) node _T_10 = and(io.req.valid, _T_9) connect ALUUnit.io.req.valid, _T_10 connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect ALUUnit.io.req.bits.kill, io.req.bits.kill connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data invalidate ALUUnit.io.req.bits.rs3_data connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data invalidate ALUUnit.io.resp.ready connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect io.bypass, ALUUnit.io.bypass connect io.brinfo, ALUUnit.io.brinfo inst PipelinedMulUnit of PipelinedMulUnit connect PipelinedMulUnit.clock, clock connect PipelinedMulUnit.reset, reset invalidate PipelinedMulUnit.io.brupdate.b2.target_offset invalidate PipelinedMulUnit.io.brupdate.b2.jalr_target invalidate PipelinedMulUnit.io.brupdate.b2.pc_sel invalidate PipelinedMulUnit.io.brupdate.b2.cfi_type invalidate PipelinedMulUnit.io.brupdate.b2.taken invalidate PipelinedMulUnit.io.brupdate.b2.mispredict invalidate PipelinedMulUnit.io.brupdate.b2.valid invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_single invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_val invalidate PipelinedMulUnit.io.brupdate.b2.uop.frs3_en invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype invalidate PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_val invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs3 invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2 invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1 invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1 invalidate PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_unique invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_stq invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_amo invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fencei invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fence invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_signed invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_size invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd invalidate PipelinedMulUnit.io.brupdate.b2.uop.bypassable invalidate PipelinedMulUnit.io.brupdate.b2.uop.exc_cause invalidate PipelinedMulUnit.io.brupdate.b2.uop.exception invalidate PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3 invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2 invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1 invalidate PipelinedMulUnit.io.brupdate.b2.uop.pdst invalidate PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx invalidate PipelinedMulUnit.io.brupdate.b2.uop.stq_idx invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx invalidate PipelinedMulUnit.io.brupdate.b2.uop.rob_idx invalidate PipelinedMulUnit.io.brupdate.b2.uop.csr_addr invalidate PipelinedMulUnit.io.brupdate.b2.uop.imm_packed invalidate PipelinedMulUnit.io.brupdate.b2.uop.taken invalidate PipelinedMulUnit.io.brupdate.b2.uop.pc_lob invalidate PipelinedMulUnit.io.brupdate.b2.uop.edge_inst invalidate PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_tag invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_mask invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sfb invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jal invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jalr invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_br invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_state invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type invalidate PipelinedMulUnit.io.brupdate.b2.uop.fu_code invalidate PipelinedMulUnit.io.brupdate.b2.uop.iq_type invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_pc invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_rvc invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_inst invalidate PipelinedMulUnit.io.brupdate.b2.uop.inst invalidate PipelinedMulUnit.io.brupdate.b2.uop.uopc invalidate PipelinedMulUnit.io.brupdate.b1.mispredict_mask invalidate PipelinedMulUnit.io.brupdate.b1.resolve_mask invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hg invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hv invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.asid invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.addr invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs2 invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs1 invalidate PipelinedMulUnit.io.resp.bits.sfence.valid invalidate PipelinedMulUnit.io.resp.bits.mxcpt.bits invalidate PipelinedMulUnit.io.resp.bits.mxcpt.valid invalidate PipelinedMulUnit.io.resp.bits.addr invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.flags invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_tsrc invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_fsrc invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_debug_if invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_single invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_val invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.frs3_en invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.dst_rtype invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_val invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs3 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.flush_on_commit invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_unique invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_stq invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_ldq invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_amo invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fencei invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fence invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_signed invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_size invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_cmd invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bypassable invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exc_cause invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exception invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stale_pdst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred_busy invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3_busy invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2_busy invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1_busy invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1 invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pdst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rxq_idx invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stq_idx invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldq_idx invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rob_idx invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.csr_addr invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.imm_packed invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.taken invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pc_lob invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.edge_inst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ftq_idx invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_tag invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_mask invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sfb invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jal invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jalr invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_br invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_state invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fu_code invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iq_type invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_pc invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_rvc invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_inst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.inst invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uopc invalidate PipelinedMulUnit.io.resp.bits.fflags.valid invalidate PipelinedMulUnit.io.resp.bits.data invalidate PipelinedMulUnit.io.resp.bits.predicated invalidate PipelinedMulUnit.io.resp.bits.uop.debug_tsrc invalidate PipelinedMulUnit.io.resp.bits.uop.debug_fsrc invalidate PipelinedMulUnit.io.resp.bits.uop.bp_xcpt_if invalidate PipelinedMulUnit.io.resp.bits.uop.bp_debug_if invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ma_if invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ae_if invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_pf_if invalidate PipelinedMulUnit.io.resp.bits.uop.fp_single invalidate PipelinedMulUnit.io.resp.bits.uop.fp_val invalidate PipelinedMulUnit.io.resp.bits.uop.frs3_en invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2_rtype invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1_rtype invalidate PipelinedMulUnit.io.resp.bits.uop.dst_rtype invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_val invalidate PipelinedMulUnit.io.resp.bits.uop.lrs3 invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2 invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1 invalidate PipelinedMulUnit.io.resp.bits.uop.ldst invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_is_rs1 invalidate PipelinedMulUnit.io.resp.bits.uop.flush_on_commit invalidate PipelinedMulUnit.io.resp.bits.uop.is_unique invalidate PipelinedMulUnit.io.resp.bits.uop.is_sys_pc2epc invalidate PipelinedMulUnit.io.resp.bits.uop.uses_stq invalidate PipelinedMulUnit.io.resp.bits.uop.uses_ldq invalidate PipelinedMulUnit.io.resp.bits.uop.is_amo invalidate PipelinedMulUnit.io.resp.bits.uop.is_fencei invalidate PipelinedMulUnit.io.resp.bits.uop.is_fence invalidate PipelinedMulUnit.io.resp.bits.uop.mem_signed invalidate PipelinedMulUnit.io.resp.bits.uop.mem_size invalidate PipelinedMulUnit.io.resp.bits.uop.mem_cmd invalidate PipelinedMulUnit.io.resp.bits.uop.bypassable invalidate PipelinedMulUnit.io.resp.bits.uop.exc_cause invalidate PipelinedMulUnit.io.resp.bits.uop.exception invalidate PipelinedMulUnit.io.resp.bits.uop.stale_pdst invalidate PipelinedMulUnit.io.resp.bits.uop.ppred_busy invalidate PipelinedMulUnit.io.resp.bits.uop.prs3_busy invalidate PipelinedMulUnit.io.resp.bits.uop.prs2_busy invalidate PipelinedMulUnit.io.resp.bits.uop.prs1_busy invalidate PipelinedMulUnit.io.resp.bits.uop.ppred invalidate PipelinedMulUnit.io.resp.bits.uop.prs3 invalidate PipelinedMulUnit.io.resp.bits.uop.prs2 invalidate PipelinedMulUnit.io.resp.bits.uop.prs1 invalidate PipelinedMulUnit.io.resp.bits.uop.pdst invalidate PipelinedMulUnit.io.resp.bits.uop.rxq_idx invalidate PipelinedMulUnit.io.resp.bits.uop.stq_idx invalidate PipelinedMulUnit.io.resp.bits.uop.ldq_idx invalidate PipelinedMulUnit.io.resp.bits.uop.rob_idx invalidate PipelinedMulUnit.io.resp.bits.uop.csr_addr invalidate PipelinedMulUnit.io.resp.bits.uop.imm_packed invalidate PipelinedMulUnit.io.resp.bits.uop.taken invalidate PipelinedMulUnit.io.resp.bits.uop.pc_lob invalidate PipelinedMulUnit.io.resp.bits.uop.edge_inst invalidate PipelinedMulUnit.io.resp.bits.uop.ftq_idx invalidate PipelinedMulUnit.io.resp.bits.uop.br_tag invalidate PipelinedMulUnit.io.resp.bits.uop.br_mask invalidate PipelinedMulUnit.io.resp.bits.uop.is_sfb invalidate PipelinedMulUnit.io.resp.bits.uop.is_jal invalidate PipelinedMulUnit.io.resp.bits.uop.is_jalr invalidate PipelinedMulUnit.io.resp.bits.uop.is_br invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p2_poisoned invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p1_poisoned invalidate PipelinedMulUnit.io.resp.bits.uop.iw_state invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_std invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_sta invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_load invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.csr_cmd invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.fcn_dw invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op_fcn invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.imm_sel invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op2_sel invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op1_sel invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.br_type invalidate PipelinedMulUnit.io.resp.bits.uop.fu_code invalidate PipelinedMulUnit.io.resp.bits.uop.iq_type invalidate PipelinedMulUnit.io.resp.bits.uop.debug_pc invalidate PipelinedMulUnit.io.resp.bits.uop.is_rvc invalidate PipelinedMulUnit.io.resp.bits.uop.debug_inst invalidate PipelinedMulUnit.io.resp.bits.uop.inst invalidate PipelinedMulUnit.io.resp.bits.uop.uopc invalidate PipelinedMulUnit.io.resp.valid invalidate PipelinedMulUnit.io.resp.ready invalidate PipelinedMulUnit.io.req.bits.kill invalidate PipelinedMulUnit.io.req.bits.pred_data invalidate PipelinedMulUnit.io.req.bits.rs3_data invalidate PipelinedMulUnit.io.req.bits.rs2_data invalidate PipelinedMulUnit.io.req.bits.rs1_data invalidate PipelinedMulUnit.io.req.bits.uop.debug_tsrc invalidate PipelinedMulUnit.io.req.bits.uop.debug_fsrc invalidate PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if invalidate PipelinedMulUnit.io.req.bits.uop.bp_debug_if invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if invalidate PipelinedMulUnit.io.req.bits.uop.fp_single invalidate PipelinedMulUnit.io.req.bits.uop.fp_val invalidate PipelinedMulUnit.io.req.bits.uop.frs3_en invalidate PipelinedMulUnit.io.req.bits.uop.lrs2_rtype invalidate PipelinedMulUnit.io.req.bits.uop.lrs1_rtype invalidate PipelinedMulUnit.io.req.bits.uop.dst_rtype invalidate PipelinedMulUnit.io.req.bits.uop.ldst_val invalidate PipelinedMulUnit.io.req.bits.uop.lrs3 invalidate PipelinedMulUnit.io.req.bits.uop.lrs2 invalidate PipelinedMulUnit.io.req.bits.uop.lrs1 invalidate PipelinedMulUnit.io.req.bits.uop.ldst invalidate PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1 invalidate PipelinedMulUnit.io.req.bits.uop.flush_on_commit invalidate PipelinedMulUnit.io.req.bits.uop.is_unique invalidate PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc invalidate PipelinedMulUnit.io.req.bits.uop.uses_stq invalidate PipelinedMulUnit.io.req.bits.uop.uses_ldq invalidate PipelinedMulUnit.io.req.bits.uop.is_amo invalidate PipelinedMulUnit.io.req.bits.uop.is_fencei invalidate PipelinedMulUnit.io.req.bits.uop.is_fence invalidate PipelinedMulUnit.io.req.bits.uop.mem_signed invalidate PipelinedMulUnit.io.req.bits.uop.mem_size invalidate PipelinedMulUnit.io.req.bits.uop.mem_cmd invalidate PipelinedMulUnit.io.req.bits.uop.bypassable invalidate PipelinedMulUnit.io.req.bits.uop.exc_cause invalidate PipelinedMulUnit.io.req.bits.uop.exception invalidate PipelinedMulUnit.io.req.bits.uop.stale_pdst invalidate PipelinedMulUnit.io.req.bits.uop.ppred_busy invalidate PipelinedMulUnit.io.req.bits.uop.prs3_busy invalidate PipelinedMulUnit.io.req.bits.uop.prs2_busy invalidate PipelinedMulUnit.io.req.bits.uop.prs1_busy invalidate PipelinedMulUnit.io.req.bits.uop.ppred invalidate PipelinedMulUnit.io.req.bits.uop.prs3 invalidate PipelinedMulUnit.io.req.bits.uop.prs2 invalidate PipelinedMulUnit.io.req.bits.uop.prs1 invalidate PipelinedMulUnit.io.req.bits.uop.pdst invalidate PipelinedMulUnit.io.req.bits.uop.rxq_idx invalidate PipelinedMulUnit.io.req.bits.uop.stq_idx invalidate PipelinedMulUnit.io.req.bits.uop.ldq_idx invalidate PipelinedMulUnit.io.req.bits.uop.rob_idx invalidate PipelinedMulUnit.io.req.bits.uop.csr_addr invalidate PipelinedMulUnit.io.req.bits.uop.imm_packed invalidate PipelinedMulUnit.io.req.bits.uop.taken invalidate PipelinedMulUnit.io.req.bits.uop.pc_lob invalidate PipelinedMulUnit.io.req.bits.uop.edge_inst invalidate PipelinedMulUnit.io.req.bits.uop.ftq_idx invalidate PipelinedMulUnit.io.req.bits.uop.br_tag invalidate PipelinedMulUnit.io.req.bits.uop.br_mask invalidate PipelinedMulUnit.io.req.bits.uop.is_sfb invalidate PipelinedMulUnit.io.req.bits.uop.is_jal invalidate PipelinedMulUnit.io.req.bits.uop.is_jalr invalidate PipelinedMulUnit.io.req.bits.uop.is_br invalidate PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned invalidate PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned invalidate PipelinedMulUnit.io.req.bits.uop.iw_state invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_std invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_load invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.br_type invalidate PipelinedMulUnit.io.req.bits.uop.fu_code invalidate PipelinedMulUnit.io.req.bits.uop.iq_type invalidate PipelinedMulUnit.io.req.bits.uop.debug_pc invalidate PipelinedMulUnit.io.req.bits.uop.is_rvc invalidate PipelinedMulUnit.io.req.bits.uop.debug_inst invalidate PipelinedMulUnit.io.req.bits.uop.inst invalidate PipelinedMulUnit.io.req.bits.uop.uopc invalidate PipelinedMulUnit.io.req.valid invalidate PipelinedMulUnit.io.req.ready node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h8)) node _T_12 = neq(_T_11, UInt<1>(0h0)) node _T_13 = and(io.req.valid, _T_12) connect PipelinedMulUnit.io.req.valid, _T_13 connect PipelinedMulUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc connect PipelinedMulUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc connect PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if connect PipelinedMulUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if connect PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if connect PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if connect PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if connect PipelinedMulUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single connect PipelinedMulUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val connect PipelinedMulUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en connect PipelinedMulUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype connect PipelinedMulUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype connect PipelinedMulUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype connect PipelinedMulUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val connect PipelinedMulUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3 connect PipelinedMulUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2 connect PipelinedMulUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1 connect PipelinedMulUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst connect PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1 connect PipelinedMulUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit connect PipelinedMulUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique connect PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc connect PipelinedMulUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq connect PipelinedMulUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq connect PipelinedMulUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo connect PipelinedMulUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei connect PipelinedMulUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence connect PipelinedMulUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed connect PipelinedMulUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size connect PipelinedMulUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd connect PipelinedMulUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable connect PipelinedMulUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause connect PipelinedMulUnit.io.req.bits.uop.exception, io.req.bits.uop.exception connect PipelinedMulUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst connect PipelinedMulUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy connect PipelinedMulUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy connect PipelinedMulUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy connect PipelinedMulUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy connect PipelinedMulUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred connect PipelinedMulUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3 connect PipelinedMulUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2 connect PipelinedMulUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1 connect PipelinedMulUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst connect PipelinedMulUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx connect PipelinedMulUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx connect PipelinedMulUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx connect PipelinedMulUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx connect PipelinedMulUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr connect PipelinedMulUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed connect PipelinedMulUnit.io.req.bits.uop.taken, io.req.bits.uop.taken connect PipelinedMulUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob connect PipelinedMulUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst connect PipelinedMulUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx connect PipelinedMulUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag connect PipelinedMulUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask connect PipelinedMulUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb connect PipelinedMulUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal connect PipelinedMulUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr connect PipelinedMulUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br connect PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned connect PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned connect PipelinedMulUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load connect PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd connect PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw connect PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn connect PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel connect PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel connect PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel connect PipelinedMulUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type connect PipelinedMulUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code connect PipelinedMulUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type connect PipelinedMulUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc connect PipelinedMulUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc connect PipelinedMulUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst connect PipelinedMulUnit.io.req.bits.uop.inst, io.req.bits.uop.inst connect PipelinedMulUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc connect PipelinedMulUnit.io.req.bits.rs1_data, io.req.bits.rs1_data connect PipelinedMulUnit.io.req.bits.rs2_data, io.req.bits.rs2_data connect PipelinedMulUnit.io.req.bits.kill, io.req.bits.kill connect PipelinedMulUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect PipelinedMulUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect PipelinedMulUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect PipelinedMulUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect PipelinedMulUnit.io.brupdate.b2.taken, io.brupdate.b2.taken connect PipelinedMulUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect PipelinedMulUnit.io.brupdate.b2.valid, io.brupdate.b2.valid connect PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect PipelinedMulUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect PipelinedMulUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect PipelinedMulUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect PipelinedMulUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect PipelinedMulUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect PipelinedMulUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect PipelinedMulUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect PipelinedMulUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect PipelinedMulUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect PipelinedMulUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect PipelinedMulUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect PipelinedMulUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect PipelinedMulUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect PipelinedMulUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect PipelinedMulUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect PipelinedMulUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect PipelinedMulUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect PipelinedMulUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect PipelinedMulUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect PipelinedMulUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect PipelinedMulUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect PipelinedMulUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect PipelinedMulUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect PipelinedMulUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect PipelinedMulUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect PipelinedMulUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect PipelinedMulUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect PipelinedMulUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect PipelinedMulUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect PipelinedMulUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect PipelinedMulUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect PipelinedMulUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect PipelinedMulUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect PipelinedMulUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect PipelinedMulUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect PipelinedMulUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect PipelinedMulUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect PipelinedMulUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect PipelinedMulUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect PipelinedMulUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect PipelinedMulUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect PipelinedMulUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect PipelinedMulUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask wire div_resp_val : UInt<1> connect div_resp_val, UInt<1>(0h0) node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid) connect io.iresp.valid, _io_iresp_valid_T node _io_iresp_bits_uop_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, PipelinedMulUnit.io.resp.bits.uop) connect io.iresp.bits.uop, _io_iresp_bits_uop_T node _io_iresp_bits_data_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, PipelinedMulUnit.io.resp.bits.data) connect io.iresp.bits.data, _io_iresp_bits_data_T node _io_iresp_bits_predicated_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, PipelinedMulUnit.io.resp.bits.predicated) connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19) node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T) node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8) node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1) node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1) node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0) node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3) node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign) node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4)) node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2)) node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2) node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4) node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6) node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14) node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1) node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2) node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3)) node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9) node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1) node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2) node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1)) node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0)) node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1) node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8) node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3) node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0))) node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0) node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1) node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5) node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo) node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo) node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11) node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12) node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo) node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20) node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign) node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo) node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo) node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo) node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T) node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1) connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2 connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd node _T_14 = add(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid) node _T_15 = bits(_T_14, 1, 0) node _T_16 = leq(_T_15, UInt<1>(0h1)) node _T_17 = eq(div_resp_val, UInt<1>(0h0)) node _T_18 = and(_T_16, _T_17) node _T_19 = add(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid) node _T_20 = bits(_T_19, 1, 0) node _T_21 = leq(_T_20, UInt<2>(0h2)) node _T_22 = and(_T_21, div_resp_val) node _T_23 = or(_T_18, _T_22) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
module ALUExeUnit_3( // @[execution-unit.scala:204:7] input clock, // @[execution-unit.scala:204:7] input reset, // @[execution-unit.scala:204:7] input io_req_valid, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14] input io_req_bits_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_req_bits_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14] input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14] input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14] input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14] input io_req_bits_kill, // @[execution-unit.scala:104:14] output io_iresp_valid, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14] output io_bypass_0_valid, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14] output io_bypass_1_valid, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_bypass_1_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_bypass_1_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_bypass_1_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_bypass_1_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_bypass_1_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_bypass_1_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_bypass_1_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_1_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_bypass_1_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_bypass_1_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_bypass_1_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_bypass_1_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_1_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_1_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_1_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_bypass_1_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_bypass_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_bypass_1_bits_data, // @[execution-unit.scala:104:14] output io_bypass_2_valid, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_bypass_2_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_bypass_2_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_bypass_2_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_bypass_2_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_bypass_2_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_bypass_2_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_bypass_2_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_2_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_bypass_2_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_bypass_2_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_bypass_2_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_bypass_2_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_2_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_bypass_2_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_bypass_2_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_bypass_2_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_bypass_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_bypass_2_bits_data, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14] input io_brupdate_b2_valid, // @[execution-unit.scala:104:14] input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14] input io_brupdate_b2_taken, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14] output [15:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14] output [3:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14] output io_brinfo_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14] output [6:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_brinfo_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14] output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14] output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14] output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14] output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14] output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14] output io_brinfo_valid, // @[execution-unit.scala:104:14] output io_brinfo_mispredict, // @[execution-unit.scala:104:14] output io_brinfo_taken, // @[execution-unit.scala:104:14] output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14] output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14] output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14] input io_status_debug, // @[execution-unit.scala:104:14] input io_status_cease, // @[execution-unit.scala:104:14] input io_status_wfi, // @[execution-unit.scala:104:14] input [1:0] io_status_dprv, // @[execution-unit.scala:104:14] input io_status_dv, // @[execution-unit.scala:104:14] input [1:0] io_status_prv, // @[execution-unit.scala:104:14] input io_status_v, // @[execution-unit.scala:104:14] input io_status_sd, // @[execution-unit.scala:104:14] input io_status_mpv, // @[execution-unit.scala:104:14] input io_status_gva, // @[execution-unit.scala:104:14] input io_status_tsr, // @[execution-unit.scala:104:14] input io_status_tw, // @[execution-unit.scala:104:14] input io_status_tvm, // @[execution-unit.scala:104:14] input io_status_mxr, // @[execution-unit.scala:104:14] input io_status_sum, // @[execution-unit.scala:104:14] input io_status_mprv, // @[execution-unit.scala:104:14] input [1:0] io_status_fs, // @[execution-unit.scala:104:14] input [1:0] io_status_mpp, // @[execution-unit.scala:104:14] input io_status_spp, // @[execution-unit.scala:104:14] input io_status_mpie, // @[execution-unit.scala:104:14] input io_status_spie, // @[execution-unit.scala:104:14] input io_status_mie, // @[execution-unit.scala:104:14] input io_status_sie // @[execution-unit.scala:104:14] ); wire _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:326:18] wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:326:18] wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:326:18] wire [39:0] _PipelinedMulUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:326:18] wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:326:18] wire [9:0] _PipelinedMulUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:326:18] wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:326:18] wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:326:18] wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:326:18] wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:326:18] wire [15:0] _PipelinedMulUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:326:18] wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:326:18] wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:326:18] wire [19:0] _PipelinedMulUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:326:18] wire [11:0] _PipelinedMulUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:326:18] wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:326:18] wire [63:0] _PipelinedMulUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:326:18] wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:326:18] wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:326:18] wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:326:18] wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:326:18] wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:326:18] wire _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:326:18] wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:326:18] wire [63:0] _PipelinedMulUnit_io_resp_bits_data; // @[execution-unit.scala:326:18] wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17] wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17] wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17] wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17] wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17] wire [15:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17] wire [3:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17] wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17] wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17] wire [6:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17] wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17] wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17] wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17] wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_bypass_1_bits_data; // @[execution-unit.scala:271:17] wire [63:0] _ALUUnit_io_bypass_2_bits_data; // @[execution-unit.scala:271:17] wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7] wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7] wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7] wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7] wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7] wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7] wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7] wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7] wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7] wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7] wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7] wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7] wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7] wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7] wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7] wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7] wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7] wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7] wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7] wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7] wire io_req_ready = 1'h0; // @[execution-unit.scala:204:7] wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_predicated = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7] wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7] wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7] wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7] wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7] wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7] wire div_busy = 1'h0; // @[execution-unit.scala:253:27] wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27] wire _io_fu_types_T_4 = 1'h0; // @[execution-unit.scala:262:32] wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33] wire div_resp_val = 1'h0; // @[execution-unit.scala:364:30] wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27] wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44] wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36] wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27] wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27] wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44] wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36] wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27] wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27] wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27] wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7] wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7] wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7] wire [9:0] io_fu_types = 10'h9; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_2 = 10'h9; // @[execution-unit.scala:260:45] wire [9:0] _io_fu_types_T_6 = 10'h9; // @[execution-unit.scala:261:45] wire [9:0] _io_fu_types_T_8 = 10'h9; // @[execution-unit.scala:262:58] wire [9:0] _io_fu_types_T_10 = 10'h9; // @[execution-unit.scala:263:45] wire [9:0] _io_fu_types_T_14 = 10'h9; // @[execution-unit.scala:264:49] wire [9:0] _io_fu_types_T_16 = 10'h9; // @[execution-unit.scala:265:60] wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7] wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7] wire _io_fu_types_T_3 = 1'h1; // @[execution-unit.scala:262:22] wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:265:22] wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44] wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36] wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_jalr_target = 40'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_5 = 10'h0; // @[execution-unit.scala:262:21] wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21] wire [9:0] _io_fu_types_T_9 = 10'h0; // @[execution-unit.scala:264:21] wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21] wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21] wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7] wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7] wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7] wire [9:0] _io_fu_types_T_1 = 10'h8; // @[execution-unit.scala:261:21] wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21] wire _io_iresp_valid_T; // @[execution-unit.scala:409:71] wire [6:0] _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] wire [31:0] _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] wire [39:0] _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] wire [9:0] _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] wire [15:0] _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] wire [3:0] _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] wire [19:0] _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] wire [6:0] _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] wire [4:0] _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] wire [5:0] _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] wire [1:0] _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7] wire io_iresp_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7] wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_1_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_1_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_1_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_1_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_bypass_1_bits_data_0; // @[execution-unit.scala:204:7] wire io_bypass_1_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_2_bits_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_bypass_2_bits_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_bypass_2_bits_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_bypass_2_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire [64:0] io_bypass_2_bits_data_0; // @[execution-unit.scala:204:7] wire io_bypass_2_valid_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7] wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7] wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7] wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7] wire [15:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7] wire [3:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7] wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7] wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7] wire [6:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7] wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7] wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7] wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7] wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7] wire io_brinfo_valid_0; // @[execution-unit.scala:204:7] wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7] wire io_brinfo_taken_0; // @[execution-unit.scala:204:7] wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7] wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7] wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7] assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15] assign io_bypass_1_bits_data_0 = {1'h0, _ALUUnit_io_bypass_1_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15] assign io_bypass_2_bits_data_0 = {1'h0, _ALUUnit_io_bypass_2_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15] assign _io_iresp_valid_T = _ALUUnit_io_resp_valid | _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:271:17, :326:18, :409:71] assign io_iresp_valid_0 = _io_iresp_valid_T; // @[execution-unit.scala:204:7, :409:71] assign _io_iresp_bits_uop_T_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _PipelinedMulUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _PipelinedMulUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _PipelinedMulUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _PipelinedMulUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _PipelinedMulUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _PipelinedMulUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _PipelinedMulUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70] wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _PipelinedMulUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _PipelinedMulUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _PipelinedMulUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _PipelinedMulUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _PipelinedMulUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _PipelinedMulUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _PipelinedMulUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _PipelinedMulUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _PipelinedMulUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _PipelinedMulUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _PipelinedMulUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _PipelinedMulUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70] wire [11:0] _io_iresp_bits_uop_T_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _PipelinedMulUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _PipelinedMulUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _PipelinedMulUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _PipelinedMulUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _PipelinedMulUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _PipelinedMulUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _PipelinedMulUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _PipelinedMulUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _PipelinedMulUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _PipelinedMulUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _PipelinedMulUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _PipelinedMulUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _PipelinedMulUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _PipelinedMulUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _PipelinedMulUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _PipelinedMulUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _PipelinedMulUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _PipelinedMulUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _PipelinedMulUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _PipelinedMulUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _PipelinedMulUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _PipelinedMulUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _PipelinedMulUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _PipelinedMulUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _PipelinedMulUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _PipelinedMulUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _PipelinedMulUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _PipelinedMulUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _PipelinedMulUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _PipelinedMulUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _PipelinedMulUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _PipelinedMulUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _PipelinedMulUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _PipelinedMulUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _PipelinedMulUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _PipelinedMulUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70] assign _io_iresp_bits_uop_T_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70] assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70] assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [63:0] _io_iresp_bits_data_T = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _PipelinedMulUnit_io_resp_bits_data; // @[Mux.scala:50:70] assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T}; // @[Mux.scala:50:70] wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18] wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}] wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21] wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39] wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}] wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21] wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56] wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}] wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21] wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56] wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56] wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}] wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21] wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}] wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44] wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}] wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}] wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15] wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}] wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}] wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15] wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15] wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15] wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15] wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15] wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15] wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}] wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60] assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_129 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_146 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_129( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_146 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FrontBus : output auto : { flip coupler_from_port_named_serial_tl_0_in_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_debug_sb_widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip fbus_clock_groups_in : { member : { fbus_0 : { clock : Clock, reset : Reset}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst fbus_clock_groups of ClockGroupAggregator_fbus inst clockGroup of ClockGroup_2 inst fixedClockNode of FixedClockBroadcast_2_1 inst broadcast of BundleBridgeNexus_NoOutput_2 inst fbus_xbar of TLXbar_fbus_i2_o1_a32d64s5k4z4u connect fbus_xbar.clock, childClock connect fbus_xbar.reset, childReset inst buffer of TLBuffer_a32d64s5k4z4u connect buffer.clock, childClock connect buffer.reset, childReset inst coupler_from_debug_sb of TLInterconnectCoupler_fbus_from_debug_sb connect coupler_from_debug_sb.clock, childClock connect coupler_from_debug_sb.reset, childReset inst coupler_from_port_named_serial_tl_0_in of TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in connect coupler_from_port_named_serial_tl_0_in.clock, childClock connect coupler_from_port_named_serial_tl_0_in.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect clockGroup.auto.in, fbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect buffer.auto.in, fbus_xbar.auto.anon_out connect buffer.auto.out.d, bus_xingIn.d connect bus_xingIn.a.bits, buffer.auto.out.a.bits connect bus_xingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, bus_xingIn.a.ready connect fbus_xbar.auto.anon_in_0, coupler_from_debug_sb.auto.tl_out connect fbus_xbar.auto.anon_in_1, coupler_from_port_named_serial_tl_0_in.auto.tl_out connect auto.bus_xing_out, bus_xingOut connect fbus_clock_groups.auto.in, auto.fbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_from_debug_sb.auto.widget_anon_in, auto.coupler_from_debug_sb_widget_anon_in connect coupler_from_port_named_serial_tl_0_in.auto.buffer_in, auto.coupler_from_port_named_serial_tl_0_in_buffer_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset
module FrontBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_debug_sb_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_fbus_clock_groups_in_member_fbus_0_reset, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire fbus_clock_groups_auto_out_member_fbus_0_reset; // @[ClockGroup.scala:53:9] wire fbus_clock_groups_auto_out_member_fbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_from_debug_sb_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [3:0] _coupler_from_debug_sb_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [31:0] _coupler_from_debug_sb_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_from_debug_sb_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_from_debug_sb_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_from_debug_sb_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [4:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _fbus_xbar_auto_anon_in_1_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_1_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_1_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_size; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_source; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_1_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_1_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_1_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_a_ready; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_in_0_d_bits_opcode; // @[BusWrapper.scala:240:32] wire [1:0] _fbus_xbar_auto_anon_in_0_d_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_0_d_bits_size; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_in_0_d_bits_sink; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_denied; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_in_0_d_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_in_0_d_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_valid; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_opcode; // @[BusWrapper.scala:240:32] wire [2:0] _fbus_xbar_auto_anon_out_a_bits_param; // @[BusWrapper.scala:240:32] wire [3:0] _fbus_xbar_auto_anon_out_a_bits_size; // @[BusWrapper.scala:240:32] wire [4:0] _fbus_xbar_auto_anon_out_a_bits_source; // @[BusWrapper.scala:240:32] wire [31:0] _fbus_xbar_auto_anon_out_a_bits_address; // @[BusWrapper.scala:240:32] wire [7:0] _fbus_xbar_auto_anon_out_a_bits_mask; // @[BusWrapper.scala:240:32] wire [63:0] _fbus_xbar_auto_anon_out_a_bits_data; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_a_bits_corrupt; // @[BusWrapper.scala:240:32] wire _fbus_xbar_auto_anon_out_d_ready; // @[BusWrapper.scala:240:32] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready_0 = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_a_valid_0 = auto_coupler_from_debug_sb_widget_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode_0 = auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_size_0 = auto_coupler_from_debug_sb_widget_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_address_0 = auto_coupler_from_debug_sb_widget_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_data_0 = auto_coupler_from_debug_sb_widget_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_d_ready_0 = auto_coupler_from_debug_sb_widget_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_fbus_clock_groups_in_member_fbus_0_clock_0 = auto_fbus_clock_groups_in_member_fbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_fbus_clock_groups_in_member_fbus_0_reset_0 = auto_fbus_clock_groups_in_member_fbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_debug_sb_widget_anon_in_a_bits_param = 3'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_a_bits_mask = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_a_bits_source = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_d_bits_source = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire fbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire fbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fbus_clock_groups_auto_in_member_fbus_0_clock = auto_fbus_clock_groups_in_member_fbus_0_clock_0; // @[ClockGroup.scala:53:9] wire fbus_clock_groups_auto_in_member_fbus_0_reset = auto_fbus_clock_groups_in_member_fbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_debug_sb_widget_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_debug_sb_widget_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire fbus_clock_groups_nodeIn_member_fbus_0_clock = fbus_clock_groups_auto_in_member_fbus_0_clock; // @[ClockGroup.scala:53:9] wire fbus_clock_groups_nodeOut_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire fbus_clock_groups_nodeIn_member_fbus_0_reset = fbus_clock_groups_auto_in_member_fbus_0_reset; // @[ClockGroup.scala:53:9] wire fbus_clock_groups_nodeOut_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_fbus_0_clock = fbus_clock_groups_auto_out_member_fbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_fbus_0_reset = fbus_clock_groups_auto_out_member_fbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign fbus_clock_groups_auto_out_member_fbus_0_clock = fbus_clock_groups_nodeOut_member_fbus_0_clock; // @[ClockGroup.scala:53:9] assign fbus_clock_groups_auto_out_member_fbus_0_reset = fbus_clock_groups_nodeOut_member_fbus_0_reset; // @[ClockGroup.scala:53:9] assign fbus_clock_groups_nodeOut_member_fbus_0_clock = fbus_clock_groups_nodeIn_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign fbus_clock_groups_nodeOut_member_fbus_0_reset = fbus_clock_groups_nodeIn_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_fbus_0_clock = clockGroup_auto_in_member_fbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_fbus_0_reset = clockGroup_auto_in_member_fbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] FixedClockBroadcast_2_1 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_fbus_i2_o1_a32d64s5k4z4u fbus_xbar ( // @[BusWrapper.scala:240:32] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_1_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_1_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), .auto_anon_in_0_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_anon_in_0_a_bits_corrupt (_coupler_from_debug_sb_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_anon_in_0_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), .auto_anon_in_0_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt), .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_fbus_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fbus_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[BusWrapper.scala:240:32] TLBuffer_a32d64s5k4z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_fbus_xbar_auto_anon_out_a_valid), // @[BusWrapper.scala:240:32] .auto_in_a_bits_opcode (_fbus_xbar_auto_anon_out_a_bits_opcode), // @[BusWrapper.scala:240:32] .auto_in_a_bits_param (_fbus_xbar_auto_anon_out_a_bits_param), // @[BusWrapper.scala:240:32] .auto_in_a_bits_size (_fbus_xbar_auto_anon_out_a_bits_size), // @[BusWrapper.scala:240:32] .auto_in_a_bits_source (_fbus_xbar_auto_anon_out_a_bits_source), // @[BusWrapper.scala:240:32] .auto_in_a_bits_address (_fbus_xbar_auto_anon_out_a_bits_address), // @[BusWrapper.scala:240:32] .auto_in_a_bits_mask (_fbus_xbar_auto_anon_out_a_bits_mask), // @[BusWrapper.scala:240:32] .auto_in_a_bits_data (_fbus_xbar_auto_anon_out_a_bits_data), // @[BusWrapper.scala:240:32] .auto_in_a_bits_corrupt (_fbus_xbar_auto_anon_out_a_bits_corrupt), // @[BusWrapper.scala:240:32] .auto_in_d_ready (_fbus_xbar_auto_anon_out_d_ready), // @[BusWrapper.scala:240:32] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (bus_xingIn_a_valid), .auto_out_a_bits_opcode (bus_xingIn_a_bits_opcode), .auto_out_a_bits_param (bus_xingIn_a_bits_param), .auto_out_a_bits_size (bus_xingIn_a_bits_size), .auto_out_a_bits_source (bus_xingIn_a_bits_source), .auto_out_a_bits_address (bus_xingIn_a_bits_address), .auto_out_a_bits_mask (bus_xingIn_a_bits_mask), .auto_out_a_bits_data (bus_xingIn_a_bits_data), .auto_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt), .auto_out_d_ready (bus_xingIn_d_ready), .auto_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Buffer.scala:75:28] TLInterconnectCoupler_fbus_from_debug_sb coupler_from_debug_sb ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_widget_anon_in_a_ready (auto_coupler_from_debug_sb_widget_anon_in_a_ready_0), .auto_widget_anon_in_a_valid (auto_coupler_from_debug_sb_widget_anon_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_a_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_a_bits_size (auto_coupler_from_debug_sb_widget_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_a_bits_address (auto_coupler_from_debug_sb_widget_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_a_bits_data (auto_coupler_from_debug_sb_widget_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_d_ready (auto_coupler_from_debug_sb_widget_anon_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_widget_anon_in_d_valid (auto_coupler_from_debug_sb_widget_anon_in_d_valid_0), .auto_widget_anon_in_d_bits_opcode (auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode_0), .auto_widget_anon_in_d_bits_param (auto_coupler_from_debug_sb_widget_anon_in_d_bits_param_0), .auto_widget_anon_in_d_bits_size (auto_coupler_from_debug_sb_widget_anon_in_d_bits_size_0), .auto_widget_anon_in_d_bits_sink (auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink_0), .auto_widget_anon_in_d_bits_denied (auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied_0), .auto_widget_anon_in_d_bits_data (auto_coupler_from_debug_sb_widget_anon_in_d_bits_data_0), .auto_widget_anon_in_d_bits_corrupt (auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt_0), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_0_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_debug_sb_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_debug_sb_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_size (_coupler_from_debug_sb_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_address (_coupler_from_debug_sb_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_debug_sb_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_debug_sb_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_from_debug_sb_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_from_debug_sb_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_0_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_0_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_0_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_0_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_0_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_0_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_0_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_0_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in coupler_from_port_named_serial_tl_0_in ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready_0), .auto_buffer_in_a_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_address (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_mask (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_a_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_d_ready (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_in_d_valid (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid_0), .auto_buffer_in_d_bits_opcode (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode_0), .auto_buffer_in_d_bits_param (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param_0), .auto_buffer_in_d_bits_size (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size_0), .auto_buffer_in_d_bits_source (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source_0), .auto_buffer_in_d_bits_sink (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink_0), .auto_buffer_in_d_bits_denied (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied_0), .auto_buffer_in_d_bits_data (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data_0), .auto_buffer_in_d_bits_corrupt (auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt_0), .auto_tl_out_a_ready (_fbus_xbar_auto_anon_in_1_a_ready), // @[BusWrapper.scala:240:32] .auto_tl_out_a_valid (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_from_port_named_serial_tl_0_in_auto_tl_out_d_ready), .auto_tl_out_d_valid (_fbus_xbar_auto_anon_in_1_d_valid), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_opcode (_fbus_xbar_auto_anon_in_1_d_bits_opcode), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_param (_fbus_xbar_auto_anon_in_1_d_bits_param), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_size (_fbus_xbar_auto_anon_in_1_d_bits_size), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_source (_fbus_xbar_auto_anon_in_1_d_bits_source), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_sink (_fbus_xbar_auto_anon_in_1_d_bits_sink), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_denied (_fbus_xbar_auto_anon_in_1_d_bits_denied), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_data (_fbus_xbar_auto_anon_in_1_d_bits_data), // @[BusWrapper.scala:240:32] .auto_tl_out_d_bits_corrupt (_fbus_xbar_auto_anon_in_1_d_bits_corrupt) // @[BusWrapper.scala:240:32] ); // @[LazyScope.scala:98:27] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt = auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_a_ready = auto_coupler_from_debug_sb_widget_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_valid = auto_coupler_from_debug_sb_widget_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode = auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_param = auto_coupler_from_debug_sb_widget_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_size = auto_coupler_from_debug_sb_widget_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink = auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied = auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_data = auto_coupler_from_debug_sb_widget_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt = auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_clock = auto_fixedClockNode_anon_out_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_reset = auto_fixedClockNode_anon_out_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_171 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_171( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CSRFile : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<4>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2)) node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv) connect reg_mstatus.prv, _reg_mstatus_prv_T_1 wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h1) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h1) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h1) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<40>, clock reg reg_dscratch0 : UInt<64>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<64>, clock reg reg_mideleg : UInt<64>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<64>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<40>, clock regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) reg reg_mtval : UInt<40>, clock reg reg_mtval2 : UInt<40>, clock reg reg_mscratch : UInt<64>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<64>, clock reg reg_mnepc : UInt<40>, clock regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<64>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<64>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_htval : UInt<40>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<40>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node _T_14 = and(reg_vstvec, _T_13) node _T_15 = bits(_T_14, 39, 39) node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0)) node read_vstvec = cat(_T_16, _T_14) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<64>, clock reg reg_vsepc : UInt<40>, clock reg reg_vscause : UInt<64>, clock reg reg_vstval : UInt<40>, clock reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_sepc : UInt<40>, clock reg reg_scause : UInt<64>, clock reg reg_stval : UInt<40>, clock reg reg_sscratch : UInt<64>, clock reg reg_stvec : UInt<39>, clock reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_17 = eq(x3, UInt<1>(0h0)) when _T_17 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_18 = eq(x11, UInt<1>(0h0)) when _T_18 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip) connect mip.seip, _mip_seip_T connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 62) node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 63, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38) node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38) node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T_2 = not(reg_mepc) node _read_mapping_T_3 = bits(reg_misa, 2, 2) node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) node _read_mapping_T_6 = not(_read_mapping_T_5) node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39) node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) node _read_mapping_T_9 = bits(reg_mtval, 39, 39) node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node _debug_csrs_T_4 = not(_debug_csrs_T_3) node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39) node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0)) node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom) node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie) node lo_4 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze) node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_19 = cat(hi_6, lo_4) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) node read_sie = and(reg_mie, sie_mask) node read_sip = and(read_mip, sie_mask) wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _read_sstatus_WIRE.uie, UInt<1>(0h0) connect _read_sstatus_WIRE.sie, UInt<1>(0h0) connect _read_sstatus_WIRE.hie, UInt<1>(0h0) connect _read_sstatus_WIRE.mie, UInt<1>(0h0) connect _read_sstatus_WIRE.upie, UInt<1>(0h0) connect _read_sstatus_WIRE.spie, UInt<1>(0h0) connect _read_sstatus_WIRE.ube, UInt<1>(0h0) connect _read_sstatus_WIRE.mpie, UInt<1>(0h0) connect _read_sstatus_WIRE.spp, UInt<1>(0h0) connect _read_sstatus_WIRE.vs, UInt<2>(0h0) connect _read_sstatus_WIRE.mpp, UInt<2>(0h0) connect _read_sstatus_WIRE.fs, UInt<2>(0h0) connect _read_sstatus_WIRE.xs, UInt<2>(0h0) connect _read_sstatus_WIRE.mprv, UInt<1>(0h0) connect _read_sstatus_WIRE.sum, UInt<1>(0h0) connect _read_sstatus_WIRE.mxr, UInt<1>(0h0) connect _read_sstatus_WIRE.tvm, UInt<1>(0h0) connect _read_sstatus_WIRE.tw, UInt<1>(0h0) connect _read_sstatus_WIRE.tsr, UInt<1>(0h0) connect _read_sstatus_WIRE.zero1, UInt<8>(0h0) connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _read_sstatus_WIRE.uxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sbe, UInt<1>(0h0) connect _read_sstatus_WIRE.mbe, UInt<1>(0h0) connect _read_sstatus_WIRE.gva, UInt<1>(0h0) connect _read_sstatus_WIRE.mpv, UInt<1>(0h0) connect _read_sstatus_WIRE.zero2, UInt<23>(0h0) connect _read_sstatus_WIRE.sd, UInt<1>(0h0) connect _read_sstatus_WIRE.v, UInt<1>(0h0) connect _read_sstatus_WIRE.prv, UInt<2>(0h0) connect _read_sstatus_WIRE.dv, UInt<1>(0h0) connect _read_sstatus_WIRE.dprv, UInt<2>(0h0) connect _read_sstatus_WIRE.isa, UInt<32>(0h0) connect _read_sstatus_WIRE.wfi, UInt<1>(0h0) connect _read_sstatus_WIRE.cease, UInt<1>(0h0) connect _read_sstatus_WIRE.debug, UInt<1>(0h0) wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect read_sstatus, _read_sstatus_WIRE connect read_sstatus.sd, io.status.sd connect read_sstatus.uxl, io.status.uxl connect read_sstatus.sd_rv32, io.status.sd_rv32 connect read_sstatus.mxr, io.status.mxr connect read_sstatus.sum, io.status.sum connect read_sstatus.xs, io.status.xs connect read_sstatus.fs, io.status.fs connect read_sstatus.vs, io.status.vs connect read_sstatus.spp, io.status.spp connect read_sstatus.spie, io.status.spie connect read_sstatus.sie, io.status.sie node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie) node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie) node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo) node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie) node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie) node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube) node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo) node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4) node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs) node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs) node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo) node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv) node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm) node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr) node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo) node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4) node lo_5 = cat(lo_hi_5, lo_lo_5) node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr) node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32) node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo) node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl) node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva) node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe) node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo) node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4) node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2) node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv) node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v) node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo) node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv) node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease) node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi) node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo) node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_20 = cat(hi_7, lo_5) node _T_21 = bits(_T_20, 63, 0) node _T_22 = bits(reg_stval, 39, 39) node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_24 = cat(_T_23, reg_stval) node hi_8 = cat(reg_satp.mode, reg_satp.asid) node _T_25 = cat(hi_8, reg_satp.ppn) node _T_26 = not(reg_sepc) node _T_27 = bits(reg_misa, 2, 2) node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3)) node _T_29 = or(_T_26, _T_28) node _T_30 = not(_T_29) node _T_31 = bits(_T_30, 39, 39) node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_33 = cat(_T_32, _T_30) node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom) node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie) node lo_6 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze) node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_34 = cat(hi_9, lo_6) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r) node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a) node _T_35 = cat(hi_10, lo_7) node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r) node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a) node _T_36 = cat(hi_11, lo_8) node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r) node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a) node _T_37 = cat(hi_12, lo_9) node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r) node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a) node _T_38 = cat(hi_13, lo_10) node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r) node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a) node _T_39 = cat(hi_14, lo_11) node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r) node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a) node _T_40 = cat(hi_15, lo_12) node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r) node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a) node _T_41 = cat(hi_16, lo_13) node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r) node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a) node _T_42 = cat(hi_17, lo_14) node lo_lo_7 = cat(_T_36, _T_35) node lo_hi_15 = cat(_T_38, _T_37) node lo_15 = cat(lo_hi_15, lo_lo_7) node hi_lo_7 = cat(_T_40, _T_39) node hi_hi_15 = cat(_T_42, _T_41) node hi_18 = cat(hi_hi_15, hi_lo_7) node _T_43 = cat(hi_18, lo_15) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_44 = cat(hi_19, lo_16) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_45 = cat(hi_20, lo_17) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_46 = cat(hi_21, lo_18) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_47 = cat(hi_22, lo_19) node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a) node _T_48 = cat(hi_23, lo_20) node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r) node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a) node _T_49 = cat(hi_24, lo_21) node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r) node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a) node _T_50 = cat(hi_25, lo_22) node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r) node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a) node _T_51 = cat(hi_26, lo_23) node lo_lo_8 = cat(_T_45, _T_44) node lo_hi_24 = cat(_T_47, _T_46) node lo_24 = cat(lo_hi_24, lo_lo_8) node hi_lo_8 = cat(_T_49, _T_48) node hi_hi_24 = cat(_T_51, _T_50) node hi_27 = cat(hi_hi_24, hi_lo_8) node _T_52 = cat(hi_27, lo_24) regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<150> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_53 = bits(decoded, 8, 8) node _T_54 = bits(decoded, 7, 7) node _T_55 = bits(decoded, 6, 6) node _T_56 = bits(decoded, 5, 5) node _T_57 = bits(decoded, 4, 4) node _T_58 = bits(decoded, 3, 3) node _T_59 = bits(decoded, 2, 2) node _T_60 = bits(decoded, 1, 1) node _T_61 = bits(decoded, 0, 0) node _T_62 = bits(_T_53, 0, 0) node insn_call = and(system_insn, _T_62) node _T_63 = bits(_T_54, 0, 0) node insn_break = and(system_insn, _T_63) node _T_64 = bits(_T_55, 0, 0) node insn_ret = and(system_insn, _T_64) node _T_65 = bits(_T_56, 0, 0) node insn_cease = and(system_insn, _T_65) node _T_66 = bits(_T_57, 0, 0) node insn_wfi = and(system_insn, _T_66) node _T_67 = bits(_T_58, 0, 0) node _T_68 = and(system_insn, _T_67) node _T_69 = bits(_T_59, 0, 0) node _T_70 = and(system_insn, _T_69) node _T_71 = bits(_T_60, 0, 0) node _T_72 = and(system_insn, _T_71) node _T_73 = bits(_T_61, 0, 0) node _T_74 = and(system_insn, _T_73) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_75 = bits(decoded_1, 8, 8) node _T_76 = bits(decoded_1, 7, 7) node _T_77 = bits(decoded_1, 6, 6) node _T_78 = bits(decoded_1, 5, 5) node _T_79 = bits(decoded_1, 4, 4) node _T_80 = bits(decoded_1, 3, 3) node _T_81 = bits(decoded_1, 2, 2) node _T_82 = bits(decoded_1, 1, 1) node _T_83 = bits(decoded_1, 0, 0) node _T_84 = bits(_T_75, 0, 0) node is_break = bits(_T_76, 0, 0) node is_ret = bits(_T_77, 0, 0) node _T_85 = bits(_T_78, 0, 0) node is_wfi = bits(_T_79, 0, 0) node is_sfence = bits(_T_80, 0, 0) node is_hfence_vvma = bits(_T_81, 0, 0) node is_hfence_gvma = bits(_T_82, 0, 0) node is_hlsv = bits(_T_83, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11) node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3) node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo) node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h306)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a)) node _csr_exists_T_114 = eq(addr, UInt<9>(0h100)) node _csr_exists_T_115 = eq(addr, UInt<9>(0h144)) node _csr_exists_T_116 = eq(addr, UInt<9>(0h104)) node _csr_exists_T_117 = eq(addr, UInt<9>(0h140)) node _csr_exists_T_118 = eq(addr, UInt<9>(0h142)) node _csr_exists_T_119 = eq(addr, UInt<9>(0h143)) node _csr_exists_T_120 = eq(addr, UInt<9>(0h180)) node _csr_exists_T_121 = eq(addr, UInt<9>(0h141)) node _csr_exists_T_122 = eq(addr, UInt<9>(0h105)) node _csr_exists_T_123 = eq(addr, UInt<9>(0h106)) node _csr_exists_T_124 = eq(addr, UInt<10>(0h303)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h302)) node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a)) node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2) node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3) node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4) node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5) node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6) node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7) node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8) node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9) node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10) node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11) node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12) node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13) node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14) node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15) node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16) node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17) node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18) node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19) node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20) node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21) node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22) node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23) node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24) node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25) node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26) node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27) node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28) node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29) node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30) node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31) node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32) node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33) node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34) node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35) node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36) node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37) node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38) node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39) node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40) node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41) node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42) node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43) node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44) node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45) node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46) node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148) node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 5, 0) node _causeIsDebugInt_T = bits(cause, 63, 63) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 63, 63) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 63, 63) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T) node _delegate_T_2 = bits(cause, 63, 63) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 63, 63) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 63, 63) node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 63, 63) node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<2>(0h2) connect io.status.sxl, UInt<2>(0h2) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<2>(0h2) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<2>(0h2) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_86 = add(insn_ret, insn_call) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(insn_break, io.exception) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_87, _T_89) node _T_91 = bits(_T_90, 2, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_92, UInt<1>(0h1), "") : assert node _T_96 = eq(io.singleStep, UInt<1>(0h0)) node _T_97 = and(insn_wfi, _T_96) node _T_98 = eq(reg_debug, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) when _T_99 : connect reg_wfi, UInt<1>(0h1) node _T_100 = orr(pending_interrupts) node _T_101 = or(_T_100, io.interrupts.debug) node _T_102 = or(_T_101, exception) when _T_102 : connect reg_wfi, UInt<1>(0h0) node _T_103 = bits(io.retire, 0, 0) node _T_104 = or(_T_103, exception) when _T_104 : connect reg_singleStepped, UInt<1>(0h1) node _T_105 = eq(io.singleStep, UInt<1>(0h0)) when _T_105 : connect reg_singleStepped, UInt<1>(0h0) node _T_106 = eq(io.singleStep, UInt<1>(0h0)) node _T_107 = leq(io.retire, UInt<1>(0h1)) node _T_108 = or(_T_106, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_113 = eq(io.retire, UInt<1>(0h0)) node _T_114 = or(_T_112, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 assert(clock, _T_114, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_118 = eq(reg_debug, UInt<1>(0h0)) when _T_118 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, reg_mstatus.prv connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, reg_mstatus.prv connect new_prv, UInt<2>(0h3) else : node _T_119 = and(delegateVS, reg_rnmie) when _T_119 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 63, 63) node _reg_vscause_T_1 = bits(cause, 63, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_120 = and(delegate, reg_rnmie) when _T_120 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, reg_mstatus.prv connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_121 = eq(delegate, UInt<1>(0h0)) node _T_122 = and(en, _T_121) node _T_123 = and(en, delegable) node _T_124 = and(_T_123, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_125 = eq(delegate, UInt<1>(0h0)) node _T_126 = and(en_1, _T_125) node _T_127 = and(en_1, delegable_1) node _T_128 = and(_T_127, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_129 = eq(delegate, UInt<1>(0h0)) node _T_130 = and(en_2, _T_129) node _T_131 = and(en_2, delegable_2) node _T_132 = and(_T_131, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_133 = eq(delegate, UInt<1>(0h0)) node _T_134 = and(en_3, _T_133) node _T_135 = and(en_3, delegable_3) node _T_136 = and(_T_135, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_137 = eq(delegate, UInt<1>(0h0)) node _T_138 = and(en_4, _T_137) node _T_139 = and(en_4, delegable_4) node _T_140 = and(_T_139, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_141 = eq(delegate, UInt<1>(0h0)) node _T_142 = and(en_5, _T_141) node _T_143 = and(en_5, delegable_5) node _T_144 = and(_T_143, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_145 = eq(delegate, UInt<1>(0h0)) node _T_146 = and(en_6, _T_145) node _T_147 = and(en_6, delegable_6) node _T_148 = and(_T_147, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_149 = eq(delegate, UInt<1>(0h0)) node _T_150 = and(en_7, _T_149) node _T_151 = and(en_7, delegable_7) node _T_152 = and(_T_151, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_153 = eq(delegate, UInt<1>(0h0)) node _T_154 = and(en_8, _T_153) node _T_155 = and(en_8, delegable_8) node _T_156 = and(_T_155, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_157 = eq(delegate, UInt<1>(0h0)) node _T_158 = and(en_9, _T_157) node _T_159 = and(en_9, delegable_9) node _T_160 = and(_T_159, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_161 = eq(delegate, UInt<1>(0h0)) node _T_162 = and(en_10, _T_161) node _T_163 = and(en_10, delegable_10) node _T_164 = and(_T_163, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_165 = eq(delegate, UInt<1>(0h0)) node _T_166 = and(en_11, _T_165) node _T_167 = and(en_11, delegable_11) node _T_168 = and(_T_167, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_169 = eq(delegate, UInt<1>(0h0)) node _T_170 = and(en_12, _T_169) node _T_171 = and(en_12, delegable_12) node _T_172 = and(_T_171, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_173 = eq(delegate, UInt<1>(0h0)) node _T_174 = and(en_13, _T_173) node _T_175 = and(en_13, delegable_13) node _T_176 = and(_T_175, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_177 = eq(delegate, UInt<1>(0h0)) node _T_178 = and(en_14, _T_177) node _T_179 = and(en_14, delegable_14) node _T_180 = and(_T_179, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_181 = eq(delegate, UInt<1>(0h0)) node _T_182 = and(en_15, _T_181) node _T_183 = and(en_15, delegable_15) node _T_184 = and(_T_183, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_185 = eq(delegate, UInt<1>(0h0)) node _T_186 = and(en_16, _T_185) node _T_187 = and(en_16, delegable_16) node _T_188 = and(_T_187, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_189 = eq(delegate, UInt<1>(0h0)) node _T_190 = and(en_17, _T_189) node _T_191 = and(en_17, delegable_17) node _T_192 = and(_T_191, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_193 = eq(delegate, UInt<1>(0h0)) node _T_194 = and(en_18, _T_193) node _T_195 = and(en_18, delegable_18) node _T_196 = and(_T_195, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_197 = eq(delegate, UInt<1>(0h0)) node _T_198 = and(en_19, _T_197) node _T_199 = and(en_19, delegable_19) node _T_200 = and(_T_199, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_201 = eq(delegate, UInt<1>(0h0)) node _T_202 = and(en_20, _T_201) node _T_203 = and(en_20, delegable_20) node _T_204 = and(_T_203, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_205 = eq(delegate, UInt<1>(0h0)) node _T_206 = and(en_21, _T_205) node _T_207 = and(en_21, delegable_21) node _T_208 = and(_T_207, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_209 = eq(delegate, UInt<1>(0h0)) node _T_210 = and(en_22, _T_209) node _T_211 = and(en_22, delegable_22) node _T_212 = and(_T_211, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_213 = eq(delegate, UInt<1>(0h0)) node _T_214 = and(en_23, _T_213) node _T_215 = and(en_23, delegable_23) node _T_216 = and(_T_215, delegate) node _en_T_104 = eq(cause, UInt<4>(0h8)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_217 = eq(delegate, UInt<1>(0h0)) node _T_218 = and(en_24, _T_217) node _T_219 = and(en_24, delegable_24) node _T_220 = and(_T_219, delegate) node _en_T_105 = eq(cause, UInt<4>(0h9)) node en_25 = and(exception, _en_T_105) node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200)) node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0)) node _T_221 = eq(delegate, UInt<1>(0h0)) node _T_222 = and(en_25, _T_221) node _T_223 = and(en_25, delegable_25) node _T_224 = and(_T_223, delegate) node _en_T_106 = eq(cause, UInt<4>(0hb)) node en_26 = and(exception, _en_T_106) node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0)) node _T_225 = eq(delegate, UInt<1>(0h0)) node _T_226 = and(en_26, _T_225) node _T_227 = and(en_26, delegable_26) node _T_228 = and(_T_227, delegate) node _en_T_107 = eq(cause, UInt<4>(0hc)) node en_27 = and(exception, _en_T_107) node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000)) node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0)) node _T_229 = eq(delegate, UInt<1>(0h0)) node _T_230 = and(en_27, _T_229) node _T_231 = and(en_27, delegable_27) node _T_232 = and(_T_231, delegate) node _en_T_108 = eq(cause, UInt<4>(0hd)) node en_28 = and(exception, _en_T_108) node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000)) node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0)) node _T_233 = eq(delegate, UInt<1>(0h0)) node _T_234 = and(en_28, _T_233) node _T_235 = and(en_28, delegable_28) node _T_236 = and(_T_235, delegate) node _en_T_109 = eq(cause, UInt<4>(0hf)) node en_29 = and(exception, _en_T_109) node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000)) node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0)) node _T_237 = eq(delegate, UInt<1>(0h0)) node _T_238 = and(en_29, _T_237) node _T_239 = and(en_29, delegable_29) node _T_240 = and(_T_239, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_241 = bits(io.rw.addr, 9, 9) node _T_242 = eq(_T_241, UInt<1>(0h0)) node _T_243 = and(UInt<1>(0h1), _T_242) when _T_243 : node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_244 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_245 = bits(io.rw.addr, 10, 10) node _T_246 = and(UInt<1>(0h1), _T_245) node _T_247 = bits(io.rw.addr, 7, 7) node _T_248 = and(_T_246, _T_247) when _T_248 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_249 = bits(io.rw.addr, 10, 10) node _T_250 = and(UInt<1>(0h0), _T_249) node _T_251 = bits(io.rw.addr, 7, 7) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(_T_250, _T_252) when _T_253 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2)) node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0)) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1 connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_254 = leq(ret_prv, UInt<1>(0h1)) node _T_255 = and(UInt<1>(0h1), _T_254) when _T_255 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2) node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3) node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4) node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5) node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6) node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7) node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8) node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9) node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10) node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11) node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12) node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13) node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14) node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15) node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16) node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17) node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18) node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19) node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20) node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21) node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22) node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23) node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24) node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25) node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26) node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27) node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28) node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29) node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30) node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31) node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32) node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33) node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34) node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35) node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36) node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37) node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38) node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39) node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40) node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41) node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42) node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43) node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44) node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45) node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_256 = andr(UInt<2>(0h1)) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_261 = or(_T_258, _T_259) node _T_262 = or(_T_261, _T_260) node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_264 = and(_T_262, _T_263) else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_267 = and(_T_265, _T_266) node _T_268 = andr(UInt<2>(0h1)) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_273 = or(_T_270, _T_271) node _T_274 = or(_T_273, _T_272) node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_276 = and(_T_274, _T_275) else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_279 = and(_T_277, _T_278) node _T_280 = andr(UInt<2>(0h1)) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_285 = or(_T_282, _T_283) node _T_286 = or(_T_285, _T_284) node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_288 = and(_T_286, _T_287) else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_291 = and(_T_289, _T_290) node _T_292 = andr(UInt<2>(0h1)) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_297 = or(_T_294, _T_295) node _T_298 = or(_T_297, _T_296) node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_300 = and(_T_298, _T_299) else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_303 = and(_T_301, _T_302) node _T_304 = andr(UInt<2>(0h0)) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_309 = or(_T_306, _T_307) node _T_310 = or(_T_309, _T_308) node _T_311 = eq(io.rw.addr, UInt<10>(0h301)) node _T_312 = and(_T_310, _T_311) else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_314 = eq(io.rw.addr, UInt<10>(0h301)) node _T_315 = and(_T_313, _T_314) node _T_316 = andr(UInt<2>(0h0)) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_321 = or(_T_318, _T_319) node _T_322 = or(_T_321, _T_320) node _T_323 = eq(io.rw.addr, UInt<10>(0h300)) node _T_324 = and(_T_322, _T_323) else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_326 = eq(io.rw.addr, UInt<10>(0h300)) node _T_327 = and(_T_325, _T_326) node _T_328 = andr(UInt<2>(0h0)) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_333 = or(_T_330, _T_331) node _T_334 = or(_T_333, _T_332) node _T_335 = eq(io.rw.addr, UInt<10>(0h305)) node _T_336 = and(_T_334, _T_335) else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_338 = eq(io.rw.addr, UInt<10>(0h305)) node _T_339 = and(_T_337, _T_338) node _T_340 = andr(UInt<2>(0h0)) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_345 = or(_T_342, _T_343) node _T_346 = or(_T_345, _T_344) node _T_347 = eq(io.rw.addr, UInt<10>(0h344)) node _T_348 = and(_T_346, _T_347) else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_350 = eq(io.rw.addr, UInt<10>(0h344)) node _T_351 = and(_T_349, _T_350) node _T_352 = andr(UInt<2>(0h0)) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_357 = or(_T_354, _T_355) node _T_358 = or(_T_357, _T_356) node _T_359 = eq(io.rw.addr, UInt<10>(0h304)) node _T_360 = and(_T_358, _T_359) else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_362 = eq(io.rw.addr, UInt<10>(0h304)) node _T_363 = and(_T_361, _T_362) node _T_364 = andr(UInt<2>(0h0)) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_369 = or(_T_366, _T_367) node _T_370 = or(_T_369, _T_368) node _T_371 = eq(io.rw.addr, UInt<10>(0h340)) node _T_372 = and(_T_370, _T_371) else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_374 = eq(io.rw.addr, UInt<10>(0h340)) node _T_375 = and(_T_373, _T_374) node _T_376 = andr(UInt<2>(0h0)) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_381 = or(_T_378, _T_379) node _T_382 = or(_T_381, _T_380) node _T_383 = eq(io.rw.addr, UInt<10>(0h341)) node _T_384 = and(_T_382, _T_383) else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_386 = eq(io.rw.addr, UInt<10>(0h341)) node _T_387 = and(_T_385, _T_386) node _T_388 = andr(UInt<2>(0h0)) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_393 = or(_T_390, _T_391) node _T_394 = or(_T_393, _T_392) node _T_395 = eq(io.rw.addr, UInt<10>(0h343)) node _T_396 = and(_T_394, _T_395) else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_398 = eq(io.rw.addr, UInt<10>(0h343)) node _T_399 = and(_T_397, _T_398) node _T_400 = andr(UInt<2>(0h0)) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_405 = or(_T_402, _T_403) node _T_406 = or(_T_405, _T_404) node _T_407 = eq(io.rw.addr, UInt<10>(0h342)) node _T_408 = and(_T_406, _T_407) else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_410 = eq(io.rw.addr, UInt<10>(0h342)) node _T_411 = and(_T_409, _T_410) node _T_412 = andr(UInt<2>(0h3)) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_417 = or(_T_414, _T_415) node _T_418 = or(_T_417, _T_416) node _T_419 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_420 = and(_T_418, _T_419) else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_422 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_423 = and(_T_421, _T_422) node _T_424 = andr(UInt<2>(0h1)) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_429 = or(_T_426, _T_427) node _T_430 = or(_T_429, _T_428) node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_432 = and(_T_430, _T_431) else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_435 = and(_T_433, _T_434) node _T_436 = andr(UInt<2>(0h1)) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_441 = or(_T_438, _T_439) node _T_442 = or(_T_441, _T_440) node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_444 = and(_T_442, _T_443) else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_447 = and(_T_445, _T_446) node _T_448 = andr(UInt<2>(0h1)) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_453 = or(_T_450, _T_451) node _T_454 = or(_T_453, _T_452) node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_456 = and(_T_454, _T_455) else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_459 = and(_T_457, _T_458) node _T_460 = andr(UInt<2>(0h0)) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_465 = or(_T_462, _T_463) node _T_466 = or(_T_465, _T_464) node _T_467 = eq(io.rw.addr, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_470 = eq(io.rw.addr, UInt<1>(0h1)) node _T_471 = and(_T_469, _T_470) node _T_472 = andr(UInt<2>(0h0)) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_477 = or(_T_474, _T_475) node _T_478 = or(_T_477, _T_476) node _T_479 = eq(io.rw.addr, UInt<2>(0h2)) node _T_480 = and(_T_478, _T_479) else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_482 = eq(io.rw.addr, UInt<2>(0h2)) node _T_483 = and(_T_481, _T_482) node _T_484 = andr(UInt<2>(0h0)) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_489 = or(_T_486, _T_487) node _T_490 = or(_T_489, _T_488) node _T_491 = eq(io.rw.addr, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_494 = eq(io.rw.addr, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = andr(UInt<2>(0h0)) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_501 = or(_T_498, _T_499) node _T_502 = or(_T_501, _T_500) node _T_503 = eq(io.rw.addr, UInt<10>(0h320)) node _T_504 = and(_T_502, _T_503) else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_506 = eq(io.rw.addr, UInt<10>(0h320)) node _T_507 = and(_T_505, _T_506) node _T_508 = andr(UInt<2>(0h2)) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_513 = or(_T_510, _T_511) node _T_514 = or(_T_513, _T_512) node _T_515 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_516 = and(_T_514, _T_515) else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_518 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_519 = and(_T_517, _T_518) node _T_520 = andr(UInt<2>(0h2)) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_525 = or(_T_522, _T_523) node _T_526 = or(_T_525, _T_524) node _T_527 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_528 = and(_T_526, _T_527) else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_530 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_531 = and(_T_529, _T_530) node _T_532 = andr(UInt<2>(0h0)) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_537 = or(_T_534, _T_535) node _T_538 = or(_T_537, _T_536) node _T_539 = eq(io.rw.addr, UInt<10>(0h323)) node _T_540 = and(_T_538, _T_539) else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_542 = eq(io.rw.addr, UInt<10>(0h323)) node _T_543 = and(_T_541, _T_542) node _T_544 = andr(UInt<2>(0h2)) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_549 = or(_T_546, _T_547) node _T_550 = or(_T_549, _T_548) node _T_551 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_552 = and(_T_550, _T_551) else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_554 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_555 = and(_T_553, _T_554) node _T_556 = andr(UInt<2>(0h0)) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_561 = or(_T_558, _T_559) node _T_562 = or(_T_561, _T_560) node _T_563 = eq(io.rw.addr, UInt<10>(0h324)) node _T_564 = and(_T_562, _T_563) else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_566 = eq(io.rw.addr, UInt<10>(0h324)) node _T_567 = and(_T_565, _T_566) node _T_568 = andr(UInt<2>(0h2)) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_573 = or(_T_570, _T_571) node _T_574 = or(_T_573, _T_572) node _T_575 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_576 = and(_T_574, _T_575) else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_578 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_579 = and(_T_577, _T_578) node _T_580 = andr(UInt<2>(0h0)) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_585 = or(_T_582, _T_583) node _T_586 = or(_T_585, _T_584) node _T_587 = eq(io.rw.addr, UInt<10>(0h325)) node _T_588 = and(_T_586, _T_587) else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_590 = eq(io.rw.addr, UInt<10>(0h325)) node _T_591 = and(_T_589, _T_590) node _T_592 = andr(UInt<2>(0h2)) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_597 = or(_T_594, _T_595) node _T_598 = or(_T_597, _T_596) node _T_599 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_600 = and(_T_598, _T_599) else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_602 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_603 = and(_T_601, _T_602) node _T_604 = andr(UInt<2>(0h0)) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_609 = or(_T_606, _T_607) node _T_610 = or(_T_609, _T_608) node _T_611 = eq(io.rw.addr, UInt<10>(0h326)) node _T_612 = and(_T_610, _T_611) else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_614 = eq(io.rw.addr, UInt<10>(0h326)) node _T_615 = and(_T_613, _T_614) node _T_616 = andr(UInt<2>(0h2)) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_621 = or(_T_618, _T_619) node _T_622 = or(_T_621, _T_620) node _T_623 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_624 = and(_T_622, _T_623) else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_626 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_627 = and(_T_625, _T_626) node _T_628 = andr(UInt<2>(0h0)) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_633 = or(_T_630, _T_631) node _T_634 = or(_T_633, _T_632) node _T_635 = eq(io.rw.addr, UInt<10>(0h327)) node _T_636 = and(_T_634, _T_635) else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_638 = eq(io.rw.addr, UInt<10>(0h327)) node _T_639 = and(_T_637, _T_638) node _T_640 = andr(UInt<2>(0h2)) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_645 = or(_T_642, _T_643) node _T_646 = or(_T_645, _T_644) node _T_647 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_648 = and(_T_646, _T_647) else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_650 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_651 = and(_T_649, _T_650) node _T_652 = andr(UInt<2>(0h0)) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_657 = or(_T_654, _T_655) node _T_658 = or(_T_657, _T_656) node _T_659 = eq(io.rw.addr, UInt<10>(0h328)) node _T_660 = and(_T_658, _T_659) else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_662 = eq(io.rw.addr, UInt<10>(0h328)) node _T_663 = and(_T_661, _T_662) node _T_664 = andr(UInt<2>(0h2)) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_669 = or(_T_666, _T_667) node _T_670 = or(_T_669, _T_668) node _T_671 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_672 = and(_T_670, _T_671) else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_674 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_675 = and(_T_673, _T_674) node _T_676 = andr(UInt<2>(0h0)) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_681 = or(_T_678, _T_679) node _T_682 = or(_T_681, _T_680) node _T_683 = eq(io.rw.addr, UInt<10>(0h329)) node _T_684 = and(_T_682, _T_683) else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_686 = eq(io.rw.addr, UInt<10>(0h329)) node _T_687 = and(_T_685, _T_686) node _T_688 = andr(UInt<2>(0h2)) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_693 = or(_T_690, _T_691) node _T_694 = or(_T_693, _T_692) node _T_695 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_696 = and(_T_694, _T_695) else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_698 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_699 = and(_T_697, _T_698) node _T_700 = andr(UInt<2>(0h0)) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_705 = or(_T_702, _T_703) node _T_706 = or(_T_705, _T_704) node _T_707 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_708 = and(_T_706, _T_707) else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_710 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_711 = and(_T_709, _T_710) node _T_712 = andr(UInt<2>(0h2)) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_717 = or(_T_714, _T_715) node _T_718 = or(_T_717, _T_716) node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_720 = and(_T_718, _T_719) else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_723 = and(_T_721, _T_722) node _T_724 = andr(UInt<2>(0h0)) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_729 = or(_T_726, _T_727) node _T_730 = or(_T_729, _T_728) node _T_731 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_732 = and(_T_730, _T_731) else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_734 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_735 = and(_T_733, _T_734) node _T_736 = andr(UInt<2>(0h2)) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_741 = or(_T_738, _T_739) node _T_742 = or(_T_741, _T_740) node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_744 = and(_T_742, _T_743) else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_747 = and(_T_745, _T_746) node _T_748 = andr(UInt<2>(0h0)) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_753 = or(_T_750, _T_751) node _T_754 = or(_T_753, _T_752) node _T_755 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_756 = and(_T_754, _T_755) else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_758 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_759 = and(_T_757, _T_758) node _T_760 = andr(UInt<2>(0h2)) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_765 = or(_T_762, _T_763) node _T_766 = or(_T_765, _T_764) node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_768 = and(_T_766, _T_767) else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_771 = and(_T_769, _T_770) node _T_772 = andr(UInt<2>(0h0)) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_777 = or(_T_774, _T_775) node _T_778 = or(_T_777, _T_776) node _T_779 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_780 = and(_T_778, _T_779) else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_782 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_783 = and(_T_781, _T_782) node _T_784 = andr(UInt<2>(0h2)) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_789 = or(_T_786, _T_787) node _T_790 = or(_T_789, _T_788) node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_792 = and(_T_790, _T_791) else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_795 = and(_T_793, _T_794) node _T_796 = andr(UInt<2>(0h0)) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_801 = or(_T_798, _T_799) node _T_802 = or(_T_801, _T_800) node _T_803 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_804 = and(_T_802, _T_803) else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_806 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_807 = and(_T_805, _T_806) node _T_808 = andr(UInt<2>(0h2)) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_813 = or(_T_810, _T_811) node _T_814 = or(_T_813, _T_812) node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_816 = and(_T_814, _T_815) else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_819 = and(_T_817, _T_818) node _T_820 = andr(UInt<2>(0h0)) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_825 = or(_T_822, _T_823) node _T_826 = or(_T_825, _T_824) node _T_827 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_828 = and(_T_826, _T_827) else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_830 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_831 = and(_T_829, _T_830) node _T_832 = andr(UInt<2>(0h2)) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_837 = or(_T_834, _T_835) node _T_838 = or(_T_837, _T_836) node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_840 = and(_T_838, _T_839) else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_843 = and(_T_841, _T_842) node _T_844 = andr(UInt<2>(0h0)) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_849 = or(_T_846, _T_847) node _T_850 = or(_T_849, _T_848) node _T_851 = eq(io.rw.addr, UInt<10>(0h330)) node _T_852 = and(_T_850, _T_851) else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_854 = eq(io.rw.addr, UInt<10>(0h330)) node _T_855 = and(_T_853, _T_854) node _T_856 = andr(UInt<2>(0h2)) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_864 = and(_T_862, _T_863) else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_866 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_867 = and(_T_865, _T_866) node _T_868 = andr(UInt<2>(0h0)) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_873 = or(_T_870, _T_871) node _T_874 = or(_T_873, _T_872) node _T_875 = eq(io.rw.addr, UInt<10>(0h331)) node _T_876 = and(_T_874, _T_875) else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_878 = eq(io.rw.addr, UInt<10>(0h331)) node _T_879 = and(_T_877, _T_878) node _T_880 = andr(UInt<2>(0h2)) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_885 = or(_T_882, _T_883) node _T_886 = or(_T_885, _T_884) node _T_887 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_888 = and(_T_886, _T_887) else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_890 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_891 = and(_T_889, _T_890) node _T_892 = andr(UInt<2>(0h0)) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_897 = or(_T_894, _T_895) node _T_898 = or(_T_897, _T_896) node _T_899 = eq(io.rw.addr, UInt<10>(0h332)) node _T_900 = and(_T_898, _T_899) else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_902 = eq(io.rw.addr, UInt<10>(0h332)) node _T_903 = and(_T_901, _T_902) node _T_904 = andr(UInt<2>(0h2)) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_909 = or(_T_906, _T_907) node _T_910 = or(_T_909, _T_908) node _T_911 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_912 = and(_T_910, _T_911) else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_914 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_915 = and(_T_913, _T_914) node _T_916 = andr(UInt<2>(0h0)) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_921 = or(_T_918, _T_919) node _T_922 = or(_T_921, _T_920) node _T_923 = eq(io.rw.addr, UInt<10>(0h333)) node _T_924 = and(_T_922, _T_923) else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_926 = eq(io.rw.addr, UInt<10>(0h333)) node _T_927 = and(_T_925, _T_926) node _T_928 = andr(UInt<2>(0h2)) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_933 = or(_T_930, _T_931) node _T_934 = or(_T_933, _T_932) node _T_935 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_936 = and(_T_934, _T_935) else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_938 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_939 = and(_T_937, _T_938) node _T_940 = andr(UInt<2>(0h0)) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_945 = or(_T_942, _T_943) node _T_946 = or(_T_945, _T_944) node _T_947 = eq(io.rw.addr, UInt<10>(0h334)) node _T_948 = and(_T_946, _T_947) else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_950 = eq(io.rw.addr, UInt<10>(0h334)) node _T_951 = and(_T_949, _T_950) node _T_952 = andr(UInt<2>(0h2)) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_957 = or(_T_954, _T_955) node _T_958 = or(_T_957, _T_956) node _T_959 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_960 = and(_T_958, _T_959) else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_962 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_963 = and(_T_961, _T_962) node _T_964 = andr(UInt<2>(0h0)) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_969 = or(_T_966, _T_967) node _T_970 = or(_T_969, _T_968) node _T_971 = eq(io.rw.addr, UInt<10>(0h335)) node _T_972 = and(_T_970, _T_971) else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_974 = eq(io.rw.addr, UInt<10>(0h335)) node _T_975 = and(_T_973, _T_974) node _T_976 = andr(UInt<2>(0h2)) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_981 = or(_T_978, _T_979) node _T_982 = or(_T_981, _T_980) node _T_983 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_984 = and(_T_982, _T_983) else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_986 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_987 = and(_T_985, _T_986) node _T_988 = andr(UInt<2>(0h0)) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_993 = or(_T_990, _T_991) node _T_994 = or(_T_993, _T_992) node _T_995 = eq(io.rw.addr, UInt<10>(0h336)) node _T_996 = and(_T_994, _T_995) else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_998 = eq(io.rw.addr, UInt<10>(0h336)) node _T_999 = and(_T_997, _T_998) node _T_1000 = andr(UInt<2>(0h2)) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1005 = or(_T_1002, _T_1003) node _T_1006 = or(_T_1005, _T_1004) node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1008 = and(_T_1006, _T_1007) else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = andr(UInt<2>(0h0)) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1017 = or(_T_1014, _T_1015) node _T_1018 = or(_T_1017, _T_1016) node _T_1019 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1020 = and(_T_1018, _T_1019) else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1022 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = andr(UInt<2>(0h2)) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1029 = or(_T_1026, _T_1027) node _T_1030 = or(_T_1029, _T_1028) node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1032 = and(_T_1030, _T_1031) else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1035 = and(_T_1033, _T_1034) node _T_1036 = andr(UInt<2>(0h0)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1041 = or(_T_1038, _T_1039) node _T_1042 = or(_T_1041, _T_1040) node _T_1043 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1044 = and(_T_1042, _T_1043) else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1046 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = andr(UInt<2>(0h2)) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1053 = or(_T_1050, _T_1051) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1056 = and(_T_1054, _T_1055) else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = andr(UInt<2>(0h0)) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1065 = or(_T_1062, _T_1063) node _T_1066 = or(_T_1065, _T_1064) node _T_1067 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1068 = and(_T_1066, _T_1067) else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1070 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = andr(UInt<2>(0h2)) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1077 = or(_T_1074, _T_1075) node _T_1078 = or(_T_1077, _T_1076) node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1080 = and(_T_1078, _T_1079) else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = andr(UInt<2>(0h0)) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1089 = or(_T_1086, _T_1087) node _T_1090 = or(_T_1089, _T_1088) node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1092 = and(_T_1090, _T_1091) else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = andr(UInt<2>(0h2)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1101 = or(_T_1098, _T_1099) node _T_1102 = or(_T_1101, _T_1100) node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1104 = and(_T_1102, _T_1103) else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = andr(UInt<2>(0h0)) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1113 = or(_T_1110, _T_1111) node _T_1114 = or(_T_1113, _T_1112) node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1116 = and(_T_1114, _T_1115) else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = andr(UInt<2>(0h2)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1125 = or(_T_1122, _T_1123) node _T_1126 = or(_T_1125, _T_1124) node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1128 = and(_T_1126, _T_1127) else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = andr(UInt<2>(0h0)) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1137 = or(_T_1134, _T_1135) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1140 = and(_T_1138, _T_1139) else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = andr(UInt<2>(0h2)) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1149 = or(_T_1146, _T_1147) node _T_1150 = or(_T_1149, _T_1148) node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1152 = and(_T_1150, _T_1151) else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = andr(UInt<2>(0h0)) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1161 = or(_T_1158, _T_1159) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1164 = and(_T_1162, _T_1163) else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = andr(UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1173 = or(_T_1170, _T_1171) node _T_1174 = or(_T_1173, _T_1172) node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1176 = and(_T_1174, _T_1175) else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = andr(UInt<2>(0h0)) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1185 = or(_T_1182, _T_1183) node _T_1186 = or(_T_1185, _T_1184) node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1188 = and(_T_1186, _T_1187) else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = andr(UInt<2>(0h2)) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1197 = or(_T_1194, _T_1195) node _T_1198 = or(_T_1197, _T_1196) node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1200 = and(_T_1198, _T_1199) else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = andr(UInt<2>(0h0)) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1209 = or(_T_1206, _T_1207) node _T_1210 = or(_T_1209, _T_1208) node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1212 = and(_T_1210, _T_1211) else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = andr(UInt<2>(0h2)) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1221 = or(_T_1218, _T_1219) node _T_1222 = or(_T_1221, _T_1220) node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1224 = and(_T_1222, _T_1223) else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = andr(UInt<2>(0h0)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1233 = or(_T_1230, _T_1231) node _T_1234 = or(_T_1233, _T_1232) node _T_1235 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1236 = and(_T_1234, _T_1235) else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1238 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = andr(UInt<2>(0h3)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1245 = or(_T_1242, _T_1243) node _T_1246 = or(_T_1245, _T_1244) node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1248 = and(_T_1246, _T_1247) else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = andr(UInt<2>(0h3)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1257 = or(_T_1254, _T_1255) node _T_1258 = or(_T_1257, _T_1256) node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1260 = and(_T_1258, _T_1259) else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = andr(UInt<2>(0h0)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1269 = or(_T_1266, _T_1267) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1272 = and(_T_1270, _T_1271) else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = andr(UInt<2>(0h0)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1281 = or(_T_1278, _T_1279) node _T_1282 = or(_T_1281, _T_1280) node _T_1283 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1284 = and(_T_1282, _T_1283) else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1286 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = andr(UInt<2>(0h0)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1293 = or(_T_1290, _T_1291) node _T_1294 = or(_T_1293, _T_1292) node _T_1295 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1296 = and(_T_1294, _T_1295) else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1298 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = andr(UInt<2>(0h0)) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1305 = or(_T_1302, _T_1303) node _T_1306 = or(_T_1305, _T_1304) node _T_1307 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1308 = and(_T_1306, _T_1307) else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1310 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = andr(UInt<2>(0h0)) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1317 = or(_T_1314, _T_1315) node _T_1318 = or(_T_1317, _T_1316) node _T_1319 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1320 = and(_T_1318, _T_1319) else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1322 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = andr(UInt<2>(0h0)) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1329 = or(_T_1326, _T_1327) node _T_1330 = or(_T_1329, _T_1328) node _T_1331 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1332 = and(_T_1330, _T_1331) else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1334 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = andr(UInt<2>(0h0)) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1341 = or(_T_1338, _T_1339) node _T_1342 = or(_T_1341, _T_1340) node _T_1343 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1344 = and(_T_1342, _T_1343) else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1346 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = andr(UInt<2>(0h0)) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1353 = or(_T_1350, _T_1351) node _T_1354 = or(_T_1353, _T_1352) node _T_1355 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1356 = and(_T_1354, _T_1355) else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1358 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = andr(UInt<2>(0h0)) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1365 = or(_T_1362, _T_1363) node _T_1366 = or(_T_1365, _T_1364) node _T_1367 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1368 = and(_T_1366, _T_1367) else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1370 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1371 = and(_T_1369, _T_1370) node _T_1372 = andr(UInt<2>(0h0)) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1377 = or(_T_1374, _T_1375) node _T_1378 = or(_T_1377, _T_1376) node _T_1379 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1380 = and(_T_1378, _T_1379) else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1382 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = andr(UInt<2>(0h0)) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1389 = or(_T_1386, _T_1387) node _T_1390 = or(_T_1389, _T_1388) node _T_1391 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1392 = and(_T_1390, _T_1391) else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1394 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = andr(UInt<2>(0h0)) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1401 = or(_T_1398, _T_1399) node _T_1402 = or(_T_1401, _T_1400) node _T_1403 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1404 = and(_T_1402, _T_1403) else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1406 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = andr(UInt<2>(0h0)) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1413 = or(_T_1410, _T_1411) node _T_1414 = or(_T_1413, _T_1412) node _T_1415 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1416 = and(_T_1414, _T_1415) else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1418 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = andr(UInt<2>(0h0)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1425 = or(_T_1422, _T_1423) node _T_1426 = or(_T_1425, _T_1424) node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1428 = and(_T_1426, _T_1427) else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = andr(UInt<2>(0h0)) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1437 = or(_T_1434, _T_1435) node _T_1438 = or(_T_1437, _T_1436) node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1440 = and(_T_1438, _T_1439) else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = andr(UInt<2>(0h0)) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1449 = or(_T_1446, _T_1447) node _T_1450 = or(_T_1449, _T_1448) node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1452 = and(_T_1450, _T_1451) else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = andr(UInt<2>(0h0)) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1461 = or(_T_1458, _T_1459) node _T_1462 = or(_T_1461, _T_1460) node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1464 = and(_T_1462, _T_1463) else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = andr(UInt<2>(0h0)) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1473 = or(_T_1470, _T_1471) node _T_1474 = or(_T_1473, _T_1472) node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1476 = and(_T_1474, _T_1475) else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = andr(UInt<2>(0h0)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1485 = or(_T_1482, _T_1483) node _T_1486 = or(_T_1485, _T_1484) node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1488 = and(_T_1486, _T_1487) else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = andr(UInt<2>(0h0)) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1497 = or(_T_1494, _T_1495) node _T_1498 = or(_T_1497, _T_1496) node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1500 = and(_T_1498, _T_1499) else : node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = andr(UInt<2>(0h0)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1509 = or(_T_1506, _T_1507) node _T_1510 = or(_T_1509, _T_1508) node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1512 = and(_T_1510, _T_1511) else : node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = andr(UInt<2>(0h0)) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1521 = or(_T_1518, _T_1519) node _T_1522 = or(_T_1521, _T_1520) node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1524 = and(_T_1522, _T_1523) else : node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = andr(UInt<2>(0h0)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1533 = or(_T_1530, _T_1531) node _T_1534 = or(_T_1533, _T_1532) node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1536 = and(_T_1534, _T_1535) else : node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1539 = and(_T_1537, _T_1538) node _T_1540 = andr(UInt<2>(0h0)) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1545 = or(_T_1542, _T_1543) node _T_1546 = or(_T_1545, _T_1544) node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1548 = and(_T_1546, _T_1547) else : node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = andr(UInt<2>(0h0)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1557 = or(_T_1554, _T_1555) node _T_1558 = or(_T_1557, _T_1556) node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1560 = and(_T_1558, _T_1559) else : node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = andr(UInt<2>(0h0)) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1569 = or(_T_1566, _T_1567) node _T_1570 = or(_T_1569, _T_1568) node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1572 = and(_T_1570, _T_1571) else : node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = andr(UInt<2>(0h0)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1581 = or(_T_1578, _T_1579) node _T_1582 = or(_T_1581, _T_1580) node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1584 = and(_T_1582, _T_1583) else : node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1587 = and(_T_1585, _T_1586) node _T_1588 = andr(UInt<2>(0h0)) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1593 = or(_T_1590, _T_1591) node _T_1594 = or(_T_1593, _T_1592) node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1596 = and(_T_1594, _T_1595) else : node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = andr(UInt<2>(0h0)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1605 = or(_T_1602, _T_1603) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1608 = and(_T_1606, _T_1607) else : node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = andr(UInt<2>(0h0)) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1617 = or(_T_1614, _T_1615) node _T_1618 = or(_T_1617, _T_1616) node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1620 = and(_T_1618, _T_1619) else : node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = andr(UInt<2>(0h0)) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1629 = or(_T_1626, _T_1627) node _T_1630 = or(_T_1629, _T_1628) node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1632 = and(_T_1630, _T_1631) else : node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = andr(UInt<2>(0h0)) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1641 = or(_T_1638, _T_1639) node _T_1642 = or(_T_1641, _T_1640) node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1644 = and(_T_1642, _T_1643) else : node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = andr(UInt<2>(0h1)) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1653 = or(_T_1650, _T_1651) node _T_1654 = or(_T_1653, _T_1652) node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1656 = and(_T_1654, _T_1655) else : node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = andr(UInt<2>(0h3)) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1665 = or(_T_1662, _T_1663) node _T_1666 = or(_T_1665, _T_1664) node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1668 = and(_T_1666, _T_1667) else : node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = andr(UInt<2>(0h3)) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1677 = or(_T_1674, _T_1675) node _T_1678 = or(_T_1677, _T_1676) node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1680 = and(_T_1678, _T_1679) else : node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = andr(UInt<2>(0h3)) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1689 = or(_T_1686, _T_1687) node _T_1690 = or(_T_1689, _T_1688) node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1692 = and(_T_1690, _T_1691) else : node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = andr(UInt<2>(0h3)) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1701 = or(_T_1698, _T_1699) node _T_1702 = or(_T_1701, _T_1700) node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1704 = and(_T_1702, _T_1703) else : node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1707 = and(_T_1705, _T_1706) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_100_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.mprv, new_mstatus.mprv node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2)) node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3 connect reg_mstatus.spp, new_mstatus.spp connect reg_mstatus.spie, new_mstatus.spie connect reg_mstatus.sie, new_mstatus.sie connect reg_mstatus.tw, new_mstatus.tw connect reg_mstatus.tsr, new_mstatus.tsr connect reg_mstatus.mxr, new_mstatus.mxr connect reg_mstatus.sum, new_mstatus.sum connect reg_mstatus.tvm, new_mstatus.tvm node _reg_mstatus_fs_T = orr(new_mstatus.fs) node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_1 connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_94_2 : node f = bits(wdata, 5, 5) node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_1709 = bits(io.pc, 1, 1) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1708, _T_1710) node _T_1712 = bits(wdata, 2, 2) node _T_1713 = or(_T_1711, _T_1712) when _T_1713 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) node _reg_misa_T_6 = not(UInt<64>(0h102d)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_108_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 connect reg_mip.ssip, new_mip.ssip connect reg_mip.stip, new_mip.stip connect reg_mip.seip, new_mip.seip when decoded_addr_76_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_132_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_129_2 : connect reg_mscratch, wdata when decoded_addr_72_2 : connect reg_mtvec, wdata when decoded_addr_29_2 : node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_136_2 : connect reg_mtval, wdata when decoded_addr_130_2 : node _reg_mcountinhibit_T = not(UInt<64>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_103_2 : node _T_1714 = bits(wdata, 63, 0) connect small_1, _T_1714 node _large_T_6 = shr(_T_1714, 6) connect large_1, _large_T_6 when decoded_addr_121_2 : node _T_1715 = bits(wdata, 63, 0) connect small, _T_1715 node _large_T_7 = shr(_T_1715, 6) connect large, _large_T_7 when decoded_addr_36_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata when decoded_addr_68_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_frm, wdata when decoded_addr_99_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata node _reg_frm_T = shr(wdata, 5) connect reg_frm, _reg_frm_T when decoded_addr_49_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm connect reg_dcsr.ebreaks, new_dcsr.ebreaks connect reg_dcsr.ebreaku, new_dcsr.ebreaku node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2)) node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv) connect reg_dcsr.prv, _reg_dcsr_prv_T_1 when decoded_addr_89_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_57_2 : connect reg_dscratch0, wdata when decoded_addr_61_2 : wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_sstatus_WIRE : UInt<105> connect _new_sstatus_WIRE, wdata node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0) connect new_sstatus.uie, _new_sstatus_T node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1) connect new_sstatus.sie, _new_sstatus_T_1 node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2) connect new_sstatus.hie, _new_sstatus_T_2 node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3) connect new_sstatus.mie, _new_sstatus_T_3 node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4) connect new_sstatus.upie, _new_sstatus_T_4 node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5) connect new_sstatus.spie, _new_sstatus_T_5 node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6) connect new_sstatus.ube, _new_sstatus_T_6 node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7) connect new_sstatus.mpie, _new_sstatus_T_7 node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8) connect new_sstatus.spp, _new_sstatus_T_8 node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9) connect new_sstatus.vs, _new_sstatus_T_9 node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11) connect new_sstatus.mpp, _new_sstatus_T_10 node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13) connect new_sstatus.fs, _new_sstatus_T_11 node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15) connect new_sstatus.xs, _new_sstatus_T_12 node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17) connect new_sstatus.mprv, _new_sstatus_T_13 node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18) connect new_sstatus.sum, _new_sstatus_T_14 node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19) connect new_sstatus.mxr, _new_sstatus_T_15 node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20) connect new_sstatus.tvm, _new_sstatus_T_16 node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21) connect new_sstatus.tw, _new_sstatus_T_17 node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22) connect new_sstatus.tsr, _new_sstatus_T_18 node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23) connect new_sstatus.zero1, _new_sstatus_T_19 node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31) connect new_sstatus.sd_rv32, _new_sstatus_T_20 node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32) connect new_sstatus.uxl, _new_sstatus_T_21 node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34) connect new_sstatus.sxl, _new_sstatus_T_22 node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36) connect new_sstatus.sbe, _new_sstatus_T_23 node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37) connect new_sstatus.mbe, _new_sstatus_T_24 node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38) connect new_sstatus.gva, _new_sstatus_T_25 node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39) connect new_sstatus.mpv, _new_sstatus_T_26 node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40) connect new_sstatus.zero2, _new_sstatus_T_27 node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63) connect new_sstatus.sd, _new_sstatus_T_28 node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64) connect new_sstatus.v, _new_sstatus_T_29 node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65) connect new_sstatus.prv, _new_sstatus_T_30 node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67) connect new_sstatus.dv, _new_sstatus_T_31 node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68) connect new_sstatus.dprv, _new_sstatus_T_32 node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70) connect new_sstatus.isa, _new_sstatus_T_33 node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102) connect new_sstatus.wfi, _new_sstatus_T_34 node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103) connect new_sstatus.cease, _new_sstatus_T_35 node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104) connect new_sstatus.debug, _new_sstatus_T_36 connect reg_mstatus.sie, new_sstatus.sie connect reg_mstatus.spie, new_sstatus.spie connect reg_mstatus.spp, new_sstatus.spp node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs) node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_3 connect reg_mstatus.vs, UInt<1>(0h0) connect reg_mstatus.mxr, new_sstatus.mxr connect reg_mstatus.sum, new_sstatus.sum when decoded_addr_48_2 : node _new_sip_T = not(read_mideleg) node _new_sip_T_1 = and(read_mip, _new_sip_T) node _new_sip_T_2 = and(wdata, read_mideleg) node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2) wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_sip_WIRE : UInt<16> connect _new_sip_WIRE, _new_sip_T_3 node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0) connect new_sip.usip, _new_sip_T_4 node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1) connect new_sip.ssip, _new_sip_T_5 node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2) connect new_sip.vssip, _new_sip_T_6 node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3) connect new_sip.msip, _new_sip_T_7 node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4) connect new_sip.utip, _new_sip_T_8 node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5) connect new_sip.stip, _new_sip_T_9 node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6) connect new_sip.vstip, _new_sip_T_10 node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7) connect new_sip.mtip, _new_sip_T_11 node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8) connect new_sip.ueip, _new_sip_T_12 node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9) connect new_sip.seip, _new_sip_T_13 node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10) connect new_sip.vseip, _new_sip_T_14 node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11) connect new_sip.meip, _new_sip_T_15 node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12) connect new_sip.sgeip, _new_sip_T_16 node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13) connect new_sip.rocc, _new_sip_T_17 node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14) connect new_sip.debug, _new_sip_T_18 node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15) connect new_sip.zero1, _new_sip_T_19 connect reg_mip.ssip, new_sip.ssip when decoded_addr_6_2 : wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} wire _new_satp_WIRE : UInt<64> connect _new_satp_WIRE, wdata node _new_satp_T = bits(_new_satp_WIRE, 43, 0) connect new_satp.ppn, _new_satp_T node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44) connect new_satp.asid, _new_satp_T_1 node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60) connect new_satp.mode, _new_satp_T_2 node _T_1716 = eq(new_satp.mode, UInt<1>(0h0)) node _T_1717 = eq(new_satp.mode, UInt<4>(0h8)) node _T_1718 = or(_T_1716, _T_1717) when _T_1718 : node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8)) connect reg_satp.mode, _reg_satp_mode_T node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0) connect reg_satp.ppn, _reg_satp_ppn_T when decoded_addr_44_2 : node _reg_mie_T_1 = not(sie_mask) node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1) node _reg_mie_T_3 = and(wdata, sie_mask) node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3) connect reg_mie, _reg_mie_T_4 when decoded_addr_15_2 : connect reg_sscratch, wdata when decoded_addr_28_2 : node _reg_sepc_T = not(wdata) node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1)) node _reg_sepc_T_2 = not(_reg_sepc_T_1) connect reg_sepc, _reg_sepc_T_2 when decoded_addr_25_2 : connect reg_stvec, wdata when decoded_addr_145_2 : node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f)) connect reg_scause, _reg_scause_T when decoded_addr_93_2 : connect reg_stval, wdata when decoded_addr_123_2 : connect reg_mideleg, wdata when decoded_addr_23_2 : connect reg_medeleg, wdata when decoded_addr_137_2 : connect reg_scounteren, wdata when decoded_addr_69_2 : wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE : UInt<64> connect _new_envcfg_WIRE, wdata node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0) connect new_envcfg.fiom, _new_envcfg_T node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1) connect new_envcfg.zero3, _new_envcfg_T_1 node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4) connect new_envcfg.cbie, _new_envcfg_T_2 node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6) connect new_envcfg.cbcfe, _new_envcfg_T_3 node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7) connect new_envcfg.cbze, _new_envcfg_T_4 node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8) connect new_envcfg.zero54, _new_envcfg_T_5 node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62) connect new_envcfg.pbmte, _new_envcfg_T_6 node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63) connect new_envcfg.stce, _new_envcfg_T_7 connect reg_senvcfg.fiom, new_envcfg.fiom when decoded_addr_35_2 : connect reg_mcounteren, wdata when decoded_addr_42_2 : wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE_1 : UInt<64> connect _new_envcfg_WIRE_1, wdata node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0) connect new_envcfg_1.fiom, _new_envcfg_T_8 node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1) connect new_envcfg_1.zero3, _new_envcfg_T_9 node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4) connect new_envcfg_1.cbie, _new_envcfg_T_10 node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6) connect new_envcfg_1.cbcfe, _new_envcfg_T_11 node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7) connect new_envcfg_1.cbze, _new_envcfg_T_12 node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8) connect new_envcfg_1.zero54, _new_envcfg_T_13 node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62) connect new_envcfg_1.pbmte, _new_envcfg_T_14 node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63) connect new_envcfg_1.stce, _new_envcfg_T_15 connect reg_menvcfg.fiom, new_envcfg_1.fiom when decoded_addr_97_2 : connect reg_tselect, wdata node _T_1719 = eq(UInt<1>(0h0), reg_tselect) node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_1721 = or(_T_1720, reg_debug) node _T_1722 = and(_T_1719, _T_1721) when _T_1722 : when decoded_addr_10_2 : connect reg_bp[0].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<64> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<64> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_1723 = gt(newBPC.action, UInt<1>(0h1)) node _T_1724 = or(dMode, _T_1723) when _T_1724 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_1725 = eq(UInt<1>(0h1), reg_tselect) node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_1727 = or(_T_1726, reg_debug) node _T_1728 = and(_T_1725, _T_1727) when _T_1728 : when decoded_addr_10_2 : connect reg_bp[1].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<64> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<64> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_1730 = or(dMode_1, _T_1729) when _T_1730 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_1732 = and(decoded_addr_141_2, _T_1731) when _T_1732 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736) node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737) node _T_1739 = eq(_T_1738, UInt<1>(0h0)) node _T_1740 = and(decoded_addr_104_2, _T_1739) when _T_1740 : connect reg_pmp[0].addr, wdata node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_1742 = and(decoded_addr_141_2, _T_1741) when _T_1742 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746) node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = and(decoded_addr_8_2, _T_1749) when _T_1750 : connect reg_pmp[1].addr, wdata node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_1752 = and(decoded_addr_141_2, _T_1751) when _T_1752 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756) node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = and(decoded_addr_125_2, _T_1759) when _T_1760 : connect reg_pmp[2].addr, wdata node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_1762 = and(decoded_addr_141_2, _T_1761) when _T_1762 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766) node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = and(decoded_addr_85_2, _T_1769) when _T_1770 : connect reg_pmp[3].addr, wdata node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_1772 = and(decoded_addr_141_2, _T_1771) when _T_1772 : node _newCfg_T_28 = shr(wdata, 32) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776) node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) node _T_1780 = and(decoded_addr_54_2, _T_1779) when _T_1780 : connect reg_pmp[4].addr, wdata node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_1782 = and(decoded_addr_141_2, _T_1781) when _T_1782 : node _newCfg_T_35 = shr(wdata, 40) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786) node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = and(decoded_addr_20_2, _T_1789) when _T_1790 : connect reg_pmp[5].addr, wdata node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_1792 = and(decoded_addr_141_2, _T_1791) when _T_1792 : node _newCfg_T_42 = shr(wdata, 48) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1796 = and(_T_1794, _T_1795) node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796) node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = and(decoded_addr_135_2, _T_1799) when _T_1800 : connect reg_pmp[6].addr, wdata node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_1802 = and(decoded_addr_141_2, _T_1801) when _T_1802 : node _newCfg_T_49 = shr(wdata, 56) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806) node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = and(decoded_addr_115_2, _T_1809) when _T_1810 : connect reg_pmp[7].addr, wdata when decoded_addr_18_2 : node _reg_custom_0_T = and(wdata, UInt<64>(0h208)) node _reg_custom_0_T_1 = not(UInt<64>(0h208)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) node _reg_custom_1_T_1 = not(UInt<64>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_38_2 : node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) node _reg_custom_2_T_1 = not(UInt<64>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_127_2 : node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) node _reg_custom_3_T_1 = not(UInt<64>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208)) node _reg_custom_0_T_5 = not(UInt<64>(0h208)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) node _reg_custom_1_T_5 = not(UInt<64>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) node _reg_custom_2_T_5 = not(UInt<64>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) node _reg_custom_3_T_5 = not(UInt<64>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_1811 = asUInt(reset) when _T_1811 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) node _T_1812 = asUInt(reset) when _T_1812 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) node _T_1813 = asUInt(reset) when _T_1813 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<39>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_1814 = asUInt(reset) when _T_1814 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_1815 = asUInt(reset) when _T_1815 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_1816 = asUInt(reset) when _T_1816 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_1817 = asUInt(reset) when _T_1817 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_1818 = asUInt(reset) when _T_1818 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_1819 = asUInt(reset) when _T_1819 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_1820 = asUInt(reset) when _T_1820 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_1821 = asUInt(reset) when _T_1821 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 63, 63) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval
module CSRFile( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [3:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value // @[CSR.scala:384:14] ); wire [63:0] _io_rw_rdata_T_298; // @[Mux.scala:30:73] reg io_status_cease_r; // @[CSR.scala:1162:31] wire io_singleStep_0; // @[CSR.scala:1001:34] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] reg reg_mstatus_mpv; // @[CSR.scala:395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [8:0] _GEN = reg_mideleg[9:1] & 9'h111; // @[CSR.scala:497:18, :498:38] wire [15:0] _GEN_0 = {6'h0, _GEN, 1'h0}; // @[CSR.scala:498:38] wire [63:0] _GEN_1 = {54'h0, _GEN, 1'h0}; // @[CSR.scala:498:38] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] _GEN_2 = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:38] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] reg reg_mip_ssip; // @[CSR.scala:504:20] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] _GEN_3 = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:32] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] _GEN_4 = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:38] reg reg_vsstatus_spp; // @[CSR.scala:562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] reg reg_wfi; // @[CSR.scala:575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] reg [5:0] small_0; // @[Counters.scala:45:41] reg [57:0] large_0; // @[Counters.scala:50:31] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] reg [5:0] small_1; // @[Counters.scala:45:41] reg [57:0] large_1; // @[Counters.scala:50:31] wire [63:0] io_time_0 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] wire [15:0] read_mip = {4'h0, io_interrupts_meip, 1'h0, reg_mip_seip | io_interrupts_seip, 1'h0, io_interrupts_mtip, 1'h0, reg_mip_stip, 1'h0, io_interrupts_msip, 1'h0, reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :606:57, :610:22] wire [15:0] _GEN_5 = reg_mie[15:0] & read_mip; // @[CSR.scala:495:20, :610:22, :614:56] wire [15:0] m_interrupts = ~(reg_mstatus_prv[1]) | reg_mstatus_mie ? ~(~_GEN_5 | _GEN_0) : 16'h0; // @[CSR.scala:395:28, :498:38, :614:56, :620:{25,51,62,83,85,105}] wire [15:0] s_interrupts = reg_mstatus_v | reg_mstatus_prv == 2'h0 | reg_mstatus_prv == 2'h1 & reg_mstatus_sie ? _GEN_5 & _GEN_0 : 16'h0; // @[CSR.scala:395:28, :498:38, :614:56, :621:{25,49,68,78,98,110,151}] wire [29:0] _GEN_6 = {reg_pmp_0_addr[28:0], reg_pmp_0_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_7 = {reg_pmp_1_addr[28:0], reg_pmp_1_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_8 = {reg_pmp_2_addr[28:0], reg_pmp_2_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_9 = {reg_pmp_3_addr[28:0], reg_pmp_3_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_10 = {reg_pmp_4_addr[28:0], reg_pmp_4_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_11 = {reg_pmp_5_addr[28:0], reg_pmp_5_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_12 = {reg_pmp_6_addr[28:0], reg_pmp_6_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] wire [29:0] _GEN_13 = {reg_pmp_7_addr[28:0], reg_pmp_7_cfg_a[0]}; // @[PMP.scala:57:31, :58:23] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [31:0] _read_mtvec_T_5 = reg_mtvec & {24'hFFFFFF, ~(reg_mtvec[0] ? 8'hFE : 8'h2)}; // @[package.scala:174:{35,37,41,46}] wire [38:0] _read_stvec_T_5 = reg_stvec & {31'h7FFFFFFF, ~(reg_stvec[0] ? 8'hFE : 8'h2)}; // @[package.scala:174:{35,37,41,46}] wire [39:0] _io_evec_T_20 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire [39:0] _read_mapping_T_6 = ~{_io_evec_T_20[39:2], _io_evec_T_20[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [39:0] _io_evec_T_10 = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [39:0] _debug_csrs_T_4 = ~{_io_evec_T_10[39:2], _io_evec_T_10[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _GEN_14 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~io_rw_addr; // @[pla.scala:78:21] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], decoded_addr_decoded_decoded_invInputs[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {io_rw_addr[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {io_rw_addr[7], io_rw_addr[8], decoded_addr_decoded_decoded_invInputs[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {io_rw_addr[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], io_rw_addr[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {io_rw_addr[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {io_rw_addr[0], io_rw_addr[1], io_rw_addr[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_invInputs[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {io_rw_addr[0], decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], io_rw_addr[4], io_rw_addr[5], decoded_addr_decoded_decoded_invInputs[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {io_rw_addr[6], io_rw_addr[7], io_rw_addr[8], io_rw_addr[9], io_rw_addr[10], decoded_addr_decoded_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_invInputs[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_invInputs[0], io_rw_addr[1], decoded_addr_decoded_decoded_invInputs[2], decoded_addr_decoded_decoded_invInputs[3], decoded_addr_decoded_decoded_invInputs[4], decoded_addr_decoded_decoded_invInputs[5], decoded_addr_decoded_decoded_invInputs[6], decoded_addr_decoded_decoded_invInputs[7], io_rw_addr[8], io_rw_addr[9], decoded_addr_decoded_decoded_invInputs[10], io_rw_addr[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [63:0] _wdata_T_2 = (io_rw_cmd[1] ? _io_rw_rdata_T_298 : 64'h0) | io_rw_wdata; // @[Mux.scala:30:73] wire [63:0] _wdata_T_6 = ~((&(io_rw_cmd[1:0])) ? io_rw_wdata : 64'h0); // @[CSR.scala:1643:{41,45,49,55}] wire system_insn = io_rw_cmd == 3'h4; // @[CSR.scala:876:31] wire [11:0] _GEN_15 = ~io_rw_addr; // @[pla.scala:78:21] wire insn_call = system_insn & (&{_GEN_15[0], _GEN_15[1], _GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], _GEN_15[8], _GEN_15[9], _GEN_15[10], _GEN_15[11]}); // @[pla.scala:78:21, :91:29, :98:{53,70}] wire insn_break = system_insn & (&{io_rw_addr[0], _GEN_15[1], _GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], _GEN_15[8], _GEN_15[9], _GEN_15[10], _GEN_15[11]}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] wire insn_ret = system_insn & (|{&{_GEN_15[2], _GEN_15[3], _GEN_15[4], _GEN_15[5], _GEN_15[6], _GEN_15[7], io_rw_addr[8], _GEN_15[10], _GEN_15[11]}, &{io_rw_addr[10], _GEN_15[11]}}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire [29:0] decoded_invInputs_1 = ~(io_decode_0_inst[31:2]); // @[pla.scala:78:21] wire [9:0] _decoded_andMatrixOutputs_T_10 = {io_decode_0_inst[22], decoded_invInputs_1[21], decoded_invInputs_1[22], decoded_invInputs_1[23], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[27], decoded_invInputs_1[28], decoded_invInputs_1[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {io_decode_0_inst[0], io_decode_0_inst[1], decoded_invInputs_1[0], decoded_invInputs_1[1], io_decode_0_inst[4], io_decode_0_inst[5], io_decode_0_inst[6], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_decode_0_inst[25], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[27], decoded_invInputs_1[28], decoded_invInputs_1[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] _decoded_orMatrixOutputs_T_10 = {&{io_decode_0_inst[0], decoded_invInputs_1[20], decoded_invInputs_1[21], decoded_invInputs_1[22], decoded_invInputs_1[23], decoded_invInputs_1[24], decoded_invInputs_1[25], io_decode_0_inst[28], decoded_invInputs_1[28], decoded_invInputs_1[29]}, &{io_decode_0_inst[30], decoded_invInputs_1[29]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] wire is_counter = io_decode_0_inst[31:20] > 12'hBFF & io_decode_0_inst[31:20] < 12'hC20 | io_decode_0_inst[31:20] > 12'hC7F & io_decode_0_inst[31:20] < 12'hCA0; // @[package.scala:213:{47,55,60}] wire allow_sfence_vma = reg_mstatus_prv[1] | ~(~reg_mstatus_v & reg_mstatus_tvm); // @[CSR.scala:395:28, :906:61, :907:{70,73,77}] wire [31:0] _GEN_16 = {27'h0, io_decode_0_inst[24:20]}; // @[CSR.scala:897:27, :911:28, :912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3 = _GEN_3 >> _GEN_16; // @[CSR.scala:532:32, :912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_11 = _GEN_4 >> _GEN_16; // @[CSR.scala:536:38, :912:70, :913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_6 = 32'h0 >> _GEN_16; // @[CSR.scala:912:70, :914:63] wire io_decode_0_fp_illegal_0 = reg_mstatus_fs == 2'h0 | reg_mstatus_v | ~(reg_misa[5]); // @[CSR.scala:395:28, :648:25, :915:{39,47,91,94,103}] wire [3:0] io_decode_0_fp_csr_invInputs = ~(io_decode_0_inst[31:28]); // @[pla.scala:78:21] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_invInputs[0], io_decode_0_fp_csr_invInputs[1], io_decode_0_fp_csr_invInputs[2], io_decode_0_fp_csr_invInputs[3]}; // @[pla.scala:78:21, :91:29, :98:53] wire _io_decode_0_virtual_access_illegal_T_24 = io_decode_0_inst[31:20] == 12'h180; // @[CSR.scala:897:27, :899:93] wire csr_exists = io_decode_0_inst[31:20] == 12'h7A0 | io_decode_0_inst[31:20] == 12'h7A1 | io_decode_0_inst[31:20] == 12'h7A2 | io_decode_0_inst[31:20] == 12'h7A3 | io_decode_0_inst[31:20] == 12'h301 | io_decode_0_inst[31:20] == 12'h300 | io_decode_0_inst[31:20] == 12'h305 | io_decode_0_inst[31:20] == 12'h344 | io_decode_0_inst[31:20] == 12'h304 | io_decode_0_inst[31:20] == 12'h340 | io_decode_0_inst[31:20] == 12'h341 | io_decode_0_inst[31:20] == 12'h343 | io_decode_0_inst[31:20] == 12'h342 | io_decode_0_inst[31:20] == 12'hF14 | io_decode_0_inst[31:20] == 12'h7B0 | io_decode_0_inst[31:20] == 12'h7B1 | io_decode_0_inst[31:20] == 12'h7B2 | io_decode_0_inst[31:20] == 12'h1 | io_decode_0_inst[31:20] == 12'h2 | io_decode_0_inst[31:20] == 12'h3 | io_decode_0_inst[31:20] == 12'h320 | io_decode_0_inst[31:20] == 12'hB00 | io_decode_0_inst[31:20] == 12'hB02 | io_decode_0_inst[31:20] == 12'h323 | io_decode_0_inst[31:20] == 12'hB03 | io_decode_0_inst[31:20] == 12'hC03 | io_decode_0_inst[31:20] == 12'h324 | io_decode_0_inst[31:20] == 12'hB04 | io_decode_0_inst[31:20] == 12'hC04 | io_decode_0_inst[31:20] == 12'h325 | io_decode_0_inst[31:20] == 12'hB05 | io_decode_0_inst[31:20] == 12'hC05 | io_decode_0_inst[31:20] == 12'h326 | io_decode_0_inst[31:20] == 12'hB06 | io_decode_0_inst[31:20] == 12'hC06 | io_decode_0_inst[31:20] == 12'h327 | io_decode_0_inst[31:20] == 12'hB07 | io_decode_0_inst[31:20] == 12'hC07 | io_decode_0_inst[31:20] == 12'h328 | io_decode_0_inst[31:20] == 12'hB08 | io_decode_0_inst[31:20] == 12'hC08 | io_decode_0_inst[31:20] == 12'h329 | io_decode_0_inst[31:20] == 12'hB09 | io_decode_0_inst[31:20] == 12'hC09 | io_decode_0_inst[31:20] == 12'h32A | io_decode_0_inst[31:20] == 12'hB0A | io_decode_0_inst[31:20] == 12'hC0A | io_decode_0_inst[31:20] == 12'h32B | io_decode_0_inst[31:20] == 12'hB0B | io_decode_0_inst[31:20] == 12'hC0B | io_decode_0_inst[31:20] == 12'h32C | io_decode_0_inst[31:20] == 12'hB0C | io_decode_0_inst[31:20] == 12'hC0C | io_decode_0_inst[31:20] == 12'h32D | io_decode_0_inst[31:20] == 12'hB0D | io_decode_0_inst[31:20] == 12'hC0D | io_decode_0_inst[31:20] == 12'h32E | io_decode_0_inst[31:20] == 12'hB0E | io_decode_0_inst[31:20] == 12'hC0E | io_decode_0_inst[31:20] == 12'h32F | io_decode_0_inst[31:20] == 12'hB0F | io_decode_0_inst[31:20] == 12'hC0F | io_decode_0_inst[31:20] == 12'h330 | io_decode_0_inst[31:20] == 12'hB10 | io_decode_0_inst[31:20] == 12'hC10 | io_decode_0_inst[31:20] == 12'h331 | io_decode_0_inst[31:20] == 12'hB11 | io_decode_0_inst[31:20] == 12'hC11 | io_decode_0_inst[31:20] == 12'h332 | io_decode_0_inst[31:20] == 12'hB12 | io_decode_0_inst[31:20] == 12'hC12 | io_decode_0_inst[31:20] == 12'h333 | io_decode_0_inst[31:20] == 12'hB13 | io_decode_0_inst[31:20] == 12'hC13 | io_decode_0_inst[31:20] == 12'h334 | io_decode_0_inst[31:20] == 12'hB14 | io_decode_0_inst[31:20] == 12'hC14 | io_decode_0_inst[31:20] == 12'h335 | io_decode_0_inst[31:20] == 12'hB15 | io_decode_0_inst[31:20] == 12'hC15 | io_decode_0_inst[31:20] == 12'h336 | io_decode_0_inst[31:20] == 12'hB16 | io_decode_0_inst[31:20] == 12'hC16 | io_decode_0_inst[31:20] == 12'h337 | io_decode_0_inst[31:20] == 12'hB17 | io_decode_0_inst[31:20] == 12'hC17 | io_decode_0_inst[31:20] == 12'h338 | io_decode_0_inst[31:20] == 12'hB18 | io_decode_0_inst[31:20] == 12'hC18 | io_decode_0_inst[31:20] == 12'h339 | io_decode_0_inst[31:20] == 12'hB19 | io_decode_0_inst[31:20] == 12'hC19 | io_decode_0_inst[31:20] == 12'h33A | io_decode_0_inst[31:20] == 12'hB1A | io_decode_0_inst[31:20] == 12'hC1A | io_decode_0_inst[31:20] == 12'h33B | io_decode_0_inst[31:20] == 12'hB1B | io_decode_0_inst[31:20] == 12'hC1B | io_decode_0_inst[31:20] == 12'h33C | io_decode_0_inst[31:20] == 12'hB1C | io_decode_0_inst[31:20] == 12'hC1C | io_decode_0_inst[31:20] == 12'h33D | io_decode_0_inst[31:20] == 12'hB1D | io_decode_0_inst[31:20] == 12'hC1D | io_decode_0_inst[31:20] == 12'h33E | io_decode_0_inst[31:20] == 12'hB1E | io_decode_0_inst[31:20] == 12'hC1E | io_decode_0_inst[31:20] == 12'h33F | io_decode_0_inst[31:20] == 12'hB1F | io_decode_0_inst[31:20] == 12'hC1F | io_decode_0_inst[31:20] == 12'h306 | io_decode_0_inst[31:20] == 12'hC00 | io_decode_0_inst[31:20] == 12'hC02 | io_decode_0_inst[31:20] == 12'h30A | io_decode_0_inst[31:20] == 12'h100 | io_decode_0_inst[31:20] == 12'h144 | io_decode_0_inst[31:20] == 12'h104 | io_decode_0_inst[31:20] == 12'h140 | io_decode_0_inst[31:20] == 12'h142 | io_decode_0_inst[31:20] == 12'h143 | _io_decode_0_virtual_access_illegal_T_24 | io_decode_0_inst[31:20] == 12'h141 | io_decode_0_inst[31:20] == 12'h105 | io_decode_0_inst[31:20] == 12'h106 | io_decode_0_inst[31:20] == 12'h303 | io_decode_0_inst[31:20] == 12'h302 | io_decode_0_inst[31:20] == 12'h10A | io_decode_0_inst[31:20] == 12'h3A0 | io_decode_0_inst[31:20] == 12'h3A2 | io_decode_0_inst[31:20] == 12'h3B0 | io_decode_0_inst[31:20] == 12'h3B1 | io_decode_0_inst[31:20] == 12'h3B2 | io_decode_0_inst[31:20] == 12'h3B3 | io_decode_0_inst[31:20] == 12'h3B4 | io_decode_0_inst[31:20] == 12'h3B5 | io_decode_0_inst[31:20] == 12'h3B6 | io_decode_0_inst[31:20] == 12'h3B7 | io_decode_0_inst[31:20] == 12'h3B8 | io_decode_0_inst[31:20] == 12'h3B9 | io_decode_0_inst[31:20] == 12'h3BA | io_decode_0_inst[31:20] == 12'h3BB | io_decode_0_inst[31:20] == 12'h3BC | io_decode_0_inst[31:20] == 12'h3BD | io_decode_0_inst[31:20] == 12'h3BE | io_decode_0_inst[31:20] == 12'h3BF | io_decode_0_inst[31:20] == 12'h7C1 | io_decode_0_inst[31:20] == 12'hF12 | io_decode_0_inst[31:20] == 12'hF11 | io_decode_0_inst[31:20] == 12'hF13 | io_decode_0_inst[31:20] == 12'hF15; // @[CSR.scala:897:27, :899:{93,111}] wire _io_decode_0_system_illegal_T = reg_mstatus_prv < io_decode_0_inst[29:28]; // @[CSR.scala:190:36, :395:28, :897:27, :920:42, :923:28] wire [5:0] io_decode_0_read_illegal_invInputs = ~(io_decode_0_inst[31:26]); // @[pla.scala:78:21] wire [11:0] io_decode_0_write_flush_addr_m = {io_decode_0_inst[31:30], io_decode_0_inst[29:20] | 10'h300}; // @[CSR.scala:897:27, :932:25] wire [63:0] cause = insn_call ? {60'h0, {2'h0, reg_mstatus_prv[0] & reg_mstatus_v ? 2'h2 : reg_mstatus_prv} - 4'h8} : insn_break ? 64'h3 : io_cause; // @[CSR.scala:395:28, :893:83, :945:105, :959:{8,40,45,65}, :960:14] wire _causeIsDebugTrigger_T_2 = cause[7:0] == 8'hE; // @[CSR.scala:959:8, :961:25, :963:53] wire causeIsDebugInt = cause[63] & _causeIsDebugTrigger_T_2; // @[CSR.scala:959:8, :963:{30,39,53}] wire causeIsDebugTrigger = ~(cause[63]) & _causeIsDebugTrigger_T_2; // @[CSR.scala:959:8, :963:{30,53}, :964:{29,44}] wire [3:0] _causeIsDebugBreak_T_4 = {reg_dcsr_ebreakm, 1'h0, reg_dcsr_ebreaks, reg_dcsr_ebreaku} >> reg_mstatus_prv; // @[CSR.scala:395:28, :403:25, :965:{62,134}] wire trapToDebug = reg_singleStepped | causeIsDebugInt | causeIsDebugTrigger | ~(cause[63]) & insn_break & _causeIsDebugBreak_T_4[0] | reg_debug; // @[CSR.scala:482:26, :486:30, :893:83, :959:8, :963:{30,39}, :964:44, :965:{27,42,56,134}, :966:{56,75,98,119}] wire [63:0] _GEN_17 = {58'h0, cause[5:0]}; // @[CSR.scala:959:8, :962:31, :970:100] wire [63:0] _delegate_T_3 = _GEN_1 >> _GEN_17; // @[CSR.scala:498:38, :970:100] wire [63:0] _delegate_T_5 = _GEN_2 >> _GEN_17; // @[CSR.scala:502:38, :970:{100,132}] wire delegate = ~(reg_mstatus_prv[1]) & (cause[63] ? _delegate_T_3[0] : _delegate_T_5[0]); // @[CSR.scala:395:28, :620:51, :959:8, :963:30, :970:{66,72,100,132}] wire [63:0] _delegateVS_T_2 = 64'h0 >> _GEN_17; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_4 = 64'h0 >> _GEN_17; // @[CSR.scala:970:100, :971:112] wire delegateVS = reg_mstatus_v & delegate & (cause[63] ? _delegateVS_T_2[0] : _delegateVS_T_4[0]); // @[CSR.scala:395:28, :959:8, :963:30, :970:66, :971:{34,46,52,80,112}] wire [39:0] notDebugTVec_base = delegate ? (delegateVS ? 40'h0 : {reg_stvec[38], _read_stvec_T_5}) : {8'h0, _read_mtvec_T_5}; // @[package.scala:132:{15,38}, :138:15, :174:35] wire _exception_T = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] assign io_singleStep_0 = reg_dcsr_step & ~reg_debug; // @[CSR.scala:403:25, :482:26, :927:45, :1001:34] wire exception = _exception_T | io_exception; // @[CSR.scala:1000:24, :1020:43]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_57 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = and(_T_139, _T_144) node _T_146 = or(UInt<1>(0h0), _T_145) node _T_147 = and(_T_138, _T_146) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_147, UInt<1>(0h1), "") : assert_2 node _T_151 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_152 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = or(UInt<1>(0h0), _T_153) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = and(_T_154, _T_159) node _T_161 = or(UInt<1>(0h0), _T_160) node _T_162 = and(UInt<1>(0h0), _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_162, UInt<1>(0h1), "") : assert_3 node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(source_ok, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_169 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_169, UInt<1>(0h1), "") : assert_5 node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(is_aligned, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_176 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_176, UInt<1>(0h1), "") : assert_7 node _T_180 = not(io.in.a.bits.mask) node _T_181 = eq(_T_180, UInt<1>(0h0)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_181, UInt<1>(0h1), "") : assert_8 node _T_185 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_185, UInt<1>(0h1), "") : assert_9 node _T_189 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_189 : node _T_190 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_191 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_194 = shr(io.in.a.bits.source, 2) node _T_195 = eq(_T_194, UInt<1>(0h0)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_8) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_199 = and(_T_197, _T_198) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_200 = shr(io.in.a.bits.source, 2) node _T_201 = eq(_T_200, UInt<1>(0h1)) node _T_202 = leq(UInt<1>(0h0), uncommonBits_9) node _T_203 = and(_T_201, _T_202) node _T_204 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_205 = and(_T_203, _T_204) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<2>(0h2)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_10) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<2>(0h3)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_11) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_219 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_220 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_221 = or(_T_193, _T_199) node _T_222 = or(_T_221, _T_205) node _T_223 = or(_T_222, _T_211) node _T_224 = or(_T_223, _T_217) node _T_225 = or(_T_224, _T_218) node _T_226 = or(_T_225, _T_219) node _T_227 = or(_T_226, _T_220) node _T_228 = and(_T_192, _T_227) node _T_229 = or(UInt<1>(0h0), _T_228) node _T_230 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_231 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = and(_T_230, _T_235) node _T_237 = or(UInt<1>(0h0), _T_236) node _T_238 = and(_T_229, _T_237) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_238, UInt<1>(0h1), "") : assert_10 node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_244 = and(_T_242, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(UInt<1>(0h0), _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_253, UInt<1>(0h1), "") : assert_11 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(source_ok, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_260, UInt<1>(0h1), "") : assert_13 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(is_aligned, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_267, UInt<1>(0h1), "") : assert_15 node _T_271 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : node _T_274 = eq(_T_271, UInt<1>(0h0)) when _T_274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_271, UInt<1>(0h1), "") : assert_16 node _T_275 = not(io.in.a.bits.mask) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_276, UInt<1>(0h1), "") : assert_17 node _T_280 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(_T_280, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_280, UInt<1>(0h1), "") : assert_18 node _T_284 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_284 : node _T_285 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_286 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_287 = and(_T_285, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_289 = shr(io.in.a.bits.source, 2) node _T_290 = eq(_T_289, UInt<1>(0h0)) node _T_291 = leq(UInt<1>(0h0), uncommonBits_12) node _T_292 = and(_T_290, _T_291) node _T_293 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_294 = and(_T_292, _T_293) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_295 = shr(io.in.a.bits.source, 2) node _T_296 = eq(_T_295, UInt<1>(0h1)) node _T_297 = leq(UInt<1>(0h0), uncommonBits_13) node _T_298 = and(_T_296, _T_297) node _T_299 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_300 = and(_T_298, _T_299) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<2>(0h2)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_14) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<2>(0h3)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_15) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_315 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_316 = or(_T_288, _T_294) node _T_317 = or(_T_316, _T_300) node _T_318 = or(_T_317, _T_306) node _T_319 = or(_T_318, _T_312) node _T_320 = or(_T_319, _T_313) node _T_321 = or(_T_320, _T_314) node _T_322 = or(_T_321, _T_315) node _T_323 = and(_T_287, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_324, UInt<1>(0h1), "") : assert_19 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = and(_T_331, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_338, UInt<1>(0h1), "") : assert_20 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(source_ok, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(is_aligned, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_348 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_348, UInt<1>(0h1), "") : assert_23 node _T_352 = eq(io.in.a.bits.mask, mask) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_352, UInt<1>(0h1), "") : assert_24 node _T_356 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_356, UInt<1>(0h1), "") : assert_25 node _T_360 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_360 : node _T_361 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_362 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_365 = shr(io.in.a.bits.source, 2) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_16) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_370 = and(_T_368, _T_369) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_371 = shr(io.in.a.bits.source, 2) node _T_372 = eq(_T_371, UInt<1>(0h1)) node _T_373 = leq(UInt<1>(0h0), uncommonBits_17) node _T_374 = and(_T_372, _T_373) node _T_375 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_377 = shr(io.in.a.bits.source, 2) node _T_378 = eq(_T_377, UInt<2>(0h2)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_18) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_382 = and(_T_380, _T_381) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_383 = shr(io.in.a.bits.source, 2) node _T_384 = eq(_T_383, UInt<2>(0h3)) node _T_385 = leq(UInt<1>(0h0), uncommonBits_19) node _T_386 = and(_T_384, _T_385) node _T_387 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_390 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_391 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_392 = or(_T_364, _T_370) node _T_393 = or(_T_392, _T_376) node _T_394 = or(_T_393, _T_382) node _T_395 = or(_T_394, _T_388) node _T_396 = or(_T_395, _T_389) node _T_397 = or(_T_396, _T_390) node _T_398 = or(_T_397, _T_391) node _T_399 = and(_T_363, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_402 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_403 = and(_T_401, _T_402) node _T_404 = or(UInt<1>(0h0), _T_403) node _T_405 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<13>(0h1000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = and(_T_404, _T_409) node _T_411 = or(UInt<1>(0h0), _T_410) node _T_412 = and(_T_400, _T_411) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_412, UInt<1>(0h1), "") : assert_26 node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(source_ok, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_422 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_422, UInt<1>(0h1), "") : assert_29 node _T_426 = eq(io.in.a.bits.mask, mask) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_426, UInt<1>(0h1), "") : assert_30 node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_430 : node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_435 = shr(io.in.a.bits.source, 2) node _T_436 = eq(_T_435, UInt<1>(0h0)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_20) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_441 = shr(io.in.a.bits.source, 2) node _T_442 = eq(_T_441, UInt<1>(0h1)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_21) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<2>(0h2)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_22) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_453 = shr(io.in.a.bits.source, 2) node _T_454 = eq(_T_453, UInt<2>(0h3)) node _T_455 = leq(UInt<1>(0h0), uncommonBits_23) node _T_456 = and(_T_454, _T_455) node _T_457 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_461 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_462 = or(_T_434, _T_440) node _T_463 = or(_T_462, _T_446) node _T_464 = or(_T_463, _T_452) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = or(_T_466, _T_460) node _T_468 = or(_T_467, _T_461) node _T_469 = and(_T_433, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_472 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_473 = and(_T_471, _T_472) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<13>(0h1000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = and(_T_474, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = and(_T_470, _T_481) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_482, UInt<1>(0h1), "") : assert_31 node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(source_ok, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(is_aligned, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_492, UInt<1>(0h1), "") : assert_34 node _T_496 = not(mask) node _T_497 = and(io.in.a.bits.mask, _T_496) node _T_498 = eq(_T_497, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_498, UInt<1>(0h1), "") : assert_35 node _T_502 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_502 : node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<1>(0h0)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_24) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<1>(0h1)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_25) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<2>(0h2)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_26) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<2>(0h3)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_27) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_533 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_534 = or(_T_506, _T_512) node _T_535 = or(_T_534, _T_518) node _T_536 = or(_T_535, _T_524) node _T_537 = or(_T_536, _T_530) node _T_538 = or(_T_537, _T_531) node _T_539 = or(_T_538, _T_532) node _T_540 = or(_T_539, _T_533) node _T_541 = and(_T_505, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = and(_T_543, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = and(_T_542, _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_551, UInt<1>(0h1), "") : assert_36 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(source_ok, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_558 = asUInt(reset) node _T_559 = eq(_T_558, UInt<1>(0h0)) when _T_559 : node _T_560 = eq(is_aligned, UInt<1>(0h0)) when _T_560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_561 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_561, UInt<1>(0h1), "") : assert_39 node _T_565 = eq(io.in.a.bits.mask, mask) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_565, UInt<1>(0h1), "") : assert_40 node _T_569 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_569 : node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_574 = shr(io.in.a.bits.source, 2) node _T_575 = eq(_T_574, UInt<1>(0h0)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_28) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h1)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_29) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<2>(0h2)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_30) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h3)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_31) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_600 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_601 = or(_T_573, _T_579) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_591) node _T_604 = or(_T_603, _T_597) node _T_605 = or(_T_604, _T_598) node _T_606 = or(_T_605, _T_599) node _T_607 = or(_T_606, _T_600) node _T_608 = and(_T_572, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_611 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_612 = cvt(_T_611) node _T_613 = and(_T_612, asSInt(UInt<13>(0h1000))) node _T_614 = asSInt(_T_613) node _T_615 = eq(_T_614, asSInt(UInt<1>(0h0))) node _T_616 = and(_T_610, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = and(_T_609, _T_617) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_618, UInt<1>(0h1), "") : assert_41 node _T_622 = asUInt(reset) node _T_623 = eq(_T_622, UInt<1>(0h0)) when _T_623 : node _T_624 = eq(source_ok, UInt<1>(0h0)) when _T_624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(is_aligned, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_628 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_628, UInt<1>(0h1), "") : assert_44 node _T_632 = eq(io.in.a.bits.mask, mask) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_632, UInt<1>(0h1), "") : assert_45 node _T_636 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_636 : node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_639 = and(_T_637, _T_638) node _T_640 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<1>(0h0)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_32) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_647 = shr(io.in.a.bits.source, 2) node _T_648 = eq(_T_647, UInt<1>(0h1)) node _T_649 = leq(UInt<1>(0h0), uncommonBits_33) node _T_650 = and(_T_648, _T_649) node _T_651 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_652 = and(_T_650, _T_651) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_653 = shr(io.in.a.bits.source, 2) node _T_654 = eq(_T_653, UInt<2>(0h2)) node _T_655 = leq(UInt<1>(0h0), uncommonBits_34) node _T_656 = and(_T_654, _T_655) node _T_657 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_658 = and(_T_656, _T_657) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_659 = shr(io.in.a.bits.source, 2) node _T_660 = eq(_T_659, UInt<2>(0h3)) node _T_661 = leq(UInt<1>(0h0), uncommonBits_35) node _T_662 = and(_T_660, _T_661) node _T_663 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_667 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_668 = or(_T_640, _T_646) node _T_669 = or(_T_668, _T_652) node _T_670 = or(_T_669, _T_658) node _T_671 = or(_T_670, _T_664) node _T_672 = or(_T_671, _T_665) node _T_673 = or(_T_672, _T_666) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_639, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = and(_T_677, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = and(_T_676, _T_684) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_685, UInt<1>(0h1), "") : assert_46 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(source_ok, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(is_aligned, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_695 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_695, UInt<1>(0h1), "") : assert_49 node _T_699 = eq(io.in.a.bits.mask, mask) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_699, UInt<1>(0h1), "") : assert_50 node _T_703 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_703, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_707 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_707, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_711 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(source_ok_1, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_715 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_715, UInt<1>(0h1), "") : assert_54 node _T_719 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_719, UInt<1>(0h1), "") : assert_55 node _T_723 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_723, UInt<1>(0h1), "") : assert_56 node _T_727 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_727, UInt<1>(0h1), "") : assert_57 node _T_731 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_731 : node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok_1, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(sink_ok, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_738 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_738, UInt<1>(0h1), "") : assert_60 node _T_742 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_742, UInt<1>(0h1), "") : assert_61 node _T_746 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_746, UInt<1>(0h1), "") : assert_62 node _T_750 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_750, UInt<1>(0h1), "") : assert_63 node _T_754 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_755, UInt<1>(0h1), "") : assert_64 node _T_759 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_759 : node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(source_ok_1, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(sink_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_766 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_767 = asUInt(reset) node _T_768 = eq(_T_767, UInt<1>(0h0)) when _T_768 : node _T_769 = eq(_T_766, UInt<1>(0h0)) when _T_769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_766, UInt<1>(0h1), "") : assert_67 node _T_770 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(_T_770, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_770, UInt<1>(0h1), "") : assert_68 node _T_774 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_774, UInt<1>(0h1), "") : assert_69 node _T_778 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_779 = or(_T_778, io.in.d.bits.corrupt) node _T_780 = asUInt(reset) node _T_781 = eq(_T_780, UInt<1>(0h0)) when _T_781 : node _T_782 = eq(_T_779, UInt<1>(0h0)) when _T_782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_779, UInt<1>(0h1), "") : assert_70 node _T_783 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_784 = or(UInt<1>(0h0), _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_784, UInt<1>(0h1), "") : assert_71 node _T_788 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_788 : node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(source_ok_1, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_792 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(_T_792, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_792, UInt<1>(0h1), "") : assert_73 node _T_796 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_796, UInt<1>(0h1), "") : assert_74 node _T_800 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_801, UInt<1>(0h1), "") : assert_75 node _T_805 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_805 : node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(source_ok_1, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_809 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_809, UInt<1>(0h1), "") : assert_77 node _T_813 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_814 = or(_T_813, io.in.d.bits.corrupt) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_814, UInt<1>(0h1), "") : assert_78 node _T_818 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_819, UInt<1>(0h1), "") : assert_79 node _T_823 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_823 : node _T_824 = asUInt(reset) node _T_825 = eq(_T_824, UInt<1>(0h0)) when _T_825 : node _T_826 = eq(source_ok_1, UInt<1>(0h0)) when _T_826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_827 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(_T_827, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_827, UInt<1>(0h1), "") : assert_81 node _T_831 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_831, UInt<1>(0h1), "") : assert_82 node _T_835 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_836, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_840 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_840, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_844 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_844, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_848 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_848, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_852 = eq(a_first, UInt<1>(0h0)) node _T_853 = and(io.in.a.valid, _T_852) when _T_853 : node _T_854 = eq(io.in.a.bits.opcode, opcode) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_854, UInt<1>(0h1), "") : assert_87 node _T_858 = eq(io.in.a.bits.param, param) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_858, UInt<1>(0h1), "") : assert_88 node _T_862 = eq(io.in.a.bits.size, size) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_862, UInt<1>(0h1), "") : assert_89 node _T_866 = eq(io.in.a.bits.source, source) node _T_867 = asUInt(reset) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : node _T_869 = eq(_T_866, UInt<1>(0h0)) when _T_869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_866, UInt<1>(0h1), "") : assert_90 node _T_870 = eq(io.in.a.bits.address, address) node _T_871 = asUInt(reset) node _T_872 = eq(_T_871, UInt<1>(0h0)) when _T_872 : node _T_873 = eq(_T_870, UInt<1>(0h0)) when _T_873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_870, UInt<1>(0h1), "") : assert_91 node _T_874 = and(io.in.a.ready, io.in.a.valid) node _T_875 = and(_T_874, a_first) when _T_875 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_876 = eq(d_first, UInt<1>(0h0)) node _T_877 = and(io.in.d.valid, _T_876) when _T_877 : node _T_878 = eq(io.in.d.bits.opcode, opcode_1) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_878, UInt<1>(0h1), "") : assert_92 node _T_882 = eq(io.in.d.bits.param, param_1) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_882, UInt<1>(0h1), "") : assert_93 node _T_886 = eq(io.in.d.bits.size, size_1) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_886, UInt<1>(0h1), "") : assert_94 node _T_890 = eq(io.in.d.bits.source, source_1) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_890, UInt<1>(0h1), "") : assert_95 node _T_894 = eq(io.in.d.bits.sink, sink) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_894, UInt<1>(0h1), "") : assert_96 node _T_898 = eq(io.in.d.bits.denied, denied) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_898, UInt<1>(0h1), "") : assert_97 node _T_902 = and(io.in.d.ready, io.in.d.valid) node _T_903 = and(_T_902, d_first) when _T_903 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_904 = and(io.in.a.valid, a_first_1) node _T_905 = and(_T_904, UInt<1>(0h1)) when _T_905 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_906 = and(io.in.a.ready, io.in.a.valid) node _T_907 = and(_T_906, a_first_1) node _T_908 = and(_T_907, UInt<1>(0h1)) when _T_908 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_909 = dshr(inflight, io.in.a.bits.source) node _T_910 = bits(_T_909, 0, 0) node _T_911 = eq(_T_910, UInt<1>(0h0)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_911, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_915 = and(io.in.d.valid, d_first_1) node _T_916 = and(_T_915, UInt<1>(0h1)) node _T_917 = eq(d_release_ack, UInt<1>(0h0)) node _T_918 = and(_T_916, _T_917) when _T_918 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_919 = and(io.in.d.ready, io.in.d.valid) node _T_920 = and(_T_919, d_first_1) node _T_921 = and(_T_920, UInt<1>(0h1)) node _T_922 = eq(d_release_ack, UInt<1>(0h0)) node _T_923 = and(_T_921, _T_922) when _T_923 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_924 = and(io.in.d.valid, d_first_1) node _T_925 = and(_T_924, UInt<1>(0h1)) node _T_926 = eq(d_release_ack, UInt<1>(0h0)) node _T_927 = and(_T_925, _T_926) when _T_927 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_928 = dshr(inflight, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_930, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_934 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_935 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_936 = or(_T_934, _T_935) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_936, UInt<1>(0h1), "") : assert_100 node _T_940 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_940, UInt<1>(0h1), "") : assert_101 else : node _T_944 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_945 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_946 = or(_T_944, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_946, UInt<1>(0h1), "") : assert_102 node _T_950 = eq(io.in.d.bits.size, a_size_lookup) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_950, UInt<1>(0h1), "") : assert_103 node _T_954 = and(io.in.d.valid, d_first_1) node _T_955 = and(_T_954, a_first_1) node _T_956 = and(_T_955, io.in.a.valid) node _T_957 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_958 = and(_T_956, _T_957) node _T_959 = eq(d_release_ack, UInt<1>(0h0)) node _T_960 = and(_T_958, _T_959) when _T_960 : node _T_961 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_962 = or(_T_961, io.in.a.ready) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_962, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_117 node _T_966 = orr(inflight) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_969 = or(_T_967, _T_968) node _T_970 = lt(watchdog, plusarg_reader.out) node _T_971 = or(_T_969, _T_970) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_971, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_975 = and(io.in.a.ready, io.in.a.valid) node _T_976 = and(io.in.d.ready, io.in.d.valid) node _T_977 = or(_T_975, _T_976) when _T_977 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_978 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_979 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_980 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_981 = and(_T_979, _T_980) node _T_982 = and(_T_978, _T_981) when _T_982 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_983 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_984 = and(_T_983, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_985 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_986 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_987 = and(_T_985, _T_986) node _T_988 = and(_T_984, _T_987) when _T_988 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_989 = dshr(inflight_1, _WIRE_15.bits.source) node _T_990 = bits(_T_989, 0, 0) node _T_991 = eq(_T_990, UInt<1>(0h0)) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_991, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_995 = and(io.in.d.valid, d_first_2) node _T_996 = and(_T_995, UInt<1>(0h1)) node _T_997 = and(_T_996, d_release_ack_1) when _T_997 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_998 = and(io.in.d.ready, io.in.d.valid) node _T_999 = and(_T_998, d_first_2) node _T_1000 = and(_T_999, UInt<1>(0h1)) node _T_1001 = and(_T_1000, d_release_ack_1) when _T_1001 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1002 = and(io.in.d.valid, d_first_2) node _T_1003 = and(_T_1002, UInt<1>(0h1)) node _T_1004 = and(_T_1003, d_release_ack_1) when _T_1004 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1005 = dshr(inflight_1, io.in.d.bits.source) node _T_1006 = bits(_T_1005, 0, 0) node _T_1007 = or(_T_1006, same_cycle_resp_1) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1011 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_108 else : node _T_1015 = eq(io.in.d.bits.size, c_size_lookup) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_109 node _T_1019 = and(io.in.d.valid, d_first_2) node _T_1020 = and(_T_1019, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1021 = and(_T_1020, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1022 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = and(_T_1023, d_release_ack_1) node _T_1025 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1028 = or(_T_1027, _WIRE_23.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_118 node _T_1032 = orr(inflight_1) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) node _T_1034 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = lt(watchdog_1, plusarg_reader_1.out) node _T_1037 = or(_T_1035, _T_1036) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1041 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1042 = and(io.in.d.ready, io.in.d.valid) node _T_1043 = or(_T_1041, _T_1042) when _T_1043 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_129 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_129 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_23 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_9 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_9 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_10 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_10 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_11 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_11 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_12 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_12 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_13 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_13 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_14 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_14 : connect states[7].g, UInt<3>(0h2) node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_15 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_15 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_16 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_16 : connect states[9].g, UInt<3>(0h2) node _T_17 = and(io.router_req.ready, io.router_req.valid) when _T_17 : node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_22 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_23 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_24 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_25 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_26 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_27 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_28 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_29 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_30 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_30 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_31 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_31 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_32 = and(io.router_req.ready, io.router_req.valid) when _T_32 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_33 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_34 = or(_T_33, vcalloc_vals[2]) node _T_35 = or(_T_34, vcalloc_vals[3]) node _T_36 = or(_T_35, vcalloc_vals[4]) node _T_37 = or(_T_36, vcalloc_vals[5]) node _T_38 = or(_T_37, vcalloc_vals[6]) node _T_39 = or(_T_38, vcalloc_vals[7]) node _T_40 = or(_T_39, vcalloc_vals[8]) node _T_41 = or(_T_40, vcalloc_vals[9]) when _T_41 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_20 : UInt<1> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375) node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376) node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377) node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378) node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379) node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389 connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>[10] node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391) node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392) node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393) node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394) node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395) node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_408 connect _io_vcalloc_req_bits_WIRE_24[0], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410) node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_24[1], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435) node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436) node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446 connect _io_vcalloc_req_bits_WIRE_24[2], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450) node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451) node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452) node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453) node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454) node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455) node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465 connect _io_vcalloc_req_bits_WIRE_24[3], _io_vcalloc_req_bits_WIRE_28 node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467) node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468) node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469) node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470) node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475) wire _io_vcalloc_req_bits_WIRE_29 : UInt<1> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484 connect _io_vcalloc_req_bits_WIRE_24[4], _io_vcalloc_req_bits_WIRE_29 node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503 connect _io_vcalloc_req_bits_WIRE_24[5], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_512 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_513 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_504, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_518 = or(_io_vcalloc_req_bits_T_517, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_519 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_510) node _io_vcalloc_req_bits_T_520 = or(_io_vcalloc_req_bits_T_519, _io_vcalloc_req_bits_T_511) node _io_vcalloc_req_bits_T_521 = or(_io_vcalloc_req_bits_T_520, _io_vcalloc_req_bits_T_512) node _io_vcalloc_req_bits_T_522 = or(_io_vcalloc_req_bits_T_521, _io_vcalloc_req_bits_T_513) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_522 connect _io_vcalloc_req_bits_WIRE_24[6], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_527 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_528 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_529 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_530 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_531 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_532 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_533 = or(_io_vcalloc_req_bits_T_523, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_534 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_525) node _io_vcalloc_req_bits_T_535 = or(_io_vcalloc_req_bits_T_534, _io_vcalloc_req_bits_T_526) node _io_vcalloc_req_bits_T_536 = or(_io_vcalloc_req_bits_T_535, _io_vcalloc_req_bits_T_527) node _io_vcalloc_req_bits_T_537 = or(_io_vcalloc_req_bits_T_536, _io_vcalloc_req_bits_T_528) node _io_vcalloc_req_bits_T_538 = or(_io_vcalloc_req_bits_T_537, _io_vcalloc_req_bits_T_529) node _io_vcalloc_req_bits_T_539 = or(_io_vcalloc_req_bits_T_538, _io_vcalloc_req_bits_T_530) node _io_vcalloc_req_bits_T_540 = or(_io_vcalloc_req_bits_T_539, _io_vcalloc_req_bits_T_531) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_540, _io_vcalloc_req_bits_T_532) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_541 connect _io_vcalloc_req_bits_WIRE_24[7], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_542 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_543 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_544 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_545 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_546 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_547 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_543) node _io_vcalloc_req_bits_T_553 = or(_io_vcalloc_req_bits_T_552, _io_vcalloc_req_bits_T_544) node _io_vcalloc_req_bits_T_554 = or(_io_vcalloc_req_bits_T_553, _io_vcalloc_req_bits_T_545) node _io_vcalloc_req_bits_T_555 = or(_io_vcalloc_req_bits_T_554, _io_vcalloc_req_bits_T_546) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_555, _io_vcalloc_req_bits_T_547) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_548) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_551) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_560 connect _io_vcalloc_req_bits_WIRE_24[8], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_561 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_562 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_562) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_563) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_578 = or(_io_vcalloc_req_bits_T_577, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_579 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_579 connect _io_vcalloc_req_bits_WIRE_24[9], _io_vcalloc_req_bits_WIRE_34 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_24 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_587 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_588 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_589 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_580, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_593 = or(_io_vcalloc_req_bits_T_592, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_594 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_585) node _io_vcalloc_req_bits_T_595 = or(_io_vcalloc_req_bits_T_594, _io_vcalloc_req_bits_T_586) node _io_vcalloc_req_bits_T_596 = or(_io_vcalloc_req_bits_T_595, _io_vcalloc_req_bits_T_587) node _io_vcalloc_req_bits_T_597 = or(_io_vcalloc_req_bits_T_596, _io_vcalloc_req_bits_T_588) node _io_vcalloc_req_bits_T_598 = or(_io_vcalloc_req_bits_T_597, _io_vcalloc_req_bits_T_589) wire _io_vcalloc_req_bits_WIRE_35 : UInt<4> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_598 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_35 wire _io_vcalloc_req_bits_WIRE_36 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_602 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_603 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_604 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_605 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_606 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_607 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = or(_io_vcalloc_req_bits_T_599, _io_vcalloc_req_bits_T_600) node _io_vcalloc_req_bits_T_610 = or(_io_vcalloc_req_bits_T_609, _io_vcalloc_req_bits_T_601) node _io_vcalloc_req_bits_T_611 = or(_io_vcalloc_req_bits_T_610, _io_vcalloc_req_bits_T_602) node _io_vcalloc_req_bits_T_612 = or(_io_vcalloc_req_bits_T_611, _io_vcalloc_req_bits_T_603) node _io_vcalloc_req_bits_T_613 = or(_io_vcalloc_req_bits_T_612, _io_vcalloc_req_bits_T_604) node _io_vcalloc_req_bits_T_614 = or(_io_vcalloc_req_bits_T_613, _io_vcalloc_req_bits_T_605) node _io_vcalloc_req_bits_T_615 = or(_io_vcalloc_req_bits_T_614, _io_vcalloc_req_bits_T_606) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_615, _io_vcalloc_req_bits_T_607) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_608) wire _io_vcalloc_req_bits_WIRE_37 : UInt<3> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_617 connect _io_vcalloc_req_bits_WIRE_36.egress_node_id, _io_vcalloc_req_bits_WIRE_37 node _io_vcalloc_req_bits_T_618 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_619 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_620 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_621 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_622 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_619) node _io_vcalloc_req_bits_T_629 = or(_io_vcalloc_req_bits_T_628, _io_vcalloc_req_bits_T_620) node _io_vcalloc_req_bits_T_630 = or(_io_vcalloc_req_bits_T_629, _io_vcalloc_req_bits_T_621) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_630, _io_vcalloc_req_bits_T_622) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_623) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_627) wire _io_vcalloc_req_bits_WIRE_38 : UInt<4> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_636 connect _io_vcalloc_req_bits_WIRE_36.egress_node, _io_vcalloc_req_bits_WIRE_38 node _io_vcalloc_req_bits_T_637 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_637, _io_vcalloc_req_bits_T_638) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_653 = or(_io_vcalloc_req_bits_T_652, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_654 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_645) node _io_vcalloc_req_bits_T_655 = or(_io_vcalloc_req_bits_T_654, _io_vcalloc_req_bits_T_646) wire _io_vcalloc_req_bits_WIRE_39 : UInt<2> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_655 connect _io_vcalloc_req_bits_WIRE_36.ingress_node_id, _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_662 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_663 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_664 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_665 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_656, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_668 = or(_io_vcalloc_req_bits_T_667, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_669 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_660) node _io_vcalloc_req_bits_T_670 = or(_io_vcalloc_req_bits_T_669, _io_vcalloc_req_bits_T_661) node _io_vcalloc_req_bits_T_671 = or(_io_vcalloc_req_bits_T_670, _io_vcalloc_req_bits_T_662) node _io_vcalloc_req_bits_T_672 = or(_io_vcalloc_req_bits_T_671, _io_vcalloc_req_bits_T_663) node _io_vcalloc_req_bits_T_673 = or(_io_vcalloc_req_bits_T_672, _io_vcalloc_req_bits_T_664) node _io_vcalloc_req_bits_T_674 = or(_io_vcalloc_req_bits_T_673, _io_vcalloc_req_bits_T_665) wire _io_vcalloc_req_bits_WIRE_40 : UInt<4> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_674 connect _io_vcalloc_req_bits_WIRE_36.ingress_node, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_677 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_678 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_679 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_680 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_681 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_682 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = or(_io_vcalloc_req_bits_T_675, _io_vcalloc_req_bits_T_676) node _io_vcalloc_req_bits_T_686 = or(_io_vcalloc_req_bits_T_685, _io_vcalloc_req_bits_T_677) node _io_vcalloc_req_bits_T_687 = or(_io_vcalloc_req_bits_T_686, _io_vcalloc_req_bits_T_678) node _io_vcalloc_req_bits_T_688 = or(_io_vcalloc_req_bits_T_687, _io_vcalloc_req_bits_T_679) node _io_vcalloc_req_bits_T_689 = or(_io_vcalloc_req_bits_T_688, _io_vcalloc_req_bits_T_680) node _io_vcalloc_req_bits_T_690 = or(_io_vcalloc_req_bits_T_689, _io_vcalloc_req_bits_T_681) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_690, _io_vcalloc_req_bits_T_682) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_683) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_684) wire _io_vcalloc_req_bits_WIRE_41 : UInt<3> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_693 connect _io_vcalloc_req_bits_WIRE_36.vnet_id, _io_vcalloc_req_bits_WIRE_41 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_36 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[8] invalidate vcalloc_reqs[0].vc_sel.`1`[9] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[8] invalidate vcalloc_reqs[0].vc_sel.`2`[9] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[5] invalidate vcalloc_reqs[1].vc_sel.`1`[6] invalidate vcalloc_reqs[1].vc_sel.`1`[7] invalidate vcalloc_reqs[1].vc_sel.`1`[8] invalidate vcalloc_reqs[1].vc_sel.`1`[9] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[5] invalidate vcalloc_reqs[1].vc_sel.`2`[6] invalidate vcalloc_reqs[1].vc_sel.`2`[7] invalidate vcalloc_reqs[1].vc_sel.`2`[8] invalidate vcalloc_reqs[1].vc_sel.`2`[9] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].flow, states[2].flow node _T_42 = bits(vcalloc_sel, 2, 2) node _T_43 = and(vcalloc_vals[2], _T_42) node _T_44 = and(_T_43, io.vcalloc_req.ready) when _T_44 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_45 = bits(vcalloc_sel, 3, 3) node _T_46 = and(vcalloc_vals[3], _T_45) node _T_47 = and(_T_46, io.vcalloc_req.ready) when _T_47 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_48 = bits(vcalloc_sel, 4, 4) node _T_49 = and(vcalloc_vals[4], _T_48) node _T_50 = and(_T_49, io.vcalloc_req.ready) when _T_50 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_51 = bits(vcalloc_sel, 5, 5) node _T_52 = and(vcalloc_vals[5], _T_51) node _T_53 = and(_T_52, io.vcalloc_req.ready) when _T_53 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].flow, states[6].flow node _T_54 = bits(vcalloc_sel, 6, 6) node _T_55 = and(vcalloc_vals[6], _T_54) node _T_56 = and(_T_55, io.vcalloc_req.ready) when _T_56 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].flow, states[7].flow node _T_57 = bits(vcalloc_sel, 7, 7) node _T_58 = and(vcalloc_vals[7], _T_57) node _T_59 = and(_T_58, io.vcalloc_req.ready) when _T_59 : connect states[7].g, UInt<3>(0h3) node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_60 = bits(vcalloc_sel, 8, 8) node _T_61 = and(vcalloc_vals[8], _T_60) node _T_62 = and(_T_61, io.vcalloc_req.ready) when _T_62 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].flow, states[9].flow node _T_63 = bits(vcalloc_sel, 9, 9) node _T_64 = and(vcalloc_vals[9], _T_63) node _T_65 = and(_T_64, io.vcalloc_req.ready) when _T_65 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_66 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_66 : node _T_67 = bits(vcalloc_sel, 0, 0) when _T_67 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_68 = eq(states[0].g, UInt<3>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_68, UInt<1>(0h1), "") : assert_3 node _T_72 = bits(vcalloc_sel, 1, 1) when _T_72 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_73 = eq(states[1].g, UInt<3>(0h2)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_73, UInt<1>(0h1), "") : assert_4 node _T_77 = bits(vcalloc_sel, 2, 2) when _T_77 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_78 = eq(states[2].g, UInt<3>(0h2)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = bits(vcalloc_sel, 3, 3) when _T_82 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_83 = eq(states[3].g, UInt<3>(0h2)) node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : node _T_86 = eq(_T_83, UInt<1>(0h0)) when _T_86 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_83, UInt<1>(0h1), "") : assert_6 node _T_87 = bits(vcalloc_sel, 4, 4) when _T_87 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_88 = eq(states[4].g, UInt<3>(0h2)) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_88, UInt<1>(0h1), "") : assert_7 node _T_92 = bits(vcalloc_sel, 5, 5) when _T_92 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_93 = eq(states[5].g, UInt<3>(0h2)) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_93, UInt<1>(0h1), "") : assert_8 node _T_97 = bits(vcalloc_sel, 6, 6) when _T_97 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_98 = eq(states[6].g, UInt<3>(0h2)) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_98, UInt<1>(0h1), "") : assert_9 node _T_102 = bits(vcalloc_sel, 7, 7) when _T_102 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_103 = eq(states[7].g, UInt<3>(0h2)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_103, UInt<1>(0h1), "") : assert_10 node _T_107 = bits(vcalloc_sel, 8, 8) when _T_107 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_108 = eq(states[8].g, UInt<3>(0h2)) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_108, UInt<1>(0h1), "") : assert_11 node _T_112 = bits(vcalloc_sel, 9, 9) when _T_112 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_113 = eq(states[9].g, UInt<3>(0h2)) node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : node _T_116 = eq(_T_113, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_113, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_338 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[9] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[9] node credit_available_lo_lo = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[2].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[2].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_hi_1 = cat(states[2].vc_sel.`1`[4], states[2].vc_sel.`1`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[2].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[2].vc_sel.`1`[6], states[2].vc_sel.`1`[5]) node credit_available_hi_hi_hi_1 = cat(states[2].vc_sel.`1`[9], states[2].vc_sel.`1`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[2].vc_sel.`1`[7]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_hi_2 = cat(states[2].vc_sel.`2`[4], states[2].vc_sel.`2`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[2].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[2].vc_sel.`2`[6], states[2].vc_sel.`2`[5]) node credit_available_hi_hi_hi_2 = cat(states[2].vc_sel.`2`[9], states[2].vc_sel.`2`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[2].vc_sel.`2`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_4 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, io.out_credit_available.`1`[7]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`2`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8] connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[8], states[2].vc_sel.`1`[8] connect salloc_arb.io.in[2].bits.vc_sel.`1`[9], states[2].vc_sel.`1`[9] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[8], states[2].vc_sel.`2`[8] connect salloc_arb.io.in[2].bits.vc_sel.`2`[9], states[2].vc_sel.`2`[9] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_117 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_118 = and(_T_117, input_buffer.io.deq[2].bits.tail) when _T_118 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_6 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[3].vc_sel.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[3].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6) node credit_available_lo_lo_7 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_hi_7 = cat(states[3].vc_sel.`1`[4], states[3].vc_sel.`1`[3]) node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, states[3].vc_sel.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(states[3].vc_sel.`1`[6], states[3].vc_sel.`1`[5]) node credit_available_hi_hi_hi_7 = cat(states[3].vc_sel.`1`[9], states[3].vc_sel.`1`[8]) node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, states[3].vc_sel.`1`[7]) node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7) node credit_available_lo_lo_8 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_hi_8 = cat(states[3].vc_sel.`2`[4], states[3].vc_sel.`2`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[3].vc_sel.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[3].vc_sel.`2`[6], states[3].vc_sel.`2`[5]) node credit_available_hi_hi_hi_8 = cat(states[3].vc_sel.`2`[9], states[3].vc_sel.`2`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[3].vc_sel.`2`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8) node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10) node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9) node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_10 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, io.out_credit_available.`1`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_10 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, io.out_credit_available.`1`[7]) node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10) node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`2`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`2`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11) node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14) node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13) node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16) node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_1) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[8], states[3].vc_sel.`1`[8] connect salloc_arb.io.in[3].bits.vc_sel.`1`[9], states[3].vc_sel.`1`[9] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[8], states[3].vc_sel.`2`[8] connect salloc_arb.io.in[3].bits.vc_sel.`2`[9], states[3].vc_sel.`2`[9] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_119 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_120 = and(_T_119, input_buffer.io.deq[3].bits.tail) when _T_120 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_12 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[4].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[4].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12) node credit_available_lo_lo_13 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_hi_13 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3]) node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, states[4].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[4].vc_sel.`1`[6], states[4].vc_sel.`1`[5]) node credit_available_hi_hi_hi_13 = cat(states[4].vc_sel.`1`[9], states[4].vc_sel.`1`[8]) node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, states[4].vc_sel.`1`[7]) node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13) node credit_available_lo_lo_14 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_hi_14 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[4].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[4].vc_sel.`2`[6], states[4].vc_sel.`2`[5]) node credit_available_hi_hi_hi_14 = cat(states[4].vc_sel.`2`[9], states[4].vc_sel.`2`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[4].vc_sel.`2`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14) node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19) node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_16 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_16, io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_16 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_16, io.out_credit_available.`1`[7]) node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_17 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_17 = cat(credit_available_lo_hi_hi_17, io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_17 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_17 = cat(credit_available_hi_hi_hi_17, io.out_credit_available.`2`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17) node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23) node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22) node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25) node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_2) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[8], states[4].vc_sel.`1`[8] connect salloc_arb.io.in[4].bits.vc_sel.`1`[9], states[4].vc_sel.`1`[9] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[8], states[4].vc_sel.`2`[8] connect salloc_arb.io.in[4].bits.vc_sel.`2`[9], states[4].vc_sel.`2`[9] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_121 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_122 = and(_T_121, input_buffer.io.deq[4].bits.tail) when _T_122 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_18 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_18 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_18, states[5].vc_sel.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_18 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_18, states[5].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18) node credit_available_lo_lo_19 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_hi_19 = cat(states[5].vc_sel.`1`[4], states[5].vc_sel.`1`[3]) node credit_available_lo_hi_19 = cat(credit_available_lo_hi_hi_19, states[5].vc_sel.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[5].vc_sel.`1`[6], states[5].vc_sel.`1`[5]) node credit_available_hi_hi_hi_19 = cat(states[5].vc_sel.`1`[9], states[5].vc_sel.`1`[8]) node credit_available_hi_hi_19 = cat(credit_available_hi_hi_hi_19, states[5].vc_sel.`1`[7]) node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19) node credit_available_lo_lo_20 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_hi_20 = cat(states[5].vc_sel.`2`[4], states[5].vc_sel.`2`[3]) node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_20, states[5].vc_sel.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[5].vc_sel.`2`[6], states[5].vc_sel.`2`[5]) node credit_available_hi_hi_hi_20 = cat(states[5].vc_sel.`2`[9], states[5].vc_sel.`2`[8]) node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_20, states[5].vc_sel.`2`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20) node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28) node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27) node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_21 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_21 = cat(credit_available_lo_hi_hi_21, io.out_credit_available.`0`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_21 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_21 = cat(credit_available_hi_hi_hi_21, io.out_credit_available.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21) node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_22 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_22, io.out_credit_available.`1`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_22 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_22, io.out_credit_available.`1`[7]) node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22) node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_23 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_23 = cat(credit_available_lo_hi_hi_23, io.out_credit_available.`2`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_23 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_23 = cat(credit_available_hi_hi_hi_23, io.out_credit_available.`2`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23) node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32) node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31) node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34) node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_3) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[8], states[5].vc_sel.`1`[8] connect salloc_arb.io.in[5].bits.vc_sel.`1`[9], states[5].vc_sel.`1`[9] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[8], states[5].vc_sel.`2`[8] connect salloc_arb.io.in[5].bits.vc_sel.`2`[9], states[5].vc_sel.`2`[9] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_123 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_124 = and(_T_123, input_buffer.io.deq[5].bits.tail) when _T_124 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_24 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_hi_24 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3]) node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_24, states[6].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5]) node credit_available_hi_hi_hi_24 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8]) node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_24, states[6].vc_sel.`0`[7]) node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24) node credit_available_lo_lo_25 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_hi_25 = cat(states[6].vc_sel.`1`[4], states[6].vc_sel.`1`[3]) node credit_available_lo_hi_25 = cat(credit_available_lo_hi_hi_25, states[6].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[6].vc_sel.`1`[6], states[6].vc_sel.`1`[5]) node credit_available_hi_hi_hi_25 = cat(states[6].vc_sel.`1`[9], states[6].vc_sel.`1`[8]) node credit_available_hi_hi_25 = cat(credit_available_hi_hi_hi_25, states[6].vc_sel.`1`[7]) node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25) node credit_available_lo_lo_26 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_hi_26 = cat(states[6].vc_sel.`2`[4], states[6].vc_sel.`2`[3]) node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_26, states[6].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[6].vc_sel.`2`[6], states[6].vc_sel.`2`[5]) node credit_available_hi_hi_hi_26 = cat(states[6].vc_sel.`2`[9], states[6].vc_sel.`2`[8]) node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_26, states[6].vc_sel.`2`[7]) node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26) node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37) node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36) node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_27 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_27 = cat(credit_available_lo_hi_hi_27, io.out_credit_available.`0`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_27 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_27 = cat(credit_available_hi_hi_hi_27, io.out_credit_available.`0`[7]) node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27) node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_28 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_28, io.out_credit_available.`1`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_28 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_28, io.out_credit_available.`1`[7]) node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28) node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_29 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_29 = cat(credit_available_lo_hi_hi_29, io.out_credit_available.`2`[2]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_29 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_29 = cat(credit_available_hi_hi_hi_29, io.out_credit_available.`2`[7]) node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29) node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41) node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40) node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43) node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_4) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8] connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[8], states[6].vc_sel.`1`[8] connect salloc_arb.io.in[6].bits.vc_sel.`1`[9], states[6].vc_sel.`1`[9] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[8], states[6].vc_sel.`2`[8] connect salloc_arb.io.in[6].bits.vc_sel.`2`[9], states[6].vc_sel.`2`[9] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_125 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_126 = and(_T_125, input_buffer.io.deq[6].bits.tail) when _T_126 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_30 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_hi_30 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3]) node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_30, states[7].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5]) node credit_available_hi_hi_hi_30 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8]) node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_30, states[7].vc_sel.`0`[7]) node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30) node credit_available_lo_lo_31 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_hi_31 = cat(states[7].vc_sel.`1`[4], states[7].vc_sel.`1`[3]) node credit_available_lo_hi_31 = cat(credit_available_lo_hi_hi_31, states[7].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[7].vc_sel.`1`[6], states[7].vc_sel.`1`[5]) node credit_available_hi_hi_hi_31 = cat(states[7].vc_sel.`1`[9], states[7].vc_sel.`1`[8]) node credit_available_hi_hi_31 = cat(credit_available_hi_hi_hi_31, states[7].vc_sel.`1`[7]) node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31) node credit_available_lo_lo_32 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_hi_32 = cat(states[7].vc_sel.`2`[4], states[7].vc_sel.`2`[3]) node credit_available_lo_hi_32 = cat(credit_available_lo_hi_hi_32, states[7].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[7].vc_sel.`2`[6], states[7].vc_sel.`2`[5]) node credit_available_hi_hi_hi_32 = cat(states[7].vc_sel.`2`[9], states[7].vc_sel.`2`[8]) node credit_available_hi_hi_32 = cat(credit_available_hi_hi_hi_32, states[7].vc_sel.`2`[7]) node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32) node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45) node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_33 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_33 = cat(credit_available_lo_hi_hi_33, io.out_credit_available.`0`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_33 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_33 = cat(credit_available_hi_hi_hi_33, io.out_credit_available.`0`[7]) node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33) node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_34 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_34 = cat(credit_available_lo_hi_hi_34, io.out_credit_available.`1`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_34 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_34 = cat(credit_available_hi_hi_hi_34, io.out_credit_available.`1`[7]) node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34) node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_35 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_35 = cat(credit_available_lo_hi_hi_35, io.out_credit_available.`2`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_35 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_35 = cat(credit_available_hi_hi_hi_35, io.out_credit_available.`2`[7]) node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35) node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50) node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49) node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52) node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_5) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8] connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[8], states[7].vc_sel.`1`[8] connect salloc_arb.io.in[7].bits.vc_sel.`1`[9], states[7].vc_sel.`1`[9] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[8], states[7].vc_sel.`2`[8] connect salloc_arb.io.in[7].bits.vc_sel.`2`[9], states[7].vc_sel.`2`[9] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_127 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_128 = and(_T_127, input_buffer.io.deq[7].bits.tail) when _T_128 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node credit_available_lo_lo_36 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_36 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_36 = cat(credit_available_lo_hi_hi_36, states[8].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_36 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_36 = cat(credit_available_hi_hi_hi_36, states[8].vc_sel.`0`[7]) node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36) node credit_available_lo_lo_37 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0]) node credit_available_lo_hi_hi_37 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3]) node credit_available_lo_hi_37 = cat(credit_available_lo_hi_hi_37, states[8].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5]) node credit_available_hi_hi_hi_37 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8]) node credit_available_hi_hi_37 = cat(credit_available_hi_hi_hi_37, states[8].vc_sel.`1`[7]) node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37) node credit_available_lo_lo_38 = cat(states[8].vc_sel.`2`[1], states[8].vc_sel.`2`[0]) node credit_available_lo_hi_hi_38 = cat(states[8].vc_sel.`2`[4], states[8].vc_sel.`2`[3]) node credit_available_lo_hi_38 = cat(credit_available_lo_hi_hi_38, states[8].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(states[8].vc_sel.`2`[6], states[8].vc_sel.`2`[5]) node credit_available_hi_hi_hi_38 = cat(states[8].vc_sel.`2`[9], states[8].vc_sel.`2`[8]) node credit_available_hi_hi_38 = cat(credit_available_hi_hi_hi_38, states[8].vc_sel.`2`[7]) node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38) node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55) node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54) node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_39 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_39 = cat(credit_available_lo_hi_hi_39, io.out_credit_available.`0`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_39 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_39 = cat(credit_available_hi_hi_hi_39, io.out_credit_available.`0`[7]) node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39) node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_40 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_40 = cat(credit_available_lo_hi_hi_40, io.out_credit_available.`1`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_40 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_40 = cat(credit_available_hi_hi_hi_40, io.out_credit_available.`1`[7]) node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40) node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_41 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_41 = cat(credit_available_lo_hi_hi_41, io.out_credit_available.`2`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_41 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_41 = cat(credit_available_hi_hi_hi_41, io.out_credit_available.`2`[7]) node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41) node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59) node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58) node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61) node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1] connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2] connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3] connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4] connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5] connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6] connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7] connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8] connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[1], states[8].vc_sel.`2`[1] connect salloc_arb.io.in[8].bits.vc_sel.`2`[2], states[8].vc_sel.`2`[2] connect salloc_arb.io.in[8].bits.vc_sel.`2`[3], states[8].vc_sel.`2`[3] connect salloc_arb.io.in[8].bits.vc_sel.`2`[4], states[8].vc_sel.`2`[4] connect salloc_arb.io.in[8].bits.vc_sel.`2`[5], states[8].vc_sel.`2`[5] connect salloc_arb.io.in[8].bits.vc_sel.`2`[6], states[8].vc_sel.`2`[6] connect salloc_arb.io.in[8].bits.vc_sel.`2`[7], states[8].vc_sel.`2`[7] connect salloc_arb.io.in[8].bits.vc_sel.`2`[8], states[8].vc_sel.`2`[8] connect salloc_arb.io.in[8].bits.vc_sel.`2`[9], states[8].vc_sel.`2`[9] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_129 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_130 = and(_T_129, input_buffer.io.deq[8].bits.tail) when _T_130 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_42 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_42 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_42 = cat(credit_available_lo_hi_hi_42, states[9].vc_sel.`0`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_42 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_42 = cat(credit_available_hi_hi_hi_42, states[9].vc_sel.`0`[7]) node credit_available_hi_56 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_63 = cat(credit_available_hi_56, credit_available_lo_42) node credit_available_lo_lo_43 = cat(states[9].vc_sel.`1`[1], states[9].vc_sel.`1`[0]) node credit_available_lo_hi_hi_43 = cat(states[9].vc_sel.`1`[4], states[9].vc_sel.`1`[3]) node credit_available_lo_hi_43 = cat(credit_available_lo_hi_hi_43, states[9].vc_sel.`1`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[9].vc_sel.`1`[6], states[9].vc_sel.`1`[5]) node credit_available_hi_hi_hi_43 = cat(states[9].vc_sel.`1`[9], states[9].vc_sel.`1`[8]) node credit_available_hi_hi_43 = cat(credit_available_hi_hi_hi_43, states[9].vc_sel.`1`[7]) node credit_available_hi_57 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_64 = cat(credit_available_hi_57, credit_available_lo_43) node credit_available_lo_lo_44 = cat(states[9].vc_sel.`2`[1], states[9].vc_sel.`2`[0]) node credit_available_lo_hi_hi_44 = cat(states[9].vc_sel.`2`[4], states[9].vc_sel.`2`[3]) node credit_available_lo_hi_44 = cat(credit_available_lo_hi_hi_44, states[9].vc_sel.`2`[2]) node credit_available_lo_44 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(states[9].vc_sel.`2`[6], states[9].vc_sel.`2`[5]) node credit_available_hi_hi_hi_44 = cat(states[9].vc_sel.`2`[9], states[9].vc_sel.`2`[8]) node credit_available_hi_hi_44 = cat(credit_available_hi_hi_hi_44, states[9].vc_sel.`2`[7]) node credit_available_hi_58 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_65 = cat(credit_available_hi_58, credit_available_lo_44) node credit_available_hi_59 = cat(_credit_available_T_65, _credit_available_T_64) node _credit_available_T_66 = cat(credit_available_hi_59, _credit_available_T_63) node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_45 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_45 = cat(credit_available_lo_hi_hi_45, io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_45 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_45 = cat(credit_available_hi_hi_hi_45, io.out_credit_available.`0`[7]) node credit_available_hi_60 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_67 = cat(credit_available_hi_60, credit_available_lo_45) node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_hi_46 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_lo_hi_46 = cat(credit_available_lo_hi_hi_46, io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5]) node credit_available_hi_hi_hi_46 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8]) node credit_available_hi_hi_46 = cat(credit_available_hi_hi_hi_46, io.out_credit_available.`1`[7]) node credit_available_hi_61 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_68 = cat(credit_available_hi_61, credit_available_lo_46) node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_hi_47 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_lo_hi_47 = cat(credit_available_lo_hi_hi_47, io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[6], io.out_credit_available.`2`[5]) node credit_available_hi_hi_hi_47 = cat(io.out_credit_available.`2`[9], io.out_credit_available.`2`[8]) node credit_available_hi_hi_47 = cat(credit_available_hi_hi_hi_47, io.out_credit_available.`2`[7]) node credit_available_hi_62 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_69 = cat(credit_available_hi_62, credit_available_lo_47) node credit_available_hi_63 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_63, _credit_available_T_67) node _credit_available_T_71 = and(_credit_available_T_66, _credit_available_T_70) node credit_available_7 = neq(_credit_available_T_71, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`1`[1], states[9].vc_sel.`1`[1] connect salloc_arb.io.in[9].bits.vc_sel.`1`[2], states[9].vc_sel.`1`[2] connect salloc_arb.io.in[9].bits.vc_sel.`1`[3], states[9].vc_sel.`1`[3] connect salloc_arb.io.in[9].bits.vc_sel.`1`[4], states[9].vc_sel.`1`[4] connect salloc_arb.io.in[9].bits.vc_sel.`1`[5], states[9].vc_sel.`1`[5] connect salloc_arb.io.in[9].bits.vc_sel.`1`[6], states[9].vc_sel.`1`[6] connect salloc_arb.io.in[9].bits.vc_sel.`1`[7], states[9].vc_sel.`1`[7] connect salloc_arb.io.in[9].bits.vc_sel.`1`[8], states[9].vc_sel.`1`[8] connect salloc_arb.io.in[9].bits.vc_sel.`1`[9], states[9].vc_sel.`1`[9] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[1], states[9].vc_sel.`2`[1] connect salloc_arb.io.in[9].bits.vc_sel.`2`[2], states[9].vc_sel.`2`[2] connect salloc_arb.io.in[9].bits.vc_sel.`2`[3], states[9].vc_sel.`2`[3] connect salloc_arb.io.in[9].bits.vc_sel.`2`[4], states[9].vc_sel.`2`[4] connect salloc_arb.io.in[9].bits.vc_sel.`2`[5], states[9].vc_sel.`2`[5] connect salloc_arb.io.in[9].bits.vc_sel.`2`[6], states[9].vc_sel.`2`[6] connect salloc_arb.io.in[9].bits.vc_sel.`2`[7], states[9].vc_sel.`2`[7] connect salloc_arb.io.in[9].bits.vc_sel.`2`[8], states[9].vc_sel.`2`[8] connect salloc_arb.io.in[9].bits.vc_sel.`2`[9], states[9].vc_sel.`2`[9] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_131 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_132 = and(_T_131, input_buffer.io.deq[9].bits.tail) when _T_132 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[10] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_237 connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13 node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_256 connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14 node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258) node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259) node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260) node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261) node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_275 connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15 node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283) node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284) node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_294 connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16 node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298) node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299) node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300) node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301) node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302) node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303) node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_313 connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17 node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315) node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316) node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317) node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318) node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319) node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320) node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321) node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323) wire _vc_sel_WIRE_18 : UInt<1> connect _vc_sel_WIRE_18, _vc_sel_T_332 connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18 node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334) node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335) node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336) node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_351 connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19 node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0)) node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358) node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359) node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360) node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_370 connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20 node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0)) node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373) node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374) node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375) node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376) node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377) node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378) node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379) node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_389 connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_22 : UInt<1>[10] node _vc_sel_T_390 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_391 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_392 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_393 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_394 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_395 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_396 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_397 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_398 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_400 = or(_vc_sel_T_390, _vc_sel_T_391) node _vc_sel_T_401 = or(_vc_sel_T_400, _vc_sel_T_392) node _vc_sel_T_402 = or(_vc_sel_T_401, _vc_sel_T_393) node _vc_sel_T_403 = or(_vc_sel_T_402, _vc_sel_T_394) node _vc_sel_T_404 = or(_vc_sel_T_403, _vc_sel_T_395) node _vc_sel_T_405 = or(_vc_sel_T_404, _vc_sel_T_396) node _vc_sel_T_406 = or(_vc_sel_T_405, _vc_sel_T_397) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_398) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_399) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_408 connect _vc_sel_WIRE_22[0], _vc_sel_WIRE_23 node _vc_sel_T_409 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_410 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_411 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_412 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_413 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_419 = or(_vc_sel_T_409, _vc_sel_T_410) node _vc_sel_T_420 = or(_vc_sel_T_419, _vc_sel_T_411) node _vc_sel_T_421 = or(_vc_sel_T_420, _vc_sel_T_412) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_413) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_414) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_415) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_416) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_417) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_418) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_427 connect _vc_sel_WIRE_22[1], _vc_sel_WIRE_24 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_436 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_437 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_438 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_430) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_431) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_432) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_433) node _vc_sel_T_443 = or(_vc_sel_T_442, _vc_sel_T_434) node _vc_sel_T_444 = or(_vc_sel_T_443, _vc_sel_T_435) node _vc_sel_T_445 = or(_vc_sel_T_444, _vc_sel_T_436) node _vc_sel_T_446 = or(_vc_sel_T_445, _vc_sel_T_437) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_446 connect _vc_sel_WIRE_22[2], _vc_sel_WIRE_25 node _vc_sel_T_447 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_451 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_452 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_453 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_454 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_455 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_456 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_457 = or(_vc_sel_T_447, _vc_sel_T_448) node _vc_sel_T_458 = or(_vc_sel_T_457, _vc_sel_T_449) node _vc_sel_T_459 = or(_vc_sel_T_458, _vc_sel_T_450) node _vc_sel_T_460 = or(_vc_sel_T_459, _vc_sel_T_451) node _vc_sel_T_461 = or(_vc_sel_T_460, _vc_sel_T_452) node _vc_sel_T_462 = or(_vc_sel_T_461, _vc_sel_T_453) node _vc_sel_T_463 = or(_vc_sel_T_462, _vc_sel_T_454) node _vc_sel_T_464 = or(_vc_sel_T_463, _vc_sel_T_455) node _vc_sel_T_465 = or(_vc_sel_T_464, _vc_sel_T_456) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_465 connect _vc_sel_WIRE_22[3], _vc_sel_WIRE_26 node _vc_sel_T_466 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_467 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_468 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_469 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_470 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_471 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_472 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_473 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_476 = or(_vc_sel_T_466, _vc_sel_T_467) node _vc_sel_T_477 = or(_vc_sel_T_476, _vc_sel_T_468) node _vc_sel_T_478 = or(_vc_sel_T_477, _vc_sel_T_469) node _vc_sel_T_479 = or(_vc_sel_T_478, _vc_sel_T_470) node _vc_sel_T_480 = or(_vc_sel_T_479, _vc_sel_T_471) node _vc_sel_T_481 = or(_vc_sel_T_480, _vc_sel_T_472) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_473) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_474) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_475) wire _vc_sel_WIRE_27 : UInt<1> connect _vc_sel_WIRE_27, _vc_sel_T_484 connect _vc_sel_WIRE_22[4], _vc_sel_WIRE_27 node _vc_sel_T_485 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_486 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_487 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_488 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_495 = or(_vc_sel_T_485, _vc_sel_T_486) node _vc_sel_T_496 = or(_vc_sel_T_495, _vc_sel_T_487) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_488) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_489) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_490) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_491) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_492) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_493) node _vc_sel_T_503 = or(_vc_sel_T_502, _vc_sel_T_494) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_503 connect _vc_sel_WIRE_22[5], _vc_sel_WIRE_28 node _vc_sel_T_504 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_511 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_512 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_513 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_514 = or(_vc_sel_T_504, _vc_sel_T_505) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_506) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_507) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_508) node _vc_sel_T_518 = or(_vc_sel_T_517, _vc_sel_T_509) node _vc_sel_T_519 = or(_vc_sel_T_518, _vc_sel_T_510) node _vc_sel_T_520 = or(_vc_sel_T_519, _vc_sel_T_511) node _vc_sel_T_521 = or(_vc_sel_T_520, _vc_sel_T_512) node _vc_sel_T_522 = or(_vc_sel_T_521, _vc_sel_T_513) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_522 connect _vc_sel_WIRE_22[6], _vc_sel_WIRE_29 node _vc_sel_T_523 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_526 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_527 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_528 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_529 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_530 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_531 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_532 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_533 = or(_vc_sel_T_523, _vc_sel_T_524) node _vc_sel_T_534 = or(_vc_sel_T_533, _vc_sel_T_525) node _vc_sel_T_535 = or(_vc_sel_T_534, _vc_sel_T_526) node _vc_sel_T_536 = or(_vc_sel_T_535, _vc_sel_T_527) node _vc_sel_T_537 = or(_vc_sel_T_536, _vc_sel_T_528) node _vc_sel_T_538 = or(_vc_sel_T_537, _vc_sel_T_529) node _vc_sel_T_539 = or(_vc_sel_T_538, _vc_sel_T_530) node _vc_sel_T_540 = or(_vc_sel_T_539, _vc_sel_T_531) node _vc_sel_T_541 = or(_vc_sel_T_540, _vc_sel_T_532) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_541 connect _vc_sel_WIRE_22[7], _vc_sel_WIRE_30 node _vc_sel_T_542 = mux(_vc_sel_T, states[0].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_543 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_544 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_545 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_546 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_547 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_548 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[8], UInt<1>(0h0)) node _vc_sel_T_552 = or(_vc_sel_T_542, _vc_sel_T_543) node _vc_sel_T_553 = or(_vc_sel_T_552, _vc_sel_T_544) node _vc_sel_T_554 = or(_vc_sel_T_553, _vc_sel_T_545) node _vc_sel_T_555 = or(_vc_sel_T_554, _vc_sel_T_546) node _vc_sel_T_556 = or(_vc_sel_T_555, _vc_sel_T_547) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_548) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_549) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_550) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_551) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_560 connect _vc_sel_WIRE_22[8], _vc_sel_WIRE_31 node _vc_sel_T_561 = mux(_vc_sel_T, states[0].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_562 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_563 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[9], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_561, _vc_sel_T_562) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_563) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_564) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_565) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_566) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_567) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_568) node _vc_sel_T_578 = or(_vc_sel_T_577, _vc_sel_T_569) node _vc_sel_T_579 = or(_vc_sel_T_578, _vc_sel_T_570) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_579 connect _vc_sel_WIRE_22[9], _vc_sel_WIRE_32 connect vc_sel.`2`, _vc_sel_WIRE_22 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4]) node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8]) node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9]) node _channel_oh_T_16 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[2]) node _channel_oh_T_18 = or(_channel_oh_T_17, vc_sel.`2`[3]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`2`[4]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`2`[5]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`2`[6]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`2`[7]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`2`[8]) node channel_oh_2 = or(_channel_oh_T_23, vc_sel.`2`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2]) node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5]) node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8]) node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7]) node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8) node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0) node _virt_channel_T_12 = orr(virt_channel_hi_5) node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5) node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4) node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0) node _virt_channel_T_14 = orr(virt_channel_hi_6) node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2) node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19) node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_lo_hi_2 = cat(virt_channel_lo_hi_hi_2, vc_sel.`2`[2]) node virt_channel_lo_8 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[6], vc_sel.`2`[5]) node virt_channel_hi_hi_hi_2 = cat(vc_sel.`2`[9], vc_sel.`2`[8]) node virt_channel_hi_hi_2 = cat(virt_channel_hi_hi_hi_2, vc_sel.`2`[7]) node virt_channel_hi_8 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_22 = cat(virt_channel_hi_8, virt_channel_lo_8) node virt_channel_hi_9 = bits(_virt_channel_T_22, 9, 8) node virt_channel_lo_9 = bits(_virt_channel_T_22, 7, 0) node _virt_channel_T_23 = orr(virt_channel_hi_9) node _virt_channel_T_24 = or(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = cat(_virt_channel_T_23, _virt_channel_T_31) node _virt_channel_T_33 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_2, _virt_channel_T_32, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_33, _virt_channel_T_34) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_35) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_37 node _T_133 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_133 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`1`[8] invalidate states[0].vc_sel.`1`[9] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`2`[8] invalidate states[0].vc_sel.`2`[9] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`1`[5] invalidate states[1].vc_sel.`1`[6] invalidate states[1].vc_sel.`1`[7] invalidate states[1].vc_sel.`1`[8] invalidate states[1].vc_sel.`1`[9] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].vc_sel.`2`[5] invalidate states[1].vc_sel.`2`[6] invalidate states[1].vc_sel.`2`[7] invalidate states[1].vc_sel.`2`[8] invalidate states[1].vc_sel.`2`[9] invalidate states[1].g connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`1`[8], UInt<1>(0h0) connect states[2].vc_sel.`1`[9], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[3], UInt<1>(0h0) connect states[2].vc_sel.`2`[4], UInt<1>(0h0) connect states[2].vc_sel.`2`[5], UInt<1>(0h0) connect states[2].vc_sel.`2`[6], UInt<1>(0h0) connect states[2].vc_sel.`2`[7], UInt<1>(0h0) connect states[2].vc_sel.`2`[8], UInt<1>(0h0) connect states[2].vc_sel.`2`[9], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[8], UInt<1>(0h0) connect states[3].vc_sel.`1`[9], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[2], UInt<1>(0h0) connect states[3].vc_sel.`2`[3], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[8], UInt<1>(0h0) connect states[3].vc_sel.`2`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[8], UInt<1>(0h0) connect states[4].vc_sel.`1`[9], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) connect states[4].vc_sel.`2`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[8], UInt<1>(0h0) connect states[4].vc_sel.`2`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[8], UInt<1>(0h0) connect states[5].vc_sel.`1`[9], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[2], UInt<1>(0h0) connect states[5].vc_sel.`2`[3], UInt<1>(0h0) connect states[5].vc_sel.`2`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[5], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`2`[8], UInt<1>(0h0) connect states[5].vc_sel.`2`[9], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`0`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[8], UInt<1>(0h0) connect states[6].vc_sel.`1`[9], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[2], UInt<1>(0h0) connect states[6].vc_sel.`2`[3], UInt<1>(0h0) connect states[6].vc_sel.`2`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[5], UInt<1>(0h0) connect states[6].vc_sel.`2`[6], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`2`[8], UInt<1>(0h0) connect states[6].vc_sel.`2`[9], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`0`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[8], UInt<1>(0h0) connect states[7].vc_sel.`1`[9], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[2], UInt<1>(0h0) connect states[7].vc_sel.`2`[3], UInt<1>(0h0) connect states[7].vc_sel.`2`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[5], UInt<1>(0h0) connect states[7].vc_sel.`2`[6], UInt<1>(0h0) connect states[7].vc_sel.`2`[7], UInt<1>(0h0) connect states[7].vc_sel.`2`[8], UInt<1>(0h0) connect states[7].vc_sel.`2`[9], UInt<1>(0h0) connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[0], UInt<1>(0h0) connect states[8].vc_sel.`1`[1], UInt<1>(0h0) connect states[8].vc_sel.`1`[2], UInt<1>(0h0) connect states[8].vc_sel.`1`[3], UInt<1>(0h0) connect states[8].vc_sel.`1`[4], UInt<1>(0h0) connect states[8].vc_sel.`1`[5], UInt<1>(0h0) connect states[8].vc_sel.`1`[6], UInt<1>(0h0) connect states[8].vc_sel.`1`[7], UInt<1>(0h0) connect states[8].vc_sel.`1`[8], UInt<1>(0h0) connect states[8].vc_sel.`1`[9], UInt<1>(0h0) connect states[8].vc_sel.`2`[0], UInt<1>(0h0) connect states[8].vc_sel.`2`[1], UInt<1>(0h0) connect states[8].vc_sel.`2`[2], UInt<1>(0h0) connect states[8].vc_sel.`2`[3], UInt<1>(0h0) connect states[8].vc_sel.`2`[4], UInt<1>(0h0) connect states[8].vc_sel.`2`[5], UInt<1>(0h0) connect states[8].vc_sel.`2`[6], UInt<1>(0h0) connect states[8].vc_sel.`2`[7], UInt<1>(0h0) connect states[8].vc_sel.`2`[8], UInt<1>(0h0) connect states[8].vc_sel.`2`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`1`[0], UInt<1>(0h0) connect states[9].vc_sel.`1`[1], UInt<1>(0h0) connect states[9].vc_sel.`1`[2], UInt<1>(0h0) connect states[9].vc_sel.`1`[3], UInt<1>(0h0) connect states[9].vc_sel.`1`[4], UInt<1>(0h0) connect states[9].vc_sel.`1`[5], UInt<1>(0h0) connect states[9].vc_sel.`1`[6], UInt<1>(0h0) connect states[9].vc_sel.`1`[7], UInt<1>(0h0) connect states[9].vc_sel.`1`[8], UInt<1>(0h0) connect states[9].vc_sel.`1`[9], UInt<1>(0h0) connect states[9].vc_sel.`2`[0], UInt<1>(0h0) connect states[9].vc_sel.`2`[1], UInt<1>(0h0) connect states[9].vc_sel.`2`[2], UInt<1>(0h0) connect states[9].vc_sel.`2`[3], UInt<1>(0h0) connect states[9].vc_sel.`2`[4], UInt<1>(0h0) connect states[9].vc_sel.`2`[5], UInt<1>(0h0) connect states[9].vc_sel.`2`[6], UInt<1>(0h0) connect states[9].vc_sel.`2`[7], UInt<1>(0h0) connect states[9].vc_sel.`2`[8], UInt<1>(0h0) connect states[9].vc_sel.`2`[9], UInt<1>(0h0) node _T_134 = asUInt(reset) when _T_134 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)
module InputUnit_129( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_7; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, 2'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_178 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_192 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_178( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_192 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s5k4z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_16 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s5k4z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s5k4z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits.sink, UInt<4>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_34 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_35 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLBuffer_a32d64s5k4z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_16 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s5k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1_6 : input clock : Clock input reset : Reset output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in inst chain of SynchronizerShiftReg_w1_d3_6 connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] wire _WIRE : UInt<1>[1] wire _WIRE_1 : UInt<1> connect _WIRE_1, chain.io.q node _T = bits(_WIRE_1, 0, 0) connect _WIRE[0], _T connect nodeOut, _WIRE
module IntSyncAsyncCrossingSink_n1x1_6( // @[Crossing.scala:74:9] input clock, // @[Crossing.scala:74:9] input reset, // @[Crossing.scala:74:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:74:9] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:74:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:74:9] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9] SynchronizerShiftReg_w1_d3_6 chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (nodeIn_sync_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_0) ); // @[ShiftReg.scala:45:23] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_24 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_24( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_24 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_77 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_77( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_pbus_out_i1_o2_a29d64s8k1z3u : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_15 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 7, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_16.bits.sink, UInt<1>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_18.bits.sink, UInt<1>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.valid, UInt<1>(0h0) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<13>(0h0) connect _WIRE_30.bits.source, UInt<8>(0h0) connect _WIRE_30.bits.size, UInt<3>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<29>(0h0) connect _WIRE_32.bits.source, UInt<8>(0h0) connect _WIRE_32.bits.size, UInt<3>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<13>(0h0) connect _WIRE_34.bits.source, UInt<8>(0h0) connect _WIRE_34.bits.size, UInt<3>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<29>(0h0) connect _WIRE_36.bits.source, UInt<8>(0h0) connect _WIRE_36.bits.size, UInt<3>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.ready, UInt<1>(0h1) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<13>(0h0) connect _WIRE_38.bits.source, UInt<8>(0h0) connect _WIRE_38.bits.size, UInt<3>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_40.bits.sink, UInt<1>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_42.bits.sink, UInt<1>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_44.bits.sink, UInt<1>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.ready, UInt<1>(0h1) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_46.bits.sink, UInt<1>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<29>(0h0) connect _WIRE_48.bits.source, UInt<8>(0h0) connect _WIRE_48.bits.size, UInt<3>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<29>(0h0) connect _WIRE_50.bits.source, UInt<8>(0h0) connect _WIRE_50.bits.size, UInt<3>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<29>(0h0) connect _WIRE_52.bits.source, UInt<8>(0h0) connect _WIRE_52.bits.size, UInt<3>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<29>(0h0) connect _WIRE_54.bits.source, UInt<8>(0h0) connect _WIRE_54.bits.size, UInt<3>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<29>(0h0) connect _WIRE_56.bits.source, UInt<8>(0h0) connect _WIRE_56.bits.size, UInt<3>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<29>(0h0) connect _WIRE_58.bits.source, UInt<8>(0h0) connect _WIRE_58.bits.size, UInt<3>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<29>(0h0) connect _WIRE_60.bits.source, UInt<8>(0h0) connect _WIRE_60.bits.size, UInt<3>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<29>(0h0) connect _WIRE_62.bits.source, UInt<8>(0h0) connect _WIRE_62.bits.size, UInt<3>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_64.bits.sink, UInt<1>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_66.bits.sink, UInt<1>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_68.bits.sink, UInt<1>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_70.bits.sink, UInt<1>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<29>(0h0) connect _addressC_WIRE.bits.source, UInt<8>(0h0) connect _addressC_WIRE.bits.size, UInt<3>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h10000000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 7, 0) node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 8) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<8>(0hff)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 7, 0) node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 8) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<8>(0hff)) node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 7, 0) node _requestDOI_T = shr(out[0].d.bits.source, 8) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<8>(0hff)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 7, 0) node _requestDOI_T_5 = shr(out[1].d.bits.source, 8) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<8>(0hff)) node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0) connect _beatsBO_WIRE_2.bits.source, UInt<8>(0h0) connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0) connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE_2.valid, UInt<1>(0h0) connect _beatsBO_WIRE_2.ready, UInt<1>(0h0) wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<29>(0h0) connect _beatsCI_WIRE.bits.source, UInt<8>(0h0) connect _beatsCI_WIRE.bits.size, UInt<3>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0) connect _portsBIO_WIRE_2.bits.source, UInt<8>(0h0) connect _portsBIO_WIRE_2.bits.size, UInt<3>(0h0) connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE_2.valid, UInt<1>(0h0) connect _portsBIO_WIRE_2.ready, UInt<1>(0h0) wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1)) node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<29>(0h0) connect _portsCOI_WIRE.bits.source, UInt<8>(0h0) connect _portsCOI_WIRE.bits.size, UInt<3>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1) wire _portsCOI_WIRE_2 : UInt<1> connect _portsCOI_WIRE_2, _portsCOI_T_2 connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2 wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect out[0].d.ready, portsDIO_filtered[0].ready wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect out[1].d.ready, portsDIO_filtered_1[0].ready wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1) wire _portsEOI_WIRE_2 : UInt<1> connect _portsEOI_WIRE_2, _portsEOI_T_2 connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2 connect out[0].a, portsAOI_filtered[0] wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<29>(0h0) connect _WIRE_72.bits.source, UInt<8>(0h0) connect _WIRE_72.bits.size, UInt<3>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_74.bits.sink, UInt<1>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect out[1].a, portsAOI_filtered[1] wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.address, UInt<29>(0h0) connect _WIRE_76.bits.source, UInt<8>(0h0) connect _WIRE_76.bits.size, UInt<3>(0h0) connect _WIRE_76.bits.param, UInt<3>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_78.bits.sink, UInt<1>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.mask, UInt<8>(0h0) connect _WIRE_80.bits.address, UInt<29>(0h0) connect _WIRE_80.bits.source, UInt<8>(0h0) connect _WIRE_80.bits.size, UInt<3>(0h0) connect _WIRE_80.bits.param, UInt<2>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready invalidate _WIRE_81.bits.corrupt invalidate _WIRE_81.bits.data invalidate _WIRE_81.bits.mask invalidate _WIRE_81.bits.address invalidate _WIRE_81.bits.source invalidate _WIRE_81.bits.size invalidate _WIRE_81.bits.param invalidate _WIRE_81.bits.opcode regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, in[0].d.ready) node _readys_T = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsDIO_filtered[0].valid) node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(in[0].d.ready, allowed[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<1> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<8> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<3> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) extmodule plusarg_reader_64 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_65 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLXbar_pbus_out_i1_o2_a29d64s8k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [12:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _portsAOI_in_0_a_ready_T_2 = ~(auto_anon_in_a_bits_address[28]) & auto_anon_out_0_a_ready | auto_anon_in_a_bits_address[28] & auto_anon_out_1_a_ready; // @[Mux.scala:30:73] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_out_1_d_valid} | _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]
Generate the Verilog code corresponding to this FIRRTL code module TageTable_5 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 3) node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 6, 0) node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 13, 7) node idx_history_hist_chunks_2 = bits(io.f1_req_ghist, 20, 14) node idx_history_hist_chunks_3 = bits(io.f1_req_ghist, 27, 21) node idx_history_hist_chunks_4 = bits(io.f1_req_ghist, 34, 28) node idx_history_hist_chunks_5 = bits(io.f1_req_ghist, 41, 35) node idx_history_hist_chunks_6 = bits(io.f1_req_ghist, 48, 42) node idx_history_hist_chunks_7 = bits(io.f1_req_ghist, 55, 49) node idx_history_hist_chunks_8 = bits(io.f1_req_ghist, 62, 56) node idx_history_hist_chunks_9 = bits(io.f1_req_ghist, 63, 63) node _idx_history_T = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1) node _idx_history_T_1 = xor(_idx_history_T, idx_history_hist_chunks_2) node _idx_history_T_2 = xor(_idx_history_T_1, idx_history_hist_chunks_3) node _idx_history_T_3 = xor(_idx_history_T_2, idx_history_hist_chunks_4) node _idx_history_T_4 = xor(_idx_history_T_3, idx_history_hist_chunks_5) node _idx_history_T_5 = xor(_idx_history_T_4, idx_history_hist_chunks_6) node _idx_history_T_6 = xor(_idx_history_T_5, idx_history_hist_chunks_7) node _idx_history_T_7 = xor(_idx_history_T_6, idx_history_hist_chunks_8) node idx_history = xor(_idx_history_T_7, idx_history_hist_chunks_9) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 6, 0) node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 8, 0) node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 17, 9) node tag_history_hist_chunks_2 = bits(io.f1_req_ghist, 26, 18) node tag_history_hist_chunks_3 = bits(io.f1_req_ghist, 35, 27) node tag_history_hist_chunks_4 = bits(io.f1_req_ghist, 44, 36) node tag_history_hist_chunks_5 = bits(io.f1_req_ghist, 53, 45) node tag_history_hist_chunks_6 = bits(io.f1_req_ghist, 62, 54) node tag_history_hist_chunks_7 = bits(io.f1_req_ghist, 63, 63) node _tag_history_T = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1) node _tag_history_T_1 = xor(_tag_history_T, tag_history_hist_chunks_2) node _tag_history_T_2 = xor(_tag_history_T_1, tag_history_hist_chunks_3) node _tag_history_T_3 = xor(_tag_history_T_2, tag_history_hist_chunks_4) node _tag_history_T_4 = xor(_tag_history_T_3, tag_history_hist_chunks_5) node _tag_history_T_5 = xor(_tag_history_T_4, tag_history_hist_chunks_6) node tag_history = xor(_tag_history_T_5, tag_history_hist_chunks_7) node _tag_T = shr(_T_1, 7) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 8, 0) smem hi_us : UInt<1>[4] [128] smem lo_us : UInt<1>[4] [128] smem table : UInt<13>[4] [128] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire _s2_req_rtage_WIRE : UInt<7> invalidate _s2_req_rtage_WIRE when io.f1_req_valid : connect _s2_req_rtage_WIRE, s1_hashed_idx read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_2 : UInt<13> connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0] node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0) connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 11, 3) connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1 node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 12, 12) connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2 wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_4 : UInt<13> connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1] node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0) connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3 node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 11, 3) connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4 node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 12, 12) connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5 wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_6 : UInt<13> connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2] node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0) connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6 node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 11, 3) connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7 node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 12, 12) connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8 wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_8 : UInt<13> connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3] node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0) connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9 node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 11, 3) connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10 node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 12, 12) connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11 wire s2_req_rtage : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4] connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid wire _s2_req_rhius_WIRE : UInt<7> invalidate _s2_req_rhius_WIRE when io.f1_req_valid : connect _s2_req_rhius_WIRE, s1_hashed_idx read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock wire _s2_req_rlous_WIRE : UInt<7> invalidate _s2_req_rlous_WIRE when io.f1_req_valid : connect _s2_req_rlous_WIRE, s1_hashed_idx read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 reg io_f3_resp_0_valid_REG : UInt<1>, clock connect io_f3_resp_0_valid_REG, s2_req_rhits[0] connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0]) reg io_f3_resp_0_bits_u_REG : UInt, clock connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG reg io_f3_resp_0_bits_ctr_REG : UInt, clock connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG reg io_f3_resp_1_valid_REG : UInt<1>, clock connect io_f3_resp_1_valid_REG, s2_req_rhits[1] connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1]) reg io_f3_resp_1_bits_u_REG : UInt, clock connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG reg io_f3_resp_1_bits_ctr_REG : UInt, clock connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG reg io_f3_resp_2_valid_REG : UInt<1>, clock connect io_f3_resp_2_valid_REG, s2_req_rhits[2] connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2]) reg io_f3_resp_2_bits_u_REG : UInt, clock connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG reg io_f3_resp_2_bits_ctr_REG : UInt, clock connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG reg io_f3_resp_3_valid_REG : UInt<1>, clock connect io_f3_resp_3_valid_REG, s2_req_rhits[3] connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3]) reg io_f3_resp_3_bits_u_REG : UInt, clock connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG reg io_f3_resp_3_bits_ctr_REG : UInt, clock connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1)) node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1) node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18) node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0)) node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1) node clear_u_idx = shr(clear_u_ctr, 11) node _T_2 = shr(io.update_pc, 3) node idx_history_hist_chunks_0_1 = bits(io.update_hist, 6, 0) node idx_history_hist_chunks_1_1 = bits(io.update_hist, 13, 7) node idx_history_hist_chunks_2_1 = bits(io.update_hist, 20, 14) node idx_history_hist_chunks_3_1 = bits(io.update_hist, 27, 21) node idx_history_hist_chunks_4_1 = bits(io.update_hist, 34, 28) node idx_history_hist_chunks_5_1 = bits(io.update_hist, 41, 35) node idx_history_hist_chunks_6_1 = bits(io.update_hist, 48, 42) node idx_history_hist_chunks_7_1 = bits(io.update_hist, 55, 49) node idx_history_hist_chunks_8_1 = bits(io.update_hist, 62, 56) node idx_history_hist_chunks_9_1 = bits(io.update_hist, 63, 63) node _idx_history_T_8 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1) node _idx_history_T_9 = xor(_idx_history_T_8, idx_history_hist_chunks_2_1) node _idx_history_T_10 = xor(_idx_history_T_9, idx_history_hist_chunks_3_1) node _idx_history_T_11 = xor(_idx_history_T_10, idx_history_hist_chunks_4_1) node _idx_history_T_12 = xor(_idx_history_T_11, idx_history_hist_chunks_5_1) node _idx_history_T_13 = xor(_idx_history_T_12, idx_history_hist_chunks_6_1) node _idx_history_T_14 = xor(_idx_history_T_13, idx_history_hist_chunks_7_1) node _idx_history_T_15 = xor(_idx_history_T_14, idx_history_hist_chunks_8_1) node idx_history_1 = xor(_idx_history_T_15, idx_history_hist_chunks_9_1) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 6, 0) node tag_history_hist_chunks_0_1 = bits(io.update_hist, 8, 0) node tag_history_hist_chunks_1_1 = bits(io.update_hist, 17, 9) node tag_history_hist_chunks_2_1 = bits(io.update_hist, 26, 18) node tag_history_hist_chunks_3_1 = bits(io.update_hist, 35, 27) node tag_history_hist_chunks_4_1 = bits(io.update_hist, 44, 36) node tag_history_hist_chunks_5_1 = bits(io.update_hist, 53, 45) node tag_history_hist_chunks_6_1 = bits(io.update_hist, 62, 54) node tag_history_hist_chunks_7_1 = bits(io.update_hist, 63, 63) node _tag_history_T_6 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1) node _tag_history_T_7 = xor(_tag_history_T_6, tag_history_hist_chunks_2_1) node _tag_history_T_8 = xor(_tag_history_T_7, tag_history_hist_chunks_3_1) node _tag_history_T_9 = xor(_tag_history_T_8, tag_history_hist_chunks_4_1) node _tag_history_T_10 = xor(_tag_history_T_9, tag_history_hist_chunks_5_1) node _tag_history_T_11 = xor(_tag_history_T_10, tag_history_hist_chunks_6_1) node tag_history_1 = xor(_tag_history_T_11, tag_history_hist_chunks_7_1) node _tag_T_2 = shr(_T_2, 7) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 8, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4] node _T_3 = mux(doing_reset, reset_idx, update_idx) wire _WIRE : UInt<13>[4] connect _WIRE[0], UInt<13>(0h0) connect _WIRE[1], UInt<13>(0h0) connect _WIRE[2], UInt<13>(0h0) connect _WIRE[3], UInt<13>(0h0) node hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _T_4 = cat(hi, update_wdata[0].ctr) node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _T_5 = cat(hi_1, update_wdata[1].ctr) node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _T_6 = cat(hi_2, update_wdata[2].ctr) node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _T_7 = cat(hi_3, update_wdata[3].ctr) wire _WIRE_1 : UInt<13>[4] connect _WIRE_1[0], _T_4 connect _WIRE_1[1], _T_5 connect _WIRE_1[2], _T_6 connect _WIRE_1[3], _T_7 node _T_8 = mux(doing_reset, _WIRE, _WIRE_1) node _T_9 = not(UInt<4>(0h0)) node lo = cat(io.update_mask[1], io.update_mask[0]) node hi_4 = cat(io.update_mask[3], io.update_mask[2]) node _T_10 = cat(hi_4, lo) node _T_11 = mux(doing_reset, _T_9, _T_10) node _T_12 = bits(_T_11, 0, 0) node _T_13 = bits(_T_11, 1, 1) node _T_14 = bits(_T_11, 2, 2) node _T_15 = bits(_T_11, 3, 3) write mport MPORT = table[_T_3], clock when _T_12 : connect MPORT[0], _T_8[0] when _T_13 : connect MPORT[1], _T_8[1] when _T_14 : connect MPORT[2], _T_8[2] when _T_15 : connect MPORT[3], _T_8[3] wire update_hi_wdata : UInt<1>[4] node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx) node _T_17 = mux(doing_reset, reset_idx, _T_16) node _T_18 = or(doing_reset, doing_clear_u_hi) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], UInt<1>(0h0) connect _WIRE_2[1], UInt<1>(0h0) connect _WIRE_2[2], UInt<1>(0h0) connect _WIRE_2[3], UInt<1>(0h0) node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata) node _T_20 = or(doing_reset, doing_clear_u_hi) node _T_21 = not(UInt<4>(0h0)) node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_22 = cat(hi_5, lo_1) node _T_23 = mux(_T_20, _T_21, _T_22) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = bits(_T_23, 2, 2) node _T_27 = bits(_T_23, 3, 3) node _T_28 = bits(_T_17, 6, 0) write mport MPORT_1 = hi_us[_T_28], clock when _T_24 : connect MPORT_1[0], _T_19[0] when _T_25 : connect MPORT_1[1], _T_19[1] when _T_26 : connect MPORT_1[2], _T_19[2] when _T_27 : connect MPORT_1[3], _T_19[3] wire update_lo_wdata : UInt<1>[4] node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx) node _T_30 = mux(doing_reset, reset_idx, _T_29) node _T_31 = or(doing_reset, doing_clear_u_lo) wire _WIRE_3 : UInt<1>[4] connect _WIRE_3[0], UInt<1>(0h0) connect _WIRE_3[1], UInt<1>(0h0) connect _WIRE_3[2], UInt<1>(0h0) connect _WIRE_3[3], UInt<1>(0h0) node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata) node _T_33 = or(doing_reset, doing_clear_u_lo) node _T_34 = not(UInt<4>(0h0)) node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_35 = cat(hi_6, lo_2) node _T_36 = mux(_T_33, _T_34, _T_35) node _T_37 = bits(_T_36, 0, 0) node _T_38 = bits(_T_36, 1, 1) node _T_39 = bits(_T_36, 2, 2) node _T_40 = bits(_T_36, 3, 3) node _T_41 = bits(_T_30, 6, 0) write mport MPORT_2 = lo_us[_T_41], clock when _T_37 : connect MPORT_2[0], _T_32[0] when _T_38 : connect MPORT_2[1], _T_32[1] when _T_39 : connect MPORT_2[2], _T_32[2] when _T_40 : connect MPORT_2[3], _T_32[3] reg wrbypass_tags : UInt<9>[2], clock reg wrbypass_idxs : UInt<7>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1) connect update_hi_wdata[0], _update_hi_wdata_0_T node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0) connect update_lo_wdata[0], _update_lo_wdata_0_T node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1) connect update_hi_wdata[1], _update_hi_wdata_1_T node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0) connect update_lo_wdata[1], _update_lo_wdata_1_T node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1) connect update_hi_wdata[2], _update_hi_wdata_2_T node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0) connect update_lo_wdata[2], _update_lo_wdata_2_T node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1) connect update_hi_wdata[3], _update_hi_wdata_3_T node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0) connect update_lo_wdata[3], _update_lo_wdata_3_T node _T_42 = or(io.update_mask[0], io.update_mask[1]) node _T_43 = or(_T_42, io.update_mask[2]) node _T_44 = or(_T_43, io.update_mask[3]) when _T_44 : node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_45 : wire _WIRE_4 : UInt<3>[4] connect _WIRE_4[0], update_wdata[0].ctr connect _WIRE_4[1], update_wdata[1].ctr connect _WIRE_4[2], update_wdata[2].ctr connect _WIRE_4[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_4 else : wire _WIRE_5 : UInt<3>[4] connect _WIRE_5[0], update_wdata[0].ctr connect _WIRE_5[1], update_wdata[1].ctr connect _WIRE_5[2], update_wdata[2].ctr connect _WIRE_5[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_5 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
module TageTable_5( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [12:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [12:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [51:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5 = io_f1_req_ghist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6 = io_f1_req_ghist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7 = io_f1_req_ghist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8 = io_f1_req_ghist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_3 = _idx_history_T_2 ^ idx_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_6 = _idx_history_T_5 ^ idx_history_hist_chunks_7; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_7 = _idx_history_T_6 ^ idx_history_hist_chunks_8; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history = {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ idx_history_hist_chunks_9}; // @[tage.scala:53:11, :55:25] wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35] wire [36:0] _idx_T = {_tag_T, io_f1_req_pc_0[9:3] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4 = io_f1_req_ghist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5 = io_f1_req_ghist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6 = io_f1_req_ghist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_2 = _tag_history_T_1 ^ tag_history_hist_chunks_3; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_4; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_4 = _tag_history_T_3 ^ tag_history_hist_chunks_5; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_5 = _tag_history_T_4 ^ tag_history_hist_chunks_6; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history = {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ tag_history_hist_chunks_7}; // @[tage.scala:53:11, :55:25] wire [29:0] _tag_T_1 = {_tag_T[29:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}] wire [12:0] _s2_req_rtage_WIRE_2 = _table_R0_data[12:0]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_4 = _table_R0_data[25:13]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_6 = _table_R0_data[38:26]; // @[tage.scala:91:27, :97:87] wire [12:0] _s2_req_rtage_WIRE_8 = _table_R0_data[51:39]; // @[tage.scala:91:27, :97:87] reg [8:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [8:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [8:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[11:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[12]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_4_1 = io_update_hist_0[34:28]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_5_1 = io_update_hist_0[41:35]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_6_1 = io_update_hist_0[48:42]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_7_1 = io_update_hist_0[55:49]; // @[tage.scala:24:7, :53:11] wire [6:0] idx_history_hist_chunks_8_1 = io_update_hist_0[62:56]; // @[tage.scala:24:7, :53:11] wire idx_history_hist_chunks_9_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire tag_history_hist_chunks_7_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11] wire [6:0] _idx_history_T_8 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_9 = _idx_history_T_8 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_10 = _idx_history_T_9 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_11 = _idx_history_T_10 ^ idx_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_12 = _idx_history_T_11 ^ idx_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_13 = _idx_history_T_12 ^ idx_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_14 = _idx_history_T_13 ^ idx_history_hist_chunks_7_1; // @[tage.scala:53:11, :55:25] wire [6:0] _idx_history_T_15 = _idx_history_T_14 ^ idx_history_hist_chunks_8_1; // @[tage.scala:53:11, :55:25] wire [6:0] idx_history_1 = {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ idx_history_hist_chunks_9_1}; // @[tage.scala:53:11, :55:25] wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35] wire [36:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[9:3] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_3_1 = io_update_hist_0[35:27]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_4_1 = io_update_hist_0[44:36]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_5_1 = io_update_hist_0[53:45]; // @[tage.scala:24:7, :53:11] wire [8:0] tag_history_hist_chunks_6_1 = io_update_hist_0[62:54]; // @[tage.scala:24:7, :53:11] wire [8:0] _tag_history_T_6 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_7 = _tag_history_T_6 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_8 = _tag_history_T_7 ^ tag_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_9 = _tag_history_T_8 ^ tag_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_10 = _tag_history_T_9 ^ tag_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25] wire [8:0] _tag_history_T_11 = _tag_history_T_10 ^ tag_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25] wire [8:0] tag_history_1 = {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ tag_history_hist_chunks_7_1}; // @[tage.scala:53:11, :55:25] wire [29:0] _tag_T_3 = {_tag_T_2[29:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}] wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [9:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [9:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 13'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 13'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 13'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 13'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [8:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [8:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_4 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_4 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_4 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_51 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_EntryData_51( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_7ClockSinkDomain : output auto : { routers_debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_7 connect routers.clock, childClock connect routers.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0 connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1 connect routers.auto.ingress_nodes_in_2, auto.routers_ingress_nodes_in_2 connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready connect auto.routers_debug_out, routers.auto.debug_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset
module TLNoC_router_7ClockSinkDomain( // @[ClockDomain.scala:14:9] output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_routers_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); Router_7 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready), .auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid), .auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head), .auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail), .auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload), .auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready), .auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid), .auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head), .auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail), .auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload), .auto_ingress_nodes_in_2_flit_ready (auto_routers_ingress_nodes_in_2_flit_ready), .auto_ingress_nodes_in_2_flit_valid (auto_routers_ingress_nodes_in_2_flit_valid), .auto_ingress_nodes_in_2_flit_bits_head (auto_routers_ingress_nodes_in_2_flit_bits_head), .auto_ingress_nodes_in_2_flit_bits_payload (auto_routers_ingress_nodes_in_2_flit_bits_payload), .auto_ingress_nodes_in_2_flit_bits_egress_id (auto_routers_ingress_nodes_in_2_flit_bits_egress_id), .auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready), .auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid), .auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head), .auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail), .auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload), .auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id), .auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready), .auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid), .auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head), .auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail), .auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload), .auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id), .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2
module NoCMonitor_52( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_29 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 3) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_43 connect _source_ok_WIRE[9], _source_ok_T_44 connect _source_ok_WIRE[10], _source_ok_T_45 node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<2>(0h3)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_77 = shr(io.in.a.bits.source, 3) node _T_78 = eq(_T_77, UInt<2>(0h2)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<3>(0h7)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_90 = shr(io.in.a.bits.source, 3) node _T_91 = eq(_T_90, UInt<4>(0h8)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = or(_T_104, _T_109) node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_112 = eq(_T_111, UInt<1>(0h0)) node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_114 = cvt(_T_113) node _T_115 = and(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = asSInt(_T_115) node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0))) node _T_118 = or(_T_112, _T_117) node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _T_127 = and(_T_11, _T_24) node _T_128 = and(_T_127, _T_37) node _T_129 = and(_T_128, _T_50) node _T_130 = and(_T_129, _T_63) node _T_131 = and(_T_130, _T_76) node _T_132 = and(_T_131, _T_89) node _T_133 = and(_T_132, _T_102) node _T_134 = and(_T_133, _T_110) node _T_135 = and(_T_134, _T_118) node _T_136 = and(_T_135, _T_126) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_136, UInt<1>(0h1), "") : assert_1 node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_140 : node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_145 = shr(io.in.a.bits.source, 2) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = leq(UInt<1>(0h0), uncommonBits_7) node _T_148 = and(_T_146, _T_147) node _T_149 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_150 = and(_T_148, _T_149) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_151 = shr(io.in.a.bits.source, 2) node _T_152 = eq(_T_151, UInt<1>(0h1)) node _T_153 = leq(UInt<1>(0h0), uncommonBits_8) node _T_154 = and(_T_152, _T_153) node _T_155 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_156 = and(_T_154, _T_155) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_157 = shr(io.in.a.bits.source, 2) node _T_158 = eq(_T_157, UInt<2>(0h2)) node _T_159 = leq(UInt<1>(0h0), uncommonBits_9) node _T_160 = and(_T_158, _T_159) node _T_161 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_162 = and(_T_160, _T_161) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_163 = shr(io.in.a.bits.source, 2) node _T_164 = eq(_T_163, UInt<2>(0h3)) node _T_165 = leq(UInt<1>(0h0), uncommonBits_10) node _T_166 = and(_T_164, _T_165) node _T_167 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_169 = shr(io.in.a.bits.source, 3) node _T_170 = eq(_T_169, UInt<2>(0h3)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_11) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_11, UInt<3>(0h7)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_175 = shr(io.in.a.bits.source, 3) node _T_176 = eq(_T_175, UInt<2>(0h2)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_12) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_181 = shr(io.in.a.bits.source, 3) node _T_182 = eq(_T_181, UInt<4>(0h8)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_190 = or(_T_144, _T_150) node _T_191 = or(_T_190, _T_156) node _T_192 = or(_T_191, _T_162) node _T_193 = or(_T_192, _T_168) node _T_194 = or(_T_193, _T_174) node _T_195 = or(_T_194, _T_180) node _T_196 = or(_T_195, _T_186) node _T_197 = or(_T_196, _T_187) node _T_198 = or(_T_197, _T_188) node _T_199 = or(_T_198, _T_189) node _T_200 = and(_T_143, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = and(_T_202, _T_207) node _T_209 = or(UInt<1>(0h0), _T_208) node _T_210 = and(_T_201, _T_209) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_210, UInt<1>(0h1), "") : assert_2 node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<1>(0h0)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_14) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<1>(0h1)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_15) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_227 = shr(io.in.a.bits.source, 2) node _T_228 = eq(_T_227, UInt<2>(0h2)) node _T_229 = leq(UInt<1>(0h0), uncommonBits_16) node _T_230 = and(_T_228, _T_229) node _T_231 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<2>(0h3)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_239 = shr(io.in.a.bits.source, 3) node _T_240 = eq(_T_239, UInt<2>(0h3)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_18) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_245 = shr(io.in.a.bits.source, 3) node _T_246 = eq(_T_245, UInt<2>(0h2)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_19) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0) node _T_251 = shr(io.in.a.bits.source, 3) node _T_252 = eq(_T_251, UInt<4>(0h8)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_20) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_20, UInt<3>(0h4)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_258 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_259 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_214 connect _WIRE[1], _T_220 connect _WIRE[2], _T_226 connect _WIRE[3], _T_232 connect _WIRE[4], _T_238 connect _WIRE[5], _T_244 connect _WIRE[6], _T_250 connect _WIRE[7], _T_256 connect _WIRE[8], _T_257 connect _WIRE[9], _T_258 connect _WIRE[10], _T_259 node _T_260 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_261 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_262 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_265 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_267 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_268 = mux(_WIRE[7], _T_260, UInt<1>(0h0)) node _T_269 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_271 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = or(_T_261, _T_262) node _T_273 = or(_T_272, _T_263) node _T_274 = or(_T_273, _T_264) node _T_275 = or(_T_274, _T_265) node _T_276 = or(_T_275, _T_266) node _T_277 = or(_T_276, _T_267) node _T_278 = or(_T_277, _T_268) node _T_279 = or(_T_278, _T_269) node _T_280 = or(_T_279, _T_270) node _T_281 = or(_T_280, _T_271) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_281 node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<27>(0h4000000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_WIRE_1, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_293, UInt<1>(0h1), "") : assert_3 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(source_ok, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_300, UInt<1>(0h1), "") : assert_5 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(is_aligned, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_307, UInt<1>(0h1), "") : assert_7 node _T_311 = not(io.in.a.bits.mask) node _T_312 = eq(_T_311, UInt<1>(0h0)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_312, UInt<1>(0h1), "") : assert_8 node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_316, UInt<1>(0h1), "") : assert_9 node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_320 : node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_323 = and(_T_321, _T_322) node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_21) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<1>(0h1)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_22) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h2)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_23) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<2>(0h3)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_24) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_349 = shr(io.in.a.bits.source, 3) node _T_350 = eq(_T_349, UInt<2>(0h3)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_25) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0) node _T_355 = shr(io.in.a.bits.source, 3) node _T_356 = eq(_T_355, UInt<2>(0h2)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_26) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_26, UInt<3>(0h7)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0) node _T_361 = shr(io.in.a.bits.source, 3) node _T_362 = eq(_T_361, UInt<4>(0h8)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_27) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_27, UInt<3>(0h4)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_368 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_369 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_370 = or(_T_324, _T_330) node _T_371 = or(_T_370, _T_336) node _T_372 = or(_T_371, _T_342) node _T_373 = or(_T_372, _T_348) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_360) node _T_376 = or(_T_375, _T_366) node _T_377 = or(_T_376, _T_367) node _T_378 = or(_T_377, _T_368) node _T_379 = or(_T_378, _T_369) node _T_380 = and(_T_323, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<27>(0h4000000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = and(_T_382, _T_387) node _T_389 = or(UInt<1>(0h0), _T_388) node _T_390 = and(_T_381, _T_389) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_390, UInt<1>(0h1), "") : assert_10 node _T_394 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_28) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_29) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_30) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_31) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0) node _T_419 = shr(io.in.a.bits.source, 3) node _T_420 = eq(_T_419, UInt<2>(0h3)) node _T_421 = leq(UInt<1>(0h0), uncommonBits_32) node _T_422 = and(_T_420, _T_421) node _T_423 = leq(uncommonBits_32, UInt<3>(0h7)) node _T_424 = and(_T_422, _T_423) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0) node _T_425 = shr(io.in.a.bits.source, 3) node _T_426 = eq(_T_425, UInt<2>(0h2)) node _T_427 = leq(UInt<1>(0h0), uncommonBits_33) node _T_428 = and(_T_426, _T_427) node _T_429 = leq(uncommonBits_33, UInt<3>(0h7)) node _T_430 = and(_T_428, _T_429) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_431 = shr(io.in.a.bits.source, 3) node _T_432 = eq(_T_431, UInt<4>(0h8)) node _T_433 = leq(UInt<1>(0h0), uncommonBits_34) node _T_434 = and(_T_432, _T_433) node _T_435 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_436 = and(_T_434, _T_435) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_439 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_394 connect _WIRE_2[1], _T_400 connect _WIRE_2[2], _T_406 connect _WIRE_2[3], _T_412 connect _WIRE_2[4], _T_418 connect _WIRE_2[5], _T_424 connect _WIRE_2[6], _T_430 connect _WIRE_2[7], _T_436 connect _WIRE_2[8], _T_437 connect _WIRE_2[9], _T_438 connect _WIRE_2[10], _T_439 node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_441 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_442 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_443 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_444 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_445 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_446 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_447 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = mux(_WIRE_2[7], _T_440, UInt<1>(0h0)) node _T_449 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_450 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_452 = or(_T_441, _T_442) node _T_453 = or(_T_452, _T_443) node _T_454 = or(_T_453, _T_444) node _T_455 = or(_T_454, _T_445) node _T_456 = or(_T_455, _T_446) node _T_457 = or(_T_456, _T_447) node _T_458 = or(_T_457, _T_448) node _T_459 = or(_T_458, _T_449) node _T_460 = or(_T_459, _T_450) node _T_461 = or(_T_460, _T_451) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_461 node _T_462 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_463 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_464 = and(_T_462, _T_463) node _T_465 = or(UInt<1>(0h0), _T_464) node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = and(_T_465, _T_470) node _T_472 = or(UInt<1>(0h0), _T_471) node _T_473 = and(_WIRE_3, _T_472) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_473, UInt<1>(0h1), "") : assert_11 node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(source_ok, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_480 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_480, UInt<1>(0h1), "") : assert_13 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_487 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_487, UInt<1>(0h1), "") : assert_15 node _T_491 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_491, UInt<1>(0h1), "") : assert_16 node _T_495 = not(io.in.a.bits.mask) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_496, UInt<1>(0h1), "") : assert_17 node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_500, UInt<1>(0h1), "") : assert_18 node _T_504 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_504 : node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_509 = shr(io.in.a.bits.source, 2) node _T_510 = eq(_T_509, UInt<1>(0h0)) node _T_511 = leq(UInt<1>(0h0), uncommonBits_35) node _T_512 = and(_T_510, _T_511) node _T_513 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_36) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<2>(0h2)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_37) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h3)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_38) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_533 = shr(io.in.a.bits.source, 3) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_39) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<2>(0h2)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_40) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_40, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_545 = shr(io.in.a.bits.source, 3) node _T_546 = eq(_T_545, UInt<4>(0h8)) node _T_547 = leq(UInt<1>(0h0), uncommonBits_41) node _T_548 = and(_T_546, _T_547) node _T_549 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_550 = and(_T_548, _T_549) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_553 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_554 = or(_T_508, _T_514) node _T_555 = or(_T_554, _T_520) node _T_556 = or(_T_555, _T_526) node _T_557 = or(_T_556, _T_532) node _T_558 = or(_T_557, _T_538) node _T_559 = or(_T_558, _T_544) node _T_560 = or(_T_559, _T_550) node _T_561 = or(_T_560, _T_551) node _T_562 = or(_T_561, _T_552) node _T_563 = or(_T_562, _T_553) node _T_564 = and(_T_507, _T_563) node _T_565 = or(UInt<1>(0h0), _T_564) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_565, UInt<1>(0h1), "") : assert_19 node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<27>(0h4000000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = and(_T_572, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_579, UInt<1>(0h1), "") : assert_20 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(is_aligned, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_589, UInt<1>(0h1), "") : assert_23 node _T_593 = eq(io.in.a.bits.mask, mask) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_593, UInt<1>(0h1), "") : assert_24 node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_597, UInt<1>(0h1), "") : assert_25 node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_601 : node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_604 = and(_T_602, _T_603) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_606 = shr(io.in.a.bits.source, 2) node _T_607 = eq(_T_606, UInt<1>(0h0)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_42) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_612 = shr(io.in.a.bits.source, 2) node _T_613 = eq(_T_612, UInt<1>(0h1)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_43) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<2>(0h2)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_44) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_624 = shr(io.in.a.bits.source, 2) node _T_625 = eq(_T_624, UInt<2>(0h3)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_45) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_630 = shr(io.in.a.bits.source, 3) node _T_631 = eq(_T_630, UInt<2>(0h3)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_46) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_46, UInt<3>(0h7)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_636 = shr(io.in.a.bits.source, 3) node _T_637 = eq(_T_636, UInt<2>(0h2)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_47) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_47, UInt<3>(0h7)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_642 = shr(io.in.a.bits.source, 3) node _T_643 = eq(_T_642, UInt<4>(0h8)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_48) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_48, UInt<3>(0h4)) node _T_647 = and(_T_645, _T_646) node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_650 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_651 = or(_T_605, _T_611) node _T_652 = or(_T_651, _T_617) node _T_653 = or(_T_652, _T_623) node _T_654 = or(_T_653, _T_629) node _T_655 = or(_T_654, _T_635) node _T_656 = or(_T_655, _T_641) node _T_657 = or(_T_656, _T_647) node _T_658 = or(_T_657, _T_648) node _T_659 = or(_T_658, _T_649) node _T_660 = or(_T_659, _T_650) node _T_661 = and(_T_604, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_664 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<27>(0h4000000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_672) node _T_674 = and(_T_662, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_674, UInt<1>(0h1), "") : assert_26 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(source_ok, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_684, UInt<1>(0h1), "") : assert_29 node _T_688 = eq(io.in.a.bits.mask, mask) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_688, UInt<1>(0h1), "") : assert_30 node _T_692 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_692 : node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<1>(0h0)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_49) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<1>(0h1)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_50) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_709 = shr(io.in.a.bits.source, 2) node _T_710 = eq(_T_709, UInt<2>(0h2)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_51) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_714 = and(_T_712, _T_713) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<2>(0h3)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_52) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_721 = shr(io.in.a.bits.source, 3) node _T_722 = eq(_T_721, UInt<2>(0h3)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_53) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_53, UInt<3>(0h7)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_727 = shr(io.in.a.bits.source, 3) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_54) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0) node _T_733 = shr(io.in.a.bits.source, 3) node _T_734 = eq(_T_733, UInt<4>(0h8)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_55) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_55, UInt<3>(0h4)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_740 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_741 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_742 = or(_T_696, _T_702) node _T_743 = or(_T_742, _T_708) node _T_744 = or(_T_743, _T_714) node _T_745 = or(_T_744, _T_720) node _T_746 = or(_T_745, _T_726) node _T_747 = or(_T_746, _T_732) node _T_748 = or(_T_747, _T_738) node _T_749 = or(_T_748, _T_739) node _T_750 = or(_T_749, _T_740) node _T_751 = or(_T_750, _T_741) node _T_752 = and(_T_695, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_755 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_756 = and(_T_754, _T_755) node _T_757 = or(UInt<1>(0h0), _T_756) node _T_758 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<27>(0h4000000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = and(_T_757, _T_762) node _T_764 = or(UInt<1>(0h0), _T_763) node _T_765 = and(_T_753, _T_764) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_765, UInt<1>(0h1), "") : assert_31 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(source_ok, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_775 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_775, UInt<1>(0h1), "") : assert_34 node _T_779 = not(mask) node _T_780 = and(io.in.a.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_781, UInt<1>(0h1), "") : assert_35 node _T_785 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<1>(0h0)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_56) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_796 = shr(io.in.a.bits.source, 2) node _T_797 = eq(_T_796, UInt<1>(0h1)) node _T_798 = leq(UInt<1>(0h0), uncommonBits_57) node _T_799 = and(_T_797, _T_798) node _T_800 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_802 = shr(io.in.a.bits.source, 2) node _T_803 = eq(_T_802, UInt<2>(0h2)) node _T_804 = leq(UInt<1>(0h0), uncommonBits_58) node _T_805 = and(_T_803, _T_804) node _T_806 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_807 = and(_T_805, _T_806) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_808 = shr(io.in.a.bits.source, 2) node _T_809 = eq(_T_808, UInt<2>(0h3)) node _T_810 = leq(UInt<1>(0h0), uncommonBits_59) node _T_811 = and(_T_809, _T_810) node _T_812 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_813 = and(_T_811, _T_812) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0) node _T_814 = shr(io.in.a.bits.source, 3) node _T_815 = eq(_T_814, UInt<2>(0h3)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_60) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_60, UInt<3>(0h7)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0) node _T_820 = shr(io.in.a.bits.source, 3) node _T_821 = eq(_T_820, UInt<2>(0h2)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_61) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_61, UInt<3>(0h7)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0) node _T_826 = shr(io.in.a.bits.source, 3) node _T_827 = eq(_T_826, UInt<4>(0h8)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_62) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_62, UInt<3>(0h4)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_834 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_835 = or(_T_789, _T_795) node _T_836 = or(_T_835, _T_801) node _T_837 = or(_T_836, _T_807) node _T_838 = or(_T_837, _T_813) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_825) node _T_841 = or(_T_840, _T_831) node _T_842 = or(_T_841, _T_832) node _T_843 = or(_T_842, _T_833) node _T_844 = or(_T_843, _T_834) node _T_845 = and(_T_788, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_848 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<27>(0h4000000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = and(_T_847, _T_852) node _T_854 = or(UInt<1>(0h0), _T_853) node _T_855 = and(_T_846, _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_855, UInt<1>(0h1), "") : assert_36 node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(source_ok, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(is_aligned, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_865 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_865, UInt<1>(0h1), "") : assert_39 node _T_869 = eq(io.in.a.bits.mask, mask) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_869, UInt<1>(0h1), "") : assert_40 node _T_873 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_873 : node _T_874 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_875 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_876 = and(_T_874, _T_875) node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<1>(0h0)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_63) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_884 = shr(io.in.a.bits.source, 2) node _T_885 = eq(_T_884, UInt<1>(0h1)) node _T_886 = leq(UInt<1>(0h0), uncommonBits_64) node _T_887 = and(_T_885, _T_886) node _T_888 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_889 = and(_T_887, _T_888) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_890 = shr(io.in.a.bits.source, 2) node _T_891 = eq(_T_890, UInt<2>(0h2)) node _T_892 = leq(UInt<1>(0h0), uncommonBits_65) node _T_893 = and(_T_891, _T_892) node _T_894 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_895 = and(_T_893, _T_894) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_896 = shr(io.in.a.bits.source, 2) node _T_897 = eq(_T_896, UInt<2>(0h3)) node _T_898 = leq(UInt<1>(0h0), uncommonBits_66) node _T_899 = and(_T_897, _T_898) node _T_900 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_901 = and(_T_899, _T_900) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0) node _T_902 = shr(io.in.a.bits.source, 3) node _T_903 = eq(_T_902, UInt<2>(0h3)) node _T_904 = leq(UInt<1>(0h0), uncommonBits_67) node _T_905 = and(_T_903, _T_904) node _T_906 = leq(uncommonBits_67, UInt<3>(0h7)) node _T_907 = and(_T_905, _T_906) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0) node _T_908 = shr(io.in.a.bits.source, 3) node _T_909 = eq(_T_908, UInt<2>(0h2)) node _T_910 = leq(UInt<1>(0h0), uncommonBits_68) node _T_911 = and(_T_909, _T_910) node _T_912 = leq(uncommonBits_68, UInt<3>(0h7)) node _T_913 = and(_T_911, _T_912) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_914 = shr(io.in.a.bits.source, 3) node _T_915 = eq(_T_914, UInt<4>(0h8)) node _T_916 = leq(UInt<1>(0h0), uncommonBits_69) node _T_917 = and(_T_915, _T_916) node _T_918 = leq(uncommonBits_69, UInt<3>(0h4)) node _T_919 = and(_T_917, _T_918) node _T_920 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_921 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_922 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_923 = or(_T_877, _T_883) node _T_924 = or(_T_923, _T_889) node _T_925 = or(_T_924, _T_895) node _T_926 = or(_T_925, _T_901) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_913) node _T_929 = or(_T_928, _T_919) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_921) node _T_932 = or(_T_931, _T_922) node _T_933 = and(_T_876, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_936 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_937 = cvt(_T_936) node _T_938 = and(_T_937, asSInt(UInt<27>(0h4000000))) node _T_939 = asSInt(_T_938) node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0))) node _T_941 = and(_T_935, _T_940) node _T_942 = or(UInt<1>(0h0), _T_941) node _T_943 = and(_T_934, _T_942) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_943, UInt<1>(0h1), "") : assert_41 node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(source_ok, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(is_aligned, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_953 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_953, UInt<1>(0h1), "") : assert_44 node _T_957 = eq(io.in.a.bits.mask, mask) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_957, UInt<1>(0h1), "") : assert_45 node _T_961 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_961 : node _T_962 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_963 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_964 = and(_T_962, _T_963) node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_70) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_972 = shr(io.in.a.bits.source, 2) node _T_973 = eq(_T_972, UInt<1>(0h1)) node _T_974 = leq(UInt<1>(0h0), uncommonBits_71) node _T_975 = and(_T_973, _T_974) node _T_976 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_977 = and(_T_975, _T_976) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<2>(0h2)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_72) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<2>(0h3)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_73) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_990 = shr(io.in.a.bits.source, 3) node _T_991 = eq(_T_990, UInt<2>(0h3)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_74) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0) node _T_996 = shr(io.in.a.bits.source, 3) node _T_997 = eq(_T_996, UInt<2>(0h2)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_75) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_75, UInt<3>(0h7)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0) node _T_1002 = shr(io.in.a.bits.source, 3) node _T_1003 = eq(_T_1002, UInt<4>(0h8)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_76, UInt<3>(0h4)) node _T_1007 = and(_T_1005, _T_1006) node _T_1008 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1009 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1010 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1011 = or(_T_965, _T_971) node _T_1012 = or(_T_1011, _T_977) node _T_1013 = or(_T_1012, _T_983) node _T_1014 = or(_T_1013, _T_989) node _T_1015 = or(_T_1014, _T_995) node _T_1016 = or(_T_1015, _T_1001) node _T_1017 = or(_T_1016, _T_1007) node _T_1018 = or(_T_1017, _T_1008) node _T_1019 = or(_T_1018, _T_1009) node _T_1020 = or(_T_1019, _T_1010) node _T_1021 = and(_T_964, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1024 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1025 = cvt(_T_1024) node _T_1026 = and(_T_1025, asSInt(UInt<27>(0h4000000))) node _T_1027 = asSInt(_T_1026) node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0))) node _T_1029 = and(_T_1023, _T_1028) node _T_1030 = or(UInt<1>(0h0), _T_1029) node _T_1031 = and(_T_1022, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_46 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(source_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(is_aligned, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1041 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_49 node _T_1045 = eq(io.in.a.bits.mask, mask) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_50 node _T_1049 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1053 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_52 node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 2) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_74 = shr(io.in.d.bits.source, 2) node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3)) node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76) node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_80 = shr(io.in.d.bits.source, 3) node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3)) node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82) node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7)) node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0) node _source_ok_T_86 = shr(io.in.d.bits.source, 3) node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2)) node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88) node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7)) node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0) node _source_ok_T_92 = shr(io.in.d.bits.source, 3) node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8)) node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94) node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4)) node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_55 connect _source_ok_WIRE_1[1], _source_ok_T_61 connect _source_ok_WIRE_1[2], _source_ok_T_67 connect _source_ok_WIRE_1[3], _source_ok_T_73 connect _source_ok_WIRE_1[4], _source_ok_T_79 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_91 connect _source_ok_WIRE_1[7], _source_ok_T_97 connect _source_ok_WIRE_1[8], _source_ok_T_98 connect _source_ok_WIRE_1[9], _source_ok_T_99 connect _source_ok_WIRE_1[10], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1061 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_54 node _T_1065 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_55 node _T_1069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_56 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_57 node _T_1077 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1077 : node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(source_ok_1, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(sink_ok, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1084 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_60 node _T_1088 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_61 node _T_1092 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_62 node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_63 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_64 node _T_1105 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(source_ok_1, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(sink_ok, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1112 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_67 node _T_1116 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_68 node _T_1120 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_69 node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1125 = or(_T_1124, io.in.d.bits.corrupt) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_70 node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1130 = or(UInt<1>(0h0), _T_1129) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_71 node _T_1134 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1134 : node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(source_ok_1, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1138 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_73 node _T_1142 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_74 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h0), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_75 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_77 node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1160 = or(_T_1159, io.in.d.bits.corrupt) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_78 node _T_1164 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1165 = or(UInt<1>(0h0), _T_1164) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_79 node _T_1169 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1169 : node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(source_ok_1, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_81 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_82 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h0), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<28>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1186 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1190 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1194 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1198 = eq(a_first, UInt<1>(0h0)) node _T_1199 = and(io.in.a.valid, _T_1198) when _T_1199 : node _T_1200 = eq(io.in.a.bits.opcode, opcode) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_87 node _T_1204 = eq(io.in.a.bits.param, param) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_88 node _T_1208 = eq(io.in.a.bits.size, size) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_89 node _T_1212 = eq(io.in.a.bits.source, source) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_90 node _T_1216 = eq(io.in.a.bits.address, address) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_91 node _T_1220 = and(io.in.a.ready, io.in.a.valid) node _T_1221 = and(_T_1220, a_first) when _T_1221 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1222 = eq(d_first, UInt<1>(0h0)) node _T_1223 = and(io.in.d.valid, _T_1222) when _T_1223 : node _T_1224 = eq(io.in.d.bits.opcode, opcode_1) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.d.bits.param, param_1) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_93 node _T_1232 = eq(io.in.d.bits.size, size_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_94 node _T_1236 = eq(io.in.d.bits.source, source_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_95 node _T_1240 = eq(io.in.d.bits.sink, sink) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_96 node _T_1244 = eq(io.in.d.bits.denied, denied) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_97 node _T_1248 = and(io.in.d.ready, io.in.d.valid) node _T_1249 = and(_T_1248, d_first) when _T_1249 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1250 = and(io.in.a.valid, a_first_1) node _T_1251 = and(_T_1250, UInt<1>(0h1)) when _T_1251 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1252 = and(io.in.a.ready, io.in.a.valid) node _T_1253 = and(_T_1252, a_first_1) node _T_1254 = and(_T_1253, UInt<1>(0h1)) when _T_1254 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1255 = dshr(inflight, io.in.a.bits.source) node _T_1256 = bits(_T_1255, 0, 0) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(_T_1257, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1257, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1261 = and(io.in.d.valid, d_first_1) node _T_1262 = and(_T_1261, UInt<1>(0h1)) node _T_1263 = eq(d_release_ack, UInt<1>(0h0)) node _T_1264 = and(_T_1262, _T_1263) when _T_1264 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1265 = and(io.in.d.ready, io.in.d.valid) node _T_1266 = and(_T_1265, d_first_1) node _T_1267 = and(_T_1266, UInt<1>(0h1)) node _T_1268 = eq(d_release_ack, UInt<1>(0h0)) node _T_1269 = and(_T_1267, _T_1268) when _T_1269 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1270 = and(io.in.d.valid, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1274 = dshr(inflight, io.in.d.bits.source) node _T_1275 = bits(_T_1274, 0, 0) node _T_1276 = or(_T_1275, same_cycle_resp) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1280 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1281 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1282 = or(_T_1280, _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_100 node _T_1286 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_101 else : node _T_1290 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1291 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1292 = or(_T_1290, _T_1291) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_102 node _T_1296 = eq(io.in.d.bits.size, a_size_lookup) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_103 node _T_1300 = and(io.in.d.valid, d_first_1) node _T_1301 = and(_T_1300, a_first_1) node _T_1302 = and(_T_1301, io.in.a.valid) node _T_1303 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1304 = and(_T_1302, _T_1303) node _T_1305 = eq(d_release_ack, UInt<1>(0h0)) node _T_1306 = and(_T_1304, _T_1305) when _T_1306 : node _T_1307 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1308 = or(_T_1307, io.in.a.ready) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_104 node _T_1312 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1313 = orr(a_set_wo_ready) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) node _T_1315 = or(_T_1312, _T_1314) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_58 node _T_1319 = orr(inflight) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog, plusarg_reader.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1328 = and(io.in.a.ready, io.in.a.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1331 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1332 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1333 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = and(_T_1331, _T_1334) when _T_1335 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1336 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1337 = and(_T_1336, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1338 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1339 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = and(_T_1337, _T_1340) when _T_1341 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1342 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1343 = bits(_T_1342, 0, 0) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1348 = and(io.in.d.valid, d_first_2) node _T_1349 = and(_T_1348, UInt<1>(0h1)) node _T_1350 = and(_T_1349, d_release_ack_1) when _T_1350 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1351 = and(io.in.d.ready, io.in.d.valid) node _T_1352 = and(_T_1351, d_first_2) node _T_1353 = and(_T_1352, UInt<1>(0h1)) node _T_1354 = and(_T_1353, d_release_ack_1) when _T_1354 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1358 = dshr(inflight_1, io.in.d.bits.source) node _T_1359 = bits(_T_1358, 0, 0) node _T_1360 = or(_T_1359, same_cycle_resp_1) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1364 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_109 else : node _T_1368 = eq(io.in.d.bits.size, c_size_lookup) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_110 node _T_1372 = and(io.in.d.valid, d_first_2) node _T_1373 = and(_T_1372, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1374 = and(_T_1373, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1375 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1376 = and(_T_1374, _T_1375) node _T_1377 = and(_T_1376, d_release_ack_1) node _T_1378 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1379 = and(_T_1377, _T_1378) when _T_1379 : node _T_1380 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<28>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1381 = or(_T_1380, _WIRE_27.ready) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_111 node _T_1385 = orr(c_set_wo_ready) when _T_1385 : node _T_1386 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_59 node _T_1390 = orr(inflight_1) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) node _T_1392 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1393 = or(_T_1391, _T_1392) node _T_1394 = lt(watchdog_1, plusarg_reader_1.out) node _T_1395 = or(_T_1393, _T_1394) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<28>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1399 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1400 = and(io.in.d.ready, io.in.d.valid) node _T_1401 = or(_T_1399, _T_1400) when _T_1401 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_29( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1328 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1328; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1328; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1401 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1401; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1401; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1401; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1254 = _T_1328 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1254 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1254 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1254 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1254 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1254 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1300 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1300 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1269 = _T_1401 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1269 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1269 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1269 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1372 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1372 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1354 = _T_1401 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1354 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1354 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1354 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]